[
  {
    "path": ".gitignore",
    "content": "*.S\n*.bin\n\nbin/\nbuild/\ncmake-build-debug/\nvalidation_log/\n__pycache__/\n.idea/\n.vscode/\n\n# Prerequisites\n*.d\n\n# Compiled Object files\n*.slo\n*.lo\n*.o\n*.obj\n\n# Precompiled Headers\n*.gch\n*.pch\n\n# Compiled Dynamic libraries\n*.so\n*.dylib\n*.dll\n\n# Compiled Static libraries\n*.lai\n*.la\n*.a\n*.lib\n\n# Executables\n*.exe\n*.out\n*.app\n"
  },
  {
    "path": "LICENSE",
    "content": "Copyright (c) 2024, VIA Research Group at KAIST\n\nPermission is hereby granted, free of charge, to any person obtaining a\ncopy of this software and associated documentation files (the\n\"Software\"), to deal in the Software without restriction, including\nwithout limitation the rights to use, copy, modify, merge, publish,\ndistribute, sublicense, and/or sell copies of the Software, and to\npermit persons to whom the Software is furnished to do so, subject to\nthe following conditions:\n\nThe above copyright notice and this permission notice shall be included\nin all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\nOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\nMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\nIN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\nCLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\nTORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\nSOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE."
  },
  {
    "path": "README.md",
    "content": "# 📖 Introduction\n<img src=\"./assets/uPIMulator_logo.png\" width=\"1000\">\n\n**Welcome to the uPIMulator Framework Documentation!**\n\nThis documentation serves as your comprehensive guide to the uPIMulator framework, catering to both novice and experienced researchers.\nHere, you'll find the resources necessary to leverage uPIMulator effectively for your research projects.\n\nWe provide in-depth coverage of uPIMulator's features, from foundational concepts to advanced functionalities.\nExplore this documentation to unlock the full potential of uPIMulator and elevate your research endeavors.\n\n# 🤙 Contact Information\n## 📍 Address\n[KAIST](https://www.kaist.ac.kr/en/), School of Electrical Engineering\n\n[Vertically Integrated Architecture Research Group](https://sites.google.com/view/kaist-via/home)\n\nOffice: N1 818 @ [KAIST](https://www.kaist.ac.kr/en/)\n\n## 📧 Email\n- Bongjoon Hyun: [bongjoon.hyun@gmail.com](mailto:bongjoon.hyun@gmail.com)\n- Taehun Kim: [taehun.kim@kaist.ac.kr](mailto:taehun.kim@kaist.ac.kr)\n- Dongjae Lee: [dongjae.lee@kaist.ac.kr](mailto:dongjae.lee@kaist.ac.kr)\n- Minsoo Rhu: [minsoo.rhu@gmail.com](mailto:minsoo.rhu@gmail.com)\n\nPlease feel free to reach out to us if you have any questions or require further assistance.\n\n# 🧑‍💻 Released Versions\n> **uPIMulator: A Flexible and Scalable Simulation Framework for General-Purpose Processing-In-Memory (PIM) Architectures**\n\nuPIMulator is a cycle-level performance simulator tailored for general-purpose Processing-In-Memory (PIM) systems adhering to the UPMEM Instruction Set Architecture (ISA). This tool provides a detailed simulation environment, empowering computer architecture researchers and PIM program developers to investigate and harness the capabilities of PIM technology.\n\nFor comprehensive insights into uPIMulator and its applications, refer to our HPCA-2024 publication:\n\n\"[Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology](https://www.computer.org/csdl/proceedings-article/hpca/2024/931300a263/1VOAAZSdy0w)\", HPCA, 2024\n\nThe currently available versions are:\n1. Python & C++ version\n2. Go version\n3. Go & virtual machine version\n\nAll source code and version history can be accessed in our GitHub repository.\n\n## The Python & C++ Version\nThis is our initial implementation of uPIMulator, used in our HPCA-2024 publication. \nYou'll find it in the `python_cpp` directory.  Refer to the included [README](./python_cpp/README.md) for usage instructions.\n\n## The Go Version\nOur second implementation, optimized for speed and memory efficiency.\nLocated in the `golang` directory, it offers an 8.5x speed increase and 7.5x memory reduction due to multi-threading.\nWe generally recommend this version for most use cases. See the [README](./golang/README.md) for details.\n\n## The Go & Virtual Machine Version\nThis latest version extends the Go version with virtual machine capabilities, eliminating the need for manual data preparation code in many scenarios.\nIt's particularly suitable for complex or dynamic benchmarks where manual data preparation is challenging, though it may not offer the fastest simulation speed.\nRefer to the [README](./golang_vm/README.md) for further guidance.\n\n# 🔍 Summary of Correlation Ratio (R²) and Mean Absolute Error (MAE)\n## Single DPU\n<img src=\"./assets/validation_single_dpu.png\" width=\"400\"/>\n\n## Multiple DPUs\n<img src=\"./assets/validation_multi_dpus.png\" width=\"400\"/>\n\n- Each data point represents a single kernel from the PrIM benchmark suite.\n- Summary of Correlation Ratio (R²) and Mean Absolute Error (MAE) for single- and multi-DPU simulations:\n\n| Scenario | Total Data Points | Correlation (R²) | MAE |\n|---|---|---|---|\n| Single DPU (no inter-DPU communication) | 710 | 98.4% | 12.0% |\n| Multi-DPU (with inter-DPU communication) | 387 | 83.6% | 26.9% |\n\n- These validation results were obtained using the Python & C++ version of uPIMulator.\n\n# List of Supported Instructions\n- uPIMulator currently supports 599 out of the 970 instructions defined in the [UPMEM-PIM ISA](https://sdk.upmem.com/2023.2.0/201_IS.html#instruction-set-architecture).\nDue to limitations in the publicly available ISA documentation, support for the remaining 371 instructions is pending.\nHowever, the currently supported instructions have been sufficient to enable functionally correct simulations of the [PrIM benchmark suite](https://github.com/CMU-SAFARI/prim-benchmarks), producing results consistent with those obtained on real UPMEM-PIM hardware.\n\n- For a detailed list of the currently supported instructions, please refer to [this Google spreadsheet](https://docs.google.com/spreadsheets/d/1xq8t6aRvafmTlGmy4Am8i3QmoOzli1heNxLmCEIlCv4/edit?usp=sharing).\n\n# 🪨 Materials\n- Bongjoon Hyun, Taehun Kim, Dongjae Lee, and Minsoo Rhu, \"[Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology](https://www.computer.org/csdl/proceedings-article/hpca/2024/931300a263/1VOAAZSdy0w)\", *The 30th IEEE International Symposium on High-Performance Computer Architecture ([HPCA-30](https://hpca-conf.org/2024/))*, Edinburgh, Scotland, Mar. 2024\n    - ${\\textsf{\\color{red}Best Paper Award}}$\n    - Acceptance rate: 18% (75 among 410)\n    - [Slide](https://drive.google.com/file/d/1TRgFu6YdBu2gtdtDKIuJI85u8Be8w60M/view?usp=sharing)\n    - [Presentation](https://youtu.be/e-RXYl568fw?si=LbTYbM7p7qod-L8w)\n\n# 🎁 Contributions\nWe welcome and encourage contributions to uPIMulator!\nIf you are interested in contributing or have questions, please feel free to open an issue or submit a pull request.\n\n## List of Maintainers\n- Bongjoon Hyun (bongjoon.hyun@gmail.com)\n- Taehun Kim (taehun.kim@kaist.ac.kr)\n- Dongjae Lee (dongjae.lee@kaist.ac.kr)\n- Minsoo Rhu (minsoo.rhu@gmail.com)\n\n## List of Contributors\n\n# 🙏 Acknowledgement\nWe would like to thank the developers of the [PrIM benchmark suite](https://github.com/CMU-SAFARI/prim-benchmarks), which was instrumental in developing this project.\n\nThis research is funded by the generous support from the following organizations:\n- Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korea government(MSIT) (No. 2022-0-01037, Development of High Performance Processing-in-Memory Technology based on DRAM) and the Korea government(MSIT) (No.RS-2024-00438851, (SW Starlab) High-performance Privacy-preserving Machine Learning System and System Software)\n- National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-2021R1A2C2091753)\n- Samsung Electronics\n\nWe appreciate their commitment to advancing research in this field.\n\n## 📔 Citation\nBongjoon Hyun, Taehun Kim, Dongjae Lee, and Minsoo Rhu, \"[Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology](https://www.computer.org/csdl/proceedings-article/hpca/2024/931300a263/1VOAAZSdy0w)\", IEEE International Symposium on High-Performance Computer Architecture (HPCA), March 2024.\n"
  },
  {
    "path": "golang/README.md",
    "content": "# ⚙️ Usage\n## Currently Supported Mode\nuPIMulator operates in an execution-driven simulation mode, enabling cycle-level performance analysis of PIM-based applications.\n\n## Workflow\nThe typical usage workflow comprises two primary stages:\n\n1. **Binary Generation:** Compile, assemble, and link your application code to generate the required binary files for simulation.\n2. **Cycle-Level Simulation:** Utilize the generated binary files as input to the cycle-level simulator to obtain detailed performance metrics and insights.\n\nWe are actively working on expanding uPIMulator's capabilities and may introduce additional usage modes in future releases. \n\n## Installation & Build\n### Prerequisites\n\n- **Go Compiler and SDK:**  uPIMulator requires Go 1.21.5 or later. \nYou can download and install Go from the [official website](https://go.dev/doc/install).\n\n- **Docker:** Please ensure that Docker is installed on your system.\n\n- **Docker Group Membership:** Your Ubuntu user account needs to be a member of the `docker` group.\n\n- **Tested Environment:** uPIMulator has been thoroughly tested on Ubuntu 18.04 with an Intel CPU.\nWhile we strive for compatibility across different environments, optimal performance and functionality are guaranteed within the tested setup.\n\n### Installation Steps\n\n1. **Install and Build**\n   Navigate to the `uPIMulator` directory and execute the build script:\n\n   ```bash\n   cd /path/to/uPIMulator/golang/uPIMulator/script\n   python build.py\n   ```\n\n## Binary Files Generation & Cycle-Level Simulation\nWe will use the VA (vector addition) benchmark as an example to demonstrate the binary file generation and simulation process.\nPlease note that the initial simulation might take approximately 30 minutes.\n\n### Execution\nTo initiate a simulation, provide the following:\n\n- **Benchmark name:** Specify the desired benchmark (e.g., 'VA').\n- **Number of tasklets:** Define the number of tasklets to be utilized.\n- **Output directory path:** Indicate the absolute path to the directory where you want to store binary files, log files, and other simulation artifacts. \n\nYou can further customize the simulation by utilizing command-line options to adjust various parameters.\n\n### Simulation Output\nDetailed simulation results will be written to the standard output (`stdout`).\n\n> **Important Notes:**\n> - **Create Output Directory:** Prior to running the simulation, create an empty directory at the specified `bin_dirpath`. \n> **Absolute Paths:**  Always provide absolute paths for both `root_dirpath` (the repository's root directory) and `bin_dirpath`.\n\n### Example Command\n\n```bash\ncd /path/to/uPIMulator/golang/uPIMulator\nrm -rf bin\nmkdir bin\n./build/uPIMulator --root_dirpath /path/to/uPIMulator/golang/uPIMulator --bin_dirpath /path/to/uPIMulator/golang/uPIMulator/bin --benchmark VA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets 16 --data_prep_params 1024\n```\n\n# 📄 Reproducing Figures from the Paper\nTo replicate the figures presented in our paper, please adhere to the instructions provided below.\nWe offer replication manuals for Figures 5, 6, 7, 9 and 10 for brevity.\n\n## Configuration of PrIM Benchmarks\n\n- **Single DPU Focus:** For Figures 5, 6, 7, and 9 the parameters `num_channels`, `num_ranks_per_channel`, and `num_dpus_per_rank` must always be set to `1`, as these experiments specifically characterize the behavior of a single DPU.\n- **Data Preparation Parameter:**  When generating the binary files for the PrIM benchmarks, please configure the `data_prep_param` parameter according to the following table:\n\n| Benchmark | `data_prep_param` (Figures 5, 6) | `data_prep_param` (Figure 10) |\n|---|---|---|\n| BS       | 32768 | 131072 |\n| GEMV     | 2048  | 4096   |\n| HST-L    | 131072 | 524288 |\n| HST-S    | 131072 | 524288 |\n| MLP      | 256   | 1024   |\n| RED      | 524288 | 2097152|\n| SCAN-RSS | 262144 | 1048576|\n| SCAN-SSA | 262144 | 1048576|\n| SEL      | 524288 | 2097152|\n| TRNS     | 1024  | 128    |\n| TS       | 2048  | 65536  |\n| UNI      | 524288 | 2097152|\n| VA       | 524288 | 2097152|\n\n### Example Command\n\n```bash\n./uPIMulator --root_dirpath /path/to/uPIMulator/ --bin_dirpath /path/to/uPIMulator/bin --benchmark VA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets 16 --data_prep_params 524288\n``` \n\nPlease ensure you adhere to these configurations to accurately replicate the figures presented in the paper. \n\n## Figure 5: PrIM Compute and Memory Utilization\n<img src=\"../assets/uPIMulator_figure5.png\" width=\"400\"/>\n\nThis figure illustrates the compute utilization (represented by red points) and memory read bandwidth utilization (represented by blue points) of the PrIM benchmarks when executed with varying numbers of threads (tasklets): 1, 4, and 16.\n\n### Metrics Calculation\n\n- **Compute Utilization (IPC):** `num_instructions` / `logic_cycle`\n- **Memory Read Bandwidth Utilization (GB/s):** Refer to the provided Excel sheet for the calculation: [link](../assets/figure5_mem_util_calculator.xlsx)\n\n> **Note:** The values for `num_instructions` and `logic_cycle` required in these calculations can be obtained from the simulation results generated by uPIMulator. \n\n## Figure 6: DPU Runtime Breakdown\n<img src=\"../assets/uPIMulator_fiture6.png\" width=\"400\"/>\n\nThis figure presents a breakdown of DPU runtime, categorizing cycles into:\n\n- **Active Cycles (Black):** Represent cycles when the DPU is actively executing instructions.\n- **Idle Cycles (Red, Yellow, Blue):** Represent cycles when the DPU is stalled due to various reasons.\n\n### Calculation of Cycle Ratios\nTo generate the breakdown depicted in the figure, you can utilize the following formulas:\n\n- **Issuable Ratio:**  `breakdown_run` / `logic_cycle`\n- **Idle (Memory) Ratio:** `breakdown_dma` / `logic_cycle`\n- **Idle (Revolver) Ratio:** `breakdown_etc` / `logic_cycle`\n- **Idle (RF) Ratio:** `backpressure` / `logic_cycle`\n\n> **Note:** The values for the variables used in these formulas (`breakdown_run`, `logic_cycle`, etc.) are available in the simulation results produced by uPIMulator. \n\n## Figure 7: Issuable Tasklets\n<img src=\"../assets/uPIMulator_figure7.png\" width=\"400\"/>\n\nThis figure visualizes the number of tasklets (threads) that are ready for execution (issuable) by the DPU scheduler at each cycle.\n\n### Replication\nTo reproduce this figure, utilize the provided [Excel sheet](../assets/figure7_active_tasklet_breakdown.xlsx).\nThe spreadsheet includes instructions on how to populate it with the relevant simulation output data, and it will automatically generate the corresponding figure.\n\n> **Important Configuration Note**: Please ensure that the number of threads is configured to **16 tasklets** when running the simulations for this figure.\n> You can achieve this by using the following command-line argument: `--num_tasklets 16`.\n\n## Figure 9: Instruction Mix (Single DPU)\n<img src=\"../assets/uPIMulator_figure9.png\" width=\"400\"/>\n\nFigure 9 provides a breakdown of the instruction mix observed during single-DPU execution.\nTo generate this figure, follow the steps outlined below using the `upmem_profiler` tool and the accompanying Excel sheet.\n\n### Procedure\n\n1. **Build the Profiler**\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_profiler/script\n   bash build.sh\n   ```\n\n2. **Extract Instructions**\n   Run the simulation with the `--verbose 1` flag to capture detailed instruction traces.\n\n   ```bash\n   cd /path/to/uPIMulator/golang/uPIMulator/\n   ./build/uPIMulator --root_dirpath /path/to/uPIMulator/golang/uPIMulator --bin_dirpath /path/to/uPIMulator/golang/uPIMulator/bin --benchmark VA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets 16 --data_prep_params 1024 --verbose 1 > trace.txt\n   ```\n\n3. **Run the Profiler**\n   Process the generated trace file using the `upmem_profiler` in `instruction_mix` mode.\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_profiler/\n   ./build/src/upmem_profiler --logpath /path/to/uPIMulator/golang/uPIMulator/trace.txt --mode instruction_mix\n   ```\n\n4. **Generate the Figure**\n   Utilize the profiler's output to populate the provided [Excel sheet](../assets/figure9_instruction_mix.xlsx), which will automatically generate the instruction mix figure.\n\n> **Important Configuration Note:** Similar to Figure 7, the instruction mix analysis in Figure 9 is based on simulations with **16 tasklets**.\n> Ensure that you maintain this configuration (`--num_tasklets 16`) for accurate replication. \n\n## Figure 10: Multi-DPU Latency Breakdown and Speedup\n<img src=\"../assets/uPIMulator_figure10.png\" width=\"400\"/>\n\nFigure 10 presents the latency breakdown and speedup achieved in multi-DPU scenarios.\n\n### Configuring the Number of DPUs\nYou can adjust the number of DPUs by modifying the following parameters in `uPIMulator`:\n\n- `num_channels` \n- `num_ranks_per_channel`\n- `num_dpus_per_rank`\n\n### Generating the Latency Breakdown\nTo obtain the latency breakdown data for plotting, utilize the `upmem_reg_model` tool located in the `tools/upmem_reg_model/` directory.\nThis tool implements a communication model between the host and DPUs based on linear regression.\n\n### Procedure\n\n1. **Prepare Input Excel:**\n   - We provide a sample input Excel file as a template.\n   - Append a new row to this file, specifying the benchmark name, number of DPUs, and the `data_prep_param` used in your simulation.\n   - Fill in the relevant time values (in milliseconds) obtained from your simulation results, such as kernel execution time.\n   You can convert cycle counts to time in milliseconds by dividing the cycle count by the corresponding clock frequency (in MHz) and then multiplying by 1000.\n\n2. **Run the Regression Model:**\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_reg_model/src\n   python main.py --input_excel_filepath /path/to/your/input_excel_file --output_excel_filepath /path/to/your/output_excel_file\n   ```\n\n3. **Access the Output:** \n   - The linear regression results will be available in the specified output Excel file.\n   - Use this data to create the latency breakdown plots as shown in Figure 10.\n\nPlease ensure that you follow these steps carefully to accurately reproduce the multi-DPU latency breakdown and speedup analysis presented in the paper.\n\n# 🌋 Adding Custom Benchmarks\nuPIMulator empowers you to go beyond the provided PrIM benchmark suite by incorporating your own custom benchmarks.\nThis is particularly beneficial if you have access to UPMEM-PIM hardware and want to evaluate your code's performance in a simulated environment.\n\n## Requirements\nTo successfully integrate a new benchmark, ensure it adheres to the following:\n\n1. **UPMEM-C Language:**  The benchmark must be implemented in UPMEM-C, a C-like language tailored for UPMEM-PIM programming.\nConsult the [UPMEM SDK documentation](https://sdk.upmem.com/2021.4.0/) for detailed programming guidelines.\n\n2. **File Structure and Naming:**  \n   - Maintain the same file hierarchy as the PrIM benchmarks, including a `dpu` subdirectory.\n   - Include a `CMakeLists.txt` file within your benchmark's directory hierarchy, mirroring the structure used in the PrIM examples.\n   This is essential as uPIMulator's interpreter and linker automatically detect and compile benchmarks using these `CMakeLists.txt` files.\n\n## Data Preparation\nSince UPMEM PIM-enabled memory directly utilizes physical addresses and uPIMulator currently doesn't support concurrent execution of host and PIM-enabled memory, exercise caution when feeding input/output data. \n\nYou'll need to provide Go source code to handle data preparation for your benchmark.\nThis script should reside in the `uPIMulator/src/assembler` directory and be recognized by `uPIMulator/src/assembler/assembler.go`.\n\n> **Key Considerations for Data Preparation Scripts**\n> - Data transferred from the host to DPUs using `dpu_push_xfer` must be organized within the `input_dpu_mram_heap_pointer_name` variable in your data preparation script.\n> - Similarly, data transferred from DPUs to the host using `dpu_push_xfer` should be placed within the `output_dpu_mram_heap_pointer_name` variable.\n\n## Reference Examples\nWe have included data preparation scripts for the 13 supported PrIM benchmarks.\nThese serve as excellent references for structuring your custom data preparation scripts.\n\nBy following these guidelines, you can seamlessly integrate your benchmarks into uPIMulator for comprehensive performance evaluation and analysis. \n\nIf you have any questions or encounter any difficulties during the integration process, don't hesitate to reach out to us for support. \n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\nPROBLEM_SIZE ?= 2\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DPROBLEM_SIZE=${PROBLEM_SIZE}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -i 262144\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/cpu/Makefile",
    "content": "all:\n\tgcc bs_omp.c -o bs_omp -fopenmp\nrun:\n\t./bs_omp 262144 16777216\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/cpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./bs_omp 2048576 16777216\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/cpu/bs_omp.c",
    "content": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n#include <stdint.h>\n#include \"timer.h\"\n\n#define DTYPE uint64_t\n/*\n* @brief creates a \"test file\" by filling a bufferwith values\n*/\nvoid create_test_file(DTYPE * input, uint64_t  nr_elements, DTYPE * querys, uint64_t n_querys) {\n\n  uint64_t max = UINT64_MAX;\n  uint64_t min = 0;\n\n  srand(time(NULL));\n\n  input[0] = 1;\n  for (uint64_t i = 1; i < nr_elements; i++) {\n        input[i] = input[i - 1] + (rand() % 10) + 1;\n  }\n\n  for(uint64_t i = 0; i < n_querys; i++)\n  {\n\tquerys[i] = input[rand() % (nr_elements - 2)];\n  }\n}\n\n/**\n* @brief compute output in the host\n*/\nuint64_t binarySearch(DTYPE * input, uint64_t input_size, DTYPE* querys, unsigned n_querys)\n{\n\n\tuint64_t found = -1;\n\tuint64_t q, r, l, m;\n\t\n       #pragma omp parallel for private(q,r,l,m)\n     \tfor(q = 0; q < n_querys; q++)\n      \t{\n\t\tl = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) \n\t\t{\n\t    \t\tm = l + (r - l) / 2;\n\n\t    \t\t// Check if x is present at mid\n\t     \t\tif (input[m] == querys[q])\n\t\t\t{\t\n\t\t    \t\tfound += m;\n\t\t\t\tbreak;\n\t\t\t}\n\t    \t\t// If x greater, ignore left half\n\t    \t\tif (input[m] < querys[q])\n\t\t\t    \tl = m + 1;\n\n\t    \t\t// If x is smaller, ignore right half\n\t\t\telse\n\t\t    \t\tr = m - 1;\n\t\t\n\t\t}\n       \t}\n\n      \treturn found;\n}\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    Timer timer;\n    uint64_t input_size = atol(argv[1]);\n    uint64_t n_querys = atol(argv[2]);\n\n    printf(\"Vector size: %lu, num searches: %lu\\n\", input_size, n_querys);\n\t\n    DTYPE * input = malloc((input_size) * sizeof(DTYPE));\n    DTYPE * querys = malloc((n_querys) * sizeof(DTYPE));\n\n    DTYPE result_host = -1;\n\n    // Create an input file with arbitrary data.\n    create_test_file(input, input_size, querys, n_querys);\n\t\n    start(&timer, 0, 0);\n    result_host = binarySearch(input, input_size - 1, querys, n_querys);   \n    stop(&timer, 0);\n\n\n    int status = (result_host);\n    if (status) {\n        printf(\"[OK] Execution time: \");\n\tprint(&timer, 0, 1);\n\tprintf(\"ms.\\n\");\n    } else {\n        printf(\"[ERROR]\\n\");\n    }\n    free(input);\n\n\n    return status ? 0 : 1;\n}\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/cpu/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/Makefile",
    "content": "all:\n\tnvcc -arch=sm_30 -m64 -Xcompiler -fPIC -shared -o cu_binary_search.so binary_search.cu -std=c++11\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    python3 run.py\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/binary_search.cu",
    "content": "#include <cuda.h>\r\n#include <limits.h>\r\n#include \"binary_search.h\"\r\n\r\n#include <chrono>\r\n#include <iostream>\r\n\r\n#define BLOCKDIM 512\r\n#define SEARCH_CHUNK 16\r\n#define BLOCK_CHUNK (BLOCKDIM*SEARCH_CHUNK)\r\n\r\n\r\n__global__ void search_kernel(const long int *arr,\r\n    const long int len, const long int *querys, const long int num_querys, long int *res, bool *flag)\r\n{\r\n    int search;\r\n    if(*flag == false) {\r\n        int tid = threadIdx.x;\r\n        __shared__ int s_arr[BLOCK_CHUNK];\r\n\r\n        /* Since each value is being copied to shared memory, the rest of the\r\n        following uncommented code is unncessary, since a direct comparison\r\n        can be done at the time of copy below. */\r\n        // for(int i = 0; i < BLOCKDIM; ++i) {\r\n        //     int shared_loc = i*SEARCH_CHUNK + tid;\r\n        //     int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n        //     if(arr[global_loc] == search) {\r\n        //         *flag = true;\r\n        //         *res = global_loc;\r\n        //     }\r\n        //     __syncthreads();\r\n        // }\r\n\r\n        /* Copy chunk of array that this entire block of threads will read\r\n        from the slower global memory to the faster shared memory. */\r\n        for(long int i = 0; i < SEARCH_CHUNK; ++i) {\r\n            int shared_loc = tid*SEARCH_CHUNK + i;\r\n            int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n\r\n            /* Make sure to stay within the bounds of the global array,\r\n            else assign a dummy value. */\r\n            if(global_loc < len) {\r\n              s_arr[shared_loc] = arr[global_loc];\r\n            }\r\n            else {\r\n              s_arr[shared_loc] = INT_MAX;\r\n            }\r\n        }\r\n        __syncthreads();\r\n\r\n        for(long int i = 0; i < num_querys; i++)\r\n        {\r\n            search = querys[i];\r\n            /* For each runtime, set the initial search range. */\r\n            int L = 0;\r\n            int R = SEARCH_CHUNK - 1;\r\n            int m = (L + R) / 2;\r\n\r\n            /* Pointer to the part of the shared array for this runtime. */\r\n            int *s_ptr = &s_arr[tid*SEARCH_CHUNK];\r\n\r\n            /* Each runtime will search a chunk of the block array.\r\n            Many blocks will not find a solution so the search must\r\n            be allowed to fail on a per block basis. The loop will\r\n            break (fail) when L >= R. */\r\n            while(L <= R && *flag == false)\r\n            {\r\n                if(s_ptr[m] < search) {\r\n                    L = m + 1;\r\n                }\r\n                else if(s_ptr[m] > search) {\r\n                    R = m - 1;\r\n                }\r\n                else {\r\n                    *flag = true;\r\n                    *res = m += tid*SEARCH_CHUNK + BLOCK_CHUNK * blockIdx.x;\r\n                }\r\n\r\n                m = (L + R) / 2;\r\n            }\r\n        }\r\n    }\r\n}\r\n\r\n\r\n\r\nint binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys)\r\n{\r\n    long int *d_arr, *d_querys, *d_res;\r\n    bool *d_flag;\r\n\r\n    size_t arr_size = len * sizeof(long int);\r\n    size_t querys_size = num_querys * sizeof(long int);\r\n    size_t res_size = sizeof(long int);\r\n    size_t flag_size = sizeof(bool);\r\n\r\n    cudaMalloc(&d_arr, arr_size);\r\n    cudaMalloc(&d_querys, querys_size);\r\n    cudaMalloc(&d_res, res_size);\r\n    cudaMalloc(&d_flag, flag_size);\r\n\r\n    cudaMemcpy(d_arr, arr, arr_size, cudaMemcpyHostToDevice);\r\n    cudaMemcpy(d_querys, querys, querys_size, cudaMemcpyHostToDevice);\r\n    cudaMemset(d_flag, 0, flag_size);\r\n\r\n    /* Set res value to -1, so that if the function returns -1, that\r\n    indicates an algorithm failure. */\r\n    cudaMemset(d_res, -0x1, res_size);\r\n\r\n    int blockSize = BLOCKDIM;\r\n    int gridSize = (len-1)/BLOCK_CHUNK + 1;\r\n\r\n    auto start = std::chrono::high_resolution_clock::now();\r\n    search_kernel<<<gridSize,blockSize>>>(d_arr, len, d_querys, num_querys ,d_res, d_flag);\r\n    cudaDeviceSynchronize();\r\n    auto end = std::chrono::high_resolution_clock::now();\r\n    std::cout << \"Kernel Time: \" <<\r\n        std::chrono::duration_cast<std::chrono::milliseconds>(end-start).count() <<\r\n        \" ms\" << std::endl;\r\n\r\n    long int res;\r\n    cudaMemcpy(&res, d_res, res_size, cudaMemcpyDeviceToHost);\r\n\r\n    return res;\r\n}\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/binary_search.h",
    "content": "#ifndef BINARY_SEARCH_H\r\n#define BINARY_SEARCH_H\r\n\r\n#ifdef _WIN32\r\n  #include <windows.h>\r\n  #define DLL_EXPORT __declspec(dllexport)\r\n#else\r\n  #define DLL_EXPORT\r\n#endif\r\n\r\n\r\nextern \"C\" {\r\n\r\n    int DLL_EXPORT binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys);\r\n\r\n}\r\n\r\n#endif /* BINARY_SEARCH_H */\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/cpu_lib.py",
    "content": "# -*- coding: utf-8 -*-\n\n\ndef binary_search(arr, search):\n\n    L = 0\n    R = len(arr)\n\n    while L <= R:\n\n        if L > R:\n            return -1  # Error code 1\n\n        m = (L + R) / 2\n        if arr[m] < search:\n            L = m + 1\n        elif arr[m] > search:\n            R = m - 1\n        else:\n            return m\n\n    return -2  # Error code 2\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/cu_lib_import.py",
    "content": "# -*- coding: utf-8 -*-\r\n\r\n__all__ = [\r\n    \"binary_search\",\r\n]\r\n\r\n\r\nimport os.path as path\r\nimport platform\r\nfrom ctypes import *\r\n\r\nfrom numpy.ctypeslib import load_library, ndpointer\r\n\r\n## Load the DLL\r\nif platform.system() == \"Linux\":\r\n    cuda_lib = load_library(\"cu_binary_search.so\", path.dirname(path.realpath(__file__)))\r\nelif platform.system() == \"Windows\":\r\n    cuda_lib = load_library(\"cu_binary_search.dll\", path.dirname(path.realpath(__file__)))\r\n\r\n\r\n## Define argtypes for all functions to import\r\nargtype_defs = {\r\n    \"binary_search\": [ndpointer(\"i8\"), c_int, ndpointer(\"i8\"), c_int],\r\n}\r\n\r\n\r\n## Import functions from DLL\r\nfor func, argtypes in argtype_defs.items():\r\n    locals().update({func: cuda_lib[func]})\r\n    locals()[func].argtypes = argtypes\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/baselines/gpu/run.py",
    "content": "# -*- coding: utf-8 -*-\n\nimport time\n\nimport numpy as np\n\n# Local Imports\nfrom cu_lib_import import binary_search as gpu_search\n\n# Set an array label to create\narr_len = 2048576\nnum_querys = 16777216\n\n# Dummy array created\narr = np.arange(0, arr_len, 1).astype(\"i8\")\n\n# Random search querys created\nquerys = np.random.randint(1, arr_len, num_querys)\n\n# GPU search function call\nt0 = time.time()\nres_gpu = gpu_search(arr, len(arr), querys, len(querys))\nprint(\"Total GPU Time: %i ms\" % ((time.time() - t0) * 1e003))\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/dpu/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/BS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(BS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/dpu/task.c",
    "content": "/*\n* Binary Search with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include <perfcounter.h>\n#include \"common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Search\nDTYPE __attribute__ ((noinline)) search(DTYPE *bufferA, DTYPE searching_for) {\n  DTYPE found = -2;\n  if(bufferA[0] <= searching_for)\n  {\n    found = -1;\n    for (uint32_t i = 0; i < BLOCK_SIZE / sizeof(DTYPE); i++){\n      if(bufferA[i] == searching_for)\n      {\n        found = i;\n        break;\n      }\n    }\n  }\n  return found;\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n  // Kernel\n  return kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n  unsigned int tasklet_id = me();\n  #if PRINT\n  printf(\"tasklet_id = %u\\n\", tasklet_id);\n  #endif\n  if(tasklet_id == 0){\n    mem_reset(); // Reset the heap\n  }\n  // Barrier\n  barrier_wait(&my_barrier);\n\n  DTYPE searching_for, found;\n  uint64_t input_size = DPU_INPUT_ARGUMENTS.input_size;\n\n  // Address of the current processing block in MRAM\n  uint32_t start_mram_block_addr_A       = (uint32_t) DPU_MRAM_HEAP_POINTER;\n  uint32_t start_mram_block_addr_aux     = start_mram_block_addr_A;\n  uint32_t end_mram_block_addr_A         = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n  uint32_t current_mram_block_addr_query = end_mram_block_addr_A + tasklet_id * (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS) * sizeof(DTYPE);\n\n  // Initialize a local cache to store the MRAM block\n  DTYPE *cache_A     = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_A = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_B = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n  dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n  // TODO(bongjoon.hyun@gmail.com): original PrIM benchmark uses uint64_t for targets' type\n  for(uint32_t targets = 0; targets < (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS); targets++)\n  {\n    found = -1;\n\n    mram_read((__mram_ptr void const *) current_mram_block_addr_query, &searching_for, 8);\n    current_mram_block_addr_query += 8;\n\n    bool end = false;\n\n    // Initialize input vector boundaries\n    start_mram_block_addr_A    = (uint32_t) DPU_MRAM_HEAP_POINTER;\n    start_mram_block_addr_aux  = start_mram_block_addr_A;\n    end_mram_block_addr_A      = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n\n    uint32_t current_mram_block_addr_A = start_mram_block_addr_A;\n\n    // Bring first and last values to WRAM\n    mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_aux_A, BLOCK_SIZE);\n    mram_read((__mram_ptr void const *) (end_mram_block_addr_A - BLOCK_SIZE * sizeof(DTYPE)),   cache_aux_B, BLOCK_SIZE);\n\n    current_mram_block_addr_A = (start_mram_block_addr_A + end_mram_block_addr_A) / 2;\n    while(!end)\n    {\n      // Load cache with current MRAM block\n      mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n\n      // Search inside block\n      found = search(cache_A, searching_for);\n\n      // If found > -1, we found the searching_for query\n      if(found > -1)\n      {\n        result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        break;\n      }\n\n      // If found == -2, we need to discard right part of the input vector\n      if(found == -2)\n      {\n        end_mram_block_addr_A     = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + start_mram_block_addr_A) / 2;\n      }\n\n      // If found == -1, we need to discard left part of the input vector\n      else if (found == -1)\n      {\n        start_mram_block_addr_A   = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + end_mram_block_addr_A) / 2;\n      }\n\n      // Start boundary check\n      if(current_mram_block_addr_A < (start_mram_block_addr_aux + BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          end = true;\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n\n      // End boundary check\n      if(current_mram_block_addr_A > (end_mram_block_addr_A - BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) end_mram_block_addr_A - BLOCK_SIZE, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n    }\n  }\n  return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/host/app.c",
    "content": "/**\n* app.c\n* BS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"params.h\"\n#include \"timer.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#define DPU_BINARY \"./bin/bs_dpu\"\n\n// Create input arrays\nvoid create_test_file(DTYPE * input, DTYPE * querys, uint64_t  nr_elements, uint64_t nr_querys) {\n\n\tinput[0] = 1;\n\tfor (uint64_t i = 1; i < nr_elements; i++) {\n\t\tinput[i] = input[i - 1] + 1;\n\t}\n\tfor (uint64_t i = 0; i < nr_querys; i++) {\n\t\tquerys[i] = i;\n\t}\n}\n\n// Compute output in the host\nint64_t binarySearch(DTYPE * input, DTYPE * querys, DTYPE input_size, uint64_t num_querys)\n{\n\tuint64_t result = -1;\n\tDTYPE r;\n\tfor(uint64_t q = 0; q < num_querys; q++)\n\t{\n\t\tDTYPE l = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) {\n\t\t\tDTYPE m = l + (r - l) / 2;\n\n\t\t\t// Check if x is present at mid\n\t\t\tif (input[m] == querys[q])\n\t\t\tresult = m;\n\n\t\t\t// If x greater, ignore left half\n\t\t\tif (input[m] < querys[q])\n\t\t\tl = m + 1;\n\n\t\t\t// If x is smaller, ignore right half\n\t\t\telse\n\t\t\tr = m - 1;\n\t\t}\n\t}\n\treturn result;\n}\n\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\tuint64_t input_size = INPUT_SIZE;\n\tuint64_t num_querys = p.num_querys;\n\tDTYPE result_host = -1;\n\tDTYPE result_dpu  = -1;\n\n\t// Create the timer\n\tTimer timer;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n\t#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n\t#endif\n\n\t// Query number adjustement for proper partitioning\n\tif(num_querys % (nr_of_dpus * NR_TASKLETS))\n\tnum_querys = num_querys + (nr_of_dpus * NR_TASKLETS - num_querys % (nr_of_dpus * NR_TASKLETS));\n\n\tassert(num_querys % (nr_of_dpus * NR_TASKLETS) == 0 && \"Input dimension\");    // Allocate input and querys vectors\n\n\tDTYPE * input  = malloc((input_size) * sizeof(DTYPE));\n\tDTYPE * querys = malloc((num_querys) * sizeof(DTYPE));\n\n\t// Create an input file with arbitrary data\n\tcreate_test_file(input, querys, input_size, num_querys);\n\n\t// Compute host solution\n\tstart(&timer, 0, 0);\n\tresult_host = binarySearch(input, querys, input_size - 1, num_querys);\n\tstop(&timer, 0);\n\n\t// Create kernel arguments\n\tuint64_t slice_per_dpu          = num_querys / nr_of_dpus;\n\tdpu_arguments_t input_arguments = {input_size, slice_per_dpu, 0};\n\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\t\t// Perform input transfers\n\t\tuint64_t i = 0;\n\n\t\tif (rep >= p.n_warmup)\n\t\tstart(&timer, 1, rep - p.n_warmup);\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, querys + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size * sizeof(DTYPE), slice_per_dpu * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n\t\t\t#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n\t\t\t#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n\t\t\t#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n\t\t\t#endif\n\t\t}\n\t\t// Print logs if required\n\t\t#if PRINT\n\t\tunsigned int each_dpu = 0;\n\t\tprintf(\"Display DPU Logs\\n\");\n\t\tDPU_FOREACH(dpu_set, dpu)\n\t\t{\n\t\t\tprintf(\"DPU#%d:\\n\", each_dpu);\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t\teach_dpu++;\n\t\t}\n\t\t#endif\n\n\t\t// Retrieve results\n\t\tif (rep >= p.n_warmup)\n\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\tdpu_results_t* results_retrieve[nr_of_dpus];\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tresults_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tfor(unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++)\n\t\t\t{\n\t\t\t\tif(results_retrieve[i][each_tasklet].found > result_dpu)\n\t\t\t\t{\n\t\t\t\t\tresult_dpu = results_retrieve[i][each_tasklet].found;\n\t\t\t\t}\n\t\t\t}\n\t\t\tfree(results_retrieve[i]);\n\t\t}\n\t\tif(rep >= p.n_warmup)\n\t\tstop(&timer, 3);\n\t}\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, p.n_reps);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n\t#if ENERGY\n\tdouble energy;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n\tprintf(\"DPU Energy (J): %f\\t\", energy * num_iterations);\n\t#endif\n\n\tint status = (result_dpu == result_host);\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] results are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] results differ!\\n\");\n\t}\n\n\tfree(input);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n\treturn status ? 0 : 1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifdef TL\n#define TASKLETS_INITIALIZER TASKLETS(TL, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU TL\n#else\n#define TASKLETS_INITIALIZER TASKLETS(16, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU 16\n#endif\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int64_t\n\n// Vector size\n#define INPUT_SIZE 2048576\n\ntypedef struct {\n\tuint64_t input_size;\n\tuint64_t slice_per_dpu;\n\tenum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    DTYPE found;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n  long  num_querys;\n  unsigned   n_warmup;\n  unsigned   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    problem size (default=2 queries)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.num_querys    = PROBLEM_SIZE;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"h:i:w:e:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.num_querys    = atol(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break; \n\tdefault:\n        \tfprintf(stderr, \"\\nUnrecognized option!\\n\");\n        \tusage();\n        \texit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n  #endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/BS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\nproject(benchmark)\n\nadd_subdirectory(BS)\nadd_subdirectory(GEMV)\nadd_subdirectory(HST-L)\nadd_subdirectory(HST-S)\nadd_subdirectory(MLP)\nadd_subdirectory(RED)\nadd_subdirectory(SCAN-RSS)\nadd_subdirectory(SCAN-SSA)\nadd_subdirectory(SEL)\nadd_subdirectory(TRNS)\nadd_subdirectory(TS)\nadd_subdirectory(UNI)\nadd_subdirectory(VA)\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/cpu/Makefile",
    "content": "all:\n\t\tgcc -o gemv -fopenmp gemv_openmp.c \n\nclean:\n\t\trm gemv\n\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/cpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/cpu/gemv_openmp.c",
    "content": "#include <stdlib.h>\n#include <stdio.h>\n#include \"../../support/timer.h\"\n#include \"gemv_utils.h\"\n\nint main(int argc, char *argv[])\n{\n  const size_t rows = 20480;\n  const size_t cols = 8192;\n\n  double **A, *b, *x;\n\n  b = (double*) malloc(sizeof(double)*rows);\n  x = (double*) malloc(sizeof(double)*cols);\n\n  allocate_dense(rows, cols, &A);\n\n  make_hilbert_mat(rows,cols, &A);\n\n#pragma omp parallel\n    {\n#pragma omp for\n    for (size_t i = 0; i < cols; i++) {\n      x[i] = (double) i+1 ;\n    }\n\n#pragma omp for\n    for (size_t i = 0; i < rows; i++) {\n      b[i] = (double) 0.0;\n    }\n    }\n\n  Timer timer;\n  start(&timer, 0, 0);\n\n\n   gemv(A, x, rows, cols, &b);\n   \n   stop(&timer, 0);\n\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n#if 0\n  print_vec(x, rows);\n  print_mat(A, rows, cols);\n  print_vec(b, rows);\n#endif\n\n  printf(\"sum(x) = %f, sum(Ax) = %f\\n\", sum_vec(x,cols), sum_vec(b,rows));\n  return 0;\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i ++ )\n  for (size_t j = 0; j < cols; j ++ ) {\n    (*b)[i] = (*b)[i] + A[i][j]*x[j];\n  }\n}\n\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      (*A)[i][j] = 1.0/( (double) i + (double) j + 1.0);\n    }\n  }\n}\n\ndouble sum_vec(double* vec, size_t rows) {\n  double sum = 0.0;\n#pragma omp parallel for reduction(+:sum)\n  for (int i = 0; i < rows; i++) sum = sum + vec[i];\n  return sum;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/cpu/gemv_utils.h",
    "content": "void allocate_dense(size_t rows,size_t  cols, double*** dense) {\n\n  *dense = malloc(sizeof(double)*rows);\n  **dense = malloc(sizeof(double)*rows*cols);\n\n  for (size_t i=0; i < rows; i++ ) {\n    (*dense)[i] = (*dense)[0] + i*cols;\n  }\n\n}\n\nvoid print_mat(double** A, size_t rows, size_t cols) {\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      printf(\"%f \", A[i][j]);\n    }\n    printf(\"\\n\");\n  }\n}\n\nvoid print_vec(double* b, size_t rows) {\n  for (size_t i = 0; i < rows; i++) {\n    printf(\"%f\\n\", b[i]);\n  }\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b);\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A);\ndouble sum_vec(double* vec, size_t rows);\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc gemv.cu -I/usr/local/cuda/include -lm -o gemv\n\nclean:\n\trm gemv\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/gpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/baselines/gpu/gemv.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n\n#define THREAD 128\n\n#define T int\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\nstruct timeval tv;\ngettimeofday(&tv, NULL);\nreturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n/* for CPU */\nint i, j;\nint *bdim, *c, *ans, *h_ans;\n//double start, stop;\n//double cpu_time, gpu_time;\nint n = 8192;\nint m = 20480;\n\nbdim = (T*)malloc(sizeof(T) *m*n);\nc = (T*)malloc(sizeof(T) *n);\nans = (T*)malloc(sizeof(T) *m);\nh_ans = (T*)malloc(sizeof(T) *m);\n\n/* for GPU */\nT *d_bdim, *d_c, *d_ans;\ncudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\ncudaMalloc((void **)&d_c, sizeof(T)*n);\ncudaMalloc((void **)&d_ans, sizeof(T)*m);\n\nfor(i = 0; i < n; i++)\n{\nc[i] = 1;\nfor(j = 0; j < m; j++)\nbdim[i*m+j] = 1;\n}\n\n//start = gettime();\ncgemv(m, n, bdim, c, ans);\n//stop = gettime();\n//cpu_time=stop - start;\n\n// Event creation\ncudaEvent_t start, stop;\ncudaEventCreate(&start);\ncudaEventCreate(&stop);\nfloat time1 = 0;\n\n\ncudaMemcpy(d_bdim, bdim, sizeof(T)*m*n, cudaMemcpyHostToDevice);\ncudaMemcpy(d_c, c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n// Start timer\ncudaEventRecord( start, 0 );\n//start = gettime();\ngemv<<<m, THREAD>>>(m, n, d_bdim, d_c, d_ans);\n//stop = gettime();\n// End timer\ncudaEventRecord( stop, 0 );\ncudaEventSynchronize( stop );\ncudaEventElapsedTime( &time1, start, stop );\n\n//gpu_time=stop - start;\n\ncudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\n//printf(\"cpu_time : %.6f[sec]\\n\",cpu_time);\n//printf(\"gpu_time : %.6f[sec]\\n\",gpu_time);\n//printf(\"%f x\\n\", cpu_time / gpu_time);\n\n\nfor(i = 0; i < m; i++)\nprintf(\"%d -- %d\\n\", ans[i], h_ans[i]);\n\nprintf(\"Execution time = %f ms\\n\", time1);\n\n\nfree(bdim);\nfree(c);\nfree(ans);\nfree(h_ans);\ncudaFree(d_bdim);\ncudaFree(d_c);\ncudaFree(d_ans);\n\nreturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\nint i;\nint div = n/THREAD;\n__shared__ T tmp[THREAD];\n\ntmp[threadIdx.x] = 0.0;\n\nfor(i = 0; i < div; i++)\n{\ntmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n}\nif(threadIdx.x < m%THREAD)\ntmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n__syncthreads();\n\nfor(i = THREAD / 2; i > 31; i = i / 2)\n{\nif(threadIdx.x < i)\ntmp[threadIdx.x] += tmp[threadIdx.x + i];\n__syncthreads();\n}\n\nif(threadIdx.x < 16)\n{\ntmp[threadIdx.x] += tmp[threadIdx.x + 16];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 8];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 4];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 2];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 1];\n__syncthreads();\n}\n\n\nif(threadIdx.x == 0)\nd_ans[blockIdx.x] = tmp[0];\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\nint i, j;\n\nfor(i = 0; i < m; i++)\nfor(j = 0; j < n; j++)\nd_ans[i] += adim[i*n+j] * b[j];\n\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/GEMV/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(GEMV_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/host/app.c",
    "content": "/**\n * app.c\n * GEMV Host Application Source File\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/gemv_dpu\"\n#endif\n\nstatic T* A;\nstatic T* B;\nstatic T* C;\nstatic T* C_dpu;\n\n// Create input arrays\nstatic void init_data(T* A, T* B, unsigned int m_size, unsigned int n_size) {\n\tsrand(0);\n\n\tfor (unsigned int i = 0; i < m_size * n_size; i++)\n\t{\n\t\tA[i] = (unsigned int) (rand()%50);\n\t}\n\n\tfor (unsigned int i = 0; i < n_size; i++)\n\t{\n\t\tB[i] = (unsigned int) (rand()%50);\n\t}\n}\n\n// Compute output in the host\nstatic void gemv_host(T* C, T* A, T* B, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int i = 0; i < m_size; i++)\n\t{\n\t\tC[i] = 0;\n\t}\n\n\tfor (unsigned int m = 0; m < m_size; m++) {\n\t\tfor (unsigned int n = 0; n < n_size; n++)\n\t\t{\n\t\t\tC[m] += A[m * n_size + n] * B[n];\n\t\t}\n\t}\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned int i;\n\tunsigned int m_size = p.m_size;\n\tunsigned int n_size = p.n_size;\n\n\t// Initialize help data\n\tdpu_info = (struct dpu_info_t *) malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tdpu_arguments_t *input_args = (dpu_arguments_t *) malloc(nr_of_dpus * sizeof(dpu_arguments_t));\n\tuint32_t max_rows_per_dpu = 0;\n\tuint32_t n_size_pad = n_size;\n\tif(n_size % 2 == 1)\n\t{\n\t\tn_size_pad++;\n\t}\n\n\ti = 0;\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tuint32_t rows_per_dpu;\n\t\tuint32_t prev_rows_dpu = 0;\n\t\tuint32_t chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tuint32_t rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows)\n\t\t\trows_per_dpu++;\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows)\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\telse\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\t// Keep max rows for parallel transfers\n\t\tuint32_t rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) // 4-byte elements\n\t\t\trows_per_dpu_pad++;\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu)\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\t// Copy input arguments to DPU\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = malloc(max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(T));\n\tB = malloc(n_size_pad * sizeof(T));\n\tC = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\n\t// Initialize data with arbitrary data\n\tinit_data(A, B, m_size, n_size);\n\n\t// Timer\n\tTimer timer;\n\n\t// Compute output on CPU (performance comparison and verification purposes)\n\tstart(&timer, 0, 0);\n\tgemv_host(C, A, B, m_size, n_size);\n\tstop(&timer, 0);\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\t// Input arguments\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t// Copy input arguments to DPU\n\t\t\tinput_args[i].max_rows = max_rows_per_dpu;\n\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n\t\t// Copy input array and vector\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A + dpu_info[i].prev_rows_dpu * n_size));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n#if PRINT\n\t\t// Display DPU Logs\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t}\n#endif\n\n\t\t// Retrieve results\n\t\tC_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\t}\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, 1);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\n\t// Check output\n\tbool status = true;\n\tunsigned int n,j;\n\ti = 0;\n\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = false;\n#if PRINT\n\t//\t\t\tprintf(\"%d: %d -- %d\\n\", i, C[i], C_dpu[n * max_rows_per_dpu + j]);\n#endif\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n\t}\n\n\t// Deallocation\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n    uint32_t rows_per_dpu;\n    uint32_t rows_per_dpu_pad;\n    uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=8192 elements)\"\n            \"\\n    -n <I>    n_size (default=8192 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 8192;\n    p.n_size        = 8192;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/GEMV/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nNR_HISTO ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_NR_DPUS_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${NR_DPUS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DNR_HISTO=${NR_HISTO} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(NR_HISTO 1)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/HST-L/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DNR_HISTO=${NR_HISTO}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(HST-L_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/dpu/task.c",
    "content": "/*\n* Histogram (HST-L) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n#include <atomic_bit.h>\n#include <mutex.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\nATOMIC_BIT_INIT(barriers_mutexes)[NR_HISTO];\nbarrier_t barriers[NR_HISTO];\n\n// Mutex\nmutex_id_t my_mutex[NR_HISTO];\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, uint32_t histo_id, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = (input[j] * bins) >> DEPTH;\n        mutex_lock(my_mutex[histo_id]);\n        histo[d] += 1;\n        mutex_unlock(my_mutex[histo_id]);\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    unsigned int l_tasklet_id = tasklet_id / NR_HISTO;\n    unsigned int nr_l_tasklet = NR_TASKLETS / NR_HISTO;\n    unsigned int my_histo_id = tasklet_id & (NR_HISTO - 1);\n\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n        // Initialize barriers\n        for (unsigned int each_barrier = 0; each_barrier < NR_HISTO; each_barrier++) {\n            barriers[each_barrier].wait_queue = 0xff;\n            barriers[each_barrier].count = nr_l_tasklet;\n            barriers[each_barrier].initial_count = nr_l_tasklet;\n            barriers[each_barrier].lock = (uint8_t) &ATOMIC_BIT_GET(barriers_mutexes)[each_barrier];\n        }\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    if (tasklet_id < NR_HISTO){ // Allocate DPU histogram\n        uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n        message[tasklet_id] = histo;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    uint32_t *my_histo = message[my_histo_id];\n\n    // Initialize local histogram\n    for(unsigned int i = l_tasklet_id; i < bins; i += nr_l_tasklet){\n        my_histo[i] = 0;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(my_histo, bins, cache_A, my_histo_id, l_size_bytes >> DIV);\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\n        for (unsigned int j = 0; j < NR_HISTO; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n    \t        mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/host/app.c",
    "content": "/**\n* app.c\n* HST-L Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\nstatic unsigned int* histo;\n\n// Create input arrays\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Compute output in the host\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus) {\n    if(!exp){\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    unsigned int input_size; // Size of input image\n    unsigned int dpu_s = p.dpu_s;\n    if(p.exp == 0)\n        input_size = p.input_size * nr_of_dpus; // Size of input image\n    else if(p.exp == 1)\n        input_size = p.input_size; // Size of input image\n\telse\n        input_size = p.input_size * dpu_s; // Size of input image\n\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    histo_host = malloc(p.bins * sizeof(unsigned int));\n    histo = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data\n    read_input(A, p);\n    if(p.exp == 0){\n        for(unsigned int j = 1; j < nr_of_dpus; j++){\n            memcpy(&A[j * input_size_dpu_8bytes], &A[0], input_size_dpu_8bytes * sizeof(T));\n        }\n    }\n    else if(p.exp == 2){\n        for(unsigned int j = 1; j < dpu_s; j++)\n            memcpy(&A[j * p.input_size], &A[0], p.input_size * sizeof(T));\n    }\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\tinput_size\\t%u\\n\", NR_TASKLETS, BL, input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n        memset(histo_host, 0, p.bins * sizeof(unsigned int));\n        memset(histo, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        histogram_host(histo_host, A, p.bins, p.input_size, 1, nr_of_dpus);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        i = 0;\n\t    dpu_arguments_t input_arguments[NR_DPUS];\n\t    for(i=0; i<nr_of_dpus-1; i++) {\n\t        input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].bins=p.bins;\n\t        input_arguments[i].kernel=kernel;\n\t    }\n\t    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].bins=p.bins;\n\t    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, histo + p.bins * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), p.bins * sizeof(unsigned int), DPU_XFER_DEFAULT));\n\t\t\n        // Final histogram merging\n        for(i = 1; i < nr_of_dpus; i++){\n            for(unsigned int j = 0; j < p.bins; j++){\n                histo[j] += histo[j + i * p.bins];\n            }\t\t\t\n        }\t\t\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    if(p.exp == 1) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else if(p.exp == 2) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(dpu_s * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, dpu_s * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else\n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(nr_of_dpus * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, nr_of_dpus * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(histo_host);\n    free(histo);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n\t        NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n\t\t    wait\n            ./bin/host_code -w 2 -e 5 -b ${b} > profile/HSTL_${b}_tl${k}_dpu${i}.txt\n\t\t    wait\n\t\t    make clean\n\t\t    wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-L/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o hist -fopenmp app_baseline.c \n\nclean:\n\trm hist\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/cpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hist -y 1006632960 -t 4\n\nFor more options:\n\n    ./hsti -h\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/cpu/app_baseline.c",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n* The macros DPU_BINARY and NR_TASKLETS are directly\n* used in the static functions, and are not passed as arguments of these functions.\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  n_threads;\n}Params;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus, int t) {\n\n    omp_set_num_threads(t);\n\n    if(!exp){\n        #pragma omp parallel for\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        #pragma omp parallel for\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            #pragma omp atomic update\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Params ---------------------------------------------------------------------\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n    p.exp           = 1;\n    p.file_name     = \"../../input/image_VanHateren.iml\";\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    uint32_t nr_of_dpus;\n    \n    const unsigned int input_size = p.input_size; // Size of input image\n    if(!p.exp)\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n    else\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    if(!p.exp)\n        histo_host = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n        histo_host = malloc(p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    read_input(A, p);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n\tif(!p.exp)\n            memset(histo_host, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n            memset(histo_host, 0, p.bins * sizeof(unsigned int));\n\n    histogram_host(histo_host, A, p.bins, input_size, p.exp, nr_of_dpus, p.n_threads);\n\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L/usr/local/cuda/lib64 -lm\n\nINC=-I/usr/local/cuda/include\n\nDEP=kernel.cpp kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/partitioner.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cpp kernel.cu\nEXE=hsti\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hsti -n 1006632960 -g 512\n\nFor more options:\n\n    ./hsti -h\n\n\nNote:\nThe input folder contains one image from Van Hateren's natural image database \n(http://www.kyb.tuebingen.mpg.de/?id=227). Image pixels are 12-bit depth. Thus, \nfor calculation of the B-bin histogram of an image, the corresponding histogram \nbin is computed as ((pixel * B) >> 12).\nMonochrome images from other databases or synthetic images can also be used. The \nread input function (in main.cpp) might need to be changed accordingly. If image \npixels are b-bit depth and the histogram contains B bins, the histogram bin will \nbe computed as ((pixel * B) >> b).\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include \"support/partitioner.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads--------------------------------------------------------------------------------------\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int n_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *worklist\n#endif\n    ) {\n    std::vector<std::thread> cpu_threads;\n    for(int k = 0; k < n_threads; k++) {\n        cpu_threads.push_back(std::thread([=]() {\n\n#ifdef CUDA_8_0\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads, worklist);\n#else\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads);\n#endif\n\n            unsigned int Hs[bins];\n            // Local histogram initialization\n            for(int i = 0; i < bins; i++) {\n                Hs[i] = 0;\n            }\n\n            for(int i = cpu_first(&p); cpu_more(&p); i = cpu_next(&p)) {\n                for(int j = 0; j < chunk; j++) {\n                    // Read pixel\n                    unsigned int d = ((data[i * chunk + j] * bins) >> 12);\n\n                    // Vote in histogram\n                    Hs[d]++;\n                }\n            }\n\n            // Merge to global histogram\n            for(int i = 0; i < bins; i++) {\n                (&histo[i])->fetch_add(Hs[i]);\n            }\n\n        }));\n    }\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#define _CUDA_COMPILER_\n\n#include \"support/common.h\"\n#include \"support/partitioner.h\"\n\n// CUDA kernel ------------------------------------------------------------------------------------------\n__global__ void Histogram_kernel(int size, int bins, int n_tasks, float alpha, unsigned int *data,\n    unsigned int *histo\n#ifdef CUDA_8_0\n    , int *worklist\n#endif\n    ) {\n\n    extern __shared__ unsigned int l_mem[];\n    unsigned int* l_histo = l_mem;\n#ifdef CUDA_8_0\n    int* l_tmp = (int*)&l_histo[bins];\n#endif\n    \n#ifdef CUDA_8_0\n    Partitioner p = partitioner_create(n_tasks, alpha, worklist, l_tmp);\n#else\n    Partitioner p = partitioner_create(n_tasks, alpha);\n#endif\n    \n    // Block and runtime index\n    const int bx = blockIdx.x;\n    const int tx = threadIdx.x;\n    const int bD = blockDim.x;\n    const int gD = gridDim.x;\n\n    // Sub-histograms initialization\n    for(int pos = tx; pos < bins; pos += bD) {\n        l_histo[pos] = 0;\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Main loop\n    for(int i = gpu_first(&p); gpu_more(&p); i = gpu_next(&p)) {\n    \n        // Global memory read\n        unsigned int d = data[i * bD + tx];\n\n        // Atomic vote in shared memory\n        atomicAdd(&l_histo[((d * bins) >> 12)], 1);\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Merge per-block histograms and write to global memory\n    for(int pos = tx; pos < bins; pos += bD) {\n// Atomic addition in global memory\n#ifdef CUDA_8_0\n        atomicAdd_system(histo + pos, l_histo[pos]);\n#else\n        atomicAdd(histo + pos, l_histo[pos]);\n#endif\n    }\n}\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n    ){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    Histogram_kernel<<<dimGrid, dimBlock, l_mem_size>>>(size, bins, n_tasks, alpha, \n        data, histo\n#ifdef CUDA_8_0\n        , worklist\n#endif\n        );\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda_runtime.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int num_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *wl\n#endif\n    );\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n\t\t);\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int   device;\n    int   n_gpu_threads;\n    int   n_gpu_blocks;\n    int   n_threads;\n    int   n_warmup;\n    int   n_reps;\n    float alpha;\n    int   in_size;\n    int   n_bins;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 256;\n        n_gpu_blocks = 16;\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        alpha         = 0.2;\n        in_size       = 1536 * 1024 * 640;\n        n_bins        = 256;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:a:n:b:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'a': alpha         = atof(optarg); break;\n            case 'n': in_size       = atoi(optarg); break;\n            case 'b': n_bins        = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        if(alpha == 0.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n        } else if(alpha == 1.0) {\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else if(alpha > 0.0 && alpha < 1.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else {\n#ifdef CUDA_8_0\n            assert((n_gpu_threads > 0 && n_gpu_blocks > 0 || n_threads > 0) && \"Invalid # of host + device workers!\");\n#else\n            assert(0 && \"Illegal value for -a\");\n#endif\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./hsti [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=256)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    -a <A>    fraction of input elements to process on host (default=0.2)\"\n#ifdef CUDA_8_0\n                \"\\n              NOTE: Dynamic partitioning used when <A> is not between 0.0 and 1.0\"\n#else\n                \"\\n              NOTE: <A> must be between 0.0 and 1.0\"\n#endif\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n                \"\\n    -n <N>    input size (default=1572864, i.e., 1536x1024)\"\n                \"\\n    -b <B>    # of bins in histogram (default=256)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(unsigned int *input, const Params &p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, \"./input/image_VanHateren.iml\");\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(int y = 0; y < p.in_size; y++) {\n            int fr   = fread(&temp, sizeof(unsigned short), 1, File);\n            input[y] = (unsigned int)ByteSwap16(temp);\n            if(input[y] >= 4096)\n                input[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate buffers\n    timer.start(\"Allocation\");\n    int n_tasks = divceil(p.in_size, p.n_gpu_threads);\n#ifdef CUDA_8_0\n    unsigned int *h_in;\n    cudaStatus = cudaMallocManaged(&h_in, p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo;\n    cudaStatus = cudaMallocManaged(&h_histo, p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    d_in     = h_in;\n    std::atomic_uint *d_histo  = h_histo;\n    std::atomic_int * worklist;\n    cudaStatus = cudaMallocManaged(&worklist, sizeof(std::atomic_int));\n#else\n    unsigned int *    h_in          = (unsigned int *)malloc(p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo       = (std::atomic_uint *)malloc(p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    h_histo_merge = (unsigned int *)malloc(p.n_bins * sizeof(unsigned int));\n    unsigned int *    d_in;\n    cudaStatus = cudaMalloc((void**)&d_in, p.in_size * sizeof(unsigned int));\n    unsigned int *    d_histo;\n    cudaStatus = cudaMalloc((void**)&d_histo, p.n_bins * sizeof(unsigned int));\n    ALLOC_ERR(h_in, h_histo, h_histo_merge);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in, p);\n#ifdef CUDA_8_0\n    for(int i = 0; i < p.n_bins; i++) {\n        h_histo[i].store(0);\n    }\n#else\n    memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n#endif\n    cudaDeviceSynchronize();\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n\n#ifndef CUDA_8_0\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    cudaStatus = cudaMemcpy(d_in, h_in, p.in_size * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaDeviceSynchronize();\n    CUDA_ERR();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n#endif\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n#ifdef CUDA_8_0\n        if(p.alpha < 0.0 || p.alpha > 1.0) { // Dynamic partitioning\n            worklist[0].store(0);\n        }\n        for(int i = 0; i < p.n_bins; i++) {\n            h_histo[i].store(0);\n        }\n#else\n        memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n        cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n        cudaDeviceSynchronize();\n        CUDA_ERR();\n#endif\n\n        if(rep >= p.n_warmup)\n            timer.start(\"Kernel\");\n\n        p.n_gpu_blocks = p.in_size / p.n_gpu_threads;\n\n        // Launch GPU threads\n        // Kernel launch\n        if(p.n_gpu_blocks > 0) {\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n            cudaStatus = call_Histogram_kernel(p.n_gpu_blocks, p.n_gpu_threads, p.in_size, p.n_bins, n_tasks, \n                p.alpha, d_in, (unsigned int*)d_histo, p.n_bins * sizeof(unsigned int)\n#ifdef CUDA_8_0\n                + sizeof(int), (int*)worklist\n#endif\n                );\n            CUDA_ERR();\n        }\n\n        // Launch CPU threads\n        std::thread main_thread(run_cpu_threads, h_histo, h_in, p.in_size, p.n_bins, p.n_threads, p.n_gpu_threads,\n            n_tasks, p.alpha\n#ifdef CUDA_8_0\n            , worklist\n#endif\n            );\n\n        cudaDeviceSynchronize();\n        main_thread.join();\n\n        if(rep >= p.n_warmup)\n            timer.stop(\"Kernel\");\n    }\n    timer.print(\"Kernel\", p.n_reps);\n\n#ifndef CUDA_8_0\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    cudaStatus = cudaMemcpy(h_histo_merge, d_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyDeviceToHost);\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    for(unsigned int i = 0; i < p.n_bins; ++i) {\n        h_histo_merge[i] += (unsigned int)h_histo[i];\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n#endif\n\n    // Verify answer\n#ifdef CUDA_8_0\n    verify((unsigned int *)h_histo, h_in, p.in_size, p.n_bins);\n#else\n    verify((unsigned int *)h_histo_merge, h_in, p.in_size, p.n_bins);\n#endif\n\n    // Free memory\n    timer.start(\"Deallocation\");\n#ifdef CUDA_8_0\n    cudaStatus = cudaFree(h_in);\n    cudaStatus = cudaFree(h_histo);\n    cudaStatus = cudaFree(worklist);\n#else\n    free(h_in);\n    free(h_histo);\n    free(h_histo_merge);\n    cudaStatus = cudaFree(d_in);\n    cudaStatus = cudaFree(d_histo);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Kernel\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/support/partitioner.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#ifndef _PARTITIONER_H_\r\n#define _PARTITIONER_H_\r\n\r\n#ifndef _CUDA_COMPILER_\r\n#include <iostream>\r\n#endif\r\n\r\n#if !defined(_CUDA_COMPILER_) && defined(CUDA_8_0)\r\n#include <atomic>\r\n#endif\r\n\r\n// Partitioner definition -----------------------------------------------------\r\n\r\ntypedef struct Partitioner {\r\n\r\n    int n_tasks;\r\n    int cut;\r\n    int current;\r\n#ifndef _CUDA_COMPILER_\r\n    int thread_id;\r\n    int n_threads;\r\n#endif\r\n\r\n\r\n#ifdef CUDA_8_0\r\n    // CUDA 8.0 support for dynamic partitioning\r\n    int strategy;\r\n#ifdef _CUDA_COMPILER_\r\n    int *worklist;\r\n    int *tmp;\r\n#else\r\n    std::atomic_int *worklist;\r\n#endif\r\n#endif\r\n\r\n} Partitioner;\r\n\r\n// Partitioning strategies\r\n#define STATIC_PARTITIONING 0\r\n#define DYNAMIC_PARTITIONING 1\r\n\r\n// Create a partitioner -------------------------------------------------------\r\n\r\n#ifdef _CUDA_COMPILER_\r\n__device__\r\n#endif\r\ninline Partitioner partitioner_create(int n_tasks, float alpha\r\n#ifndef _CUDA_COMPILER_\r\n    , int thread_id, int n_threads\r\n#endif\r\n#ifdef CUDA_8_0\r\n#ifdef _CUDA_COMPILER_\r\n    , int *worklist\r\n    , int *tmp\r\n#else\r\n    , std::atomic_int *worklist\r\n#endif\r\n#endif\r\n    ) {\r\n    Partitioner p;\r\n    p.n_tasks = n_tasks;\r\n#ifndef _CUDA_COMPILER_\r\n    p.thread_id = thread_id;\r\n    p.n_threads = n_threads;\r\n#endif\r\n    if(alpha >= 0.0 && alpha <= 1.0) {\r\n        p.cut = p.n_tasks * alpha;\r\n#ifdef CUDA_8_0\r\n        p.strategy = STATIC_PARTITIONING;\r\n#endif\r\n    } else {\r\n#ifdef CUDA_8_0\r\n        p.strategy = DYNAMIC_PARTITIONING;\r\n        p.worklist = worklist;\r\n#ifdef _CUDA_COMPILER_\r\n        p.tmp = tmp;\r\n#endif\r\n#endif\r\n    }\r\n    return p;\r\n}\r\n\r\n// Partitioner iterators: first() ---------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->thread_id;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->cut + blockIdx.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: more() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline bool cpu_more(const Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        return (p->current < p->n_tasks);\r\n    } else\r\n#endif\r\n    {\r\n        return (p->current < p->cut);\r\n    }\r\n}\r\n\r\n#else\r\n\r\n__device__ inline bool gpu_more(const Partitioner *p) {\r\n    return (p->current < p->n_tasks);\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: next() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + p->n_threads;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + gridDim.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n#include <string.h>\n\ninline int compare_output(unsigned int *outp, unsigned int *outpCPU, int bins) {\n    for(int i = 0; i < bins; i++) {\n        if(outp[i] != outpCPU[i]) {\n            printf(\"Test failed\\n\");\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential implementation for comparison purposes\ninline void HistogramCPU(unsigned int *histo, unsigned int *data, int size, int bins) {\n    for(int i = 0; i < size; i++) {\n        // Read pixel\n        unsigned int d = ((data[i] * bins) >> 12);\n        // Vote in histogram\n        histo[d]++;\n    }\n}\n\ninline void verify(unsigned int *histo, unsigned int *input, int size, int bins) {\n    unsigned int *gold = (unsigned int *)malloc(bins * sizeof(unsigned int));\n    memset(gold, 0, bins * sizeof(unsigned int));\n    HistogramCPU(gold, input, size, bins);\n    compare_output(histo, gold, bins);\n    free(gold);\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/HST-S/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(HST-S_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/dpu/task.c",
    "content": "/*\n* Histogram (HST-S) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = input[j];\n        histo[(d * bins) >> DEPTH] += 1;\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n\n    // Initialize local histogram\n    for(unsigned int i = 0; i < bins; i++){\n        histo[i] = 0;\n    }\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(histo, bins, cache_A, l_size_bytes >> DIV);\n\n    }\n    message[tasklet_id] = histo;\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\t\t\n        for (unsigned int j = 0; j < NR_TASKLETS; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n                mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/host/app.c",
    "content": "/**\n* app.c\n* HST-S Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\nstatic unsigned int* histo;\n\n// Create input arrays\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Compute output in the host\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus) {\n    if(!exp){\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    unsigned int input_size; // Size of input image\n    unsigned int dpu_s = p.dpu_s;\n    if(p.exp == 0)\n        input_size = p.input_size * nr_of_dpus; // Size of input image\n    else if(p.exp == 1)\n        input_size = p.input_size; // Size of input image\n    else\n        input_size = p.input_size * dpu_s; // Size of input image\n\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    histo_host = malloc(p.bins * sizeof(unsigned int));\n    histo = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data\n    read_input(A, p);\n    if(p.exp == 0){\n        for(unsigned int j = 1; j < nr_of_dpus; j++){\n            memcpy(&A[j * input_size_dpu_8bytes], &A[0], input_size_dpu_8bytes * sizeof(T));\n        }\n    }\n    else if(p.exp == 2){\n        for(unsigned int j = 1; j < dpu_s; j++)\n            memcpy(&A[j * p.input_size], &A[0], p.input_size * sizeof(T));\n    }\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\tinput_size\\t%u\\n\", NR_TASKLETS, BL, input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n        memset(histo_host, 0, p.bins * sizeof(unsigned int));\n        memset(histo, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        histogram_host(histo_host, A, p.bins, p.input_size, 1, nr_of_dpus);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        i = 0;\n\t    dpu_arguments_t input_arguments[NR_DPUS];\n\t    for(i=0; i<nr_of_dpus-1; i++) {\n\t        input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].bins=p.bins;\n\t        input_arguments[i].kernel=kernel;\n\t    }\n\t    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].bins=p.bins;\n\t    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, histo + p.bins * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), p.bins * sizeof(unsigned int), DPU_XFER_DEFAULT));\n\n        // Final histogram merging\n        for(i = 1; i < nr_of_dpus; i++){\n            for(unsigned int j = 0; j < p.bins; j++){\n                histo[j] += histo[j + i * p.bins];\n            }\t\t\t\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(p.exp == 1) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else if(p.exp == 2) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(dpu_s * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, dpu_s * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else\n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(nr_of_dpus * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, nr_of_dpus * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(histo_host);\n    free(histo);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n            NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n            wait\n            ./bin/host_code -w 2 -e 5 -b ${b} -x 1 > profile/HSTS_${b}_tl${k}_dpu${i}.txt\n            wait\n            make clean\n            wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/HST-S/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/cpu/Makefile",
    "content": "all:\n\tgcc mlp_openmp.c -o mlp_openmp -fopenmp -std=c99\nrun:\n\t./mlp_openmp\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/cpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp_openmp\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/cpu/mlp_openmp.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include \"../../support/timer.h\"\n#include \"../../support/common.h\"\n\nT** A;\nT* B;\nT* C;\n\n// Create input arrays\nstatic void init_data(T** A, T* B, unsigned int m_size, unsigned int n_size){\n    for (unsigned int l = 0; l < NUM_LAYERS; l++)\n\t\tfor (unsigned int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l][i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l][i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\tfor (unsigned int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t}\n}\n\n// Compute output in the host\nstatic void mlp_host(T* C, T** A, T* B, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\t#pragma omp parallel for\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl][m * n_size + n] * B[n];\n\t\t\t}\n\t\t\tC[m] = max(0, C[m]);\n\t\t}\n\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\nstatic uint64_t mlp_host_sum(uint64_t n_size, uint64_t m_size) {\n  uint64_t sum = 0;\n  for (uint64_t m = 0; m < n_size; m++){\n    sum += B[m];\n  }\n  return sum;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  char* dpu_type;\n  int   nr_of_ranks;\n  int   input_size_n;\n  int   input_size_m;\n  int   n_warmup;\n  int   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -d <D>    DPU type (default=fsim)\"\n    \"\\n    -r <R>    # of ranks (default=2)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    input size (default=8M elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.dpu_type      = \"fsim\";\n    p.nr_of_ranks   = 1;\n    p.input_size_n  = 1 << 9;\n    p.input_size_m  = 1 << 9;\n    p.n_warmup      = 2;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:r:i:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'd': p.dpu_type        = optarg; break;\n        case 'r': p.nr_of_ranks     = atoi(optarg); break;\n        case 'n': p.input_size_n    = atoi(optarg); break;\n        case 'm': p.input_size_m    = atoi(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(p.nr_of_ranks > 0 && \"Invalid # of ranks!\");\n\n    return p;\n  }\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n    uint64_t n_size = 8192;\n    uint64_t m_size = 20480;\n\n    Timer timer;\n    A = malloc(NUM_LAYERS * sizeof(T*));\n    for(int l = 0; l < NUM_LAYERS; l++)\n        A[l] = malloc(n_size*m_size*sizeof(unsigned int));\n    B = malloc(m_size*sizeof(unsigned int));\n    C = malloc(m_size*sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    init_data(A, B, m_size, n_size);\n\n    start(&timer, 0, 1);\n    mlp_host(C, A, B, n_size, m_size);\n    stop(&timer, 0);\n\n    uint32_t sum = mlp_host_sum(n_size, m_size);\n   \n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    printf(\"SUM = %d \\n\", sum);\n\n    for(int l = 0; l < NUM_LAYERS; l++)\n        free(A[l]);\n    free(A);\n    free(B);\n    free(C);\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc mlp.cu -I/usr/local/cuda/include -lm -o mlp\n\nclean:\n\trm mlp\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/gpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/baselines/gpu/mlp.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n#include \"../../support/common.h\"\n\n#define THREAD 128\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\n\tstruct timeval tv;\n\tgettimeofday(&tv, NULL);\n\treturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n\t/* for CPU */\n\tint i, j;\n\tT **bdim; \n\tT *c, *ans, *h_ans, *h_c;\n\tint n = 8192;\n\tint m = 20480;\n\n\tbdim = (T**) malloc(NUM_LAYERS * sizeof(T*));\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tbdim[l] = (T*)malloc(sizeof(T)*m*n);\n\tc = (T*)malloc(sizeof(T) *n);\n\th_c = (T*)malloc(sizeof(T) *n);\n\tans = (T*)malloc(sizeof(T) *m);\n\th_ans = (T*)malloc(sizeof(T) *m);\n\n\t/* for GPU */\n\tT *d_bdim; \n\tT *d_c, *d_ans;\n\tcudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\n\tcudaMalloc((void **)&d_c, sizeof(T)*n);\n\tcudaMalloc((void **)&d_ans, sizeof(T)*m);\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(i % 50 < 48)\n\t\t{\n\t\t\tc[i] = 0;\n\t\t\th_c[i] = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tc[i] = i % 2;\n\t\t\th_c[i] = i % 2;\n\t\t}\n\t}\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfor(i = 0; i < n; i++)\n\t\t{\n\t\t\tfor(j = 0; j < m; j++){\n\t\t\t\tif(j % 100 < 98)\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = 0;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = (l + i) % 2;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tfor(j = 0; j < m; j++){\n\t\tans[j] = 0;\n\t\th_ans[j] = 0;\n\t}\n\t// Computation on the host for verification\n\tT* vector = c;\n\tT* output = ans;\n\tT* matrix;\n\tint mm = m;\n\tint nn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tmatrix = bdim[l];\n\t\tcgemv(mm, nn, matrix, vector, output);\n\t\tvector = output;\n                h_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\t// Event creation\n\tcudaEvent_t start, stop;\n\tcudaEventCreate(&start);\n\tcudaEventCreate(&stop);\n\tfloat time1 = 0;\n\tfloat time2 = 0;\n\tcudaMemcpy(d_ans, h_ans, sizeof(T)*m, cudaMemcpyHostToDevice);\n\tcudaMemcpy(d_c, h_c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n\tvector = d_c;\n\toutput = d_ans;\n\tmm = m;\n\tnn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tcudaMemcpy(d_bdim, bdim[l], sizeof(T)*m*n, cudaMemcpyHostToDevice);\n\t\tmatrix = d_bdim;\n\t\t// Start timer\n\t\tcudaEventRecord( start, 0 );\n\t\tgemv<<<mm, THREAD>>>(mm, nn, matrix, vector, output);\n\t\t// End timer\n\t\tcudaEventRecord( stop, 0 );\n\t\tcudaEventSynchronize( stop );\n\t\tcudaEventElapsedTime( &time2, start, stop );\n\t\ttime1 += time2;\n\t\tvector = output;\n\t\td_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\tcudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\tcudaMemcpy(h_c, d_c, sizeof(T)*n, cudaMemcpyDeviceToHost);\n\n\tfor(i = 0; i < m; i++)\n\t{\n\t\tif(ans[i] != h_ans[i])\n\t\tprintf(\"ERROR in Ans %d -> %d -- %d\\n\", i, ans[i], h_ans[i]);\n        }\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(c[i] != h_c[i])\n\t\tprintf(\"ERROR in C %d -> %d -- %d\\n\", i, c[i], h_c[i]);\n\t}\n\tprintf(\"Execution time = %f ms\\n\", time1);\n\n\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfree(bdim[l]);\n\n\n\tfree(bdim);\n\tfree(c);\n\tfree(ans);\n\tfree(h_c);\n\tcudaFree(d_bdim);\n\tcudaFree(d_c);\n\tcudaFree(d_ans);\n\tcudaEventDestroy(start);\n\tcudaEventDestroy(stop);\n\n\treturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\n\tint i;\n\tint div = n/THREAD;\n\t__shared__ T tmp[THREAD];\n\n\ttmp[threadIdx.x] = 0.0;\n\n\tfor(i = 0; i < div; i++){\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n\t}\n\tif(threadIdx.x < m%THREAD)\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n\t__syncthreads();\n\n\tfor(i = THREAD / 2; i > 31; i = i / 2)\n\t{\n\t\tif(threadIdx.x < i)\n\t\t\ttmp[threadIdx.x] += tmp[threadIdx.x + i];\n\t\t__syncthreads();\n\t}\n\n\tif(threadIdx.x < 16)\n\t{\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 16];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 8];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 4];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 2];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 1];\n\t\t__syncthreads();\n\t}\n\n\n\tif(threadIdx.x == 0)\n\t\td_ans[blockIdx.x] = max(0, tmp[0]);\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\n\tint i, j;\n\n\tfor(i = 0; i < m; i++){\n\t\tfor(j = 0; j < n; j++)\n\t\t\td_ans[i] += adim[i*n+j] * b[j];\n\t\td_ans[i] = max(0, d_ans[i]);\n\t}\n\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/MLP/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(MLP_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/host/app.c",
    "content": "/**\n * app.c\n * MLP Host Application Source File\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/mlp_dpu\"\n#endif\n\nstatic T** A;\nstatic T* B;\nstatic T* B_host;\nstatic T* B_tmp;\nstatic T* C;\nstatic T* C_dpu;\n\n// Create input arrays\nstatic void init_data(T** A, T* B, T* B_host, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int l = 0; l < NUM_LAYERS; l++)\n\t\tfor (unsigned int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l][i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l][i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\tfor (unsigned int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t\tB_host[i] = B[i];\n\t}\n}\n\n// Compute output in the host\nstatic void mlp_host(T* C, T** A, T* B, unsigned int m_size, unsigned int n_size) {\n\n\tfor (unsigned int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl][m * n_size + n] * B[n];\n\t\t\t}\n\t\t\tC[m] = max(0, C[m]);\n\t\t}\n\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned int i, l;\n\tunsigned int m_size = p.m_size;\n\tunsigned int n_size = p.n_size;\n\n\t// Initialize help data\n\tdpu_info = (struct dpu_info_t *) malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tdpu_arguments_t *input_args = (dpu_arguments_t *) malloc(nr_of_dpus * sizeof(dpu_arguments_t));\n\tuint32_t max_rows_per_dpu = 0;\n\tuint32_t n_size_pad = n_size;\n\tif(n_size % 2 == 1){\n\t\tn_size_pad++;\n\t}\n\n\t// Timer\n\tTimer timer;\n\ti = 0;\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tuint32_t rows_per_dpu;\n\t\tuint32_t prev_rows_dpu = 0;\n\t\tuint32_t chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tuint32_t rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows)\n\t\t\trows_per_dpu++;\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows)\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\telse\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\t// Keep max rows for parallel transfers\n\t\tuint32_t rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) // 4-byte elements\n\t\t\trows_per_dpu_pad++;\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu)\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\t// Copy input arguments to DPU\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = (T**)malloc(NUM_LAYERS * sizeof(T*));\n\tfor(l = 0; l < NUM_LAYERS; l++)\n\t\tA[l] = (T*)malloc( max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(T));\n\n\n\tB = (T*)malloc(n_size * sizeof(T));\n\tB_host = (T*)malloc(n_size * sizeof(T));\n\tC = (T*)malloc(m_size * sizeof(T));\n\tC_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\tB_tmp = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\n\tinit_data(A, B, B_host, m_size, n_size);\n\n\t// Compute output on CPU (performance comparison and verification purposes)\n\tstart(&timer, 0, 0);\n\tmlp_host(C, A, B_host, m_size, n_size);\n\tstop(&timer, 0);\n\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\t// Input arguments\n\t\ti = 0;\n\t\t// Copy input arguments to DPU\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tinput_args[i].max_rows = max_rows_per_dpu;\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n\n\t\t// Copy input array and vector\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A[0] + dpu_info[i].prev_rows_dpu * n_size));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n\n\t\tfor(int lay = 1; lay < NUM_LAYERS; lay++){\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t\tstart(&timer, 4, rep - p.n_warmup);\n\t\t\ti = 0;\n\n\t\t\t// Copy C_dpu\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\t// B = C\n\t\t\tunsigned int n, j;\n\t\t\ti = 0;\n\t\t\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\t\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\t\t\tB_tmp[i] = C_dpu[n * max_rows_per_dpu + j];\n\t\t\t\t\ti++;\n\t\t\t\t}\n\t\t\t}\n\t\t\ti = 0;\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B_tmp));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\t// Copy next matrix of weights\n\t\t\ti = 0;\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A[lay] + dpu_info[i].prev_rows_dpu * n_size));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\tif(rep >= p.n_warmup)\n\t\t\t\tstop(&timer, 4);\n\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t{\n\t\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t\t}\n\n\t\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t{\n\t\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t\t}\n\t\t}\n\n#if PRINT\n\t\t// Display DPU Logs\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t}\n#endif\n\n\t\t// Retrieve results\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\t}\n\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, 1);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"Inter-DPU Time (ms): \");\n\tprint(&timer, 4, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\tprintf(\"\\n\\n\");\n\n\t// Check output\n\tbool status = true;\n\tunsigned int n, j;\n\ti = 0;\n\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = false;\n#if PRINT\n\t\t\t\tprintf(\"%d: %d -- %d\\n\", i, C[i], C_dpu[n * max_rows_per_dpu + j]);\n#endif\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n\t}\n\n\t// Deallocation\n\tfor(i = 0; i < NUM_LAYERS; i++)\n\t\tfree(A[i]);\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n  uint32_t rows_per_dpu;\n  uint32_t rows_per_dpu_pad;\n  uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n#define NUM_LAYERS 3 \n#define max(x, y) (x > y ? x : y)\n#define min(x, y) (x < y ? x : y)\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=2048 elements)\"\n            \"\\n    -n <I>    n_size (default=2048 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 163840;\n    p.n_size        = 4096;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/MLP/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nVERSION ?= SINGLE\nSYNC ?= HAND\nTYPE ?= INT64\nENERGY ?= 0\nPERF ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_VERSION_$(4)_SYNC_$(5)_TYPE_$(6).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${VERSION},${SYNC},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DENERGY=${ENERGY} -DPERF=${PERF}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DPERF=${PERF}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -w 0 -e 1 -i 6553600 -x 1\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/cpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000 -t 4\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 1;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\t\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        thrust::omp::vector<T> d_input(input_size);\n        memcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        count = thrust::reduce(thrust::omp::par, d_input.begin(), d_input.end());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n        h_output = d_input;\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/gpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 160 * 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        count = thrust::reduce(d_input.begin(),d_input.end());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n\tcudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\nSET(VERSION SINGLE)\r\nSET(SYNC HAND)\r\nSET(PERF 0)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/RED/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DPERF=${PERF}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(RED_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/dpu/task.c",
    "content": "/*\n* Reduction with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input, unsigned int l_size){\n    T output = 0;\n    for (unsigned int j = 0; j < l_size; j++){\n        output += input[j];\n    }\n    return output;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n#if PERF\n        perfcounter_config(COUNT_CYCLES, true);\n#endif\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n#if PERF && !PERF_SYNC\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n#if !PERF_SYNC // COMMENT OUT TO COMPARE SYNC PRIMITIVES (Experiment in Appendix)\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\t\t\n        // Reduction in each tasklet\n        l_count += reduction(cache_A, l_size_bytes >> DIV);\n\n    }\n#endif\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n#ifdef TREE // Tree-based reduction\n#ifdef BARRIER\n    // Barrier\n    barrier_wait(&my_barrier);\n#endif\n\n    #pragma unroll\n    for (unsigned int offset = 1; offset < NR_TASKLETS; offset <<= 1){\n\n        if((tasklet_id & (2*offset - 1)) == 0){\n#ifndef BARRIER\n            // Wait\n            handshake_wait_for(tasklet_id + offset);\n#endif\n            message[tasklet_id] += message[tasklet_id + offset];\n        }\n\n#ifdef BARRIER\n        // Barrier\n        barrier_wait(&my_barrier);\n#else\n        else if ((tasklet_id & (offset - 1)) == 0){ // Ensure that wait and notify are in pair\n            // Notify\n            handshake_notify();\n        }\n#endif\n\n    }\n\n#else  // Single-thread reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0)\n        #pragma unroll\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n#endif\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    // Total count in this DPU\n    if(tasklet_id == 0){\n        result->t_count = message[tasklet_id];\n    }\n\n#if PERF && !PERF_SYNC\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/host/app.c",
    "content": "/**\n* app.c\n* RED Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T)(rand());\n    }\n}\n\n// Compute output in the host\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n#if PERF\n    double cc = 0;\n    double cc_min = 0;\n#endif\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        count = 0;\n        // Input arguments\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments[NR_DPUS];\n        for(i=0; i<nr_of_dpus-1; i++) {\n            input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].kernel=kernel;\n        }\n        input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n        input_arguments[nr_of_dpus-1].kernel=kernel;\t\t\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_count = malloc(nr_of_dpus * sizeof(T));\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == 0)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n#if !PERF\n            free(results_retrieve[i]);\n#endif\n            // Sequential reduction\n            count += results[i].t_count;\n#if PRINT\n            printf(\"i=%d -- %lu\\n\", i, count);\n#endif\n        }\n\n#if PERF\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if (results_retrieve[i][each_tasklet].cycles > results[i].cycles)\n                    results[i].cycles = results_retrieve[i][each_tasklet].cycles;\n            }\n            free(results_retrieve[i]);\n        }\n#endif\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n        // Free memory\n        free(results_count);\n    }\n#if PERF\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n#endif\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(count != count_host) status = false;\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor j in BARRIER HAND\n\tdo \t\n\t\tfor k in 1 2 4 8 16\n\t\tdo\n\t\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=TREE SYNC=$j make all\n\t\t\twait\n            ./bin/host_code -w 2 -e 10 -i 2097152 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n            #./bin/host_code -w 2 -e 10 -i 2048 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\n\t\tdone\n\tdone\ndone\n\nfor i in 1 \ndo\n    for k in 1 2 4 8 16\n\tdo\n\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=SINGLE make all\n\t\twait\n        ./bin/host_code -w 2 -e 10 -i 2097152 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n        #./bin/host_code -w 2 -e 10 -i 2048 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n\t\twait\n\t\tmake clean\n\t\twait\n\tdone\ndone\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n    T t_count;\n} dpu_results_t;\n\n#ifndef PERF\n#define PERF 0 // Use perfcounters?\n#endif\n#ifndef PERF_SYNC\n#define PERF_SYNC 0 // Use perfcounters to time sync primitives?\n#endif\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=6553600 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/RED/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200 -t 4\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size =  p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        memcpy(thrust::raw_pointer_cast(&h_output[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        thrust::exclusive_scan(thrust::omp::par, h_output.begin(),h_output.end(),h_output.begin());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            //printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=640 * 3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1258291200;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        thrust::exclusive_scan(d_input.begin(),d_input.end(),d_input.begin());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n        cudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SCAN-RSS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SCAN-RSS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Reduce-scan-scan)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input){\n    T output = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output += input[j];\n    }\n    return output;\n}\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Reduction\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Reduction in each tasklet\n        l_count += reduction(cache_A);\n\n    }\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n    // Single-runtime reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0){\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n        // Total count in this DPU\n        result->t_count = message[0];\n    }\n\n    return 0;\n}\n\n// Scan\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\t\t\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/host/app.c",
    "content": "/**\n* app.c\n* SCAN-RSS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    T accum = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel, 0};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_scan = malloc(nr_of_dpus * sizeof(T));\n        i = 0;\n        accum = 0;\n\t\t\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == 0)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n            free(results_retrieve[i]);\n            // Sequential scan\n            T temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %lu,  %lu, %lu\\n\", i, results_scan[i], accum, temp);\n#endif\n        }\n\n        // Arguments for scan kernel (2nd kernel)\n        kernel = 1;\n        dpu_arguments_t input_arguments_2[NR_DPUS];\n        for(i=0; i<nr_of_dpus; i++) {\n            input_arguments_2[i].size=input_size_dpu * sizeof(T); \n            input_arguments_2[i].kernel=kernel;\n            input_arguments_2[i].t_count=results_scan[i];\n        }\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments_2[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments_2[0]), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 4, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 4);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 5, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 5);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel Reduction \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU (Scan) \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU Kernel Scan \");\n    print(&timer, 4, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 5, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 VERSION=SINGLE make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-RSS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SCAN-SSA/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SCAN-SSA_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Scan-scan-add)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Scan-(handshake)scan\nint main_kernel1() {\n#if 1 // Comment out for appendix experiment\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\n#endif\n    return 0;\n}\n\n// Add\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    T t_count = DPU_INPUT_ARGUMENTS.t_count;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_A, BLOCK_SIZE);\n\n        // Add in each tasklet\n        add_(cache_A, t_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/host/app.c",
    "content": "/**\n* app.c\n* SCAN-SSA Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    T accum = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel, 0};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_scan = malloc(nr_of_dpus * sizeof(T));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == NR_TASKLETS - 1)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n            free(results_retrieve[i]);\n            // Sequential scan\n            T temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %lu,  %lu, %lu\\n\", i, results_scan[i], accum, temp);\n#endif\n        }\n\n        // Arguments for add kernel (2nd kernel)\n        kernel = 1;\n        dpu_arguments_t input_arguments_2[NR_DPUS];\n        for(i=0; i<nr_of_dpus; i++) {\n            input_arguments_2[i].size=input_size_dpu * sizeof(T); \n            input_arguments_2[i].kernel=kernel;\n            input_arguments_2[i].t_count=results_scan[i];\n        }\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments_2[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments_2[0]), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 4, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 4);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 5, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 5);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel Scan \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU (Scan) \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU Kernel Add \");\n    print(&timer, 4, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 5, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SCAN-SSA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o sel -fopenmp app_baseline.c \n\nclean:\n\trm sel\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/cpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./sel -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic uint64_t *A;\nstatic uint64_t *B;\nstatic uint64_t *C;\nstatic uint64_t *C2;\nstatic int pos;\n\nbool pred(const uint64_t x){\n  return (x % 2) == 0;\n}\n\n\nvoid  *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    B = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    C = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        A[i] = i+1;\n        B[i] = 0;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic int select_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(!pred(A[my])) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n    return pos;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    char* dpu_type;\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -d <D>    DPU type (default=fsim)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=2)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=5)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = select_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n    \n    free(A);\n    free(B);\n    free(C);\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc select.cu -I/usr/local/cuda/include -lm -o select -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm select\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/gpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./select 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays (Note: Sample predicate is only for INT)\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__global__ void select_remove_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(!pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n\n__global__ void select_copy_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/baselines/gpu/select.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n\n// Sample predicate for partition (only for INT)\nstruct is_even{\n  __host__ __device__\n  bool operator()(const T &x){\n    return (x % 2) == 0;\n  }\n};\n\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_copy_if(T* output, T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(pred(input[i])){\n\t  output[pos] = input[i];\n      pos++;\n    }\n  }\n}\nvoid cpu_remove_if(T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(!pred(input[i])){\n\t  input[pos] = input[i];\n      pos++;\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Select on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n  float time3 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n  T *h_D = (T*)malloc(size);\n\n  // Allocate the device input vector A and output vector B\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n  T *d_B = NULL;\n  cudaMalloc((void **)&d_B, size);\n\n#define WARMUP 2\n#define REP 10\n  unsigned int flagM1 = 0;\n  unsigned int flagM2 = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++)\n        h_A[i] = i % 2 != 0 ? i:i+1;\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x] % 2 != 0){\n            h_A[x] = x * 2;\n            m--;\n        }\n    }\n\n#if PRINT\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    const int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Copy_if)\n    select_copy_if<<<num_wg, ldim>>>(d_B, d_A, numElements, d_flags, is_even());\n\n    cudaMemcpy(&flagM1, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // Stop timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM1) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Copy_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Atomic flags\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Remove_if)\n    select_remove_if<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags, is_even()); \n\n    cudaMemcpy(&flagM2, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time3 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time3 / REP;\n      double bw = (double)((numElements + flagM2) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Remove_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);\n  cudaMemcpy(h_C, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_copy_if(h_D, h_A, numElements, is_even());\n  cpu_remove_if(h_A, numElements, is_even());\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_D+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM1 - 1; ++i){\n      if (h_B[i] != h_D[i]){\n          fprintf(stderr, \"Copy_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  for (int i = 0; i < flagM2 - 1; ++i){\n      if (h_C[i] != h_A[i]){\n          fprintf(stderr, \"Remove_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaFree(d_B);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n  free(h_D);\n\n  return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SEL/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SEL_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/dpu/task.c",
    "content": "/*\n* Select with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nuint32_t message_partial_count;\n\n// SEL in each tasklet\nunsigned int __attribute__ ((noinline)) select(T *output, T *input){\n    unsigned int pos = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        if(!pred(input[j])) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nunsigned int __attribute__ ((noinline)) handshake_sync(unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = 0;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // SELECT in each tasklet\n        uint32_t l_count = select(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint32_t p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + p_count) * sizeof(T)), l_count * sizeof(T));\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/host/app.c",
    "content": "/**\n* app.c\n* SEL Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand());\n        A[i] = i + 1;\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) { // Complete with removable elements\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic unsigned int select_host(T* C, T* A, unsigned int nr_elements) {\n    unsigned int pos = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        if(!pred(A[i])) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    uint32_t accum = 0;\n    uint32_t total_count = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        total_count = select_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        uint32_t* results_scan = malloc(nr_of_dpus * sizeof(uint32_t));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n\t\t    start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                // Count of this DPU\n                if(each_tasklet == NR_TASKLETS - 1){\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n                }\n            }\n            // Sequential scan\n            uint32_t temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %u,  %u, %u\\n\", i, results_scan[i], accum, temp);\n#endif\n            free(results_retrieve[i]);\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 4, rep - p.n_warmup);\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferC + results_scan[i], results[i].t_count * sizeof(T)));\n\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 4);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(accum != total_count) status = false;\n    for (i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Sample predicate\nbool pred(const T x){\n  return (x % 2) == 0;\n}\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/SEL/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=g++\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -lm -pthread\n\nDEP=kernel.cpp kernel.h main.cpp support/common.h support/setup.h support/timer.h \nSRC=main.cpp kernel.cpp\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 \n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   data[b];\n            T   backup[b];\n            int done;\n            int m = A * B - 1;\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < m) {\n                int next_in_cycle = (gid * A) - m * (gid / B);\n                if(next_in_cycle == gid) {\n                    // Dynamic fetch\n                    gid = (head)->fetch_add(1);\n                    continue;\n                }\n                for(int i = 0; i < b; i++) {\n                    data[i] = input[gid * b + i];\n                }\n                //make sure the read is not cached\n                done = (finished + gid)->load();\n                for(; done == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n                    for(int i = 0; i < b; i++) {\n                        backup[i] = input[next_in_cycle * b + i];\n                    }\n                    done = (finished + next_in_cycle)->exchange(1);\n                    if(!done) {\n                        for(int i = 0; i < b; i++) {\n                            input[next_in_cycle * b + i] = data[i];\n                        }\n                    }\n                    for(int i = 0; i < b; i++) {\n                        data[i] = backup[i];\n                    }\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n            }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_010(T *input, std::atomic_int* head, int a, int b, int tiles, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   tile[a * b];\n            int m = a * b - 1;\n\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < tiles) {\n                T* input_array = input + a * b * gid;\n                for (int j = 0; j < a * b; j++) {\n                    int next = (j * a)-m*(j/b);\n                    tile[next] = input_array[j];\n                }\n                for (int j = 0; j < a * b; j++) {\n                    input_array[j] = tile[j];\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n\t\t    }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads);\nvoid run_cpu_threads_010(T *input, std::atomic_int *head, int m, int n, int tiles, int threads);\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int M_;\n    int m;\n    int N_;\n    int n;\n\n    Params(int argc, char **argv) {\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"ht:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n\t\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    Timer        timer;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 1\");\n        // Launch CPU threads\n        std::thread main_thread_1(run_cpu_threads_100, h_in_out, h_finished, h_head, M_ * m, N_, n, p.n_threads); //M_ * m * N_);\n        main_thread_1.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 1\");\n\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 2\");\n        // Launch CPU threads\n        std::thread main_thread_2(run_cpu_threads_010, h_in_out, h_head, m, n, M_ * N_, p.n_threads);\n        main_thread_2.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 2\");\n\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 3\");\n        // Launch CPU threads\n        for(int i = 0; i < N_; i++){\n            std::thread main_thread_3(run_cpu_threads_100, h_in_out + i * M_ * n * m, h_finished + i * M_ * n, h_head + i, M_, n, m, p.n_threads); //M_ * n);\n            main_thread_3.join();\n\t\t}\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 3\");\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Verify answer\n    //verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    free(h_in_backup);\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T double\n#else\n#define T float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/support/setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, struct timeval> startTime;\r\n    map<string, struct timeval> stopTime;\r\n    map<string, double>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            time[name] = 0.0;\r\n        }\r\n        gettimeofday(&startTime[name], NULL);\r\n    }\r\n\r\n    void stop(string name) {\r\n        gettimeofday(&stopTime[name], NULL);\r\n        time[name] += (stopTime[name].tv_sec - startTime[name].tv_sec) * 1000000.0 +\r\n                      (stopTime[name].tv_usec - startTime[name].tv_usec);\r\n    }\r\n\r\n\t\tvoid print(string name, int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / (1000 * REP)); }\r\n};\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/cpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L$/usr/local/cuda/lib64/ -lm\n\nINC=-I/usr/local/cuda/include/\n\nDEP=kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cu\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 -i 64\n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/common.h\"\n\nextern __shared__ int l_mem[];\n\n// GPU kernel ------------------------------------------------------------------------------------------\n__global__ void PTTWAC_soa_asta(int A, int B, int b, T *input, int *finished, int *head) {\n\n    int* done = l_mem;\n    int* gid_ = &done[1];\n\n    const int tid = threadIdx.x;\n    int       m   = A * B - 1;\n\n    if(tid == 0) // Dynamic fetch\n        gid_[0] = atomicAdd(&head[0], 1);\n    __syncthreads();\n\n    while(gid_[0] < m) {\n        int next_in_cycle = (gid_[0] * A) - m * (gid_[0] / B);\n        if(next_in_cycle == gid_[0]) {\n            if(tid == 0) // Dynamic fetch\n                gid_[0] = atomicAdd(&head[0], 1);\n            __syncthreads();\n            continue;\n        }\n        T   data1, data2, data3, data4;\n        int i = tid;\n        if(i < b)\n            data1 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data2 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data3 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data4 = input[gid_[0] * b + i];\n\n        if(tid == 0) {\n            //make sure the read is not cached\n            done[0] = atomicAdd(&finished[gid_[0]], 0);\n        }\n        __syncthreads();\n\n        for(; done[0] == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n            T backup1, backup2, backup3, backup4;\n            i = tid;\n            if(i < b)\n                backup1 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup2 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup3 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup4 = input[next_in_cycle * b + i];\n\n            if(tid == 0) {\n                done[0] = atomicExch(&finished[next_in_cycle], (int)1);\n            }\n            __syncthreads();\n\n            if(!done[0]) {\n                i = tid;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data1;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data2;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data3;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data4;\n            }\n            i = tid;\n            if(i < b)\n                data1 = backup1;\n            i += blockDim.x;\n            if(i < b)\n                data2 = backup2;\n            i += blockDim.x;\n            if(i < b)\n                data3 = backup3;\n            i += blockDim.x;\n            if(i < b)\n                data4 = backup4;\n        }\n\n        if(tid == 0) // Dynamic fetch\n            gid_[0] = atomicAdd(&head[0], 1);\n        __syncthreads();\n    }\n}\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    PTTWAC_soa_asta<<<dimGrid, dimBlock, l_mem_size>>>(A, B, b, input, \n        finished, head);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n\n__global__ void BS_marshal(T *input, int tile_size, int width) {\n\n  T* tile = (T*)l_mem;\n\n  int tidx = threadIdx.x;\n  int m = width*tile_size-1;\n  int bid = blockIdx.x;\n\n  input += tile_size*width*bid;\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    int next = (i * tile_size)-m*(i/width);\n    tile[next] = input[i];\n  }\n  __syncthreads();\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    input[i] = tile[i];\n  }\n}\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    BS_marshal<<<dimGrid, dimBlock, l_mem_size>>>(input, m, n);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"cuda_runtime.h\"\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size);\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size);\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int device;\n    int n_gpu_threads;\n    int n_gpu_blocks;\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int   M_;\n    int   m;\n    int   N_;\n    int   n;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 64;\n        n_gpu_blocks = 16;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        assert((n_gpu_threads > 0 && n_gpu_blocks > 0)\n            && \"TRNS only runs on CPU-only or GPU-only: './trns -g 0' or './trns -t 0'\");\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=64)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n\t\t        \"\\nBenchmark-specific options:\"\n\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T * d_in_out;\n    int * d_finished;\n    int * d_head;\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMalloc((void**)&d_in_out, in_size * sizeof(T));\n        cudaStatus = cudaMalloc((void**)&d_finished, (p.n_gpu_blocks != 0) ? sizeof(int) * finished_size : 0);\n        cudaStatus = cudaMalloc((void**)&d_head, (p.n_gpu_blocks != 0) ? N_ * sizeof(int) : 0);\n        CUDA_ERR();\n    }\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n        CUDA_ERR();\n    }\n    cudaDeviceSynchronize();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\t\tcudaDeviceSynchronize();\n\n        // Launch GPU threads\n        if(p.n_gpu_blocks > 0) {\n            // Kernel launch\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n\n            cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 1\");\n            // Step 1\n            cudaStatus = call_PTTWAC_soa_asta(M_ * m * N_, p.n_gpu_threads, M_ * m, N_, n,\n                d_in_out, (int*)d_finished, (int*)d_head, sizeof(int) + sizeof(int));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 1\");\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 2\");\n            // Step 2\n            cudaStatus = call_BS_marshal(M_ * N_, p.n_gpu_threads, m, n, d_in_out, m * n * sizeof(T));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 2\");\n\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n            // start timer\n            if(rep >= p.n_warmup)\n                timer.start(\"Step 3\");\n            // Step 3\n            for(int i = 0; i < N_; i++){\n                cudaStatus = call_PTTWAC_soa_asta(M_ * n, p.n_gpu_threads, M_, n, m,\n                    d_in_out + i * M_ * n * m, (int*)d_finished + i * M_ * n, (int*)d_head + i, sizeof(int) + sizeof(int));\n                CUDA_ERR();\n            }\n            // end timer\n            if(rep >= p.n_warmup)\n                timer.stop(\"Step 3\");\n\n        }\n\n        cudaDeviceSynchronize();\n\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(h_in_out, d_in_out, in_size * sizeof(T), cudaMemcpyDeviceToHost);\n        CUDA_ERR();\n        cudaDeviceSynchronize();\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n\n    // Verify answer\n    verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaFree(d_in_out);\n        cudaStatus = cudaFree(d_finished);\n        cudaStatus = cudaFree(d_head);\n        CUDA_ERR();\n    }\n    free(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Step 1\");\n    timer.release(\"Step 2\");\n    timer.release(\"Step 3\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T long int // double\n#else\n#define T int // float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/dpu/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/TRNS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(TRNS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/dpu/task.c",
    "content": "/*\n* 3-step matrix transposition with multiple tasklets\n* Acks: Stefano Ballarin (P&S PIM Fall 2020)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <mutex.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\nuint32_t curr_tile = 0; // protected by MUTEX\nuint32_t get_tile();\nvoid read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\nvoid write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\n_Bool get_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n_Bool get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Mutexes\nMUTEX_INIT(tile_mutex);\nMUTEX_INIT(done_mutex);\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Step 2: 0010\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER; // A in MRAM\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n\n    T* data = (T*) mem_alloc(m * n * sizeof(T));\n    T* backup = (T*) mem_alloc(m * n * sizeof(T));\n\n    for(unsigned int tile = tasklet_id; tile < M_; tile += NR_TASKLETS){\n        read_tile_step2(A, tile * m * n, data, m, n);\n        for (unsigned int i = 0; i < m * n; i++){\n            backup[(i * m) - (m * n - 1) * (i / n)] = data[i];\n        }\n        write_tile_step2(A, tile * m * n, backup, m, n);\n    }\n\n    return 0;\n}\n\n// Step 3: 0100\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t done_array = (uint32_t)(DPU_MRAM_HEAP_POINTER + M_ * m * n * sizeof(T));\n\n    const uint32_t tile_max = M_ * n - 1; // Tile id upper bound\n\n    T* data = (T*)mem_alloc(sizeof(T) * m);\n    T* backup = (T*)mem_alloc(sizeof(T) * m);\n    T* read_done = (T*)mem_alloc(sizeof(T));\n\n    uint32_t tile;\n    _Bool done;\n\n    tile = get_tile();\n\n    while (tile < tile_max){\n        uint32_t next_in_cycle = ((tile * M_) - tile_max * (tile / n));\n        if (next_in_cycle == tile){\n            tile = get_tile();\n            continue;\n        }\n        read_tile_step3(A, tile * m, data, m);\n\n        done = get_done(done_array, tile, read_done);\n        for(; done == 0; next_in_cycle = ((next_in_cycle * M_) - tile_max * (next_in_cycle / n))){\n            read_tile_step3(A, next_in_cycle * m, backup, m);\n\n            done = get_and_set_done(done_array, next_in_cycle, read_done);\n\n            if(!done) {\n                write_tile_step3(A, next_in_cycle * m, data, m);\n            }\n            for(uint32_t i = 0; i < m; i++){\n                data[i] = backup[i];\n            }\n        }\n        tile = get_tile();\n    }\n\t\t\n    return 0;\n}\n\n// Auxiliary functions\nuint32_t __attribute__ ((noinline)) get_tile(){\n    mutex_lock(tile_mutex);\n    uint32_t value = curr_tile;\n    curr_tile++;\n    mutex_unlock(tile_mutex);\n    return value;\n}\n\nvoid __attribute__ ((noinline)) read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_read((__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), variable + (m * n - rest) * sizeof(T), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_write(variable + (m * n - rest) * sizeof(T), (__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_read((__mram_ptr void*)(A + offset * sizeof(T)), variable, sizeof(T) * m);\n}\n\nvoid __attribute__ ((noinline)) write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_write(variable, (__mram_ptr void*)(A + offset * sizeof(T)), sizeof(T) * m);\n}\n\n_Bool __attribute__ ((noinline)) get_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n\n_Bool __attribute__ ((noinline))get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    *read_done |= (0x01 << (address % sizeof(T)));\n    mram_write(read_done, (__mram_ptr void*)(done_array_step3 + address), sizeof(T));\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/host/app.c",
    "content": "/**\n* app.c\n* TRNS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A_host;\nstatic T* A_backup;\nstatic T* A_result;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    unsigned int i = 0;\n    unsigned int N_ = p.N_;\n    const unsigned int n = p.n;\n    const unsigned int M_ = p.M_;\n    const unsigned int m = p.m;\n    N_ = p.exp == 0 ? N_ * NR_DPUS : N_;\n\n    // Input/output allocation\n    A_host = malloc(M_ * m * N_ * n * sizeof(T));\n    A_backup = malloc(M_ * m * N_ * n * sizeof(T));\n    A_result = malloc(M_ * m * N_ * n * sizeof(T));\n    T* done_host = malloc(M_ * n); // Host array to reset done array of step 3\n    memset(done_host, 0, M_ * n);\n\n    // Create an input file with arbitrary data\n    read_input(A_host, M_ * m * N_ * n);\n    memcpy(A_backup, A_host, M_ * m * N_ * n * sizeof(T));\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\n\", NR_TASKLETS);\n    printf(\"M_\\t%u, m\\t%u, N_\\t%u, n\\t%u\\n\", M_, m, N_, n);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        int timer_fix = 0;\n        // Compute output on CPU (performance comparison and verification purposes)\n        memcpy(A_host, A_backup, M_ * m * N_ * n * sizeof(T));\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup + timer_fix);\n        trns_host(A_host, M_ * m, N_ * n, 1);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        unsigned int curr_dpu = 0;\n        unsigned int active_dpus;\n        unsigned int active_dpus_before = 0;\n        unsigned int first_round = 1;\n\n        while(curr_dpu < N_){\n            // Allocate DPUs and load binary\n            if((N_ - curr_dpu) > NR_DPUS){\n                active_dpus = NR_DPUS;\n            } else {\n                active_dpus = (N_ - curr_dpu);\n            }\n            if((active_dpus_before != active_dpus) && (!(first_round))){\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(active_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n                printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n            } else if (first_round){\n                DPU_ASSERT(dpu_alloc(active_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n                printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n            }\n\n            printf(\"Load input data (step 1)\\n\");\n            if(rep >= p.n_warmup)\n                start(&timer, 1, rep - p.n_warmup + timer_fix);\n            // Load input matrix (step 1)\n            for(unsigned int j = 0; j < M_ * m; j++){\n                unsigned int i = 0;\n                DPU_FOREACH(dpu_set, dpu) {\n                    DPU_ASSERT(dpu_prepare_xfer(dpu, &A_backup[j * N_ * n + n * (i + curr_dpu)]));\n                    i++;\n                }\n                DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, sizeof(T) * j * n, sizeof(T) * n, DPU_XFER_DEFAULT));\n            }\n            if(rep >= p.n_warmup)\n                stop(&timer, 1);\n            // Reset done array (for step 3)\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpu_prepare_xfer(dpu, done_host));\n            }\n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, M_ * m * n * sizeof(T), (M_ * n) / 8 == 0 ? 8 : M_ * n, DPU_XFER_DEFAULT));\n\n            unsigned int kernel = 0;\n            dpu_arguments_t input_arguments = {m, n, M_, kernel};\n\t        DPU_FOREACH(dpu_set, dpu, i) {\n\t            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n\t        }\n\t        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n            printf(\"Run step 2 on DPU(s) \\n\");\n            // Run DPU kernel\n            if(rep >= p.n_warmup){\n                start(&timer, 2, rep - p.n_warmup + timer_fix);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_start(&probe));\n#endif\n            }\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if(rep >= p.n_warmup){\n                stop(&timer, 2);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n            }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n            kernel = 1;\n            dpu_arguments_t input_arguments2 = {m, n, M_, kernel};\n\t        DPU_FOREACH(dpu_set, dpu, i) {\n\t            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments2));\n\t        }\n\t        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments2), DPU_XFER_DEFAULT));\n            printf(\"Run step 3 on DPU(s) \\n\");\n            // Run DPU kernel\n            if(rep >= p.n_warmup){\n                start(&timer, 3, rep - p.n_warmup + timer_fix);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_start(&probe));\n#endif\n            }\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if(rep >= p.n_warmup){\n                stop(&timer, 3);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n            }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n            printf(\"Retrieve results\\n\");\n            if(rep >= p.n_warmup)\n                start(&timer, 4, rep - p.n_warmup + timer_fix);\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpu_prepare_xfer(dpu, (T*)(&A_result[curr_dpu * m * n * M_])));\n                curr_dpu++;\n            }\n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, sizeof(T) * m * n * M_, DPU_XFER_DEFAULT));\n            if(rep >= p.n_warmup)\n                stop(&timer, 4);\n\n            if(first_round){\n                first_round = 0;\n            }\n            timer_fix++;\n        }\n        DPU_ASSERT(dpu_free(dpu_set));\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU (Step 1) \");\n    print(&timer, 1, p.n_reps);\n    printf(\"Step 2 \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Step 3 \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < M_ * m * N_ * n; i++) {\n        if(A_host[i] != A_result[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, A_host[i], A_result[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A_host);\n    free(A_backup);\n    free(A_result);\n    free(done_host);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int64_t\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t m;\n    uint32_t n;\n    uint32_t M_;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   M_;\n    unsigned int   m;\n    unsigned int   N_;\n    unsigned int   n;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -m <I>    m (default=16 elements)\"\n        \"\\n    -n <I>    n (default=8 elements)\"\n        \"\\n    -o <I>    M_ (default=12288 elements)\"\n        \"\\n    -p <I>    N_ (default=1 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.M_            = 12288;\n    p.m             = 16;\n    p.N_            = 1;\n    p.n             = 8;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:x:m:n:o:p:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'm': p.m             = atoi(optarg); break;\n        case 'n': p.n             = atoi(optarg); break;\n        case 'o': p.M_            = atoi(optarg); break;\n        case 'p': p.N_            = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TRNS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -lm\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -n 131072\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/TS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(TS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/dpu/task.c",
    "content": "/*\n * STREAMP implementation of Matrix Profile with multiple tasklets\n *\n */\n\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include \"common.h\"\n\n#define DOTPIP BLOCK_SIZE / sizeof(DTYPE)\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_result_t DPU_RESULTS[NR_TASKLETS];\n\n// Dot product\nvoid __attribute__ ((noinline)) dot_product(DTYPE *vectorA, DTYPE *vectorA_aux, DTYPE *vectorB, DTYPE * result) {\n\n\tfor(uint32_t i = 0; i <  BLOCK_SIZE / sizeof(DTYPE); i++)\n\t{\n\t\tfor(uint32_t j = 0; j < DOTPIP; j++)\n\t\t{\n\t\t\tif((j + i) > BLOCK_SIZE / sizeof(DTYPE) - 1)\n\t\t\t{\n\t\t\t\tresult[j] += vectorA_aux[(j + i) - BLOCK_SIZE / sizeof(DTYPE)]  * vectorB[i];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tresult[j] += vectorA[j + i] * vectorB[i];\n\t\t\t}\n\t\t}\n\t}\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n\t// Kernel\n\treturn kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif(tasklet_id == 0){\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\t// Input arguments\n\tuint32_t query_length  = DPU_INPUT_ARGUMENTS.query_length;\n\tDTYPE query_mean       = DPU_INPUT_ARGUMENTS.query_mean;\n\tDTYPE query_std        = DPU_INPUT_ARGUMENTS.query_std;\n\tuint32_t slice_per_dpu = DPU_INPUT_ARGUMENTS.slice_per_dpu;\n\n\t// Boundaries for current tasklet\n\tuint32_t myStartElem = tasklet_id  * (slice_per_dpu / (NR_TASKLETS));\n\tuint32_t myEndElem   = myStartElem + (slice_per_dpu / (NR_TASKLETS)) - 1;\n\n\t// Check time series limit\n\tif(myEndElem > slice_per_dpu - query_length) myEndElem = slice_per_dpu - query_length;\n\n\t// Starting address of the current processing block in MRAM\n\tuint32_t mem_offset = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t// Starting address of the query subsequence\n\tuint32_t current_mram_block_addr_query = (uint32_t)(mem_offset);\n\tmem_offset += query_length * sizeof(DTYPE);\n\n\t// Starting address of the time series slice\n\tmem_offset += myStartElem * sizeof(DTYPE);\n\tuint32_t starting_offset_ts = mem_offset;\n\tuint32_t current_mram_block_addr_TS = (uint32_t) mem_offset;\n\n\t// Starting address of the time series means\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSMean = (uint32_t)(mem_offset);\n\n\t// Starting address of the time series standard deviations\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSSigma = (uint32_t)(mem_offset);\n\n\t// Initialize local caches to store the MRAM blocks\n\tDTYPE *cache_TS       = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TS_aux   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_query    = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSMean   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSSigma  = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_dotprods = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n\t// Create result structure pointer\n\tdpu_result_t *result = &DPU_RESULTS[tasklet_id];\n\n\t// Auxiliary variables\n\tDTYPE distance;\n\tDTYPE min_distance = DTYPE_MAX;\n\tuint32_t min_index = 0;\n\n\n\tfor(uint32_t i = myStartElem; i < myEndElem; i+= (BLOCK_SIZE / sizeof(DTYPE)))\n\t{\n\t\tfor(uint32_t d = 0; d < DOTPIP; d++)\n\t\t\tcache_dotprods[d] = 0;\n\n\t\tcurrent_mram_block_addr_TS    = (uint32_t) starting_offset_ts + (i - myStartElem) * sizeof(DTYPE);\n\t\tcurrent_mram_block_addr_query = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t\tfor(uint32_t j = 0; j < (query_length) / (BLOCK_SIZE / sizeof(DTYPE)); j++)\n\t\t{\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS, cache_TS, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS + BLOCK_SIZE, cache_TS_aux, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_query, cache_query, BLOCK_SIZE);\n\n\t\t\tcurrent_mram_block_addr_TS    += BLOCK_SIZE;\n\t\t\tcurrent_mram_block_addr_query += BLOCK_SIZE;\n\t\t\tdot_product(cache_TS, cache_TS_aux, cache_query, cache_dotprods);\n\t\t}\n\n\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSMean, cache_TSMean, BLOCK_SIZE);\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSSigma, cache_TSSigma, BLOCK_SIZE);\n\t\tcurrent_mram_block_addr_TSMean  += BLOCK_SIZE;\n\t\tcurrent_mram_block_addr_TSSigma += BLOCK_SIZE;\n\n\t\tfor (uint32_t k = 0; k < (BLOCK_SIZE / sizeof(DTYPE)); k++)\n\t\t{\n\t\t\tdistance = 2 * ((DTYPE) query_length - (cache_dotprods[k] - (DTYPE) query_length * cache_TSMean[k]\n\t\t\t\t\t\t* query_mean) / (cache_TSSigma[k] * query_std));\n\n\t\t\tif(distance < min_distance)\n\t\t\t{\n\t\t\t\tmin_distance =  distance;\n\t\t\t\tmin_index    =  i + k;\n\t\t\t}\n\t\t}\n\t}\n\n\t// Save the result\n\tresult->minValue = min_distance;\n\tresult->minIndex = min_index;\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/host/app.c",
    "content": "/**\n * app.c\n * TS Host Application Source File\n *\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n#include <time.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"params.h\"\n#include \"timer.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#define DPU_BINARY \"./bin/ts_dpu\"\n\n#define MAX_DATA_VAL 127\n\nstatic DTYPE tSeries[1 << 26];\nstatic DTYPE query  [1 << 15];\nstatic DTYPE AMean  [1 << 26];\nstatic DTYPE ASigma [1 << 26];\nstatic DTYPE minHost;\nstatic DTYPE minHostIdx;\n\n// Create input arrays\nstatic DTYPE *create_test_file(unsigned int ts_elements, unsigned int query_elements) {\n\tsrand(0);\n\n\tfor (uint64_t i = 0; i < ts_elements; i++)\n\t{\n\t\ttSeries[i] = i % MAX_DATA_VAL;\n\t}\n\n\tfor (uint64_t i = 0; i < query_elements; i++)\n\t{\n\t\tquery[i] = i % MAX_DATA_VAL;\n\t}\n\n\treturn tSeries;\n}\n\n// Compute output in the host\nstatic void streamp(DTYPE* tSeries, DTYPE* AMean, DTYPE* ASigma, int ProfileLength,\n\t\tDTYPE* query, int queryLength, DTYPE queryMean, DTYPE queryStdDeviation)\n{\n\tDTYPE distance;\n\tDTYPE dotprod;\n\tminHost    = INT32_MAX;\n\tminHostIdx = 0;\n\n\tfor (int subseq = 0; subseq < ProfileLength; subseq++)\n\t{\n\t\tdotprod = 0;\n\t\tfor(int j = 0; j < queryLength; j++)\n\t\t{\n\t\t\tdotprod += tSeries[j + subseq] * query[j];\n\t\t}\n\n\t\tdistance = 2 * (queryLength - (dotprod - queryLength * AMean[subseq]\n\t\t\t\t\t* queryMean) / (ASigma[subseq] * queryStdDeviation));\n\n\t\tif(distance < minHost)\n\t\t{\n\t\t\tminHost = distance;\n\t\t\tminHostIdx = subseq;\n\t\t}\n\t}\n}\n\nstatic void compute_ts_statistics(unsigned int timeSeriesLength, unsigned int ProfileLength, unsigned int queryLength)\n{\n\tdouble* ACumSum = malloc(sizeof(double) * timeSeriesLength);\n\tACumSum[0] = tSeries[0];\n\tfor (uint64_t i = 1; i < timeSeriesLength; i++)\n\t\tACumSum[i] = tSeries[i] + ACumSum[i - 1];\n\tdouble* ASqCumSum = malloc(sizeof(double) * timeSeriesLength);\n\tASqCumSum[0] = tSeries[0] * tSeries[0];\n\tfor (uint64_t i = 1; i < timeSeriesLength; i++)\n\t\tASqCumSum[i] = tSeries[i] * tSeries[i] + ASqCumSum[i - 1];\n\tdouble* ASum = malloc(sizeof(double) * ProfileLength);\n\tASum[0] = ACumSum[queryLength - 1];\n\tfor (uint64_t i = 0; i < timeSeriesLength - queryLength; i++)\n\t\tASum[i + 1] = ACumSum[queryLength + i] - ACumSum[i];\n\tdouble* ASumSq = malloc(sizeof(double) * ProfileLength);\n\tASumSq[0] = ASqCumSum[queryLength - 1];\n\tfor (uint64_t i = 0; i < timeSeriesLength - queryLength; i++)\n\t\tASumSq[i + 1] = ASqCumSum[queryLength + i] - ASqCumSum[i];\n\tdouble * AMean_tmp = malloc(sizeof(double) * ProfileLength);\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t\tAMean_tmp[i] = ASum[i] / queryLength;\n\tdouble* ASigmaSq = malloc(sizeof(double) * ProfileLength);\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t\tASigmaSq[i] = ASumSq[i] / queryLength - AMean[i] * AMean[i];\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t{\n\t\tASigma[i] = sqrt(ASigmaSq[i]);\n\t\tAMean[i]  = (DTYPE) AMean_tmp[i];\n\t}\n\n\tfree(ACumSum);\n\tfree(ASqCumSum);\n\tfree(ASum);\n\tfree(ASumSq);\n\tfree(ASigmaSq);\n\tfree(AMean_tmp);\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\t// Timer declaration\n\tTimer timer;\n\n\tstruct Params p = input_params(argc, argv);\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned long int ts_size =  p.input_size_n;\n\tconst unsigned int query_length = p.input_size_m;\n\n\t// Size adjustment\n\tif(ts_size % (nr_of_dpus * NR_TASKLETS*query_length))\n\t\tts_size = ts_size +  (nr_of_dpus * NR_TASKLETS * query_length - ts_size % (nr_of_dpus * NR_TASKLETS*query_length));\n\n\t// Create an input file with arbitrary data\n\tcreate_test_file(ts_size, query_length);\n\tcompute_ts_statistics(ts_size, ts_size - query_length, query_length);\n\n\tDTYPE query_mean;\n\tdouble queryMean = 0;\n\tfor(unsigned i = 0; i < query_length; i++) queryMean += query[i];\n\tqueryMean /= (double) query_length;\n\tquery_mean = (DTYPE) queryMean;\n\n\tDTYPE query_std;\n\tdouble queryStdDeviation;\n\tdouble queryVariance = 0;\n\tfor(unsigned i = 0; i < query_length; i++)\n\t{\n\t\tqueryVariance += (query[i] - queryMean) * (query[i] - queryMean);\n\t}\n\tqueryVariance /= (double) query_length;\n\tqueryStdDeviation = sqrt(queryVariance);\n\tquery_std = (DTYPE) queryStdDeviation;\n\n\tDTYPE *bufferTS     = tSeries;\n\tDTYPE *bufferQ      = query;\n\tDTYPE *bufferAMean  = AMean;\n\tDTYPE *bufferASigma = ASigma;\n\n\tuint32_t slice_per_dpu = ts_size / nr_of_dpus;\n\n\tunsigned int kernel = 0;\n\tdpu_arguments_t input_arguments = {ts_size, query_length, query_mean, query_std, slice_per_dpu, 0, kernel};\n\tuint32_t mem_offset;\n\n\tdpu_result_t result;\n\tresult.minValue = INT32_MAX;\n\tresult.minIndex = 0;\n\tresult.maxValue = 0;\n\tresult.maxIndex = 0;\n\n\tfor (int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\tuint32_t i = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tinput_arguments.exclusion_zone = 0;\n\n\t\t\tDPU_ASSERT(dpu_copy_to(dpu, \"DPU_INPUT_ARGUMENTS\", 0, (const void *) &input_arguments, sizeof(input_arguments)));\n\t\t\ti++;\n\t\t}\n\n\t\ti = 0;\n\t\tmem_offset = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferQ));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, query_length * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tmem_offset += query_length * sizeof(DTYPE);\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferTS + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset,(slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tmem_offset += ((slice_per_dpu + query_length) * sizeof(DTYPE));\n\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferAMean + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tmem_offset += ((slice_per_dpu + query_length) * sizeof(DTYPE));\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferASigma + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n\n\t\tdpu_result_t* results_retrieve[nr_of_dpus];\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tresults_retrieve[i] = (dpu_result_t*)malloc(NR_TASKLETS * sizeof(dpu_result_t));\n\t\t}\n\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_result_t), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tfor (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n\t\t\t\tif(results_retrieve[i][each_tasklet].minValue < result.minValue && results_retrieve[i][each_tasklet].minValue > 0)\n\t\t\t\t{\n\t\t\t\t\tresult.minValue = results_retrieve[i][each_tasklet].minValue;\n\t\t\t\t\tresult.minIndex = (DTYPE)results_retrieve[i][each_tasklet].minIndex + (i * slice_per_dpu);\n\t\t\t\t}\n\n\t\t\t}\n\t\t\tfree(results_retrieve[i]);\n\t\t\ti++;\n\t\t}\n\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\n\n#if PRINT\n\t\tprintf(\"LOGS\\n\");\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpu_log_read(dpu, stdout));\n\t\t}\n#endif\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 4, rep - p.n_warmup);\n\t\tstreamp(tSeries, AMean, ASigma, ts_size - query_length - 1, query, query_length, query_mean, query_std);\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 4);\n\t}\n\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 4, p.n_reps);\n\tprintf(\"Inter-DPU Time (ms): \");\n\tprint(&timer, 0, p.n_reps);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\n\tint status = (minHost == result.minValue);\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] results are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] results differ!\\n\");\n\t}\n\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int32_t\n#define DTYPE_MAX INT32_MAX\n\ntypedef struct  {\n\tuint32_t ts_length;\n    uint32_t query_length;\n    DTYPE query_mean;\n    DTYPE query_std;\n    uint32_t slice_per_dpu;\n    int32_t exclusion_zone;\n    enum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n}dpu_arguments_t;\n\ntypedef struct  {\n    DTYPE minValue;\n    uint32_t minIndex;\n    DTYPE maxValue;\n    uint32_t maxIndex;\n}dpu_result_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  unsigned long  input_size_n;\n  unsigned long  input_size_m;\n  int  n_warmup;\n  int  n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -n <n>    n (TS length. Default=64K elements)\"\n    \"\\n    -m <m>    m (Query length. Default=256 elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size_n  = 1 << 16;\n    p.input_size_m  = 1 << 8;\n\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:n:m:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'n': p.input_size_n  = atol(optarg); break;\n        case 'm': p.input_size_m  = atol(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/TS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o uni -fopenmp app_baseline.c \n\nclean:\n\trm uni\n\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/cpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./uni -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/cpu/app_baseline.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\n#define T int64_t\n\nstatic int pos;\n\nstatic T *A;\nstatic T *B;\nstatic T *C;\nstatic T *C2;\n\n// Create a \"test file\"\nstatic T *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (T*) malloc(nr_elements * sizeof(T));\n    B = (T*) malloc(nr_elements * sizeof(T));\n    C = (T*) malloc(nr_elements * sizeof(T));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        //A[i] = i+1;\n        //A[i] = i%2==0?i+1:i;\n        A[i] = i%2==0?i:i+1;\n        B[i] = 0;\n    }\n\n    return A;\n}\n\n// Compute output in the host\nstatic int unique_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(A[my] != A[my-1]) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n\n    return pos;\n}\n\n// Params \ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:i:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n// Main\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = unique_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n    return 0;\n  }\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc unique.cu -I/usr/local/cuda/include -lm -o unique -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm unique\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/gpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./unique 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__device__ T warp_up(T reg, int delta){\n  __shared__ volatile T R[L_DIM];\n\n  R[threadIdx.x] = reg;\n\n  return (lane_id() - delta >= 0 ? R[threadIdx.x - delta] : 0);\n}\n__device__ T __shuffle_up(T* matrix, int my_s, int pos, T regi, int i){\n#if (__CUDA_ARCH__ >= 300 )\n  T p = __shfl_up(regi, 1);\n#else\n  T p = warp_up(regi, 1);\n#endif\n  if(lane_id() == 0 && i > 0)\n    p = matrix[pos - 1]; \n  if(lane_id() == 0 && threadIdx.x != 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s > 0 && threadIdx.x == 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s == 0 && threadIdx.x == 0 && i == 0)\n    p = -1;\n  return p;\n}\n\n__global__ void unique(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(reg[j] != __shuffle_up(matrix, my_s, pos, reg[j], j))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/baselines/gpu/unique.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_unique(T* output, T* input, int elements){\n  int j = 0;\n  output[j] = input[j];\n  j++;\n  for (int i = 1; i < elements; i++){\n    if (input[i] != input[i-1]){\n      output[j] = input[i];\n      j++;\t\t\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Unique on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n\n  // Allocate the device input vector A\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n\n#define WARMUP 0\n#define REP 1\n  int value1 = 0;\n  int value2 = 1;\n  int value3 = 2;\n  int value4 = 3;\n  unsigned int flagM = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++){\n    \th_A[i] = value1;\n        if(i >= numElements/4 && i < numElements/2) h_A[i] = value2;\n        if(i >= numElements/2 && i < 3*numElements/4) h_A[i] = value3;\n        if(i >= 3*numElements/4 && i < numElements) h_A[i] = value4;\n    }\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x]==value1 || h_A[x]==value2 || h_A[x]==value3 || h_A[x]==value4){\n    \t    h_A[x] = x+2;\n            m--;\n        }\n    }\n\n#if PRINT\n    printf(\"\\n\");\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch\n    unique<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags);\n\n    cudaMemcpy(&flagM, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_unique(h_C, h_A, numElements);\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_C+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM - 1; ++i){\n      if (h_B[i] != h_C[i]){\n          fprintf(stderr, \"Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n\n  return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/UNI/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(UNI_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/dpu/task.c",
    "content": "/*\n* Unique with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nT        message_value[NR_TASKLETS];\nuint32_t message_offset[NR_TASKLETS];\nuint32_t message_partial_count;\nT        message_last_from_last;\n\n// UNI in each tasklet\nunsigned int __attribute__ ((noinline)) unique(T *output, T *input){\n    unsigned int pos = 0;\n    output[pos] = input[pos];\n    pos++;\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        if(input[j] != input[j - 1]) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nuint3 __attribute__ ((noinline)) handshake_sync(T *output, unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count, o_count, offset;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n        offset = (message_value[tasklet_id] == output[0])?1:0;\n        o_count = message_offset[tasklet_id];\n    }\n    else{\n        p_count = 0;\n        offset = (message_last_from_last == output[0])?1:0;\n        o_count = 0;\n    }\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        message_value[tasklet_id + 1] = output[l_count - 1];\n        message_offset[tasklet_id + 1] = o_count + offset;\n        handshake_notify();\n    }\n    uint3 result = {p_count, o_count, offset}; \n    return result;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1){\n        message_partial_count = 0;\n        message_last_from_last = 0xFFFFFFFF; // A value that is not in the input array\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    unsigned int i = 0; // Iteration count\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // UNI in each tasklet\n        unsigned int l_count = unique(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint3 po_count = handshake_sync(cache_B, l_count, tasklet_id);\n\n        // Write cache to current MRAM block\n        mram_write(&cache_B[po_count.z], (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + po_count.x - po_count.y) * sizeof(T)), l_count * sizeof(T));\n\n        // First\n        if(tasklet_id == 0 && i == 0){\n            result->first = cache_B[0];\n        }\n        \n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            message_last_from_last = cache_B[l_count - 1];\n            result->last = cache_B[l_count - 1];\n            result->t_count = message_partial_count + po_count.x + l_count - po_count.y - po_count.z;\n            message_partial_count = result->t_count;\n        }\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        i++;\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/host/app.c",
    "content": "/**\n* app.c\n* UNI Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand());\n        A[i] = i%2==0?i:i+1;\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = A[nr_elements - 1];\n    }\n}\n\n// Compute output in the host\nstatic unsigned int unique_host(T* C, T* A, unsigned int nr_elements) {\n    unsigned int pos = 0;\n    C[pos] = A[pos];\n    pos++;\n    for(unsigned int i = 1; i < nr_elements; i++) {\n        if(A[i] != A[i-1]) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    uint32_t accum = 0;\n    uint32_t total_count = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        total_count = unique_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        uint32_t* results_scan = malloc(nr_of_dpus * sizeof(uint32_t));\n        uint32_t* offset = calloc(nr_of_dpus, sizeof(uint32_t));\n        uint32_t* offset_scan = calloc(nr_of_dpus, sizeof(uint32_t));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                // First output element of this DPU\n                if(each_tasklet == 0){\n                    results[i].first = results_retrieve[i][each_tasklet].first;\n                }\n                // Last output element of this DPU and count\n                if(each_tasklet == NR_TASKLETS - 1){\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n                    results[i].last = results_retrieve[i][each_tasklet].last;\n                }\n            }\n            // Check if first(i) == last(i-1) -- offset\n            if(i != 0){\n                if(results[i].first == results[i - 1].last)\n                    offset[i] = 1;\n                // Sequential scan - offset\n                offset_scan[i] += offset[i];\n            }\n            // Sequential scan\n            uint32_t temp = results[i].t_count - offset[i];\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %u,  %u, %u -- %u\\n\", i, results_scan[i], accum, temp, offset_scan[i]);\n#endif\n            free(results_retrieve[i]);\n        }\n        if(rep >= p.n_warmup)\n\t\t    stop(&timer, 3);\n\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 4, rep - p.n_warmup);\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferC + results_scan[i] - offset_scan[i], results[i].t_count * sizeof(T)));\n\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 4);\n\n        // Free memory\n        free(results_scan);\n        free(offset);\n        free(offset_scan);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n#if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n#endif\t\n\n    // Check output\n    bool status = true;\n    if(accum != total_count) status = false;\n#if PRINT\n    printf(\"accum %u, total_count %u\\n\", accum, total_count);\n#endif\n    for (i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Data type\n#define T int64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n    T first;\n    T last;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\ntypedef struct{unsigned int x; unsigned int y; unsigned int z;} uint3;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/UNI/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nTYPE ?= INT32\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o ${HOST_TARGET}.bin ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o va -fopenmp app_baseline.c \n\nclean:\n\trm va\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/cpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va -t 4\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic int32_t *A;\nstatic int32_t *B;\nstatic int32_t *C;\nstatic int32_t *C2; \n\n/**\n* @brief creates a \"test file\" by filling a buffer of 64MB with pseudo-random values\n* @param nr_elements how many 32-bit elements we want the file to be\n* @return the buffer address\n*/\nvoid  *create_test_file(unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    A = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    B = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    C = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    \n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = (int) (rand());\n        B[i] = (int) (rand());\n    }\n\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void vector_addition_host(unsigned int nr_elements, int t) {\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for (int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16777216;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads        = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    vector_addition_host(file_size, p.n_threads);\n\t\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n\n   return 0;\n }\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc vec_add.cu -I/usr/local/cuda/include -lm -o va\n\nclean:\n\trm va\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/gpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/baselines/gpu/vec_add.cu",
    "content": "/* File:     vec_add.cu\n * Purpose:  Implement vector addition on a gpu using cuda\n *\n * Compile:  nvcc [-g] [-G] -o vec_add vec_add.cu\n * Run:      ./vec_add\n */\n\n#include <stdio.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <math.h>\n\n__global__ void Vec_add(unsigned int x[], unsigned int y[], unsigned int z[], int n) {\n    int thread_id = blockIdx.x * blockDim.x + threadIdx.x;\n    if (thread_id < n){\n        z[thread_id] = x[thread_id] + y[thread_id];\n    }\n}\n\n\nint main(int argc, char* argv[]) {\n    int n, m;\n    unsigned int *h_x, *h_y, *h_z;\n    unsigned int *d_x, *d_y, *d_z;\n    size_t size;\n\n    /* Define vector length */\n    n = 2621440;\n    m = 320;\n    size = m * n * sizeof(unsigned int);\n\n    // Allocate memory for the vectors on host memory.\n    h_x = (unsigned int*) malloc(size);\n    h_y = (unsigned int*) malloc(size);\n    h_z = (unsigned int*) malloc(size);\n\n    for (int i = 0; i < n * m; i++) {\n        h_x[i] = i+1;\n        h_y[i] = n-i;\n    }\n\n    printf(\"Input size = %d\\n\", n * m);\n\n    // Print original vectors.\n    /*printf(\"h_x = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_x[i]);\n    }\n    printf(\"\\n\\n\");\n    printf(\"h_y = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_y[i]);\n    }\n    printf(\"\\n\\n\");*/\n\n    // Event creation\n    cudaEvent_t start, stop;\n    cudaEventCreate(&start);\n    cudaEventCreate(&stop);\n    float time1 = 0;\n\n    /* Allocate vectors in device memory */\n    cudaMalloc(&d_x, size);\n    cudaMalloc(&d_y, size);\n    cudaMalloc(&d_z, size);\n\n    /* Copy vectors from host memory to device memory */\n    cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);\n    cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);\n    \n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    /* Kernel Call */\n    Vec_add<<<(n * m) / 256, 256>>>(d_x, d_y, d_z, n * m);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n\n    cudaMemcpy(h_z, d_z, size, cudaMemcpyDeviceToHost);\n    /*printf(\"The sum is: \\n\");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_z[i]);\n    }\n    printf(\"\\n\");*/\n\n    printf(\"Execution time = %f ms\\n\", time1);\n\n    /* Free device memory */\n    cudaFree(d_x);\n    cudaFree(d_y);\n    cudaFree(d_z);\n    /* Free host memory */\n    free(h_x);\n    free(h_y);\n    free(h_z);\n\n    return 0;\n}  /* main */\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT32)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/VA/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(VA_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/dpu/task.c",
    "content": "/*\n* Vector addition with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// vector_addition: Computes the vector addition of a cached block \nvoid __attribute__ ((noinline)) vector_addition(T *bufferB, T *bufferA, unsigned int l_size) {\n    for (unsigned int i = 0; i < l_size; i++){\n        bufferB[i] += bufferA[i];\n    }\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, l_size_bytes);\n\n        // Computer vector addition\n        vector_addition(cache_B, cache_A, l_size_bytes >> DIV);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), l_size_bytes);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/host/app.c",
    "content": "/**\n* app.c\n* VA Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void vector_addition_host(T* C, T* A, T* B, unsigned int nr_elements) {\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n\n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n    unsigned int i = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    B = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        vector_addition_host(C, A, B, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments[NR_DPUS];\n        for(i=0; i<nr_of_dpus-1; i++) {\n            input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].kernel=kernel;\n        }\n        input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n        input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n        input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n \n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferB + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n#if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n#endif\t\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2621440 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2621440;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/VA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang/uPIMulator/benchmark/build.py",
    "content": "import os\nimport shutil\nimport subprocess\nimport argparse\n\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\"--num_dpus\", type=int, default=1)\n    parser.add_argument(\"--num_tasklets\", type=int, default=1)\n    args = parser.parse_args()\n\n    benchmark_dir_path = os.path.dirname(__file__)\n\n    build_dir_path = os.path.join(benchmark_dir_path, \"build\")\n\n    if os.path.exists(build_dir_path):\n        shutil.rmtree(build_dir_path)\n    os.makedirs(build_dir_path)\n\n    subprocess.run(\n        [\n            \"cmake\",\n            \"-D\",\n            f\"NR_DPUS={args.num_dpus}\",\n            \"-D\"\n            f\"NR_TASKLETS={args.num_tasklets}\",\n            \"-S\",\n            benchmark_dir_path,\n            \"-B\",\n            build_dir_path,\n            \"-G\",\n            \"Ninja\",\n        ]\n    )\n    subprocess.run([\"ninja\", \"-C\", build_dir_path])\n"
  },
  {
    "path": "golang/uPIMulator/docker/Dockerfile",
    "content": "FROM ubuntu:22.04\r\n\r\nENV DEBIAN_FRONTEND=noninteractive\r\n\r\nRUN apt update\r\nRUN apt install -y git\r\nRUN apt install -y wget\r\nRUN apt install -y cmake\r\nRUN apt install -y ninja-build\r\nRUN apt install -y pkg-config\r\nRUN apt install -y python3\r\nRUN apt install -y python3-pip\r\n\r\n# UPMEM SDK\r\nWORKDIR /root\r\nRUN wget sdk-releases.upmem.com/2023.2.0/ubuntu_22.04/upmem-2023.2.0-Linux-x86_64.tar.gz\r\nRUN tar -zxvf upmem-2023.2.0-Linux-x86_64.tar.gz\r\nRUN echo \"source /root/upmem-2023.2.0-Linux-x86_64/upmem_env.sh\" > /root/.bashrc\r\n\r\nWORKDIR /root/uPIMulator\r\n"
  },
  {
    "path": "golang/uPIMulator/go.mod",
    "content": "module uPIMulator\n\ngo 1.21.5\n"
  },
  {
    "path": "golang/uPIMulator/go.sum",
    "content": "github.com/alecthomas/template v0.0.0-20190718012654-fb15b899a751 h1:JYp7IbQjafoB+tBA3gMyHYHrpOtNuDiK/uB5uXxq5wM=\ngithub.com/alecthomas/template v0.0.0-20190718012654-fb15b899a751/go.mod h1:LOuyumcjzFXgccqObfd/Ljyb9UuFJ6TxHnclSeseNhc=\ngithub.com/alecthomas/units v0.0.0-20231202071711-9a357b53e9c9 h1:ez/4by2iGztzR4L0zgAOR8lTQK9VlyBVVd7G4omaOQs=\ngithub.com/alecthomas/units v0.0.0-20231202071711-9a357b53e9c9/go.mod h1:OMCwj8VM1Kc9e19TLln2VL61YJF0x1XFtfdL4JdbSyE=\ngithub.com/dave/dst v0.27.3 h1:P1HPoMza3cMEquVf9kKy8yXsFirry4zEnWOdYPOoIzY=\ngithub.com/dave/dst v0.27.3/go.mod h1:jHh6EOibnHgcUW3WjKHisiooEkYwqpHLBSX1iOBhEyc=\ngithub.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38=\ngithub.com/davecgh/go-spew v1.1.1/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38=\ngithub.com/fatih/structtag v1.2.0 h1:/OdNE99OxoI/PqaW/SuSK9uxxT3f/tcSZgon/ssNSx4=\ngithub.com/fatih/structtag v1.2.0/go.mod h1:mBJUNpUnHmRKrKlQQlmCrh5PuhftFbNv8Ys4/aAZl94=\ngithub.com/konsorten/go-windows-terminal-sequences v1.0.3 h1:CE8S1cTafDpPvMhIxNJKvHsGVBgn1xWYf1NbHQhywc8=\ngithub.com/konsorten/go-windows-terminal-sequences v1.0.3/go.mod h1:T0+1ngSBFLxvqU3pZ+m/2kptfBszLMUkC4ZK/EgS/cQ=\ngithub.com/mattn/go-colorable v0.1.13 h1:fFA4WZxdEF4tXPZVKMLwD8oUnCTTo08duU7wxecdEvA=\ngithub.com/mattn/go-colorable v0.1.13/go.mod h1:7S9/ev0klgBDR4GtXTXX8a3vIGJpMovkB8vQcUbaXHg=\ngithub.com/mattn/go-isatty v0.0.16/go.mod h1:kYGgaQfpe5nmfYZH+SKPsOc2e4SrIfOl2e/yFXSvRLM=\ngithub.com/mattn/go-isatty v0.0.20 h1:xfD0iDuEKnDkl03q4limB+vH+GxLEtL/jb4xVJSWWEY=\ngithub.com/mattn/go-isatty v0.0.20/go.mod h1:W+V8PltTTMOvKvAeJH7IuucS94S2C6jfK/D7dTCTo3Y=\ngithub.com/mgutz/ansi v0.0.0-20200706080929-d51e80ef957d h1:5PJl274Y63IEHC+7izoQE9x6ikvDFZS2mDVS3drnohI=\ngithub.com/mgutz/ansi v0.0.0-20200706080929-d51e80ef957d/go.mod h1:01TrycV0kFyexm33Z7vhZRXopbI8J3TDReVlkTgMUxE=\ngithub.com/pmezard/go-difflib v1.0.0 h1:4DBwDE0NGyQoBHbLQYPwSUPoCMWR5BEzIk/f1lZbAQM=\ngithub.com/pmezard/go-difflib v1.0.0/go.mod h1:iKH77koFhYxTK1pcRnkKkqfTogsbg7gZNVY4sRDYZ/4=\ngithub.com/segmentio/golines v0.11.0 h1:5NVrYkCBoe9wLerhTi+WFOlqx9g3PtP5Tm27uartkL0=\ngithub.com/segmentio/golines v0.11.0/go.mod h1:BRnGHV3is9Qs/58zOqy3CFwH1B2jdVsViGY3G+qctSs=\ngithub.com/sirupsen/logrus v1.9.3 h1:dueUQJ1C2q9oE3F7wvmSGAaVtTmUizReu6fjN8uqzbQ=\ngithub.com/sirupsen/logrus v1.9.3/go.mod h1:naHLuLoDiP4jHNo9R0sCBMtWGeIprob74mVsIT4qYEQ=\ngithub.com/stretchr/objx v0.1.0/go.mod h1:HFkY916IF+rwdDfMAkV7OtwuqBVzrE8GR6GFx+wExME=\ngithub.com/stretchr/testify v1.4.0/go.mod h1:j7eGeouHqKxXV5pUuKE4zz7dFj8WfuZ+81PSLYec5m4=\ngithub.com/stretchr/testify v1.7.0/go.mod h1:6Fq8oRcR53rry900zMqJjRRixrwX3KX962/h/Wwjteg=\ngithub.com/x-cray/logrus-prefixed-formatter v0.5.2 h1:00txxvfBM9muc0jiLIEAkAcIMJzfthRT6usrui8uGmg=\ngithub.com/x-cray/logrus-prefixed-formatter v0.5.2/go.mod h1:2duySbKsL6M18s5GU7VPsoEPHyzalCE06qoARUCeBBE=\ngolang.org/x/crypto v0.17.0 h1:r8bRNjWL3GshPW3gkd+RpvzWrZAwPS49OmTGZ/uhM4k=\ngolang.org/x/crypto v0.17.0/go.mod h1:gCAAfMLgwOJRpTjQ2zCCt2OcSfYMTeZVSRtQlPC7Nq4=\ngolang.org/x/mod v0.14.0 h1:dGoOF9QVLYng8IHTm7BAyWqCqSheQ5pYWGhzW00YJr0=\ngolang.org/x/mod v0.14.0/go.mod h1:hTbmBsO62+eylJbnUtE2MGJUyE7QWk4xUqPFrRgJ+7c=\ngolang.org/x/sys v0.0.0-20220715151400-c0bba94af5f8/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=\ngolang.org/x/sys v0.0.0-20220811171246-fbc7d0a398ab/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=\ngolang.org/x/sys v0.6.0/go.mod h1:oPkhp1MJrh7nUepCBck5+mAzfO9JrbApNNgaTdGDITg=\ngolang.org/x/sys v0.15.0 h1:h48lPFYpsTvQJZF4EKyI4aLHaev3CxivZmv7yZig9pc=\ngolang.org/x/sys v0.15.0/go.mod h1:/VUhepiaJMQUp4+oa/7Zr1D23ma6VTLIYjOOTFZPUcA=\ngolang.org/x/term v0.15.0 h1:y/Oo/a/q3IXu26lQgl04j/gjuBDOBlx7X6Om1j2CPW4=\ngolang.org/x/term v0.15.0/go.mod h1:BDl952bC7+uMoWR75FIrCDx79TPU9oHkTZ9yRbYOrX0=\ngolang.org/x/tools v0.16.1 h1:TLyB3WofjdOEepBHAU20JdNC1Zbg87elYofWYAY5oZA=\ngolang.org/x/tools v0.16.1/go.mod h1:kYVVN6I1mBNoB1OX+noeBjbRk4IUEPa7JJ+TJMEooJ0=\ngolang.org/x/xerrors v0.0.0-20231012003039-104605ab7028 h1:+cNy6SZtPcJQH3LJVLOSmiC7MMxXNOb3PU/VUEz+EhU=\ngolang.org/x/xerrors v0.0.0-20231012003039-104605ab7028/go.mod h1:NDW/Ps6MPRej6fsCIbMTohpP40sJ/P/vI1MoTEGwX90=\ngopkg.in/alecthomas/kingpin.v2 v2.2.6 h1:jMFz6MfLP0/4fUyZle81rXUoxOBFi19VUFKVDOQfozc=\ngopkg.in/alecthomas/kingpin.v2 v2.2.6/go.mod h1:FMv+mEhP44yOT+4EoQTLFTRgOQ1FBLkstjWtayDeSgw=\ngopkg.in/check.v1 v0.0.0-20161208181325-20d25e280405/go.mod h1:Co6ibVJAznAaIkqp8huTwlJQCZ016jof/cbN4VW5Yz0=\ngopkg.in/yaml.v2 v2.2.2/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI=\ngopkg.in/yaml.v3 v3.0.0-20200313102051-9f266ea9e77c/go.mod h1:K4uyk7z7BCEPqu6E+C64Yfv1cQ7kz7rIZviUmN+EgEM=\n"
  },
  {
    "path": "golang/uPIMulator/script/build.py",
    "content": "import os\r\nimport shutil\r\nimport subprocess\r\n\r\n\r\nif __name__ == \"__main__\":\r\n    script_dirpath = os.path.dirname(__file__)\r\n\r\n    build_dirpath = os.path.join(script_dirpath, \"..\", \"build\")\r\n    src_dirpath = os.path.join(script_dirpath, \"..\", \"src\")\r\n\r\n    if os.path.exists(build_dirpath):\r\n        shutil.rmtree(build_dirpath)\r\n    os.makedirs(build_dirpath)\r\n\r\n    binary_filepath = os.path.join(build_dirpath, \"uPIMulator\")\r\n\r\n    subprocess.run([\"go\", \"build\", \"-C\", src_dirpath, \"-o\", binary_filepath])\r\n"
  },
  {
    "path": "golang/uPIMulator/script/format.py",
    "content": "import os\r\nimport subprocess\r\n\r\n\r\nif __name__ == \"__main__\":\r\n    script_dirpath = os.path.dirname(__file__)\r\n\r\n    src_dirpath = os.path.join(script_dirpath, \"..\", \"src\")\r\n\r\n    subprocess.run([\"gofmt\", \"-l\", src_dirpath])\r\n    subprocess.run([\"golines\", \"-w\", src_dirpath])\r\n"
  },
  {
    "path": "golang/uPIMulator/script/run_validation.sh",
    "content": "#/bin/bash\n\nroot_dir=/home/via/dongjae/upimulator_beta/golang/uPIMulator\n\neval \"mkdir -p ${root_dir}/bin/\"\n\nfor num_tasklets in 1 2 4 8 16\ndo\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark BS --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 8192\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/BS_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"BS-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark GEMV --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 256\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/GEMV_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"GEMV-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark HST-L --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 32768\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/HST-L_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"HST-L-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark HST-S --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 32768\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/HST-S_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"HST-S-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark MLP --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 64\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/MLP_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"MLP-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark RED --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/RED_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"RED-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark SCAN-RSS --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/SCAN-RSS_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"SCAN-RSS-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark SCAN-SSA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/SCAN-SSA_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"SCAN-SSA-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark SEL --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/SEL_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"SEL-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark TRNS --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 128\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/TRNS_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"TRNS-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark TS --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 256\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/TS_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"TS-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark UNI --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/UNI_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"UNI-${num_tasklets} done \\n\"\n\n    eval \"${root_dir}/build/uPIMulator --root_dirpath ${root_dir}/ --bin_dirpath ${root_dir}/bin --benchmark VA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets ${num_tasklets} --data_prep_params 65536\"\n    eval \"mv ${root_dir}/bin/log.txt ${root_dir}/validation_log/VA_${num_tasklets}.txt\"\n    eval \"rm ${root_dir}/bin/*\"\n    echo \"VA-${num_tasklets} done \\n\"\n\n\ndone"
  },
  {
    "path": "golang/uPIMulator/script/visualize.py",
    "content": "import graphviz\r\nimport os\r\n\r\n\r\nif __name__ == \"__main__\":\r\n    script_dirpath = os.path.dirname(__file__)\r\n\r\n    bin_dirpath = os.path.join(script_dirpath, \"..\", \"bin\")\r\n    host_dirpath = os.path.join(bin_dirpath, \"host\")\r\n\r\n    nodes_filepath = os.path.join(host_dirpath, \"ast_nodes.txt\")\r\n    edges_filepath = os.path.join(host_dirpath, \"ast_edges.txt\")\r\n\r\n    g = graphviz.Digraph(filename=\"ast\", format=\"pdf\", directory=host_dirpath)\r\n\r\n    with open(nodes_filepath, \"r\") as f:\r\n        for line in f.readlines():\r\n            node = line.strip()\r\n\r\n            g.node(name=node)\r\n\r\n    with open(edges_filepath, \"r\") as f:\r\n        for line in f.readlines():\r\n            tail, head = line.split(\"->\")\r\n\r\n            tail = tail.strip()\r\n            head = head.strip()\r\n\r\n            g.edge(tail_name=tail, head_name=head)\r\n\r\n    g.view()\r\n"
  },
  {
    "path": "golang/uPIMulator/sdk/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\nproject(sdk)\n\nadd_subdirectory(misc)\nadd_subdirectory(stdlib)\nadd_subdirectory(syslib)\n"
  },
  {
    "path": "golang/uPIMulator/sdk/build.py",
    "content": "import os\nimport shutil\nimport subprocess\nimport argparse\n\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\"--num_tasklets\", type=int, default=1)\n    args = parser.parse_args()\n\n    sdk_dir_path = os.path.dirname(__file__)\n\n    build_dir_path = os.path.join(sdk_dir_path, \"build\")\n\n    if os.path.exists(build_dir_path):\n        shutil.rmtree(build_dir_path)\n    os.makedirs(build_dir_path)\n\n    subprocess.run(\n        [\n            \"cmake\",\n            \"-D\",\n            f\"NR_TASKLETS={args.num_tasklets}\",\n            \"-S\",\n            sdk_dir_path,\n            \"-B\",\n            build_dir_path,\n            \"-G\",\n            \"Ninja\",\n        ]\n    )\n    subprocess.run([\"ninja\", \"-C\", build_dir_path])\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(misc ${SRCS})\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/accessMramFromDpu.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    // Preconditions:\n    //  - MRAM offset is a multiple of 8\n    //  - Buffer size is a multiple of 8\n\n    __asm__ volatile(\"  sd zero, 0, d0\\n\" // Saving context\n                     \"  sd zero, 8, d2\\n\"\n                     \"  or r0, zero, 0, ?xnz, . + 2\\n\"\n                     \"  or r0, r0, 0x2\\n\"\n                     \"  addc r0, r0, 0\\n\"\n                     \"  sw zero, 16, r0\\n\"\n                     \"  lw r0, zero, 20\\n\" // MRAM offset, must be patched by the Host\n                     \"resume_start:\\n\"\n                     \"  lw r1, zero, 24\\n\" // Buffer size, must be patched by the Host\n                     \"  move r2, 32\\n\" // Wram offset\n                     \"  move r3, 2048\\n\" // Transfer size\n                     \"  transfer_loop:\\n\"\n                     \"  jltu r1, r3, last_transfer\\n\"\n                     \"  ldma r2, r0, 255\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r3\\n\"\n                     \"  add r2, r2, r3\\n\"\n                     \"  sub r1, r1, r3, true, transfer_loop\\n\"\n                     \"last_transfer:\\n\"\n                     \"  jz r1, end\\n\"\n                     \"  lsr r3, r1, 3\\n\"\n                     \"  add r3, r3, -1\\n\"\n                     \"  lsl_add r2, r2, r3, 24\\n\"\n                     \"  ldma r2, r0, 0\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r1\\n\"\n                     \"end:\\n\"\n                     \"  lw r2, zero, 28\\n\" // Restoring context if needed\n                     \"  jnz r2, . + 2\\n\"\n                     \"  stop true, resume_start\\n\"\n                     \"  ld d2, zero, 8\\n\"\n                     \"  lw r0, zero, 16\\n\"\n                     \"  add r1, r0, r0\\n\"\n                     \"  add r0, r0, r1\\n\"\n                     \"  call zero, r0, . + 1\\n\"\n                     \"  add r0, zero, 0x00000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 0\n                     \"  add r0, mneg, 0x80000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 1\n                     \"  add r0, zero, 0x00000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 0\n                     \"  add r0, mneg, 0x80000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 1\n    );\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/coreDump.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"core dump\" program, used by debugging processes to fetch each\n * runtime register and the atomic bits.\n * The program should be booted once on runtime 0.\n *\n * The output in WRAM has the following form:\n *  - byte 0..255 = atomic bits : each bit is stored into an individual byte\n *  - byte 256..2559 = work registers\n *  - byte 2560..2555 = flags\n *\n * Only the runtime 0 fills in the atomic bits part of the output.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0), d0\\n\"\n        \"  or r0, zero, 0, ?xnz, no_z_flag\\n\"\n        \"  or r0, r0, 0x2\\n\"\n        \"  no_z_flag:\\n\"\n        \"  addc r0, r0, 0\\n\"\n        \"  sw id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12), r0\\n\"\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1), d2\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2), d4\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3), d6\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4), d8\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5), d10\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6), d12\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7), d14\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8), d16\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9), d18\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10), d20\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11), d22\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  sb r0, 0, 0xFF\\n\"\n        \"  acquire r0, 0, nz, atomic_next\\n\"\n        \"  sb r0, 0, 0x00\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/crt0.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <macro_utils.h>\n#include <attributes.h>\n#include <stdint.h>\n#include <dpuruntime.h>\n\n__mram_noinit uint8_t __sys_used_mram_end[0];\n\nuint64_t __sys_null_pointer __attribute__((used, section(\".data.__sys_zero\"))) = 0ULL;\n\nuint32_t __lower_data(\"thread_profiling\") thread_profiling[NR_THREADS];\nuint32_t perfcounter_end_value;\n\n#define DECLARE_STACK(x)                                                                                                         \\\n    extern uint32_t __sys_stack_thread_##x;                                                                                      \\\n    extern uint32_t STACK_SIZE_TASKLET_##x;\n#define SET_STACK_TABLE_PTR(x)                                                                                                   \\\n    [x] = { .stack_ptr = (uint32_t)&__sys_stack_thread_##x, .stack_size = (uint32_t)&STACK_SIZE_TASKLET_##x },\n\n__FOR_EACH_THREAD(DECLARE_STACK);\n\nthread_stack_t __keep __dma_aligned __SP_TABLE__[NR_THREADS] = { __FOR_EACH_THREAD(SET_STACK_TABLE_PTR) };\n\n__host const volatile uint32_t CLOCKS_PER_SEC;\n\n__host const volatile uint32_t error_storage;\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"), no_instrument_function)) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jnz id, __sys_start_thread\\n\"\n        __CONFIG_PERFCOUNTER_ENTRY__\n        \"  sd zero, \" __STR(__STDOUT_BUFFER_STATE) \", 0\\n\"\n        \"  move r23, \" __STR(__atomic_end_addr) \"\\n\"\n        \"__sys_atomic_bit_clear:\\n\"\n        \"  jeq r23, \" __STR(__atomic_used_addr) \", __sys_start_thread\\n\"\n        \"  release r23, 0, nz, . + 1\\n\"\n        \"  add r23, r23, -1, true, __sys_atomic_bit_clear\\n\"\n        \"__sys_start_thread:\\n\"\n        \"  jeq id, NR_TASKLETS - 1, . + 2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d22, id8, \" __STR(__SP_TABLE__) \"\\n\"\n        \"  call r23, main\\n\"\n        \".globl __sys_end\\n\"\n        \"__sys_end:\\n\"\n        __SAVE_PERFCOUNTER_ENTRY__\n        \"  stop true, __sys_end\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/dpu.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Default linker script for DPU programs.\n * The bootstrap sequence is generated by the studio as __bootstrap.\n * The two DPU memories (IRAM and WRAM) are mapped on two different\n * \"virtual\" spaces:\n *  - IRAM: starts at address 0x80000000, which may imply fixups\n *    when loading and debugging of programs\n *  - WRAM: exposed as is at address 0x00000000\n *\n * In addition, the run-time environment information is stored into\n * a virtual physical space at 0x40000000.\n */\nENTRY(__bootstrap)\nMEMORY {\n    iram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n    mram (wa) : ORIGIN = 0x08000000, LENGTH = 64M\n    wram (wa) : ORIGIN = 0x00000000, LENGTH = 64K\n    atomic (r) : ORIGIN = 0xF0000000, LENGTH = 256\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text.__bootstrap)\n    *(.text)\n    *(.text.*) \n  } > iram\n\n  /*\n   * Atomic bits 'allocator'\n   */\n  .atomic (NOLOAD) : {\n    __atomic_start_addr = .;\n    . = . + 200;\n    __atomic_used_addr = .;\n    *(.atomic)\n    __atomic_end_addr = .;\n  } > atomic\n\n  /*\n   * Locate every other section as data.\n   */\n  .data : {\n    KEEP(*(.data.__sys_zero))\n    . += MAX(8, .);\n    /* WRAM accessible using loads and stores with immediate 11-bit offsets */\n    *(.data.immediate_memory .data.immediate_memory.*)\n    HIDDEN(__imm_mem_end = .);\n    ASSERT(__imm_mem_end < 2048, \"immediate memory not accessible with 11-bit address\")\n    __rodata_start_addr = .;\n    *(.rodata .rodata.*)\n    __rodata_end_addr = .;\n    *(.bss .bss.*)\n    *(COMMON)\n    /* Data that we want to keep even there seems to be no use,\n     * usually because host may need it.\n     */\n    KEEP(*(.data.__sys_keep))\n    *(.data .data.*)\n    . = ALIGN(8);\n  } > wram\n\n  .data.__sys_host : {\n    . = ALIGN(8);\n    KEEP(*(.dpu_host))\n  } > wram\n\n  .data.__sys_profiling : {\n    . = ALIGN(4);\n    KEEP(*(.dpu_profiling))\n  } > wram\n\n  .data.stacks (NOLOAD) : {\n    ASSERT(NR_TASKLETS >= 0 && NR_TASKLETS <= 24, \"NR_TASKLETS should be in the range: [0; 24]\")\n    ASSERT(((STACK_SIZE_TASKLET_0  % 8 == 0) && (STACK_SIZE_TASKLET_0  > 0)) || (NR_TASKLETS <= 0 ), \"STACK_SIZE_TASKLET_0  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_1  % 8 == 0) && (STACK_SIZE_TASKLET_1  > 0)) || (NR_TASKLETS <= 1 ), \"STACK_SIZE_TASKLET_1  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_2  % 8 == 0) && (STACK_SIZE_TASKLET_2  > 0)) || (NR_TASKLETS <= 2 ), \"STACK_SIZE_TASKLET_2  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_3  % 8 == 0) && (STACK_SIZE_TASKLET_3  > 0)) || (NR_TASKLETS <= 3 ), \"STACK_SIZE_TASKLET_3  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_4  % 8 == 0) && (STACK_SIZE_TASKLET_4  > 0)) || (NR_TASKLETS <= 4 ), \"STACK_SIZE_TASKLET_4  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_5  % 8 == 0) && (STACK_SIZE_TASKLET_5  > 0)) || (NR_TASKLETS <= 5 ), \"STACK_SIZE_TASKLET_5  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_6  % 8 == 0) && (STACK_SIZE_TASKLET_6  > 0)) || (NR_TASKLETS <= 6 ), \"STACK_SIZE_TASKLET_6  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_7  % 8 == 0) && (STACK_SIZE_TASKLET_7  > 0)) || (NR_TASKLETS <= 7 ), \"STACK_SIZE_TASKLET_7  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_8  % 8 == 0) && (STACK_SIZE_TASKLET_8  > 0)) || (NR_TASKLETS <= 8 ), \"STACK_SIZE_TASKLET_8  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_9  % 8 == 0) && (STACK_SIZE_TASKLET_9  > 0)) || (NR_TASKLETS <= 9 ), \"STACK_SIZE_TASKLET_9  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_10 % 8 == 0) && (STACK_SIZE_TASKLET_10 > 0)) || (NR_TASKLETS <= 10), \"STACK_SIZE_TASKLET_10 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_11 % 8 == 0) && (STACK_SIZE_TASKLET_11 > 0)) || (NR_TASKLETS <= 11), \"STACK_SIZE_TASKLET_11 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_12 % 8 == 0) && (STACK_SIZE_TASKLET_12 > 0)) || (NR_TASKLETS <= 12), \"STACK_SIZE_TASKLET_12 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_13 % 8 == 0) && (STACK_SIZE_TASKLET_13 > 0)) || (NR_TASKLETS <= 13), \"STACK_SIZE_TASKLET_13 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_14 % 8 == 0) && (STACK_SIZE_TASKLET_14 > 0)) || (NR_TASKLETS <= 14), \"STACK_SIZE_TASKLET_14 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_15 % 8 == 0) && (STACK_SIZE_TASKLET_15 > 0)) || (NR_TASKLETS <= 15), \"STACK_SIZE_TASKLET_15 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_16 % 8 == 0) && (STACK_SIZE_TASKLET_16 > 0)) || (NR_TASKLETS <= 16), \"STACK_SIZE_TASKLET_16 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_17 % 8 == 0) && (STACK_SIZE_TASKLET_17 > 0)) || (NR_TASKLETS <= 17), \"STACK_SIZE_TASKLET_17 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_18 % 8 == 0) && (STACK_SIZE_TASKLET_18 > 0)) || (NR_TASKLETS <= 18), \"STACK_SIZE_TASKLET_18 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_19 % 8 == 0) && (STACK_SIZE_TASKLET_19 > 0)) || (NR_TASKLETS <= 19), \"STACK_SIZE_TASKLET_19 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_20 % 8 == 0) && (STACK_SIZE_TASKLET_20 > 0)) || (NR_TASKLETS <= 20), \"STACK_SIZE_TASKLET_20 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_21 % 8 == 0) && (STACK_SIZE_TASKLET_21 > 0)) || (NR_TASKLETS <= 21), \"STACK_SIZE_TASKLET_21 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_22 % 8 == 0) && (STACK_SIZE_TASKLET_22 > 0)) || (NR_TASKLETS <= 22), \"STACK_SIZE_TASKLET_22 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_23 % 8 == 0) && (STACK_SIZE_TASKLET_23 > 0)) || (NR_TASKLETS <= 23), \"STACK_SIZE_TASKLET_23 should be a multiple of 8 and > 0\")\n    ASSERT((NR_TASKLETS > 0 ) || (STACK_SIZE_TASKLET_0  == 0) , \"STACK_SIZE_TASKLET_0  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 1 ) || (STACK_SIZE_TASKLET_1  == 0) , \"STACK_SIZE_TASKLET_1  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 2 ) || (STACK_SIZE_TASKLET_2  == 0) , \"STACK_SIZE_TASKLET_2  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 3 ) || (STACK_SIZE_TASKLET_3  == 0) , \"STACK_SIZE_TASKLET_3  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 4 ) || (STACK_SIZE_TASKLET_4  == 0) , \"STACK_SIZE_TASKLET_4  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 5 ) || (STACK_SIZE_TASKLET_5  == 0) , \"STACK_SIZE_TASKLET_5  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 6 ) || (STACK_SIZE_TASKLET_6  == 0) , \"STACK_SIZE_TASKLET_6  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 7 ) || (STACK_SIZE_TASKLET_7  == 0) , \"STACK_SIZE_TASKLET_7  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 8 ) || (STACK_SIZE_TASKLET_8  == 0) , \"STACK_SIZE_TASKLET_8  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 9 ) || (STACK_SIZE_TASKLET_9  == 0) , \"STACK_SIZE_TASKLET_9  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 10) || (STACK_SIZE_TASKLET_10 == 0) , \"STACK_SIZE_TASKLET_10 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 11) || (STACK_SIZE_TASKLET_11 == 0) , \"STACK_SIZE_TASKLET_11 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 12) || (STACK_SIZE_TASKLET_12 == 0) , \"STACK_SIZE_TASKLET_12 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 13) || (STACK_SIZE_TASKLET_13 == 0) , \"STACK_SIZE_TASKLET_13 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 14) || (STACK_SIZE_TASKLET_14 == 0) , \"STACK_SIZE_TASKLET_14 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 15) || (STACK_SIZE_TASKLET_15 == 0) , \"STACK_SIZE_TASKLET_15 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 16) || (STACK_SIZE_TASKLET_16 == 0) , \"STACK_SIZE_TASKLET_16 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 17) || (STACK_SIZE_TASKLET_17 == 0) , \"STACK_SIZE_TASKLET_17 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 18) || (STACK_SIZE_TASKLET_18 == 0) , \"STACK_SIZE_TASKLET_18 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 19) || (STACK_SIZE_TASKLET_19 == 0) , \"STACK_SIZE_TASKLET_19 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 20) || (STACK_SIZE_TASKLET_20 == 0) , \"STACK_SIZE_TASKLET_20 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 21) || (STACK_SIZE_TASKLET_21 == 0) , \"STACK_SIZE_TASKLET_21 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 22) || (STACK_SIZE_TASKLET_22 == 0) , \"STACK_SIZE_TASKLET_22 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 23) || (STACK_SIZE_TASKLET_23 == 0) , \"STACK_SIZE_TASKLET_23 should be equal to 0 as the tasklet is not active\")\n    . = ALIGN(8);\n    __sys_stack_thread_0  = .;\n    . += STACK_SIZE_TASKLET_0;\n    __sys_stack_thread_1  = .;\n    . += STACK_SIZE_TASKLET_1;\n    __sys_stack_thread_2  = .;\n    . += STACK_SIZE_TASKLET_2;\n    __sys_stack_thread_3  = .;\n    . += STACK_SIZE_TASKLET_3;\n    __sys_stack_thread_4  = .;\n    . += STACK_SIZE_TASKLET_4;\n    __sys_stack_thread_5  = .;\n    . += STACK_SIZE_TASKLET_5;\n    __sys_stack_thread_6  = .;\n    . += STACK_SIZE_TASKLET_6;\n    __sys_stack_thread_7  = .;\n    . += STACK_SIZE_TASKLET_7;\n    __sys_stack_thread_8  = .;\n    . += STACK_SIZE_TASKLET_8;\n    __sys_stack_thread_9  = .;\n    . += STACK_SIZE_TASKLET_9;\n    __sys_stack_thread_10 = .;\n    . += STACK_SIZE_TASKLET_10;\n    __sys_stack_thread_11 = .;\n    . += STACK_SIZE_TASKLET_11;\n    __sys_stack_thread_12 = .;\n    . += STACK_SIZE_TASKLET_12;\n    __sys_stack_thread_13 = .;\n    . += STACK_SIZE_TASKLET_13;\n    __sys_stack_thread_14 = .;\n    . += STACK_SIZE_TASKLET_14;\n    __sys_stack_thread_15 = .;\n    . += STACK_SIZE_TASKLET_15;\n    __sys_stack_thread_16 = .;\n    . += STACK_SIZE_TASKLET_16;\n    __sys_stack_thread_17 = .;\n    . += STACK_SIZE_TASKLET_17;\n    __sys_stack_thread_18 = .;\n    . += STACK_SIZE_TASKLET_18;\n    __sys_stack_thread_19 = .;\n    . += STACK_SIZE_TASKLET_19;\n    __sys_stack_thread_20 = .;\n    . += STACK_SIZE_TASKLET_20;\n    __sys_stack_thread_21 = .;\n    . += STACK_SIZE_TASKLET_21;\n    __sys_stack_thread_22 = .;\n    . += STACK_SIZE_TASKLET_22;\n    __sys_stack_thread_23 = .;\n    . += STACK_SIZE_TASKLET_23;\n    . = ALIGN(8);\n  } > wram\n\n\n  .data.sw_cache (NOLOAD): {\n    . = ALIGN(8);\n    __sw_cache_buffer = .;\n    . += 8 * NR_TASKLETS;\n  } > wram\n\n  .data.heap_pointer_reset (NOLOAD) : {\n    /* Start of heap: must be aligned on DMA size.\n     * Stored as a symbol \"__reset_heap_pointer\", so that\n     * the bootstrap just moves the value into a register to\n     * initialize heap pointer at each reboot.\n     */\n    . = ALIGN(8);\n    PROVIDE(__sys_heap_pointer_reset = .);\n  } > wram\n\n  .mram.noinit (NOLOAD) : {\n    *(.mram.noinit .mram.noinit.*)\n    KEEP(*(.mram.noinit.keep .mram.noinit.keep.*))\n  } > mram\n\n  .mram : {\n    *(.mram .mram.*)\n    KEEP(*(.mram.keep .mram.keep.*))\n    . = ALIGN(8);\n    __sys_used_mram_end = .;\n  } > mram\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/internalStateReset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The strict minimum to reset the internal state of the DPU (that can only be changed by a DPU program).\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sub r0, \" __STR(NR_ATOMIC_BITS) \" - 1, id\\n\"\n        \"before_release:\\n\"\n        // Resetting Atomic bits\n        \"  release r0, 0, nz, after_release\\n\"\n        \"after_release:\\n\"\n        \"  sub r0, r0, \" __STR(NR_THREADS) \", pl, before_release\\n\"\n        // Resetting Zero and Carry flags + Preparing configuration for perfcounter register\n        \"  add r0, zero, 7\\n\"\n        // Resetting Performance Counter\n        \"  time_cfg zero, r0\\n\"\n        // Resetting Pc\n        \"  stop true, 0\\n\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/linkerScript.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Simple linker script for embedded programs.\n */\nENTRY(__bootstrap)\nMEMORY {\n\tiram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text)\n  } > iram\n}\n\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/restoreRegisters.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"restore registers\" program, is used by debugging processes to restore every registers of every runtime.\n * The program should be booted once on runtime 0.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d2,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1)\\n\"\n        \"  ld d4,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2)\\n\"\n        \"  ld d6,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3)\\n\"\n        \"  ld d8,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4)\\n\"\n        \"  ld d10, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5)\\n\"\n        \"  ld d12, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6)\\n\"\n        \"  ld d14, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7)\\n\"\n        \"  ld d16, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8)\\n\"\n        \"  ld d18, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9)\\n\"\n        \"  ld d20, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10)\\n\"\n        \"  ld d22, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11)\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  lbu r1, r0, 0\\n\"\n        \"  jz r1, atomic_release\\n\"\n        \"  acquire r0, 0, true, atomic_next\\n\"\n        \"atomic_release:\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/misc/restore_carry_and_zero_flag.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"macro_utils.h\"\n\n/* clang-format off */\n#define __RESTORE_CARRY_AND_ZERO_FLAG(x) \\\n        \"add r0, zero, 0x00000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 0 */ \\\n        \"add r0, mneg, 0x80000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 1 */ \\\n        \"add r0, zero, 0x00000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 1, C = 0 */ \\\n        \"add r0, mneg, 0x80000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" // ... restore Z = 1, C = 1 */\n\n#define RESTORE_CARRY_AND_ZERO_FLAG \\\n        \"  lw r0,  id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12)\\n\" \\\n        \"  add r1, r0,  r0\\n\" \\\n        \"  add r0, r0,  r1\\n\" /* r0 =  3 * r0 (each line of ending_routines is 3 instructions) */ \\\n        \"  or  r1, id8, 0 \\n\" \\\n        \"  add r1, id4, r1\\n\" /* r1 = 12 * id (there are 12 instructions per runtime in ending_routines) */ \\\n        \"  add r0, r0,  r1\\n\" /* r0 = r0 + r1 (compute the offset (in number of instructions) to jump to) */ \\\n        \"  call zero, r0, ending_routines\\n\" \\\n        \"ending_routines:\\n\" \\\n        __FOR_EACH_THREAD(__RESTORE_CARRY_AND_ZERO_FLAG)\n\n/* clang-format on */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(stdlib ${SRCS})\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/abort.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n\nvoid\nabort()\n{\n    halt();\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/assert.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ASSERT_H_\n#define _DPUSYSCORE_ASSERT_H_\n\n/**\n * @file assert.h\n * @brief Provides a way to verify assumptions with <code>assert</code>.\n */\n\n#define static_assert _Static_assert\n\n#ifdef NDEBUG\n\n/**\n * @def assert\n * @hideinitializer\n * @brief When NDEBUG is defined, <code>assert</code> is not available and calling it will do nothing.\n */\n#define assert(ignore) ((void)0)\n\n#else\n\n#include <dpufault.h>\n#include <macro_utils.h>\n\n/**\n * @def assert\n * @hideinitializer\n * @brief Verify the assumption of the specified expression, resulting in a fault if it fails.\n *\n * @param expression the assumption to verify\n * @throws FAULT_ASSERT_FAILED when the assertion failed\n * @todo add a diagnostic message to the log, if it exists, when the assertion fails\n */\n#define assert(expression)                                                                                                       \\\n    do {                                                                                                                         \\\n        if (!(expression)) {                                                                                                     \\\n            __asm__ volatile(\"fault \" __STR(__FAULT_ASSERT_FAILED__));                                                           \\\n        }                                                                                                                        \\\n    } while (0)\n\n#endif /* NDEBUG */\n\n#endif /* _DPUSYSCORE_ASSERT_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/atoi.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nint\natoi(const char *nptr)\n{\n    int result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/atol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nlong\natol(const char *nptr)\n{\n    long result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/ctype.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_CTYPE_H_\n#define _DPUSYSCORE_CTYPE_H_\n\n/**\n * @file ctype.h\n * @brief Provides useful functions for testing and mapping characters.\n */\n\n/**\n * @brief Checks whether the specified character is a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisdigit(int c)\n{\n    return (c >= '0') && (c <= '9');\n}\n\n/**\n * @brief Checks whether the specified character is a lowercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int islower(c) { return (c >= 'a') && (c <= 'z'); }\n\n/**\n * @brief Checks whether the specified character is an uppercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is an uppercase letter (using 0 as false and anything else as true).\n */\nstatic inline int isupper(c) { return (c >= 'A') && (c <= 'Z'); }\n\n/**\n * @brief Checks whether the specified character is a letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter (using 0 as false and anything else as true).\n */\nstatic inline int\nisalpha(int c)\n{\n    return islower(c) || isupper(c);\n}\n\n/**\n * @brief Checks whether the specified character is a letter or a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter or a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisalnum(int c)\n{\n    return isalpha(c) || isdigit(c);\n}\n\n/**\n * @brief Checks whether the specified character is a control character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a control character (using 0 as false and anything else as true).\n */\nstatic inline int\niscntrl(int c)\n{\n    return (c <= 0x1f) || (c == 0x7f);\n}\n\n/**\n * @brief Checks whether the specified character is printable.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is printable (using 0 as false and anything else as true).\n */\nstatic inline int\nisprint(int c)\n{\n    return !iscntrl(c);\n}\n\n/**\n * @brief Checks whether the specified character has graphical representation using locale.\n\n * @param c an unsigned char or EOF\n * @return Whether the character has graphical representation using locale (using 0 as false and anything else as true).\n */\nstatic inline int\nisgraph(int c)\n{\n    return isprint(c) && (c != ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a punctuation character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a punctuation character (using 0 as false and anything else as true).\n */\nstatic inline int\nispunct(int c)\n{\n    return (c >= '!' && c <= '/') || (c >= ':' && c <= '@') || (c >= '[' && c <= '`') || (c >= '{' && c <= '~');\n}\n\n/**\n * @brief Checks whether the specified character is a white-space.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a white-space (using 0 as false and anything else as true).\n */\nstatic inline int\nisspace(int c)\n{\n    return (c >= 0x9 && c <= 0xd) || (c == ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a hexadecimal digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a hexadecimal digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisxdigit(int c)\n{\n    return isdigit(c) || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f');\n}\n\n/**\n * @brief Checks whether the specified character is a blank character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a blank character (using 0 as false and anything else as true).\n */\nstatic inline int\nisblank(int c)\n{\n    return c == ' ' || c == '\\t';\n}\n\n/**\n * @brief Converts the specified character to a lowercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The lowercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntolower(int c)\n{\n    return isupper(c) ? (c + 0x20) : c;\n}\n\n/**\n * @brief Converts the specified character to a uppercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The uppercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntoupper(int c)\n{\n    return islower(c) ? (c - 0x20) : c;\n}\n\n#endif /* _DPUSYSCORE_CTYPE_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/errno.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nint __errno[NR_THREADS];\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/errno.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ERRNO_H_\n#define _DPUSYSCORE_ERRNO_H_\n\n#include <defs.h>\n\n/**\n * @file errno.h\n * @brief Defines the system error numbers.\n */\n\n// errno is an array indexed on the tasklet id rather than\n// a single integer.\nextern int __errno[];\n\n// Mimic errno variable as an index to __errno.\n// Defined in such a way that users can't override errno.\n#define errno (*(__errno + me()))\n\n/**\n * @def E2BIG\n * @brief  Argument list too long.\n */\n#define E2BIG 1\n/**\n * @def EACCES\n * @brief  Permission denied.\n */\n#define EACCES 2\n/**\n * @def EADDRINUSE\n * @brief  Address in use.\n */\n#define EADDRINUSE 3\n/**\n * @def EADDRNOTAVAIL\n * @brief  Address not available.\n */\n#define EADDRNOTAVAIL 4\n/**\n * @def EAFNOSUPPORT\n * @brief  Address family not supported.\n */\n#define EAFNOSUPPORT 5\n/**\n * @def EAGAIN\n * @brief  Resource unavailable, try again.\n */\n#define EAGAIN 6\n/**\n * @def EALREADY\n * @brief  Connection already in progress.\n */\n#define EALREADY 7\n/**\n * @def EBADF\n * @brief  Bad file descriptor.\n */\n#define EBADF 8\n/**\n * @def EBADMSG\n * @brief  Bad message.\n */\n#define EBADMSG 9\n/**\n * @def EBUSY\n * @brief  Device or resource busy.\n */\n#define EBUSY 10\n/**\n * @def ECANCELED\n * @brief  Operation canceled.\n */\n#define ECANCELED 11\n/**\n * @def ECHILD\n * @brief  No child processes.\n */\n#define ECHILD 12\n/**\n * @def ECONNABORTED\n * @brief  Connection aborted.\n */\n#define ECONNABORTED 13\n/**\n * @def ECONNREFUSED\n * @brief  Connection refused.\n */\n#define ECONNREFUSED 14\n/**\n * @def ECONNRESET\n * @brief  Connection reset.\n */\n#define ECONNRESET 15\n/**\n * @def EDEADLK\n * @brief  Resource deadlock would occur.\n */\n#define EDEADLK 16\n/**\n * @def EDESTADDRREQ\n * @brief  Destination address required.\n */\n#define EDESTADDRREQ 17\n/**\n * @def EDOM\n * @brief  Mathematics argument out of domain of function.\n */\n#define EDOM 18\n/**\n * @def EDQUOT\n * @brief  Reserved.\n */\n#define EDQUOT 19\n/**\n * @def EEXIST\n * @brief  File exists.\n */\n#define EEXIST 20\n/**\n * @def EFAULT\n * @brief  Bad address.\n */\n#define EFAULT 21\n/**\n * @def EFBIG\n * @brief  File too large.\n */\n#define EFBIG 22\n/**\n * @def EHOSTUNREACH\n * @brief  Host is unreachable.\n */\n#define EHOSTUNREACH 23\n/**\n * @def EIDRM\n * @brief  Identifier removed.\n */\n#define EIDRM 24\n/**\n * @def EILSEQ\n * @brief  Illegal byte sequence.\n */\n#define EILSEQ 25\n/**\n * @def EINPROGRESS\n * @brief  Operation in progress.\n */\n#define EINPROGRESS 26\n/**\n * @def EINTR\n * @brief  Interrupted function.\n */\n#define EINTR 27\n/**\n * @def EINVAL\n * @brief  Invalid argument.\n */\n#define EINVAL 28\n/**\n * @def EIO\n * @brief  I/O error.\n */\n#define EIO 29\n/**\n * @def EISCONN\n * @brief  Socket is connected.\n */\n#define EISCONN 30\n/**\n * @def EISDIR\n * @brief  Is a directory.\n */\n#define EISDIR 31\n/**\n * @def ELOOP\n * @brief  Too many levels of symbolic links.\n */\n#define ELOOP 32\n/**\n * @def EMFILE\n * @brief  File descriptor value too large.\n */\n#define EMFILE 33\n/**\n * @def EMLINK\n * @brief  Too many links.\n */\n#define EMLINK 34\n/**\n * @def EMSGSIZE\n * @brief  Message too large.\n */\n#define EMSGSIZE 35\n/**\n * @def EMULTIHOP\n * @brief  Reserved.\n */\n#define EMULTIHOP 36\n/**\n * @def ENAMETOOLONG\n * @brief  Filename too long.\n */\n#define ENAMETOOLONG 37\n/**\n * @def ENETDOWN\n * @brief  Network is down.\n */\n#define ENETDOWN 38\n/**\n * @def ENETRESET\n * @brief  Connection aborted by network.\n */\n#define ENETRESET 39\n/**\n * @def ENETUNREACH\n * @brief  Network unreachable.\n */\n#define ENETUNREACH 40\n/**\n * @def ENFILE\n * @brief  Too many files open in system.\n */\n#define ENFILE 41\n/**\n * @def ENOBUFS\n * @brief  No buffer space available.\n */\n#define ENOBUFS 42\n/**\n * @def ENODATA\n * @brief  No message is available on the STREAM head read queue.\n */\n#define ENODATA 43\n/**\n * @def ENODEV\n * @brief  No such device.\n */\n#define ENODEV 44\n/**\n * @def ENOENT\n * @brief  No such file or directory.\n */\n#define ENOENT 45\n/**\n * @def ENOEXEC\n * @brief  Executable file format error.\n */\n#define ENOEXEC 46\n/**\n * @def ENOLCK\n * @brief  No locks available.\n */\n#define ENOLCK 47\n/**\n * @def ENOLINK\n * @brief  Reserved.\n */\n#define ENOLINK 48\n/**\n * @def ENOMEM\n * @brief  Not enough space.\n */\n#define ENOMEM 49\n/**\n * @def ENOMSG\n * @brief  No message of the desired type.\n */\n#define ENOMSG 50\n/**\n * @def ENOPROTOOPT\n * @brief  Protocol not available.\n */\n#define ENOPROTOOPT 51\n/**\n * @def ENOSPC\n * @brief  No space left on device.\n */\n#define ENOSPC 52\n/**\n * @def ENOSR\n * @brief  No STREAM resources.\n */\n#define ENOSR 53\n/**\n * @def ENOSTR\n * @brief  Not a STREAM.\n */\n#define ENOSTR 54\n/**\n * @def ENOSYS\n * @brief  Function not supported.\n */\n#define ENOSYS 55\n/**\n * @def ENOTCONN\n * @brief  The socket is not connected.\n */\n#define ENOTCONN 56\n/**\n * @def ENOTDIR\n * @brief  Not a directory or a symbolic link to a directory.\n */\n#define ENOTDIR 57\n/**\n * @def ENOTEMPTY\n * @brief  Directory not empty.\n */\n#define ENOTEMPTY 58\n/**\n * @def ENOTRECOVERABLE\n * @brief  State not recoverable.\n */\n#define ENOTRECOVERABLE 59\n/**\n * @def ENOTSOCK\n * @brief  Not a socket.\n */\n#define ENOTSOCK 60\n/**\n * @def ENOTSUP\n * @brief  Not supported.\n */\n#define ENOTSUP 61\n/**\n * @def ENOTTY\n * @brief  Inappropriate I/O control operation.\n */\n#define ENOTTY 62\n/**\n * @def ENXIO\n * @brief  No such device or address.\n */\n#define ENXIO 63\n/**\n * @def EOPNOTSUPP\n * @brief  Operation not supported on socket.\n */\n#define EOPNOTSUPP ENOTSUP\n/**\n * @def EOVERFLOW\n * @brief  Value too large to be stored in data type.\n */\n#define EOVERFLOW 65\n/**\n * @def EOWNERDEAD\n * @brief  Previous owner died.\n */\n#define EOWNERDEAD 66\n/**\n * @def EPERM\n * @brief  Operation not permitted.\n */\n#define EPERM 67\n/**\n * @def EPIPE\n * @brief  Broken pipe.\n */\n#define EPIPE 68\n/**\n * @def EPROTO\n * @brief  Protocol error.\n */\n#define EPROTO 69\n/**\n * @def EPROTONOSUPPORT\n * @brief  Protocol not supported.\n */\n#define EPROTONOSUPPORT 70\n/**\n * @def EPROTOTYPE\n * @brief  Protocol wrong type for socket.\n */\n#define EPROTOTYPE 71\n/**\n * @def ERANGE\n * @brief  Result too large.\n */\n#define ERANGE 72\n/**\n * @def EROFS\n * @brief  Read-only file system.\n */\n#define EROFS 73\n/**\n * @def ESPIPE\n * @brief  Invalid seek.\n */\n#define ESPIPE 74\n/**\n * @def ESRCH\n * @brief  No such process.\n */\n#define ESRCH 75\n/**\n * @def ESTALE\n * @brief  Reserved.\n */\n#define ESTALE 76\n/**\n * @def ETIME\n * @brief  Stream ioctl() timeout.\n */\n#define ETIME 77\n/**\n * @def ETIMEDOUT\n * @brief  Connection timed out.\n */\n#define ETIMEDOUT 78\n/**\n * @def ETXTBSY\n * @brief  Text file busy.\n */\n#define ETXTBSY 79\n/**\n * @def EWOULDBLOCK\n * @brief  Operation would block.\n */\n#define EWOULDBLOCK ENOTSUP\n/**\n * @def EXDEV\n * @brief  Cross-device link.\n */\n#define EXDEV 81\n\n#endif /* _DPUSYSCORE_ERRNO_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/exit.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include \"defs.h\"\n#include \"stdlib.h\"\n\n#define unreachable() __builtin_unreachable()\n\nvoid\nexit(int __attribute__((unused)) status)\n{\n    __asm__ volatile(\"stop true, __sys_end\");\n    unreachable();\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/inttypes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_INTTYPES_H_\n#define _DPUSYSCORE_INTTYPES_H_\n\n/**\n * @file inttypes.h\n * @brief Extends stdint.h.\n */\n\n#include <stdint.h>\n\ntypedef struct {\n    intmax_t quot;\n    intmax_t rem;\n} imaxdiv_t;\n\nstatic inline intmax_t\nimaxabs(intmax_t x)\n{\n    return (x < 0) ? -x : x;\n}\n\nstatic inline imaxdiv_t\nimaxdiv(intmax_t numer, intmax_t denom)\n{\n    imaxdiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/* Macros for printing format specifiers.  */\n\n/* Decimal notation.  */\n#define PRId8 \"d\"\n#define PRId16 \"d\"\n#define PRId32 \"d\"\n#define PRId64 \"ld\"\n\n#define PRIdLEAST8 \"d\"\n#define PRIdLEAST16 \"d\"\n#define PRIdLEAST32 \"d\"\n#define PRIdLEAST64 \"ld\"\n\n#define PRIdFAST8 \"d\"\n#define PRIdFAST16 \"d\"\n#define PRIdFAST32 \"d\"\n#define PRIdFAST64 \"ld\"\n\n#define PRIi8 \"i\"\n#define PRIi16 \"i\"\n#define PRIi32 \"i\"\n#define PRIi64 \"li\"\n\n#define PRIiLEAST8 \"i\"\n#define PRIiLEAST16 \"i\"\n#define PRIiLEAST32 \"i\"\n#define PRIiLEAST64 \"li\"\n\n#define PRIiFAST8 \"i\"\n#define PRIiFAST16 \"i\"\n#define PRIiFAST32 \"i\"\n#define PRIiFAST64 \"li\"\n\n/* Octal notation.  */\n#define PRIo8 \"o\"\n#define PRIo16 \"o\"\n#define PRIo32 \"o\"\n#define PRIo64 \"lo\"\n\n#define PRIoLEAST8 \"o\"\n#define PRIoLEAST16 \"o\"\n#define PRIoLEAST32 \"o\"\n#define PRIoLEAST64 \"lo\"\n\n#define PRIoFAST8 \"o\"\n#define PRIoFAST16 \"o\"\n#define PRIoFAST32 \"o\"\n#define PRIoFAST64 \"lo\"\n\n/* Unsigned integers.  */\n#define PRIu8 \"u\"\n#define PRIu16 \"u\"\n#define PRIu32 \"u\"\n#define PRIu64 \"lu\"\n\n#define PRIuLEAST8 \"u\"\n#define PRIuLEAST16 \"u\"\n#define PRIuLEAST32 \"u\"\n#define PRIuLEAST64 \"lu\"\n\n#define PRIuFAST8 \"u\"\n#define PRIuFAST16 \"u\"\n#define PRIuFAST32 \"u\"\n#define PRIuFAST64 \"lu\"\n\n/* lowercase hexadecimal notation.  */\n#define PRIx8 \"x\"\n#define PRIx16 \"x\"\n#define PRIx32 \"x\"\n#define PRIx64 \"lx\"\n\n#define PRIxLEAST8 \"x\"\n#define PRIxLEAST16 \"x\"\n#define PRIxLEAST32 \"x\"\n#define PRIxLEAST64 \"lx\"\n\n#define PRIxFAST8 \"x\"\n#define PRIxFAST16 \"x\"\n#define PRIxFAST32 \"x\"\n#define PRIxFAST64 \"lx\"\n\n/* UPPERCASE hexadecimal notation.  */\n#define PRIX8 \"X\"\n#define PRIX16 \"X\"\n#define PRIX32 \"X\"\n#define PRIX64 \"lX\"\n\n#define PRIXLEAST8 \"X\"\n#define PRIXLEAST16 \"X\"\n#define PRIXLEAST32 \"X\"\n#define PRIXLEAST64 \"lX\"\n\n#define PRIXFAST8 \"X\"\n#define PRIXFAST16 \"X\"\n#define PRIXFAST32 \"X\"\n#define PRIXFAST64 \"lX\"\n\n/* Macros for printing `intmax_t' and `uintmax_t'.  */\n#define PRIdMAX \"ld\"\n#define PRIiMAX \"li\"\n#define PRIoMAX \"lo\"\n#define PRIuMAX \"lu\"\n#define PRIxMAX \"lx\"\n#define PRIXMAX \"lX\"\n\n/* Macros for printing `intptr_t' and `uintptr_t'.  */\n#define PRIdPTR \"d\"\n#define PRIiPTR \"i\"\n#define PRIoPTR \"o\"\n#define PRIuPTR \"u\"\n#define PRIxPTR \"x\"\n#define PRIXPTR \"X\"\n\n#endif /* _DPUSYSCORE_INTTYPES_H_ */"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/iso646.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ISO646_H_\n#define _DPUSYSCORE_ISO646_H_\n\n/**\n * @file iso646.h\n * @brief Alternative spellings for operators not supported by the ISO646 standard character set.\n */\n\n/**\n * @def and\n * @brief Logical AND.\n */\n#define and &&\n/**\n * @def and_eq\n * @brief Bitwise AND accumulation.\n */\n#define and_eq &=\n/**\n * @def bitand\n * @brief Bitwise AND.\n */\n#define bitand &\n/**\n * @def bitor\n * @brief Bitwise OR.\n */\n#define bitor |\n/**\n * @def compl\n * @brief Bitwise NOT.\n */\n#define compl ~\n/**\n * @def not\n * @brief Logical NOT.\n */\n#define not !\n/**\n * @def not_eq\n * @brief Difference.\n */\n#define not_eq !=\n/**\n * @def or\n * @brief Logical OR.\n */\n#define or ||\n/**\n * @def or_eq\n * @brief Bitwise OR accumulation.\n */\n#define or_eq |=\n/**\n * @def xor\n * @brief Bitwise XOR.\n */\n#define xor ^\n/**\n * @def xor_eq\n * @brief Bitwise XOR accumulation.\n */\n#define xor_eq ^=\n\n#endif /* _DPUSYSCORE_ISO646_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/limits.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_LIMITS_H_\n#define _DPUSYSCORE_LIMITS_H_\n\n#define SCHAR_MAX (0x0000007f)\n#define SHRT_MAX (0x00007fff)\n#define INT_MAX (0x7fffffff)\n#define LONG_MAX (0x7fffffffffffffffl)\n#define LLONG_MAX (0x7fffffffffffffffl)\n\n#define SCHAR_MIN (-SCHAR_MAX - 1)\n#define SHRT_MIN (-SHRT_MAX - 1)\n#define INT_MIN (-INT_MAX - 1)\n#define LONG_MIN (-LONG_MAX - 1)\n#define LLONG_MIN (-LLONG_MAX - 1)\n\n#define UCHAR_MAX (SCHAR_MAX * 2 + 1)\n#define USHRT_MAX (SHRT_MAX * 2 + 1)\n#define UINT_MAX (INT_MAX * 2U + 1U)\n#define ULONG_MAX (LONG_MAX * 2UL + 1UL)\n#define ULLONG_MAX (LLONG_MAX * 2UL + 1UL)\n\n#ifdef __CHAR_UNSIGNED__ /* -funsigned-char */\n#define CHAR_MIN 0\n#define CHAR_MAX UCHAR_MAX\n#else\n#define CHAR_MIN SCHAR_MIN\n#define CHAR_MAX SCHAR_MAX\n#endif\n\n/* The maximum number of bytes in a multi-byte character.  */\n#define MB_LEN_MAX 16\n\n/* Limits of integral types */\n\n/**\n * @def CHAR_BIT\n * @hideinitializer\n * @brief The number of bits in a char type.\n */\n#define CHAR_BIT (8)\n\n/**\n * @def WORD_BIT\n * @hideinitializer\n * @brief The number of bits in a word type.\n */\n#define WORD_BIT (32)\n\n/**\n * @def LONG_BIT\n * @hideinitializer\n * @brief The number of bits in a pseudo-long type.\n */\n#define LONG_BIT (32)\n\n/* Minimum of signed integral types */\n\n/**\n * @def INT8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MIN (-0x7f - 1)\n\n/**\n * @def INT16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MIN (-0x7fff - 1)\n\n/**\n * @def INT32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MIN (-0x7fffffff - 1)\n\n/**\n * @def INT64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types */\n\n/**\n * @def INT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MAX (0x7f)\n/**\n * @def INT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MAX (0x7fff)\n/**\n * @def INT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MAX (0x7fffffff)\n/**\n * @def INT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types */\n\n/**\n * @def UINT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint8_t</code>.\n */\n#define UINT8_MAX (0xff)\n/**\n * @def UINT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint16_t</code>.\n */\n#define UINT16_MAX (0xffff)\n/**\n * @def UINT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint32_t</code>.\n */\n#define UINT32_MAX (0xffffffff)\n/**\n * @def UINT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint64_t</code>.\n */\n#define UINT64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MIN (-0x7f - 1)\n/**\n * @def INT_LEAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MIN (-0x7fff - 1)\n/**\n * @def INT_LEAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_LEAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MAX (0x7f)\n/**\n * @def INT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MAX (0x7fff)\n/**\n * @def INT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MAX (0x7fffffff)\n/**\n * @def INT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types having a minimum size */\n\n/**\n * @def UINT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least8_t</code>.\n */\n#define UINT_LEAST8_MAX (0xff)\n/**\n * @def UINT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least16_t</code>.\n */\n#define UINT_LEAST16_MAX (0xffff)\n/**\n * @def UINT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least32_t</code>.\n */\n#define UINT_LEAST32_MAX (0xffffffff)\n/**\n * @def UINT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least64_t</code>.\n */\n#define UINT_LEAST64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MIN (-0x7f - 1)\n/**\n * @def INT_FAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MAX (0x7f)\n/**\n * @def INT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MAX (0x7fffffff)\n/**\n * @def INT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MAX (0x7fffffff)\n/**\n * @def INT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of fast unsigned integral types having a minimum size */\n\n/**\n * @def UINT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast8_t</code>.\n */\n#define UINT_FAST8_MAX (0xff)\n/**\n * @def UINT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast16_t</code>.\n */\n#define UINT_FAST16_MAX (0xffffffffU)\n/**\n * @def UINT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast32_t</code>.\n */\n#define UINT_FAST32_MAX (0xffffffffU)\n/**\n * @def UINT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast64_t</code>.\n */\n#define UINT_FAST64_MAX (0xffffffffffffffffUL)\n\n/* Limits for integral types holding void* pointers */\n\n/**\n * @def INTPTR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MIN (-0x7fffffff - 1)\n/**\n * @def INTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MAX (0x7fffffff)\n/**\n * @def UINTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintptr_t</code>.\n */\n#define UINTPTR_MAX (0xffffffffU)\n\n/* Limits of greatest-width integer types */\n\n/**\n * @def INTMAX_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MIN (-0x7fffffffffffffffLL - 1)\n/**\n * @def INTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MAX (0x7fffffffffffffffLL)\n/**\n * @def UINTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintmax_t</code>.\n */\n#define UINTMAX_MAX (0xffffffffffffffffULL)\n\n/* Limits of others integer types */\n\n/**\n * @def PTRDIFF_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MIN (-0x7fffffff - 1)\n/**\n * @def PTRDIFF_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MAX (0x7fffffff)\n\n/**\n * @def SIZE_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>size_t</code>.\n * @see size_t\n */\n#define SIZE_MAX (0xffffffffU)\n\n/**\n * @def WCHAR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MIN (-0x7fffffff - 1)\n/**\n * @def WCHAR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MAX (0x7fffffff)\n\n/**\n * @def WINT_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MIN (0u)\n/**\n * @def WINT_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MAX (0xffffffffu)\n\n/* Macros for integer constant expressions */\n\n/* Signed */\n\n/**\n * @def INT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least8_t</code>\n */\n#define INT8_C(value) value\n/**\n * @def INT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least16_t</code>\n */\n#define INT16_C(value) value\n/**\n * @def INT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least32_t</code>\n */\n#define INT32_C(value) value\n/**\n * @def INT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least64_t</code>\n */\n#define INT64_C(value) value##LL\n\n/* Unsigned */\n\n/**\n * @def UINT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least8_t</code>\n */\n#define UINT8_C(value) value##U\n/**\n * @def UINT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least16_t</code>\n */\n#define UINT16_C(value) value##U\n/**\n * @def UINT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least32_t</code>\n */\n#define UINT32_C(value) value##U\n/**\n * @def UINT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least64_t</code>\n */\n#define UINT64_C(value) value##ULL\n\n/* Maximum types */\n\n/**\n * @def INTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>intmax_t</code>\n */\n#define INTMAX_C(value) value##LL\n/**\n * @def UINTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uintmax_t</code>\n */\n#define UINTMAX_C(value) value##ULL\n\n#endif /* _DPUSYSCORE_LIMITS_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nvoid *\nmemchr(const void *area, int character, size_t size)\n{\n    const char *ptr = (const char *)area;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        if (ptr[each_byte] == character) {\n            return (void *)(ptr + each_byte);\n        }\n    }\n\n    return NULL;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nint\nmemcmp(const void *area1, const void *area2, size_t size)\n{\n    const unsigned char *ptr1 = (const unsigned char *)area1;\n    const unsigned char *ptr2 = (const unsigned char *)area2;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        int diff = ptr1[each_byte] - ptr2[each_byte];\n        if (diff != 0) {\n            return diff;\n        }\n    }\n\n    return 0;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\n__attribute__((used)) void *\n__memcpy_wram_4align(void *dest, const void *src, size_t len)\n{\n    uint32_t *dw = (uint32_t *)dest;\n    uint32_t *sw = (uint32_t *)src;\n\n    for (uint32_t i = 0; i < (len / sizeof(uint32_t)); ++i) {\n        dw[i] = sw[i];\n    }\n    return dest;\n}\n\nvoid *\nmemcpy(void *dest, const void *src, size_t len)\n{\n    uint8_t *d = (uint8_t *)dest;\n    const uint8_t *s = (const uint8_t *)src;\n    uint32_t *dw;\n    const uint32_t *sw;\n    uint8_t *head;\n    uint8_t *const tail = (uint8_t *)dest + len;\n    /* Set 'body' to the last word boundary */\n    uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);\n\n    if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n        /* Misaligned. no body, no tail. */\n        head = tail;\n    } else {\n        /* Aligned */\n        if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))\n            /* len is shorter than the first word boundary */\n            head = tail;\n        else\n            /* Set 'head' to the first word boundary */\n            head = (uint8_t *)(((uintptr_t)d + 3) & ~3);\n    }\n\n    /* Copy head */\n    uint32_t head_len = head - d;\n    if (head_len != 0) {\n        for (uint32_t i = 0; i < head_len; ++i)\n            d[i] = s[i];\n    }\n\n    /* Copy body */\n    dw = (uint32_t *)(d + head_len);\n    sw = (uint32_t *)(s + head_len);\n\n    uint32_t body_len = (body < dw) ? 0 : body - dw;\n    if (body_len != 0) {\n        __memcpy_wram_4align(dw, sw, body_len * sizeof(uint32_t));\n    }\n\n    /* Copy tail */\n    d = (uint8_t *)(dw + body_len);\n    s = (const uint8_t *)(sw + body_len);\n    uint32_t tail_len = tail - d;\n    if (tail_len != 0) {\n        for (uint32_t i = 0; i < tail_len; ++i)\n            d[i] = s[i];\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mw(__mram_ptr void *dest, const void *src, size_t len)\n{\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n\n    if (destOff != 0) {\n        size_t part = MIN(remaining, MRAM_CACHE_SIZE - destOff);\n        mram_read(dest, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache + destOff, src, part);\n        mram_write(destCache, dest, MRAM_CACHE_SIZE);\n        remaining -= part;\n        idx += part;\n    }\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_write(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            memcpy(destCache, src + idx, MRAM_CACHE_SIZE);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache, src + idx, remaining);\n        mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) void *\n__memcpy_wm(void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n    size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n\n    mram_read(src, srcCache, MRAM_CACHE_SIZE);\n    memcpy(dest, srcCache + srcOff, part);\n    remaining -= part;\n    idx += part;\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(dest + idx, srcCache, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n        memcpy(dest + idx, srcCache, remaining);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mm(__mram_ptr void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    if (srcOff == destOff) {\n        uint32_t idx = 0;\n\n        if (destOff != 0) {\n            size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, part);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            remaining -= part;\n            idx += part;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            mram_write(srcCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache, srcCache, remaining);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n        }\n    } else {\n        uint32_t srcIdx = 0;\n        uint32_t destIdx = 0;\n        size_t initLen = MIN(remaining, MRAM_CACHE_SIZE - MIN(destOff, srcOff));\n\n        if (initLen == remaining) {\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, remaining);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            return dest;\n        }\n\n        mram_read(src, srcCache, MRAM_CACHE_SIZE);\n        srcIdx += MRAM_CACHE_SIZE;\n\n        if (destOff != 0) {\n            mram_read(dest, destCache, DMA_ALIGNED(destOff));\n\n            if (destOff > srcOff) {\n                size_t part = MRAM_CACHE_SIZE - destOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n\n                srcOff += part;\n            } else {\n                size_t part = MRAM_CACHE_SIZE - srcOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx += MRAM_CACHE_SIZE;\n\n                size_t part2 = srcOff - destOff;\n                memcpy(destCache + destOff + part, srcCache, part2);\n\n                srcOff = part2;\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            destIdx += MRAM_CACHE_SIZE;\n            remaining -= MRAM_CACHE_SIZE - destOff;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n            mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx += MRAM_CACHE_SIZE;\n\n            size_t part2 = srcOff;\n            memcpy(destCache + part, srcCache, part2);\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            destIdx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + destIdx, destCache, MRAM_CACHE_SIZE);\n\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n\n            if (remaining > part) {\n                size_t part2 = remaining - part;\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + part, srcCache, part2);\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n        }\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memmove.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <string.h>\n#include <stdint.h>\n\nvoid *\nmemmove(void *dest, const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return memcpy(dest, src, len);\n    } else {\n        /* Need to copy from tail because there is overlap. */\n        char *d = (char *)dest + len;\n        const char *s = (const char *)src + len;\n        uint32_t *dw;\n        const uint32_t *sw;\n        char *head;\n        char *const tail = (char *)dest;\n        /* Set 'body' to the last word boundary */\n        uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3);\n\n        if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n            /* Misaligned. no body, no tail. */\n            head = tail;\n        } else {\n            /* Aligned */\n            if ((uintptr_t)tail > ((uintptr_t)d & ~3))\n                /* Shorter than the first word boundary */\n                head = tail;\n            else\n                /* Set 'head' to the first word boundary */\n                head = (char *)((uintptr_t)d & ~3);\n        }\n\n        /* Copy head */\n        uint32_t head_len = d - head;\n        for (int32_t i = head_len - 1; i >= 0; --i)\n            d[i - head_len] = s[i - head_len];\n\n        /* Copy body */\n        dw = (uint32_t *)(d - head_len);\n        sw = (uint32_t *)(s - head_len);\n\n        uint32_t body_len = (dw < body) ? 0 : dw - body;\n        for (int32_t i = body_len - 1; i >= 0; --i)\n            dw[i - body_len] = sw[i - body_len];\n\n        /* Copy tail */\n        d = (char *)(dw - body_len);\n        s = (const char *)(sw - body_len);\n\n        uint32_t tail_len = d - tail;\n        for (int32_t i = tail_len - 1; i >= 0; --i)\n            d[i - tail_len] = s[i - tail_len];\n\n        return dest;\n    }\n}\n\n__mram_ptr void *\n__memmove_mm(__mram_ptr void *dest, __mram_ptr const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return (__mram_ptr void *)memcpy(dest, src, len);\n    } else {\n        uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        void *srcCache = (void *)srcCache64;\n        void *destCache = (void *)destCache64;\n\n        __mram_ptr const void *srcIdx = src + len;\n        __mram_ptr void *dstIdx = dest + len;\n        uint32_t remaining = len;\n\n        uint32_t srcOff = ((uintptr_t)srcIdx) & DMA_OFF_MASK;\n        uint32_t dstOff = ((uintptr_t)dstIdx) & DMA_OFF_MASK;\n\n        if (srcOff == dstOff) {\n            size_t part = MIN(remaining, srcOff);\n            uint32_t off = srcOff - part;\n\n            if (dstOff != 0) {\n                srcIdx -= srcOff;\n                dstIdx -= dstOff;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, part);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= part;\n            }\n\n            srcIdx -= MRAM_CACHE_SIZE;\n            dstIdx -= MRAM_CACHE_SIZE;\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                mram_write(srcCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= MRAM_CACHE_SIZE;\n                srcIdx -= MRAM_CACHE_SIZE;\n                dstIdx -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                uint32_t off = MRAM_CACHE_SIZE - remaining;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, remaining);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        } else {\n            size_t initLen = MIN(remaining, MIN(dstOff, srcOff));\n\n            if (initLen == remaining) {\n                mram_read(dest, destCache, MRAM_CACHE_SIZE);\n                mram_read(src, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + dstOff - remaining, srcCache + srcOff - remaining, remaining);\n                mram_write(destCache, dest, MRAM_CACHE_SIZE);\n                return dest;\n            }\n\n            mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx -= MRAM_CACHE_SIZE;\n\n            if (dstOff != 0) {\n                size_t part = DMA_ALIGNED(dstOff);\n                mram_read(dstIdx, destCache + MRAM_CACHE_SIZE - part, part);\n\n                if (srcOff > dstOff) {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n                    memcpy(destCache, srcCache + srcOff - part, part);\n                    srcOff -= part;\n                } else {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                    memcpy(destCache + dstOff - part, srcCache, part);\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    srcIdx -= MRAM_CACHE_SIZE;\n\n                    size_t part2 = dstOff - part;\n                    memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n\n                    srcOff = MRAM_CACHE_SIZE - part2;\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n            }\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx -= MRAM_CACHE_SIZE;\n\n                size_t part2 = MRAM_CACHE_SIZE - part;\n                memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n\n                if (remaining > part) {\n                    size_t part2 = remaining - part;\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    memcpy(destCache + MRAM_CACHE_SIZE - remaining, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        }\n\n        return dest;\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memmram_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_MEMMRAM_UTILS_H_\n#define _DPUSYSCORE_MEMMRAM_UTILS_H_\n\n#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))\n#define ALIGN(x, a) ALIGN_MASK((x), (a)-1)\n#define DMA_ALIGNMENT 8\n#define DMA_OFF_MASK (DMA_ALIGNMENT - 1)\n#define DMA_ALIGNED(x) ALIGN(x, DMA_ALIGNMENT)\n\n#define MIN(a, b) ((a) < (b) ? (a) : (b))\n\n#define MRAM_CACHE_SIZE 8\n\n#endif /* _DPUSYSCORE_MEMMRAM_UTILS_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/memset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\nstatic void *\n__memset_wram_1align(void *dest, int c, size_t len)\n{\n    uint8_t *dest8 = (uint8_t *)(dest);\n    for (uint32_t i = 0; i < (len); ++i) {\n        dest8[i] = (c);\n    }\n    return dest;\n}\n\ntypedef uint32_t memset_wram_t;\n/* Requisite:\n *  - dest: align on 4 bytes\n *  - len: mutiple of 4 bytes\n */\nvoid *__attribute__((used)) __memset_wram_4align(void *dest, int c, size_t len)\n{\n    uint32_t cccc;\n    memset_wram_t *dest32 = (memset_wram_t *)dest;\n\n    c &= 0xff; /* Clear upper bits before ORing below */\n    cccc = c | (c << 8) | (c << 16) | (c << 24);\n\n    for (uint32_t i = 0; i < len / sizeof(memset_wram_t); ++i) {\n        dest32[i] = cccc;\n    }\n\n    return dest;\n}\n\nvoid *\nmemset(void *dest, int c, size_t len)\n{\n    const uint32_t align = sizeof(memset_wram_t);\n    const uint32_t align_off_mask = (align - 1);\n    uint32_t align_offset = ((uintptr_t)dest) & align_off_mask;\n    uint8_t *d = (uint8_t *)dest;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = align - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        __memset_wram_1align(d, c, head_len);\n\n        len -= head_len;\n        d += head_len;\n    }\n\n    /* memset body */\n    if (len >= align) {\n        size_t body_len = len & (~align_off_mask);\n\n        __memset_wram_4align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        __memset_wram_1align(d, c, len);\n    }\n\n    return dest;\n}\n\n#define MEMSET_MRAM_CACHE_SIZE (8)\n/* Requisite:\n *  - dest: align on 8 bytes\n *  - len: mutiple of 8 bytes\n */\n__attribute__((used)) __mram_ptr void *\n__memset_mram_8align(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n\n    __memset_wram_4align(cache, c, MEMSET_MRAM_CACHE_SIZE);\n\n    for (uint32_t idx = 0; idx < len; idx += MEMSET_MRAM_CACHE_SIZE) {\n        mram_write(cache, dest + idx, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memset_mram(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n    __mram_ptr uint8_t *d = (__mram_ptr uint8_t *)((uintptr_t)dest & (~DMA_OFF_MASK));\n    uint32_t align_offset = ((uintptr_t)dest) & DMA_OFF_MASK;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = MEMSET_MRAM_CACHE_SIZE - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache + align_offset, c, head_len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n\n        len -= head_len;\n        d += MEMSET_MRAM_CACHE_SIZE;\n    }\n\n    /* memset body */\n    if (len >= MRAM_CACHE_SIZE) {\n        size_t body_len = len & (~(MEMSET_MRAM_CACHE_SIZE - 1));\n\n        __memset_mram_8align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache, c, len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdalign.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDALIGN_H_\n#define _DPUSYSCORE_STDALIGN_H_\n\n/**\n * @file stdalign.h\n * @brief Defines align macros.\n */\n\n/**\n * @def alignas\n * @brief _Alignas specifier.\n */\n#define alignas _Alignas\n\n/**\n * @def alignof\n * @brief _Alignof operator.\n */\n#define alignof _Alignof\n\n/**\n * @def __alignas_is_defined\n * @brief Whether the alignas macro is defined.\n */\n#define __alignas_is_defined 1\n\n/**\n * @def __alignof_is_defined\n * @brief Whether the alignof macro is defined.\n */\n#define __alignof_is_defined 1\n\n#endif /* _DPUSYSCORE_STDALIGN_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdarg.h",
    "content": "/*===---- stdarg.h - Variable argument handling ----------------------------===\n *\n * Copyright (c) 2008 Eli Friedman\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __STDARG_H\n#define __STDARG_H\n\n#ifndef _VA_LIST\ntypedef __builtin_va_list va_list;\n#define _VA_LIST\n#endif\n#define va_start(ap, param) __builtin_va_start(ap, param)\n#define va_end(ap) __builtin_va_end(ap)\n#define va_arg(ap, type) __builtin_va_arg(ap, type)\n\n/* GCC always defines __va_copy, but does not define va_copy unless in c99 mode\n * or -ansi is not specified, since it was not part of C90.\n */\n#define __va_copy(d, s) __builtin_va_copy(d, s)\n\n#if __STDC_VERSION__ >= 199901L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__)\n#define va_copy(dest, src) __builtin_va_copy(dest, src)\n#endif\n\n#ifndef __GNUC_VA_LIST\n#define __GNUC_VA_LIST 1\ntypedef __builtin_va_list __gnuc_va_list;\n#endif\n\n#endif /* __STDARG_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdbool.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDBOOL_H_\n#define _DPUSYSCORE_STDBOOL_H_\n\n/**\n * @file stdbool.h\n * @brief Defines the boolean type.\n */\n\n/**\n * @def __bool_true_false_are_defined\n * @brief Whether the boolean type and values are defined.\n */\n#define __bool_true_false_are_defined 1\n\n/**\n * @def bool\n * @brief The boolean type.\n */\n#define bool _Bool\n\n/**\n * @def true\n * @brief The <code>true</code> constant, represented by <code>1</code>\n */\n#define true 1\n/**\n * @def false\n * @brief The <code>false</code> constant, represented by <code>0</code>\n */\n#define false 0\n\n#endif /* _DPUSYSCORE_STDBOOL_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stddef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDDEF_H_\n#define _DPUSYSCORE_STDDEF_H_\n\n/**\n * @file stddef.h\n * @brief Defines some standard types.\n */\n\n/**\n * @brief The type for the result of subtracting two pointers.\n */\ntypedef int ptrdiff_t;\n\n/**\n * @brief The type for the result of the <code>sizeof</code> operator.\n *\n * @internal No memory or object in the DPU can be more than megabytes of data.\n *           As a consequence, we can restrict the sizes to 32 bits, which is\n *           already a lot.\n */\ntypedef unsigned int size_t;\n\n/**\n * @brief Value whose alignment requirement is at least as strict (as large) as that of every scalar type.\n */\ntypedef unsigned long int max_align_t;\n\n/**\n * @brief The type for wide-character codes.\n */\ntypedef unsigned int wchar_t;\n\n/**\n * @def NULL\n * @brief The null pointer constant.\n */\n#define NULL ((void *)0)\n\n/**\n * @def offsetof\n * @hideinitializer\n * @brief Offset in bytes to the structure member, from the beginning of its structure.\n *\n * @param st the structure\n * @param m the member name\n *\n * @internal Raw version of offsetof, should be enough in our context, with all the underlying risks.\n */\n#define offsetof(st, m) ((size_t)(&((st *)0)->m))\n\n#endif /* _DPUSYSCORE_STDDEF_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdint.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDINT_H_\n#define _DPUSYSCORE_STDINT_H_\n\n/**\n * @file stdint.h\n * @brief Provides abstraction over machine types.\n */\n\n/* Exact integer types */\n\n/* Signed */\n\n/**\n * @brief A signed 8-bit value.\n */\ntypedef signed char int8_t;\n/**\n * @brief A signed 16-bit value.\n */\ntypedef short int int16_t;\n/**\n * @brief A signed 32-bit value.\n */\ntypedef int int32_t;\n/**\n * @brief A signed 64-bit value.\n */\ntypedef long long int int64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned 8-bit value.\n */\ntypedef unsigned char uint8_t;\n/**\n * @brief An unsigned 16-bit value.\n */\ntypedef unsigned short int uint16_t;\n/**\n * @brief An unsigned 32-bit value.\n */\ntypedef unsigned int uint32_t;\n\n/**\n * @brief An unsigned 64-bit value.\n */\ntypedef unsigned long int uint64_t;\n\n/* Small types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits.\n */\ntypedef signed char int_least8_t;\n/**\n * @brief A signed value on at least 16 bits.\n */\ntypedef short int int_least16_t;\n/**\n * @brief A signed value on at least 32 bits.\n */\ntypedef int int_least32_t;\n/**\n * @brief A signed value on at least 64 bits.\n */\ntypedef long int int_least64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits.\n */\ntypedef unsigned char uint_least8_t;\n/**\n * @brief An unsigned value on at least 16 bits.\n */\ntypedef unsigned short int uint_least16_t;\n/**\n * @brief An unsigned value on at least 32 bits.\n */\ntypedef unsigned int uint_least32_t;\n/**\n * @brief An unsigned value on at least 64 bits.\n */\ntypedef unsigned long int uint_least64_t;\n\n/* Fast types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits, optimized for that length.\n */\ntypedef signed char int_fast8_t;\n/**\n * @brief A signed value on at least 16 bits, optimized for that length.\n */\ntypedef int int_fast16_t;\n/**\n * @brief A signed value on at least 32 bits, optimized for that length.\n */\ntypedef int int_fast32_t;\n/**\n * @brief A signed value on at least 64 bits, optimized for that length.\n */\ntypedef long int int_fast64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits, optimized for that length.\n */\ntypedef unsigned char uint_fast8_t;\n/**\n * @brief An unsigned value on at least 16 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast16_t;\n/**\n * @brief An unsigned value on at least 32 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast32_t;\n/**\n * @brief An unsigned value on at least 64 bits, optimized for that length.\n */\ntypedef unsigned long int uint_fast64_t;\n\n/* Types for void* pointers */\n\n/**\n * @brief A signed value which can contain a pointer value.\n */\ntypedef int intptr_t;\n/**\n * @brief An unsigned value which can contain a pointer value.\n */\ntypedef unsigned int uintptr_t;\n\n/* Greatest-width integer types */\n\n/**\n * @brief A signed value which can contain all signed values.\n */\ntypedef long long int intmax_t;\n/**\n * @brief An unsigned value which can contain all unsigned values.\n */\ntypedef unsigned long long int uintmax_t;\n\n#include <limits.h>\n\n#endif /* _DPUSYSCORE_STDINT_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdio.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdarg.h>\n#include <string.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n#include <mram.h>\n#include <dpuruntime.h>\n\n#define DEFAULT_STDOUT_BUFFER_SIZE (1 << 20)\n\nunsigned char __weak __mram_noinit __stdout_buffer[DEFAULT_STDOUT_BUFFER_SIZE];\nunsigned int __weak __stdout_buffer_size = DEFAULT_STDOUT_BUFFER_SIZE;\n\n/* __lower_data: needed to make sure that the structure address will be less that a signed12\n *               (sd endian:e ra off:s12 imm:s16 used in bootstrap).\n *\n * __dma_aligned: needed to make sure that the structure address will be aligned on 8 bytes (for sd in bootstrap as well).\n *\n * This structure is initialize at zero in the bootsrap\n */\n__lower_data(__STR(__STDOUT_BUFFER_STATE)) __dma_aligned struct {\n    uint32_t wp;\n    uint32_t has_wrapped;\n} __STDOUT_BUFFER_STATE;\n\nstatic uint32_t __stdout_buffer_write_pointer_initial;\nstatic uint32_t __stdout_nr_of_wrapping;\n\n#define STDOUT_CACHE_BUFFER_SIZE 8\n_Static_assert((STDOUT_CACHE_BUFFER_SIZE >= 8) && (STDOUT_CACHE_BUFFER_SIZE <= 2048) && (STDOUT_CACHE_BUFFER_SIZE % 8 == 0),\n    \"STDOUT_CACHE_BUFFER_SIZE needs to be a multiple of 8 in ]0; 2048]\");\n\nstatic char __stdout_cache_buffer[STDOUT_CACHE_BUFFER_SIZE] __dma_aligned;\nstatic unsigned int __stdout_cache_write_index;\n\nATOMIC_BIT_INIT(__stdout_buffer_lock);\n\n__attribute__((noinline)) static void\n__transfer_cache_to_mram()\n{\n    __mram_ptr void *offset_in_mram = (__mram_ptr void *)(__STDOUT_BUFFER_STATE.wp + (uintptr_t)__stdout_buffer);\n\n    __STDOUT_BUFFER_STATE.wp += STDOUT_CACHE_BUFFER_SIZE;\n    if (__STDOUT_BUFFER_STATE.wp >= __stdout_buffer_size) {\n        __STDOUT_BUFFER_STATE.wp = 0;\n        __STDOUT_BUFFER_STATE.has_wrapped = true;\n        __stdout_nr_of_wrapping++;\n    }\n\n    mram_write(__stdout_cache_buffer, offset_in_mram, STDOUT_CACHE_BUFFER_SIZE);\n}\n\n// Generic template that will be used everywhere: cache a byte and flush to MRAM\n// when the cache is full.\n__attribute__((noinline)) static void\n__write_byte_and_flush_if_needed(uint8_t byte)\n{\n    __stdout_cache_buffer[__stdout_cache_write_index++] = byte;\n    if (__stdout_cache_write_index == STDOUT_CACHE_BUFFER_SIZE) {\n        __transfer_cache_to_mram();\n        __stdout_cache_write_index = 0;\n    }\n}\n\n__attribute__((noinline)) static void\n__finalized_print_sequence()\n{\n    memset(__stdout_cache_buffer + __stdout_cache_write_index, 0, STDOUT_CACHE_BUFFER_SIZE - __stdout_cache_write_index);\n    __transfer_cache_to_mram();\n\n    if (__stdout_nr_of_wrapping > 1\n        || (__stdout_nr_of_wrapping == 1 && __STDOUT_BUFFER_STATE.wp > __stdout_buffer_write_pointer_initial))\n        __asm__(\"fault \" __STR(__FAULT_PRINTF_OVERFLOW__)); // need to throw fault because we will not be able to print the buffer\n}\n\n__attribute__((noinline)) static void\n__open_print_sequence()\n{\n    ATOMIC_BIT_ACQUIRE(__stdout_buffer_lock);\n    __stdout_cache_write_index = 0;\n    __stdout_nr_of_wrapping = 0;\n    __stdout_buffer_write_pointer_initial = __STDOUT_BUFFER_STATE.wp;\n}\n\n/* Nothing else that the release instruction should be in this function in order to make sure that the print routine in complete\n * at this point*/\n__attribute__((noinline)) static void\n__close_print_sequence()\n{\n    ATOMIC_BIT_RELEASE(__stdout_buffer_lock);\n}\n\nvoid\nprintf(const char *restrict format, ...)\n{\n    bool insert_string_arg = true;\n    bool insert_string_arg_end_character = false;\n    char *current_format_char_ptr = (char *)format;\n\n    __open_print_sequence();\n\n    va_list args;\n    va_start(args, format);\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_format_process;\n\n            __write_byte_and_flush_if_needed('%');\n\n            while (*current_format_char_ptr != '\\0') {\n                if (*current_format_char_ptr == 'l') {\n                    __write_byte_and_flush_if_needed(*current_format_char_ptr);\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if ((*current_format_char_ptr == 'L') || (*current_format_char_ptr == 'z')) {\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if (*current_format_char_ptr == 'i') {\n                    __write_byte_and_flush_if_needed('d');\n                    break;\n                }\n                __write_byte_and_flush_if_needed(*current_format_char_ptr);\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            insert_string_arg = true;\n\n        } else {\n        standard_character_format_process:\n            if (insert_string_arg) {\n                __write_byte_and_flush_if_needed('%');\n                __write_byte_and_flush_if_needed('s');\n                insert_string_arg = false;\n            }\n        }\n    }\n\n    __write_byte_and_flush_if_needed('\\0');\n    current_format_char_ptr = (char *)format;\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_process;\n\n            if (insert_string_arg_end_character) {\n                insert_string_arg_end_character = false;\n                __write_byte_and_flush_if_needed('\\0');\n            }\n\n            bool arg_is_64_bits = false;\n\n            while (*current_format_char_ptr != '\\0') {\n                if ((*current_format_char_ptr == 'l') || (*current_format_char_ptr == 'L')) {\n                    arg_is_64_bits = true;\n                    current_format_char_ptr++;\n                    continue;\n                } else if (*current_format_char_ptr == 'z') {\n                    current_format_char_ptr++;\n                    continue;\n                }\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            switch (*current_format_char_ptr) {\n                case 's': {\n                    char *arg = (char *)va_arg(args, int);\n                    while (*arg != '\\0') {\n                        __write_byte_and_flush_if_needed(*arg);\n                        arg++;\n                    }\n                    __write_byte_and_flush_if_needed('\\0');\n                    break;\n                }\n                case 'c': {\n                    char arg_as_char = (char)va_arg(args, int);\n                    __write_byte_and_flush_if_needed(arg_as_char);\n                    break;\n                }\n                case 'f':\n                case 'e':\n                case 'E':\n                case 'g':\n                case 'G': {\n                    __asm__ volatile(\"nop\");\n                    double val = va_arg(args, double);\n                    char *arg = (char *)&val;\n                    for (int i = 0; i < 8; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                    break;\n                }\n                default: {\n                    unsigned int arg_size_in_bytes;\n                    long val;\n\n                    if (arg_is_64_bits) {\n                        val = va_arg(args, long);\n                        arg_size_in_bytes = 8;\n                    } else {\n                        val = (long)va_arg(args, int);\n                        arg_size_in_bytes = 4;\n                    }\n\n                    char *arg = (char *)&val;\n                    for (unsigned int i = 0; i < arg_size_in_bytes; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                }\n            }\n        } else {\n        standard_character_process:\n            __write_byte_and_flush_if_needed(*current_format_char_ptr);\n            insert_string_arg_end_character = true;\n        }\n    }\n\n    if (insert_string_arg_end_character) {\n        __write_byte_and_flush_if_needed('\\0');\n    }\n\n    va_end(args);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputs(const char *str)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('s');\n    __write_byte_and_flush_if_needed('\\0');\n\n    for (char *current_char_ptr = (char *)str; *current_char_ptr != '\\0'; current_char_ptr++) {\n        __write_byte_and_flush_if_needed(*current_char_ptr);\n    }\n\n    __write_byte_and_flush_if_needed('\\n');\n    __write_byte_and_flush_if_needed('\\0');\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputchar(int c)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('c');\n    __write_byte_and_flush_if_needed('\\0');\n\n    char arg_as_char = (char)c;\n    __write_byte_and_flush_if_needed(arg_as_char);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdio.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDIO_H_\n#define _DPUSYSCORE_STDIO_H_\n\n#include <attributes.h>\n#include <stddef.h>\n\n/**\n * @file stdio.h\n * @brief Standard input/output library functions.\n */\n\n/**\n * @def STDOUT_BUFFER_INIT\n * @hideinitializer\n * @brief Declares the stdout buffer. Should be used as when declaring a global variable.\n * @param size the size of the stdout buffer. Must be a multiple of 8, and greater than 0.\n */\n#define STDOUT_BUFFER_INIT(size)                                                                                                 \\\n    _Static_assert((size >= 8) && (((size)&7) == 0), \"stdout buffer size must be a multiple of 8 and > 0\");                      \\\n    unsigned char __dma_aligned __mram_noinit __stdout_buffer[(size)];                                                           \\\n    const unsigned int __stdout_buffer_size = (size);\n\n/**\n * @fn printf\n * @brief Writes the formatted data in the stdout buffer.\n *\n * This function has a prototype close to the one of the standard printf function.\n * However, the format string comply to the java.util.Formatter format, which is\n * similar to the printf format, but not quit exactly the same. Date formatter may\n * produce interpreted results, but they will probably be incorrect. Every format\n * specifier should reference one and only one of the variadic argument (eg. \"%n\"\n * is not supported).\n *\n * There is no compile-time check to verify that the format is correct: any other\n * character in the format string will not be interpreted.\n *\n * @param format how the logged data should be formatted\n * @param ... the different data to be printed\n */\nvoid __attribute__((format(printf, 1, 2))) printf(const char *restrict format, ...);\n\n/**\n * @fn puts\n * @brief Writes the string in the stdout buffer. A newline character is appended to the output.\n * @param str the null-terminated string to be written\n */\nvoid\nputs(const char *str);\n\n/**\n * @fn putchar\n * @brief Writes the character in the stdout buffer.\n * @param c the character to be written\n */\nvoid\nputchar(int c);\n\n#endif /* _DPUSYSCORE_STDIO_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdlib.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STDLIB_H\n#define DPUSYSCORE_STDLIB_H\n\n/**\n * @file stdlib.h\n * @brief Elementary standard C functions: calls the system function halt.\n */\n\n#include <stddef.h>\n#include <attributes.h>\n\n/**\n * @def EXIT_FAILURE\n * @hideinitializer\n * @brief Unsuccessful termination for exit().\n */\n#define EXIT_FAILURE 1\n\n/**\n * @def EXIT_SUCCESS\n * @hideinitializer\n * @brief Successful termination for exit().\n */\n#define EXIT_SUCCESS 0\n\n/**\n * @brief Aborts the DPU execution triggering a processor fault.\n */\n__NO_RETURN void\nabort(void);\n\n/**\n * @brief Terminates the invoking tasklet, returning the specified status.\n */\n__NO_RETURN void\nexit(int status);\n\n/**\n * @brief Get an environment variable, or NULL. In the DPU case, always NULL.\n */\nstatic inline char *\ngetenv(__attribute__((unused)) const char *name)\n{\n    return NULL;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline int\nabs(int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long int\nlabs(long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long long int\nllabs(long long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\ntypedef struct {\n    int quot;\n    int rem;\n} div_t;\n\ntypedef struct {\n    long int quot;\n    long int rem;\n} ldiv_t;\n\ntypedef struct {\n    long long int quot;\n    long long int rem;\n} lldiv_t;\n\nstatic inline div_t\ndiv(int numer, int denom)\n{\n    div_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline ldiv_t\nldiv(long int numer, long int denom)\n{\n    ldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline lldiv_t\nlldiv(long long int numer, long long int denom)\n{\n    lldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/**\n * @brief Converts a string to an integer\n *\n * Function converts the initial part of the string in nptr to an integer value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atoi()\n * returns INT_MIN. If an overflow occurs, atoi() returns INT_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nint\natoi(const char *nptr);\n\n/**\n * @brief Converts a string to a long integer (64 bits)\n *\n * Function converts the initial part of the string in nptr to a long value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atol()\n * returns LONG_MIN. If an overflow occurs, atol() returns LONG_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nlong\natol(const char *nptr);\n\n///**\n// * @brief Converts a string to a long integer (64 bits) according to the given base\n// * between 2 and 36 inclusive, or be the special value 0\n// *\n// * TODO : If the given base is oustide of the range [2...36], then errno is set to EINVAL\n// *\n// * Function converts the initial part of the string in nptr to a long value. The string may begin\n// * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n// *\n// * If base is zero or 16, the string may then include a \"0x\" prefix, and the number will be read\n// * in base 16; otherwise, a zero base is taken as 10 (decimal) unless the next character is '0',\n// * in which case it is taken as 8 (octal).\n// *\n// * Conversion stops at the first character not representing a digit in the given base.\n// * Accepted digits are : in bases above 10, the letter 'A' in either uppercase or lowercase\n// * represents 10, 'B' represents 11, and so forth, with 'Z' representing 35.\n// *\n// * If endptr is not NULL, strtol() stores the address of the first invalid character in *endptr.\n// * If there were no digits at all, strtol() stores the original value of nptr in *endptr (and\n// * returns 0). In particular, if *nptr is not '\\0' but **endptr is '\\0' on return, the entire\n// * string is valid.\n// *\n// * If an underflow occurs, atol() returns LONG_MIN. If an overflow occurs, atol()\n// * returns LONG_MAX. TODO!!! In both cases errno is set to ERANGE.\n// *\n// * @param nptr string that contains an integer in a string format\n// * @param endptr\n// * @param base\n//\n// * @return the result of conversion unless the value would overflow or underflow.\n//*/\n// long int strtol(const char *nptr, char **endptr, int base);\n// TODO : strtol() doesn't work : has to be written in assembly\n\n#endif /* DPUSYSCORE_STDLIB_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stdnoreturn.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDNORETURN_H_\n#define _DPUSYSCORE_STDNORETURN_H_\n\n/**\n * @file stdnoreturn.h\n * @brief Defines the noreturn macro.\n */\n\n/**\n * @def noreturn\n * @brief _Noreturn attribute.\n */\n#define noreturn _Noreturn\n\n#endif /* _DPUSYSCORE_STDNORETURN_H_ */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stpcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nchar *\nstpcpy(char *destination, const char *source)\n{\n    char c = *source;\n\n    while (c != '\\0') {\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    *destination = c;\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/stpncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstpncpy(char *destination, const char *source, size_t size)\n{\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            char *null_char_ptr = destination;\n\n            for (; each_byte < size; ++each_byte) {\n                *destination = '\\0';\n                destination++;\n            }\n\n            return null_char_ptr;\n        }\n\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strcat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcat(char *destination, const char *source)\n{\n    size_t length = strlen(destination);\n    unsigned int i;\n\n    for (i = 0; source[i] != '\\0'; i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrchr(const char *string, int character)\n{\n    char *str = (char *)string;\n    unsigned char c = *str;\n\n    while (1) {\n        if (c == character) {\n            return str;\n        }\n        if (c == '\\0') {\n            return NULL;\n        }\n\n        str++;\n        c = *str;\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrcmp(const char *string1, const char *string2)\n{\n    unsigned char c1 = *string1;\n    unsigned char c2 = *string2;\n\n    while (c1 != '\\0') {\n        if (c1 - c2 != 0) {\n            return c1 - c2;\n        }\n\n        string1++;\n        string2++;\n        c1 = *string1;\n        c2 = *string2;\n    }\n\n    return c1 - c2;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcpy(char *destination, const char *source)\n{\n    char *ptr = destination;\n    char c = *source;\n\n    while (c != '\\0') {\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    *ptr = c;\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strcspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrcspn(const char *string, const char *reject)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        for (unsigned int reject_index = 0; reject[reject_index] != '\\0'; ++reject_index) {\n            if (reject[reject_index] == c) {\n                return prefix_length;\n            }\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strdup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrdup(const char *string)\n{\n    size_t length = strlen(string) + 1; // we get the length of the string for memory allocation\n\n    char *result = buddy_alloc(length); // we allocate length+1 bytes for the duplicate\n\n    if (result != NULL) {\n        memcpy(result, string, length); // we copy length bytes from string to the duplicate\n    }\n\n    return result;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strerror.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <defs.h>\n#include \"errno.h\"\n\n// http://www.delorie.com/gnu/docs/glibc/libc_17.html\n\n// static char* strerror_errors[] = { \"Success\",\n//\"E2BIG\", \"EACCES\", \"EADDRINUSE\", \"EADDRNOTAVAIL\", \"EAFNOSUPPORT\", \"EAGAIN\", \"EALREADY\", \"EBADF\",\n//\"EBADMSG\", \"EBUSY\", \"ECANCELED\", \"ECHILD\", \"ECONNABORTED\", \"ECONNREFUSED\", \"ECONNRESET\", \"EDEADLK\",\n//\"EDESTADDRREQ\", \"EDOM\", \"EDQUOT\", \"EEXIST\", \"EFAULT\", \"EFBIG\", \"EHOSTUNREACH\", \"EIDRM\",\n//\"EILSEQ\", \"EINPROGRESS\", \"EINTR\", \"EINVAL\", \"EIO\", \"EISCONN\", \"EISDIR\", \"ELOOP\",\n//\"EMFILE\", \"EMLINK\", \"EMSGSIZE\", \"EMULTIHOP\", \"ENAMETOOLONG\", \"ENETDOWN\", \"ENETRESET\", \"ENETUNREACH\",\n//\"ENFILE\", \"ENOBUFS\", \"ENODATA\", \"ENODEV\", \"ENOENT\", \"ENOEXEC\", \"ENOLCK\", \"ENOLINK\",\n//\"ENOMEM\", \"ENOMSG\", \"ENOPROTOOPT\", \"ENOSPC\", \"ENOSR\", \"ENOSTR\", \"ENOSYS\", \"ENOTCONN\",\n//\"ENOTDIR\", \"ENOTEMPTY\", \"ENOTRECOVERABLE\", \"ENOTSOCK\", \"ENOTSUP\", \"ENOTTY\", \"ENXIO\", \"EOPNOTSUPP\",\n//\"EOVERFLOW\", \"EOWNERDEAD\", \"EPERM\", \"EPIPE\", \"EPROTO\", \"EPROTONOSUPPORT\", \"EPROTOTYPE\", \"ERANGE\",\n//\"EROFS\", \"ESPIPE\", \"ESRCH\", \"ESTALE\", \"ETIME\", \"ETIMEDOUT\", \"ETXTBSY\", \"EWOULDBLOCK\",\n//\"EXDEV\"\n//};\n\n// 81 errors in total including 2 not supported ones.\n\nconst static char *strerror_errors_complete[] = { \"Success\",\n    \"Argument list too long\",\n    \"Permission denied\",\n    \"Address in use\",\n    \"Address not available\",\n    \"Address family not supported\",\n    \"Resource unavailable, try again\",\n    \"Connection already in progress\",\n    \"Bad file descriptor\",\n\n    \"Bad message\",\n    \"Device or resource busy\",\n    \"Operation canceled\",\n    \"No child processes\",\n    \"Connection aborted\",\n    \"Connection refused\",\n    \"Connection reset\",\n    \"Resource deadlock would occur\",\n\n    \"Destination address required\",\n    \"Mathematics argument out of domain of function\",\n    \"Disk quota exceeded\",\n    \"File exists\",\n    \"Bad address\",\n    \"File too big\",\n    \"Host unreachable\",\n    \"Identifier removed\",\n\n    \"Illegal byte sequence\",\n    \"Operation in progress\",\n    \"Interrupted function\",\n    \"Invalid argument\",\n    \"I/O error\",\n    \"Socket is connected\",\n    \"File is a directory\",\n    \"Too many levels of symbolic links\",\n\n    \"File descriptor value too large\",\n    \"Too many links\",\n    \"Message too large\",\n    \"EMULTIHOP\",\n    \"Filename too long\",\n    \"Network is down\",\n    \"Connection aborted by network\",\n    \"Network unreachable\",\n\n    \"Too many files open in system\",\n    \"No buffer space available\",\n    \"No message is available on the STREAM head read queue\",\n    \"No such device\",\n    \"No such file or directory\",\n    \"Executable file format error\",\n    \"No locks available\",\n    \"ENOLINK\",\n\n    \"Not enough space\",\n    \"No message of the desired type\",\n    \"Protocol unavailable\",\n    \"No space left on device\",\n    \"No STREAM resources\",\n    \"Not a STREAM\",\n    \"Function not supported\",\n    \"The socket is not connected\",\n\n    \"Not a directory or a symbolic link to a directory\",\n    \"Directory not empty\",\n    \"State not recoverable\",\n    \"Not a socket\",\n    \"Not supported\",\n    \"Inappropriate I/O control operation\",\n    \"No such device or address\",\n    \"Operation not supported on socket\",\n\n    \"Value too large to be stored in data type\",\n    \"Previous owner died\",\n    \"Operation not permitted\",\n    \"Broken pipe\",\n    \"Protocol error\",\n    \"Protocol not supported\",\n    \"Protocol wrong type for socket\",\n    \"Result too large\",\n\n    \"Read-only file system\",\n    \"Invalid seek\",\n    \"No such process\",\n    \"ESTALE\",\n    \"Stream ioctl() timeout\",\n    \"Connection timed out\",\n    \"Text file busy\",\n    \"Operation would block\",\n\n    \"Cross-device link\",\n    \"Unknown error\" };\n\nchar *\nstrerror(int errnum)\n{\n    unsigned int length = sizeof(strerror_errors_complete) / sizeof(strerror_errors_complete[0]) - 1; //-1 for \"Unknown error\"\n    if (((unsigned int)errnum) >= length) {\n        errno = EINVAL;\n        return (char *)strerror_errors_complete[length];\n    }\n    return (char *)strerror_errors_complete[errnum];\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/string.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STRING_H\n#define DPUSYSCORE_STRING_H\n\n/**\n * @file string.h\n * @brief Provides functions to manipulate arrays of characters.\n */\n\n#include <stddef.h>\n\n/**\n * @brief Computes the length of the given null-terminated string.\n *\n * @param string the string for which we want the length.\n * @return The length of the string, not including the null character.\n */\nsize_t\nstrlen(const char *string);\n\n/**\n * @brief Computes the length of the given null-terminated string if this length is less than <code>max_len</code>.\n * strnlen checks at most <code>max_len</code> bytes and returns <code>max_len</code> if it has read as many bytes.\n *\n * @param string the string for which we want to find the length.\n * @param max_len maximum number of bytes to check\n * @return The length of the string, not including the null character or <code>max_len</code> if null character\n * wasn't found.\n */\nsize_t\nstrnlen(const char *string, size_t max_len);\n\n/**\n * @brief Compares the first <code>size</code> bytes of <code>area1</code> and <code>area2</code>.\n *\n * @param area1 the pointer to the start of the first area of the comparison\n * @param area2 the pointer to the start of the second area of the comparison\n * @param size the number of bytes to compare between each area.\n * @return <code>0</code> if the areas are the same, a non-zero value otherwise.\n */\nint\nmemcmp(const void *area1, const void *area2, size_t size);\n\n/**\n * @brief Compares the two null-terminated strings <code>string1</code> and <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrcmp(const char *string1, const char *string2);\n\n/**\n * @brief Compares the first <code>size</code> bytes of the two null-terminated strings <code>string1</code> and\n * <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @param size the maximum number of bytes to compare between each string.\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrncmp(const char *string1, const char *string2, size_t size);\n\n/**\n * @brief Set the first <code>size</code> bytes of <code>area</code> at <code>value</code>.\n *\n * @param area the pointer to the start of the area to set\n * @param value the value at which the area is set\n * @param size the number of bytes being set\n * @return A pointer to the start of the set area.\n */\nvoid *\nmemset(void *area, int value, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the first <code>size</code> bytes of <code>area</code>.\n *\n * @param area the pointer to the start of the area to search\n * @param character the value to search for\n * @param size the number of bytes to search\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nvoid *\nmemchr(const void *area, int character, size_t size);\n\n/**\n * @brief Concatenate the string <code>source</code> after the string <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrcat(char *destination, const char *source);\n\n/**\n * @brief Concatenate the first <code>size</code> bytes of the string <code>source</code> after the string\n * <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @param size the maximum number of bytes to concatenate\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrncat(char *destination, const char *source, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrchr(const char *string, int character);\n\n/**\n * @brief Search for the last occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the last occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrrchr(const char *string, int character);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * @warning This function is not safe for overlapping memory blocks.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemcpy(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * This is a safer method than <code>memcpy</code> for overlapping memory blocks.\n *\n * @see memcpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemmove(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrncpy(char *destination, const char *source, size_t size);\n\n/**\n * @def strxfrm\n * @hideinitializer\n * @brief Transform the first <code>size</code> bytes of the string <code>source</code> into current locale and place them in the\n * string <code>destination</code>.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strncpy</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @see strncpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\n#define strxfrm strncpy\n\n/**\n * @def strcoll\n * @hideinitializer\n * @brief Compare two null-terminated strings using the current locale.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strcmp</code>.\n *\n * @see strcmp\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\n#define strcoll strcmp\n\n/**\n * @brief Copy the string <code>source</code> into the string <code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n * If <code>size</code> is less than the length of the <code>source</code>, then\n * the remaining characters in <code>destination</code> will be filled with '\\0'\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpncpy(char *destination, const char *source, size_t size);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrlwr(char *string);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrupr(char *string);\n\n/**\n * @brief Reverses the order of characters in the string\n *\n * For example, a string \"Hello\" becomes \"olleH\". The NULL character at the end\n * of the string remains at the end.\n *\n * @param string the string we want to reverse\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrrev(char *string);\n\n/**\n * @brief Returns a string corresponding to the error number\n *\n * Warning : the returned pointer should be duplicated if the user ever needs to modify it\n *\n * @param errnum number of error\n * @return the pointer to the message corresponding to the errnum or NULL if none was found\n */\nchar *\nstrerror(int errnum);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strdup(const char *string);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument (copies at most n bytes)\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @param n max number of characters to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strndup(const char *string, size_t n);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes in accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters that the longest prefix consists of\n * @return the index of the first character in string that is not in accept\n */\nsize_t\nstrspn(const char *string, const char *accept);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes not in reject.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param reject key characters that must not be in the longest prefix\n * @return the index of the first character in string that is the same as any of the ones in reject\n */\nsize_t\nstrcspn(const char *string, const char *reject);\n\n/**\n * @brief Locates the first occurrence in the target string of any of the bytes in the string accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters\n * @return a pointer to the byte in string that matches one of the bytes in accept, or NULL if no such byte is found.\n */\nchar *\nstrpbrk(const char *string, const char *accept);\n\n/**\n * @brief Finds the first occurrence of the substring needle in the string haystack.\n *\n * If needle is an empty string, the result will be the same pointer as the one passed to haystack\n * This function uses KMP algorithm, and thereby uses more memory space\n *\n * @param haystack the target string where we look for a pattern\n * @param needle pattern to look for\n * @return a pointer to the beginning of the located substring, or NULL if the substring is not found\n */\nchar *\nstrstr(const char *haystack, const char *needle);\n\n/**\n * @brief Extracts a token from a string\n *\n * The strtok_r() function breaks a string into a sequence of zero or more nonempty tokens.\n *\n * On the first call to strtok_r(), str should point to the string to be parsed, and the value of saveptr is ignored (modified\n * internally). In each subsequent call that should parse the same string, str must be NULL and saveptr should be unchanged since\n * the previous call.\n *\n * The caller may specify different strings in delim in successive calls that parse the same string. For instance, if string is\n * \"a,b,c d e f,g\", by calling strtok_r() only with \",\" delimiter will create 4 tokens, but if the user calls it 2 times with \",\"\n * delimiter and then the rest with \" \" delimiter, 6 tokens wil be created : \"a\",\"b\",\"c\",\"d\",\"e\",\"f,g\" (\"f,g\" is indeed one token\n * as strtok_r() was called with \" \" delimiter).\n *\n * Each call to strtok_r() returns a pointer to a null-terminated string containing the next token. This string does not include\n * the delimiting byte. If no more tokens are found, strtok_r() returns NULL.\n *\n * A sequence of calls to strtok_r() that operate on the same string maintains a pointer that determines the point from which to\n * start searching for the next token. The first call to strtok_r() sets this pointer to point to the first byte of the string.\n * The start of the next token is determined by scanning forward for the next nondelimiter byte in str. If such a byte is found,\n * it is taken as the start of the next token. If no such byte is found, then there are no more tokens, and strtok_r() returns\n * NULL. (A string that is empty or that contains only delimiters will thus cause strtok() to return NULL on the first call.)\n *\n * The end of each token is found by scanning forward until either the next delimiter byte is found or until the terminating null\n * byte ('\\0') is encountered. If a delimiter byte is found, it is OVERWRITTEN with a null byte to terminate the current token,\n * and strtok_r() saves a pointer to the following byte; that pointer will be used as the starting point when searching for the\n * next token. In this case, strtok_r() returns a pointer to the start of the found token.\n *\n * From the above description, it follows that a sequence of two or more contiguous delimiter bytes in the parsed string is\n * considered to be a single delimiter, and that delimiter bytes at the start or end of the string are ignored. Put another way:\n * the tokens returned by strtok() are always nonempty strings.\n *\n * Different strings may be parsed concurrently using sequences of calls to strtok_r() that specify different saveptr arguments.\n *\n * Warning :\n *      strtok_r modifies str\n *      identity of delimiter bytes is lost (i.e. most of them will be replaced by '\\0' in str)\n *      if NULL is passed as the first argument for the FIRST call, *saveptr (not saveptr) should also be NULL\n *\n * @param str string to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @param saveptr pointer used internally by strtok_r in order to maintain context between successive calls that parse the same\n * string\n * @return a pointer to the beginning of the next token terminated by '\\0' or NULL if there are no more tokens\n */\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr);\n\n/**\n * @brief Extracts a token from a string\n *\n * If *stringp is NULL, the strsep() function returns NULL and does nothing else. Otherwise, this function finds the first token\n * in the string *stringp, that is delimited by one of the bytes in the string delim. This token is terminated by overwriting the\n * delimiter with a null byte ('\\0'), and *stringp is updated to point past the token. In case no delimiter was found, the token\n * is taken to be the entire string *stringp, and *stringp is made NULL.\n *\n * Warning:\n *      strsep() modifies its first parameter\n *      identity of delimiter bytes is lost (they will be replaced by '\\0' in *stringp)\n *\n * @param stringp pointer to a string (because string will be modified) to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @return a pointer to the found null-terminated token, that is, it returns the original value of *stringp\n */\nchar *\nstrsep(char **stringp, const char *delim);\n\n#endif /* DPUSYSCORE_STRING_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrlen(const char *string)\n{\n    const char *ptr = string;\n\n    while (*ptr != '\\0') {\n        ptr++;\n    }\n\n    return ptr - string;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strlwr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrlwr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = tolower(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strncat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrncat(char *destination, const char *source, size_t size)\n{\n    size_t length = strlen(destination);\n    size_t i;\n\n    for (i = 0; (i < size) && (source[i] != '\\0'); i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strncmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrncmp(const char *string1, const char *string2, size_t size)\n{\n    for (size_t len = 0; len < size; ++len) {\n        unsigned char c1 = string1[len];\n        unsigned char c2 = string2[len];\n\n        if (((c1 - c2) != 0) || (c1 == '\\0')) {\n            return c1 - c2;\n        }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrncpy(char *destination, const char *source, size_t size)\n{\n    char *ptr = destination;\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            for (; each_byte < size; ++each_byte) {\n                *ptr = '\\0';\n                ptr++;\n            }\n\n            return destination;\n        }\n\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strndup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrndup(const char *string, size_t n)\n{\n    size_t length = strnlen(string, n);\n    char *result = buddy_alloc(length + 1);\n\n    if (result != NULL) {\n        memcpy(result, string, length);\n        ((char *)result)[length + 1] = '\\0';\n    }\n\n    return result;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strnlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrnlen(const char *string, size_t max_len)\n{\n    size_t len = 0;\n\n    while ((string[len] != '\\0') && len < max_len) {\n        len++;\n    }\n\n    return len;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strpbrk.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\nchar *\nstrpbrk(const char *string, const char *accept)\n{\n    string += strcspn(string, accept);\n    return *string ? (char *)string : NULL;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strrchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrrchr(char *string, int character)\n{\n    char *pos = NULL;\n    char *ptr = string;\n    unsigned char c;\n\n    do {\n        c = *ptr;\n        if (c == character) {\n            pos = ptr;\n        }\n        ptr++;\n    } while (c != '\\0');\n\n    return pos;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strrev.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrrev(char *string)\n{\n    size_t length = strlen(string);\n\n    for (size_t each_char = 0; each_char < length / 2; ++each_char) {\n        char c = string[each_char];\n        string[each_char] = string[length - each_char - 1];\n        string[length - each_char - 1] = c;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strsep.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrsep(char **stringp, const char *delim)\n{\n    if (*stringp == NULL) {\n        return NULL;\n    }\n\n    char *original = *stringp;\n    char *delim_ptr = strpbrk(*stringp, delim);\n\n    if (delim_ptr == NULL) {\n        *stringp = NULL;\n    } else {\n        *delim_ptr = '\\0';\n        *stringp = delim_ptr + 1;\n    }\n\n    return original;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrspn(const char *string, const char *accept)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        unsigned int accept_index = 0;\n        while (true) {\n            char a = accept[accept_index];\n\n            if (c == a) {\n                break;\n            }\n\n            if (a == '\\0') {\n                return prefix_length;\n            }\n\n            accept_index++;\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strstr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"stdbool.h\"\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrstr(const char *haystack, const char *needle)\n{\n    char *current_needle = (char *)needle;\n    char *start_haystack = (char *)haystack;\n    char *current_haystack = start_haystack;\n\n    while (true) {\n        char needle_char = *current_needle;\n\n        if (needle_char == '\\0') {\n            return start_haystack;\n        }\n\n        char haystack_char = *current_haystack;\n\n        if (haystack_char == needle_char) {\n            current_haystack++;\n            current_needle++;\n        } else if (haystack_char == '\\0') {\n            return NULL;\n        } else {\n            current_needle = (char *)needle;\n            current_haystack = ++start_haystack;\n        }\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strtok_r.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr)\n{\n    char *end;\n\n    if (str == NULL) {\n        str = *saveptr;\n    }\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    str += strspn(str, delim);\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    end = str + strcspn(str, delim);\n    if (*end == '\\0') {\n        *saveptr = end;\n        return str;\n    }\n\n    *end = '\\0';\n    *saveptr = end + 1;\n    return str;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strtol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n////\n//////TODO : **endptr\n////\n////#include <stddef.h>\n////#include \"ctype.h\"\n////#include \"limits.h\"\n////\n////static long overflow(int sign)\n////{\n////    if(sign)\n////        return INT64_MAX;\n////    else\n////        return INT64_MIN;\n////\n////\n////}\n////\n////long strtol(const char *nptr, char **endptr, int base)\n////{\n////    if(nptr == NULL)\n////        return 0;\n////    unsigned long result = 0;\n////    int sign = 1;\n////    int i = 0;\n//////    while(isspace(nptr[i]))\n//////        i++;\n////\n//////    switch(nptr[i]){\n//////        case '-' :\n//////            sign = 0;       //we change sign only when '-' was encountered\n//////        case '+' :\n//////            i++;            //we increment i in both cases\n//////    }\n////\n//////\n//////    if((base == 16 ) && (nptr[i] == '0') && (nptr[i+1] == 'x'))\n//////        i+=2;\n//////    else if(base == 0){\n//////        if(nptr[i] == '0'){\n//////            base = 8;\n//////            i++;\n//////            if(nptr[i+1] == 'x'){\n//////                base = 16;\n//////                i++;\n//////            }\n//////        }\n//////        else\n//////            base = 10;\n//////    }\n////\n//////    switch(base) {\n//////        case 10 :\n////            while(((nptr[i]>>4) == 0x3) && ((nptr[i] & 0xf)<=9)){\n////                if((unsigned long)result>>60){\n////                    return overflow(sign);\n////                }\n////\n////                result = (unsigned long)(result<<1) + (unsigned long)(result<<3) + (unsigned long) nptr[i] - (unsigned long)\n///'0';\n//////                if((unsigned long)result>>63){\n//////                    return overflow(sign);\n//////                }\n////                i++;\n////            }\n//////            break;\n//////        case 2 :\n//////            while((nptr[i] & 0xfe) == 0x30){\n//////                result = (result<<1) + (unsigned long)(nptr[i] & 0x1);\n//////                i++;\n//////            }\n//////            break;\n//////        case 4 :\n//////            while((nptr[i] & 0xfc) == 0x30){\n//////                result = (result<<2) + (unsigned long)(nptr[i] & 0x3);\n//////                i++;\n//////            }\n//////            break;\n//////        case 8 :\n//////            while((nptr[i] & 0xf8) == 0x30){\n//////                result = (result<<3) + (unsigned long)(nptr[i] & 0x7);\n//////                i++;\n//////            }\n//////            break;\n//////        case 16 :\n//////            while(((nptr[i]>='0') && (nptr[i]<='9')) || ((nptr[i]>='a') && (nptr[i]<='f')) || ((nptr[i]>='A') &&\n///(nptr[i]<='F')) ){\n//////                unsigned long digit = ((nptr[i]>='0') && (nptr[i]<='9')) ? (unsigned long)(nptr[i] - '0') : (unsigned\n/// long)((nptr[i] & 0xf) + 10);\n//////                result = result<<4;\n//////                result = result + digit;\n//////                i++;\n//////            }\n//////            break;\n//////        default :\n//////            if(base < 2 || base > 36){ //base 0 has already been replaced by 8,10 or 16\n//////                //TODO!!!\n//////                break;\n//////            }\n//////    }\n////\n//////    if(sign == 0)\n//////        return (long)0 - (long)result;\n//////    else\n////        return (long) result;\n////\n////}\n////\n//\n//\n//\n////\n//\n//// Copyright (c) 2014-2019 - UPMEM\n//\n////\n//\n//#include <stddef.h>\n//\n//#include \"limits.h\"\n//\n//#include \"ctype.h\"\n//\n// static long overflow(int sign)\n//\n//{\n//\n//    if(sign)\n//\n//        return INT64_MAX;\n//\n//    else\n//\n//        return INT64_MIN;\n//\n//}\n//\n// long int strtol(const char *nptr, char **endptr, int base)\n//\n//{\n//\n//    if(nptr == NULL)\n//\n//        return 0;\n//\n//    int sign = 1;\n//\n//    int i=0;\n//\n//    long result = 0;\n//\n//\n//\n//    while((nptr[i]>='0') && (nptr[i]<='9')){\n//\n//        if(result>>60){\n//\n//                    return overflow(sign);\n//\n//                }\n//\n//        result = (result<<1) + (result<<3)+ nptr[i] - '0';\n//\n//        i++;\n//\n//    }\n//\n//    return result;\n//\n//}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/stdlib/strupr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrupr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = toupper(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(syslib ${SRCS})\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/absvdi2.c",
    "content": "/*===-- absvdi2.c - Implement __absvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __absvdi2 for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI di_int\n__absvdi2(di_int a)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    if (a == ((di_int)1 << (N - 1)))\n        compilerrt_abort();\n    const di_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/absvsi2.c",
    "content": "/* ===-- absvsi2.c - Implement __absvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __absvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI si_int\n__absvsi2(si_int a)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    if (a == (1 << (N - 1)))\n        compilerrt_abort();\n    const si_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/adddf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI double\n__adddf3(double a, double b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_dadd(double a, double b)\n{\n    return __adddf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/addsf3.c",
    "content": "//===-- lib/addsf3.c - Single-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI float\n__addsf3(float a, float b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_fadd(float a, float b)\n{\n    return __addsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/addvdi3.c",
    "content": "/* ===-- addvdi3.c - Implement __addvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI di_int\n__addvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a + (du_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/addvsi3.c",
    "content": "/* ===-- addvsi3.c - Implement __addvsi3 -----------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI si_int\n__addvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a + (su_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nvolatile unsigned int __sys_heap_pointer = (unsigned int)(&__sys_heap_pointer_reset);\n\nATOMIC_BIT_INIT(__heap_pointer);\n\n/* noinline, because part of grind tracked functions\n * Also used by seqread.inc\n */\nvoid *__noinline\nmem_alloc_nolock(size_t size)\n{\n    unsigned int pointer = __HEAP_POINTER;\n\n    if (size != 0) {\n        pointer = (pointer + 7) & ~7;\n\n        unsigned int new_heap_pointer, dummy;\n\n        __asm__ volatile(\"\\tadd %[nhp], %[ptr], %[sz], nc, . + 2\\n\"\n                         \"\\tfault \" __STR(__FAULT_ALLOC_HEAP_FULL__) \"\\n\"\n                                                                     \"\\tlbu %[dumb], %[nhp], -1\\n\"\n                         : [nhp] \"=r\"(new_heap_pointer), [dumb] \"=r\"(dummy)\n                         : [ptr] \"r\"(pointer), [sz] \"r\"(size));\n\n        __HEAP_POINTER = new_heap_pointer;\n    }\n    return (void *)pointer;\n}\n\nvoid *\nmem_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n    void *pointer = mem_alloc_nolock(size);\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n    return pointer;\n}\n\nvoid *\nmem_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    void *initial = &__sys_heap_pointer_reset;\n\n    __sys_heap_pointer = (unsigned int)initial;\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return (void *)initial;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ALLOC_H\n#define DPUSYSCORE_ALLOC_H\n\n/**\n * @file alloc.h\n * @brief Provides a way to manage heap allocation.\n *\n * @internal The heap is situated after the different kernel structures, local and global variables.\n *           It can grow until reaching the end of the WRAM. A reboot of the DPU reset the Heap.\n *           The current heap pointer can be accessed at the address defined by __HEAP_POINTER__.\n */\n\n#include <stddef.h>\n\n#include <fsb_allocator.h>\n#include <buddy_alloc.h>\n\n#include <attributes.h>\n\n/**\n * @fn mem_alloc\n * @brief Allocates a buffer of the given size in the heap.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * @param size the allocated buffer's size, in bytes\n * @throws a fault if there is no memory left\n * @return The allocated buffer address.\n */\nvoid *\nmem_alloc(size_t size);\n\n/**\n * @fn mem_reset\n * @brief Resets the heap.\n *\n * Every allocated buffer becomes invalid, since subsequent allocations restart from the beginning\n * of the heap.\n *\n * @return The heap initial address.\n */\nvoid *\nmem_reset(void);\n\n#endif /* DPUSYSCORE_ALLOC_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ashldi3.c",
    "content": "/* ====-- ashldi3.c - Implement __ashldi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashldi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a << b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashldi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.low = 0;\n        result.s.high = input.s.low << (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.low = input.s.low << b;\n        result.s.high = (input.s.high << b) | (input.s.low >> (bits_in_word - b));\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsl(di_int a, si_int b)\n{\n    return __ashldi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ashrdi3.c",
    "content": "/*===-- ashrdi3.c - Implement __ashrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: arithmetic a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        /* result.s.high = input.s.high < 0 ? -1 : 0 */\n        result.s.high = input.s.high >> (bits_in_word - 1);\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_lasr(di_int a, si_int b)\n{\n    return __ashrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/atomic_bit.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATOMIC_BIT_H\n#define DPUSYSCORE_ATOMIC_BIT_H\n\n/**\n * @file atomic_bit.h\n * @brief Provides direct access to the atomic bits.\n */\n\n#include <stdint.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n#define ATOMIC_BIT_GET(_name) __CONCAT(__atomic_bit_, _name)\n#define ATOMIC_BIT_INIT(_name) uint8_t __atomic_bit ATOMIC_BIT_GET(_name)\n#define ATOMIC_BIT_EXTERN(_name) extern ATOMIC_BIT_INIT(_name)\n\nextern uint8_t __atomic_start_addr;\n#define ATOMIC_BIT_INDEX(_name) (&ATOMIC_BIT_GET(_name) - &__atomic_start_addr)\n\n#define __ATOMIC_BIT_ACQUIRE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"acquire %[areg], %[abit], nz, .\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define __ATOMIC_BIT_RELEASE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"release %[areg], %[abit], nz, .+1\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define ATOMIC_BIT_ACQUIRE(_name) __asm__ volatile(\"acquire zero, %[abit], nz, .\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#define ATOMIC_BIT_RELEASE(_name) __asm__ volatile(\"release zero, %[abit], nz, .+1\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#endif /* DPUSYSCORE_ATOMIC_BIT_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/atomics.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Prototype of function can be found here: https://llvm.org/docs/Atomics.html\n */\n\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\n#define ATOMIC_BIT llvm_atomic_functions\nATOMIC_BIT_INIT(ATOMIC_BIT);\n\n#define FOR_ALL_TYPES(fct) fct(1, char) fct(2, short) fct(4, int) fct(8, long long)\n\n#define PROLOGUE(ptr, load, n_type)                                                                                              \\\n    n_type load;                                                                                                                 \\\n    ATOMIC_BIT_ACQUIRE(ATOMIC_BIT);                                                                                              \\\n    load = *ptr;\n\n#define EPILOGUE(load)                                                                                                           \\\n    ATOMIC_BIT_RELEASE(ATOMIC_BIT);                                                                                              \\\n    return load;\n\n#define __SYNC_VAL_COMPARE_AND_SWAP_N(n_val, n_type)                                                                             \\\n    n_type __dpu_sync_val_compare_and_swap_##n_val(volatile n_type *ptr, n_type expected, n_type desired)                        \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        if (load == expected)                                                                                                    \\\n            *ptr = desired;                                                                                                      \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_VAL_COMPARE_AND_SWAP_N)\n\n#define __SYNC_LOCK_TEST_AND_SET_N(n_val, n_type)                                                                                \\\n    n_type __dpu_sync_lock_test_and_set_##n_val(volatile n_type *ptr, n_type val)                                                \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = val;                                                                                                              \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_LOCK_TEST_AND_SET_N)\n\n#define __SYNC_FETCH_AND_DO_N(fct, fct_name, n_val, n_type)                                                                      \\\n    n_type __dpu_sync_fetch_and_##fct_name##_##n_val(volatile n_type *ptr, n_type val)                                           \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = fct(load, val, n_type);                                                                                           \\\n        EPILOGUE(load);                                                                                                          \\\n    }\n\n#define DO_ADD(a, b, n_type) ((a) + (b))\n#define __SYNC_FETCH_AND_ADD_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_ADD, add, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_ADD_N)\n\n#define DO_SUB(a, b, n_type) ((a) - (b))\n#define __SYNC_FETCH_AND_SUB_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_SUB, sub, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_SUB_N)\n\n#define DO_AND(a, b, n_type) ((a) & (b))\n#define __SYNC_FETCH_AND_AND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_AND, and, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_AND_N)\n\n#define DO_OR(a, b, n_type) ((a) | (b))\n#define __SYNC_FETCH_AND_OR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_OR, or, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_OR_N)\n\n#define DO_XOR(a, b, n_type) ((a) ^ (b))\n#define __SYNC_FETCH_AND_XOR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_XOR, xor, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_XOR_N)\n\n#define DO_NAND(a, b, n_type) (~((a) & (b)))\n#define __SYNC_FETCH_AND_NAND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_NAND, nand, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_NAND_N)\n\n#define DO_MAX(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MAX, max, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MAX_N)\n\n#define DO_UMAX(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMAX, umax, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMAX_N)\n\n#define DO_MIN(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MIN, min, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MIN_N)\n\n#define DO_UMIN(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMIN, umin, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMIN_N)\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/attributes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATTRIBUTES_H\n#define DPUSYSCORE_ATTRIBUTES_H\n\n/**\n * @file attributes.h\n * @brief Provides common useful compiler attributes.\n */\n\n#define DEPRECATED __attribute__((deprecated))\n\n#if __STDC_VERSION__ >= 201112L\n#define __NO_RETURN _Noreturn\n#else\n#define __NO_RETURN\n#endif /* __STDC_VERSION__ */\n\n#define __weak __attribute__((weak))\n\n#define __section(s) __attribute__((section(s)))\n\n#define __aligned(a) __attribute__((aligned(a)))\n\n#define __used __attribute__((used))\n\n#define __noinline __attribute__((noinline))\n\n#define __atomic_bit __section(\".atomic\")\n\n#define __dma_aligned __aligned(8)\n\n#define __keep __used __section(\".data.__sys_keep\")\n\n#define __host __aligned(8) __used __section(\".dpu_host\")\n\n// Use this macro at variable definition to place this variable into the section\n// .data.immediate_memory and then makes it possible to use this variable\n// directly as an immediate into load store instructions (and then avoids the need\n// to move the address into a register before): immediate values are 12 signed bits\n// large.\n#define __lower_data(name) __attribute__((used, section(\".data.immediate_memory.\" name)))\n\n/**\n * @def __mram_ptr\n * @brief An attribute declaring that a pointer is an address in MRAM.\n *\n * A typical usage is: ``unsigned int __mram_ptr * array32 = (unsigned int __mram_ptr *) 0xf000;``\n *\n * Performing a cast between a pointer in MRAM and a pointer in WRAM is not allowed by the compiler.\n *\n */\n#define __mram_ptr __attribute__((address_space(255)))\n\n#define __mram __mram_ptr __section(\".mram\") __dma_aligned __used\n\n#define __mram_noinit __mram_ptr __section(\".mram.noinit\") __dma_aligned __used\n\n#define __mram_keep __mram_ptr __section(\".mram.keep\") __dma_aligned __used\n\n#define __mram_noinit_keep __mram_ptr __section(\".mram.noinit.keep\") __dma_aligned __used\n\n#endif /* DPUSYSCORE_ATTRIBUTES_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/barrier.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <barrier.h>\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nvoid\nbarrier_wait(struct barrier_t *barrier)\n{\n    unsigned char lock = barrier->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = barrier->count;\n    unsigned char last = barrier->wait_queue;\n    unsigned char first;\n    thread_id_t tid = me();\n\n    /* Count = 1 means that I am the last to enter the barrier.\n     * Need to wake up everybody.*/\n    if (unlikely(count == 1)) {\n        if (likely(last != __EMPTY_WAIT_QUEUE)) {\n            first = __WAIT_QUEUE_TABLE[last];\n            while (first != last) {\n                __resume(first, \"0\");\n                first = __WAIT_QUEUE_TABLE[first];\n            }\n            __resume(first, \"0\");\n            barrier->wait_queue = __EMPTY_WAIT_QUEUE;\n            barrier->count = barrier->initial_count;\n        }\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    } else {\n        if (unlikely(last == __EMPTY_WAIT_QUEUE)) {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        } else {\n            first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        }\n\n        barrier->wait_queue = tid;\n        barrier->count = --count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/barrier.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BARRIER_H\n#define DPUSYSCORE_BARRIER_H\n\n/**\n * @file barrier.h\n * @brief Synchronization with barriers.\n *\n * This synchronization mechanism allows to suspend a fixed number of tasklets until the expected number of subscribers is\n * present. When the required number of tasklets reached the barrier, the counter of the barrier will be reinitialised to the\n * original value.\n *\n * @internal The barriers are represented by a static value, defining the number of expected tasklets, a counter for the\n *           current number of tasklets suspended by this barrier and a wait queue entry.\n *           Whenever a new tasklet reaches the barrier (barrier_wait), the counter is  decremented and the tasklet\n *           is put into the wait queue.\n *           If the counter is reduced to 0, all the tasklets that were suspended by this barrier will be resumed and\n *           the counter will be reinitialised to its initial value.\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef barrier_t\n * @brief A barrier object, as declared by BARRIER_INIT.\n */\ntypedef struct barrier_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} barrier_t;\n\n/**\n * @def BARRIER_INIT\n * @hideinitializer\n * @brief Declare and initialize a barrier associated to the given name.\n */\n/* clang-format off */\n#define BARRIER_INIT(_name, _counter)                                                                                            \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"barrier counter must be encoded on a byte\");                         \\\n    ATOMIC_BIT_INIT(__CONCAT(barrier_, _name));                                                                                  \\\n    extern barrier_t _name;                                                                                                      \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR( _name) \",@object\\n\"                                                                                  \\\n            \".globl \" __STR( _name) \"\\n\"                                                                                         \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(barrier_,_name))) \"\\n\"                                                        \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn barrier_wait\n * @brief Decrements the counter associated to the barrier and suspends the invoking tasklet.\n *\n * The counter of the barrier is decremented and the invoking tasklet is suspended until\n * the counter associated to the barrier is reduced to 0.\n *\n * @param barrier the barrier the tasklet will be associated to.\n */\nvoid\nbarrier_wait(barrier_t *barrier);\n\n#endif /* DPUSYSCORE_BARRIER_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/bswapdi2.c",
    "content": "/* ===-- bswapdi2.c - Implement __bswapdi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint64_t\n__bswapdi2(uint64_t u)\n{\n    return ((((u)&0xff00000000000000ULL) >> 56) | (((u)&0x00ff000000000000ULL) >> 40) | (((u)&0x0000ff0000000000ULL) >> 24)\n        | (((u)&0x000000ff00000000ULL) >> 8) | (((u)&0x00000000ff000000ULL) << 8) | (((u)&0x0000000000ff0000ULL) << 24)\n        | (((u)&0x000000000000ff00ULL) << 40) | (((u)&0x00000000000000ffULL) << 56));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/bswapsi2.c",
    "content": "/* ===-- bswapsi2.c - Implement __bswapsi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint32_t\n__bswapsi2(uint32_t u)\n{\n    return ((((u)&0xff000000) >> 24) | (((u)&0x00ff0000) >> 8) | (((u)&0x0000ff00) << 8) | (((u)&0x000000ff) << 24));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/buddy_alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <buddy_alloc.h>\n#include <alloc.h> //for mem_alloc\n#include <stddef.h> //for size_t\n#include <string.h> //for memset\n#include <dpuruntime.h>\n#include <errno.h>\n#include <defs.h>\n#include <stdbool.h>\n#include <built_ins.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nstatic unsigned char __buddy_init_done = 0;\nstatic int *__buddy_blocks = 0;\nstatic void *__buddy_heap_start = 0;\nstatic unsigned int __BUDDY_SIZE_OF_HEAP__ = 0;\nstatic unsigned char __BUDDY_MAX_POWER__ = 0;\nstatic unsigned char __BUDDY_NUMBER_OF_LEVELS__ = 0;\n\nATOMIC_BIT_INIT(__buddy_lock);\n\n#define __BUDDY_DEPTH_LEVELS__ 3\n#define __BUDDY_SHIFT_ADDRESS_TO_INDEX__ 4\n\nstatic inline unsigned int\nnext_power_of_2(int x)\n{\n    // in order to find the size of the block to allocate we\n    // count the number of leading zeros to get the correct\n    // log2(size)\n    // if size has only one \"1\" bit then we keep this power of 2\n    // otherwise, we add 1\n\n    unsigned int power_of_2 = 31 - count_leading_zeros(x);\n\n    if (count_population(x) != 1) {\n        power_of_2++;\n    }\n\n    return power_of_2;\n}\n\n/*\n * Note 1:\n *   each bit represents the state of a block. It can equal either 0 or 1 and can represent 4 different states of a block :\n *   target = 1 & buddy = 0                                      -> free                     : target block is [free] and can be\n * allocated without the need to cut the bigger block in half target = 1 & buddy = 1                                      -> not\n * in use               : neither target nor its buddy are in use and bigger blocks must be checked\n *\n *   target = 0 & both successors = 1 [not in use]               -> allocated                : this block is completely allocated\n *   target = 0 & one or both of the successors = 0 [allocated]  -> partially allocated      : block is partially allocated i.e.\n * at least one of the sub-blocks is [allocated]\n *\n * Note 2:\n *  Indexes of __buddy_blocks are indeed quite bizarre, which was a mistake during the conception stage. It doesn't change much.\n *  Indexe_in_level start from 0 from left to right, but not for the 5 least significant bits where they still start from 0 but\n * from right to left\n */\nvoid *\nsafe_buddy_alloc(size_t size)\n{\n    if ((size == 0) || (size > __BUDDY_SIZE_OF_HEAP__)) {\n        errno = EINVAL;\n        return NULL;\n    }\n\n    // we replace the size by the smallest 2 to the power of X such as it is greater than or equals the size\n    // afterwards, we take X as power_of_2 and thereby find the correct level to search for free blocks:\n    // blocks_level = __BUDDY_MAX_POWER__ - power_of_2\n    // for example if we try to allocate a block of 64 bytes (64=2^6), blocks_level = __BUDDY_MAX_POWER__ - 6\n\n    unsigned int power_of_2 = next_power_of_2(size);\n    int blocks_level = __BUDDY_MAX_POWER__ - power_of_2;\n\n    // if the size is smaller than the minimal size of\n    // block divided by 2, then we can't allocate a block\n    // so small and we have to allocate the block of the\n    // minimal allowed size\n    if (blocks_level >= __BUDDY_NUMBER_OF_LEVELS__) {\n        blocks_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n    }\n\n    // we browse all levels until we find the smallest free block that is big enough to contain \"size\" bytes\n    for (int blocks_level_current = blocks_level; blocks_level_current >= 0; --blocks_level_current) {\n        // we initialise index_in_level as the biggest index permitted in level\n        unsigned int index_in_level = 1 << blocks_level_current;\n\n        // levels 0-4 are in the same bitfield,\n        // level 5 consists of a single bitfield\n        // all other levels consist of 1<<(#level - 5)\n        // bitfields\n        unsigned int initial_number_of_current_bitfield = 0;\n        unsigned int loaded_case_mask;\n\n        switch (blocks_level_current) {\n            default:\n                initial_number_of_current_bitfield = ((1 << blocks_level_current) >> 5) - 1;\n                loaded_case_mask = 0xFFFFFFFF;\n                break;\n            case 0:\n                loaded_case_mask = 0x40000000;\n                break;\n            case 1:\n                loaded_case_mask = 0x30000000;\n                break;\n            case 2:\n                loaded_case_mask = 0x0F000000;\n                break;\n            case 3:\n                loaded_case_mask = 0x00FF0000;\n                break;\n            case 4:\n                loaded_case_mask = 0x0000FFFF;\n                break;\n        }\n\n        for (int number_of_current_bitfield = initial_number_of_current_bitfield; number_of_current_bitfield >= 0;\n             --number_of_current_bitfield, index_in_level -= 32) {\n            // sizes of levels in __buddy_blocks is a geometric\n            // series and thereby we can easily calculate the\n            // number of bitfields that precede the current level\n            unsigned int real_index = (1 << blocks_level_current) >> 5;\n            // we load the bitfield\n            unsigned int *initial_loaded_case_address\n                = (unsigned int *)(__buddy_blocks + number_of_current_bitfield + real_index);\n            // if we are in the very first bitfield\n            // that contains first 5 levels, then we\n            // need to make sure that buddy_free will\n            // ignore the bits that represent blocks\n            // that don't belong to blocks_level_current\n            unsigned int loaded_case = *initial_loaded_case_address & loaded_case_mask;\n\n            // this formula gives the number of zeros\n            // before the first pair of free/allocated blocks\n            // present in the current bitfield. If it equals\n            // 32, then no such pair is present.\n            unsigned int lz_before_first_pair_tmp = ((loaded_case << 1) ^ loaded_case) & 0xAAAAAAAA;\n\n            if (lz_before_first_pair_tmp != 0) {\n                unsigned int lz_before_first_pair = count_leading_zeros(lz_before_first_pair_tmp);\n                index_in_level = index_in_level - lz_before_first_pair - 1;\n\n                // if we are in the very first bitfield,\n                // then we need to take into account the special\n                // positioning of the 5 levels of blocks\n                // inside this bitfield\n                if (blocks_level_current < 5) {\n                    index_in_level += 1 << blocks_level_current;\n                }\n\n                unsigned int highlight_target_bit = 1 << index_in_level;\n\n                // if current level is among first 4\n                //(5th is unnecessary to consider)\n                // then we need to shift the mask\n                if (blocks_level_current < 4) {\n                    // we want to find the value of the offset to shift the mask for target and its buddy\n                    // offset = 32 - 2^(current_lvl+1)\n                    highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                }\n\n                // we have the position of a pair of\n                // free/allocated blocks, but we might\n                // need to shift this position by 1\n                // if the target's buddy is the potential\n                // block to allocate\n                loaded_case = loaded_case & highlight_target_bit;\n\n                if (loaded_case == 0) {\n                    highlight_target_bit = highlight_target_bit >> 1;\n                    index_in_level--;\n                }\n\n                // loaded_case have been modified if the first bitfield is handled\n                loaded_case = *initial_loaded_case_address;\n\n                // we mark the target bit as allocated\n                loaded_case -= highlight_target_bit;\n                *initial_loaded_case_address = loaded_case;\n\n                // if we have already had a free block of the necessary size,\n                // we return its address, otherwise we jump to\n                //__buddy_alloc_break_loop and start cutting the blocks\n                // in half until we get a block of the required size\n                if (blocks_level == blocks_level_current) {\n                    return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n                }\n\n                // we have already set the block to 0 [partially allocated]\n                // so we descend and start with the next one\n                blocks_level_current++;\n\n                while (blocks_level_current <= blocks_level) {\n                    index_in_level = index_in_level << 1;\n                    highlight_target_bit = 1 << index_in_level;\n\n                    // first 5 levels are stored in the same\n                    // bitfield. We need to handle this\n                    // special case and shift the mask\n                    int blocks_level_clamped = blocks_level_current - 4;\n\n                    if (blocks_level_clamped < 0) {\n                        highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                    }\n\n                    // we load the bitfield\n\n                    // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n                    unsigned int real_index = 0;\n                    blocks_level_clamped--;\n                    if (blocks_level_clamped >= 0) {\n                        real_index = 1 << blocks_level_clamped;\n                        blocks_level_clamped = index_in_level >> 5;\n                        real_index += blocks_level_clamped;\n                    }\n                    loaded_case = __buddy_blocks[real_index];\n\n                    // we mark the bit as allocated\n                    __buddy_blocks[real_index] = loaded_case - highlight_target_bit;\n\n                    // we continue to descend\n                    blocks_level_current++;\n                }\n\n                return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n            }\n        }\n    }\n\n    // if no level contains a big enough block, we return NULL\n    errno = ENOMEM;\n    return NULL;\n}\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nint\nbuddy_search_for_pointer(void *pointer, buddy_search_context_t context)\n{\n    // if the pointer is not aligned to 64 bits, then it is corrupted\n    // if the pointer is outside of the heap, we can do nothing\n    if (((((unsigned int)pointer) & 7) != 0) || (pointer < __buddy_heap_start)\n        || (pointer > (__buddy_heap_start + __BUDDY_SIZE_OF_HEAP__ - 1))) {\n        errno = EINVAL;\n        return -1;\n    }\n\n    // we transform the real address into an index for __buddy_blocks\n    // index_in_level = (pointer - START_OF_HEAP)>>__BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    unsigned int index_in_level = (pointer - __buddy_heap_start) >> __BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    // we start to search for the pointer from the lowest level\n    unsigned int target_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n\n    while (true) {\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        unsigned int highlight_target_bit = 1 << index_in_level;\n        unsigned int highlight_buddy_bit;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the\n        // same bitfield. We need to handle\n        // this special case and shift\n        // the masks\n        int target_level_clamped = target_level - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << target_level);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding to the index\n        // in __buddy_blocks\n        // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n        unsigned int real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index_in_level >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        unsigned int loaded_case = __buddy_blocks[real_index];\n\n        // We search for an allocated block\n        // if we are on the highest level, we quit.\n        if (((loaded_case & highlight_target_bit) == 0) || (target_level <= 0)) {\n            context->target_level = target_level;\n            context->real_index = real_index;\n            context->highlight_target_bit = highlight_target_bit;\n            context->highlight_buddy_bit = highlight_buddy_bit;\n            return index_in_level;\n        }\n\n        // Condition required to avoid unwanted release\n        if ((loaded_case & highlight_buddy_bit) == 0) {\n            errno = EINVAL;\n            return -1;\n        }\n\n        // we rise to the higher level\n        index_in_level = index_in_level >> 1;\n        target_level--;\n    }\n}\n\nstatic void\nbuddy_free_fusion_of_blocks(unsigned int index, buddy_search_context_t context)\n{\n    unsigned int real_index = context->real_index;\n    unsigned int current_level_freeing = context->target_level;\n    unsigned int highlight_target_bit = context->highlight_target_bit;\n    unsigned int highlight_buddy_bit = context->highlight_buddy_bit;\n    unsigned int loaded_case = __buddy_blocks[real_index];\n    // if we are at the highest level, there is nothing to fuse\n    while (current_level_freeing > 0) {\n        // fusion occurs only when both blocks are free\n        if (((loaded_case & highlight_target_bit) == 0) | ((loaded_case & highlight_buddy_bit) == 0)) {\n            return;\n        }\n\n        // index of predecessor = index of successor >> 1\n        index = index >> 1;\n        // we rise to the higher level\n        current_level_freeing--;\n\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        highlight_target_bit = 1 << index;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the same bitfield.\n        // We need to handle this special case and shift\n        // the masks\n        int target_level_clamped = current_level_freeing - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << current_level_freeing);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding\n        // to the index in __buddy_blocks\n        //\n        // As both sub-blocks were freed, their \"father\"\n        // must be marked as free.\n        real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        loaded_case = __buddy_blocks[real_index] | highlight_target_bit;\n        __buddy_blocks[real_index] = loaded_case;\n    }\n}\n\nvoid\nsafe_buddy_free(void *pointer)\n{\n    struct _buddy_search_context_t context;\n\n    int index = buddy_search_for_pointer(pointer, &context);\n\n    if (index != -1) {\n        __buddy_blocks[context.real_index] |= context.highlight_target_bit;\n        buddy_free_fusion_of_blocks(index, &context);\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline *\nbuddy_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = safe_buddy_alloc(size);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_free(void *pointer)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    safe_buddy_free(pointer);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n\n/*if the size of the smallest block needs to be changed, then only 2 things need to change :\n *  __BUDDY_DEPTH_LEVELS__ here in buddy_init.c\n *  __BUDDY_SHIFT_ADDRESS_TO_INDEX__ in buddy_defs.s\n *\n *  When the minimal size of a block needs to be 32 bytes, then these two constants must equal 4 and 5 correspondingly\n *  If minimal size needs to be 16 bytes, then these two constants must equal 3 and 4 correspondingly\n *  If minimal size needs to be 8 bytes, then these two constants must equal 2 and 3 correspondingly\n *\n *  Also, certain tests (Global, Reset, LevelByLevel) should also be changed.\n */\n\n// TODO: Right now the size must be of power of 2 : 2048, 4096, 8192 and it won't work with other sizes.\n// TODO: There is no point in accepting other sizes, as the whole idea of having buddy allocation is based on it.\n// TODO: Right now the possibility of failure of mem_alloc is not taken into account of.\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_init(size_t size_of_heap)\n{\n    if (__buddy_init_done == 0) {\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n\n        __BUDDY_SIZE_OF_HEAP__ = size_of_heap;\n\n        unsigned int power_of_2 = count_leading_zeros(size_of_heap);\n        __BUDDY_MAX_POWER__ = (31 - power_of_2);\n\n        __BUDDY_NUMBER_OF_LEVELS__ = __BUDDY_MAX_POWER__ - __BUDDY_DEPTH_LEVELS__;\n\n        unsigned int blocks_in_buddy_blocks = (1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2;\n        __buddy_blocks = mem_alloc(size_of_heap + blocks_in_buddy_blocks);\n\n        __buddy_heap_start = __buddy_blocks + (blocks_in_buddy_blocks >> 2);\n\n        __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n        memset(&__buddy_blocks[1], 0xff, blocks_in_buddy_blocks - 4); // in order to initialize the __buddy_blocks structure\n        __buddy_init_done = 1;\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n\n    __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n    memset(&__buddy_blocks[1],\n        0xff,\n        ((1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2) - 4); // in order to initialize the __buddy_blocks structure\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/buddy_alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BUDDY_ALLOC_H\n#define DPUSYSCORE_BUDDY_ALLOC_H\n\n/**\n * @file buddy_alloc.h\n * @brief Dynamic memory allocation and freeing.\n *\n * This library allows to create unique memory space in the heap to allocate and free\n * blocks of data.\n *\n * The memory space is initialized with <code>buddy_init</code>, which must be invoked only once during\n * the program's lifecycle.\n *\n * Functions can then dynamically get and free buffers, using <code>buddy_alloc</code> and <code>buddy_free</code>\n * respectively.\n *\n * In this implementation, the allocatable buffer size is chosen during the first call to <code>buddy_init</code>.\n * Tested sizes : 2048, 4096, 8192, 16384 and 32768 bytes\n * The allocated buffers are properly aligned on DMA transfer constraints, so that they can be\n * used as is in MRAM/WRAM transfer operations.\n */\n\n/*\n * @internal The algorithm used in this implementation is Buddy memory allocation.\n *\n * A particularity of this implementation is that no headers are created and thereby\n * the memory consumption of the heap is reduced. The drawback is a slight slow-down\n * in speed of memory freeing.\n *\n * Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free. If the pointer given in the parameter\n *   is not currently allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>, <code>buddy_free</code>\n *   will do nothing.\n *\n */\n\n#include <stddef.h>\n\n/**\n * @fn buddy_init\n * @brief Allocates size_of_heap bytes for a heap that <code>buddy_alloc</code> can access to.\n *\n * Reserves memory space in the heap used to perform dynamic allocation and release of buffers.\n *\n * @param size_of_heap the size of heap in bytes that <code>buddy_alloc</code> can access to\n */\nvoid\nbuddy_init(size_t size_of_heap);\n\n/**\n * @fn buddy_reset\n * @brief Resets the heap.\n *\n * Quickly frees all pointers allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>.\n * Warning : currently buddy_reset() doesn't reset the size of the allocated heap.\n */\nvoid\nbuddy_reset(void);\n\n/**\n * @fn buddy_alloc\n * @brief Allocates a buffer of the given size in the heap, in a runtime-safe way.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * Due to the idea of the buddy algorithm (to decrease external fragmentation),\n * the allocated blocks will be of size equal to a power of 2. In other words,\n * if the user allocates 33 bytes, 64 bytes will be allocated and when 2049 bytes\n * are requested, 4096 will be allocated. The user might want to take this into\n * account if she/he wishes to minimise the memory consumption.\n *\n * The minimal size of the allocated block is 16 bytes, but can easily be changed in\n * future implementations, so <code>buddy_alloc</code> is mostly adapted to allocating medium and\n * big structures, such as arrays containing more than 8 bytes (in order to make sure\n * that not too much memory space is wasted), binary trees or linked lists.\n *\n * If the <code>size</code> passed in parameter is less or equal to 0 or greater than the size of heap,\n * errno will be set to EINVAL and <code>buddy_alloc</code> will do nothing.\n * If <code>buddy_alloc</code> fails to find enough free memory space to allocate, errno will be\n * set to ENOMEM.\n *\n * @param size the allocated buffer's size, in bytes\n * @return A pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_alloc(size_t size);\n\n/**\n * @fn buddy_free\n * @brief Frees a specified pointer, in a runtime-safe way.\n *\n *  Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free and will see a pointer to the beginning of the\n *   block in the same way as the pointer to anywhere inside the block. For example, if we have\n *   allocated an int array[10], <code>buddy_free</code> will treat &array[0] the same way as &array[1]\n *   or as the address of any other element inside this array and will free the whole block.\n *\n * If the pointer given in the parameter is not currently allocated by <code>buddy_alloc</code> or\n * <code>buddy_realloc</code>, <code>buddy_free</code> will do nothing.\n *\n * This function frees the memory space pointed to by pointer, which\n * must have been returned by a previous call to <code>buddy_alloc</code> or <code>buddy_realloc</code>\n * If it wasn't or if <code>buddy_free</code> has already been called for this pointer before,\n * then <code>buddy_free</code> will do nothing. If pointer is NULL, no operation is performed.\n * If the pointer passed as a parameter is not aligned to 64 bits or if it is outside\n * of the allocated heap errno will be set to EINVAL.\n * If <code>buddy_free</code> detects the attempt to free a non-allocated pointer, it will equally\n * set errno to EINVAL.\n *\n * @param pointer the pointer to the block to free\n */\nvoid\nbuddy_free(void *pointer);\n\n/**\n * @fn buddy_realloc\n * @brief Changes the size of the memory block pointed to by <code>ptr</code> to <code>size</code> bytes in a runtime-safe way.\n *\n * The contents will be unchanged in the range from the start of the region up to the minimum of the old and new sizes.\n * If the new <code>size</code> is larger than the old size, the added memory will not be initialized.\n * If <code>ptr</code> is NULL, then the call is equivalent to <code>buddy_alloc(size)</code> for all values of <code>size</code>.\n * If <code>size</code> is equal to zero, and <code>ptr</code> is not NULL, then the call is equivalent to\n * <code>buddy_free(ptr)</code> and the return value will be equal to the pointer passed as the parameter. Unless <code>ptr</code>\n * is NULL, it should have been returned by an earlier call to <code>buddy_alloc()</code> or <code>buddy_realloc()</code>. If it\n * wasn't, then <code>buddy_realloc()</code> will try to find this pointer among the allocated ones, but undefined behavior might\n * occur.\n *\n * If new <code>size</code> is smaller than the old size, then the remaining memory will potentially be released (depends\n * on the size of block).\n *\n * <code>buddy_realloc()</code> internally calls <code>buddy_alloc</code> and <code>buddy_free</code> and thereby will set errno\n * to ENOMEM or EINVAL on failure.\n *\n * @param ptr original pointer\n * @param size the new allocated buffer's size, in bytes\n * @return A new (or the same) pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_realloc(void *ptr, size_t size);\n\n#endif /* DPUSYSCORE_BUDDY_ALLOC_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/buddy_realloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n// todo integrate in buddy_alloc.c, when we have reduced the buddy_alloc object file size\n\n#include <buddy_alloc.h>\n#include <stddef.h>\n#include <alloc.h>\n#include <string.h> //for memcpy\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nATOMIC_BIT_EXTERN(__buddy_lock);\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nextern void *\nsafe_buddy_alloc(size_t size);\nextern void\nsafe_buddy_free(void *ptr);\nextern int\nbuddy_search_for_pointer(void *ptr, buddy_search_context_t context);\n\nstatic int\nbuddy_sizeofblock(void *pointer)\n{\n    // We get the pointer (address) as the parameter and look for any allocated block that starts at this address.\n    // If it is allocated, it will be found and its size will be returned.\n    // If it is currently non allocated, buddy_sizeofblock will do nothing.\n    struct _buddy_search_context_t dummy;\n    int index = buddy_search_for_pointer(pointer, &dummy);\n\n    if (index == -1) {\n        return -1;\n    }\n\n    return 1 << (12 - index);\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nbuddy_realloc(void *ptr, size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = ptr;\n    if (ptr == NULL) { // if ptr == NULL, then buddy_realloc must behave as buddy_alloc\n        result = safe_buddy_alloc(size);\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n        return result; //\n    }\n\n    if (size == 0) { // if size == 0 and ptr != NULL, then buddy_realloc behaves as buddy_free\n        safe_buddy_free(ptr); //\n        ATOMIC_BIT_RELEASE(__buddy_lock); //\n        return ptr; //\n    }\n\n    size_t size_block = buddy_sizeofblock(ptr);\n\n    if (size_block == ((size_t)-1)) { // size_block is set to -1 if ptr was not found among\n        ATOMIC_BIT_RELEASE(__buddy_lock); // allocated pointers and that there is nothing to do\n        return NULL;\n    }\n\n    if (size <= (size_block >> 1)) { // if newly allocated block is smaller than the currently allocated block\n        size_block = size; // we will only copy \"size\" bytes\n    } else if (size <= size_block) { // if newly allocated block is of the same size as the currently allocated block\n        ATOMIC_BIT_RELEASE(__buddy_lock); // then there is no reason to do anything\n        return ptr;\n    }\n\n    safe_buddy_free(ptr); // newly allocated block is either bigger or smaller than the currently allocated\n    result = safe_buddy_alloc(size); // block and we need to call buddy_alloc to be sure that external fragmentation\n    memcpy(result, ptr, size_block); // is avoided.\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/built_ins.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef BUILT_INS_H\n#define BUILT_INS_H\n\n/**\n * @file built_ins.h\n * @brief Provides access to the built-in functions\n *\n * Automatically generated by the DPU assembler\n */\n\n#define __builtin_nor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rri(rc, ra, shift) __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zri(zero, ra, shift) __asm__(\"lsr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrr(zero, ra, rb) __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_boot_rici(ra, imm, boot_cc, pc) __asm__(\"boot %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_erii(endian, ra, off, imm) __asm__(\"sb \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_esii(endian, sa, off, imm) __asm__(\"sb \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsl_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rri(rc, ra, shift) __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zri(zero, ra, shift) __asm__(\"lsl %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrr(zero, ra, rb) __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sw_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_erii(endian, ra, off, imm) __asm__(\"sw \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_esii(endian, sa, off, imm) __asm__(\"sw \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_asr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rri(rc, ra, imm) __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zri(zero, rb, imm) __asm__(\"addc %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrici(rc, ra, imm, add_nz_cc, pc)                                                                         \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrici(zero, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                          \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrr(zero, ra, rb) __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_u_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_u_rr(dc, rb) __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_s_rci(dc, true_cc, pc) __asm__(\"time.s %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_s_r(dc) __asm__(\"time.s %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_call_rri(rc, ra, off) __asm__(\"call %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_zri(zero, ra, off) __asm__(\"call %[zero], %[ra_r32], \" off \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"call %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_call_zrr(zero, ra, rb) __asm__(\"call %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zri(zero, ra, shift) __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrr(zero, ra, rb) __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_stop_ci(boot_cc, pc) __asm__(\"stop \" boot_cc \", \" pc \"\" :::)\n\n#define __builtin_ldmai_rri(ra, rb, immDma)                                                                                      \\\n    __asm__(\"ldmai %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_rrci(rc, rb, true_cc, pc)                                                                             \\\n    __asm__(\"time_cfg %[rc_wr32], %[rb_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zrci(zero, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg %[zero], %[rb_wr32], \" true_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_rr(rc, rb) __asm__(\"time_cfg %[rc_wr32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zr(zero, rb) __asm__(\"time_cfg %[zero], %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rri(rc, ra, imm) __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zri(zero, rb, imm) __asm__(\"or %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrici(rc, ra, imm, log_nz_cc, pc)                                                                           \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrici(zero, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rric(rc, ra, imm, log_set_cc)                                                                               \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zric(zero, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrif(rc, ra, imm, false_cc)                                                                                 \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrif(zero, ra, imm, false_cc) __asm__(\"or %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                            \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrrc(rc, ra, rb, log_set_cc)                                                                                \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrrc(zero, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrr(rc, ra, rb)                                                                                             \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrr(zero, ra, rb) __asm__(\"or %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cao_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rr(dc, ra) __asm__(\"cao.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zri(zero, ra, shift) __asm__(\"lsrx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrr(zero, ra, rb) __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rr(dc, ra) __asm__(\"cls.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sd_erir(endian, ra, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[ra_r32], \" off \", %[db_wr64]\" ::[ra_r32] \"r\"(ra), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_erii(endian, ra, off, imm) __asm__(\"sd \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sd_esir(endian, sa, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[sa_r32], \" off \", %[db_wr64]\" ::[sa_r32] \"r\"(sa), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_esii(endian, sa, off, imm) __asm__(\"sd \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsrx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sdma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"sdma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zri(zero, ra, shift) __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_zrr(zero, ra, rb) __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_time_u_rci(dc, true_cc, pc) __asm__(\"time.u %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_u_r(dc) __asm__(\"time.u %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_subc_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rr(dc, ra) __asm__(\"clo.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_zrr(zero, ra, rb) __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrr(zero, ra, rb) __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rir(rc, imm, ra) __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zir(zero, imm, rb) __asm__(\"sub %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirc(rc, imm, ra, sub_set_cc)                                                                              \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirc(zero, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirf(rc, imm, ra, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirf(zero, imm, ra, false_cc) __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rric(rc, ra, imm, ext_sub_set_cc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zric(zero, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrif(zero, ra, imm, false_cc) __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_ssi(sc, sa, imm) __asm__(\"sub %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sub_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"sub %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_sub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                          \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_zrr(zero, ra, rb) __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsb_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrc(zero, ra, log_set_cc) __asm__(\"extsb %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rr(rc, ra) __asm__(\"extsb %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zr(zero, ra) __asm__(\"extsb %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_movd_rrci(dc, db, true_false_cc, pc)                                                                           \\\n    __asm__(\"movd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_lsl1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zri(zero, ra, shift) __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_zrr(zero, ra, rb) __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rr(dc, ra) __asm__(\"sats.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rri(rc, ra, imm) __asm__(\"and %[rc_wr32], %[ra_wr32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_wr32] \"r\"(ra) :)\n\n#define __builtin_and_zri(zero, rb, imm) __asm__(\"and %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrif(zero, ra, imm, false_cc) __asm__(\"and %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrr(zero, ra, rb) __asm__(\"and %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrc(zero, ra, log_set_cc) __asm__(\"cls %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rr(rc, ra) __asm__(\"cls %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zr(zero, ra) __asm__(\"cls %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrrc(rc, ra, rb, sub_set_cc)                                                                              \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrrc(zero, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrr(zero, ra, rb) __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_div_step_rrrici(dc, ra, db, shift, div_cc, pc)                                                                 \\\n    __asm__(\"div_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" div_cc \", \" pc \"\"                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_rol_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rri(rc, ra, shift) __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zri(zero, ra, shift) __asm__(\"rol %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrr(zero, ra, rb) __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_swapd_rrci(dc, db, true_false_cc, pc)                                                                          \\\n    __asm__(\"swapd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_add_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrr(zero, ra, rb) __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_s_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_id_erii(endian, ra, off, imm) __asm__(\"sb_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rki(dc, ra, imm) __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nop_() __asm__(\"nop \" :::)\n\n#define __builtin_sd_id_erii(endian, ra, off, imm) __asm__(\"sd_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_id_erii(endian, ra, off, imm) __asm__(\"sh_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrc(zero, ra, log_set_cc) __asm__(\"extsh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rr(rc, ra) __asm__(\"extsh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zr(zero, ra) __asm__(\"extsh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_acquire_rici(ra, imm, acquire_cc, pc)                                                                          \\\n    __asm__(\"acquire %[ra_r32], \" imm \", \" acquire_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rri(rc, ra, imm) __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zri(zero, rb, imm) __asm__(\"xor %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrif(zero, ra, imm, false_cc) __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrr(zero, ra, rb) __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zri(zero, ra, shift) __asm__(\"lslx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrr(zero, ra, rb) __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrr(zero, ra, rb) __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rr(dc, ra) __asm__(\"clo.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rr(dc, ra) __asm__(\"extsh.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rri(rc, ra, shift) __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zri(zero, ra, shift) __asm__(\"ror %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrr(zero, ra, rb) __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_fault_i(imm) __asm__(\"fault \" imm \"\" :::)\n\n#define __builtin_clz_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rr(dc, ra) __asm__(\"clz.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rri(dc, rb, imm) __asm__(\"or.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_s_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sats_rrci(rc, ra, log_nz_cc, pc)                                                                               \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrci(zero, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rrc(rc, ra, log_set_cc)                                                                                   \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrc(zero, ra, log_set_cc) __asm__(\"sats %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rr(rc, ra) __asm__(\"sats %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zr(zero, ra) __asm__(\"sats %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_erri(endian, rc, ra, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lw_ersi(endian, rc, sa, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extsb_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rr(dc, ra) __asm__(\"extsb.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rr(dc, rb) __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrc(zero, ra, log_set_cc) __asm__(\"cao %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rr(rc, ra) __asm__(\"cao %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zr(zero, ra) __asm__(\"cao %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrc(zero, ra, log_set_cc) __asm__(\"extuh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rr(rc, ra) __asm__(\"extuh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zr(zero, ra) __asm__(\"extuh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_u_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rki(dc, ra, imm) __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrif(zero, ra, imm, false_cc) __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrr(zero, ra, rb) __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrc(zero, ra, log_set_cc) __asm__(\"clo %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rr(rc, ra) __asm__(\"clo %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zr(zero, ra) __asm__(\"clo %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extub_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrc(zero, ra, log_set_cc) __asm__(\"extub %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rr(rc, ra) __asm__(\"extub %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zr(zero, ra) __asm__(\"extub %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_id_erii(endian, ra, off, imm) __asm__(\"sw_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_rci(rc, true_cc, pc) __asm__(\"time %[rc_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_zci(zero, true_cc, pc) __asm__(\"time %[zero], \" true_cc \", \" pc \"\" :::)\n\n#define __builtin_time_r(rc) __asm__(\"time %[rc_wr32]\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_z(zero) __asm__(\"time %[zero]\" :::)\n\n#define __builtin_asr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rri(rc, ra, shift) __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zri(zero, ra, shift) __asm__(\"asr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrr(zero, ra, rb) __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ldma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"ldma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ld_erri(endian, dc, ra, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ld_ersi(endian, dc, sa, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[sa_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cls_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rr(dc, ra) __asm__(\"cls.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rr(dc, ra) __asm__(\"extuh.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rr(dc, ra) __asm__(\"sats.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_resume_rici(ra, imm, boot_cc, pc) __asm__(\"resume %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cao_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rr(dc, ra) __asm__(\"cao.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rr(dc, ra) __asm__(\"clz.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zri(zero, ra, shift) __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrr(zero, ra, rb) __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrc(rc, ra, rb, sub_set_cc)                                                                             \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrc(zero, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_zrr(zero, ra, rb) __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rri(rc, ra, imm) __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zri(zero, rb, imm) __asm__(\"add %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrici(rc, ra, imm, add_nz_cc, pc)                                                                          \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrici(zero, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrif(zero, ra, imm, false_cc) __asm__(\"add %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_ssi(sc, sa, imm) __asm__(\"add %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_add_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                           \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrr(zero, ra, rb) __asm__(\"add %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"add %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_nor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrif(zero, ra, imm, false_cc) __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrr(zero, ra, rb) __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rri(dc, rb, imm) __asm__(\"or.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_u_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rir(rc, imm, ra) __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zir(zero, imm, rb) __asm__(\"subc %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirc(rc, imm, ra, sub_set_cc)                                                                             \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirc(zero, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirf(rc, imm, ra, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirf(zero, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rric(rc, ra, imm, ext_sub_set_cc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zric(zero, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                         \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_zrr(zero, ra, rb) __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extub_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rr(dc, ra) __asm__(\"extub.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrr(zero, ra, rb) __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_release_rici(ra, imm, release_cc, pc)                                                                          \\\n    __asm__(\"release %[ra_r32], \" imm \", \" release_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clz_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrc(zero, ra, log_set_cc) __asm__(\"clz %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rr(rc, ra) __asm__(\"clz %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zr(zero, ra) __asm__(\"clz %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_step_rrrici(dc, ra, db, shift, boot_cc, pc)                                                                \\\n    __asm__(\"mul_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" boot_cc \", \" pc \"\"                                         \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_sh_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_erii(endian, ra, off, imm) __asm__(\"sh \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_esii(endian, sa, off, imm) __asm__(\"sh \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lbu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#endif /* BUILT_INS_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/clzdi2.c",
    "content": "/* ===-- clzdi2.c - Implement __clzdi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.high == 0);\n    return __builtin_clz((x.s.high & ~f) | (x.s.low & f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/clzsi2.c",
    "content": "/* ===-- clzsi2.c - Implement __clzsi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0xFFFF0000) == 0) << 4; /* if (x is small) t = 16 else 0 */\n    x >>= 16 - t; /* x = [0 - 0xFFFF] */\n    su_int r = t; /* r = [0, 16] */\n    /* return r + clz(x) */\n    t = ((x & 0xFF00) == 0) << 3;\n    x >>= 8 - t; /* x = [0 - 0xFF] */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + clz(x) */\n    t = ((x & 0xF0) == 0) << 2;\n    x >>= 4 - t; /* x = [0 - 0xF] */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + clz(x) */\n    t = ((x & 0xC) == 0) << 1;\n    x >>= 2 - t; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + clz(x) */\n    /*     switch (x)\n     *     {\n     *     case 0:\n     *         return r + 2;\n     *     case 1:\n     *         return r + 1;\n     *     case 2:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - x) & -((x & 2) == 0));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/cmpdi2.c",
    "content": "/* ===-- cmpdi2.c - Implement __cmpdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __cmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__cmpdi2(di_int a, di_int b)\n{\n    dwords x;\n    x.all = a;\n    dwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_lcmp(di_int a, di_int b)\n{\n    return __cmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/comparedf2.c",
    "content": "//===-- lib/comparedf2.c - Double-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// // This file implements the following soft-float comparison routines:\n//\n//   __eqdf2   __gedf2   __unorddf2\n//   __ledf2   __gtdf2\n//   __ltdf2\n//   __nedf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __ledf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gedf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unorddf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __ledf2( ) and __gedf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ledf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a floating-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpdf2, __ledf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gedf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unorddf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nedf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtdf2(fp_t a, fp_t b)\n{\n    return __gedf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_dcmpun(fp_t a, fp_t b)\n{\n    return __unorddf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/comparesf2.c",
    "content": "//===-- lib/comparesf2.c - Single-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements the following soft-fp_t comparison routines:\n//\n//   __eqsf2   __gesf2   __unordsf2\n//   __lesf2   __gtsf2\n//   __ltsf2\n//   __nesf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __lesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unordsf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__lesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a fp_ting-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpsf2, __lesf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unordsf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nesf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtsf2(fp_t a, fp_t b)\n{\n    return __gesf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_fcmpun(fp_t a, fp_t b)\n{\n    return __unordsf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ctzdi2.c",
    "content": "/* ===-- ctzdi2.c - Implement __ctzdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits  */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.low == 0);\n    return __builtin_ctz((x.s.high & f) | (x.s.low & ~f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ctzsi2.c",
    "content": "/* ===-- ctzsi2.c - Implement __ctzsi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0x0000FFFF) == 0) << 4; /* if (x has no small bits) t = 16 else 0 */\n    x >>= t; /* x = [0 - 0xFFFF] + higher garbage bits */\n    su_int r = t; /* r = [0, 16]  */\n    /* return r + ctz(x) */\n    t = ((x & 0x00FF) == 0) << 3;\n    x >>= t; /* x = [0 - 0xFF] + higher garbage bits */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + ctz(x) */\n    t = ((x & 0x0F) == 0) << 2;\n    x >>= t; /* x = [0 - 0xF] + higher garbage bits */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + ctz(x) */\n    t = ((x & 0x3) == 0) << 1;\n    x >>= t;\n    x &= 3; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + ctz(x) */\n\n    /*  The branch-less return statement below is equivalent\n     *  to the following switch statement:\n     *     switch (x)\n     *    {\n     *     case 0:\n     *         return r + 2;\n     *     case 2:\n     *         return r + 1;\n     *     case 1:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - (x >> 1)) & -((x & 1) == 0));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/defs.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nint\ncheck_stack()\n{\n    unsigned int stack_base, stack_size;\n    int stack_limit, remaining;\n    thread_id_t tid = me();\n\n    stack_base = __SP_TABLE__[tid].stack_ptr;\n    stack_size = __SP_TABLE__[tid].stack_size;\n    stack_limit = (int)(stack_base + stack_size);\n    __asm__ volatile(\"sub %[r], %[l], r22\" : [r] \"=r\"(remaining) : [l] \"r\"(stack_limit));\n\n    return remaining;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/defs.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEFS_H\n#define DPUSYSCORE_DEFS_H\n\n#include <sysdef.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n/**\n * @file defs.h\n * @brief Miscellaneous system functions.\n *\n * General purpose definitions.\n */\n\n#if __STDC_VERSION__ >= 201112L\n#define __ATTRIBUTE_NO_RETURN__ _Noreturn\n#else\n#define __ATTRIBUTE_NO_RETURN__\n#endif /* __STDC_VERSION__ */\n\n/**\n * @fn me\n * @internal This just returns the value of the special register id.\n * @return The current tasklet's sysname.\n */\nstatic inline sysname_t\nme()\n{\n    return __builtin_dpu_tid();\n}\n\n/**\n * @fn halt\n * @brief Halts the DPU.\n * @throws FAULT_HALT always\n */\n__ATTRIBUTE_NO_RETURN__ static inline void\nhalt()\n{\n    __builtin_trap();\n    __builtin_unreachable();\n}\n\n/**\n * @fn check_stack\n * @return the number of unused 32-bits words in the current runtime's stack.\n *         If the number is negative, it indicates by how much 32-bits words the stack overflowed.\n *\n * @internal This fetches the position of the next stack in memory from the Stack Pointer Table (cf. tasklet.h)\n *           and compute the remaining bytes.\n */\nint\ncheck_stack();\n\n#endif /* DPUSYSCORE_DEFS_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/devprivate.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEVPRIVATE_H\n#define DPUSYSCORE_DEVPRIVATE_H\n\n/**\n * @file devprivate.h\n * @brief Reserved for internal use ... please do not use those functions unless you know exactly what you do.\n */\n\n/**\n * @def tell\n * @brief On a simulator, injects a tell instruction to print out developer debug info.\n * @nolink\n *\n * @warning This function will not work on a target different from simulator.\n *\n * @param reg a register\n * @param val a constant value\n */\n#define tell(reg, val) __asm__(\"tell %[r], \" val : : [r] \"r\"(reg) :)\n\n#endif /* DPUSYSCORE_DEVPRIVATE_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/div32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __udiv32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"  clz r3, r1, max, __udiv32_division_by_zero\\n\" // r3 = by how many the divider can be shifted on 32-bit\n                     \"  clz r4, r0\\n\" // r4 = number of useless bits of the dividend\n                     \"  sub r3, r4, r3, gtu, __udiv32_result_0\\n\" // r3 = the maximal shift to be done\n                     \"  move r4, r1\\n\"\n                     \"  move.u d0, r0\\n\"\n                     \"  jump r3, __udiv32_base\\n\" // As we will jump backward relatively to __udiv32_base\n                     \"  div_step d0, r4, d0, 31\\n\"\n                     \"  div_step d0, r4, d0, 30\\n\"\n                     \"  div_step d0, r4, d0, 29\\n\"\n                     \"  div_step d0, r4, d0, 28\\n\"\n                     \"  div_step d0, r4, d0, 27\\n\"\n                     \"  div_step d0, r4, d0, 26\\n\"\n                     \"  div_step d0, r4, d0, 25\\n\"\n                     \"  div_step d0, r4, d0, 24\\n\"\n                     \"  div_step d0, r4, d0, 23\\n\"\n                     \"  div_step d0, r4, d0, 22\\n\"\n                     \"  div_step d0, r4, d0, 21\\n\"\n                     \"  div_step d0, r4, d0, 20\\n\"\n                     \"  div_step d0, r4, d0, 19\\n\"\n                     \"  div_step d0, r4, d0, 18\\n\"\n                     \"  div_step d0, r4, d0, 17\\n\"\n                     \"  div_step d0, r4, d0, 16\\n\"\n                     \"  div_step d0, r4, d0, 15\\n\"\n                     \"  div_step d0, r4, d0, 14\\n\"\n                     \"  div_step d0, r4, d0, 13\\n\"\n                     \"  div_step d0, r4, d0, 12\\n\"\n                     \"  div_step d0, r4, d0, 11\\n\"\n                     \"  div_step d0, r4, d0, 10\\n\"\n                     \"  div_step d0, r4, d0, 9\\n\"\n                     \"  div_step d0, r4, d0, 8\\n\"\n                     \"  div_step d0, r4, d0, 7\\n\"\n                     \"  div_step d0, r4, d0, 6\\n\"\n                     \"  div_step d0, r4, d0, 5\\n\"\n                     \"  div_step d0, r4, d0, 4\\n\"\n                     \"  div_step d0, r4, d0, 3\\n\"\n                     \"  div_step d0, r4, d0, 2\\n\"\n                     \"  div_step d0, r4, d0, 1\\n\"\n                     \"__udiv32_base:\\n\"\n                     \"  div_step d0, r4, d0, 0\\n\"\n                     \"__udiv32_exit:\\n\"\n                     \"  jump r23\\n\"\n                     \"__udiv32_result_0:\\n\"\n                     \"  move.u d0, r0, true, __udiv32_exit\\n\"\n                     \"__udiv32_division_by_zero:\\n\"\n                     \"  fault \"__STR(__FAULT_DIVISION_BY_ZERO__));\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __div32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"sd r22, 0, d22\\n\"\n                     \"add r22, r22, 8\\n\"\n                     // The quotient's sign depends on the sign of the dividend and divider... After few tries it sounds\n                     // like the quickest way to select the operators is to branch according to the cases.\n                     \"  clo r3, r0, z, __div32_pos_dividend\\n\"\n                     \"  clo r3, r1, z, __div32_neg_dividend_pos_divider\\n\"\n                     \"__div32_neg_dividend_neg_divider:\\n\" // As a result, the quotient is positive and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1, true, __div32_exit\\n\"\n                     \"__div32_neg_dividend_pos_divider:\\n\" // As a result, the quotient is negative and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend:\\n\"\n                     \"  clo r3, r1, z, __div32_pos_dividend_pos_divider\\n\"\n                     \"  neg r1, r1\\n\" // As a result, the quotient is negative and the remainder positive\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend_pos_divider:\\n\" // The dividend and divider are both positive\n                     \"  call r23, __udiv32\\n\"\n                     \"__div32_exit:\\n\"\n                     \"  ld d22, r22, -8\\n\"\n                     \"  jump r23\\n\");\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/divdf3.c",
    "content": "//===-- lib/divdf3.c - Double-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divdf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    const uint32_t q31b = bSignificand >> 21;\n    uint32_t recip32 = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction32;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n\n    // recip32 might have overflowed to exactly zero in the preceding\n    // computation if the high word of b is exactly 1.0.  This would sabotage\n    // the full-width final stage of the computation that follows, so we adjust\n    // recip32 downward by one bit.\n    recip32--;\n\n    // We need to perform one more iteration to get us to 56 binary digits;\n    // The last iteration needs to happen with extra precision.\n    const uint32_t q63blo = bSignificand << 11;\n    uint64_t correction, reciprocal;\n    correction = -((uint64_t)recip32 * q31b + ((uint64_t)recip32 * q63blo >> 32));\n    uint32_t cHi = correction >> 32;\n    uint32_t cLo = correction;\n    reciprocal = (uint64_t)recip32 * cHi + ((uint64_t)recip32 * cLo >> 32);\n\n    // We already adjusted the 32-bit estimate, now we need to adjust the final\n    // 64-bit reciprocal estimate downward to ensure that it is strictly smaller\n    // than the infinitely precise exact reciprocal.  Because the computation\n    // of the Newton-Raphson step is truncating at every step, this adjustment\n    // is small; most of the work is already done.\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-56, lies in the\n    // interval [0.5, 1.0), and is strictly smaller than the true reciprocal\n    // of b.  Multiplying a by this reciprocal thus gives a numerical q = a/b\n    // in Q53 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0.5, 2.0)\n    //    3. the error in q is bounded away from 2^-53 (actually, we have a\n    //       couple of bits to spare, but this is all we need).\n\n    // We need a 64 x 64 multiply high to compute q, which isn't a basic\n    // operation in C, so we need to be a little bit fussy.\n    rep_t quotient, quotientLo;\n    wideMultiply(aSignificand << 2, reciprocal, &quotient, &quotientLo);\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 53) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 52) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        const double result = fromRep(absResult | quotientSign);\n        return result;\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ddiv(fp_t a, fp_t b)\n{\n    return __divdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/divdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__divdi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 0);\n        } else {\n            return -__udiv64(dividend, -divider, 0);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 0);\n    } else {\n        // Negative dividend, negative divider\n        return __udiv64(-dividend, -divider, 0);\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/divmodsi4.c",
    "content": "/*===-- divmodsi4.c - Implement __divmodsi4 --------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__divmodsi4(si_int a, si_int b, si_int *rem)\n{\n    long res = __div32(a, b);\n    *rem = (int)res;\n    return (int)(res >> 32);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/divsf3.c",
    "content": "//===-- lib/divsf3.c - Single-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divsf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    uint32_t q31b = bSignificand << 8;\n    uint32_t reciprocal = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n\n    // Exhaustive testing shows that the error in reciprocal after three steps\n    // is in the interval [-0x1.f58108p-31, 0x1.d0e48cp-29], in line with our\n    // expectations.  We bump the reciprocal by a tiny value to force the error\n    // to be strictly positive (in the range [0x1.4fdfp-37,0x1.287246p-29], to\n    // be specific).  This also causes 1/1 to give a sensible approximation\n    // instead of zero (due to overflow).\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-28, lies in the\n    // interval [0x1.000000eep-1, 0x1.fffffffcp-1], and is strictly smaller\n    // than the true reciprocal of b.  Multiplying a by this reciprocal thus\n    // gives a numerical q = a/b in Q24 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0x1.000000eep-1, 0x1.fffffffcp0)\n    //    3. the error in q is at most 2^-24 + 2^-27 -- the 2^24 term comes\n    //       from the fact that we truncate the product, and the 2^27 term\n    //       is the error in the reciprocal of b scaled by the maximum\n    //       possible value of a.  As a consequence of this error bound,\n    //       either q or nextafter(q) is the correctly rounded\n    rep_t quotient = (uint64_t)reciprocal * (aSignificand << 1) >> 32;\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 24) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 23) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        return fromRep(absResult | quotientSign);\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fdiv(fp_t a, fp_t b)\n{\n    return __divsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/divsi3.c",
    "content": "/* ===-- divsi3.c - Implement __divsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b)\n{\n    const int bits_in_word_m1 = (int)(sizeof(si_int) * CHAR_BIT) - 1;\n    si_int s_a = a >> bits_in_word_m1; /* s_a = a < 0 ? -1 : 0 */\n    si_int s_b = b >> bits_in_word_m1; /* s_b = b < 0 ? -1 : 0 */\n    a = (a ^ s_a) - s_a; /* negate if s_a == -1 */\n    b = (b ^ s_b) - s_b; /* negate if s_b == -1 */\n    s_a ^= s_b; /* sign of quotient */\n    /*\n     * On CPUs without unsigned hardware division support,\n     *  this calls __udivsi3 (notice the cast to su_int).\n     * On CPUs with unsigned hardware division support,\n     *  this uses the unsigned division instruction.\n     */\n    return ((su_int)a / (su_int)b ^ s_a) - s_a; /* negate if s_a == -1 */\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_idiv(si_int a, si_int b)\n{\n    return __divsi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/dpuconst.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUCONST_H\n#define DPUSYSCORE_DPUCONST_H\n\n#define __DPU_NUMBER_OF_THREADS 24\n#define __DPU_MRAM_SIZE_LOG2 26\n\n#endif /* DPUSYSCORE_DPUCONST_H */"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/dpufault.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUFAULT_H\n#define DPUSYSCORE_DPUFAULT_H\n\n// A list of \"fault codes\"\n#define __FAULT_ALLOC_HEAP_FULL__ 1\n#define __FAULT_DIVISION_BY_ZERO__ 2\n#define __FAULT_ASSERT_FAILED__ 3\n// Used in the compiler to implement a trap\n#define __FAULT_HALT__ 4\n#define __FAULT_PRINTF_OVERFLOW__ 5\n#define __FAULT_ALREADY_PROFILING__ 6\n#define __FAULT_NOT_PROFILING__ 7\n\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/dpuruntime.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPURUNTIME_H\n#define DPUSYSCORE_DPURUNTIME_H\n\n#include <built_ins.h>\n#include <dpuconst.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <stdint.h>\n\n// todo fix: This file should not be included by another syslib header file, only by source files (conflicting definitions).\n\n#define __INITIAL_HEAP_POINTER __sys_heap_pointer_reset\n#define __HEAP_POINTER __sys_heap_pointer\n#define __WAIT_QUEUE_TABLE __sys_wq_table\n#define __SP_TABLE__ __sys_thread_stack_table_ptr\n#define __STDOUT_BUFFER_STATE __stdout_buffer_state\n\n/* The order needs to match the __bootstrap function expectation */\ntypedef struct {\n    uint32_t stack_size;\n    uint32_t stack_ptr;\n} thread_stack_t;\n\nextern unsigned int __INITIAL_HEAP_POINTER;\nextern volatile unsigned int __HEAP_POINTER;\nextern unsigned char __WAIT_QUEUE_TABLE[];\nextern thread_stack_t __SP_TABLE__[];\n\n#define __acquire(base, off) __builtin_acquire_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __release(base, off, at) __builtin_release_rici(base, off, \"nz\", at)\n\n#define __resume(base, off) __builtin_resume_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __stop() __builtin_stop_ci(\"false\", \"0\")\n#define __stop_at(label) __builtin_stop_ci(\"true\", label)\n\n#define likely(x) __builtin_expect((x), 1)\n#define unlikely(x) __builtin_expect((x), 0)\n#define unreachable() __builtin_unreachable()\n\n#define count_leading_zeros(x) __builtin_clz(x)\n#define count_population(x) __builtin_popcount(x)\n\n#define __EMPTY_WAIT_QUEUE 0xFF\n\n#define __AT_THIS_INSTRUCTION \".+0\"\n#define __AT_NEXT_INSTRUCTION \".+1\"\n\n// Use this macro at the beginning of an assembly function in order to get profiled.\n#ifdef DPU_PROFILING\n#define __ADD_PROFILING_ENTRY__ \"call r23, mcount\\n\"\n#else\n#define __ADD_PROFILING_ENTRY__ \"\\n\"\n#endif\n\n#ifdef DPU_PROFILING\n/* Reset counter + count cycles */\n#define __CONFIG_PERFCOUNTER_ENTRY__                                                                                             \\\n    \"  move r23, 3\\n\"                                                                                                            \\\n    \"  time_cfg zero, r23\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__                                                                                               \\\n    \"  time r23\\n\"                                                                                                               \\\n    \"  sw zero, perfcounter_end_value, r23\\n\"\n#else\n#define __CONFIG_PERFCOUNTER_ENTRY__ \"\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__ \"\\n\"\n#endif\n\n#endif /* DPUSYSCORE_DPURUNTIME_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/extendhfsf2.c",
    "content": "//===-- lib/extendhfsf2.c - half -> single conversion -------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_HALF\n#define DST_SINGLE\n#include \"fp_extend_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE float\n__extendhfsf2(uint16_t a)\n{\n    return __extendXfYf2__(a);\n}\n\nCOMPILER_RT_ABI float\n__gnu_h2f_ieee(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_h2f(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/extendsfdf2.c",
    "content": "//===-- lib/extendsfdf2.c - single -> double conversion -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_SINGLE\n#define DST_DOUBLE\n#include \"fp_extend_impl.inc\"\n\nCOMPILER_RT_ABI double\n__extendsfdf2(float a)\n{\n    return __extendXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_f2d(float a)\n{\n    return __extendsfdf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ffsdi2.c",
    "content": "/* ===-- ffsdi2.c - Implement __ffsdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctz(x.s.high) + (1 + sizeof(si_int) * CHAR_BIT);\n    }\n    return __builtin_ctz(x.s.low) + 1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ffssi2.c",
    "content": "/* ===-- ffssi2.c - Implement __ffssi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffssi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffssi2(si_int a)\n{\n    if (a == 0) {\n        return 0;\n    }\n    return __builtin_ctz(a) + 1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ffsti2.c",
    "content": "/* ===-- ffsti2.c - Implement __ffsti2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsti2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n#ifdef CRT_HAS_128BIT\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsti2(ti_int a)\n{\n    twords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctzll(x.s.high) + (1 + sizeof(di_int) * CHAR_BIT);\n    }\n    return __builtin_ctzll(x.s.low) + 1;\n}\n\n#endif /* CRT_HAS_128BIT */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixdfdi.c",
    "content": "/* ===-- fixdfdi.c - Implement __fixdfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a);\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(double a)\n{\n    if (a < 0.0) {\n        return -__fixunsdfdi(-a);\n    }\n    return __fixunsdfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_d2lz(fp_t a)\n{\n#else\n__aeabi_d2lz(double a)\n{\n#endif\n    return __fixdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixdfsi.c",
    "content": "/* ===-- fixdfsi.c - Implement __fixdfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixdfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_d2iz(fp_t a)\n{\n    return __fixdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixsfdi.c",
    "content": "/* ===-- fixsfdi.c - Implement __fixsfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a);\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(float a)\n{\n    if (a < 0.0f) {\n        return -__fixunssfdi(-a);\n    }\n    return __fixunssfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_f2lz(fp_t a)\n{\n#else\n__aeabi_f2lz(float a)\n{\n#endif\n    return __fixsfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixsfsi.c",
    "content": "/* ===-- fixsfsi.c - Implement __fixsfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixsfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_f2iz(fp_t a)\n{\n    return __fixsfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixunsdfdi.c",
    "content": "/* ===-- fixunsdfdi.c - Implement __fixunsdfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a)\n{\n    if (a <= 0.0)\n        return 0;\n    su_int high = a / 4294967296.f; /* a / 0x1p32f; */\n    su_int low = a - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_d2ulz(fp_t a)\n{\n#else\n__aeabi_d2ulz(double a)\n{\n#endif\n    return __fixunsdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixunsdfsi.c",
    "content": "/* ===-- fixunsdfsi.c - Implement __fixunsdfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunsdfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_d2uiz(fp_t a)\n{\n    return __fixunsdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixunssfdi.c",
    "content": "/* ===-- fixunssfdi.c - Implement __fixunssfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a)\n{\n    if (a <= 0.0f)\n        return 0;\n    double da = a;\n    su_int high = da / 4294967296.f; /* da / 0x1p32f; */\n    su_int low = da - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_f2ulz(fp_t a)\n{\n#else\n__aeabi_f2ulz(float a)\n{\n#endif\n    return __fixunssfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fixunssfsi.c",
    "content": "/* ===-- fixunssfsi.c - Implement __fixunssfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __fixunssfsi for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunssfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_f2uiz(fp_t a)\n{\n    return __fixunssfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/float.h",
    "content": "/*===---- float.h - Characteristics of floating point types ----------------===\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __FLOAT_H\n#define __FLOAT_H\n\n/**\n * @file float.h\n */\n\n/* Characteristics of floating point types, C99 5.2.4.2.2 */\n\n#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__\n#define FLT_ROUNDS (__builtin_flt_rounds())\n#define FLT_RADIX __FLT_RADIX__\n\n#define FLT_MANT_DIG __FLT_MANT_DIG__\n#define DBL_MANT_DIG __DBL_MANT_DIG__\n#define LDBL_MANT_DIG __LDBL_MANT_DIG__\n\n#if __STDC_VERSION__ >= 199901L || !defined(__STRICT_ANSI__)\n#define DECIMAL_DIG __DECIMAL_DIG__\n#endif\n\n#define FLT_DIG __FLT_DIG__\n#define DBL_DIG __DBL_DIG__\n#define LDBL_DIG __LDBL_DIG__\n\n#define FLT_MIN_EXP __FLT_MIN_EXP__\n#define DBL_MIN_EXP __DBL_MIN_EXP__\n#define LDBL_MIN_EXP __LDBL_MIN_EXP__\n\n#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__\n#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__\n#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__\n\n#define FLT_MAX_EXP __FLT_MAX_EXP__\n#define DBL_MAX_EXP __DBL_MAX_EXP__\n#define LDBL_MAX_EXP __LDBL_MAX_EXP__\n\n#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__\n#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__\n#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__\n\n#define FLT_MAX __FLT_MAX__\n#define DBL_MAX __DBL_MAX__\n#define LDBL_MAX __LDBL_MAX__\n\n#define FLT_EPSILON __FLT_EPSILON__\n#define DBL_EPSILON __DBL_EPSILON__\n#define LDBL_EPSILON __LDBL_EPSILON__\n\n#define FLT_MIN __FLT_MIN__\n#define DBL_MIN __DBL_MIN__\n#define LDBL_MIN __LDBL_MIN__\n\n#define FLT_HAS_SUBNORM (-1)\n#define DBL_HAS_SUBNORM (-1)\n#define LDBL_HAS_SUBNORM (-1)\n#define DBL_FLT_HAS_SUBNORM (-1)\n#define LDBL_FLT_HAS_SUBNORM (-1)\n\n#if __STDC_VERSION__ >= 201112L || !defined(__STRICT_ANSI__)\n#define FLT_TRUE_MIN __FLT_DENORM_MIN__\n#define DBL_TRUE_MIN __DBL_DENORM_MIN__\n#define LDBL_TRUE_MIN __LDBL_DENORM_MIN__\n#define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__\n#define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__\n#define LDBL_DECIMAL_DIG __LDBL_DECIMAL_DIG__\n#endif\n\n#endif /* __FLOAT_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatdidf.c",
    "content": "/*===-- floatdidf.c - Implement __floatdidf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdidf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop32 = 4294967296.0; // 0x1.0p32\n\n    union {\n        int64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    const double high = (int32_t)(a >> 32) * twop32;\n    low.x |= a & INT64_C(0x00000000ffffffff);\n\n    const double result = (high - twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         * Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_l2d(di_int a)\n{\n    return __floatdidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatdisf.c",
    "content": "/*===-- floatdisf.c - Implement __floatdisf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even.*/\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatdisf(di_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_l2f(di_int a)\n{\n    return __floatdisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatsidf.c",
    "content": "//===-- lib/floatsidf.c - integer -> double-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsidf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.  Extra\n    // cast to unsigned int is necessary to get the correct behavior for\n    // the input INT_MIN.\n    const int shift = significandBits - exponent;\n    result = (rep_t)(unsigned int)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2d(int a)\n{\n    return __floatsidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatsisf.c",
    "content": "//===-- lib/floatsisf.c - integer -> single-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsisf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2f(int a)\n{\n    return __floatsisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatundidf.c",
    "content": "/* ===-- floatundidf.c - Implement __floatundidf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundidf for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             du_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop84 = 19342813113834066795298816.0; // 0x1.0p84\n    static const double twop84_plus_twop52 = 19342813118337666422669312.0; // 0x1.00000001p84\n\n    union {\n        uint64_t x;\n        double d;\n    } high = { .d = twop84 };\n    union {\n        uint64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    high.x |= a >> 32;\n    low.x |= a & UINT64_C(0x00000000ffffffff);\n\n    const double result = (high.d - twop84_plus_twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         *  Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low  */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_ul2d(du_int a)\n{\n    return __floatundidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatundisf.c",
    "content": "/*===-- floatundisf.c - Implement __floatundisf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even. */\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *            du_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatundisf(du_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* 8 exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_ul2f(du_int a)\n{\n    return __floatundisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatunsidf.c",
    "content": "//===-- lib/floatunsidf.c - uint -> double-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsidf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.\n    const int shift = significandBits - exponent;\n    result = (rep_t)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2d(unsigned int a)\n{\n    return __floatunsidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/floatunsisf.c",
    "content": "//===-- lib/floatunsisf.c - uint -> single-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsisf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2f(unsigned int a)\n{\n    return __floatunsisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_add_impl.inc",
    "content": "//===----- lib/fp_add_impl.inc - floaing point addition -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float addition with the IEEE-754 default rounding\n// (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __addXf3__(fp_t a, fp_t b) {\n    rep_t aRep = toRep(a);\n    rep_t bRep = toRep(b);\n    const rep_t aAbs = aRep & absMask;\n    const rep_t bAbs = bRep & absMask;\n\n    // Detect if a or b is zero, infinity, or NaN.\n    if (aAbs - REP_C(1) >= infRep - REP_C(1) ||\n        bAbs - REP_C(1) >= infRep - REP_C(1)) {\n        // NaN + anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything + NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // +/-infinity + -/+infinity = qNaN\n            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);\n            // +/-infinity + anything remaining = +/- infinity\n            else return a;\n        }\n\n        // anything remaining + +/-infinity = +/-infinity\n        if (bAbs == infRep) return b;\n\n        // zero + anything = anything\n        if (!aAbs) {\n            // but we need to get the sign right for zero + zero\n            if (!bAbs) return fromRep(toRep(a) & toRep(b));\n            else return b;\n        }\n\n        // anything + zero = anything\n        if (!bAbs) return a;\n    }\n\n    // Swap a and b if necessary so that a has the larger absolute value.\n    if (bAbs > aAbs) {\n        const rep_t temp = aRep;\n        aRep = bRep;\n        bRep = temp;\n    }\n\n    // Extract the exponent and significand from the (possibly swapped) a and b.\n    int aExponent = aRep >> significandBits & maxExponent;\n    int bExponent = bRep >> significandBits & maxExponent;\n    rep_t aSignificand = aRep & significandMask;\n    rep_t bSignificand = bRep & significandMask;\n\n    // Normalize any denormals, and adjust the exponent accordingly.\n    if (aExponent == 0) aExponent = normalize(&aSignificand);\n    if (bExponent == 0) bExponent = normalize(&bSignificand);\n\n    // The sign of the result is the sign of the larger operand, a.  If they\n    // have opposite signs, we are performing a subtraction; otherwise addition.\n    const rep_t resultSign = aRep & signBit;\n    const bool subtraction = (aRep ^ bRep) & signBit;\n\n    // Shift the significands to give us round, guard and sticky, and or in the\n    // implicit significand bit.  (If we fell through from the denormal path it\n    // was already set by normalize( ), but setting it twice won't hurt\n    // anything.)\n    aSignificand = (aSignificand | implicitBit) << 3;\n    bSignificand = (bSignificand | implicitBit) << 3;\n\n    // Shift the significand of b by the difference in exponents, with a sticky\n    // bottom bit to get rounding correct.\n    const unsigned int align = aExponent - bExponent;\n    if (align) {\n        if (align < typeWidth) {\n            const bool sticky = bSignificand << (typeWidth - align);\n            bSignificand = bSignificand >> align | sticky;\n        } else {\n            bSignificand = 1; // sticky; b is known to be non-zero.\n        }\n    }\n    if (subtraction) {\n        aSignificand -= bSignificand;\n        // If a == -b, return +zero.\n        if (aSignificand == 0) return fromRep(0);\n\n        // If partial cancellation occured, we need to left-shift the result\n        // and adjust the exponent:\n        if (aSignificand < implicitBit << 3) {\n            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);\n            aSignificand <<= shift;\n            aExponent -= shift;\n        }\n    }\n    else /* addition */ {\n        aSignificand += bSignificand;\n\n        // If the addition carried up, we need to right-shift the result and\n        // adjust the exponent:\n        if (aSignificand & implicitBit << 4) {\n            const bool sticky = aSignificand & 1;\n            aSignificand = aSignificand >> 1 | sticky;\n            aExponent += 1;\n        }\n    }\n\n    // If we have overflowed the type, return +/- infinity:\n    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);\n\n    if (aExponent <= 0) {\n        // Result is denormal before rounding; the exponent is zero and we\n        // need to shift the significand.\n        const int shift = 1 - aExponent;\n        const bool sticky = aSignificand << (typeWidth - shift);\n        aSignificand = aSignificand >> shift | sticky;\n        aExponent = 0;\n    }\n\n    // Low three bits are round, guard, and sticky.\n    const int roundGuardSticky = aSignificand & 0x7;\n\n    // Shift the significand into place, and mask off the implicit bit.\n    rep_t result = aSignificand >> 3 & significandMask;\n\n    // Insert the exponent and sign.\n    result |= (rep_t)aExponent << significandBits;\n    result |= resultSign;\n\n    // Final rounding.  The result may overflow to infinity, but that is the\n    // correct result in that case.\n    if (roundGuardSticky > 0x4) result++;\n    if (roundGuardSticky == 0x4) result += result & 1;\n    return fromRep(result);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_extend.h",
    "content": "//===-lib/fp_extend.h - low precision -> high precision conversion -*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_EXTEND_HEADER\n#define FP_EXTEND_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n#define src_rep_t_clz __builtin_clz\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\nstatic __inline int\nsrc_rep_t_clz(src_rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#elif defined SRC_HALF\ntypedef uint16_t src_t;\ntypedef uint16_t src_rep_t;\n#define SRC_REP_C UINT16_C\nstatic const int srcSigBits = 10;\n#define src_rep_t_clz __builtin_clz\n\n#else\n#error Source should be half, single, or double precision!\n#endif // end source precision\n\n#if defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_QUAD\ntypedef long double dst_t;\ntypedef __uint128_t dst_rep_t;\n#define DST_REP_C (__uint128_t)\nstatic const int dstSigBits = 112;\n\n#else\n#error Destination should be single, double, or quad precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n// End helper routines.  Conversion implementation follows.\n\n#endif // FP_EXTEND_HEADER\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_extend_impl.inc",
    "content": "//=-lib/fp_extend_impl.inc - low precision -> high precision conversion -*-- -//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a narrower to a wider\n// IEEE-754 floating-point type.  The constants and types defined following the\n// includes below parameterize the conversion.\n//\n// It does not support types that don't use the usual IEEE-754 interchange\n// formats; specifically, some work would be needed to adapt it to\n// (for example) the Intel 80-bit format or PowerPC double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *widening* operations; if you need to convert to a *narrower* floating-point\n// type (e.g. double -> float), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.  You also may\n// run into trouble finding an appropriate CLZ function for wide source types;\n// you will likely need to roll your own on some platforms.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_extend.h\"\n\nstatic __inline dst_t __extendXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const dst_rep_t dstMinNormal = DST_REP_C(1) << dstSigBits;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    // If sizeof(src_rep_t) < sizeof(int), the subtraction result is promoted\n    // to (signed) int.  To avoid that, explicitly cast to src_rep_t.\n    if ((src_rep_t)(aAbs - srcMinNormal) < srcInfinity - srcMinNormal) {\n        // a is a normal number.\n        // Extend to the destination type by shifting the significand and\n        // exponent into the proper position and rebiasing the exponent.\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits);\n        absResult += (dst_rep_t)(dstExpBias - srcExpBias) << dstSigBits;\n    }\n\n    else if (aAbs >= srcInfinity) {\n        // a is NaN or infinity.\n        // Conjure the result by beginning with infinity, then setting the qNaN\n        // bit (if needed) and right-aligning the rest of the trailing NaN\n        // payload field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= (dst_rep_t)(aAbs & srcQNaN) << (dstSigBits - srcSigBits);\n        absResult |= (dst_rep_t)(aAbs & srcNaNCode) << (dstSigBits - srcSigBits);\n    }\n\n    else if (aAbs) {\n        // a is denormal.\n        // renormalize the significand and clear the leading bit, then insert\n        // the correct adjusted exponent in the destination type.\n        const int scale = src_rep_t_clz(aAbs) - src_rep_t_clz(srcMinNormal);\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits + scale);\n        absResult ^= dstMinNormal;\n        const int resultExponent = dstExpBias - srcExpBias - scale + 1;\n        absResult |= (dst_rep_t)resultExponent << dstSigBits;\n    }\n\n    else {\n        // a is zero.\n        absResult = 0;\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_fixint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixint_t __fixint(fp_t a) {\n    const fixint_t fixint_max = (fixint_t)((~(fixuint_t)0) / 2);\n    const fixint_t fixint_min = -fixint_max - 1;\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const fixint_t sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If exponent is negative, the result is zero.\n    if (exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixint_t) * CHAR_BIT)\n        return sign == 1 ? fixint_max : fixint_min;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return sign * (significand >> (significandBits - exponent));\n    else\n        return sign * ((fixint_t)significand << (exponent - significandBits));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_fixuint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to unsigned integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixuint_t __fixuint(fp_t a) {\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const int sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If either the value or the exponent is negative, the result is zero.\n    if (sign == -1 || exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixuint_t) * CHAR_BIT)\n        return ~(fixuint_t)0;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return significand >> (significandBits - exponent);\n    else\n        return (fixuint_t)significand << (exponent - significandBits);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_lib.h",
    "content": "//===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file is a configuration header for soft-float routines in compiler-rt.\n// This file does not provide any part of the compiler-rt interface, but defines\n// many useful constants and utility routines that are used in the\n// implementation of the soft-float routines in compiler-rt.\n//\n// Assumes that float, double and long double correspond to the IEEE-754\n// binary32, binary64 and binary 128 types, respectively, and that integer\n// endianness matches floating point endianness on the target platform.\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_LIB_HEADER\n#define FP_LIB_HEADER\n\n#include <stdint.h>\n#include <stdbool.h>\n#include <limits.h>\n#include \"int_lib.h\"\n\n// x86_64 FreeBSD prior v9.3 define fixed-width types incorrectly in\n// 32-bit mode.\n#if defined(__FreeBSD__) && defined(__i386__)\n#include <sys/param.h>\n#if __FreeBSD_version < 903000 // v9.3\n#define uint64_t unsigned long long\n#define int64_t long long\n#undef UINT64_C\n#define UINT64_C(c) (c##ULL)\n#endif\n#endif\n\n#if defined SINGLE_PRECISION\n\ntypedef uint32_t rep_t;\ntypedef int32_t srep_t;\ntypedef float fp_t;\n#define REP_C UINT32_C\n#define significandBits 23\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    return __builtin_clz(a);\n}\n\n// 32x32 --> 64 bit multiply\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    const uint64_t product = (uint64_t)a * b;\n    *hi = product >> 32;\n    *lo = product;\n}\nCOMPILER_RT_ABI fp_t\n__addsf3(fp_t a, fp_t b);\n\n#elif defined DOUBLE_PRECISION\n\ntypedef uint64_t rep_t;\ntypedef int64_t srep_t;\ntypedef double fp_t;\n#define REP_C UINT64_C\n#define significandBits 52\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#define loWord(a) (a & 0xffffffffU)\n#define hiWord(a) (a >> 32)\n\n// 64x64 -> 128 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    // Each of the component 32x32 -> 64 products\n    const uint64_t plolo = loWord(a) * loWord(b);\n    const uint64_t plohi = loWord(a) * hiWord(b);\n    const uint64_t philo = hiWord(a) * loWord(b);\n    const uint64_t phihi = hiWord(a) * hiWord(b);\n    // Sum terms that contribute to lo in a way that allows us to get the carry\n    const uint64_t r0 = loWord(plolo);\n    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);\n    *lo = r0 + (r1 << 32);\n    // Sum terms contributing to hi with the carry from lo\n    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;\n}\n#undef loWord\n#undef hiWord\n\nCOMPILER_RT_ABI fp_t\n__adddf3(fp_t a, fp_t b);\n\n#elif defined QUAD_PRECISION\n#if __LDBL_MANT_DIG__ == 113\n#define CRT_LDBL_128BIT\ntypedef __uint128_t rep_t;\ntypedef __int128_t srep_t;\ntypedef long double fp_t;\n#define REP_C (__uint128_t)\n// Note: Since there is no explicit way to tell compiler the constant is a\n// 128-bit integer, we let the constant be casted to 128-bit integer\n#define significandBits 112\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    const union {\n        __uint128_t ll;\n#if _YUGA_BIG_ENDIAN\n        struct {\n            uint64_t high, low;\n        } s;\n#else\n        struct {\n            uint64_t low, high;\n        } s;\n#endif\n    } uu = { .ll = a };\n\n    uint64_t word;\n    uint64_t add;\n\n    if (uu.s.high) {\n        word = uu.s.high;\n        add = 0;\n    } else {\n        word = uu.s.low;\n        add = 64;\n    }\n    return __builtin_clzll(word) + add;\n}\n\n#define Word_LoMask UINT64_C(0x00000000ffffffff)\n#define Word_HiMask UINT64_C(0xffffffff00000000)\n#define Word_FullMask UINT64_C(0xffffffffffffffff)\n#define Word_1(a) (uint64_t)((a >> 96) & Word_LoMask)\n#define Word_2(a) (uint64_t)((a >> 64) & Word_LoMask)\n#define Word_3(a) (uint64_t)((a >> 32) & Word_LoMask)\n#define Word_4(a) (uint64_t)(a & Word_LoMask)\n\n// 128x128 -> 256 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n\n    const uint64_t product11 = Word_1(a) * Word_1(b);\n    const uint64_t product12 = Word_1(a) * Word_2(b);\n    const uint64_t product13 = Word_1(a) * Word_3(b);\n    const uint64_t product14 = Word_1(a) * Word_4(b);\n    const uint64_t product21 = Word_2(a) * Word_1(b);\n    const uint64_t product22 = Word_2(a) * Word_2(b);\n    const uint64_t product23 = Word_2(a) * Word_3(b);\n    const uint64_t product24 = Word_2(a) * Word_4(b);\n    const uint64_t product31 = Word_3(a) * Word_1(b);\n    const uint64_t product32 = Word_3(a) * Word_2(b);\n    const uint64_t product33 = Word_3(a) * Word_3(b);\n    const uint64_t product34 = Word_3(a) * Word_4(b);\n    const uint64_t product41 = Word_4(a) * Word_1(b);\n    const uint64_t product42 = Word_4(a) * Word_2(b);\n    const uint64_t product43 = Word_4(a) * Word_3(b);\n    const uint64_t product44 = Word_4(a) * Word_4(b);\n\n    const __uint128_t sum0 = (__uint128_t)product44;\n    const __uint128_t sum1 = (__uint128_t)product34 + (__uint128_t)product43;\n    const __uint128_t sum2 = (__uint128_t)product24 + (__uint128_t)product33 + (__uint128_t)product42;\n    const __uint128_t sum3 = (__uint128_t)product14 + (__uint128_t)product23 + (__uint128_t)product32 + (__uint128_t)product41;\n    const __uint128_t sum4 = (__uint128_t)product13 + (__uint128_t)product22 + (__uint128_t)product31;\n    const __uint128_t sum5 = (__uint128_t)product12 + (__uint128_t)product21;\n    const __uint128_t sum6 = (__uint128_t)product11;\n\n    const __uint128_t r0 = (sum0 & Word_FullMask) + ((sum1 & Word_LoMask) << 32);\n    const __uint128_t r1 = (sum0 >> 64) + ((sum1 >> 32) & Word_FullMask) + (sum2 & Word_FullMask) + ((sum3 << 32) & Word_HiMask);\n\n    *lo = r0 + (r1 << 64);\n    *hi = (r1 >> 64) + (sum1 >> 96) + (sum2 >> 64) + (sum3 >> 32) + sum4 + (sum5 << 32) + (sum6 << 64);\n}\n#undef Word_1\n#undef Word_2\n#undef Word_3\n#undef Word_4\n#undef Word_HiMask\n#undef Word_LoMask\n#undef Word_FullMask\n#endif // __LDBL_MANT_DIG__ == 113\n#else\n#error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.\n#endif\n\n#if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) || defined(CRT_LDBL_128BIT)\n#define typeWidth (sizeof(rep_t) * CHAR_BIT)\n#define exponentBits (typeWidth - significandBits - 1)\n#define maxExponent ((1 << exponentBits) - 1)\n#define exponentBias (maxExponent >> 1)\n\n#define implicitBit (REP_C(1) << significandBits)\n#define significandMask (implicitBit - 1U)\n#define signBit (REP_C(1) << (significandBits + exponentBits))\n#define absMask (signBit - 1U)\n#define exponentMask (absMask ^ significandMask)\n#define oneRep ((rep_t)exponentBias << significandBits)\n#define infRep exponentMask\n#define quietBit (implicitBit >> 1)\n#define qnanRep (exponentMask | quietBit)\n\nstatic __inline rep_t\ntoRep(fp_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline fp_t\nfromRep(rep_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\nstatic __inline int\nnormalize(rep_t *significand)\n{\n    const int shift = rep_clz(*significand) - rep_clz(implicitBit);\n    *significand <<= shift;\n    return 1 - shift;\n}\n\nstatic __inline void\nwideLeftShift(rep_t *hi, rep_t *lo, int count)\n{\n    *hi = *hi << count | *lo >> (typeWidth - count);\n    *lo = *lo << count;\n}\n\nstatic __inline void\nwideRightShiftWithSticky(rep_t *hi, rep_t *lo, unsigned int count)\n{\n    if (count < typeWidth) {\n        const bool sticky = *lo << (typeWidth - count);\n        *lo = *hi << (typeWidth - count) | *lo >> count | sticky;\n        *hi = *hi >> count;\n    } else if (count < 2 * typeWidth) {\n        const bool sticky = *hi << (2 * typeWidth - count) | *lo;\n        *lo = *hi >> (count - typeWidth) | sticky;\n        *hi = 0;\n    } else {\n        const bool sticky = *hi | *lo;\n        *lo = sticky;\n        *hi = 0;\n    }\n}\n#endif\n\n#endif // FP_LIB_HEADER\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_mul_impl.inc",
    "content": "//===---- lib/fp_mul_impl.inc - floating point multiplication -----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float multiplication with the IEEE-754 default\n// rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __mulXf3__(fp_t a, fp_t b) {\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN * anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything * NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity * non-zero = +/- infinity\n            if (bAbs) return fromRep(aAbs | productSign);\n            // infinity * zero = NaN\n            else return fromRep(qnanRep);\n        }\n\n        if (bAbs == infRep) {\n            //? non-zero * infinity = +/- infinity\n            if (aAbs) return fromRep(bAbs | productSign);\n            // zero * infinity = NaN\n            else return fromRep(qnanRep);\n        }\n\n        // zero * anything = +/- zero\n        if (!aAbs) return fromRep(productSign);\n        // anything * zero = +/- zero\n        if (!bAbs) return fromRep(productSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale += normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n\n    // Get the significand of a*b.  Before multiplying the significands, shift\n    // one of them left to left-align it in the field.  Thus, the product will\n    // have (exponentBits + 2) integral digits, all but two of which must be\n    // zero.  Normalizing this result is just a conditional left-shift by one\n    // and bumping the exponent accordingly.\n    rep_t productHi, productLo;\n    wideMultiply(aSignificand, bSignificand << exponentBits,\n                 &productHi, &productLo);\n\n    int productExponent = aExponent + bExponent - exponentBias + scale;\n\n    // Normalize the significand, adjust exponent if needed.\n    if (productHi & implicitBit) productExponent++;\n    else wideLeftShift(&productHi, &productLo, 1);\n\n    // If we have overflowed the type, return +/- infinity.\n    if (productExponent >= maxExponent) return fromRep(infRep | productSign);\n\n    if (productExponent <= 0) {\n        // Result is denormal before rounding\n        //\n        // If the result is so small that it just underflows to zero, return\n        // a zero of the appropriate sign.  Mathematically there is no need to\n        // handle this case separately, but we make it a special case to\n        // simplify the shift logic.\n        const unsigned int shift = REP_C(1) - (unsigned int)productExponent;\n        if (shift >= typeWidth) return fromRep(productSign);\n\n        // Otherwise, shift the significand of the result so that the round\n        // bit is the high bit of productLo.\n        wideRightShiftWithSticky(&productHi, &productLo, shift);\n    }\n    else {\n        // Result is normal before rounding; insert the exponent.\n        productHi &= significandMask;\n        productHi |= (rep_t)productExponent << significandBits;\n    }\n\n    // Insert the sign of the result:\n    productHi |= productSign;\n\n    // Final rounding.  The final result may overflow to infinity, or underflow\n    // to zero, but those are the correct results in those cases.  We use the\n    // default IEEE-754 round-to-nearest, ties-to-even rounding mode.\n    if (productLo > signBit) productHi++;\n    if (productLo == signBit) productHi += productHi & 1;\n    return fromRep(productHi);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_trunc.h",
    "content": "//=== lib/fp_trunc.h - high precision -> low precision conversion *- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination precision setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_TRUNC_HEADER\n#define FP_TRUNC_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\n\n#elif defined SRC_QUAD\ntypedef long double src_t;\ntypedef __uint128_t src_rep_t;\n#define SRC_REP_C (__uint128_t)\nstatic const int srcSigBits = 112;\n\n#else\n#error Source should be double precision or quad precision!\n#endif // end source precision\n\n#if defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_HALF\ntypedef uint16_t dst_t;\ntypedef uint16_t dst_rep_t;\n#define DST_REP_C UINT16_C\nstatic const int dstSigBits = 10;\n\n#else\n#error Destination should be single precision or double precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\n#endif // FP_TRUNC_HEADER\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fp_trunc_impl.inc",
    "content": "//= lib/fp_trunc_impl.inc - high precision -> low precision conversion *-*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a wider to a narrower\n// IEEE-754 floating-point type in the default (round to nearest, ties to even)\n// rounding mode.  The constants and types defined following the includes below\n// parameterize the conversion.\n//\n// This routine can be trivially adapted to support conversions to\n// half-precision or from quad-precision. It does not support types that don't\n// use the usual IEEE-754 interchange formats; specifically, some work would be\n// needed to adapt it to (for example) the Intel 80-bit format or PowerPC\n// double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *narrowing* operations; if you need to convert to a *wider* floating-point\n// type (e.g. float -> double), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_trunc.h\"\n\nstatic __inline dst_t __truncXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcSignificandMask = srcMinNormal - 1;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t roundMask = (SRC_REP_C(1) << (srcSigBits - dstSigBits)) - 1;\n    const src_rep_t halfway = SRC_REP_C(1) << (srcSigBits - dstSigBits - 1);\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const int underflowExponent = srcExpBias + 1 - dstExpBias;\n    const int overflowExponent = srcExpBias + dstInfExp - dstExpBias;\n    const src_rep_t underflow = (src_rep_t)underflowExponent << srcSigBits;\n    const src_rep_t overflow = (src_rep_t)overflowExponent << srcSigBits;\n\n    const dst_rep_t dstQNaN = DST_REP_C(1) << (dstSigBits - 1);\n    const dst_rep_t dstNaNCode = dstQNaN - 1;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    if (aAbs - underflow < aAbs - overflow) {\n        // The exponent of a is within the range of normal numbers in the\n        // destination format.  We can convert by simply right-shifting with\n        // rounding and adjusting the exponent.\n        absResult = aAbs >> (srcSigBits - dstSigBits);\n        absResult -= (dst_rep_t)(srcExpBias - dstExpBias) << dstSigBits;\n\n        const src_rep_t roundBits = aAbs & roundMask;\n        // Round to nearest\n        if (roundBits > halfway)\n            absResult++;\n        // Ties to even\n        else if (roundBits == halfway)\n            absResult += absResult & 1;\n    }\n    else if (aAbs > srcInfinity) {\n        // a is NaN.\n        // Conjure the result by beginning with infinity, setting the qNaN\n        // bit and inserting the (truncated) trailing NaN field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= dstQNaN;\n        absResult |= ((aAbs & srcNaNCode) >> (srcSigBits - dstSigBits)) & dstNaNCode;\n    }\n    else if (aAbs >= overflow) {\n        // a overflows to infinity.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n    }\n    else {\n        // a underflows on conversion to the destination type or is an exact\n        // zero.  The result may be a denormal or zero.  Extract the exponent\n        // to get the shift amount for the denormalization.\n        const int aExp = aAbs >> srcSigBits;\n        const int shift = srcExpBias - dstExpBias - aExp + 1;\n\n        const src_rep_t significand = (aRep & srcSignificandMask) | srcMinNormal;\n\n        // Right shift by the denormalization amount with sticky.\n        if (shift > srcSigBits) {\n            absResult = 0;\n        } else {\n            const bool sticky = significand << (srcBits - shift);\n            src_rep_t denormalizedSignificand = significand >> shift | sticky;\n            absResult = denormalizedSignificand >> (srcSigBits - dstSigBits);\n            const src_rep_t roundBits = denormalizedSignificand & roundMask;\n            // Round to nearest\n            if (roundBits > halfway)\n                absResult++;\n            // Ties to even\n            else if (roundBits == halfway)\n                absResult += absResult & 1;\n        }\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | sign >> (srcBits - dstBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fsb_allocator.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <fsb_allocator.h>\n#include <alloc.h>\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <attributes.h>\n#include <atomic_bit.h>\n\nATOMIC_BIT_INIT(__fsb_lock);\n\n// noinline, because part of grind tracked functions\nfsb_allocator_t __noinline\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks)\n{\n    if (block_size > 0xFFFFFFF8) {\n        __asm__ volatile(\"fault \" __STR(__FAULT_ALLOC_HEAP_FULL__));\n        unreachable();\n    }\n\n    block_size = (block_size == 0) ? 8 : (block_size + 7) & ~7;\n\n    unsigned int memory_space_to_allocate = block_size * nb_of_blocks + 4;\n    void *memory = mem_alloc(memory_space_to_allocate);\n\n    unsigned int first_block = (unsigned int)memory;\n\n    for (unsigned int each_block = 0; each_block < nb_of_blocks - 1; ++each_block) {\n        unsigned int next_block_address = (unsigned int)(memory + block_size);\n        *((unsigned int *)memory) = next_block_address;\n        memory = (void *)next_block_address;\n    }\n\n    *((unsigned int *)memory) = 0;\n    memory += block_size;\n\n    void *free_ptr = memory;\n    *((unsigned int *)free_ptr) = first_block;\n\n    return (fsb_allocator_t)free_ptr;\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nfsb_get(fsb_allocator_t allocator)\n{\n    void **result;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(result) : [alloc] \"r\"(allocator));\n\n    if (result == NULL) {\n        ATOMIC_BIT_RELEASE(__fsb_lock);\n        return NULL;\n    }\n\n    void *next = *result;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(next), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n\n    return (void *)result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nfsb_free(fsb_allocator_t allocator, void *ptr)\n{\n    void *next_free;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(next_free) : [alloc] \"r\"(allocator));\n\n    *((void **)ptr) = next_free;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(ptr), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/fsb_allocator.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_FBS_ALLOC_H\n#define DPUSYSCORE_FBS_ALLOC_H\n\n/**\n * @file fsb_allocator.h\n * @brief Provides a fixed-size block memory allocator.\n *\n * @internal When defining an allocator, the total memory needed will be allocated, using mem_alloc.\n *           The allocator structure is a pointer to the next available block. In each free block, the first four bytes\n *           store a pointer to the following free block, creating a linked list. To allocate a block, we just check\n *           the free pointer, check the next free pointer and update the free pointer accordingly. To free a block, we\n *           just check the free pointer, update it with the newly free block, and update the next pointer of this block\n *           with the previous free pointer.\n *           There is no protection to prevent invalid block to be added to the list. Moreover, the list being in the free\n *           blocks, if there is some memory overflow from a block, the list might be corrupted and totally invalid.\n */\n\n/**\n * @fn fsb_allocator_t\n * @brief A fixed-size block allocator.\n */\ntypedef void **fsb_allocator_t;\n\n/**\n * @fn fsb_alloc\n * @brief Allocate and initialize a fixed-size block allocator.\n *\n * @param block_size the size of the blocks allocated (will be realigned on 8 bytes, with a minimum of 8 bytes)\n * @param nb_of_blocks the number of blocks allocated\n * @throws a fault if there is no memory left\n * @return The newly allocated and ready-to-use fixed-size block allocator.\n */\nfsb_allocator_t\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks);\n\n/**\n * @fn fsb_get\n * @brief Own a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator from which we take the block\n * @return A pointer to the owned block if one was available, NULL otherwise.\n */\nvoid *\nfsb_get(fsb_allocator_t allocator);\n\n/**\n * @fn fsb_free\n * @brief Free a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator in which we put the block back in\n * @param ptr the pointer to the block to free\n */\nvoid\nfsb_free(fsb_allocator_t allocator, void *ptr);\n\n#endif /* DPUSYSCORE_FBS_ALLOC_H */"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/handshake.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <errno.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\nunsigned char __handshake_array[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };\n\nATOMIC_BIT_INIT(__handshake)[NR_THREADS];\n\n#define __acquire_handshake(off) __ATOMIC_BIT_ACQUIRE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n#define __release_handshake(off) __ATOMIC_BIT_RELEASE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n\nvoid\nhandshake_notify(void)\n{\n    thread_id_t tid = me();\n    unsigned char info;\n    __acquire_handshake(tid);\n    info = __handshake_array[tid];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[tid] = tid;\n        __release_handshake(tid);\n        __stop();\n    } else {\n        __resume(info, \"0\");\n        __handshake_array[tid] = __EMPTY_WAIT_QUEUE;\n        __release_handshake(tid);\n    }\n}\n\nint\nhandshake_wait_for(unsigned int notifier)\n{\n    thread_id_t tid = me();\n\n    unsigned char thread = (unsigned char)notifier;\n\n    __acquire_handshake(thread);\n    unsigned char info = __handshake_array[thread];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[thread] = tid;\n        __release_handshake(thread);\n        __stop();\n    } else {\n        if (unlikely(info != thread)) {\n            errno = EALREADY;\n            __release_handshake(thread);\n            return EALREADY;\n        } else {\n            __resume(info, \"0\");\n            __handshake_array[thread] = __EMPTY_WAIT_QUEUE;\n        }\n\n        __release_handshake(thread);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/handshake.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_HANDSHAKE_H\n#define DPUSYSCORE_HANDSHAKE_H\n\n/**\n * @file handshake.h\n * @brief Synchronization with handshakes.\n *\n * This synchronization mechanism allows to synchronize 2 tasklets. One tasklet will serve as a notifier\n * and will call handshake_notify() and the other as a customer and will call handshake_wait_for(notifier).\n *\n * @internal    If the notifier called handshake_notify() before the customer, it will stop until some tasklet\n *              calls handshake_wait_for(notifier).\n *              If a tasklet called handshake_wait_for(notifier) before the notifier, it will stop until\n *              the notifier calls handshake_notify(). If afterwards (still before the notifier calls\n *              handshake_notify()) another tasklet attempts to call handshake_wait_for(notifier) with\n *              the same tasklet in the parameter, the function will do nothing and will return the number\n *              of error and set the errno to the corresponding error number.\n */\n\n#include <sysdef.h>\n\n/**\n * @fn handshake_notify\n * @brief Notifies a tasklet waiting for the notifier.\n *\n * The invoking tasklet is suspended until another tasklet calls handshake_wait_for(notifier).\n * When this condition is reached, the function resumes the waiting tasklet.\n */\nvoid\nhandshake_notify(void);\n\n/**\n * @fn handshake_wait_for\n * @brief Waits for the notifier tasklet\n *\n * The invoking tasklet is suspended until the notifier tasklet (indicated in the parameter) sends a\n * notification to tell the invoking tasklet that it can go ahead.\n *\n * Beware that if the notifier tasklet and the invoking tasklet are the same, the tasklet will be suspended with no\n * easy way to wake it up. The user should check this case itself if it is something that their program allows.\n *\n * If the number of the notifier is not a defined tasklet, the function behavior is undefined. If some other tasklet has\n * already called handshake_wait_for() with the same notifier in the parameter and that the notifier has not yet called\n * handshake_notify(), the function will do nothing and simply return EALREADY.\n *\n * In both cases the errno will be set to the corresponding error number.\n *\n * @param notifier a number to wait the notification from. It must be a defined tasklet.\n * @return 0 if no error was detected, EALREADY if a corresponding error was detected.\n */\nint\nhandshake_wait_for(sysname_t notifier);\n\n#endif /* DPUSYSCORE_HANDSHAKE_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_endianness.h",
    "content": "/* ===-- int_endianness.h - configuration header for compiler-rt ------------===\n *\n *\t\t       The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_ENDIANNESS_H\n#define INT_ENDIANNESS_H\n\n#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && defined(__ORDER_LITTLE_ENDIAN__)\n\n/* Clang and GCC provide built-in endianness definitions. */\n#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* __BYTE_ORDER__ */\n\n#else /* Compilers other than Clang or GCC. */\n\n#if defined(__SVR4) && defined(__sun)\n#include <sys/byteorder.h>\n\n#if defined(_BIG_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif defined(_LITTLE_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#else /* !_LITTLE_ENDIAN */\n#error \"unknown endianness\"\n#endif /* !_LITTLE_ENDIAN */\n\n#endif /* Solaris and AuroraUX. */\n\n/* .. */\n\n#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__minix)\n#include <sys/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* *BSD */\n\n#if defined(__OpenBSD__) || defined(__Bitrig__)\n#include <machine/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* OpenBSD and Bitrig. */\n\n/* .. */\n\n/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the\n * compiler (at least with GCC) */\n#if defined(__APPLE__) || defined(__ellcc__)\n\n#ifdef __BIG_ENDIAN__\n#if __BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#endif\n#endif /* __BIG_ENDIAN__ */\n\n#ifdef __LITTLE_ENDIAN__\n#if __LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif\n#endif /* __LITTLE_ENDIAN__ */\n\n#endif /* Mac OSX */\n\n/* .. */\n\n#if defined(_WIN32)\n\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n\n#endif /* Windows */\n\n#endif /* Clang or GCC. */\n\n/* . */\n\n#if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN)\n#error Unable to determine endian\n#endif /* Check we found an endianness correctly. */\n\n#endif /* INT_ENDIANNESS_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_lib.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_LIB_H\n#define INT_LIB_H\n\n/* Assumption: Signed integral is 2's complement. */\n/* Assumption: Right shift of signed negative is arithmetic shift. */\n/* Assumption: Endianness is little or big (not mixed). */\n\n#if defined(__ELF__)\n#define FNALIAS(alias_name, original_name) void alias_name() __attribute__((alias(#original_name)))\n#else\n#define FNALIAS(alias, name) _Pragma(\"GCC error(\\\"alias unsupported on this file format\\\")\")\n#endif\n\n/* ABI macro definitions */\n\n#if __ARM_EABI__\n#ifdef COMPILER_RT_ARMHF_TARGET\n#define COMPILER_RT_ABI\n#else\n#define COMPILER_RT_ABI __attribute__((__pcs__(\"aapcs\")))\n#endif\n#else\n#define COMPILER_RT_ABI\n#endif\n\n#define AEABI_RTABI __attribute__((__pcs__(\"aapcs\")))\n\n#ifdef _MSC_VER\n#define ALWAYS_INLINE __forceinline\n#define NOINLINE __declspec(noinline)\n#define NORETURN __declspec(noreturn)\n#define UNUSED\n#else\n#define ALWAYS_INLINE __attribute__((always_inline))\n#define NOINLINE __attribute__((noinline))\n#define NORETURN __attribute__((noreturn))\n#define UNUSED __attribute__((unused))\n#endif\n\n#if defined(__NetBSD__) && (defined(_KERNEL) || defined(_STANDALONE))\n/*\n * Kernel and boot environment can't use normal headers,\n * so use the equivalent system headers.\n */\n#include <machine/limits.h>\n#include <sys/stdint.h>\n#include <sys/types.h>\n#else\n/* Include the standard compiler builtin headers we use functionality from. */\n#include <limits.h>\n#include <stdint.h>\n#include <stdbool.h>\n#include <float.h>\n#endif\n\n/* Include the commonly used internal type definitions. */\n#include \"int_types.h\"\n\n/* Include internal utility function declarations. */\n#include \"int_util.h\"\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a);\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a);\n\nCOMPILER_RT_ABI di_int\n__divdi3(di_int a, di_int b);\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b);\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem);\nCOMPILER_RT_ABI du_int\n__udivmoddi4(du_int a, du_int b, du_int *rem);\n#ifdef CRT_HAS_128BIT\nCOMPILER_RT_ABI si_int\n__clzti2(ti_int a);\nCOMPILER_RT_ABI tu_int\n__udivmodti4(tu_int a, tu_int b, tu_int *rem);\n#endif\n\n/* Definitions for builtins unavailable on MSVC */\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <intrin.h>\n\nuint32_t __inline __builtin_ctz(uint32_t value)\n{\n    unsigned long trailing_zero = 0;\n    if (_BitScanForward(&trailing_zero, value))\n        return trailing_zero;\n    return 32;\n}\n\nuint32_t __inline __builtin_clz(uint32_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse(&leading_zero, value))\n        return 31 - leading_zero;\n    return 32;\n}\n\n#if defined(_M_ARM) || defined(_M_X64)\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse64(&leading_zero, value))\n        return 63 - leading_zero;\n    return 64;\n}\n#else\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    if (value == 0)\n        return 64;\n    uint32_t msh = (uint32_t)(value >> 32);\n    uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF);\n    if (msh != 0)\n        return __builtin_clz(msh);\n    return 32 + __builtin_clz(lsh);\n}\n#endif\n\n#define __builtin_clzl __builtin_clzll\n#endif /* defined(_MSC_VER) && !defined(__clang__) */\n\n#endif /* INT_LIB_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_math.h",
    "content": "/* ===-- int_math.h - internal math inlines ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines substitutes for the libm functions used in some of the\n * compiler-rt implementations, defined in such a way that there is not a direct\n * dependency on libm or math.h. Instead, we use the compiler builtin versions\n * where available. This reduces our dependencies on the system SDK by foisting\n * the responsibility onto the compiler.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_MATH_H\n#define INT_MATH_H\n\n#ifndef __has_builtin\n#define __has_builtin(x) 0\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <math.h>\n#include <stdlib.h>\n#include <ymath.h>\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define CRT_INFINITY INFINITY\n#else\n#define CRT_INFINITY __builtin_huge_valf()\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_isfinite(x) _finite((x))\n#define crt_isinf(x) !_finite((x))\n#define crt_isnan(x) _isnan((x))\n#else\n/* Define crt_isfinite in terms of the builtin if available, otherwise provide\n * an alternate version in terms of our other functions. This supports some\n * versions of GCC which didn't have __builtin_isfinite.\n */\n#if __has_builtin(__builtin_isfinite)\n#define crt_isfinite(x) __builtin_isfinite((x))\n#elif defined(__GNUC__)\n#define crt_isfinite(x)                                                                                                          \\\n    __extension__(({                                                                                                             \\\n        __typeof((x)) x_ = (x);                                                                                                  \\\n        crt_isinf(x_) && crt_isnan(x_);                                                                                          \\\n    }))\n#else\n#error \"Do not know how to check for infinity\"\n#endif /* __has_builtin(__builtin_isfinite) */\n#define crt_isinf(x) __builtin_isinf((x))\n#define crt_isnan(x) __builtin_isnan((x))\n#endif /* _MSC_VER */\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_copysign(x, y) copysign((x), (y))\n#define crt_copysignf(x, y) copysignf((x), (y))\n#define crt_copysignl(x, y) copysignl((x), (y))\n#else\n#define crt_copysign(x, y) __builtin_copysign((x), (y))\n#define crt_copysignf(x, y) __builtin_copysignf((x), (y))\n#define crt_copysignl(x, y) __builtin_copysignl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fabs(x) fabs((x))\n#define crt_fabsf(x) fabsf((x))\n#define crt_fabsl(x) fabs((x))\n#else\n#define crt_fabs(x) __builtin_fabs((x))\n#define crt_fabsf(x) __builtin_fabsf((x))\n#define crt_fabsl(x) __builtin_fabsl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fmax(x, y) __max((x), (y))\n#define crt_fmaxf(x, y) __max((x), (y))\n#define crt_fmaxl(x, y) __max((x), (y))\n#else\n#define crt_fmax(x, y) __builtin_fmax((x), (y))\n#define crt_fmaxf(x, y) __builtin_fmaxf((x), (y))\n#define crt_fmaxl(x, y) __builtin_fmaxl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_logb(x) logb((x))\n#define crt_logbf(x) logbf((x))\n#define crt_logbl(x) logbl((x))\n#else\n#define crt_logb(x) __builtin_logb((x))\n#define crt_logbf(x) __builtin_logbf((x))\n#define crt_logbl(x) __builtin_logbl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_scalbn(x, y) scalbn((x), (y))\n#define crt_scalbnf(x, y) scalbnf((x), (y))\n#define crt_scalbnl(x, y) scalbnl((x), (y))\n#else\n#define crt_scalbn(x, y) __builtin_scalbn((x), (y))\n#define crt_scalbnf(x, y) __builtin_scalbnf((x), (y))\n#define crt_scalbnl(x, y) __builtin_scalbnl((x), (y))\n#endif\n\n#endif /* INT_MATH_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_types.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines various standard types, most importantly a number of unions\n * used to access parts of larger types.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_TYPES_H\n#define INT_TYPES_H\n\n#include \"int_endianness.h\"\n\n/* si_int is defined in Linux sysroot's asm-generic/siginfo.h */\n#ifdef si_int\n#undef si_int\n#endif\ntypedef int si_int;\ntypedef unsigned su_int;\n\ntypedef long long di_int;\ntypedef unsigned long long du_int;\n\ntypedef union {\n    di_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        si_int high;\n#else\n        si_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} dwords;\n\ntypedef union {\n    du_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        su_int high;\n#else\n        su_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} udwords;\n\n#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64))\n#define CRT_HAS_128BIT\n#endif\n\n#ifdef CRT_HAS_128BIT\ntypedef int ti_int __attribute__((mode(TI)));\ntypedef unsigned tu_int __attribute__((mode(TI)));\n\ntypedef union {\n    ti_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        di_int high;\n#else\n        di_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} twords;\n\ntypedef union {\n    tu_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        du_int high;\n#else\n        du_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} utwords;\n\nstatic __inline ti_int\nmake_ti(di_int h, di_int l)\n{\n    twords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\nstatic __inline tu_int\nmake_tu(du_int h, du_int l)\n{\n    utwords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\n#endif /* CRT_HAS_128BIT */\n\ntypedef union {\n    su_int u;\n    float f;\n} float_bits;\n\ntypedef union {\n    udwords u;\n    double f;\n} double_bits;\n\ntypedef struct {\n#if _YUGA_LITTLE_ENDIAN\n    udwords low;\n    udwords high;\n#else\n    udwords high;\n    udwords low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n} uqwords;\n\ntypedef union {\n    uqwords u;\n    long double f;\n} long_double_bits;\n\n#if __STDC_VERSION__ >= 199901L\ntypedef float _Complex Fcomplex;\ntypedef double _Complex Dcomplex;\ntypedef long double _Complex Lcomplex;\n\n#define COMPLEX_REAL(x) __real__(x)\n#define COMPLEX_IMAGINARY(x) __imag__(x)\n#else\ntypedef struct {\n    float real, imaginary;\n} Fcomplex;\n\ntypedef struct {\n    double real, imaginary;\n} Dcomplex;\n\ntypedef struct {\n    long double real, imaginary;\n} Lcomplex;\n\n#define COMPLEX_REAL(x) (x).real\n#define COMPLEX_IMAGINARY(x) (x).imaginary\n#endif\n#endif /* INT_TYPES_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_util.c",
    "content": "/* ===-- int_util.c - Implement internal utilities --------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_util.h\"\n\n/* NOTE: The definitions in this file are declared weak because we clients to be\n * able to arbitrarily package individual functions into separate .a files. If\n * we did not declare these weak, some link situations might end up seeing\n * duplicate strong definitions of the same symbol.\n *\n * We can't use this solution for kernel use (which may not support weak), but\n * currently expect that when built for kernel use all the functionality is\n * packaged into a single library.\n */\n\n#ifdef KERNEL_USE\n\nNORETURN extern void\npanic(const char *, ...);\n#ifndef _WIN32\n__attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    panic(\"%s:%d: abort in %s\", file, line, function);\n}\n\n#elif __APPLE__\n\n/* from libSystem.dylib */\nNORETURN extern void\n__assert_rtn(const char *func, const char *file, int line, const char *message);\n\n#ifndef _WIN32\n__attribute__((weak)) __attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    __assert_rtn(function, file, line, \"libcompiler_rt abort\");\n}\n\n#else\n\n/* Get the system definition of abort() */\n#include <stdlib.h>\n\n#ifndef _WIN32\n// JFR dirty patch\n// DPUCC doesn't like it either __attribute__((weak))\n// DPUCC doesn't like it either __attribute__((visibility(\"hidden\")))\n// End of patch\n#endif\nvoid\ncompilerrt_abort_impl(const char *file __attribute__((unused)),\n    int line __attribute__((unused)),\n    const char *function __attribute__((unused)))\n{\n    abort();\n}\n\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/int_util.h",
    "content": "/* ===-- int_util.h - internal utility functions ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines non-inline utilities which are available for use in the\n * library. The function definitions themselves are all contained in int_util.c\n * which will always be compiled into any compiler-rt library.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_UTIL_H\n#define INT_UTIL_H\n\n/** \\brief Trigger a program abort (or panic for kernel code). */\n#define compilerrt_abort() compilerrt_abort_impl(__FILE__, __LINE__, __func__)\n\nNORETURN void\ncompilerrt_abort_impl(const char *file, int line, const char *function);\n\n#define COMPILE_TIME_ASSERT(expr) COMPILE_TIME_ASSERT1(expr, __COUNTER__)\n#define COMPILE_TIME_ASSERT1(expr, cnt) COMPILE_TIME_ASSERT2(expr, cnt)\n#define COMPILE_TIME_ASSERT2(expr, cnt) typedef char ct_assert_##cnt[(expr) ? 1 : -1] UNUSED\n\n#endif /* INT_UTIL_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/listener.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#include <sysdef.h>\n#include <defs.h>\n\nextern bool\nfetch_request(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\nextern bool\nfifo_is_full(uint32_t fifo_info, uint32_t request_size);\nextern void\nfifo_produce(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\n\nstatic inline uint32_t\nfifo_sys_fetch_info(uint32_t fid)\n{\n    extern uint32_t __sys_fifo_sys_table;\n    return (&__sys_fifo_sys_table)[fid];\n}\n\nstatic inline uint32_t\nfifo_fetch_info(sysname_t recipient)\n{\n    extern uint32_t __sys_fifo_table_ptr;\n    return *((uint32_t *)((&__sys_fifo_table_ptr)[recipient] & 0xFFFF));\n}\n\nstatic inline sysname_t\nfetch_recipient(uint32_t id)\n{\n    return id >> 24;\n}\n\nstatic inline sysname_t\nfetch_request_id(uint32_t id)\n{\n    return id & 0x00FFFFFF;\n}\n\nvoid\n__sys_internal_listener_loop(uint32_t *request, uint32_t request_size)\n{\n    sysname_t id = me();\n    uint32_t self_fifo_info;\n    uint32_t from_host_fifo_info;\n    uint32_t to_host_fifo_info;\n\n    self_fifo_info = fifo_fetch_info(id);\n    from_host_fifo_info = fifo_sys_fetch_info(0);\n    to_host_fifo_info = fifo_sys_fetch_info(1);\n\n    while (true) {\n        if (fetch_request(self_fifo_info, request, request_size)) {\n            while (fifo_is_full(to_host_fifo_info, request_size)) {\n                // Waiting for the recipient to read some of its pending requests...\n                // Do we want to add some \"sleep\" here?\n            }\n\n            fifo_produce(to_host_fifo_info, request, request_size);\n        }\n        if (fetch_request(from_host_fifo_info, request, request_size)) {\n            sysname_t recipient = fetch_recipient(request[0]);\n\n            /* If a message is sent to the listener from the host, we interpret it as a shutdown order. */\n            if (recipient == id)\n                break;\n\n            request[0] = fetch_request_id(request[0]);\n\n            extern void internal_actor_send(uint32_t recipient, uint32_t * request, uint32_t request_size);\n            internal_actor_send(recipient, request, request_size);\n        }\n\n        // Waiting for some request...\n        // Do we want to add some \"sleep\" here?\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/lshrdi3.c",
    "content": "/* ===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __lshrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: logical a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__lshrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    udwords input;\n    udwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.high = 0;\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsr(di_int a, si_int b)\n{\n    return __lshrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/macro_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MACRO_UTILS_H\n#define DPUSYSCORE_MACRO_UTILS_H\n\n/**\n * @file macro_utils.h\n * @brief Provide utility macros.\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\n#define __CONCAT(x, y) __CONCAT_AGAIN(x, y)\n#define __CONCAT_AGAIN(x, y) x##y\n\n#define __REPEAT_0(x)\n#define __REPEAT_1(x) x(0) __REPEAT_0(x)\n#define __REPEAT_2(x) x(1) __REPEAT_1(x)\n#define __REPEAT_3(x) x(2) __REPEAT_2(x)\n#define __REPEAT_4(x) x(3) __REPEAT_3(x)\n#define __REPEAT_5(x) x(4) __REPEAT_4(x)\n#define __REPEAT_6(x) x(5) __REPEAT_5(x)\n#define __REPEAT_7(x) x(6) __REPEAT_6(x)\n#define __REPEAT_8(x) x(7) __REPEAT_7(x)\n#define __REPEAT_9(x) x(8) __REPEAT_8(x)\n#define __REPEAT_10(x) x(9) __REPEAT_9(x)\n#define __REPEAT_11(x) x(10) __REPEAT_10(x)\n#define __REPEAT_12(x) x(11) __REPEAT_11(x)\n#define __REPEAT_13(x) x(12) __REPEAT_12(x)\n#define __REPEAT_14(x) x(13) __REPEAT_13(x)\n#define __REPEAT_15(x) x(14) __REPEAT_14(x)\n#define __REPEAT_16(x) x(15) __REPEAT_15(x)\n#define __REPEAT_17(x) x(16) __REPEAT_16(x)\n#define __REPEAT_18(x) x(17) __REPEAT_17(x)\n#define __REPEAT_19(x) x(18) __REPEAT_18(x)\n#define __REPEAT_20(x) x(19) __REPEAT_19(x)\n#define __REPEAT_21(x) x(20) __REPEAT_20(x)\n#define __REPEAT_22(x) x(21) __REPEAT_21(x)\n#define __REPEAT_23(x) x(22) __REPEAT_22(x)\n#define __REPEAT_24(x) x(23) __REPEAT_23(x)\n#define __FOR_EACH_THREAD(x) __CONCAT(__REPEAT_, NR_THREADS)(x)\n\n#endif /* DPUSYSCORE_MACRO_UTILS_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mcount.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, noinline, no_instrument_function)) mcount(void)\n{\n    // Please see ret_mcount comment regarding why mcount references ret_mcount.\n    __asm__ volatile(\"jump ret_mcount\");\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) ret_mcount(void)\n{\n    // ret_mcount is used in statistics mode, mcount *must* reference ret_mcount\n    // so that ret_mcount symbol is not gc (remember that we patch the binary\n    // when copying it to iram).\n    __asm__ volatile(\"sh id4, thread_profiling, r23\\n\"\n                     \"jump r23\");\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/moddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__moddi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 1);\n        } else {\n            return __udiv64(dividend, -divider, 1);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 1);\n    } else {\n        // Negative dividend, negative divider\n        return -__udiv64(-dividend, -divider, 1);\n    }\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/modsi3.c",
    "content": "/* ===-- modsi3.c - Implement __modsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __modsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__modsi3(si_int a, si_int b)\n{\n    long res = __div32(a, b);\n    return (int)res;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mram.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MRAM_H\n#define DPUSYSCORE_MRAM_H\n\n#include <stdint.h>\n#include <attributes.h>\n\n/**\n * @file mram.h\n * @brief MRAM Transfer Management.\n */\n\n#define DPU_MRAM_HEAP_POINTER ((__mram_ptr void *)(&__sys_used_mram_end))\nextern __mram_ptr __dma_aligned uint8_t __sys_used_mram_end[0];\n\n/**\n * @fn mram_read\n * @brief Stores the specified number of bytes from MRAM to WRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in MRAM\n * @param to destination address in WRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_read(const __mram_ptr void *from, void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_ldma(to, from, nb_of_bytes);\n}\n\n/**\n * @fn mram_write\n * @brief Stores the specified number of bytes from WRAM to MRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in WRAM\n * @param to destination address in MRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_write(const void *from, __mram_ptr void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_sdma(from, to, nb_of_bytes);\n}\n\n#endif /* DPUSYSCORE_MRAM_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mul32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nint __attribute__((noinline)) __mulsi3(int a, int b)\n{\n    int dest;\n    __asm__ volatile(\"  jgtu %2, %1, __mulsi3_swap\\n\"\n                     \"  move r2, %1\\n\"\n                     \"  move r0, %2, true, __mulsi3_start\\n\"\n                     \"__mulsi3_swap:\\n\"\n                     \"  move r2, %2\\n\"\n                     \"  move r0, %1\\n\"\n                     \"__mulsi3_start:\\n\"\n                     \"  move r1, zero\\n\"\n                     \"  mul_step d0, r2, d0, 0 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 1 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 2 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 3 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 4 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 5 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 6 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 7 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 8 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 9 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 10, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 11, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 12, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 13, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 14, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 15, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 16, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 17, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 18, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 19, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 20, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 21, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 22, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 23, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 24, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 25, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 26, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 27, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 28, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 29, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 30, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 31, z, __mulsi3_exit\\n\"\n                     \"__mulsi3_exit:\\n\"\n                     \"  move %0, r1\\n\"\n                     : \"=r\"(dest)\n                     : \"r\"(a), \"r\"(b));\n    return dest;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mul64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication emulation.\n *\n * A relatively fast emulation of 64x64 multiplication using byte multipliers.\n * Basically, the two operands X and Y are seen as byte polynomials:\n *  - X = X0.2^0 + X1.2^8 + X2.2^16 + X3.2^24 + X4.2^32 + X5.2^40 + X6.2^48 + X7.2^56\n *  - Y = Y0.2^0 + Y1.2^8 + Y2.2^16 + Y3.2^24 + Y4.2^32 + Y5.2^40 + Y6.2^48 + Y7.2^56\n *\n * The product Z is expressed as a similar polynomial. Since the result is 64 bits,\n * the function drops any coefficient for a power greater than 56, hence the following\n * formula:\n *  Z = (X0.Y0).2^0\n *      + (X0.Y1 + X1.Y0).2^8\n *      + (X0.Y2 + X2.Y0 + X1.Y1).2^16\n *      + (X0.Y3 + X1.Y2 + X2.Y1 + X3.Y0).2^24\n *      + (X0.Y4 + X1.Y3 + X2.Y2 + X3.Y1 + X4.Y0).2^32\n *      etc.\n *\n * Each individual produce is computed with the native built-in 8x8 instructions.\n * Resulting processing time is in the magnitude of 150 instructions.\n *\n * The two operands are found in __D0 and the first kernel nano-stack entry.\n * The result goes into __R0 (lsbits) and __R1 (msbits).\n * Also, __R2 contains the return address register, instead of __RET__.\n */\n#include <stdint.h>\n\nstatic uint16_t\n_mul00(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * (b & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul01(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\n#define _mul02(a, b) _mul00(a, (b >> 16))\n#define _mul03(a, b) _mul01(a, (b >> 16))\n\nstatic uint16_t\n_mul11(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul12(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 16) & 0xff);\n#else\n    uint32_t r = (b >> 16);\n    __asm__ volatile(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(r) :);\n    return r;\n#endif\n}\n\n#define _mul13(a, b) _mul11(a, (b >> 16))\n#define _mul22(a, b) _mul00((a >> 16), (b >> 16))\n#define _mul23(a, b) _mul01((a >> 16), (b >> 16))\n#define _mul33(a, b) _mul11((a >> 16), (b >> 16))\n\n#define mulx0y0(xl, yl) _mul00(xl, yl)\n#define mulx0y1(xl, yl) _mul01(xl, yl)\n#define mulx0y2(xl, yl) _mul02(xl, yl)\n#define mulx0y3(xl, yl) _mul03(xl, yl)\n#define mulx0y4(xl, yh) _mul00(xl, yh)\n#define mulx0y5(xl, yh) _mul01(xl, yh)\n#define mulx0y6(xl, yh) _mul02(xl, yh)\n#define mulx0y7(xl, yh) _mul03(xl, yh)\n\n#define mulx1y1(xl, yl) _mul11(xl, yl)\n#define mulx1y2(xl, yl) _mul12(xl, yl)\n#define mulx1y3(xl, yl) _mul13(xl, yl)\n#define mulx1y4(xl, yh) _mul01(yh, xl)\n#define mulx1y5(xl, yh) _mul11(xl, yh)\n#define mulx1y6(xl, yh) _mul12(xl, yh)\n\n#define mulx2y2(xl, yl) _mul22(xl, yl)\n#define mulx2y3(xl, yl) _mul23(xl, yl)\n#define mulx2y4(xl, yh) _mul02(yh, xl)\n#define mulx2y5(xl, yh) _mul12(yh, xl)\n\n#define mulx3y3(xl, yl) _mul33(xl, yl)\n#define mulx3y4(xl, yh) _mul03(yh, xl)\n\n// Symmetry...\n#define mulx1y0(xl, yl) mulx0y1(yl, xl)\n#define mulx2y0(xl, yl) mulx0y2(yl, xl)\n#define mulx2y1(xl, yl) mulx1y2(yl, xl)\n#define mulx3y0(xl, yl) mulx0y3(yl, xl)\n#define mulx3y1(xl, yl) mulx1y3(yl, xl)\n#define mulx3y2(xl, yl) mulx2y3(yl, xl)\n#define mulx4y0(xh, yl) mulx0y4(yl, xh)\n#define mulx4y1(xh, yl) mulx1y4(yl, xh)\n#define mulx4y2(xh, yl) mulx2y4(yl, xh)\n#define mulx4y3(xh, yl) mulx3y4(yl, xh)\n#define mulx5y0(xh, yl) mulx0y5(yl, xh)\n#define mulx5y1(xh, yl) mulx1y5(yl, xh)\n#define mulx5y2(xh, yl) mulx2y5(yl, xh)\n#define mulx6y0(xh, yl) mulx0y6(yl, xh)\n#define mulx6y1(xh, yl) mulx1y6(yl, xh)\n#define mulx7y0(xh, yl) mulx0y7(yl, xh)\n\nuint64_t\n__muldi3(uint64_t x, uint64_t y)\n{\n    uint32_t xl = x;\n    uint32_t xh = ((uint64_t)x >> 32);\n    uint32_t yl = y;\n    uint32_t yh = ((uint64_t)y >> 32);\n\n    // Each fragment of the product.\n    uint32_t p0, p1, p2, p3, p4, p5, p6, p7, rh;\n    uint64_t rl;\n\n    p0 = mulx0y0(xl, yl);\n    rl = (uint64_t)p0;\n    p1 = mulx0y1(xl, yl) + mulx1y0(xl, yl);\n    rl += ((uint64_t)p1 << 8);\n    p2 = mulx0y2(xl, yl) + mulx2y0(xl, yl) + mulx1y1(xl, yl);\n    rl += ((uint64_t)p2 << 16);\n    p3 = mulx0y3(xl, yl) + mulx3y0(xl, yl) + mulx1y2(xl, yl) + mulx2y1(xl, yl);\n    rl += ((uint64_t)p3 << 24);\n    p4 = mulx0y4(xl, yh) + mulx4y0(xh, yl) + mulx1y3(xl, yl) + mulx3y1(xl, yl) + mulx2y2(xl, yl);\n    rh = p4;\n    p5 = mulx0y5(xl, yh) + mulx5y0(xh, yl) + mulx1y4(xl, yh) + mulx4y1(xh, yl) + mulx2y3(xl, yl) + mulx3y2(xl, yl);\n    rh += p5 << 8;\n    p6 = mulx0y6(xl, yh) + mulx6y0(xh, yl) + mulx1y5(xl, yh) + mulx5y1(xh, yl) + mulx2y4(xl, yh) + mulx4y2(xh, yl)\n        + mulx3y3(xl, yl);\n    rh += p6 << 16;\n    p7 = mulx0y7(xl, yh) + mulx7y0(xh, yl) + mulx1y6(xl, yh) + mulx6y1(xh, yl) + mulx2y5(xl, yh) + mulx5y2(xh, yl)\n        + mulx3y4(xl, yh) + mulx4y3(xh, yl);\n    rh += p7 << 24;\n\n    return rl + (((uint64_t)rh) << 32);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/muldc3.c",
    "content": "/* ===-- muldc3.c - Implement __muldc3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __muldc3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_math.h\"\n\n/* Returns: the product of a + ib and c + id */\n\nCOMPILER_RT_ABI Dcomplex\n__muldc3(double __a, double __b, double __c, double __d)\n{\n    double __ac = __a * __c;\n    double __bd = __b * __d;\n    double __ad = __a * __d;\n    double __bc = __b * __c;\n    Dcomplex z;\n    COMPLEX_REAL(z) = __ac - __bd;\n    COMPLEX_IMAGINARY(z) = __ad + __bc;\n    if (crt_isnan(COMPLEX_REAL(z)) && crt_isnan(COMPLEX_IMAGINARY(z))) {\n        int __recalc = 0;\n        if (crt_isinf(__a) || crt_isinf(__b)) {\n            __a = crt_copysign(crt_isinf(__a) ? 1 : 0, __a);\n            __b = crt_copysign(crt_isinf(__b) ? 1 : 0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (crt_isinf(__c) || crt_isinf(__d)) {\n            __c = crt_copysign(crt_isinf(__c) ? 1 : 0, __c);\n            __d = crt_copysign(crt_isinf(__d) ? 1 : 0, __d);\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            __recalc = 1;\n        }\n        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) || crt_isinf(__ad) || crt_isinf(__bc))) {\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (__recalc) {\n            COMPLEX_REAL(z) = CRT_INFINITY * (__a * __c - __b * __d);\n            COMPLEX_IMAGINARY(z) = CRT_INFINITY * (__a * __d + __b * __c);\n        }\n    }\n    return z;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/muldf3.c",
    "content": "//===-- lib/muldf3.c - Double-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__muldf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dmul(fp_t a, fp_t b)\n{\n    return __muldf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mulodi4.c",
    "content": "/*===-- mulodi4.c - Implement __mulodi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulodi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulodi4(di_int a, di_int b, int *overflow)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    *overflow = 0;\n    di_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mulosi4.c",
    "content": "/*===-- mulosi4.c - Implement __mulosi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulosi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulosi4(si_int a, si_int b, int *overflow)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    *overflow = 0;\n    si_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mulsf3.c",
    "content": "//===-- lib/mulsf3.c - Single-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__mulsf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fmul(fp_t a, fp_t b)\n{\n    return __mulsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mulvdi3.c",
    "content": "/*===-- mulvdi3.c - Implement __mulvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulvdi3(di_int a, di_int b)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mulvsi3.c",
    "content": "/* ===-- mulvsi3.c - Implement __mulvsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulvsi3(si_int a, si_int b)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/mutex.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MUTEX_H\n#define DPUSYSCORE_MUTEX_H\n\n/**\n * @file mutex.h\n * @brief Mutual exclusions.\n *\n * A mutex ensures mutual exclusion between threads: only one runtime can have the mutex at a time, blocking all the\n * other threads trying to take the mutex.\n *\n * @internal All the mutexes are stored in a table in WRAM. In this table, each byte represents a mutex,\n *           and can be accessed directly by taking the base address of the table and adding it the sysname of the mutex\n *           we want (thus, the sysname should be an integer in the range [0; NB_MUTEX -1]). The result of\n *           this addition is what a mutex_get will return.\n *           A lock is made by using an lb_a instruction on the address of the mutex given as a parameter.\n *           An unlock is made by using an sb_r instruction on the address of the mutex given as a parameter.\n *           The id of the runtime doing the unlock is what is currently stored at the address of the mutex.\n *           The base address of this table is associated with the pointer defined by __MUTEX_TABLE__.\n */\n\n#include <stdint.h>\n#include <sysdef.h>\n#include <stdbool.h>\n#include <atomic_bit.h>\n\n/**\n * @typedef mutex_id_t\n * @brief A mutex object reference, as declared by MUTEX_INIT.\n */\ntypedef uint8_t *mutex_id_t;\n\n/**\n * @def MUTEX_GET\n * @hideinitializer\n * @brief Return the symbol to use when using the mutex associated to the given name.\n */\n#define MUTEX_GET(_name) _name\n\n/**\n * @def MUTEX_INIT\n * @hideinitializer\n * @brief Declare and initialize a mutex associated to the given name.\n */\n#define MUTEX_INIT(_name)                                                                                                        \\\n    ATOMIC_BIT_INIT(__CONCAT(mutex_, _name));                                                                                    \\\n    const mutex_id_t MUTEX_GET(_name) = &ATOMIC_BIT_GET(__CONCAT(mutex_, _name))\n\n/**\n * @fn mutex_lock\n * @brief Takes the lock on the given mutex.\n * @param mutex the mutex we want to lock\n */\nstatic inline void\nmutex_lock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"acquire %[mtx], 0, nz, .\" : : [mtx] \"r\"(mutex) :);\n}\n\n/**\n * @fn mutex_trylock\n * @brief Tries to take the lock on the given mutex. If the lock is already taken, returns immediately.\n * @param mutex the mutex we want to lock\n * @return Whether the mutex has been successfully locked.\n */\nstatic inline bool\nmutex_trylock(mutex_id_t mutex)\n{\n    bool result = true;\n    __asm__ volatile(\"acquire %[mtx], 0, z, .+2; move %[res], 0\" : [res] \"+r\"(result) : [mtx] \"r\"(mutex) :);\n    return result;\n}\n\n/**\n * @fn mutex_unlock\n * @brief Releases the lock on the given mutex.\n * @param mutex the mutex we want to unlock\n */\nstatic inline void\nmutex_unlock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"release %[mtx], 0, nz, .+1\" : : [mtx] \"r\"(mutex) :);\n}\n\n#endif /* DPUSYSCORE_MUTEX_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/negdf2.c",
    "content": "//===-- lib/negdf2.c - double-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negdf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dneg(fp_t a)\n{\n    return __negdf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/negdi2.c",
    "content": "/* ===-- negdi2.c - Implement __negdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\nCOMPILER_RT_ABI di_int\n__negdi2(di_int a)\n{\n    /* Note: this routine is here for API compatibility; any sane compiler\n     * should expand it inline.\n     */\n    return -a;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/negsf2.c",
    "content": "//===-- lib/negsf2.c - single-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negsf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fneg(fp_t a)\n{\n    return __negsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/negvdi2.c",
    "content": "/* ===-- negvdi2.c - Implement __negvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI di_int\n__negvdi2(di_int a)\n{\n    const di_int MIN = (di_int)1 << ((int)(sizeof(di_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/negvsi2.c",
    "content": "/* ===-- negvsi2.c - Implement __negvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI si_int\n__negvsi2(si_int a)\n{\n    const si_int MIN = (si_int)1 << ((int)(sizeof(si_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/paritydi2.c",
    "content": "/* ===-- paritydi2.c - Implement __paritydi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritydi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    return __paritysi2(x.s.high ^ x.s.low);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/paritysi2.c",
    "content": "/* ===-- paritysi2.c - Implement __paritysi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritysi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x ^= x >> 16;\n    x ^= x >> 8;\n    x ^= x >> 4;\n    return (0x6996 >> (x & 0xF)) & 1;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/perfcounter.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <perfcounter.h>\n#include <attributes.h>\n\n#define BIT_IMPRECISION 4\n\nperfcounter_t\nperfcounter_get(void)\n{\n    uint32_t reg_value;\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(reg_value));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n\n#ifndef DPU_PROFILING\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value)\n{\n    uint32_t reg_value;\n    uint32_t reg_config = (reset_value ? 1 : 0) | (config << 1);\n    __asm__ volatile(\"time_cfg %[r], %[c]\" : [r] \"=r\"(reg_value) : [c] \"r\"(reg_config));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n#endif /* !DPU_PROFILING */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/perfcounter.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PERFCOUNTER_H\n#define DPUSYSCORE_PERFCOUNTER_H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n/**\n * @file perfcounter.h\n * @brief Utilities concerning the performance counter register.\n *\n */\n\n/**\n * @typedef perfcounter_t\n * @brief A value which can be stored by the performance counter.\n */\ntypedef uint64_t perfcounter_t;\n\n/**\n * @enum perfcounter_config_t\n * @brief A configuration for the performance counter, defining what should be counted.\n *\n * @var COUNT_SAME          keep the previous configuration\n * @var COUNT_CYCLES        switch to counting clock cycles\n * @var COUNT_INSTRUCTIONS  switch to counting executed instructions\n * @var COUNT_NOTHING       does not count anything\n */\ntypedef enum _perfcounter_config_t {\n    COUNT_SAME = 0,\n    COUNT_CYCLES = 1,\n    COUNT_INSTRUCTIONS = 2,\n    COUNT_NOTHING = 3,\n} perfcounter_config_t;\n\n/**\n * @def CLOCKS_PER_SEC\n * @hideinitializer\n * @brief A number used to convert the value returned by the perfcounter_get and perfcounter_config functions into seconds,\n *        when counting clock cycles.\n */\nextern const volatile uint32_t CLOCKS_PER_SEC;\n\n/**\n * @fn perfcounter_get\n * @brief Fetch the value of the performance counter register.\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_get(void);\n\n#ifndef DPU_PROFILING\n/**\n * @fn perfcounter_config\n * @brief Configure the performance counter behavior.\n *\n * This function cannot be used when profiling an application.\n *\n * @param config        The new behavior for the performance counter register\n * @param reset_value   Whether the performance counter register should be set to 0\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value);\n#else\n#define perfcounter_config(config, reset_value)                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* !DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PERFCOUNTER_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/popcountdi2.c",
    "content": "/* ===-- popcountdi2.c - Implement __popcountdi2 ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountdi2(di_int a)\n{\n    du_int x2 = (du_int)a;\n    x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL);\n    /* Every 2 bits holds the sum of every pair of bits (32) */\n    x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) */\n    x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) */\n    su_int x = (su_int)(x2 + (x2 >> 32));\n    /* The lower 32 bits hold four 16 bit sums (5 significant bits). */\n    /*   Upper 32 bits are garbage */\n    x = x + (x >> 16);\n    /* The lower 16 bits hold two 32 bit sums (6 significant bits). */\n    /*   Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000007F; /* (7 significant bits) */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/popcountsi2.c",
    "content": "/* ===-- popcountsi2.c - Implement __popcountsi2 ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x = x - ((x >> 1) & 0x55555555);\n    /* Every 2 bits holds the sum of every pair of bits */\n    x = ((x >> 2) & 0x33333333) + (x & 0x33333333);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) */\n    x = (x + (x >> 4)) & 0x0F0F0F0F;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) */\n    x = (x + (x >> 16));\n    /* The lower 16 bits hold two 8 bit sums (5 significant bits).*/\n    /*    Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/powidf2.c",
    "content": "/* ===-- powidf2.cpp - Implement __powidf2 ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powidf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI double\n__powidf2(double a, si_int b)\n{\n    const int recip = b < 0;\n    double r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/powisf2.c",
    "content": "/*===-- powisf2.cpp - Implement __powisf2 ---------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powisf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI float\n__powisf2(float a, si_int b)\n{\n    const int recip = b < 0;\n    float r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/profiling.c",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include <profiling.h>\n#include <defs.h>\n#include <dpufault.h>\n#include <dpuruntime.h>\n#include <macro_utils.h>\n#include <stdint.h>\n#include <sysdef.h>\n\n#ifdef DPU_PROFILING\nvoid __attribute__((no_instrument_function)) profiling_start(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] != PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_ALREADY_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->start[tid] = perfcounter_value;\n}\n\nvoid __attribute__((no_instrument_function)) profiling_stop(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] == PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_NOT_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->count[tid] += perfcounter_value - context->start[tid];\n    context->start[tid] = PROFILING_RESET_VALUE;\n}\n#endif /* DPU_PROFILING */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/profiling.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PROFILING_H\n#define DPUSYSCORE_PROFILING_H\n\n/**\n * @file profiling.h\n * @brief Code section profiling management.\n */\n\n#include <attributes.h>\n#include <limits.h>\n#include <profiling_internals.h>\n\n#define PROFILING_RESET_VALUE (UINT32_MAX)\n\n/**\n * @def PROFILING_INIT\n * @hideinitializer\n * @brief Declare and initialize a profiling context associated to the given name.\n */\n#define PROFILING_INIT(_name)                                                                                                    \\\n    __section(\".dpu_profiling\") dpu_profiling_t _name = {                                                                        \\\n        .start = { [0 ...(NR_THREADS - 1)] = PROFILING_RESET_VALUE },                                                            \\\n        .count = { [0 ...(NR_THREADS - 1)] = 0 },                                                                                \\\n    }\n\n#ifdef DPU_PROFILING\n/**\n * @fn profiling_start\n * @brief Start profiling a code section.\n *\n * This function saves the perfcounter current value in the profiling context.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_start(dpu_profiling_t *context);\n\n/**\n * @fn profiling_stop\n * @brief Stop profiling a code section.\n *\n * This function gets the perfcounter current value and computes the number of cyles spent in the code section.\n * The profiling_start function must be called beforehand.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_stop(dpu_profiling_t *context);\n#else\n#define profiling_start(context)                                                                                                 \\\n    do {                                                                                                                         \\\n    } while (0)\n#define profiling_stop(context)                                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PROFILING_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/profiling_internals.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/* Shared with backends */\n\n#ifndef DPUSYSCORE_PROFILING_INTERNALS_H\n#define DPUSYSCORE_PROFILING_INTERNALS_H\n\n/**\n * @file profiling_internals.h\n * @brief Code section profiling internals.\n */\n\n#include <stdint.h>\n\n#ifndef NR_THREADS\n#ifdef DPU_NR_THREADS\n#define NR_THREADS DPU_NR_THREADS\n#else\n#error \"DPU_NR_THREADS and NR_THREADS are undefined\"\n#endif /* DPU_NR_THREADS */\n#endif /* !NR_THREADS */\n\n/**\n * @typedef dpu_profiling_t\n * @brief A profiling context.\n */\ntypedef struct {\n    uint32_t start[NR_THREADS];\n    uint32_t count[NR_THREADS];\n} dpu_profiling_t;\n\n#endif /* DPUSYSCORE_PROFILING_INTERNALS_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/sem.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <sem.h>\n\n#include <defs.h>\n#include <dpuruntime.h>\n\nvoid\nsem_take(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    char count = sem->count - 1;\n    thread_id_t tid = me();\n\n    if (count < 0) {\n        unsigned char last = sem->wait_queue;\n\n        if (last != __EMPTY_WAIT_QUEUE) {\n            unsigned char first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        } else {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        }\n\n        sem->wait_queue = tid;\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    } else {\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    }\n}\n\nvoid\nsem_give(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = sem->count + 1;\n    unsigned char last = sem->wait_queue;\n\n    if (last != __EMPTY_WAIT_QUEUE) {\n        unsigned char first = __WAIT_QUEUE_TABLE[last];\n\n        if (first == last) {\n            sem->wait_queue = __EMPTY_WAIT_QUEUE;\n        } else {\n            __WAIT_QUEUE_TABLE[last] = __WAIT_QUEUE_TABLE[first];\n        }\n\n        __resume(first, \"0\");\n    }\n\n    sem->count = count;\n    __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/sem.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEM_H\n#define DPUSYSCORE_SEM_H\n\n/**\n * @file sem.h\n * @brief Synchronization with semaphores.\n *\n * A semaphore is characterized by a counter and a wait queue. It provides two functions:\n *\n *   - Take: the counter is decremented by 1. If the counter is negative, the runtime is blocked (stop) and placed in the\n *     semaphore's wait queue, waiting to be resume by another runtime.\n *   - Give: the counter is incremented by 1. If the counter was negative before the increment, the runtime resumes the execution\n *     of the first runtime waiting in the waiting queue. In all the cases, the runtime continues its own execution.\n *\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef sem_t\n * @brief A semaphore object, as declared by SEMAPHORE_INIT.\n */\ntypedef struct sem_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} sem_t;\n\n/**\n * @def SEMAPHORE_INIT\n * @hideinitializer\n * @brief Declare and initialize a semaphore associated to the given name.\n */\n/* clang-format off */\n#define SEMAPHORE_INIT(_name, _counter)                                                                                          \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"semaphore counter must be encoded on a byte\");                       \\\n    ATOMIC_BIT_INIT(__CONCAT(semaphore_, _name));                                                                                \\\n    extern sem_t (_name);                                                                                                        \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR(_name) \",@object\\n\"                                                                                   \\\n            \".globl \" __STR(_name) \"\\n\"                                                                                          \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(semaphore_, _name))) \"\\n\"                                                     \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn sem_take\n * @brief Takes one unit in the given semaphore (cf Take definition).\n * @param sem the semaphore we want to take\n */\nvoid\nsem_take(sem_t *sem);\n\n/**\n * @fn sem_give\n * @brief Gives on unit in the given semaphore (cf Give definition).\n * @param sem the semaphore we want to give\n */\nvoid\nsem_give(sem_t *sem);\n\n#endif /* DPUSYSCORE_SEM_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEQREAD_H\n#define DPUSYSCORE_SEQREAD_H\n\n/**\n * @file seqread.h\n * @brief Sequential reading of items in MRAM.\n *\n * A sequential reader allows to parse a contiguous area in MRAM in sequence.\n * For example, if the MRAM contains an array of N structures, a sequential\n * reader on this array will automatically fetch the data into WRAM, thus\n * simplify the iterative loop on the elements.\n *\n * The size of cached area is defined by default but can be overriden by\n * defining this value in SEQREAD_CACHE_SIZE.\n *\n * The use of a sequential reader implies:\n *\n *  - first, to allocate some storage in WRAM to cache the items, using seqread_alloc.\n *  - then to initialize a reader on the MRAM area, via seqread_init\n *  - finally to iterate on the elements, invoking seqread_get whenever a new item is accessed.\n *\n */\n\n#include <stdint.h>\n#include <mram.h>\n#include <macro_utils.h>\n\n#ifndef SEQREAD_CACHE_SIZE\n/**\n * @def SEQREAD_CACHE_SIZE\n * @hideinitializer\n * @brief Size of caches used by seqread.\n */\n#define SEQREAD_CACHE_SIZE 256\n#endif\n\n_Static_assert(SEQREAD_CACHE_SIZE == 32 || SEQREAD_CACHE_SIZE == 64 || SEQREAD_CACHE_SIZE == 128 || SEQREAD_CACHE_SIZE == 256\n        || SEQREAD_CACHE_SIZE == 512 || SEQREAD_CACHE_SIZE == 1024,\n    \"seqread error: invalid cache size defined\");\n\n#define __SEQREAD_FCT(suffix) __CONCAT(__CONCAT(seqread, SEQREAD_CACHE_SIZE), suffix)\n#define __SEQREAD_ALLOC __SEQREAD_FCT(_alloc)\n#define __SEQREAD_INIT __SEQREAD_FCT(_init)\n#define __SEQREAD_GET __SEQREAD_FCT(_get)\n#define __SEQREAD_TELL __SEQREAD_FCT(_tell)\n#define __SEQREAD_SEEK __SEQREAD_FCT(_seek)\n\n/**\n * @typedef seqreader_buffer_t\n * @brief An buffer to use to initial a sequential reader.\n */\ntypedef uintptr_t seqreader_buffer_t;\n\n/**\n * @typedef seqreader_t\n * @brief An object used to perform sequential reading of MRAM.\n */\ntypedef struct {\n    seqreader_buffer_t wram_cache;\n    uintptr_t mram_addr;\n} seqreader_t;\n\nseqreader_buffer_t\n__SEQREAD_ALLOC();\n\n/**\n * @fn seqread_alloc\n * @brief Initializes an area in WRAM to cache the read buffers.\n *\n * Notice that this buffer can be re-used for different sequential reads,\n * as long as it is initialized each time to a new buffer in MRAM.\n *\n * @return A pointer to the allocated cache base address.\n */\n#define seqread_alloc __SEQREAD_ALLOC\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_init\n * @brief Creates a sequential reader.\n *\n * The reader is associated to an existing cache in WRAM, created with\n * seqread_alloc and a contiguous area of data in MRAM. The function\n * loads the first pages of data into the cache and provides a pointer\n * to the first byte in cache actually mapping the expected data.\n *\n * Notice that the provided MRAM address does not need to be aligned on\n * any constraint: the routine does the alignment automatically.\n *\n * @param cache the reader's cache in WRAM\n * @param mram_addr the buffer address in MRAM\n * @param reader the sequential reader to init to the supplied MRAM address\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_init __SEQREAD_INIT\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader);\n\n/**\n * @fn seqread_get\n * @brief Fetches the next item in a sequence.\n *\n * This operation basically consists in incrementing the pointer that goes\n * through the mapped area of memory. The function automatically reloads\n * data from cache if necessary.\n *\n * As a result, the provided pointer to the cache area is set to its new value.\n *\n * The provided increment must be less than SEQREAD_CACHE_SIZE. The reader's\n * behavior is undefined if the increment exceeds this value.\n *\n * @param ptr the incremented pointer\n * @param inc the number of bytes added to this pointer\n * @param reader a pointer to the sequential reader\n * @return The updated pointer value.\n */\n#define seqread_get __SEQREAD_GET\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_seek\n * @brief Set the position of the cache to the supplied MRAM address\n *\n * Update automatically the cache if necessary.\n *\n * @param mram_addr the new buffer address in MRAM\n * @param reader a pointer to the sequential reader\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_seek __SEQREAD_SEEK\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader);\n\n/**\n * @fn seqread_tell\n * @brief Get the MRAM address corresponding to the supplied ptr in the cache\n *\n * @param ptr a pointer in the cache\n * @param reader a pointer to the sequential reader\n * @return A ptr to the MRAM address corresponding to the supplied pointer in the cache\n */\n#define seqread_tell __SEQREAD_TELL\n\n#endif /* DPUSYSCORE_SEQREAD_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread.inc",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <seqread.h>\n#include <mram.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <stddef.h>\n\n#define PAGE_SIZE (SEQREAD_CACHE_SIZE)\n#define PAGE_ALLOC_SIZE (2 * PAGE_SIZE)\n#define PAGE_OFF_MASK (PAGE_SIZE - 1)\n#define PAGE_IDX_MASK (~PAGE_OFF_MASK)\n\n#define MRAM_READ_PAGE(from, to) mram_read((__mram_ptr void *)(from), (void *)(to), PAGE_ALLOC_SIZE)\n\nextern void *\nmem_alloc_nolock(size_t size);\nATOMIC_BIT_EXTERN(__heap_pointer);\n\nseqreader_buffer_t\n__SEQREAD_ALLOC(void)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    unsigned int heap_pointer = __HEAP_POINTER;\n    seqreader_buffer_t pointer = (seqreader_buffer_t)((heap_pointer + PAGE_OFF_MASK) & PAGE_IDX_MASK);\n    size_t size = pointer + PAGE_ALLOC_SIZE - heap_pointer;\n    /* We already compute the return pointer\n     * mem_alloc_nolock is only used to really reserve the memory area in the heap */\n    mem_alloc_nolock(size);\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return pointer;\n}\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    reader->wram_cache = cache;\n    reader->mram_addr = (uintptr_t)(1 << __DPU_MRAM_SIZE_LOG2);\n\n    return __SEQREAD_SEEK(mram_addr, reader);\n}\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader)\n{\n    return (void *)__builtin_dpu_seqread_get((uintptr_t)ptr, inc, reader, PAGE_SIZE);\n}\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    uintptr_t target_addr = (uintptr_t)mram_addr;\n    uintptr_t current_addr = (uintptr_t)reader->mram_addr;\n    uintptr_t wram_cache = (uintptr_t)reader->wram_cache;\n    uintptr_t mram_offset = target_addr - current_addr;\n    if ((mram_offset & PAGE_IDX_MASK) != 0) {\n        uintptr_t target_addr_idx_page = target_addr & PAGE_IDX_MASK;\n        MRAM_READ_PAGE(target_addr_idx_page, wram_cache);\n        mram_offset = target_addr & PAGE_OFF_MASK;\n        reader->mram_addr = target_addr_idx_page;\n    }\n    return (void *)(mram_offset + wram_cache);\n}\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader)\n{\n    return (__mram_ptr void *)((uintptr_t)reader->mram_addr + ((uintptr_t)ptr & PAGE_OFF_MASK));\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread1024.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 1024\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread128.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 128\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread256.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 256\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 32\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread512.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 512\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/seqread64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 64\n#include <seqread.inc>\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/soft_cache.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <attributes.h>\n\nunsigned long __sw_cache_buffer[NR_THREADS] __dma_aligned __used;\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/soft_cache.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SOFT_CACHE_H\n#define DPUSYSCORE_SOFT_CACHE_H\n\n/**\n * @file soft_cache.h\n * @brief Software cache\n *\n * The software cache mechanism emulates a hardware cache to transparently load and store data from and to the\n * MRAM.\n *\n * This mechanism is quite slow, thus would only be used during the development process, to simplify the code.\n *\n * This module defines:\n *\n *  - A procedure to start the software cache, by creating a \"virtual TLB\" in the system, along with an area in WRAM to contain\n *    the cached MRAM pages\n *  - A procedure to flush the cache at the end of an execution, ensuring that the data in MRAM are consistent with the cached\n *    data\n *  - The special C directive \"__mram\", used to declare a pointer directly representing a buffer in MRAM.\n *\n * An MRAM pointer is mapped by the caching system. As a consequence, any access to data within this buffer is trapped\n * by a cache load or store procedure, transparently performing the required memory transactions to fetch and write back\n * the data.\n *\n */\n\n#include <attributes.h>\n\n#endif /* DPUSYSCORE_SOFT_CACHE_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/subdf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subdf3(fp_t a, fp_t b)\n{\n    return __adddf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dsub(fp_t a, fp_t b)\n{\n    return __subdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/subsf3.c",
    "content": "//===-- lib/subsf3.c - Single-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subsf3(fp_t a, fp_t b)\n{\n    return __addsf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fsub(fp_t a, fp_t b)\n{\n    return __subsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/subvdi3.c",
    "content": "/* ===-- subvdi3.c - Implement __subvdi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI di_int\n__subvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a - (du_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/subvsi3.c",
    "content": "/* ===-- subvsi3.c - Implement __subvsi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI si_int\n__subvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a - (su_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/sysdef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SYSDEF_H\n#define DPUSYSCORE_SYSDEF_H\n\n/**\n * @file sysdef.h\n * @brief Provides useful system abstractions.\n */\n\n/**\n * @typedef thread_id_t\n * @brief A unique runtime number.\n */\ntypedef unsigned int thread_id_t;\n\n/**\n * @typedef sysname_t\n * @brief A system name.\n *\n * Used to name system structures, like mutexes, semaphores, meetpoints, etc... In practice, system names\n * are integers, representing a unique identifier for the given type of structure.\n */\ntypedef unsigned int sysname_t;\n\n#endif /* DPUSYSCORE_SYSDEF_H */\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/truncdfhf2.c",
    "content": "//===-- lib/truncdfhf2.c - double -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI uint16_t\n__truncdfhf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_d2h(double a)\n{\n    return __truncdfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/truncdfsf2.c",
    "content": "//===-- lib/truncdfsf2.c - double -> single conversion ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_SINGLE\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI float\n__truncdfsf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_d2f(double a)\n{\n    return __truncdfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/truncsfhf2.c",
    "content": "//===-- lib/truncsfhf2.c - single -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_SINGLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE uint16_t\n__truncsfhf2(float a)\n{\n    return __truncXfYf2__(a);\n}\n\nCOMPILER_RT_ABI uint16_t\n__gnu_f2h_ieee(float a)\n{\n    return __truncsfhf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_f2h(float a)\n{\n    return __truncsfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/ucmpdi2.c",
    "content": "/* ===-- ucmpdi2.c - Implement __ucmpdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ucmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns:  if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__ucmpdi2(du_int a, du_int b)\n{\n    udwords x;\n    x.all = a;\n    udwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_ulcmp(di_int a, di_int b)\n{\n    return __ucmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/udiv64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication unsigned division.\n */\n#include <stdint.h>\n#include <dpuruntime.h>\n\nstatic unsigned int\n__clz__(uint64_t x)\n{\n    return __builtin_clzl(x);\n}\n\nuint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder)\n{\n    uint64_t dxo = dividend, dxe = 0;\n\n    if (divider == 0)\n        goto division_by_zero;\n    if (divider > dividend) {\n        if (ask_remainder == 0)\n            return 0;\n        else\n            return dividend;\n    }\n\n    // Mimic the div_step.\n    /// div_step functionality:\n    //   if (Dxo >= (Ra<< #u5)) {\n    //     Dxo = Dxo - (Ra<< #u5);\n    //     Dxe = (Dxe << 1) | 1;\n    //   } else {\n    //     Dxe =  Dxe << 1;\n    //   }\n    int dividerl0 = __clz__(divider), dividendl0 = __clz__(dividend);\n\n    int i = dividerl0 - dividendl0;\n\n    for (; i >= 0; i--) {\n        uint64_t pivot = ((uint64_t)divider << i);\n        if (dxo >= pivot) {\n            dxo = dxo - pivot;\n            dxe = ((uint64_t)dxe << 1) | 1L;\n        } else {\n            dxe = (uint64_t)dxe << 1;\n        }\n    }\n    if (ask_remainder == 1)\n        return dxo;\n    else\n        return dxe;\n\ndivision_by_zero:\n    __asm__ volatile(\"fault \" __STR(__FAULT_DIVISION_BY_ZERO__));\n    unreachable();\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/udivdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__udivdi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 0);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/udivmodsi4.c",
    "content": "/*===-- udivmodsi4.c - Implement __udivmodsi4 ------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem)\n{\n    unsigned long res = __udiv32(a, b);\n    *rem = (unsigned int)res;\n    return (unsigned int)(res >> 32);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/udivsi3.c",
    "content": "/* ===-- udivsi3.c - Implement __udivsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\n/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */\n\n/* This function should not call __divsi3! */\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d)\n{\n    const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT;\n    su_int q;\n    su_int r;\n    unsigned sr;\n    /* special cases */\n    if (d == 0)\n        return 0; /* ?! */\n    if (n == 0)\n        return 0;\n    sr = __builtin_clz(d) - __builtin_clz(n);\n    /* 0 <= sr <= n_uword_bits - 1 or sr large */\n    if (sr > n_uword_bits - 1) /* d > r */\n        return 0;\n    if (sr == n_uword_bits - 1) /* d == 1 */\n        return n;\n    ++sr;\n    /* 1 <= sr <= n_uword_bits - 1 */\n    /* Not a special case */\n    q = n << (n_uword_bits - sr);\n    r = n >> sr;\n    su_int carry = 0;\n    for (; sr > 0; --sr) {\n        /* r:q = ((r:q)  << 1) | carry */\n        r = (r << 1) | (q >> (n_uword_bits - 1));\n        q = (q << 1) | carry;\n        /* carry = 0;\n         * if (r.all >= d.all)\n         * {\n         *      r.all -= d.all;\n         *      carry = 1;\n         * }\n         */\n        const si_int s = (si_int)(d - r - 1) >> (n_uword_bits - 1);\n        carry = s & 1;\n        r -= d & s;\n    }\n    q = (q << 1) | carry;\n    return q;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_uidiv(su_int n, su_int d)\n{\n    return __udivsi3(n, d);\n}\n#endif\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/umoddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned remainder.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__umoddi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 1);\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/umodsi3.c",
    "content": "/* ===-- umodsi3.c - Implement __umodsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __umodsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__umodsi3(su_int a, su_int b)\n{\n    unsigned long res = __udiv32(a, b);\n    return (unsigned int)res;\n}\n"
  },
  {
    "path": "golang/uPIMulator/sdk/syslib/waitqueue.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nunsigned char __attribute__((used)) __sys_wq_table[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };"
  },
  {
    "path": "golang/uPIMulator/src/abi/encoding/ascii_encoder.go",
    "content": "package encoding\n\ntype AsciiEncoder struct {\n\ttable          map[string]uint8\n\tinverted_table map[uint8]string\n\tunknown        string\n}\n\nfunc (this *AsciiEncoder) Init() {\n\tthis.table = make(map[string]uint8, 0)\n\tthis.inverted_table = make(map[uint8]string, 0)\n\n\tthis.table[\"\\t\"] = 9\n\tthis.table[\" \"] = 32\n\tthis.table[\"!\"] = 33\n\tthis.table[\"\\\"\"] = 34\n\tthis.table[\"#\"] = 35\n\tthis.table[\"$\"] = 36\n\tthis.table[\"%\"] = 37\n\tthis.table[\"&\"] = 38\n\tthis.table[\"'\"] = 39\n\tthis.table[\"(\"] = 40\n\tthis.table[\")\"] = 41\n\tthis.table[\"*\"] = 42\n\tthis.table[\"+\"] = 43\n\tthis.table[\",\"] = 44\n\tthis.table[\"-\"] = 45\n\tthis.table[\".\"] = 46\n\tthis.table[\"/\"] = 47\n\tthis.table[\"0\"] = 48\n\tthis.table[\"1\"] = 49\n\tthis.table[\"2\"] = 50\n\tthis.table[\"3\"] = 51\n\tthis.table[\"4\"] = 52\n\tthis.table[\"5\"] = 53\n\tthis.table[\"6\"] = 54\n\tthis.table[\"7\"] = 55\n\tthis.table[\"8\"] = 56\n\tthis.table[\"9\"] = 57\n\tthis.table[\":\"] = 58\n\tthis.table[\"\"] = 59\n\tthis.table[\"<\"] = 60\n\tthis.table[\"=\"] = 61\n\tthis.table[\">\"] = 62\n\tthis.table[\"?\"] = 63\n\tthis.table[\"@\"] = 64\n\tthis.table[\"A\"] = 65\n\tthis.table[\"B\"] = 66\n\tthis.table[\"C\"] = 67\n\tthis.table[\"D\"] = 68\n\tthis.table[\"E\"] = 69\n\tthis.table[\"F\"] = 70\n\tthis.table[\"G\"] = 71\n\tthis.table[\"H\"] = 72\n\tthis.table[\"I\"] = 73\n\tthis.table[\"J\"] = 74\n\tthis.table[\"K\"] = 75\n\tthis.table[\"L\"] = 76\n\tthis.table[\"M\"] = 77\n\tthis.table[\"N\"] = 78\n\tthis.table[\"O\"] = 79\n\tthis.table[\"P\"] = 80\n\tthis.table[\"Q\"] = 81\n\tthis.table[\"R\"] = 82\n\tthis.table[\"S\"] = 83\n\tthis.table[\"T\"] = 84\n\tthis.table[\"U\"] = 85\n\tthis.table[\"V\"] = 86\n\tthis.table[\"W\"] = 87\n\tthis.table[\"X\"] = 88\n\tthis.table[\"Y\"] = 89\n\tthis.table[\"Z\"] = 90\n\tthis.table[\"[\"] = 91\n\tthis.table[\"\\\\\"] = 92\n\tthis.table[\"]\"] = 93\n\tthis.table[\"^\"] = 94\n\tthis.table[\"_\"] = 95\n\tthis.table[\"`\"] = 96\n\tthis.table[\"a\"] = 97\n\tthis.table[\"b\"] = 98\n\tthis.table[\"c\"] = 99\n\tthis.table[\"d\"] = 100\n\tthis.table[\"e\"] = 101\n\tthis.table[\"f\"] = 102\n\tthis.table[\"g\"] = 103\n\tthis.table[\"h\"] = 104\n\tthis.table[\"i\"] = 105\n\tthis.table[\"j\"] = 106\n\tthis.table[\"k\"] = 107\n\tthis.table[\"l\"] = 108\n\tthis.table[\"m\"] = 109\n\tthis.table[\"n\"] = 110\n\tthis.table[\"o\"] = 111\n\tthis.table[\"p\"] = 112\n\tthis.table[\"q\"] = 113\n\tthis.table[\"r\"] = 114\n\tthis.table[\"s\"] = 115\n\tthis.table[\"t\"] = 116\n\tthis.table[\"u\"] = 117\n\tthis.table[\"v\"] = 118\n\tthis.table[\"w\"] = 119\n\tthis.table[\"x\"] = 120\n\tthis.table[\"y\"] = 121\n\tthis.table[\"z\"] = 122\n\tthis.table[\"{\"] = 123\n\tthis.table[\"|\"] = 124\n\tthis.table[\"}\"] = 125\n\tthis.table[\"~\"] = 126\n\tthis.table[\"Ç\"] = 128\n\tthis.table[\"ü\"] = 129\n\tthis.table[\"é\"] = 130\n\tthis.table[\"â\"] = 131\n\tthis.table[\"ä\"] = 132\n\tthis.table[\"à\"] = 133\n\tthis.table[\"å\"] = 134\n\tthis.table[\"ç\"] = 135\n\tthis.table[\"ê\"] = 136\n\tthis.table[\"ë\"] = 137\n\tthis.table[\"è\"] = 138\n\tthis.table[\"ï\"] = 139\n\tthis.table[\"î\"] = 140\n\tthis.table[\"ì\"] = 141\n\tthis.table[\"Ä\"] = 142\n\tthis.table[\"Å\"] = 143\n\tthis.table[\"É\"] = 144\n\tthis.table[\"æ\"] = 145\n\tthis.table[\"Æ\"] = 146\n\tthis.table[\"ô\"] = 147\n\tthis.table[\"ö\"] = 148\n\tthis.table[\"ò\"] = 149\n\tthis.table[\"û\"] = 150\n\tthis.table[\"ù\"] = 151\n\tthis.table[\"ÿ\"] = 152\n\tthis.table[\"Ö\"] = 153\n\tthis.table[\"Ü\"] = 154\n\tthis.table[\"ø\"] = 155\n\tthis.table[\"£\"] = 156\n\tthis.table[\"Ø\"] = 157\n\tthis.table[\"×\"] = 158\n\tthis.table[\"ƒ\"] = 159\n\tthis.table[\"á\"] = 160\n\tthis.table[\"í\"] = 161\n\tthis.table[\"ó\"] = 162\n\tthis.table[\"ú\"] = 163\n\tthis.table[\"ñ\"] = 164\n\tthis.table[\"Ñ\"] = 165\n\tthis.table[\"ª\"] = 166\n\tthis.table[\"º\"] = 167\n\tthis.table[\"¿\"] = 168\n\tthis.table[\"®\"] = 169\n\tthis.table[\"¬\"] = 170\n\tthis.table[\"½\"] = 171\n\tthis.table[\"¼\"] = 172\n\tthis.table[\"¡\"] = 173\n\tthis.table[\"«\"] = 174\n\tthis.table[\"»\"] = 175\n\tthis.table[\"░\"] = 176\n\tthis.table[\"▒\"] = 177\n\tthis.table[\"▓\"] = 178\n\tthis.table[\"│\"] = 179\n\tthis.table[\"┤\"] = 180\n\tthis.table[\"Á\"] = 181\n\tthis.table[\"Â\"] = 182\n\tthis.table[\"À\"] = 183\n\tthis.table[\"©\"] = 184\n\tthis.table[\"╣\"] = 185\n\tthis.table[\"║\"] = 186\n\tthis.table[\"╗\"] = 187\n\tthis.table[\"╝\"] = 188\n\tthis.table[\"¢\"] = 189\n\tthis.table[\"¥\"] = 190\n\tthis.table[\"┐\"] = 191\n\tthis.table[\"└\"] = 192\n\tthis.table[\"┴\"] = 193\n\tthis.table[\"┬\"] = 194\n\tthis.table[\"├\"] = 195\n\tthis.table[\"─\"] = 196\n\tthis.table[\"┼\"] = 197\n\tthis.table[\"ã\"] = 198\n\tthis.table[\"Ã\"] = 199\n\tthis.table[\"╚\"] = 200\n\tthis.table[\"╔\"] = 201\n\tthis.table[\"╩\"] = 202\n\tthis.table[\"╦\"] = 203\n\tthis.table[\"╠\"] = 204\n\tthis.table[\"═\"] = 205\n\tthis.table[\"╬\"] = 206\n\tthis.table[\"¤\"] = 207\n\tthis.table[\"ð\"] = 208\n\tthis.table[\"Ð\"] = 209\n\tthis.table[\"Ê\"] = 210\n\tthis.table[\"Ë\"] = 211\n\tthis.table[\"È\"] = 212\n\tthis.table[\"ı\"] = 213\n\tthis.table[\"Í\"] = 214\n\tthis.table[\"Î\"] = 215\n\tthis.table[\"Ï\"] = 216\n\tthis.table[\"┘\"] = 217\n\tthis.table[\"┌\"] = 218\n\tthis.table[\"█\"] = 219\n\tthis.table[\"▄\"] = 220\n\tthis.table[\"¦\"] = 221\n\tthis.table[\"Ì\"] = 222\n\tthis.table[\"▀\"] = 223\n\tthis.table[\"Ó\"] = 224\n\tthis.table[\"ß\"] = 225\n\tthis.table[\"Ô\"] = 226\n\tthis.table[\"Ò\"] = 227\n\tthis.table[\"õ\"] = 228\n\tthis.table[\"Õ\"] = 229\n\tthis.table[\"µ\"] = 230\n\tthis.table[\"þ\"] = 231\n\tthis.table[\"Þ\"] = 232\n\tthis.table[\"Ú\"] = 233\n\tthis.table[\"Û\"] = 234\n\tthis.table[\"Ù\"] = 235\n\tthis.table[\"ý\"] = 236\n\tthis.table[\"Ý\"] = 237\n\tthis.table[\"¯\"] = 238\n\tthis.table[\"´\"] = 239\n\tthis.table[\"≡\"] = 240\n\tthis.table[\"±\"] = 241\n\tthis.table[\"‗\"] = 242\n\tthis.table[\"¾\"] = 243\n\tthis.table[\"¶\"] = 244\n\tthis.table[\"§\"] = 245\n\tthis.table[\"÷\"] = 246\n\tthis.table[\"¸\"] = 247\n\tthis.table[\"°\"] = 248\n\tthis.table[\"¨\"] = 249\n\tthis.table[\"·\"] = 250\n\tthis.table[\"¹\"] = 251\n\tthis.table[\"³\"] = 252\n\tthis.table[\"²\"] = 253\n\tthis.table[\"■\"] = 254\n\n\tfor character, value := range this.table {\n\t\tthis.inverted_table[value] = character\n\t}\n\n\tthis.unknown = \"■\"\n}\n\nfunc (this *AsciiEncoder) Encode(characters string) *ByteStream {\n\tbyte_stream := new(ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, character := range characters {\n\t\tvalue := this.table[string(character)]\n\t\tbyte_stream.Append(value)\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *AsciiEncoder) Decode(byte_stream *ByteStream) string {\n\tcharacters := \"\"\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tcharacters += this.inverted_table[value]\n\t}\n\n\treturn characters\n}\n\nfunc (this *AsciiEncoder) Unknown() string {\n\treturn this.unknown\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/abi/encoding/byte_stream.go",
    "content": "package encoding\n\ntype ByteStream struct {\n\tbytes []uint8\n}\n\nfunc (this *ByteStream) Init() {\n\tthis.bytes = make([]uint8, 0)\n}\n\nfunc (this *ByteStream) Size() int64 {\n\treturn int64(len(this.bytes))\n}\n\nfunc (this *ByteStream) Get(pos int) uint8 {\n\treturn this.bytes[pos]\n}\n\nfunc (this *ByteStream) Set(pos int, value uint8) {\n\tthis.bytes[pos] = value\n}\n\nfunc (this *ByteStream) Append(value uint8) {\n\tthis.bytes = append(this.bytes, value)\n}\n\nfunc (this *ByteStream) Merge(byte_stream *ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tthis.Append(value)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/abi/word/intermediate.go",
    "content": "package word\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype Immediate struct {\n\trepresentation Representation\n\tvalue          int64\n\tword           *Word\n}\n\nfunc (this *Immediate) Init(representation Representation, width int, value int64) {\n\tthis.representation = representation\n\tthis.value = value\n\n\tthis.word = new(Word)\n\tthis.word.Init(width)\n\tthis.word.SetValue(value)\n}\n\nfunc (this *Immediate) Representation() Representation {\n\treturn this.representation\n}\n\nfunc (this *Immediate) Width() int {\n\treturn this.word.Width()\n}\n\nfunc (this *Immediate) Bit(pos int) bool {\n\treturn this.word.Bit(pos)\n}\n\nfunc (this *Immediate) BitSlice(begin int, end int) int64 {\n\treturn this.word.BitSlice(this.representation, begin, end)\n}\n\nfunc (this *Immediate) Value() int64 {\n\treturn this.value\n}\n\nfunc (this *Immediate) ToByteStream() *encoding.ByteStream {\n\treturn this.word.ToByteStream()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/abi/word/word.go",
    "content": "package word\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype Representation int\n\nconst (\n\tUNSIGNED Representation = iota\n\tSIGNED\n)\n\ntype Word struct {\n\tbits []bool\n}\n\nfunc (this *Word) Init(width int) {\n\tif width <= 0 {\n\t\terr := errors.New(\"width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.bits = make([]bool, width)\n}\n\nfunc (this *Word) Width() int {\n\treturn len(this.bits)\n}\n\nfunc (this *Word) Size() int {\n\tif this.Width()%8 != 0 {\n\t\terr := errors.New(\"width is not a multiple of 8\")\n\t\tpanic(err)\n\t}\n\n\treturn this.Width() / 8\n}\n\nfunc (this *Word) SignBit() bool {\n\treturn this.bits[this.Width()-1]\n}\n\nfunc (this *Word) Bit(pos int) bool {\n\treturn this.bits[pos]\n}\n\nfunc (this *Word) SetBit(pos int) {\n\tthis.bits[pos] = true\n}\n\nfunc (this *Word) ClearBit(pos int) {\n\tthis.bits[pos] = false\n}\n\nfunc (this *Word) BitSlice(representation Representation, begin int, end int) int64 {\n\tthis.VerifySlice(begin, end)\n\n\tslice_width := end - begin\n\tvalue := int64(0)\n\tfor i := 0; i < slice_width; i++ {\n\t\tif this.Bit(begin + i) {\n\t\t\tif representation == SIGNED && i == slice_width-1 {\n\t\t\t\tvalue -= this.Pow2(i)\n\t\t\t} else {\n\t\t\t\tvalue += this.Pow2(i)\n\t\t\t}\n\t\t}\n\t}\n\treturn value\n}\n\nfunc (this *Word) SetBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value >= 0 {\n\t\tthis.SetPositiveBitSlice(begin, end, value)\n\t} else {\n\t\tthis.SetNegativeBitSlice(begin, end, value)\n\t}\n}\n\nfunc (this *Word) Value(representation Representation) int64 {\n\treturn this.BitSlice(representation, 0, this.Width())\n}\n\nfunc (this *Word) SetValue(value int64) {\n\tthis.SetBitSlice(0, this.Width(), value)\n}\n\nfunc (this *Word) ToByteStream() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := 0; i < this.Size(); i++ {\n\t\tbegin := 8 * i\n\t\tend := begin + 8\n\n\t\tvalue := uint8(this.BitSlice(UNSIGNED, begin, end))\n\t\tbyte_stream.Append(value)\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Word) FromByteStream(byte_stream *encoding.ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tbegin := int(8 * i)\n\t\tend := int(begin + 8)\n\n\t\tvalue := int64(byte_stream.Get(int(i)))\n\t\tthis.SetBitSlice(begin, end, value)\n\t}\n}\n\nfunc (this *Word) VerifySlice(begin int, end int) {\n\tif begin < 0 {\n\t\terr := errors.New(\"begin < 0\")\n\t\tpanic(err)\n\t}\n\n\tif begin >= end {\n\t\terr := errors.New(\"begin >= end\")\n\t\tpanic(err)\n\t}\n\n\tif end > this.Width() {\n\t\terr := errors.New(\"end > width\")\n\t\tpanic(err)\n\t}\n\n\tif end-begin > 64 {\n\t\terr := errors.New(\"end - begin >= 64\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Word) Pow2(exponent int) int64 {\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n\nfunc (this *Word) SetPositiveBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value < 0 {\n\t\terr := errors.New(\"value < 0\")\n\t\tpanic(err)\n\t}\n\n\tslice_width := end - begin\n\tfor i := 0; i < slice_width; i++ {\n\t\tif value%2 == 1 {\n\t\t\tthis.SetBit(begin + i)\n\t\t} else {\n\t\t\tthis.ClearBit(begin + i)\n\t\t}\n\n\t\tvalue /= 2\n\t}\n\n\tif value != 0 {\n\t\terr := errors.New(\"value != 0\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Word) SetNegativeBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value >= 0 {\n\t\terr := errors.New(\"value >= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.SetBit(end - 1)\n\n\tif begin+1 < end {\n\t\tslice_width := end - begin\n\t\tvalue += this.Pow2(slice_width - 1)\n\t\tthis.SetPositiveBitSlice(begin, end-1, value)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/assemblable.go",
    "content": "package assembler\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Assemblable interface {\n\tInit(command_line_parser *misc.CommandLineParser)\n\n\tInputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream\n\tOutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream\n\n\tInputDpuMramHeapPointerName(execution int, dpu_id int) (int64, *encoding.ByteStream)\n\tOutputDpuMramHeapPointerName(execution int, dpu_id int) (int64, *encoding.ByteStream)\n\n\tNumExecutions() int\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/assembler.go",
    "content": "package assembler\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/assembler/prim\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Assembler struct {\n\tbin_dirpath string\n\n\tbenchmark string\n\n\tnum_channels          int\n\tnum_ranks_per_channel int\n\tnum_dpus_per_rank     int\n\tnum_dpus              int\n\n\tnum_tasklets int\n\n\tassemblables map[string]Assemblable\n}\n\nfunc (this *Assembler) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tthis.num_channels = int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.num_ranks_per_channel = int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tthis.num_dpus_per_rank = int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_dpus = this.num_channels * this.num_ranks_per_channel * this.num_dpus_per_rank\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.assemblables = make(map[string]Assemblable, 0)\n\n\tthis.assemblables[\"BS\"] = new(prim.Bs)\n\tthis.assemblables[\"GEMV\"] = new(prim.Gemv)\n\tthis.assemblables[\"HST-L\"] = new(prim.HstL)\n\tthis.assemblables[\"HST-S\"] = new(prim.HstS)\n\tthis.assemblables[\"MLP\"] = new(prim.Mlp)\n\tthis.assemblables[\"RED\"] = new(prim.Red)\n\tthis.assemblables[\"SCAN-RSS\"] = new(prim.ScanRss)\n\tthis.assemblables[\"SCAN-SSA\"] = new(prim.ScanSsa)\n\tthis.assemblables[\"SEL\"] = new(prim.Sel)\n\tthis.assemblables[\"TRNS\"] = new(prim.Trns)\n\tthis.assemblables[\"TS\"] = new(prim.Ts)\n\tthis.assemblables[\"UNI\"] = new(prim.Uni)\n\tthis.assemblables[\"VA\"] = new(prim.Va)\n\n\tif assemblable, found := this.assemblables[this.benchmark]; found {\n\t\tassemblable.Init(command_line_parser)\n\t} else {\n\t\terr := errors.New(\"assemblable is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Assembler) Assemble() {\n\tthis.AssembleInputDpuHost()\n\tthis.AssembleOutputDpuHost()\n\tthis.AssembleInputDpuMramHeapPointerName()\n\tthis.AssembleOutputDpuMramHeapPointerName()\n\tthis.AssembleNumExecutions()\n}\n\nfunc (this *Assembler) AssembleInputDpuHost() {\n\tassemblable := this.assemblables[this.benchmark]\n\n\tfor execution := 0; execution < assemblable.NumExecutions(); execution++ {\n\t\tfor dpu_id := 0; dpu_id < this.num_dpus; dpu_id++ {\n\t\t\tinput_dpu_host := assemblable.InputDpuHost(execution, dpu_id)\n\n\t\t\tfor name, byte_stream := range input_dpu_host {\n\t\t\t\tfilename := fmt.Sprintf(\"input_%s_%d_%d.bin\", name, execution, dpu_id)\n\t\t\t\tfilepath_ := filepath.Join(this.bin_dirpath, filename)\n\n\t\t\t\tfile_dumper := new(misc.FileDumper)\n\t\t\t\tfile_dumper.Init(filepath_)\n\n\t\t\t\tlines := make([]string, 0)\n\t\t\t\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\t\t\t\tline := fmt.Sprintf(\"%d\", byte_stream.Get(int(i)))\n\n\t\t\t\t\tlines = append(lines, line)\n\t\t\t\t}\n\n\t\t\t\tfile_dumper.WriteLines(lines)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Assembler) AssembleOutputDpuHost() {\n\tassemblable := this.assemblables[this.benchmark]\n\n\tfor execution := 0; execution < assemblable.NumExecutions(); execution++ {\n\t\tfor dpu_id := 0; dpu_id < this.num_dpus; dpu_id++ {\n\t\t\toutput_dpu_host := assemblable.OutputDpuHost(execution, dpu_id)\n\n\t\t\tfor name, byte_stream := range output_dpu_host {\n\t\t\t\tfilename := fmt.Sprintf(\"output_%s_%d_%d.bin\", name, execution, dpu_id)\n\t\t\t\tfilepath_ := filepath.Join(this.bin_dirpath, filename)\n\n\t\t\t\tfile_dumper := new(misc.FileDumper)\n\t\t\t\tfile_dumper.Init(filepath_)\n\n\t\t\t\tlines := make([]string, 0)\n\t\t\t\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\t\t\t\tline := fmt.Sprintf(\"%d\", byte_stream.Get(int(i)))\n\n\t\t\t\t\tlines = append(lines, line)\n\t\t\t\t}\n\n\t\t\t\tfile_dumper.WriteLines(lines)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Assembler) AssembleInputDpuMramHeapPointerName() {\n\tassemblable := this.assemblables[this.benchmark]\n\n\tfor execution := 0; execution < assemblable.NumExecutions(); execution++ {\n\t\tfor dpu_id := 0; dpu_id < this.num_dpus; dpu_id++ {\n\t\t\toffset, byte_stream := assemblable.InputDpuMramHeapPointerName(execution, dpu_id)\n\n\t\t\tfilename := fmt.Sprintf(\n\t\t\t\t\"input_dpu_mram_heap_pointer_name_%d_%d_%d.bin\",\n\t\t\t\toffset,\n\t\t\t\texecution,\n\t\t\t\tdpu_id,\n\t\t\t)\n\t\t\tfilepath_ := filepath.Join(this.bin_dirpath, filename)\n\n\t\t\tfile_dumper := new(misc.FileDumper)\n\t\t\tfile_dumper.Init(filepath_)\n\n\t\t\tlines := make([]string, 0)\n\t\t\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\t\t\tline := fmt.Sprintf(\"%d\", byte_stream.Get(int(i)))\n\n\t\t\t\tlines = append(lines, line)\n\t\t\t}\n\n\t\t\tfile_dumper.WriteLines(lines)\n\t\t}\n\t}\n}\n\nfunc (this *Assembler) AssembleOutputDpuMramHeapPointerName() {\n\tassemblable := this.assemblables[this.benchmark]\n\n\tfor execution := 0; execution < assemblable.NumExecutions(); execution++ {\n\t\tfor dpu_id := 0; dpu_id < this.num_dpus; dpu_id++ {\n\t\t\toffset, byte_stream := assemblable.OutputDpuMramHeapPointerName(execution, dpu_id)\n\n\t\t\tfilename := fmt.Sprintf(\n\t\t\t\t\"output_dpu_mram_heap_pointer_name_%d_%d_%d.bin\",\n\t\t\t\toffset,\n\t\t\t\texecution,\n\t\t\t\tdpu_id,\n\t\t\t)\n\t\t\tfilepath_ := filepath.Join(this.bin_dirpath, filename)\n\n\t\t\tfile_dumper := new(misc.FileDumper)\n\t\t\tfile_dumper.Init(filepath_)\n\n\t\t\tlines := make([]string, 0)\n\t\t\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\t\t\tline := fmt.Sprintf(\"%d\", byte_stream.Get(int(i)))\n\n\t\t\t\tlines = append(lines, line)\n\t\t\t}\n\n\t\t\tfile_dumper.WriteLines(lines)\n\t\t}\n\t}\n}\n\nfunc (this *Assembler) AssembleNumExecutions() {\n\tassemblable := this.assemblables[this.benchmark]\n\n\tpath := filepath.Join(this.bin_dirpath, \"num_executions.txt\")\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\n\tline := fmt.Sprintf(\"%d\", assemblable.NumExecutions())\n\tlines := make([]string, 0)\n\tlines = append(lines, line)\n\n\tfile_dumper.WriteLines(lines)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/bs.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Bs struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tsize              int64\n\tinput_buffer      []int64\n\tquery_buffer      []int64\n\tresults           [][]int64\n\tslice_per_dpu     int64\n\tquery_per_tasklet int64\n\tkernel            int64\n}\n\nfunc (this *Bs) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tthis.size = int64(command_line_parser.DataPrepParams()[0])\n\tnum_queries := int64(command_line_parser.DataPrepParams()[0] / 8)\n\n\tif num_queries%int64(this.num_dpus*this.num_tasklets) != 0 {\n\t\tnum_queries += int64(this.num_dpus*this.num_tasklets) - num_queries%int64(this.num_dpus*this.num_tasklets)\n\t}\n\n\tif num_queries%int64(this.num_dpus*this.num_tasklets) != 0 {\n\t\terr := errors.New(\"num queries % (num dpus * num tasklets) != 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.size; i++ {\n\t\tthis.input_buffer = append(this.input_buffer, i+1)\n\t}\n\n\tthis.query_buffer = make([]int64, 0)\n\tfor i := int64(0); i < num_queries; i++ {\n\t\tthis.query_buffer = append(this.query_buffer, i)\n\t}\n\n\tthis.results = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.results = append(this.results, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.results[i] = append(this.results[i], 0)\n\t\t}\n\t}\n\n\tthis.slice_per_dpu = num_queries / int64(this.num_dpus)\n\tthis.query_per_tasklet = this.slice_per_dpu / int64(this.num_tasklets)\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tfor k := 0; k < int(this.query_per_tasklet); k++ {\n\t\t\t\tis_found := false\n\t\t\t\tl := int64(0)\n\t\t\t\tr := this.size - 1\n\n\t\t\t\tfor l <= r {\n\t\t\t\t\tm := l + (r-l)/2\n\n\t\t\t\t\tif this.input_buffer[m] == this.query_buffer[k+j*int(this.query_per_tasklet)+i*int(this.slice_per_dpu)] {\n\t\t\t\t\t\tthis.results[i][j] = m\n\t\t\t\t\t\tis_found = true\n\t\t\t\t\t\tbreak\n\t\t\t\t\t}\n\n\t\t\t\t\tif this.input_buffer[m] < this.query_buffer[k+j*int(this.query_per_tasklet)+i*int(this.slice_per_dpu)] {\n\t\t\t\t\t\tl = m + 1\n\t\t\t\t\t} else {\n\t\t\t\t\t\tr = m - 1\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif !is_found {\n\t\t\t\t\tthis.results[i][j] = -1\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.kernel = 0\n}\n\nfunc (this *Bs) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tsize_word := new(word.Word)\n\tsize_word.Init(64)\n\tsize_word.SetValue(this.size)\n\tdpu_input_arguments_byte_stream.Merge(size_word.ToByteStream())\n\n\tslice_per_dpu_word := new(word.Word)\n\tslice_per_dpu_word.Init(64)\n\tslice_per_dpu_word.SetValue(this.slice_per_dpu)\n\tdpu_input_arguments_byte_stream.Merge(slice_per_dpu_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernel)\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Bs) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tfor _, result := range this.results[dpu_id] {\n\t\tresult_word := new(word.Word)\n\t\tresult_word.Init(64)\n\t\tresult_word.SetValue(result)\n\t\tdpu_results_byte_stream.Merge(result_word.ToByteStream())\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Bs) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, element := range this.input_buffer {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\tstart_elem := this.slice_per_dpu * int64(dpu_id)\n\tend_elem := this.slice_per_dpu * int64(dpu_id+1)\n\n\tfor _, element := range this.query_buffer[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\treturn 0, byte_stream\n}\n\nfunc (this *Bs) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Bs) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Bs) Sum(s []int64) int64 {\n\tsum := int64(0)\n\tfor _, element := range s {\n\t\tsum += element\n\t}\n\treturn sum\n}\n\nfunc (this *Bs) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/gemv.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Gemv struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tm_size      int64\n\tn_size      int64\n\tn_size_pads []int64\n\tnr_rows     []int64\n\tmax_rows    []int64\n\tbuffer_a    [][]int64\n\tbuffer_b    []int64\n\tbuffer_c    [][]int64\n}\n\nfunc (this *Gemv) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.m_size = int64(command_line_parser.DataPrepParams()[0])\n\tthis.n_size = 64\n\n\tthis.num_executions = 1\n\n\tif this.m_size%int64(this.num_dpus) != 0 {\n\t\terr := errors.New(\"m size % num dpus != 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.n_size_pads = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif this.n_size%2 == 0 {\n\t\t\tthis.n_size_pads = append(this.n_size_pads, this.n_size)\n\t\t} else {\n\t\t\tthis.n_size_pads = append(this.n_size_pads, this.n_size+1)\n\t\t}\n\t}\n\n\tthis.nr_rows = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.nr_rows = append(this.nr_rows, this.m_size/int64(this.num_dpus))\n\t}\n\n\tthis.max_rows = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif this.nr_rows[i]%2 == 0 {\n\t\t\tthis.max_rows = append(this.max_rows, this.nr_rows[i])\n\t\t} else {\n\t\t\tthis.max_rows = append(this.max_rows, this.nr_rows[i]+1)\n\t\t}\n\t}\n\n\tthis.buffer_a = make([][]int64, 0)\n\tfor i := int64(0); i < this.m_size; i++ {\n\t\tthis.buffer_a = append(this.buffer_a, make([]int64, 0))\n\n\t\tfor j := int64(0); j < this.n_size; j++ {\n\t\t\tthis.buffer_a[i] = append(this.buffer_a[i], int64(rand.Intn(50)))\n\t\t}\n\t}\n\n\tthis.buffer_b = make([]int64, 0)\n\tfor i := int64(0); i < this.n_size; i++ {\n\t\tthis.buffer_b = append(this.buffer_b, int64(rand.Intn(50)))\n\t}\n\n\tthis.buffer_c = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([]int64, 0))\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_row := this.nr_rows[i] * int64(i)\n\t\tend_row := this.nr_rows[i] * int64(i+1)\n\n\t\tthis.buffer_c[i] = this.MatMul(this.buffer_a[start_row:end_row], this.buffer_b)\n\t}\n}\n\nfunc (this *Gemv) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tn_size_word := new(word.Word)\n\tn_size_word.Init(32)\n\tn_size_word.SetValue(this.n_size)\n\tdpu_input_arguments_byte_stream.Merge(n_size_word.ToByteStream())\n\n\tn_size_pad_word := new(word.Word)\n\tn_size_pad_word.Init(32)\n\tn_size_pad_word.SetValue(this.n_size_pads[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(n_size_pad_word.ToByteStream())\n\n\tnr_row_word := new(word.Word)\n\tnr_row_word.Init(32)\n\tnr_row_word.SetValue(this.nr_rows[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(nr_row_word.ToByteStream())\n\n\tmax_row_word := new(word.Word)\n\tmax_row_word.Init(32)\n\tmax_row_word.SetValue(this.max_rows[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(max_row_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Gemv) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *Gemv) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_row := this.nr_rows[dpu_id] * int64(dpu_id)\n\tend_row := this.nr_rows[dpu_id] * int64(dpu_id+1)\n\n\tfor _, row := range this.buffer_a[start_row:end_row] {\n\t\tfor _, element := range row {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(32)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\tfor _, element := range this.buffer_b {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Gemv) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_row := this.nr_rows[dpu_id] * int64(dpu_id)\n\tend_row := this.nr_rows[dpu_id] * int64(dpu_id+1)\n\n\toffset := int64(0)\n\tfor i := 0; i < len(this.buffer_a[start_row:end_row]); i++ {\n\t\tfor j := 0; j < len(this.buffer_a[i]); j++ {\n\t\t\toffset += 4\n\t\t}\n\t}\n\n\tfor i := 0; i < len(this.buffer_b); i++ {\n\t\toffset += 4\n\t}\n\n\tfor _, element := range this.buffer_c[dpu_id] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn offset, byte_stream\n}\n\nfunc (this *Gemv) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Gemv) MatMul(x [][]int64, y []int64) []int64 {\n\tresults := make([]int64, 0)\n\tfor i := 0; i < len(x); i++ {\n\t\tresults = append(results, 0)\n\t}\n\n\tfor i := 0; i < len(x); i++ {\n\t\tfor j := 0; j < len(y); j++ {\n\t\t\tresults[i] += x[i][j] * y[j]\n\t\t}\n\t}\n\n\treturn results\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/hst_l.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype HstL struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tnum_bins              int64\n\tinput_size_dpu_8bytes int64\n\tbuffer_a              []int64\n\tbuffer_c              [][]int64\n\tsizes                 []int64\n\tdpu_arg_sizes         []int64\n\ttransfer_size         int64\n\tkernel                int64\n}\n\nfunc (this *HstL) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\tthis.num_bins = 256\n\n\telem_size := int64(4)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tvar input_size_8bytes int64\n\tif (input_size*elem_size)%8 == 0 {\n\t\tinput_size_8bytes = input_size\n\t} else {\n\t\tinput_size_8bytes = int64(math.Ceil(float64(input_size)/float64(8)) * 8)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif (input_size_dpu*elem_size)%8 == 0 {\n\t\tthis.input_size_dpu_8bytes = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_8bytes = int64(math.Ceil(float64(input_size_dpu)/float64(8)) * 8)\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < input_size; i++ {\n\t\tthis.buffer_a = append(this.buffer_a, int64(rand.Intn(4096)))\n\t}\n\n\tdepth := int64(12)\n\n\tthis.buffer_c = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([]int64, 0))\n\n\t\tfor j := int64(0); j < this.num_bins; j++ {\n\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], 0)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_8bytes * int64(i)\n\t\tend_elem := this.input_size_dpu_8bytes * int64(i+1)\n\n\t\tfor _, elem := range this.buffer_a[start_elem:end_elem] {\n\t\t\tthis.buffer_c[i][(elem*this.num_bins)>>depth] += 1\n\t\t}\n\t}\n\n\tthis.dpu_arg_sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif i != this.num_dpus-1 {\n\t\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, this.input_size_dpu_8bytes*elem_size)\n\t\t} else {\n\t\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, (input_size_8bytes-this.input_size_dpu_8bytes*int64(this.num_dpus-1))*elem_size)\n\t\t}\n\t}\n\n\tthis.transfer_size = this.input_size_dpu_8bytes * elem_size\n\tthis.kernel = 0\n}\n\nfunc (this *HstL) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\ttransfer_size_word := new(word.Word)\n\ttransfer_size_word.Init(32)\n\ttransfer_size_word.SetValue(this.transfer_size)\n\tdpu_input_arguments_byte_stream.Merge(transfer_size_word.ToByteStream())\n\n\tnum_bins_word := new(word.Word)\n\tnum_bins_word.Init(32)\n\tnum_bins_word.SetValue(this.num_bins)\n\tdpu_input_arguments_byte_stream.Merge(num_bins_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernel)\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *HstL) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *HstL) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_8bytes * int64(dpu_id)\n\tend_elem := this.input_size_dpu_8bytes * int64(dpu_id+1)\n\n\tfor _, element := range this.buffer_a[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *HstL) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, element := range this.buffer_c[dpu_id] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn this.input_size_dpu_8bytes * 4, byte_stream\n}\n\nfunc (this *HstL) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *HstL) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/hst_s.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype HstS struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tnum_bins              int64\n\tinput_size_dpu_8bytes int64\n\tbuffer_a              []int64\n\tbuffer_c              [][]int64\n\tsizes                 []int64\n\tdpu_arg_sizes         []int64\n\ttransfer_size         int64\n\tkernel                int64\n}\n\nfunc (this *HstS) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\tthis.num_bins = 256\n\n\telem_size := int64(4)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tvar input_size_8bytes int64\n\tif (input_size*elem_size)%8 == 0 {\n\t\tinput_size_8bytes = input_size\n\t} else {\n\t\tinput_size_8bytes = int64(math.Ceil(float64(input_size)/float64(8)) * 8)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif (input_size_dpu*elem_size)%8 == 0 {\n\t\tthis.input_size_dpu_8bytes = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_8bytes = int64(math.Ceil(float64(input_size_dpu)/float64(8)) * 8)\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < input_size; i++ {\n\t\tthis.buffer_a = append(this.buffer_a, int64(rand.Intn(4096)))\n\t}\n\n\tdepth := int64(12)\n\n\tthis.buffer_c = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([]int64, 0))\n\n\t\tfor j := int64(0); j < this.num_bins; j++ {\n\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], 0)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_8bytes * int64(i)\n\t\tend_elem := this.input_size_dpu_8bytes * int64(i+1)\n\n\t\tfor _, elem := range this.buffer_a[start_elem:end_elem] {\n\t\t\tthis.buffer_c[i][(elem*this.num_bins)>>depth] += 1\n\t\t}\n\t}\n\n\tthis.dpu_arg_sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif i != this.num_dpus-1 {\n\t\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, this.input_size_dpu_8bytes*elem_size)\n\t\t} else {\n\t\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, (input_size_8bytes-this.input_size_dpu_8bytes*int64(this.num_dpus-1))*elem_size)\n\t\t}\n\t}\n\n\tthis.transfer_size = this.input_size_dpu_8bytes * elem_size\n\tthis.kernel = 0\n}\n\nfunc (this *HstS) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\ttransfer_size_word := new(word.Word)\n\ttransfer_size_word.Init(32)\n\ttransfer_size_word.SetValue(this.transfer_size)\n\tdpu_input_arguments_byte_stream.Merge(transfer_size_word.ToByteStream())\n\n\tnum_bins_word := new(word.Word)\n\tnum_bins_word.Init(32)\n\tnum_bins_word.SetValue(this.num_bins)\n\tdpu_input_arguments_byte_stream.Merge(num_bins_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernel)\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *HstS) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *HstS) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_8bytes * int64(dpu_id)\n\tend_elem := this.input_size_dpu_8bytes * int64(dpu_id+1)\n\n\tfor _, element := range this.buffer_a[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *HstS) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, element := range this.buffer_c[dpu_id] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn this.input_size_dpu_8bytes * 4, byte_stream\n}\n\nfunc (this *HstS) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *HstS) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/mlp.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Mlp struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tm_size      int64\n\tn_size      int64\n\tnum_layers  int64\n\tn_size_pads []int64\n\tnr_rows     []int64\n\tmax_rows    []int64\n\tbuffer_a    [][][]int64\n\tbuffer_b    [][]int64\n\tbuffer_c    [][][]int64\n}\n\nfunc (this *Mlp) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.m_size = int64(command_line_parser.DataPrepParams()[0])\n\tthis.n_size = int64(command_line_parser.DataPrepParams()[0])\n\n\tthis.num_layers = 3\n\n\tthis.num_executions = int(this.num_layers)\n\n\tif this.m_size%int64(this.num_dpus) != 0 {\n\t\terr := errors.New(\"m size % num dpus != 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.n_size_pads = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif this.n_size%2 == 0 {\n\t\t\tthis.n_size_pads = append(this.n_size_pads, this.n_size)\n\t\t} else {\n\t\t\tthis.n_size_pads = append(this.n_size_pads, this.n_size+1)\n\t\t}\n\t}\n\n\tthis.nr_rows = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.nr_rows = append(this.nr_rows, this.m_size/int64(this.num_dpus))\n\t}\n\n\tthis.max_rows = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tif this.nr_rows[i]%2 == 0 {\n\t\t\tthis.max_rows = append(this.max_rows, this.nr_rows[i])\n\t\t} else {\n\t\t\tthis.max_rows = append(this.max_rows, this.nr_rows[i]+1)\n\t\t}\n\t}\n\n\tthis.buffer_a = make([][][]int64, 0)\n\tfor i := int64(0); i < this.num_layers; i++ {\n\t\tthis.buffer_a = append(this.buffer_a, make([][]int64, 0))\n\n\t\tfor j := int64(0); j < this.m_size; j++ {\n\t\t\tthis.buffer_a[i] = append(this.buffer_a[i], make([]int64, 0))\n\n\t\t\tfor k := int64(0); k < this.n_size; k++ {\n\t\t\t\tif k%100 < 98 {\n\t\t\t\t\tthis.buffer_a[i][j] = append(this.buffer_a[i][j], 0)\n\t\t\t\t} else {\n\t\t\t\t\tthis.buffer_a[i][j] = append(this.buffer_a[i][j], (i+k)%2)\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.buffer_b = make([][]int64, 0)\n\tfor i := int64(0); i < this.num_layers; i++ {\n\t\tthis.buffer_b = append(this.buffer_b, make([]int64, 0))\n\n\t\tfor j := int64(0); j < this.n_size; j++ {\n\t\t\tif j%50 < 48 {\n\t\t\t\tthis.buffer_b[i] = append(this.buffer_b[i], 0)\n\t\t\t} else {\n\t\t\t\tthis.buffer_b[i] = append(this.buffer_b[i], j%2)\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.buffer_c = make([][][]int64, 0)\n\tfor i := int64(0); i < this.num_layers; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([][]int64, 0))\n\n\t\tfor j := 0; j < this.num_dpus; j++ {\n\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], make([]int64, 0))\n\t\t}\n\t}\n\n\tfor i := int64(0); i < this.num_layers; i++ {\n\t\tfor j := 0; j < this.num_dpus; j++ {\n\t\t\tstart_row := this.nr_rows[j] * int64(j)\n\t\t\tend_row := this.nr_rows[j] * int64(j+1)\n\n\t\t\tthis.buffer_c[i][j] = this.MatMul(this.buffer_a[i][start_row:end_row], this.buffer_b[i])\n\n\t\t\tfor k := 0; k < len(this.buffer_c[i][j]); k++ {\n\t\t\t\tif this.buffer_c[i][j][k] < 0 {\n\t\t\t\t\tthis.buffer_c[i][j][k] = 0\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif i < this.num_layers-1 {\n\t\t\t\tif len(this.buffer_b[i+1][start_row:end_row]) != len(this.buffer_c[i][j]) {\n\t\t\t\t\terr := errors.New(\"buffer b [i+1][start_row:end_row]'s length != buffer c [i][j]'s length\")\n\t\t\t\t\tpanic(err)\n\t\t\t\t}\n\n\t\t\t\tfor k, element := range this.buffer_c[i][j] {\n\t\t\t\t\tthis.buffer_b[i+1][k] = element\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Mlp) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tn_size_word := new(word.Word)\n\tn_size_word.Init(32)\n\tn_size_word.SetValue(this.n_size)\n\tdpu_input_arguments_byte_stream.Merge(n_size_word.ToByteStream())\n\n\tn_size_pad_word := new(word.Word)\n\tn_size_pad_word.Init(32)\n\tn_size_pad_word.SetValue(this.n_size_pads[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(n_size_pad_word.ToByteStream())\n\n\tnr_row_word := new(word.Word)\n\tnr_row_word.Init(32)\n\tnr_row_word.SetValue(this.nr_rows[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(nr_row_word.ToByteStream())\n\n\tmax_row_word := new(word.Word)\n\tmax_row_word.Init(32)\n\tmax_row_word.SetValue(this.max_rows[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(max_row_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Mlp) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *Mlp) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_row := this.nr_rows[dpu_id] * int64(dpu_id)\n\tend_row := this.nr_rows[dpu_id] * int64(dpu_id+1)\n\n\tfor _, row := range this.buffer_a[execution][start_row:end_row] {\n\t\tfor _, element := range row {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(32)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\tfor _, element := range this.buffer_b[execution] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Mlp) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_row := this.nr_rows[dpu_id] * int64(dpu_id)\n\tend_row := this.nr_rows[dpu_id] * int64(dpu_id+1)\n\n\toffset := int64(0)\n\tfor i := 0; i < len(this.buffer_a[execution][start_row:end_row]); i++ {\n\t\tfor j := 0; j < len(this.buffer_a[execution][i]); j++ {\n\t\t\toffset += 4\n\t\t}\n\t}\n\n\tfor i := 0; i < len(this.buffer_b[execution]); i++ {\n\t\toffset += 4\n\t}\n\n\tfor _, element := range this.buffer_c[execution][dpu_id] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn offset, byte_stream\n}\n\nfunc (this *Mlp) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Mlp) MatMul(x [][]int64, y []int64) []int64 {\n\tresults := make([]int64, 0)\n\tfor i := 0; i < len(x); i++ {\n\t\tresults = append(results, 0)\n\t}\n\n\tfor i := 0; i < len(x); i++ {\n\t\tfor j := 0; j < len(y); j++ {\n\t\t\tresults[i] += x[i][j] * y[j]\n\t\t}\n\t}\n\n\treturn results\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/red.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Red struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tinput_size_dpu_8bytes int64\n\tbuffer_a              []int64\n\tcounts                []int64\n\tdpu_arg_sizes         []int64\n\tkernels               []int64\n\tinput_t_counts        []int64\n\tcycles                [][]int64\n\tt_counts              [][]int64\n}\n\nfunc (this *Red) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(8)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tvar input_size_8bytes int64\n\tif (input_size*elem_size)%8 == 0 {\n\t\tinput_size_8bytes = input_size\n\t} else {\n\t\tinput_size_8bytes = int64(math.Ceil(float64(input_size)/float64(8)) * 8)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif (input_size_dpu*elem_size)%8 == 0 {\n\t\tthis.input_size_dpu_8bytes = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_8bytes = int64(math.Ceil(float64(input_size_dpu)/float64(8)) * 8)\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_8bytes*int64(this.num_dpus); i++ {\n\t\ta := int64(rand.Intn(this.Pow2(31)))\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t}\n\n\tthis.counts = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.counts = append(this.counts, 0)\n\t}\n\n\tthis.dpu_arg_sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, 0)\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_8bytes * int64(i)\n\n\t\tvar end_elem int64\n\t\tif i != this.num_dpus-1 {\n\t\t\tend_elem = this.input_size_dpu_8bytes * int64(i+1)\n\t\t} else {\n\t\t\tend_elem = input_size\n\t\t}\n\n\t\tthis.counts[i] = this.Sum(this.buffer_a[start_elem:end_elem])\n\n\t\tif i != this.num_dpus-1 {\n\t\t\tthis.dpu_arg_sizes[i] = this.input_size_dpu_8bytes * elem_size\n\t\t} else {\n\t\t\tthis.dpu_arg_sizes[i] = (input_size_8bytes - this.input_size_dpu_8bytes*int64(this.num_dpus-1)) * elem_size\n\t\t}\n\t}\n\n\tthis.kernels = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.kernels = append(this.kernels, 0)\n\t}\n\n\tthis.input_t_counts = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.input_t_counts = append(this.input_t_counts, 0)\n\t}\n\n\tthis.cycles = make([][]int64, 0)\n\tthis.t_counts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.cycles = append(this.cycles, make([]int64, 0))\n\t\tthis.t_counts = append(this.t_counts, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.cycles[i] = append(this.cycles[i], 0)\n\n\t\t\tif j == 0 {\n\t\t\t\tthis.t_counts[i] = append(this.t_counts[i], this.counts[i])\n\t\t\t} else {\n\t\t\t\tthis.t_counts[i] = append(this.t_counts[i], 0)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Red) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tinput_t_count_word := new(word.Word)\n\tinput_t_count_word.Init(32)\n\tinput_t_count_word.SetValue(this.input_t_counts[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(input_t_count_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Red) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tif len(this.cycles[dpu_id]) != len(this.t_counts[dpu_id]) {\n\t\terr := errors.New(\"cycles' length != t counts' length\")\n\t\tpanic(err)\n\t}\n\n\tfor i := 0; i < len(this.cycles[dpu_id]); i++ {\n\t\tcycle_word := new(word.Word)\n\t\tcycle_word.Init(64)\n\t\tcycle_word.SetValue(this.cycles[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(cycle_word.ToByteStream())\n\n\t\tt_count_word := new(word.Word)\n\t\tt_count_word.Init(64)\n\t\tt_count_word.SetValue(this.t_counts[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(t_count_word.ToByteStream())\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Red) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_8bytes * int64(dpu_id)\n\n\tfor i := int64(0); i < this.input_size_dpu_8bytes; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(this.buffer_a[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Red) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Red) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Red) Sum(s []int64) int64 {\n\tsum := int64(0)\n\tfor _, element := range s {\n\t\tsum += element\n\t}\n\treturn sum\n}\n\nfunc (this *Red) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/scan_rss.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype ScanRss struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tinput_size_dpu_round int64\n\tbuffer_a             []int64\n\tbuffer_c             []int64\n\tlast_result_values   []int64\n\tresult_t_counts      [][]int64\n\tdpu_arg_size         int64\n\tkernels              []int64\n\tt_counts             [][]int64\n}\n\nfunc (this *ScanRss) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 2\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(8)\n\n\tregs := int64(128)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif input_size_dpu%(int64(this.num_tasklets)*regs) == 0 {\n\t\tthis.input_size_dpu_round = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_round = int64(math.Ceil(float64(input_size_dpu)/float64(int64(this.num_tasklets)*regs))) * int64(this.num_tasklets) * regs\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar a int64\n\t\tif i < input_size {\n\t\t\ta = int64(rand.Intn(100))\n\t\t} else {\n\t\t\ta = 0\n\t\t}\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t}\n\n\tthis.buffer_c = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar c int64\n\t\tif i == 0 {\n\t\t\tc = this.buffer_a[i]\n\t\t} else {\n\t\t\tc = this.buffer_c[i-1] + this.buffer_a[i]\n\t\t}\n\n\t\tthis.buffer_c = append(this.buffer_c, c)\n\t}\n\n\tthis.last_result_values = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.last_result_values = append(this.last_result_values, 0)\n\t}\n\n\tthis.result_t_counts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.result_t_counts = append(this.result_t_counts, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.result_t_counts[i] = append(this.result_t_counts[i], 0)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_round * int64(i)\n\t\tend_elem := this.input_size_dpu_round * int64(i+1)\n\n\t\tthis.last_result_values[i] = this.Sum1D(this.buffer_a[start_elem:end_elem])\n\t\tthis.result_t_counts[i][0] = this.last_result_values[i]\n\t}\n\n\tthis.dpu_arg_size = this.input_size_dpu_round * elem_size\n\tthis.kernels = []int64{0, 1}\n\n\tthis.t_counts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.t_counts = append(this.t_counts, make([]int64, 0))\n\n\t\tfor j := 0; j < 2; j++ {\n\t\t\tif i == 0 {\n\t\t\t\tthis.t_counts[i] = []int64{\n\t\t\t\t\t0,\n\t\t\t\t\t0,\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tthis.t_counts[i] = []int64{\n\t\t\t\t\t0,\n\t\t\t\t\tthis.Sum2D(this.result_t_counts[0:i]),\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *ScanRss) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_size)\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[execution])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tt_count_word := new(word.Word)\n\tt_count_word.Init(64)\n\tt_count_word.SetValue(this.t_counts[dpu_id][execution])\n\tdpu_input_arguments_byte_stream.Merge(t_count_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *ScanRss) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tif execution == 0 {\n\t\tfor _, result_t_count := range this.result_t_counts[dpu_id] {\n\t\t\tresult_t_count_word := new(word.Word)\n\t\t\tresult_t_count_word.Init(64)\n\t\t\tresult_t_count_word.SetValue(result_t_count)\n\t\t\tdpu_results_byte_stream.Merge(result_t_count_word.ToByteStream())\n\t\t}\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *ScanRss) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution == 0 {\n\t\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\t\tend_elem := this.input_size_dpu_round * int64(dpu_id+1)\n\n\t\tfor _, element := range this.buffer_a[start_elem:end_elem] {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(64)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *ScanRss) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution == this.num_executions-1 {\n\t\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\t\tend_elem := this.input_size_dpu_round * int64(dpu_id+1)\n\n\t\tfor _, element := range this.buffer_c[start_elem:end_elem] {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(64)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\treturn int64(this.input_size_dpu_round * 8), byte_stream\n}\n\nfunc (this *ScanRss) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *ScanRss) Sum1D(s []int64) int64 {\n\tsum := int64(0)\n\tfor _, element := range s {\n\t\tsum += element\n\t}\n\treturn sum\n}\n\nfunc (this *ScanRss) Sum2D(s [][]int64) int64 {\n\tsum := int64(0)\n\tfor _, elements := range s {\n\t\tfor _, element := range elements {\n\t\t\tsum += element\n\t\t}\n\t}\n\treturn sum\n}\n\nfunc (this *ScanRss) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/scan_ssa.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype ScanSsa struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tinput_size_dpu_round int64\n\tbuffer_a             []int64\n\tbuffer_c             []int64\n\tlast_result_values   []int64\n\tresult_t_counts      [][]int64\n\tdpu_arg_size         int64\n\tkernels              []int64\n\tt_counts             [][]int64\n}\n\nfunc (this *ScanSsa) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 2\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(8)\n\n\tregs := int64(128)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif input_size_dpu%(int64(this.num_tasklets)*regs) == 0 {\n\t\tthis.input_size_dpu_round = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_round = int64(math.Ceil(float64(input_size_dpu)/float64(int64(this.num_tasklets)*regs))) * int64(this.num_tasklets) * regs\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar a int64\n\t\tif i < input_size {\n\t\t\ta = int64(rand.Intn(100))\n\t\t} else {\n\t\t\ta = 0\n\t\t}\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t}\n\n\tthis.buffer_c = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar c int64\n\t\tif i == 0 {\n\t\t\tc = this.buffer_a[i]\n\t\t} else {\n\t\t\tc = this.buffer_c[i-1] + this.buffer_a[i]\n\t\t}\n\n\t\tthis.buffer_c = append(this.buffer_c, c)\n\t}\n\n\tthis.last_result_values = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.last_result_values = append(this.last_result_values, 0)\n\t}\n\n\tthis.result_t_counts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.result_t_counts = append(this.result_t_counts, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.result_t_counts[i] = append(this.result_t_counts[i], 0)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_round * int64(i)\n\t\tend_elem := this.input_size_dpu_round * int64(i+1)\n\n\t\tthis.last_result_values[i] = this.Sum1D(this.buffer_a[start_elem:end_elem])\n\t\tthis.result_t_counts[i][this.num_tasklets-1] = this.last_result_values[i]\n\t}\n\n\tthis.dpu_arg_size = this.input_size_dpu_round * elem_size\n\tthis.kernels = []int64{0, 1}\n\n\tthis.t_counts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.t_counts = append(this.t_counts, make([]int64, 0))\n\n\t\tfor j := 0; j < 2; j++ {\n\t\t\tif i == 0 {\n\t\t\t\tthis.t_counts[i] = []int64{\n\t\t\t\t\t0,\n\t\t\t\t\t0,\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tthis.t_counts[i] = []int64{\n\t\t\t\t\t0,\n\t\t\t\t\tthis.Sum2D(this.result_t_counts[0:i]),\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *ScanSsa) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_size)\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[execution])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tt_count_word := new(word.Word)\n\tt_count_word.Init(64)\n\tt_count_word.SetValue(this.t_counts[dpu_id][execution])\n\tdpu_input_arguments_byte_stream.Merge(t_count_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *ScanSsa) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tif execution == 0 {\n\t\tfor _, result_t_count := range this.result_t_counts[dpu_id] {\n\t\t\tresult_t_count_word := new(word.Word)\n\t\t\tresult_t_count_word.Init(64)\n\t\t\tresult_t_count_word.SetValue(result_t_count)\n\t\t\tdpu_results_byte_stream.Merge(result_t_count_word.ToByteStream())\n\t\t}\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *ScanSsa) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution == 0 {\n\t\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\t\tend_elem := this.input_size_dpu_round * int64(dpu_id+1)\n\n\t\tfor _, element := range this.buffer_a[start_elem:end_elem] {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(64)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *ScanSsa) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution == this.num_executions-1 {\n\t\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\t\tend_elem := this.input_size_dpu_round * int64(dpu_id+1)\n\n\t\tfor _, element := range this.buffer_c[start_elem:end_elem] {\n\t\t\telement_word := new(word.Word)\n\t\t\telement_word.Init(64)\n\t\t\telement_word.SetValue(element)\n\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t}\n\t}\n\n\treturn int64(this.input_size_dpu_round * 8), byte_stream\n}\n\nfunc (this *ScanSsa) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *ScanSsa) Sum1D(s []int64) int64 {\n\tsum := int64(0)\n\tfor _, element := range s {\n\t\tsum += element\n\t}\n\treturn sum\n}\n\nfunc (this *ScanSsa) Sum2D(s [][]int64) int64 {\n\tsum := int64(0)\n\tfor _, elements := range s {\n\t\tfor _, element := range elements {\n\t\t\tsum += element\n\t\t}\n\t}\n\treturn sum\n}\n\nfunc (this *ScanSsa) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/sel.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Sel struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tbuffer_a             []int64\n\tbuffer_c             [][]int64\n\tinput_size_dpu_round int64\n\tpos                  []int64\n\tdpu_arg_sizes        []int64\n\tkernels              []int64\n\tresults              [][]int64\n}\n\nfunc (this *Sel) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(8)\n\n\tregs := int64(128)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif input_size_dpu%(int64(this.num_tasklets)*regs) == 0 {\n\t\tthis.input_size_dpu_round = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_round = int64(math.Ceil(float64(input_size_dpu)/float64(int64(this.num_tasklets)*regs))) * int64(this.num_tasklets) * regs\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar a int64\n\t\tif i < input_size {\n\t\t\ta = i + 1\n\t\t} else {\n\t\t\ta = 0\n\t\t}\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t}\n\n\tthis.buffer_c = make([][]int64, 0)\n\tthis.pos = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([]int64, 0))\n\n\t\tstart_elem := this.input_size_dpu_round * int64(i)\n\t\tend_elem := this.input_size_dpu_round * int64(i+1)\n\n\t\tfor _, a := range this.buffer_a[start_elem:end_elem] {\n\t\t\tif a%2 != 0 {\n\t\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], a)\n\t\t\t}\n\t\t}\n\n\t\tthis.pos = append(this.pos, int64(len(this.buffer_c[i])))\n\n\t\tfor int64(len(this.buffer_c[i])) < this.input_size_dpu_round {\n\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], 0)\n\t\t}\n\t}\n\n\tthis.dpu_arg_sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.dpu_arg_sizes = append(this.dpu_arg_sizes, this.input_size_dpu_round*elem_size)\n\t}\n\n\tthis.kernels = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.kernels = append(this.kernels, 0)\n\t}\n\n\tthis.results = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.results = append(this.results, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tif j != this.num_tasklets-1 {\n\t\t\t\tthis.results[i] = append(this.results[i], 0)\n\t\t\t} else {\n\t\t\t\tthis.results[i] = append(this.results[i], this.pos[i])\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Sel) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tdpu_arg_size_word := new(word.Word)\n\tdpu_arg_size_word.Init(32)\n\tdpu_arg_size_word.SetValue(this.dpu_arg_sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(dpu_arg_size_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Sel) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tfor _, result := range this.results[dpu_id] {\n\t\tresult_word := new(word.Word)\n\t\tresult_word.Init(32)\n\t\tresult_word.SetValue(result)\n\t\tdpu_results_byte_stream.Merge(result_word.ToByteStream())\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Sel) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\n\tfor i := int64(0); i < this.input_size_dpu_round; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(this.buffer_a[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Sel) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i, element := range this.buffer_c[dpu_id] {\n\t\tif int64(i) >= this.pos[dpu_id] {\n\t\t\tbreak\n\t\t}\n\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(int64(element))\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn this.input_size_dpu_round * 8, byte_stream\n}\n\nfunc (this *Sel) NumExecutions() int {\n\treturn this.num_executions\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/trns.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Trns struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tnum_active_dpus_at_begining int64\n\tn                           int64\n\tM                           int64\n\tm                           int64\n\tN                           int64\n\n\tbuffer_a [][][]int64\n\tbuffer_c [][][]int64\n\tdones    []int64\n\n\tkernels []int64\n}\n\nfunc (this *Trns) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\t//NOTE(dongjae.lee@kaist.ac.kr): different parameter given if single dpu is simulated\n\tif num_channels == 1 && num_ranks_per_channel == 1 && num_dpus_per_rank == 1 {\n\t\tthis.N = 1\n\t\tthis.n = 4\n\t\tthis.M = int64(command_line_parser.DataPrepParams()[0])\n\t\tthis.m = 16\n\t} else {\n\t\tthis.N = 64\n\t\tthis.n = 8\n\t\tthis.M = int64(command_line_parser.DataPrepParams()[0])\n\t\tthis.m = 4\n\t}\n\n\tis_strong_scaling := true\n\tif !is_strong_scaling {\n\t\tthis.N *= int64(this.num_dpus)\n\t}\n\n\tif this.N > int64(this.num_dpus) {\n\t\tthis.num_active_dpus_at_begining = int64(this.num_dpus)\n\t} else {\n\t\tthis.num_active_dpus_at_begining = this.N\n\t}\n\n\tif is_strong_scaling {\n\t\tthis.num_executions = int(2 * (this.N / this.num_active_dpus_at_begining))\n\t} else {\n\t\tthis.num_executions = int(2 * this.N)\n\t}\n\n\tthis.buffer_a = make([][][]int64, 0)\n\tfor i := int64(0); i < this.N; i++ {\n\t\tthis.buffer_a = append(this.buffer_a, make([][]int64, 0))\n\n\t\tfor j := int64(0); j < this.M*this.m; j++ {\n\t\t\tthis.buffer_a[i] = append(this.buffer_a[i], make([]int64, 0))\n\n\t\t\tfor k := int64(0); k < this.n; k++ {\n\t\t\t\tthis.buffer_a[i][j] = append(this.buffer_a[i][j], int64(rand.Intn(100)))\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.dones = make([]int64, 0)\n\tif (this.M*this.n)/8 == 0 {\n\t\tfor i := 0; i < 8; i++ {\n\t\t\tthis.dones = append(this.dones, 0)\n\t\t}\n\t} else {\n\t\tfor i := int64(0); i < this.M*this.n; i++ {\n\t\t\tthis.dones = append(this.dones, 0)\n\t\t}\n\t}\n\n\tthis.buffer_c = make([][][]int64, 0)\n\tfor i := int64(0); i < this.N; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, this.Transpose(this.buffer_a[i]))\n\t}\n\n\tthis.kernels = []int64{0, 1}\n}\n\nfunc (this *Trns) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tm_word := new(word.Word)\n\tm_word.Init(32)\n\tm_word.SetValue(this.m)\n\tdpu_input_arguments_byte_stream.Merge(m_word.ToByteStream())\n\n\tn_word := new(word.Word)\n\tn_word.Init(32)\n\tn_word.SetValue(this.n)\n\tdpu_input_arguments_byte_stream.Merge(n_word.ToByteStream())\n\n\tM_word := new(word.Word)\n\tM_word.Init(32)\n\tM_word.SetValue(this.M)\n\tdpu_input_arguments_byte_stream.Merge(M_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[execution%2])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Trns) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *Trns) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution%2 == 0 {\n\t\tfor _, row := range this.buffer_a[(this.num_active_dpus_at_begining*(int64(execution)/2))+int64(dpu_id)] {\n\t\t\tfor _, element := range row {\n\t\t\t\telement_word := new(word.Word)\n\t\t\t\telement_word.Init(64)\n\t\t\t\telement_word.SetValue(element)\n\t\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t\t}\n\t\t}\n\n\t\tfor _, done := range this.dones {\n\t\t\tdone_word := new(word.Word)\n\t\t\tdone_word.Init(8)\n\t\t\tdone_word.SetValue(done)\n\t\t\tbyte_stream.Merge(done_word.ToByteStream())\n\t\t}\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Trns) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tif execution%2 == 1 {\n\t\tfor _, row := range this.buffer_c[(this.num_active_dpus_at_begining*(int64(execution)/2))+int64(dpu_id)] {\n\t\t\tfor _, element := range row {\n\t\t\t\telement_word := new(word.Word)\n\t\t\t\telement_word.Init(64)\n\t\t\t\telement_word.SetValue(element)\n\t\t\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Trns) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Trns) Transpose(s [][]int64) [][]int64 {\n\txl := len(s[0])\n\tyl := len(s)\n\n\tresult := make([][]int64, xl)\n\n\tfor i, _ := range result {\n\t\tresult[i] = make([]int64, yl)\n\t}\n\n\tfor i := 0; i < xl; i++ {\n\t\tfor j := 0; j < yl; j++ {\n\t\t\tresult[i][j] = s[j][i]\n\t\t}\n\t}\n\treturn result\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/ts.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Ts struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tts_size        int64\n\tquery_length   int64\n\tquery_mean     int64\n\tquery_std      int64\n\tslice_per_dpu  int64\n\texclusion_zone int64\n\tkernel         int64\n\n\tmin_vals [][]int64\n\tmin_idxs [][]int64\n\tmax_vals [][]int64\n\tmax_idxs [][]int64\n\n\tquery_buffer    []int64\n\tt_series_buffer []int64\n\tamean_buffer    []int64\n\tasigma_buffer   []int64\n\n\tblock_size int64\n\tdotpip     int64\n\telem_size  int64\n}\n\nfunc (this *Ts) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tthis.ts_size = int64(command_line_parser.DataPrepParams()[0])\n\tthis.query_length = 64\n\n\tif this.ts_size%(int64(this.num_dpus)*int64(this.num_tasklets)*this.query_length) != 0 {\n\t\tthis.ts_size += int64(this.num_dpus)*int64(this.num_tasklets)*this.query_length - this.ts_size%(int64(this.num_dpus)*int64(this.num_tasklets)*this.query_length)\n\t}\n\n\tthis.t_series_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size; i++ {\n\t\tthis.t_series_buffer = append(this.t_series_buffer, i%127)\n\t}\n\n\tthis.query_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.query_length; i++ {\n\t\tthis.query_buffer = append(this.query_buffer, i%127)\n\t}\n\n\tthis.asigma_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size; i++ {\n\t\tthis.asigma_buffer = append(this.asigma_buffer, 0)\n\t}\n\n\tthis.amean_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size; i++ {\n\t\tthis.amean_buffer = append(this.amean_buffer, 0)\n\t}\n\n\tacum_sum_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size; i++ {\n\t\tif i == 0 {\n\t\t\tacum_sum_buffer = append(acum_sum_buffer, this.t_series_buffer[i])\n\t\t} else {\n\t\t\tacum_sum_buffer = append(acum_sum_buffer, this.t_series_buffer[i]+acum_sum_buffer[i-1])\n\t\t}\n\t}\n\n\tasqcum_sum_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size; i++ {\n\t\tif i == 0 {\n\t\t\tasqcum_sum_buffer = append(\n\t\t\t\tasqcum_sum_buffer,\n\t\t\t\tthis.t_series_buffer[i]*this.t_series_buffer[i],\n\t\t\t)\n\t\t} else {\n\t\t\tasqcum_sum_buffer = append(asqcum_sum_buffer, this.t_series_buffer[i]*this.t_series_buffer[i]+asqcum_sum_buffer[i-1])\n\t\t}\n\t}\n\n\tasum_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length+1; i++ {\n\t\tif i == 0 {\n\t\t\tasum_buffer = append(asum_buffer, acum_sum_buffer[this.query_length-i-1])\n\t\t} else {\n\t\t\tasum_buffer = append(asum_buffer, acum_sum_buffer[this.query_length+i-1]-acum_sum_buffer[i-1])\n\t\t}\n\t}\n\n\tasum_sq_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length+1; i++ {\n\t\tif i == 0 {\n\t\t\tasum_sq_buffer = append(asum_sq_buffer, asqcum_sum_buffer[this.query_length+i-1])\n\t\t} else {\n\t\t\tasum_sq_buffer = append(asum_sq_buffer, asqcum_sum_buffer[this.query_length+i-1]-asqcum_sum_buffer[i-1])\n\t\t}\n\t}\n\n\tamean_temp_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length; i++ {\n\t\tamean_temp_buffer = append(amean_temp_buffer, asum_buffer[i]/this.query_length)\n\t}\n\n\tasigma_sq_buffer := make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length; i++ {\n\t\tasigma_sq_buffer = append(\n\t\t\tasigma_sq_buffer,\n\t\t\tasum_sq_buffer[i]/this.query_length-this.amean_buffer[i]*this.amean_buffer[i],\n\t\t)\n\t}\n\n\tthis.asigma_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length; i++ {\n\t\tthis.asigma_buffer = append(\n\t\t\tthis.asigma_buffer,\n\t\t\tint64(math.Sqrt(float64(asigma_sq_buffer[i]))),\n\t\t)\n\t}\n\n\tthis.amean_buffer = make([]int64, 0)\n\tfor i := int64(0); i < this.ts_size-this.query_length; i++ {\n\t\tthis.amean_buffer = append(this.amean_buffer, amean_temp_buffer[i])\n\t}\n\n\tfor i := int64(0); i < this.query_length; i++ {\n\t\tthis.t_series_buffer = append(this.t_series_buffer, 0)\n\t}\n\n\tfor i := int64(0); i < this.query_length*2; i++ {\n\t\tthis.asigma_buffer = append(this.asigma_buffer, 0)\n\t\tthis.amean_buffer = append(this.amean_buffer, 0)\n\t}\n\n\tif len(this.t_series_buffer) != len(this.amean_buffer) {\n\t\terr := errors.New(\"t series buffer's length != amean buffer's length\")\n\t\tpanic(err)\n\t}\n\n\tthis.query_mean = 0\n\tfor i := int64(0); i < this.query_length; i++ {\n\t\tthis.query_mean += this.query_buffer[i]\n\t}\n\tthis.query_mean /= this.query_length\n\n\tquery_variance := int64(0)\n\tfor i := int64(0); i < this.query_length; i++ {\n\t\tquery_variance += (this.query_buffer[i] - this.query_mean) * (this.query_buffer[i] - this.query_mean)\n\t}\n\tquery_variance /= this.query_length\n\n\tquery_std_dev := math.Sqrt(float64(query_variance))\n\tthis.query_std = int64(query_std_dev)\n\n\tthis.slice_per_dpu = this.ts_size / int64(this.num_dpus)\n\n\tthis.min_vals = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.min_vals = append(this.min_vals, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.min_vals[i] = append(this.min_vals[i], 0x7FFFFFFF)\n\t\t}\n\t}\n\n\tthis.min_idxs = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.min_idxs = append(this.min_idxs, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.min_idxs[i] = append(this.min_idxs[i], 0)\n\t\t}\n\t}\n\n\tthis.max_vals = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.max_vals = append(this.max_vals, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.max_vals[i] = append(this.max_vals[i], 0)\n\t\t}\n\t}\n\n\tthis.max_idxs = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.max_idxs = append(this.max_idxs, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tthis.max_idxs[i] = append(this.max_idxs[i], 0)\n\t\t}\n\t}\n\n\tmy_start_elems := make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tmy_start_elems = append(my_start_elems, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tmy_start_elems[i] = append(\n\t\t\t\tmy_start_elems[i],\n\t\t\t\tthis.slice_per_dpu*int64(i)+int64(j)*(this.slice_per_dpu/int64(this.num_tasklets)),\n\t\t\t)\n\t\t}\n\t}\n\n\tmy_end_elems := make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tmy_end_elems = append(my_end_elems, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tmy_end_elems[i] = append(\n\t\t\t\tmy_end_elems[i],\n\t\t\t\tmy_start_elems[i][j]+(this.slice_per_dpu/int64(this.num_tasklets))-1,\n\t\t\t)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tif my_end_elems[i][j] > this.slice_per_dpu*int64(i+1)-this.query_length {\n\t\t\t\tmy_end_elems[i][j] = this.slice_per_dpu*int64(i+1) - this.query_length\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.block_size = 256\n\tthis.elem_size = 4\n\tincrement := this.block_size / this.elem_size\n\tthis.dotpip = this.block_size / this.elem_size\n\titer := int64(0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\titer = 0\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tfor k := my_start_elems[i][j]; k < my_end_elems[i][j]; k += increment {\n\t\t\t\tcache_dotprods := make([]int64, 0)\n\t\t\t\tfor l := int64(0); l < this.dotpip; l++ {\n\t\t\t\t\tcache_dotprods = append(cache_dotprods, 0)\n\t\t\t\t}\n\n\t\t\t\tfor l := int64(0); l < this.query_length/increment; l++ {\n\t\t\t\t\tcache_dotprods = this.DotProduct(this.t_series_buffer[k:k+increment],\n\t\t\t\t\t\tthis.t_series_buffer[k+increment:k+2*increment],\n\t\t\t\t\t\tthis.query_buffer[l*increment:(l+1)*increment],\n\t\t\t\t\t\tcache_dotprods,\n\t\t\t\t\t)\n\t\t\t\t}\n\n\t\t\t\tfor l := int64(0); l < increment; l++ {\n\t\t\t\t\tdistance := 2 * (this.query_length - (cache_dotprods[l]-this.query_length*this.amean_buffer[l+iter*increment+int64(i)*this.slice_per_dpu]*this.query_mean)/(this.asigma_buffer[l+iter*increment+int64(i)*this.slice_per_dpu]*this.query_std))\n\n\t\t\t\t\tif distance < this.min_vals[i][j] {\n\t\t\t\t\t\tthis.min_vals[i][j] = distance\n\t\t\t\t\t\tthis.min_idxs[i][j] = int64(k) + l - (int64(i) * this.slice_per_dpu)\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\titer++\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.exclusion_zone = 0\n\tthis.kernel = 0\n}\n\nfunc (this *Ts) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tts_size_word := new(word.Word)\n\tts_size_word.Init(32)\n\tts_size_word.SetValue(this.ts_size)\n\tdpu_input_arguments_byte_stream.Merge(ts_size_word.ToByteStream())\n\n\tquery_length_word := new(word.Word)\n\tquery_length_word.Init(32)\n\tquery_length_word.SetValue(this.query_length)\n\tdpu_input_arguments_byte_stream.Merge(query_length_word.ToByteStream())\n\n\tquery_mean_word := new(word.Word)\n\tquery_mean_word.Init(32)\n\tquery_mean_word.SetValue(this.query_mean)\n\tdpu_input_arguments_byte_stream.Merge(query_mean_word.ToByteStream())\n\n\tquery_std_word := new(word.Word)\n\tquery_std_word.Init(32)\n\tquery_std_word.SetValue(this.query_std)\n\tdpu_input_arguments_byte_stream.Merge(query_std_word.ToByteStream())\n\n\tslice_per_dpu_word := new(word.Word)\n\tslice_per_dpu_word.Init(32)\n\tslice_per_dpu_word.SetValue(this.slice_per_dpu)\n\tdpu_input_arguments_byte_stream.Merge(slice_per_dpu_word.ToByteStream())\n\n\texclusion_zone_word := new(word.Word)\n\texclusion_zone_word.Init(32)\n\texclusion_zone_word.SetValue(this.exclusion_zone)\n\tdpu_input_arguments_byte_stream.Merge(exclusion_zone_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernel)\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Ts) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tfor i := 0; i < this.num_tasklets; i++ {\n\t\tmin_val_word := new(word.Word)\n\t\tmin_val_word.Init(32)\n\t\tmin_val_word.SetValue(this.min_vals[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(min_val_word.ToByteStream())\n\n\t\tmin_idx_word := new(word.Word)\n\t\tmin_idx_word.Init(32)\n\t\tmin_idx_word.SetValue(this.min_idxs[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(min_idx_word.ToByteStream())\n\n\t\tmax_val_word := new(word.Word)\n\t\tmax_val_word.Init(32)\n\t\tmax_val_word.SetValue(this.max_vals[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(max_val_word.ToByteStream())\n\n\t\tmax_idx_word := new(word.Word)\n\t\tmax_idx_word.Init(32)\n\t\tmax_idx_word.SetValue(this.max_idxs[dpu_id][i])\n\t\tdpu_results_byte_stream.Merge(max_idx_word.ToByteStream())\n\t}\n\n\tdpu_results := make(map[string]*encoding.ByteStream, 0)\n\tdpu_results[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_results\n}\n\nfunc (this *Ts) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.slice_per_dpu * int64(dpu_id)\n\tend_elem := this.slice_per_dpu*int64(dpu_id+1) + this.query_length\n\n\tfor _, element := range this.query_buffer {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\tfor _, element := range this.t_series_buffer[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\tfor _, element := range this.amean_buffer[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\tfor _, element := range this.asigma_buffer[start_elem:end_elem] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Ts) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Ts) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Ts) DotProduct(a []int64, a_aux []int64, query []int64, result []int64) []int64 {\n\tfor i := int64(0); i < this.block_size/this.elem_size; i++ {\n\t\tfor j := int64(0); j < this.dotpip; j++ {\n\t\t\tif (j + i) > (this.block_size/this.elem_size)-1 {\n\t\t\t\tresult[j] += a_aux[(j+i)-this.block_size/this.elem_size] * query[i]\n\t\t\t} else {\n\t\t\t\tresult[j] += a[j+i] * query[i]\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/uni.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Uni struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tbuffer_a             []int64\n\tbuffer_c             [][]int64\n\tinput_size_dpu_round int64\n\tpos                  int64\n\tinput_sizes_dpu      []int64\n\tkernels              []int64\n\tt_counts             [][]int64\n\tfirsts               [][]int64\n\tlasts                [][]int64\n}\n\nfunc (this *Uni) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tsize := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(8)\n\n\tregs := int64(128)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = size\n\t} else {\n\t\tinput_size = size * int64(this.num_dpus)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif input_size_dpu%(int64(this.num_tasklets)*regs) == 0 {\n\t\tthis.input_size_dpu_round = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_round = int64(math.Ceil(float64(input_size_dpu)/float64(int64(this.num_tasklets)*regs))) * int64(this.num_tasklets) * regs\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_round*int64(this.num_dpus); i++ {\n\t\tvar a int64\n\t\tif i < input_size {\n\t\t\tif i%2 == 0 {\n\t\t\t\ta = i\n\t\t\t} else {\n\t\t\t\ta = i + 1\n\t\t\t}\n\t\t} else {\n\t\t\ta = this.buffer_a[input_size-1]\n\t\t}\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t}\n\n\tthis.buffer_c = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.buffer_c = append(this.buffer_c, make([]int64, 0))\n\n\t\tfor j := int64(0); j < this.input_size_dpu_round; j++ {\n\t\t\tthis.buffer_c[i] = append(this.buffer_c[i], 0)\n\t\t}\n\t}\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_round * int64(i)\n\n\t\tthis.buffer_c[i][0] = this.buffer_a[start_elem]\n\n\t\tthis.pos = 1\n\t\tfor j := int64(1); j < this.input_size_dpu_round; j++ {\n\t\t\tif this.buffer_a[start_elem+j] != this.buffer_a[start_elem+j-1] {\n\t\t\t\tthis.buffer_c[i][this.pos] = this.buffer_a[start_elem+j]\n\t\t\t\tthis.pos++\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.input_sizes_dpu = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.input_sizes_dpu = append(this.input_sizes_dpu, this.input_size_dpu_round*elem_size)\n\t}\n\n\tthis.kernels = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.kernels = append(this.kernels, 0)\n\t}\n\n\tthis.t_counts = make([][]int64, 0)\n\tthis.firsts = make([][]int64, 0)\n\tthis.lasts = make([][]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tstart_elem := this.input_size_dpu_round * int64(i)\n\n\t\tthis.t_counts = append(this.t_counts, make([]int64, 0))\n\t\tthis.firsts = append(this.firsts, make([]int64, 0))\n\t\tthis.lasts = append(this.lasts, make([]int64, 0))\n\n\t\tfor j := 0; j < this.num_tasklets; j++ {\n\t\t\tvar t_count int64\n\t\t\tvar first int64\n\t\t\tvar last int64\n\n\t\t\tif j == 0 && j != this.num_tasklets-1 {\n\t\t\t\tt_count = 0\n\t\t\t\tfirst = this.buffer_a[start_elem]\n\t\t\t\tlast = 0\n\t\t\t} else if j == this.num_tasklets-1 {\n\t\t\t\tt_count = this.pos\n\t\t\t\tfirst = 0\n\t\t\t\tlast = this.buffer_c[i][this.pos-1]\n\t\t\t} else {\n\t\t\t\tt_count = 0\n\t\t\t\tfirst = 0\n\t\t\t\tlast = 0\n\t\t\t}\n\n\t\t\tthis.t_counts[i] = append(this.t_counts[i], t_count)\n\t\t\tthis.firsts[i] = append(this.firsts[i], first)\n\t\t\tthis.lasts[i] = append(this.lasts[i], last)\n\t\t}\n\t}\n}\n\nfunc (this *Uni) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tinput_size_dpu_word := new(word.Word)\n\tinput_size_dpu_word.Init(32)\n\tinput_size_dpu_word.SetValue(this.input_sizes_dpu[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(input_size_dpu_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Uni) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_results_byte_stream := new(encoding.ByteStream)\n\tdpu_results_byte_stream.Init()\n\n\tif len(this.t_counts[dpu_id]) != len(this.firsts[dpu_id]) {\n\t\terr := errors.New(\"t counts' length != firsts' length\")\n\t\tpanic(err)\n\t} else if len(this.t_counts[dpu_id]) != len(this.lasts[dpu_id]) {\n\t\terr := errors.New(\"t counts' length != lasts' length\")\n\t\tpanic(err)\n\t}\n\n\tfor i := 0; i < len(this.t_counts[dpu_id]); i++ {\n\t\tt_count := this.t_counts[dpu_id][i]\n\t\tfirst := this.firsts[dpu_id][i]\n\t\tlast := this.lasts[dpu_id][i]\n\n\t\tt_count_word := new(word.Word)\n\t\tt_count_word.Init(64)\n\t\tt_count_word.SetValue(t_count)\n\t\tdpu_results_byte_stream.Merge(t_count_word.ToByteStream())\n\n\t\tfirst_word := new(word.Word)\n\t\tfirst_word.Init(64)\n\t\tfirst_word.SetValue(first)\n\t\tdpu_results_byte_stream.Merge(first_word.ToByteStream())\n\n\t\tlast_word := new(word.Word)\n\t\tlast_word.Init(64)\n\t\tlast_word.SetValue(last)\n\t\tdpu_results_byte_stream.Merge(last_word.ToByteStream())\n\t}\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_RESULTS\"] = dpu_results_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Uni) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_round * int64(dpu_id)\n\n\tfor i := int64(0); i < this.input_size_dpu_round; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(this.buffer_a[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Uni) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, element := range this.buffer_c[dpu_id] {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(64)\n\t\telement_word.SetValue(element)\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn this.input_size_dpu_round * 8, byte_stream\n}\n\nfunc (this *Uni) NumExecutions() int {\n\treturn this.num_executions\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/assembler/prim/va.go",
    "content": "package prim\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"math/rand\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Va struct {\n\tnum_dpus       int\n\tnum_tasklets   int\n\tnum_executions int\n\n\tinput_size_dpu_8bytes int64\n\tbuffer_a              []int64\n\tbuffer_b              []int64\n\tbuffer_c              []int64\n\tsizes                 []int64\n\ttransfer_sizes        []int64\n\tkernels               []int64\n}\n\nfunc (this *Va) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.num_executions = 1\n\n\tbuffer_size := int64(command_line_parser.DataPrepParams()[0])\n\n\telem_size := int64(4)\n\n\tis_strong_scaling := true\n\n\tvar input_size int64\n\tif is_strong_scaling {\n\t\tinput_size = buffer_size\n\t} else {\n\t\tinput_size = buffer_size * int64(this.num_dpus)\n\t}\n\n\tvar input_size_8bytes int64\n\tif (input_size*elem_size)%8 == 0 {\n\t\tinput_size_8bytes = input_size\n\t} else {\n\t\tinput_size_8bytes = int64(math.Ceil(float64(input_size)/float64(8)) * 8)\n\t}\n\n\tinput_size_dpu := (input_size-1)/int64(this.num_dpus) + 1\n\n\tif (input_size_dpu*elem_size)%8 == 0 {\n\t\tthis.input_size_dpu_8bytes = input_size_dpu\n\t} else {\n\t\tthis.input_size_dpu_8bytes = int64(math.Ceil(float64(input_size_dpu)/float64(8)) * 8)\n\t}\n\n\tthis.buffer_a = make([]int64, 0)\n\tthis.buffer_b = make([]int64, 0)\n\tthis.buffer_c = make([]int64, 0)\n\tfor i := int64(0); i < this.input_size_dpu_8bytes*int64(this.num_dpus); i++ {\n\t\ta := int64(rand.Intn(this.Pow2(31)))\n\t\tb := int64(rand.Intn(this.Pow2(31)))\n\n\t\tc := a + b\n\n\t\tthis.buffer_a = append(this.buffer_a, a)\n\t\tthis.buffer_b = append(this.buffer_b, b)\n\t\tthis.buffer_c = append(this.buffer_c, c)\n\t}\n\n\tthis.sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus-1; i++ {\n\t\tthis.sizes = append(this.sizes, this.input_size_dpu_8bytes*elem_size)\n\t}\n\tsize := (input_size_8bytes - this.input_size_dpu_8bytes*int64(this.num_dpus-1)) * elem_size\n\tthis.sizes = append(this.sizes, size)\n\n\tthis.transfer_sizes = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.transfer_sizes = append(this.transfer_sizes, this.input_size_dpu_8bytes*elem_size)\n\t}\n\n\tthis.kernels = make([]int64, 0)\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.kernels = append(this.kernels, 0)\n\t}\n}\n\nfunc (this *Va) InputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tdpu_input_arguments_byte_stream := new(encoding.ByteStream)\n\tdpu_input_arguments_byte_stream.Init()\n\n\tsize_word := new(word.Word)\n\tsize_word.Init(32)\n\tsize_word.SetValue(this.sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(size_word.ToByteStream())\n\n\ttransfer_size_word := new(word.Word)\n\ttransfer_size_word.Init(32)\n\ttransfer_size_word.SetValue(this.transfer_sizes[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(transfer_size_word.ToByteStream())\n\n\tkernel_word := new(word.Word)\n\tkernel_word.Init(32)\n\tkernel_word.SetValue(this.kernels[dpu_id])\n\tdpu_input_arguments_byte_stream.Merge(kernel_word.ToByteStream())\n\n\tdpu_host := make(map[string]*encoding.ByteStream, 0)\n\tdpu_host[\"DPU_INPUT_ARGUMENTS\"] = dpu_input_arguments_byte_stream\n\n\treturn dpu_host\n}\n\nfunc (this *Va) OutputDpuHost(execution int, dpu_id int) map[string]*encoding.ByteStream {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\treturn make(map[string]*encoding.ByteStream, 0)\n}\n\nfunc (this *Va) InputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_8bytes * int64(dpu_id)\n\n\tfor i := int64(0); i < this.input_size_dpu_8bytes; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(this.buffer_a[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\tfor i := int64(0); i < this.input_size_dpu_8bytes; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(this.buffer_b[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn 0, byte_stream\n}\n\nfunc (this *Va) OutputDpuMramHeapPointerName(\n\texecution int,\n\tdpu_id int,\n) (int64, *encoding.ByteStream) {\n\tif execution >= this.num_executions {\n\t\terr := errors.New(\"execution >= num executions\")\n\t\tpanic(err)\n\t} else if dpu_id >= this.num_dpus {\n\t\terr := errors.New(\"DPU ID >= num DPUs\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tstart_elem := this.input_size_dpu_8bytes * int64(dpu_id)\n\n\tfor i := int64(0); i < this.input_size_dpu_8bytes; i++ {\n\t\telement_word := new(word.Word)\n\t\telement_word.Init(32)\n\t\telement_word.SetValue(this.buffer_c[start_elem+i])\n\t\tbyte_stream.Merge(element_word.ToByteStream())\n\t}\n\n\treturn this.input_size_dpu_8bytes * 4, byte_stream\n}\n\nfunc (this *Va) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Va) Pow2(exponent int) int {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := 1\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/compiler/compiler.go",
    "content": "package compiler\n\nimport (\n\t\"os/exec\"\n\t\"path/filepath\"\n\t\"strconv\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Compiler struct {\n\tcommand_line_parser *misc.CommandLineParser\n\n\troot_dirpath string\n\tbenchmark    string\n\n\tnum_dpus     int\n\tnum_tasklets int\n}\n\nfunc (this *Compiler) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n\n\tthis.root_dirpath = command_line_parser.StringParameter(\"root_dirpath\")\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.Build()\n}\n\nfunc (this *Compiler) Build() {\n\tdocker_dirpath := filepath.Join(this.root_dirpath, \"docker\")\n\n\tcommand := exec.Command(\"docker\", \"build\", \"-t\", \"bongjoonhyun/upimulator\", docker_dirpath)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Compiler) Compile() {\n\tthis.CompileBenchmark()\n\tthis.CompileSdk()\n}\n\nfunc (this *Compiler) CompileBenchmark() {\n\tcommand := exec.Command(\n\t\t\"docker\",\n\t\t\"run\",\n\t\t\"--privileged\",\n\t\t\"--rm\",\n\t\t\"-v\",\n\t\tthis.root_dirpath+\":/root/uPIMulator\",\n\t\t\"bongjoonhyun/upimulator\",\n\t\t\"python3\",\n\t\t\"/root/uPIMulator/benchmark/build.py\",\n\t\t\"--num_dpus\",\n\t\tstrconv.Itoa(this.num_dpus),\n\t\t\"--num_tasklets\",\n\t\tstrconv.Itoa(this.num_tasklets),\n\t)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Compiler) CompileSdk() {\n\tcommand := exec.Command(\n\t\t\"docker\",\n\t\t\"run\",\n\t\t\"--privileged\",\n\t\t\"--rm\",\n\t\t\"-v\",\n\t\tthis.root_dirpath+\":/root/uPIMulator\",\n\t\t\"bongjoonhyun/upimulator\",\n\t\t\"python3\",\n\t\t\"/root/uPIMulator/sdk/build.py\",\n\t\t\"--num_tasklets\",\n\t\tstrconv.Itoa(this.num_tasklets),\n\t)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/core/job.go",
    "content": "package core\n\ntype Job interface {\n\tExecute()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/core/thread_pool.go",
    "content": "package core\n\nimport (\n\t\"errors\"\n\t\"sync\"\n)\n\ntype ThreadPool struct {\n\tnum_threads  int\n\tchannel_size int\n\n\tjobs []Job\n\n\twg sync.WaitGroup\n}\n\nfunc (this *ThreadPool) Init(num_threads int) {\n\tif num_threads <= 0 {\n\t\terr := errors.New(\"num threads <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.num_threads = num_threads\n\n\tthis.jobs = make([]Job, 0)\n}\n\nfunc (this *ThreadPool) Enque(job Job) {\n\tthis.wg.Add(1)\n\tthis.jobs = append(this.jobs, job)\n}\n\nfunc (this *ThreadPool) Start() {\n\tfor _, job := range this.jobs {\n\t\tgo this.Dispatch(job)\n\t}\n\tthis.wg.Wait()\n}\n\nfunc (this *ThreadPool) Dispatch(job Job) {\n\tdefer this.wg.Done()\n\tjob.Execute()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/analyze_liveness_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/logic\"\n)\n\ntype AnalyzeLivenessJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *AnalyzeLivenessJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *AnalyzeLivenessJob) Execute() {\n\tfmt.Printf(\"Analyzing the liveness of %s...\\n\", this.relocatable.Path())\n\n\tliveness_analyzer := new(logic.LivenessAnalyzer)\n\tliveness_analyzer.Init()\n\n\tliveness := liveness_analyzer.Analyze(this.relocatable)\n\tthis.relocatable.SetLiveness(liveness)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/ascii_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype AsciiDirective struct {\n\tcharacters string\n}\n\nfunc (this *AsciiDirective) Init(characters string) {\n\tthis.characters = characters\n}\n\nfunc (this *AsciiDirective) Characters() string {\n\treturn this.characters\n}\n\nfunc (this *AsciiDirective) Size() int64 {\n\treturn int64(len(this.characters))\n}\n\nfunc (this *AsciiDirective) Encode() *encoding.ByteStream {\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\treturn ascii_encoder.Encode(this.characters)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/asciz_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype AscizDirective struct {\n\tcharacters string\n}\n\nfunc (this *AscizDirective) Init(characters string) {\n\tthis.characters = characters\n}\n\nfunc (this *AscizDirective) Characters() string {\n\treturn this.characters\n}\n\nfunc (this *AscizDirective) Size() int64 {\n\treturn int64(len(this.characters)) + 1\n}\n\nfunc (this *AscizDirective) Encode() *encoding.ByteStream {\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\treturn ascii_encoder.Encode(this.characters + ascii_encoder.Unknown())\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/byte_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n)\n\ntype ByteDirective struct {\n\timmediate *word.Immediate\n}\n\nfunc (this *ByteDirective) Init(value int64) {\n\tthis.immediate = new(word.Immediate)\n\tthis.immediate.Init(word.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *ByteDirective) Size() int64 {\n\treturn 1\n}\n\nfunc (this *ByteDirective) Immediate() *word.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ByteDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/long_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n)\n\ntype LongDirective struct {\n\timmediate *word.Immediate\n}\n\nfunc (this *LongDirective) Init(value int64) {\n\tthis.immediate = new(word.Immediate)\n\tthis.immediate.Init(word.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *LongDirective) Size() int64 {\n\treturn 4\n}\n\nfunc (this *LongDirective) Immediate() *word.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *LongDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/quad_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n)\n\ntype QuadDirective struct {\n\timmediate *word.Immediate\n}\n\nfunc (this *QuadDirective) Init(value int64) {\n\tthis.immediate = new(word.Immediate)\n\tthis.immediate.Init(word.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *QuadDirective) Size() int64 {\n\treturn 8\n}\n\nfunc (this *QuadDirective) Immediate() *word.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *QuadDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/short_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n)\n\ntype ShortDirective struct {\n\timmediate *word.Immediate\n}\n\nfunc (this *ShortDirective) Init(value int64) {\n\tthis.immediate = new(word.Immediate)\n\tthis.immediate.Init(word.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *ShortDirective) Size() int64 {\n\treturn 2\n}\n\nfunc (this *ShortDirective) Immediate() *word.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ShortDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/directive/zero_directive.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n)\n\ntype ZeroDirective struct {\n\tsize      int64\n\timmediate *word.Immediate\n}\n\nfunc (this *ZeroDirective) Init(size int64, value int64) {\n\tif size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\n\tthis.immediate = new(word.Immediate)\n\tthis.immediate.Init(word.UNSIGNED, 8, value)\n}\n\nfunc (this *ZeroDirective) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *ZeroDirective) Immediate() *word.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ZeroDirective) Encode() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < this.size; i++ {\n\t\tbyte_stream.Merge(this.immediate.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/encodable.go",
    "content": "package kernel\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype Encodable interface {\n\tEncode() *encoding.ByteStream\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/executable.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"sort\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Executable struct {\n\tname string\n\tpath string\n\n\tbenchmark_relocatable *Relocatable\n\tsdk_relocatables      map[*Relocatable]bool\n\n\ttoken_stream *lexer.TokenStream\n\tast          *parser.Ast\n\tliveness     *Liveness\n\n\tsections    map[*Section]bool\n\tcur_section *Section\n}\n\nfunc (this *Executable) Init(name string) {\n\tthis.name = name\n\n\tthis.sdk_relocatables = make(map[*Relocatable]bool, 0)\n\n\tthis.liveness = new(Liveness)\n\tthis.liveness.Init()\n\n\tthis.sections = make(map[*Section]bool, 0)\n}\n\nfunc (this *Executable) Name() string {\n\treturn this.name\n}\n\nfunc (this *Executable) Path() string {\n\treturn this.path\n}\n\nfunc (this *Executable) SetPath(path string) {\n\tthis.path = path\n}\n\nfunc (this *Executable) SetBenchmarkRelocatable(relocatable *Relocatable) {\n\tthis.benchmark_relocatable = relocatable\n\n\tthis.UpdateUnresolvedSymbols(relocatable)\n}\n\nfunc (this *Executable) AddSdkRelocatable(relocatable *Relocatable) {\n\tthis.sdk_relocatables[relocatable] = true\n\n\tthis.UpdateLocalSymbols(relocatable)\n\tthis.UpdateUnresolvedSymbols(relocatable)\n}\n\nfunc (this *Executable) TokenStream() *lexer.TokenStream {\n\treturn this.token_stream\n}\n\nfunc (this *Executable) SetTokenStream(token_stream *lexer.TokenStream) {\n\tthis.token_stream = token_stream\n}\n\nfunc (this *Executable) Ast() *parser.Ast {\n\treturn this.ast\n}\n\nfunc (this *Executable) SetAst(ast *parser.Ast) {\n\tthis.ast = ast\n}\n\nfunc (this *Executable) Liveness() *Liveness {\n\treturn this.liveness\n}\n\nfunc (this *Executable) DumpAssembly() {\n\tlines := this.benchmark_relocatable.Lines()\n\n\tfor sdk_relocatable, _ := range this.sdk_relocatables {\n\t\tlines = append(lines, sdk_relocatable.Lines()...)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(this.path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpAddresses(path string) {\n\tlines := make([]string, 0)\n\n\tfor label_name, label_address := range this.Addresses() {\n\t\tline := fmt.Sprintf(\"%s: %d\", label_name, label_address)\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpAtomic(path string) {\n\tatomic_byte_stream := this.AtomicByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < atomic_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", atomic_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpIram(path string) {\n\tiram_byte_stream := this.IramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < iram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", iram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpWram(path string) {\n\twram_byte_stream := this.WramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < wram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", wram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpMram(path string) {\n\tmram_byte_stream := this.MramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < mram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", mram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) Section(section_name SectionName, name string) *Section {\n\tfor section, _ := range this.sections {\n\t\tif section.SectionName() == section_name && section.Name() == name {\n\t\t\treturn section\n\t\t}\n\t}\n\treturn nil\n}\n\nfunc (this *Executable) Sections(section_name SectionName) map[*Section]bool {\n\tsections := make(map[*Section]bool, 0)\n\tfor section, _ := range this.sections {\n\t\tif section.SectionName() == section_name {\n\t\t\tsections[section] = true\n\t\t}\n\t}\n\treturn sections\n}\n\nfunc (this *Executable) AddSection(\n\tsection_name SectionName,\n\tname string,\n\tsection_flags map[SectionFlag]bool,\n\tsection_type SectionType,\n) {\n\tif this.Section(section_name, name) == nil {\n\t\tsection := new(Section)\n\t\tsection.Init(section_name, name, section_flags, section_type)\n\t\tthis.sections[section] = true\n\t}\n}\n\nfunc (this *Executable) CurSection() *Section {\n\treturn this.cur_section\n}\n\nfunc (this *Executable) CheckoutSection(section_name SectionName, name string) {\n\tif section := this.Section(section_name, name); section != nil {\n\t\tthis.cur_section = section\n\t} else {\n\t\terr := errors.New(\"section is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Executable) Label(label_name string) *Label {\n\tvar label *Label = nil\n\tfor section, _ := range this.sections {\n\t\tsection_label := section.Label(label_name)\n\n\t\tif section_label != nil {\n\t\t\tif label != nil {\n\t\t\t\terr := errors.New(\"labels are duplicated\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tlabel = section_label\n\t\t}\n\t}\n\treturn label\n}\n\nfunc (this *Executable) Addresses() map[string]int64 {\n\taddresses := make(map[string]int64, 0)\n\tfor section, _ := range this.sections {\n\t\tfor _, label := range section.Labels() {\n\t\t\taddresses[label.Name()] = label.Address()\n\t\t}\n\t}\n\treturn addresses\n}\n\nfunc (this *Executable) AtomicByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tatomic_sections := this.Sort(\n\t\tconfig_loader.AtomicOffset(),\n\t\tconfig_loader.AtomicOffset()+config_loader.AtomicSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, atomic_section := range atomic_sections {\n\t\tbyte_stream.Merge(atomic_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) IramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_sections := this.Sort(\n\t\tconfig_loader.IramOffset(),\n\t\tconfig_loader.IramOffset()+config_loader.IramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, iram_section := range iram_sections {\n\t\tbyte_stream.Merge(iram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) WramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_sections := this.Sort(\n\t\tconfig_loader.WramOffset(),\n\t\tconfig_loader.WramOffset()+config_loader.WramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, wram_section := range wram_sections {\n\t\tbyte_stream.Merge(wram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) MramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_sections := this.Sort(\n\t\tconfig_loader.MramOffset(),\n\t\tconfig_loader.MramOffset()+config_loader.MramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, mram_section := range mram_sections {\n\t\tbyte_stream.Merge(mram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) UpdateLocalSymbols(relocatable *Relocatable) {\n\tfor old_name, _ := range relocatable.Liveness().LocalSymbols() {\n\t\tnew_name := relocatable.Name() + \".\" + old_name\n\n\t\trelocatable.RenameLocalSymbol(old_name, new_name)\n\t}\n}\n\nfunc (this *Executable) UpdateUnresolvedSymbols(relocatable *Relocatable) {\n\tfor def, _ := range relocatable.Liveness().Defs() {\n\t\tthis.liveness.AddDef(def)\n\t}\n\n\tfor use, _ := range relocatable.Liveness().Uses() {\n\t\tthis.liveness.AddUse(use)\n\t}\n\n\tfor global_symbol, _ := range relocatable.Liveness().GlobalSymbols() {\n\t\tthis.liveness.AddGlobalSymbol(global_symbol)\n\t}\n}\n\nfunc (this *Executable) Sort(begin_address int64, end_address int64) []*Section {\n\tsections := make([]*Section, 0)\n\n\tfor section, _ := range this.sections {\n\t\taddress := section.Address()\n\n\t\tif begin_address <= address && address < end_address {\n\t\t\tsections = append(sections, section)\n\t\t}\n\t}\n\n\tsort_fn := func(i int, j int) bool {\n\t\treturn sections[i].Address() < sections[j].Address()\n\t}\n\n\tsort.Slice(sections, sort_fn)\n\n\treturn sections\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/acquire_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype AcquireCc struct {\n\tcondition Condition\n}\n\nfunc (this *AcquireCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *AcquireCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/add_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype AddNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *AddNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tNC5:  true,\n\t\tNC6:  true,\n\t\tNC7:  true,\n\t\tNC8:  true,\n\t\tNC9:  true,\n\t\tNC10: true,\n\t\tNC11: true,\n\t\tNC12: true,\n\t\tNC13: true,\n\t\tNC14: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *AddNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/boot_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype BootCc struct {\n\tcondition Condition\n}\n\nfunc (this *BootCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *BootCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/cc.go",
    "content": "package cc\n\ntype Condition int\n\nconst (\n\tTRUE Condition = iota\n\tFALSE\n\n\tZ\n\tNZ\n\n\tE\n\tO\n\n\tPL\n\tMI\n\n\tOV\n\tNOV\n\n\tC\n\tNC\n\n\tSZ\n\tSNZ\n\n\tSPL\n\tSMI\n\n\tSO\n\tSE\n\n\tNC5\n\tNC6\n\tNC7\n\tNC8\n\tNC9\n\tNC10\n\tNC11\n\tNC12\n\tNC13\n\tNC14\n\n\tMAX\n\tNMAX\n\n\tSH32\n\tNSH32\n\n\tEQ\n\tNEQ\n\n\tLTU\n\tLEU\n\tGTU\n\tGEU\n\n\tLTS\n\tLES\n\tGTS\n\tGES\n\n\tXZ\n\tXNZ\n\n\tXLEU\n\tXGTU\n\n\tXLES\n\tXGTS\n\n\tSMALL\n\tLARGE\n)\n\ntype Cc interface {\n\tCondition() Condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/const_cc_ge0.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcGe0 struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcGe0) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tPL: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcGe0) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/const_cc_geu.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcGeu struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcGeu) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tGEU: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcGeu) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/const_cc_zero.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcZero struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcZero) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcZero) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/count_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype CountNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *CountNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tMAX:  true,\n\t\tNMAX: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *CountNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/div_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype DivCc struct {\n\tcondition Condition\n}\n\nfunc (this *DivCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *DivCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/div_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype DivNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *DivNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *DivNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/ext_sub_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ExtSubSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *ExtSubSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tEQ:   true,\n\t\tNEQ:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tGES:  true,\n\t\tGEU:  true,\n\t\tGTS:  true,\n\t\tGTU:  true,\n\t\tLES:  true,\n\t\tLEU:  true,\n\t\tLTS:  true,\n\t\tLTU:  true,\n\t\tXGTS: true,\n\t\tXGTU: true,\n\t\tXLES: true,\n\t\tXLEU: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ExtSubSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/false_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype FalseCc struct {\n\tcondition Condition\n}\n\nfunc (this *FalseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *FalseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/imm_shift_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ImmShiftNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *ImmShiftNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tE:    true,\n\t\tO:    true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tSE:   true,\n\t\tSO:   true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ImmShiftNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/log_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype LogNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *LogNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *LogNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/log_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype LogSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *LogSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:   true,\n\t\tNZ:  true,\n\t\tXZ:  true,\n\t\tXNZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *LogSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/mul_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype MulNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *MulNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tLARGE: true,\n\t\tSMALL: true,\n\t\tTRUE:  true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *MulNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/no_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype NoCc struct {\n\tcondition Condition\n}\n\nfunc (this *NoCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *NoCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/release_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ReleaseCc struct {\n\tcondition Condition\n}\n\nfunc (this *ReleaseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tNZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ReleaseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/shift_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ShiftNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *ShiftNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tE:     true,\n\t\tO:     true,\n\t\tPL:    true,\n\t\tMI:    true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSE:    true,\n\t\tSO:    true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tSH32:  true,\n\t\tNSH32: true,\n\t\tTRUE:  true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ShiftNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/sub_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype SubNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *SubNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tMI:   true,\n\t\tPL:   true,\n\t\tEQ:   true,\n\t\tNEQ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tGES:  true,\n\t\tGEU:  true,\n\t\tGTS:  true,\n\t\tGTU:  true,\n\t\tLES:  true,\n\t\tLEU:  true,\n\t\tLTS:  true,\n\t\tLTU:  true,\n\t\tXGTS: true,\n\t\tXGTU: true,\n\t\tXLES: true,\n\t\tXLEU: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *SubNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/sub_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype SubSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *SubSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:   true,\n\t\tNZ:  true,\n\t\tXZ:  true,\n\t\tXNZ: true,\n\t\tEQ:  true,\n\t\tNEQ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *SubSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/true_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype TrueCc struct {\n\tcondition Condition\n}\n\nfunc (this *TrueCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *TrueCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/cc/true_false_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype TrueFalseCc struct {\n\tcondition Condition\n}\n\nfunc (this *TrueFalseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *TrueFalseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/endian.go",
    "content": "package instruction\n\ntype Endian int\n\nconst (\n\tLITTLE Endian = iota\n\tBIG\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/exception.go",
    "content": "package instruction\n\ntype Exception int\n\nconst (\n\tMEMORY_FAULT Exception = iota\n\tDMA_FAULT\n\tHEAP_FULL\n\tDIVISION_BY_ZERO\n\tASSERT\n\tHALT\n\tPRINT_OVERFLOW\n\tALREADY_PROFILING\n\tNOT_PROFILING\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/flag.go",
    "content": "package instruction\n\ntype Flag int\n\nconst (\n\tZERO Flag = iota\n\tCARRY\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/instruction.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"strconv\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Instruction struct {\n\top_code OpCode\n\tsuffix  Suffix\n\n\trc *reg_descriptor.GpRegDescriptor\n\tra *reg_descriptor.SrcRegDescriptor\n\trb *reg_descriptor.SrcRegDescriptor\n\n\tdc *reg_descriptor.PairRegDescriptor\n\tdb *reg_descriptor.PairRegDescriptor\n\n\tcondition *cc.Condition\n\n\timm *word.Immediate\n\toff *word.Immediate\n\tpc  *word.Immediate\n\n\tendian *Endian\n}\n\nfunc (this *Instruction) InitRici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RiciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RICI\n\tthis.ra = ra\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 16, imm)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = condition\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRri(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRric(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRIC\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\t\text_sub_setcc := new(cc.ExtSubSetCc)\n\t\text_sub_setcc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_setcc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRrici(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRICI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRrif(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRIF\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tfalse_cc := new(cc.FalseCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitRrr(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRR\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitRrrc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRC\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRrrci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRCI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZri(op_code OpCode, ra *reg_descriptor.SrcRegDescriptor, imm int64) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRI\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 28, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZric(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRIC\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 27, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 27, imm)\n\n\t\text_sub_setcc := new(cc.ExtSubSetCc)\n\t\text_sub_setcc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_setcc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZrici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRICI\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZrif(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRIF\n\tthis.ra = ra\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 27, imm)\n\n\tfalse_cc := new(cc.LogSetCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitZrr(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRR\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitZrrc(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRC\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZrrci(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRCI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRI && suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid S_RRI nor U_RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRric(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRIC && suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid S_RRI nor U_RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRrici(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRICI && suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRrif(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRIF && suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tfalse_cc := new(cc.FalseCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRrr(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRR && suffix != U_RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitSRrrc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRC && suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRrrci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRCI && suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRr(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RR\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitRrc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRC\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitRrci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRCI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZr(op_code OpCode, ra *reg_descriptor.SrcRegDescriptor) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZR\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitZrc(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRC\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitZrci(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRCI\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRr(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RR && suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitSRrc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRC && suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRrci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRCI && suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitDrdici(\n\top_code OpCode,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tdb *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.DrdiciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DRDICI\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tif _, is_div_step_drdici_op_code := this.DivStepDrdiciOpCodes()[op_code]; is_div_step_drdici_op_code {\n\t\tdiv_cc := new(cc.DivCc)\n\t\tdiv_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = div_cc.Condition()\n\t} else if _, is_mul_step_drdici_op_code := this.MulStepDrdiciOpCodes()[op_code]; is_mul_step_drdici_op_code {\n\t\tboot_cc := new(cc.BootCc)\n\t\tboot_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = boot_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRrri(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitRrrici(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRICI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZrri(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitZrrici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRICI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRrri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRI && suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitSRrrici(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRICI && suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRir(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIR\n\tthis.rc = rc\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitRirc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIRC\n\tthis.rc = rc\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitRirci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIRCI\n\tthis.rc = rc\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZir(op_code OpCode, imm int64, ra *reg_descriptor.SrcRegDescriptor) {\n\tif _, found := this.RirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIR\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitZirc(\n\top_code OpCode,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIRC\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 27, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitZirci(\n\top_code OpCode,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIRCI\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 11, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRirc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RIRC && suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRirci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RIRCI && suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitR(op_code OpCode, rc *reg_descriptor.GpRegDescriptor) {\n\tif _, found := this.ROpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = R\n\tthis.rc = rc\n}\n\nfunc (this *Instruction) InitRci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RCI\n\tthis.rc = rc\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZ(op_code OpCode) {\n\tif _, found := this.ROpCodes()[op_code]; !found && op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = Z\n}\n\nfunc (this *Instruction) InitZci(\n\top_code OpCode,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZCI\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSR(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n) {\n\tif _, found := this.ROpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_R && suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n}\n\nfunc (this *Instruction) InitSRci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RCI && suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitCi(op_code OpCode, condition cc.Condition, pc int64) {\n\tif _, found := this.CiOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = CI\n\n\tboot_cc := new(cc.BootCc)\n\tboot_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = boot_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitI(op_code OpCode, imm int64) {\n\tif _, found := this.IOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = I\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n}\n\nfunc (this *Instruction) InitDdci(\n\top_code OpCode,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tdb *reg_descriptor.PairRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.DdciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DDCI\n\n\tthis.dc = dc\n\tthis.db = db\n\n\ttrue_false_cc := new(cc.TrueFalseCc)\n\ttrue_false_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_false_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitErri(\n\top_code OpCode,\n\tendian Endian,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.ErriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERRI\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitSErri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tendian Endian,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.ErriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_ERRI && suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitEdri(\n\top_code OpCode,\n\tendian Endian,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.EdriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = EDRI\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitErii(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\timm int64,\n) {\n\tif _, found := this.EriiOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERII\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 16, imm)\n}\n\nfunc (this *Instruction) InitErir(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.ErirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERIR\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitErid(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\tdb *reg_descriptor.PairRegDescriptor,\n) {\n\tif _, found := this.EridOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERID\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\tthis.db = db\n}\n\nfunc (this *Instruction) InitDmaRri(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.DmaRriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DMA_RRI\n\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 8, imm)\n}\n\nfunc (this *Instruction) OpCode() OpCode {\n\treturn this.op_code\n}\n\nfunc (this *Instruction) Suffix() Suffix {\n\treturn this.suffix\n}\n\nfunc (this *Instruction) Rc() *reg_descriptor.GpRegDescriptor {\n\treturn this.rc\n}\n\nfunc (this *Instruction) Ra() *reg_descriptor.SrcRegDescriptor {\n\treturn this.ra\n}\n\nfunc (this *Instruction) Rb() *reg_descriptor.SrcRegDescriptor {\n\treturn this.rb\n}\n\nfunc (this *Instruction) Dc() *reg_descriptor.PairRegDescriptor {\n\treturn this.dc\n}\n\nfunc (this *Instruction) Db() *reg_descriptor.PairRegDescriptor {\n\treturn this.db\n}\n\nfunc (this *Instruction) Condition() cc.Condition {\n\tif this.condition == nil {\n\t\terr := errors.New(\"condition == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.condition\n}\n\nfunc (this *Instruction) Imm() *word.Immediate {\n\treturn this.imm\n}\n\nfunc (this *Instruction) Off() *word.Immediate {\n\treturn this.off\n}\n\nfunc (this *Instruction) Pc() *word.Immediate {\n\treturn this.pc\n}\n\nfunc (this *Instruction) Endian() Endian {\n\tif this.endian == nil {\n\t\terr := errors.New(\"endian == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.endian\n}\n\nfunc (this *Instruction) Encode() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tword_ := new(word.Word)\n\tword_.Init(config_loader.IramDataWidth())\n\n\tthis.EncodeOpCode(word_)\n\tthis.EncodeSuffix(word_)\n\n\tif this.suffix == RICI {\n\t\tthis.EncodeRici(word_)\n\t} else if this.suffix == RRI {\n\t\tthis.EncodeRri(word_)\n\t} else if this.suffix == RRIC {\n\t\tthis.EncodeRric(word_)\n\t} else if this.suffix == RRICI {\n\t\tthis.EncodeRrici(word_)\n\t} else if this.suffix == RRIF {\n\t\tthis.EncodeRrif(word_)\n\t} else if this.suffix == RRR {\n\t\tthis.EncodeRrr(word_)\n\t} else if this.suffix == RRRC {\n\t\tthis.EncodeRrrc(word_)\n\t} else if this.suffix == RRRCI {\n\t\tthis.EncodeRrrci(word_)\n\t} else if this.suffix == ZRI {\n\t\tthis.EncodeZri(word_)\n\t} else if this.suffix == ZRIC {\n\t\tthis.EncodeZric(word_)\n\t} else if this.suffix == ZRICI {\n\t\tthis.EncodeZrici(word_)\n\t} else if this.suffix == ZRIF {\n\t\tthis.EncodeZrif(word_)\n\t} else if this.suffix == ZRR {\n\t\tthis.EncodeZrr(word_)\n\t} else if this.suffix == ZRRC {\n\t\tthis.EncodeZrrc(word_)\n\t} else if this.suffix == ZRRCI {\n\t\tthis.EncodeZrrci(word_)\n\t} else if this.suffix == S_RRI || this.suffix == U_RRI {\n\t\tthis.EncodeSRri(word_)\n\t} else if this.suffix == S_RRIC || this.suffix == U_RRIC {\n\t\tthis.EncodeSRric(word_)\n\t} else if this.suffix == S_RRICI || this.suffix == U_RRICI {\n\t\tthis.EncodeSRrici(word_)\n\t} else if this.suffix == S_RRIF || this.suffix == U_RRIF {\n\t\tthis.EncodeSRrif(word_)\n\t} else if this.suffix == S_RRR || this.suffix == U_RRR {\n\t\tthis.EncodeSRrr(word_)\n\t} else if this.suffix == S_RRRC || this.suffix == U_RRRC {\n\t\tthis.EncodeSRrrc(word_)\n\t} else if this.suffix == S_RRRCI || this.suffix == U_RRRCI {\n\t\tthis.EncodeSRrrci(word_)\n\t} else if this.suffix == RR {\n\t\tthis.EncodeRr(word_)\n\t} else if this.suffix == RRC {\n\t\tthis.EncodeRrc(word_)\n\t} else if this.suffix == RRCI {\n\t\tthis.EncodeRrci(word_)\n\t} else if this.suffix == ZR {\n\t\tthis.EncodeZr(word_)\n\t} else if this.suffix == ZRC {\n\t\tthis.EncodeZrc(word_)\n\t} else if this.suffix == ZRCI {\n\t\tthis.EncodeZrci(word_)\n\t} else if this.suffix == S_RR || this.suffix == U_RR {\n\t\tthis.EncodeSRr(word_)\n\t} else if this.suffix == S_RRC || this.suffix == U_RRC {\n\t\tthis.EncodeSRrc(word_)\n\t} else if this.suffix == S_RRCI || this.suffix == U_RRCI {\n\t\tthis.EncodeSRrci(word_)\n\t} else if this.suffix == DRDICI {\n\t\tthis.EncodeDrdici(word_)\n\t} else if this.suffix == RRRI {\n\t\tthis.EncodeRrri(word_)\n\t} else if this.suffix == RRRICI {\n\t\tthis.EncodeRrrici(word_)\n\t} else if this.suffix == ZRRI {\n\t\tthis.EncodeZrri(word_)\n\t} else if this.suffix == ZRRICI {\n\t\tthis.EncodeZrrici(word_)\n\t} else if this.suffix == S_RRRI || this.suffix == U_RRRI {\n\t\tthis.EncodeSRrri(word_)\n\t} else if this.suffix == S_RRRICI || this.suffix == U_RRRICI {\n\t\tthis.EncodeSRrrici(word_)\n\t} else if this.suffix == RIR {\n\t\tthis.EncodeRir(word_)\n\t} else if this.suffix == RIRC {\n\t\tthis.EncodeRirc(word_)\n\t} else if this.suffix == RIRCI {\n\t\tthis.EncodeRirci(word_)\n\t} else if this.suffix == ZIR {\n\t\tthis.EncodeZir(word_)\n\t} else if this.suffix == ZIRC {\n\t\tthis.EncodeZirc(word_)\n\t} else if this.suffix == ZIRCI {\n\t\tthis.EncodeZirci(word_)\n\t} else if this.suffix == S_RIRC || this.suffix == U_RIRC {\n\t\tthis.EncodeSRirc(word_)\n\t} else if this.suffix == S_RIRCI || this.suffix == U_RIRCI {\n\t\tthis.EncodeSRirci(word_)\n\t} else if this.suffix == R {\n\t\tthis.EncodeR(word_)\n\t} else if this.suffix == RCI {\n\t\tthis.EncodeRci(word_)\n\t} else if this.suffix == Z {\n\t\tthis.EncodeZ(word_)\n\t} else if this.suffix == ZCI {\n\t\tthis.EncodeZci(word_)\n\t} else if this.suffix == S_R || this.suffix == U_R {\n\t\tthis.EncodeSR(word_)\n\t} else if this.suffix == S_RCI || this.suffix == U_RCI {\n\t\tthis.EncodeSRci(word_)\n\t} else if this.suffix == CI {\n\t\tthis.EncodeCi(word_)\n\t} else if this.suffix == I {\n\t\tthis.EncodeI(word_)\n\t} else if this.suffix == DDCI {\n\t\tthis.EncodeDdci(word_)\n\t} else if this.suffix == ERRI {\n\t\tthis.EncodeErri(word_)\n\t} else if this.suffix == S_ERRI || this.suffix == U_ERRI {\n\t\tthis.EncodeSErri(word_)\n\t} else if this.suffix == EDRI {\n\t\tthis.EncodeEdri(word_)\n\t} else if this.suffix == ERII {\n\t\tthis.EncodeErii(word_)\n\t} else if this.suffix == ERIR {\n\t\tthis.EncodeErir(word_)\n\t} else if this.suffix == ERID {\n\t\tthis.EncodeErid(word_)\n\t} else if this.suffix == DMA_RRI {\n\t\tthis.EncodeDmaRri(word_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn word_.ToByteStream()\n}\n\nfunc (this *Instruction) EncodeRici(word_ *word.Word) {\n\tif _, found := this.RiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.pc.Width()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeRric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeRrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeZric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeZrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRI && this.suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeSRric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIC && this.suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRICI && this.suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIF && this.suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeSRrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRC && this.suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRCI && this.suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeRrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeZrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RR && this.suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeSRrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRC && this.suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRCI && this.suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeDrdici(word_ *word.Word) {\n\tif _, found := this.DrdiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tdb_begin := ra_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n\n\timm_begin := db_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeRrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeZrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRI && this.suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeSRrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRICI && this.suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRir(word_ *word.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeRirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZir(word_ *word.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeZirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRC && this.suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRCI && this.suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeR(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != R {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n}\n\nfunc (this *Instruction) EncodeRci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RCI {\n\t\terr := errors.New(\"suffix is not RCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tcondition_begin := rc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZ(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found && this.op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != Z {\n\t\terr := errors.New(\"suffix is not Z\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) EncodeZci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZCI {\n\t\terr := errors.New(\"suffix is not ZCI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSR(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_R && this.suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n}\n\nfunc (this *Instruction) EncodeSRci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RCI && this.suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tcondition_begin := dc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeCi(word_ *word.Word) {\n\tif _, found := this.CiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeI(word_ *word.Word) {\n\tif _, found := this.IOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != I {\n\t\terr := errors.New(\"suffix is not I\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeDdci(word_ *word.Word) {\n\tif _, found := this.DdciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tdb_begin := dc_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n\n\tcondition_begin := db_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeErri(word_ *word.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\trc_begin := endian_end\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeSErri(word_ *word.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_ERRI && this.suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeEdri(word_ *word.Word) {\n\tif _, found := this.EdriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeErii(word_ *word.Word) {\n\tif _, found := this.EriiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\timm_begin := off_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeErir(word_ *word.Word) {\n\tif _, found := this.ErirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\trb_begin := off_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeErid(word_ *word.Word) {\n\tif _, found := this.EridOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\tdb_begin := off_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n}\n\nfunc (this *Instruction) EncodeDmaRri(word_ *word.Word) {\n\tif _, found := this.DmaRriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeOpCode(word_ *word.Word) {\n\tword_.SetBitSlice(this.OpCodeBegin(), this.OpCodeEnd(), int64(this.op_code))\n}\n\nfunc (this *Instruction) EncodeSuffix(word_ *word.Word) {\n\tword_.SetBitSlice(this.SuffixBegin(), this.SuffixEnd(), int64(this.suffix))\n}\n\nfunc (this *Instruction) EncodeGpRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n) {\n\tword_.SetBitSlice(begin, end, int64(gp_reg_descriptor.Index()))\n}\n\nfunc (this *Instruction) EncodeSrcRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n) {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\tword_.SetBitSlice(begin, end, int64(src_reg_descriptor.GpRegDescriptor().Index()))\n\t} else if src_reg_descriptor.IsSpRegDescriptor() {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tindex := config_loader.NumGpRegisters() + int(*src_reg_descriptor.SpRegDescriptor())\n\t\tword_.SetBitSlice(begin, end, int64(index))\n\t} else {\n\t\terr := errors.New(\"sp reg descriptor is corrupted\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) EncodePairRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n) {\n\tword_.SetBitSlice(begin, end, int64(pair_reg_descriptor.Index()))\n}\n\nfunc (this *Instruction) EncodeImm(word_ *word.Word, begin int, end int, value int64) {\n\tword_.SetBitSlice(begin, end, value)\n}\n\nfunc (this *Instruction) EncodeCondition(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\tcondition cc.Condition,\n) {\n\tword_.SetBitSlice(begin, end, int64(condition))\n}\n\nfunc (this *Instruction) EncodePc(word_ *word.Word, begin int, end int, pc int64) {\n\tthis.EncodeImm(word_, begin, end, pc)\n}\n\nfunc (this *Instruction) EncodeEndian(word_ *word.Word, begin int, end int, endian Endian) {\n\tword_.SetBitSlice(begin, end, int64(endian))\n}\n\nfunc (this *Instruction) EncodeOff(word_ *word.Word, begin int, end int, value int64) {\n\tthis.EncodeImm(word_, begin, end, value)\n}\n\nfunc (this *Instruction) Decode(byte_stream *encoding.ByteStream) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tword_ := new(word.Word)\n\tword_.Init(config_loader.IramDataWidth())\n\tword_.FromByteStream(byte_stream)\n\n\tthis.op_code = this.DecodeOpCode(word_)\n\tthis.suffix = this.DecodeSuffix(word_)\n\n\tif this.suffix == RICI {\n\t\tthis.DecodeRici(word_)\n\t} else if this.suffix == RRI {\n\t\tthis.DecodeRri(word_)\n\t} else if this.suffix == RRIC {\n\t\tthis.DecodeRric(word_)\n\t} else if this.suffix == RRICI {\n\t\tthis.DecodeRrici(word_)\n\t} else if this.suffix == RRIF {\n\t\tthis.DecodeRrif(word_)\n\t} else if this.suffix == RRR {\n\t\tthis.DecodeRrr(word_)\n\t} else if this.suffix == RRRC {\n\t\tthis.DecodeRrrc(word_)\n\t} else if this.suffix == RRRCI {\n\t\tthis.DecodeRrrci(word_)\n\t} else if this.suffix == ZRI {\n\t\tthis.DecodeZri(word_)\n\t} else if this.suffix == ZRIC {\n\t\tthis.DecodeZric(word_)\n\t} else if this.suffix == ZRICI {\n\t\tthis.DecodeZrici(word_)\n\t} else if this.suffix == ZRIF {\n\t\tthis.DecodeZrif(word_)\n\t} else if this.suffix == ZRR {\n\t\tthis.DecodeZrr(word_)\n\t} else if this.suffix == ZRRC {\n\t\tthis.DecodeZrrc(word_)\n\t} else if this.suffix == ZRRCI {\n\t\tthis.DecodeZrrci(word_)\n\t} else if this.suffix == S_RRI || this.suffix == U_RRI {\n\t\tthis.DecodeSRri(word_)\n\t} else if this.suffix == S_RRIC || this.suffix == U_RRIC {\n\t\tthis.DecodeSRric(word_)\n\t} else if this.suffix == S_RRICI || this.suffix == U_RRICI {\n\t\tthis.DecodeSRrici(word_)\n\t} else if this.suffix == S_RRIF || this.suffix == U_RRIF {\n\t\tthis.DecodeSRrif(word_)\n\t} else if this.suffix == S_RRR || this.suffix == U_RRR {\n\t\tthis.DecodeSRrr(word_)\n\t} else if this.suffix == S_RRRC || this.suffix == U_RRRC {\n\t\tthis.DecodeSRrrc(word_)\n\t} else if this.suffix == S_RRRCI || this.suffix == U_RRRCI {\n\t\tthis.DecodeSRrrci(word_)\n\t} else if this.suffix == RR {\n\t\tthis.DecodeRr(word_)\n\t} else if this.suffix == RRC {\n\t\tthis.DecodeRrc(word_)\n\t} else if this.suffix == RRCI {\n\t\tthis.DecodeRrci(word_)\n\t} else if this.suffix == ZR {\n\t\tthis.DecodeZr(word_)\n\t} else if this.suffix == ZRC {\n\t\tthis.DecodeZrc(word_)\n\t} else if this.suffix == ZRCI {\n\t\tthis.DecodeZrci(word_)\n\t} else if this.suffix == S_RR || this.suffix == U_RR {\n\t\tthis.DecodeSRr(word_)\n\t} else if this.suffix == S_RRC || this.suffix == U_RRC {\n\t\tthis.DecodeSRrc(word_)\n\t} else if this.suffix == S_RRCI || this.suffix == U_RRCI {\n\t\tthis.DecodeSRrci(word_)\n\t} else if this.suffix == DRDICI {\n\t\tthis.DecodeDrdici(word_)\n\t} else if this.suffix == RRRI {\n\t\tthis.DecodeRrri(word_)\n\t} else if this.suffix == RRRICI {\n\t\tthis.DecodeRrrici(word_)\n\t} else if this.suffix == ZRRI {\n\t\tthis.DecodeZrri(word_)\n\t} else if this.suffix == ZRRICI {\n\t\tthis.DecodeZrrici(word_)\n\t} else if this.suffix == S_RRRI || this.suffix == U_RRRI {\n\t\tthis.DecodeSRrri(word_)\n\t} else if this.suffix == S_RRRICI || this.suffix == U_RRRICI {\n\t\tthis.DecodeSRrrici(word_)\n\t} else if this.suffix == RIR {\n\t\tthis.DecodeRir(word_)\n\t} else if this.suffix == RIRC {\n\t\tthis.DecodeRirc(word_)\n\t} else if this.suffix == RIRCI {\n\t\tthis.DecodeRirci(word_)\n\t} else if this.suffix == ZIR {\n\t\tthis.DecodeZir(word_)\n\t} else if this.suffix == ZIRC {\n\t\tthis.DecodeZirc(word_)\n\t} else if this.suffix == ZIRCI {\n\t\tthis.DecodeZirci(word_)\n\t} else if this.suffix == S_RIRC || this.suffix == U_RIRC {\n\t\tthis.DecodeSRirc(word_)\n\t} else if this.suffix == S_RIRCI || this.suffix == U_RIRCI {\n\t\tthis.DecodeSRirci(word_)\n\t} else if this.suffix == R {\n\t\tthis.DecodeR(word_)\n\t} else if this.suffix == RCI {\n\t\tthis.DecodeRci(word_)\n\t} else if this.suffix == Z {\n\t\tthis.DecodeZ(word_)\n\t} else if this.suffix == ZCI {\n\t\tthis.DecodeZci(word_)\n\t} else if this.suffix == S_R || this.suffix == U_R {\n\t\tthis.DecodeSR(word_)\n\t} else if this.suffix == S_RCI || this.suffix == U_RCI {\n\t\tthis.DecodeSRci(word_)\n\t} else if this.suffix == CI {\n\t\tthis.DecodeCi(word_)\n\t} else if this.suffix == I {\n\t\tthis.DecodeI(word_)\n\t} else if this.suffix == DDCI {\n\t\tthis.DecodeDdci(word_)\n\t} else if this.suffix == ERRI {\n\t\tthis.DecodeErri(word_)\n\t} else if this.suffix == S_ERRI || this.suffix == U_ERRI {\n\t\tthis.DecodeSErri(word_)\n\t} else if this.suffix == EDRI {\n\t\tthis.DecodeEdri(word_)\n\t} else if this.suffix == ERII {\n\t\tthis.DecodeErii(word_)\n\t} else if this.suffix == ERIR {\n\t\tthis.DecodeErir(word_)\n\t} else if this.suffix == ERID {\n\t\tthis.DecodeErid(word_)\n\t} else if this.suffix == DMA_RRI {\n\t\tthis.DecodeDmaRri(word_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeRici(word_ *word.Word) {\n\tif _, found := this.RiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 16\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 16, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tcondition := this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = condition\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.SIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeRric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeRrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 28\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 28, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeZric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 27\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 27, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 27\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 27, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 11, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIF {\n\t\terr := errors.New(\"suffix is not ZRIF\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 27\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 27, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRR {\n\t\terr := errors.New(\"suffix is not ZRR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeZrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRri(word_ *word.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRI && this.suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeSRric(word_ *word.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIC && this.suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrici(word_ *word.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRICI && this.suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\t\tthis.imm = new(word.Immediate)\n\t\tthis.imm.Init(word.SIGNED, 8, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRrif(word_ *word.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIF && this.suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrr(word_ *word.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeSRrrc(word_ *word.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRC && this.suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrrci(word_ *word.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRCI && this.suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeRrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeZrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRC {\n\t\terr := errors.New(\"suffix is not ZRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRr(word_ *word.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RR && this.suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeSRrc(word_ *word.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRC && this.suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrci(word_ *word.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRCI && this.suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeDrdici(word_ *word.Word) {\n\tif _, found := this.DrdiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tdb_begin := ra_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n\n\timm_begin := db_end\n\timm_end := imm_begin + 5\n\timm := this.DecodePc(word_, imm_begin, imm_end)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeRrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeZrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRrri(word_ *word.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRI && this.suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeSRrrici(word_ *word.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRICI && this.suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRir(word_ *word.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 32\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeRirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZir(word_ *word.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 32\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 32, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeZirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRirc(word_ *word.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRC && this.suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRirci(word_ *word.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRCI && this.suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeR(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != R {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n}\n\nfunc (this *Instruction) DecodeRci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RCI {\n\t\terr := errors.New(\"suffix is not RCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tcondition_begin := rc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZ(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found && this.op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != Z {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeZci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZCI {\n\t\terr := errors.New(\"suffix is not ZCI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSR(word_ *word.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_R && this.suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n}\n\nfunc (this *Instruction) DecodeSRci(word_ *word.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RCI && this.suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tcondition_begin := dc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeCi(word_ *word.Word) {\n\tif _, found := this.CiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeI(word_ *word.Word) {\n\tif _, found := this.IOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != I {\n\t\terr := errors.New(\"suffix is not I\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 24, imm)\n}\n\nfunc (this *Instruction) DecodeDdci(word_ *word.Word) {\n\tif _, found := this.DdciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tdb_begin := dc_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n\n\tcondition_begin := db_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, word.UNSIGNED)\n\n\tthis.pc = new(word.Immediate)\n\tthis.pc.Init(word.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeErri(word_ *word.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\trc_begin := endian_end\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeSErri(word_ *word.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_ERRI && this.suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeEdri(word_ *word.Word) {\n\tif _, found := this.EdriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeErii(word_ *word.Word) {\n\tif _, found := this.EriiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\timm_begin := off_end\n\timm_end := imm_begin + 16\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.SIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.SIGNED, 16, imm)\n}\n\nfunc (this *Instruction) DecodeErir(word_ *word.Word) {\n\tif _, found := this.ErirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\trb_begin := off_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeErid(word_ *word.Word) {\n\tif _, found := this.EridOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, word.SIGNED)\n\n\tthis.off = new(word.Immediate)\n\tthis.off.Init(word.SIGNED, 24, off)\n\n\tdb_begin := off_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n}\n\nfunc (this *Instruction) DecodeDmaRri(word_ *word.Word) {\n\tif _, found := this.DmaRriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, word.UNSIGNED)\n\n\tthis.imm = new(word.Immediate)\n\tthis.imm.Init(word.UNSIGNED, 8, imm)\n}\n\nfunc (this *Instruction) DecodeOpCode(word_ *word.Word) OpCode {\n\treturn OpCode(word_.BitSlice(word.UNSIGNED, this.OpCodeBegin(), this.OpCodeEnd()))\n}\n\nfunc (this *Instruction) DecodeSuffix(word_ *word.Word) Suffix {\n\treturn Suffix(word_.BitSlice(word.UNSIGNED, this.SuffixBegin(), this.SuffixEnd()))\n}\n\nfunc (this *Instruction) DecodeGpRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.GpRegDescriptor {\n\tindex := int(word_.BitSlice(word.UNSIGNED, begin, end))\n\n\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\tgp_reg_descriptor.Init(index)\n\n\treturn gp_reg_descriptor\n}\n\nfunc (this *Instruction) DecodeSrcRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.SrcRegDescriptor {\n\tindex := int(word_.BitSlice(word.UNSIGNED, begin, end))\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif index < config_loader.NumGpRegisters() {\n\t\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\t\tgp_reg_descriptor.Init(index)\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitGpRegDescriptor(gp_reg_descriptor)\n\n\t\treturn src_reg_descriptor\n\t} else {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.SpRegDescriptor(index - config_loader.NumGpRegisters())\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\n\t\treturn src_reg_descriptor\n\t}\n}\n\nfunc (this *Instruction) DecodePairRegDescriptor(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.PairRegDescriptor {\n\tindex := int(word_.BitSlice(word.UNSIGNED, begin, end))\n\n\tpair_reg_descriptor := new(reg_descriptor.PairRegDescriptor)\n\tpair_reg_descriptor.Init(index)\n\n\treturn pair_reg_descriptor\n}\n\nfunc (this *Instruction) DecodeImm(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\trepresentation word.Representation,\n) int64 {\n\treturn word_.BitSlice(representation, begin, end)\n}\n\nfunc (this *Instruction) DecodeCondition(word_ *word.Word, begin int, end int) cc.Condition {\n\treturn cc.Condition(word_.BitSlice(word.UNSIGNED, begin, end))\n}\n\nfunc (this *Instruction) DecodePc(word_ *word.Word, begin int, end int) int64 {\n\treturn this.DecodeImm(word_, begin, end, word.UNSIGNED)\n}\n\nfunc (this *Instruction) DecodeEndian(word_ *word.Word, begin int, end int) Endian {\n\treturn Endian(word_.BitSlice(word.UNSIGNED, begin, end))\n}\n\nfunc (this *Instruction) DecodeOff(\n\tword_ *word.Word,\n\tbegin int,\n\tend int,\n\trepresentation word.Representation,\n) int64 {\n\treturn this.DecodeImm(word_, begin, end, representation)\n}\n\nfunc (this *Instruction) OpCodeBegin() int {\n\treturn 0\n}\n\nfunc (this *Instruction) OpCodeEnd() int {\n\treturn this.OpCodeBegin() + this.OpCodeWidth()\n}\n\nfunc (this *Instruction) OpCodeWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(SDMA))))\n}\n\nfunc (this *Instruction) SuffixBegin() int {\n\treturn this.OpCodeEnd()\n}\n\nfunc (this *Instruction) SuffixEnd() int {\n\treturn this.SuffixBegin() + this.SuffixWidth()\n}\n\nfunc (this *Instruction) SuffixWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(DMA_RRI))))\n}\n\nfunc (this *Instruction) RegisterWidth() int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\treturn int(\n\t\tmath.Ceil(\n\t\t\tmath.Log2(float64(config_loader.NumGpRegisters()) + 1.0 + float64(reg_descriptor.ID8)),\n\t\t),\n\t)\n}\n\nfunc (this *Instruction) ConditionWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(cc.LARGE))))\n}\n\nfunc (this *Instruction) PcWidth() int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\treturn config_loader.AddressWidth()\n}\n\nfunc (this *Instruction) EndianWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(BIG))))\n}\n\nfunc (this *Instruction) AcquireRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tACQUIRE: true,\n\t}\n}\n\nfunc (this *Instruction) ReleaseRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRELEASE: true,\n\t}\n}\n\nfunc (this *Instruction) BootRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tBOOT:   true,\n\t\tRESUME: true,\n\t}\n}\n\nfunc (this *Instruction) RiciOpCodes() map[OpCode]bool {\n\tacquire_rici_op_codes := this.AcquireRiciOpCodes()\n\trelease_rici_op_codes := this.ReleaseRiciOpCodes()\n\tboot_rici_op_codes := this.BootRiciOpCodes()\n\n\trici_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range acquire_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\tfor k, v := range release_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\tfor k, v := range boot_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\treturn rici_op_codes\n}\n\nfunc (this *Instruction) AddRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tOR:   true,\n\t\tXOR:  true,\n\t}\n}\n\nfunc (this *Instruction) AsrRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) CallRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCALL: true,\n\t}\n}\n\nfunc (this *Instruction) RriOpCodes() map[OpCode]bool {\n\tadd_rri_op_codes := this.AddRriOpCodes()\n\tasr_rri_op_codes := this.AsrRriOpCodes()\n\tcall_rri_op_codes := this.CallRriOpCodes()\n\n\trri_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range add_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\tfor k, v := range call_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\treturn rri_op_codes\n}\n\nfunc (this *Instruction) AddRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) SubRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RricOpCodes() map[OpCode]bool {\n\tadd_rric_op_codes := this.AddRricOpCodes()\n\tasr_rric_op_codes := this.AsrRricOpCodes()\n\tsub_rric_op_codes := this.SubRricOpCodes()\n\n\trric_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range add_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\treturn rric_op_codes\n}\n\nfunc (this *Instruction) AddRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t}\n}\n\nfunc (this *Instruction) AndRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) SubRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RriciOpCodes() map[OpCode]bool {\n\tadd_rrici_op_codes := this.AddRriciOpCodes()\n\tand_rrici_op_codes := this.AndRriciOpCodes()\n\tasr_rrici_op_codes := this.AsrRriciOpCodes()\n\tsub_rrici_op_codes := this.SubRriciOpCodes()\n\n\trrici_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range add_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range and_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\treturn rrici_op_codes\n}\n\nfunc (this *Instruction) RrifOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) RrrOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:       true,\n\t\tADDC:      true,\n\t\tAND:       true,\n\t\tANDN:      true,\n\t\tASR:       true,\n\t\tCMPB4:     true,\n\t\tLSL:       true,\n\t\tLSL1:      true,\n\t\tLSL1X:     true,\n\t\tLSLX:      true,\n\t\tLSR:       true,\n\t\tLSR1:      true,\n\t\tLSR1X:     true,\n\t\tLSRX:      true,\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t\tNAND:      true,\n\t\tNOR:       true,\n\t\tNXOR:      true,\n\t\tOR:        true,\n\t\tORN:       true,\n\t\tROL:       true,\n\t\tROR:       true,\n\t\tRSUB:      true,\n\t\tRSUBC:     true,\n\t\tSUB:       true,\n\t\tSUBC:      true,\n\t\tXOR:       true,\n\t\tHASH:      true,\n\t\tCALL:      true,\n\t}\n}\n\nfunc (this *Instruction) AddRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:       true,\n\t\tADDC:      true,\n\t\tAND:       true,\n\t\tANDN:      true,\n\t\tASR:       true,\n\t\tCMPB4:     true,\n\t\tLSL:       true,\n\t\tLSL1:      true,\n\t\tLSL1X:     true,\n\t\tLSLX:      true,\n\t\tLSR:       true,\n\t\tLSR1:      true,\n\t\tLSR1X:     true,\n\t\tLSRX:      true,\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t\tNAND:      true,\n\t\tNOR:       true,\n\t\tNXOR:      true,\n\t\tROL:       true,\n\t\tROR:       true,\n\t\tOR:        true,\n\t\tORN:       true,\n\t\tXOR:       true,\n\t\tHASH:      true,\n\t\tCALL:      true,\n\t}\n}\n\nfunc (this *Instruction) RsubRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRSUB:  true,\n\t\tRSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) SubRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RrrcOpCodes() map[OpCode]bool {\n\tadd_rrrc_op_codes := this.AddRrrcOpCodes()\n\trsub_rrrc_op_codes := this.RsubRrrcOpCodes()\n\tsub_rrrc_op_codes := this.SubRrrcOpCodes()\n\n\trrrc_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range add_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\tfor k, v := range rsub_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\treturn rrrc_op_codes\n}\n\nfunc (this *Instruction) AddRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t}\n}\n\nfunc (this *Instruction) AndRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tCMPB4: true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) MulRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t}\n}\n\nfunc (this *Instruction) RsubRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRSUB:  true,\n\t\tRSUBC: true,\n\t\tSUB:   true,\n\t\tSUBC:  true,\n\t}\n}\n\nfunc (this *Instruction) RrrciOpCodes() map[OpCode]bool {\n\tadd_rrrci_op_codes := this.AddRrrciOpCodes()\n\tand_rrrci_op_codes := this.AndRrrciOpCodes()\n\tasr_rrrci_op_codes := this.AsrRrrciOpCodes()\n\tmul_rrrci_op_codes := this.MulRrrciOpCodes()\n\trsub_rrrci_op_codes := this.RsubRrrciOpCodes()\n\n\trrrci_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range add_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range and_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range mul_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range rsub_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\treturn rrrci_op_codes\n}\n\nfunc (this *Instruction) RrOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO:      true,\n\t\tCLO:      true,\n\t\tCLS:      true,\n\t\tCLZ:      true,\n\t\tEXTSB:    true,\n\t\tEXTSH:    true,\n\t\tEXTUB:    true,\n\t\tEXTUH:    true,\n\t\tSATS:     true,\n\t\tTIME_CFG: true,\n\t}\n}\n\nfunc (this *Instruction) RrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO:   true,\n\t\tCLO:   true,\n\t\tCLS:   true,\n\t\tCLZ:   true,\n\t\tEXTSB: true,\n\t\tEXTSH: true,\n\t\tEXTUB: true,\n\t\tEXTUH: true,\n\t\tSATS:  true,\n\t}\n}\n\nfunc (this *Instruction) CaoRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO: true,\n\t\tCLO: true,\n\t\tCLS: true,\n\t\tCLZ: true,\n\t}\n}\n\nfunc (this *Instruction) ExtsbRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tEXTSB: true,\n\t\tEXTSH: true,\n\t\tEXTUB: true,\n\t\tEXTUH: true,\n\t\tSATS:  true,\n\t}\n}\n\nfunc (this *Instruction) TimeCfgRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME_CFG: true,\n\t}\n}\n\nfunc (this *Instruction) RrciOpCodes() map[OpCode]bool {\n\tcao_rrci_op_codes := this.CaoRrciOpCodes()\n\textsb_rrci_op_codes := this.ExtsbRrciOpCodes()\n\ttime_cfg_rrci_op_codes := this.TimeCfgRrciOpCodes()\n\n\trrci_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range cao_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range extsb_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range time_cfg_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\treturn rrci_op_codes\n}\n\nfunc (this *Instruction) DivStepDrdiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tDIV_STEP: true,\n\t}\n}\n\nfunc (this *Instruction) MulStepDrdiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMUL_STEP: true,\n\t}\n}\n\nfunc (this *Instruction) DrdiciOpCodes() map[OpCode]bool {\n\tdiv_step_drdici_op_codes := this.DivStepDrdiciOpCodes()\n\tmul_step_drdici_op_codes := this.MulStepDrdiciOpCodes()\n\n\tdrdici_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range div_step_drdici_op_codes {\n\t\tdrdici_op_codes[k] = v\n\t}\n\n\tfor k, v := range mul_step_drdici_op_codes {\n\t\tdrdici_op_codes[k] = v\n\t}\n\n\treturn drdici_op_codes\n}\n\nfunc (this *Instruction) RrriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLSL_ADD: true,\n\t\tLSL_SUB: true,\n\t\tLSR_ADD: true,\n\t\tROL_ADD: true,\n\t}\n}\n\nfunc (this *Instruction) RrriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLSL_ADD: true,\n\t\tLSL_SUB: true,\n\t\tLSR_ADD: true,\n\t\tROL_ADD: true,\n\t}\n}\n\nfunc (this *Instruction) RirOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RircOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RirciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) ROpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME: true,\n\t}\n}\n\nfunc (this *Instruction) RciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME: true,\n\t}\n}\n\nfunc (this *Instruction) CiOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSTOP: true,\n\t}\n}\n\nfunc (this *Instruction) IOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tFAULT: true,\n\t}\n}\n\nfunc (this *Instruction) MovdDdciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMOVD: true,\n\t}\n}\n\nfunc (this *Instruction) SwapdDdciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSWAPD: true,\n\t}\n}\n\nfunc (this *Instruction) DdciOpCodes() map[OpCode]bool {\n\tmovd_ddci_op_codes := this.MovdDdciOpCodes()\n\tswapd_ddci_op_codes := this.SwapdDdciOpCodes()\n\n\tddci_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range movd_ddci_op_codes {\n\t\tddci_op_codes[k] = v\n\t}\n\n\tfor k, v := range swapd_ddci_op_codes {\n\t\tddci_op_codes[k] = v\n\t}\n\n\treturn ddci_op_codes\n}\n\nfunc (this *Instruction) ErriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLBS: true,\n\t\tLBU: true,\n\t\tLHS: true,\n\t\tLHU: true,\n\t\tLW:  true,\n\t}\n}\n\nfunc (this *Instruction) EdriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLD: true,\n\t}\n}\n\nfunc (this *Instruction) EriiOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSB:    true,\n\t\tSB_ID: true,\n\t\tSD:    true,\n\t\tSD_ID: true,\n\t\tSH:    true,\n\t\tSH_ID: true,\n\t\tSW:    true,\n\t\tSW_ID: true,\n\t}\n}\n\nfunc (this *Instruction) ErirOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSB: true,\n\t\tSH: true,\n\t\tSW: true,\n\t}\n}\n\nfunc (this *Instruction) EridOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSD: true,\n\t}\n}\n\nfunc (this *Instruction) LdmaDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLDMA: true,\n\t}\n}\n\nfunc (this *Instruction) LdmaiDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLDMAI: true,\n\t}\n}\n\nfunc (this *Instruction) SdmaDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSDMA: true,\n\t}\n}\n\nfunc (this *Instruction) DmaRriOpCodes() map[OpCode]bool {\n\tldma_dma_rri_op_codes := this.LdmaDmaRriOpCodes()\n\tldmai_dma_rri_op_codes := this.LdmaiDmaRriOpCodes()\n\tsdma_dma_rri_op_codes := this.SdmaDmaRriOpCodes()\n\n\tdma_rri_op_codes := make(map[OpCode]bool, 0)\n\n\tfor k, v := range ldma_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\tfor k, v := range ldmai_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\tfor k, v := range sdma_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\treturn dma_rri_op_codes\n}\n\nfunc (this *Instruction) Stringify() string {\n\tstr := this.StringifyOpCode() + \", \"\n\tstr += this.StringifySuffix() + \", \"\n\n\tif this.suffix == RICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == RRIC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRICI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRIF {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == RRRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ZRIC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRIF {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRR {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == ZRRC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRRCI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == S_RRIC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRIF {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == S_RRRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == U_RRIC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRIF {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == U_RRRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == RRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZR {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == ZRC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRCI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == S_RRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == U_RRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == DRDICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRRI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == RRRICI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ZRRICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == S_RRRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == U_RRRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RIR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == RIRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RIRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZIR {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == ZIRC {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZIRCI {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RIRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RIRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RIRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RIRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == R {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc)\n\t} else if this.suffix == RCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == Z {\n\t\tstr = str[:len(str)-2]\n\t} else if this.suffix == ZCI {\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_R {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc)\n\t} else if this.suffix == S_RCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_R {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc)\n\t} else if this.suffix == U_RCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == CI {\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == I {\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == DDCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == S_ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == U_ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == EDRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == ERII {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ERIR {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == ERID {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db)\n\t} else if this.suffix == DMA_RRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn str\n}\n\nfunc (this *Instruction) StringifyOpCode() string {\n\tif this.op_code == ACQUIRE {\n\t\treturn \"acquire\"\n\t} else if this.op_code == RELEASE {\n\t\treturn \"release\"\n\t} else if this.op_code == RELEASE {\n\t\treturn \"release\"\n\t} else if this.op_code == ADD {\n\t\treturn \"add\"\n\t} else if this.op_code == ADDC {\n\t\treturn \"addc\"\n\t} else if this.op_code == AND {\n\t\treturn \"and\"\n\t} else if this.op_code == ANDN {\n\t\treturn \"andn\"\n\t} else if this.op_code == ASR {\n\t\treturn \"asr\"\n\t} else if this.op_code == CAO {\n\t\treturn \"cao\"\n\t} else if this.op_code == CLO {\n\t\treturn \"clo\"\n\t} else if this.op_code == CLS {\n\t\treturn \"cls\"\n\t} else if this.op_code == CLZ {\n\t\treturn \"clz\"\n\t} else if this.op_code == CMPB4 {\n\t\treturn \"cmpb4\"\n\t} else if this.op_code == DIV_STEP {\n\t\treturn \"div_step\"\n\t} else if this.op_code == EXTSB {\n\t\treturn \"extsb\"\n\t} else if this.op_code == EXTSH {\n\t\treturn \"extsh\"\n\t} else if this.op_code == EXTUB {\n\t\treturn \"extub\"\n\t} else if this.op_code == EXTUH {\n\t\treturn \"extuh\"\n\t} else if this.op_code == LSL {\n\t\treturn \"lsl\"\n\t} else if this.op_code == LSL_ADD {\n\t\treturn \"lsl_add\"\n\t} else if this.op_code == LSL_SUB {\n\t\treturn \"lsl_sub\"\n\t} else if this.op_code == LSL1 {\n\t\treturn \"lsl1\"\n\t} else if this.op_code == LSL1X {\n\t\treturn \"lsl1x\"\n\t} else if this.op_code == LSLX {\n\t\treturn \"lslx\"\n\t} else if this.op_code == LSR {\n\t\treturn \"lsr\"\n\t} else if this.op_code == LSR_ADD {\n\t\treturn \"lsr_add\"\n\t} else if this.op_code == LSR1 {\n\t\treturn \"lsr1\"\n\t} else if this.op_code == LSR1X {\n\t\treturn \"lsr1x\"\n\t} else if this.op_code == LSRX {\n\t\treturn \"lsrx\"\n\t} else if this.op_code == MUL_SH_SH {\n\t\treturn \"mul_sh_sh\"\n\t} else if this.op_code == MUL_SH_SL {\n\t\treturn \"mul_sh_sl\"\n\t} else if this.op_code == MUL_SH_UH {\n\t\treturn \"mul_sh_uh\"\n\t} else if this.op_code == MUL_SH_UL {\n\t\treturn \"mul_sh_ul\"\n\t} else if this.op_code == MUL_SL_SH {\n\t\treturn \"mul_sl_sh\"\n\t} else if this.op_code == MUL_SL_SL {\n\t\treturn \"mul_sl_sl\"\n\t} else if this.op_code == MUL_SL_UH {\n\t\treturn \"mul_sl_uh\"\n\t} else if this.op_code == MUL_SL_UL {\n\t\treturn \"mul_sl_ul\"\n\t} else if this.op_code == MUL_STEP {\n\t\treturn \"mul_step\"\n\t} else if this.op_code == MUL_UH_UH {\n\t\treturn \"mul_uh_uh\"\n\t} else if this.op_code == MUL_UH_UL {\n\t\treturn \"mul_uh_ul\"\n\t} else if this.op_code == MUL_UL_UH {\n\t\treturn \"mul_ul_uh\"\n\t} else if this.op_code == MUL_UL_UL {\n\t\treturn \"mul_ul_ul\"\n\t} else if this.op_code == NAND {\n\t\treturn \"nand\"\n\t} else if this.op_code == NOR {\n\t\treturn \"nor\"\n\t} else if this.op_code == NXOR {\n\t\treturn \"nxor\"\n\t} else if this.op_code == OR {\n\t\treturn \"or\"\n\t} else if this.op_code == ORN {\n\t\treturn \"orn\"\n\t} else if this.op_code == ROL {\n\t\treturn \"rol\"\n\t} else if this.op_code == ROL_ADD {\n\t\treturn \"rol_add\"\n\t} else if this.op_code == ROR {\n\t\treturn \"ror\"\n\t} else if this.op_code == RSUB {\n\t\treturn \"rsub\"\n\t} else if this.op_code == RSUBC {\n\t\treturn \"rsubc\"\n\t} else if this.op_code == SUB {\n\t\treturn \"sub\"\n\t} else if this.op_code == SUBC {\n\t\treturn \"subc\"\n\t} else if this.op_code == XOR {\n\t\treturn \"xor\"\n\t} else if this.op_code == BOOT {\n\t\treturn \"boot\"\n\t} else if this.op_code == RESUME {\n\t\treturn \"resume\"\n\t} else if this.op_code == STOP {\n\t\treturn \"stop\"\n\t} else if this.op_code == CALL {\n\t\treturn \"call\"\n\t} else if this.op_code == FAULT {\n\t\treturn \"fault\"\n\t} else if this.op_code == NOP {\n\t\treturn \"nop\"\n\t} else if this.op_code == SATS {\n\t\treturn \"sats\"\n\t} else if this.op_code == MOVD {\n\t\treturn \"movd\"\n\t} else if this.op_code == SWAPD {\n\t\treturn \"swapd\"\n\t} else if this.op_code == HASH {\n\t\treturn \"hash\"\n\t} else if this.op_code == TIME {\n\t\treturn \"time\"\n\t} else if this.op_code == TIME_CFG {\n\t\treturn \"time_cfg\"\n\t} else if this.op_code == LBS {\n\t\treturn \"lbs\"\n\t} else if this.op_code == LBU {\n\t\treturn \"lbu\"\n\t} else if this.op_code == LD {\n\t\treturn \"ld\"\n\t} else if this.op_code == LHS {\n\t\treturn \"lhs\"\n\t} else if this.op_code == LHU {\n\t\treturn \"lhu\"\n\t} else if this.op_code == LW {\n\t\treturn \"lw\"\n\t} else if this.op_code == SB {\n\t\treturn \"sb\"\n\t} else if this.op_code == SB_ID {\n\t\treturn \"sb_id\"\n\t} else if this.op_code == SD {\n\t\treturn \"sd\"\n\t} else if this.op_code == SD_ID {\n\t\treturn \"sd_id\"\n\t} else if this.op_code == SH {\n\t\treturn \"sh\"\n\t} else if this.op_code == SH_ID {\n\t\treturn \"sh_id\"\n\t} else if this.op_code == SW {\n\t\treturn \"sw\"\n\t} else if this.op_code == SW_ID {\n\t\treturn \"sw_id\"\n\t} else if this.op_code == LDMA {\n\t\treturn \"ldma\"\n\t} else if this.op_code == LDMAI {\n\t\treturn \"ldmai\"\n\t} else if this.op_code == SDMA {\n\t\treturn \"sdma\"\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifySuffix() string {\n\tif this.suffix == RICI {\n\t\treturn \"rici\"\n\t} else if this.suffix == RRI {\n\t\treturn \"rri\"\n\t} else if this.suffix == RRIC {\n\t\treturn \"rric\"\n\t} else if this.suffix == RRICI {\n\t\treturn \"rrici\"\n\t} else if this.suffix == RRIF {\n\t\treturn \"rrif\"\n\t} else if this.suffix == RRR {\n\t\treturn \"rrr\"\n\t} else if this.suffix == RRRC {\n\t\treturn \"rrrc\"\n\t} else if this.suffix == RRRCI {\n\t\treturn \"rrrci\"\n\t} else if this.suffix == ZRI {\n\t\treturn \"zri\"\n\t} else if this.suffix == ZRIC {\n\t\treturn \"zric\"\n\t} else if this.suffix == ZRICI {\n\t\treturn \"zrici\"\n\t} else if this.suffix == ZRIF {\n\t\treturn \"zrif\"\n\t} else if this.suffix == ZRR {\n\t\treturn \"zrr\"\n\t} else if this.suffix == ZRRC {\n\t\treturn \"zrrc\"\n\t} else if this.suffix == ZRRCI {\n\t\treturn \"zrrci\"\n\t} else if this.suffix == S_RRI {\n\t\treturn \"s_rri\"\n\t} else if this.suffix == S_RRIC {\n\t\treturn \"s_rric\"\n\t} else if this.suffix == S_RRICI {\n\t\treturn \"s_rrici\"\n\t} else if this.suffix == S_RRIF {\n\t\treturn \"s_rrif\"\n\t} else if this.suffix == S_RRR {\n\t\treturn \"s_rrr\"\n\t} else if this.suffix == S_RRRC {\n\t\treturn \"s_rrrc\"\n\t} else if this.suffix == S_RRRCI {\n\t\treturn \"s_rrrci\"\n\t} else if this.suffix == U_RRI {\n\t\treturn \"u_rri\"\n\t} else if this.suffix == U_RRIC {\n\t\treturn \"u_rric\"\n\t} else if this.suffix == U_RRICI {\n\t\treturn \"u_rrici\"\n\t} else if this.suffix == U_RRIF {\n\t\treturn \"u_rrif\"\n\t} else if this.suffix == U_RRR {\n\t\treturn \"u_rrr\"\n\t} else if this.suffix == U_RRRC {\n\t\treturn \"u_rrrc\"\n\t} else if this.suffix == U_RRRCI {\n\t\treturn \"u_rrrci\"\n\t} else if this.suffix == RR {\n\t\treturn \"rr\"\n\t} else if this.suffix == RRC {\n\t\treturn \"rrc\"\n\t} else if this.suffix == RRCI {\n\t\treturn \"rrci\"\n\t} else if this.suffix == ZR {\n\t\treturn \"zr\"\n\t} else if this.suffix == ZRC {\n\t\treturn \"zrc\"\n\t} else if this.suffix == ZRCI {\n\t\treturn \"zrci\"\n\t} else if this.suffix == S_RR {\n\t\treturn \"s_rr\"\n\t} else if this.suffix == S_RRC {\n\t\treturn \"s_rrc\"\n\t} else if this.suffix == S_RRCI {\n\t\treturn \"s_rrci\"\n\t} else if this.suffix == U_RR {\n\t\treturn \"u_rr\"\n\t} else if this.suffix == U_RRC {\n\t\treturn \"u_rrc\"\n\t} else if this.suffix == U_RRCI {\n\t\treturn \"u_rrci\"\n\t} else if this.suffix == DRDICI {\n\t\treturn \"drdici\"\n\t} else if this.suffix == RRRI {\n\t\treturn \"rrri\"\n\t} else if this.suffix == RRRICI {\n\t\treturn \"rrrici\"\n\t} else if this.suffix == ZRRI {\n\t\treturn \"zrri\"\n\t} else if this.suffix == ZRRICI {\n\t\treturn \"zrrici\"\n\t} else if this.suffix == S_RRRI {\n\t\treturn \"s_rrri\"\n\t} else if this.suffix == S_RRRICI {\n\t\treturn \"s_rrrici\"\n\t} else if this.suffix == U_RRRI {\n\t\treturn \"u_rrri\"\n\t} else if this.suffix == U_RRRICI {\n\t\treturn \"u_rrrici\"\n\t} else if this.suffix == RIR {\n\t\treturn \"rir\"\n\t} else if this.suffix == RIRC {\n\t\treturn \"rirc\"\n\t} else if this.suffix == RIRCI {\n\t\treturn \"rirci\"\n\t} else if this.suffix == ZIR {\n\t\treturn \"zir\"\n\t} else if this.suffix == ZIRC {\n\t\treturn \"zirc\"\n\t} else if this.suffix == ZIRCI {\n\t\treturn \"zirci\"\n\t} else if this.suffix == S_RIRC {\n\t\treturn \"s_zirc\"\n\t} else if this.suffix == S_RIRCI {\n\t\treturn \"s_zirci\"\n\t} else if this.suffix == U_RIRC {\n\t\treturn \"u_zirc\"\n\t} else if this.suffix == U_RIRCI {\n\t\treturn \"u_zirci\"\n\t} else if this.suffix == R {\n\t\treturn \"r\"\n\t} else if this.suffix == RCI {\n\t\treturn \"rci\"\n\t} else if this.suffix == Z {\n\t\treturn \"z\"\n\t} else if this.suffix == ZCI {\n\t\treturn \"zci\"\n\t} else if this.suffix == S_R {\n\t\treturn \"s_r\"\n\t} else if this.suffix == S_RCI {\n\t\treturn \"s_rci\"\n\t} else if this.suffix == U_R {\n\t\treturn \"u_r\"\n\t} else if this.suffix == U_RCI {\n\t\treturn \"u_rci\"\n\t} else if this.suffix == CI {\n\t\treturn \"ci\"\n\t} else if this.suffix == I {\n\t\treturn \"i\"\n\t} else if this.suffix == DDCI {\n\t\treturn \"ddci\"\n\t} else if this.suffix == ERRI {\n\t\treturn \"erri\"\n\t} else if this.suffix == S_ERRI {\n\t\treturn \"s_erri\"\n\t} else if this.suffix == U_ERRI {\n\t\treturn \"u_erri\"\n\t} else if this.suffix == EDRI {\n\t\treturn \"edri\"\n\t} else if this.suffix == ERII {\n\t\treturn \"erii\"\n\t} else if this.suffix == ERIR {\n\t\treturn \"erir\"\n\t} else if this.suffix == ERID {\n\t\treturn \"erid\"\n\t} else if this.suffix == DMA_RRI {\n\t\treturn \"dma_rri\"\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyGpRegDescriptor(\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n) string {\n\treturn \"r\" + strconv.Itoa(gp_reg_descriptor.Index())\n}\n\nfunc (this *Instruction) StringifySrcRegDescriptor(\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n) string {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\treturn this.StringifyGpRegDescriptor(src_reg_descriptor.GpRegDescriptor())\n\t} else {\n\t\tsp_reg_descriptor := src_reg_descriptor.SpRegDescriptor()\n\n\t\tif *sp_reg_descriptor == reg_descriptor.ZERO {\n\t\t\treturn \"zero\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ONE {\n\t\t\treturn \"one\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.LNEG {\n\t\t\treturn \"lneg\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.MNEG {\n\t\t\treturn \"mneg\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID {\n\t\t\treturn \"id\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID2 {\n\t\t\treturn \"id2\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID4 {\n\t\t\treturn \"id4\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID8 {\n\t\t\treturn \"id8\"\n\t\t} else {\n\t\t\terr := errors.New(\"sp reg descriptor is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Instruction) StringifyPairRegDescriptor(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n) string {\n\treturn \"d\" + strconv.Itoa(pair_reg_descriptor.Index())\n}\n\nfunc (this *Instruction) StringifyImm(imm *word.Immediate) string {\n\treturn strconv.FormatInt(imm.Value(), 10)\n}\n\nfunc (this *Instruction) StringifyCondition(condition cc.Condition) string {\n\tif condition == cc.TRUE {\n\t\treturn \"true\"\n\t} else if condition == cc.FALSE {\n\t\treturn \"false\"\n\t} else if condition == cc.Z {\n\t\treturn \"z\"\n\t} else if condition == cc.NZ {\n\t\treturn \"nz\"\n\t} else if condition == cc.E {\n\t\treturn \"e\"\n\t} else if condition == cc.O {\n\t\treturn \"o\"\n\t} else if condition == cc.PL {\n\t\treturn \"pl\"\n\t} else if condition == cc.MI {\n\t\treturn \"mi\"\n\t} else if condition == cc.OV {\n\t\treturn \"ov\"\n\t} else if condition == cc.NOV {\n\t\treturn \"nov\"\n\t} else if condition == cc.C {\n\t\treturn \"c\"\n\t} else if condition == cc.NC {\n\t\treturn \"nc\"\n\t} else if condition == cc.SZ {\n\t\treturn \"sz\"\n\t} else if condition == cc.SNZ {\n\t\treturn \"snz\"\n\t} else if condition == cc.SPL {\n\t\treturn \"spl\"\n\t} else if condition == cc.SMI {\n\t\treturn \"smi\"\n\t} else if condition == cc.SO {\n\t\treturn \"so\"\n\t} else if condition == cc.SE {\n\t\treturn \"se\"\n\t} else if condition == cc.NC5 {\n\t\treturn \"nc5\"\n\t} else if condition == cc.NC6 {\n\t\treturn \"nc6\"\n\t} else if condition == cc.NC7 {\n\t\treturn \"nc7\"\n\t} else if condition == cc.NC8 {\n\t\treturn \"nc8\"\n\t} else if condition == cc.NC9 {\n\t\treturn \"nc9\"\n\t} else if condition == cc.NC10 {\n\t\treturn \"nc10\"\n\t} else if condition == cc.NC11 {\n\t\treturn \"nc11\"\n\t} else if condition == cc.NC12 {\n\t\treturn \"nc12\"\n\t} else if condition == cc.NC13 {\n\t\treturn \"nc13\"\n\t} else if condition == cc.NC14 {\n\t\treturn \"nc14\"\n\t} else if condition == cc.MAX {\n\t\treturn \"max\"\n\t} else if condition == cc.NMAX {\n\t\treturn \"nmax\"\n\t} else if condition == cc.SH32 {\n\t\treturn \"sh32\"\n\t} else if condition == cc.NSH32 {\n\t\treturn \"nsh32\"\n\t} else if condition == cc.EQ {\n\t\treturn \"eq\"\n\t} else if condition == cc.NEQ {\n\t\treturn \"neq\"\n\t} else if condition == cc.LTU {\n\t\treturn \"ltu\"\n\t} else if condition == cc.LEU {\n\t\treturn \"leu\"\n\t} else if condition == cc.GTU {\n\t\treturn \"gtu\"\n\t} else if condition == cc.GEU {\n\t\treturn \"geu\"\n\t} else if condition == cc.LTS {\n\t\treturn \"lts\"\n\t} else if condition == cc.LES {\n\t\treturn \"les\"\n\t} else if condition == cc.GTS {\n\t\treturn \"gts\"\n\t} else if condition == cc.GES {\n\t\treturn \"ges\"\n\t} else if condition == cc.XZ {\n\t\treturn \"xz\"\n\t} else if condition == cc.XNZ {\n\t\treturn \"xnz\"\n\t} else if condition == cc.XLEU {\n\t\treturn \"xleu\"\n\t} else if condition == cc.XGTU {\n\t\treturn \"xgtu\"\n\t} else if condition == cc.XLES {\n\t\treturn \"xles\"\n\t} else if condition == cc.XGTS {\n\t\treturn \"xgts\"\n\t} else if condition == cc.SMALL {\n\t\treturn \"small\"\n\t} else if condition == cc.LARGE {\n\t\treturn \"large\"\n\t} else {\n\t\terr := errors.New(\"condition is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyEndian(endian Endian) string {\n\tif endian == LITTLE {\n\t\treturn \"!little\"\n\t} else if endian == BIG {\n\t\treturn \"!big\"\n\t} else {\n\t\terr := errors.New(\"endian is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyOff(off *word.Immediate) string {\n\treturn strconv.FormatInt(off.Value(), 10)\n}\n\nfunc (this *Instruction) StringifyPc(pc *word.Immediate) string {\n\treturn strconv.FormatInt(pc.Value(), 10)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/op_code.go",
    "content": "package instruction\n\ntype OpCode int\n\nconst (\n\tACQUIRE OpCode = iota\n\tRELEASE\n\n\tADD\n\tADDC\n\tAND\n\tANDN\n\tASR\n\tCAO\n\tCLO\n\tCLS\n\tCLZ\n\tCMPB4\n\tDIV_STEP\n\tEXTSB\n\tEXTSH\n\tEXTUB\n\tEXTUH\n\tLSL\n\tLSL_ADD\n\tLSL_SUB\n\tLSL1\n\tLSL1X\n\tLSLX\n\tLSR\n\tLSR_ADD\n\tLSR1\n\tLSR1X\n\tLSRX\n\tMUL_SH_SH\n\tMUL_SH_SL\n\tMUL_SH_UH\n\tMUL_SH_UL\n\tMUL_SL_SH\n\tMUL_SL_SL\n\tMUL_SL_UH\n\tMUL_SL_UL\n\tMUL_STEP\n\tMUL_UH_UH\n\tMUL_UH_UL\n\tMUL_UL_UH\n\tMUL_UL_UL\n\tNAND\n\tNOR\n\tNXOR\n\tOR\n\tORN\n\tROL\n\tROL_ADD\n\tROR\n\tRSUB\n\tRSUBC\n\tSUB\n\tSUBC\n\tXOR\n\n\tBOOT\n\tRESUME\n\tSTOP\n\n\tCALL\n\n\tFAULT\n\tNOP\n\tSATS\n\tMOVD\n\tSWAPD\n\n\tHASH\n\tTIME\n\tTIME_CFG\n\n\tLBS\n\tLBU\n\tLD\n\tLHS\n\tLHU\n\tLW\n\n\tSB\n\tSB_ID\n\tSD\n\tSD_ID\n\tSH\n\tSH_ID\n\tSW\n\tSW_ID\n\n\tLDMA\n\tLDMAI\n\tSDMA\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/reg_descriptor/gp_reg_descriptor.go",
    "content": "package reg_descriptor\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype GpRegDescriptor struct {\n\tindex int\n}\n\nfunc (this *GpRegDescriptor) Init(index int) {\n\tif index < 0 {\n\t\terr := errors.New(\"index < 0\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif index >= config_loader.NumGpRegisters() {\n\t\terr := errors.New(\"index >= num gp registers\")\n\t\tpanic(err)\n\t}\n\n\tthis.index = index\n}\n\nfunc (this *GpRegDescriptor) Index() int {\n\treturn this.index\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/reg_descriptor/pair_reg_descriptor.go",
    "content": "package reg_descriptor\n\nimport (\n\t\"errors\"\n)\n\ntype PairRegDescriptor struct {\n\teven_reg_descriptor *GpRegDescriptor\n\todd_reg_descriptor  *GpRegDescriptor\n}\n\nfunc (this *PairRegDescriptor) Init(index int) {\n\tif index%2 != 0 {\n\t\terr := errors.New(\"index %2 != 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.even_reg_descriptor = new(GpRegDescriptor)\n\tthis.even_reg_descriptor.Init(index)\n\n\tthis.odd_reg_descriptor = new(GpRegDescriptor)\n\tthis.odd_reg_descriptor.Init(index + 1)\n}\n\nfunc (this *PairRegDescriptor) Index() int {\n\treturn this.even_reg_descriptor.Index()\n}\n\nfunc (this *PairRegDescriptor) EvenRegDescriptor() *GpRegDescriptor {\n\treturn this.even_reg_descriptor\n}\n\nfunc (this *PairRegDescriptor) OddRegDescriptor() *GpRegDescriptor {\n\treturn this.odd_reg_descriptor\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/reg_descriptor/sp_reg_descriptor.go",
    "content": "package reg_descriptor\n\ntype SpRegDescriptor int\n\nconst (\n\tZERO SpRegDescriptor = iota\n\tONE\n\tLNEG\n\tMNEG\n\tID\n\tID2\n\tID4\n\tID8\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/reg_descriptor/src_reg_descriptor.go",
    "content": "package reg_descriptor\n\ntype SrcRegDescriptor struct {\n\tgp_reg_descriptor *GpRegDescriptor\n\tsp_reg_descriptor *SpRegDescriptor\n}\n\nfunc (this *SrcRegDescriptor) InitGpRegDescriptor(gp_reg_descriptor *GpRegDescriptor) {\n\tthis.gp_reg_descriptor = gp_reg_descriptor\n\tthis.sp_reg_descriptor = nil\n}\n\nfunc (this *SrcRegDescriptor) InitSpRegDescriptor(sp_reg_descriptor *SpRegDescriptor) {\n\tthis.gp_reg_descriptor = nil\n\tthis.sp_reg_descriptor = sp_reg_descriptor\n}\n\nfunc (this *SrcRegDescriptor) IsGpRegDescriptor() bool {\n\treturn this.gp_reg_descriptor != nil\n}\n\nfunc (this *SrcRegDescriptor) IsSpRegDescriptor() bool {\n\treturn this.sp_reg_descriptor != nil\n}\n\nfunc (this *SrcRegDescriptor) GpRegDescriptor() *GpRegDescriptor {\n\treturn this.gp_reg_descriptor\n}\n\nfunc (this *SrcRegDescriptor) SpRegDescriptor() *SpRegDescriptor {\n\treturn this.sp_reg_descriptor\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/instruction/suffix.go",
    "content": "package instruction\n\ntype Suffix int\n\nconst (\n\tRICI Suffix = iota\n\n\tRRI\n\tRRIC\n\tRRICI\n\tRRIF\n\tRRR\n\tRRRC\n\tRRRCI\n\n\tZRI\n\tZRIC\n\tZRICI\n\tZRIF\n\tZRR\n\tZRRC\n\tZRRCI\n\n\tS_RRI\n\tS_RRIC\n\tS_RRICI\n\tS_RRIF\n\tS_RRR\n\tS_RRRC\n\tS_RRRCI\n\n\tU_RRI\n\tU_RRIC\n\tU_RRICI\n\tU_RRIF\n\tU_RRR\n\tU_RRRC\n\tU_RRRCI\n\n\tRR\n\tRRC\n\tRRCI\n\n\tZR\n\tZRC\n\tZRCI\n\n\tS_RR\n\tS_RRC\n\tS_RRCI\n\n\tU_RR\n\tU_RRC\n\tU_RRCI\n\n\tDRDICI\n\n\tRRRI\n\tRRRICI\n\n\tZRRI\n\tZRRICI\n\n\tS_RRRI\n\tS_RRRICI\n\n\tU_RRRI\n\tU_RRRICI\n\n\tRIR\n\tRIRC\n\tRIRCI\n\n\tZIR\n\tZIRC\n\tZIRCI\n\n\tS_RIRC\n\tS_RIRCI\n\n\tU_RIRC\n\tU_RIRCI\n\n\tR\n\tRCI\n\n\tZ\n\tZCI\n\n\tS_R\n\tS_RCI\n\n\tU_R\n\tU_RCI\n\n\tCI\n\tI\n\n\tDDCI\n\n\tERRI\n\n\tS_ERRI\n\tU_ERRI\n\n\tEDRI\n\n\tERII\n\tERIR\n\tERID\n\n\tDMA_RRI\n)\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/kernel.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype Kernel struct {\n\taddresses map[string]int64\n\n\tatomic *encoding.ByteStream\n\tiram   *encoding.ByteStream\n\twram   *encoding.ByteStream\n\tmram   *encoding.ByteStream\n}\n\nfunc (this *Kernel) Init() {\n\tthis.addresses = make(map[string]int64, 0)\n}\n\nfunc (this *Kernel) Address(label_name string) int64 {\n\tif address, found := this.addresses[label_name]; found {\n\t\treturn address\n\t} else {\n\t\terr := errors.New(\"address is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Kernel) Atomic() *encoding.ByteStream {\n\treturn this.atomic\n}\n\nfunc (this *Kernel) SetAtomic(atomic *encoding.ByteStream) {\n\tthis.atomic = atomic\n}\n\nfunc (this *Kernel) Iram() *encoding.ByteStream {\n\treturn this.iram\n}\n\nfunc (this *Kernel) SetIram(iram *encoding.ByteStream) {\n\tthis.iram = iram\n}\n\nfunc (this *Kernel) Wram() *encoding.ByteStream {\n\treturn this.wram\n}\n\nfunc (this *Kernel) SetWram(wram *encoding.ByteStream) {\n\tthis.wram = wram\n}\n\nfunc (this *Kernel) Mram() *encoding.ByteStream {\n\treturn this.mram\n}\n\nfunc (this *Kernel) SetMram(mram *encoding.ByteStream) {\n\tthis.mram = mram\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/label.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype Label struct {\n\tname        string\n\taddress     *int64\n\tsize        int64\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Label) Init(name string) {\n\tthis.name = name\n\tthis.address = nil\n\tthis.size = 0\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n}\n\nfunc (this *Label) Name() string {\n\treturn this.name\n}\n\nfunc (this *Label) Address() int64 {\n\tif this.address == nil {\n\t\terr := errors.New(\"address is not yet set\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.address\n}\n\nfunc (this *Label) BeginAddress() int64 {\n\treturn this.Address()\n}\n\nfunc (this *Label) EndAddress() int64 {\n\treturn this.Address() + this.Size()\n}\n\nfunc (this *Label) SetAddress(address int64) {\n\tif this.address != nil {\n\t\terr := errors.New(\"address is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.address = new(int64)\n\t*this.address = address\n}\n\nfunc (this *Label) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Label) SetSize(size int64) {\n\tthis.size = size\n}\n\nfunc (this *Label) ToByteStream() *encoding.ByteStream {\n\tif this.size != this.byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\treturn this.byte_stream\n}\n\nfunc (this *Label) Append(encodable Encodable) {\n\tthis.byte_stream.Merge(encodable.Encode())\n\n\tif this.byte_stream.Size() > this.size {\n\t\terr := errors.New(\"byte stream's size > size\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/liveness.go",
    "content": "package kernel\n\ntype Liveness struct {\n\tdefs           map[string]bool\n\tuses           map[string]bool\n\tglobal_symbols map[string]bool\n}\n\nfunc (this *Liveness) Init() {\n\tthis.defs = make(map[string]bool, 0)\n\tthis.uses = make(map[string]bool, 0)\n\tthis.global_symbols = make(map[string]bool, 0)\n}\n\nfunc (this *Liveness) Defs() map[string]bool {\n\treturn this.defs\n}\n\nfunc (this *Liveness) AddDef(def string) {\n\tthis.defs[def] = true\n}\n\nfunc (this *Liveness) Uses() map[string]bool {\n\treturn this.uses\n}\n\nfunc (this *Liveness) AddUse(use string) {\n\tthis.uses[use] = true\n}\n\nfunc (this *Liveness) GlobalSymbols() map[string]bool {\n\treturn this.global_symbols\n}\n\nfunc (this *Liveness) AddGlobalSymbol(global_symbol string) {\n\tthis.global_symbols[global_symbol] = true\n}\n\nfunc (this *Liveness) LocalSymbols() map[string]bool {\n\tlocal_symbols := make(map[string]bool, 0)\n\tfor def, _ := range this.defs {\n\t\tif _, found := this.global_symbols[def]; !found {\n\t\t\tlocal_symbols[def] = true\n\t\t}\n\t}\n\treturn local_symbols\n}\n\nfunc (this *Liveness) UnresolvedSymbols() map[string]bool {\n\tunresolved_symbols := make(map[string]bool, 0)\n\tfor use, _ := range this.uses {\n\t\tif _, found := this.defs[use]; !found {\n\t\t\tunresolved_symbols[use] = true\n\t\t}\n\t}\n\treturn unresolved_symbols\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/relocatable.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"strings\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Relocatable struct {\n\tname string\n\tpath string\n\n\ttoken_stream *lexer.TokenStream\n\tast          *parser.Ast\n\tliveness     *Liveness\n\n\trenames map[string]string\n}\n\nfunc (this *Relocatable) Init(name string) {\n\tthis.name = name\n\n\tthis.renames = make(map[string]string, 0)\n}\n\nfunc (this *Relocatable) Name() string {\n\treturn this.name\n}\n\nfunc (this *Relocatable) Path() string {\n\treturn this.path\n}\n\nfunc (this *Relocatable) SetPath(path string) {\n\tthis.path = path\n}\n\nfunc (this *Relocatable) TokenStream() *lexer.TokenStream {\n\treturn this.token_stream\n}\n\nfunc (this *Relocatable) SetTokenStream(token_stream *lexer.TokenStream) {\n\tthis.token_stream = token_stream\n}\n\nfunc (this *Relocatable) Ast() *parser.Ast {\n\treturn this.ast\n}\n\nfunc (this *Relocatable) SetAst(ast *parser.Ast) {\n\tthis.ast = ast\n}\n\nfunc (this *Relocatable) Liveness() *Liveness {\n\treturn this.liveness\n}\n\nfunc (this *Relocatable) SetLiveness(liveness *Liveness) {\n\tthis.liveness = liveness\n}\n\nfunc (this *Relocatable) Lines() []string {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(this.path)\n\n\tlines := file_scanner.ReadLines()\n\tfor i, line := range lines {\n\t\tlines[i] = this.RenameLine(line)\n\t}\n\treturn lines\n}\n\nfunc (this *Relocatable) RenameLocalSymbol(old_name string, new_name string) {\n\tif _, found := this.liveness.LocalSymbols()[old_name]; !found {\n\t\terr := errors.New(\"local symbol is not found\")\n\t\tpanic(err)\n\t}\n\n\tif rename, found := this.renames[old_name]; found {\n\t\tif rename != new_name {\n\t\t\terr := errors.New(\"rename is already set\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.renames[old_name] = new_name\n}\n\nfunc (this *Relocatable) RenameLine(line string) string {\n\tfor old_name, new_name := range this.renames {\n\t\tline = strings.ReplaceAll(line, old_name+\",\", new_name+\",\")\n\t\tline = strings.ReplaceAll(line, old_name+\" \", new_name+\" \")\n\t\tline = strings.ReplaceAll(line, old_name+\"\\t\", new_name+\"\\t\")\n\t\tline = strings.ReplaceAll(line, old_name+\":\", new_name+\":\")\n\t\tline = strings.ReplaceAll(line, old_name+\"+\", new_name+\"+\")\n\t\tline = strings.ReplaceAll(line, old_name+\"-\", new_name+\"-\")\n\n\t\tif len(line) > len(old_name) {\n\t\t\tpos := len(line) - len(old_name)\n\n\t\t\tif line[pos:] == old_name {\n\t\t\t\tline = line[:pos] + new_name\n\t\t\t}\n\t\t}\n\t}\n\treturn line\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/kernel/section.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype SectionName int\n\nconst (\n\tATOMIC SectionName = iota\n\tBSS\n\tDATA\n\tDEBUG_ABBREV\n\tDEBUG_FRAME\n\tDEBUG_INFO\n\tDEBUG_LINE\n\tDEBUG_LOC\n\tDEBUG_RANGES\n\tDEBUG_STR\n\tDPU_HOST\n\tMRAM\n\tRODATA\n\tSTACK_SIZES\n\tTEXT\n)\n\ntype SectionFlag int\n\nconst (\n\tALLOC SectionFlag = iota\n\tWRITE\n\tEXECINSTR\n\tLINK_ORDER\n\tMERGE\n\tSTRINGS\n)\n\ntype SectionType int\n\nconst (\n\tPROGBITS SectionType = iota\n\tNOBITS\n)\n\ntype Section struct {\n\tsection_name  SectionName\n\tname          string\n\tsection_flags map[SectionFlag]bool\n\tsection_type  SectionType\n\n\tlabels    []*Label\n\tcur_label *Label\n}\n\nfunc (this *Section) Init(\n\tsection_name SectionName,\n\tname string,\n\tsection_flags map[SectionFlag]bool,\n\tsection_type SectionType,\n) {\n\tthis.section_name = section_name\n\tthis.name = name\n\tthis.section_flags = section_flags\n\tthis.section_type = section_type\n\n\tdefault_label := new(Label)\n\tdefault_label.Init(this.HiddenLabelName())\n\n\tthis.labels = make([]*Label, 0)\n\tthis.labels = append(this.labels, default_label)\n\n\tthis.cur_label = default_label\n}\n\nfunc (this *Section) SectionName() SectionName {\n\treturn this.section_name\n}\n\nfunc (this *Section) Name() string {\n\treturn this.name\n}\n\nfunc (this *Section) SectionFlags() map[SectionFlag]bool {\n\treturn this.section_flags\n}\n\nfunc (this *Section) SectionType() SectionType {\n\treturn this.section_type\n}\n\nfunc (this *Section) Address() int64 {\n\treturn this.labels[0].Address()\n}\n\nfunc (this *Section) SetAddress(address int64) {\n\tcur_address := address\n\tfor _, label := range this.labels {\n\t\tlabel.SetAddress(cur_address)\n\t\tcur_address += label.Size()\n\t}\n}\n\nfunc (this *Section) Size() int64 {\n\tsize := int64(0)\n\tfor _, label := range this.labels {\n\t\tsize += label.Size()\n\t}\n\treturn size\n}\n\nfunc (this *Section) Label(label_name string) *Label {\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn label\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *Section) Labels() []*Label {\n\treturn this.labels\n}\n\nfunc (this *Section) AppendLabel(label_name string) {\n\tlabel := new(Label)\n\tlabel.Init(label_name)\n\n\tthis.labels = append(this.labels, label)\n}\n\nfunc (this *Section) CheckoutLabel(label_name string) {\n\tif this.Label(label_name) == nil {\n\t\terr := errors.New(\"label is not found\")\n\t\tpanic(err)\n\t}\n\n\tthis.cur_label = this.Label(label_name)\n}\n\nfunc (this *Section) CurLabel() *Label {\n\treturn this.cur_label\n}\n\nfunc (this *Section) ToByteStream() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, label := range this.labels {\n\t\tbyte_stream.Merge(label.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Section) HiddenLabelName() string {\n\tif this.section_name == ATOMIC {\n\t\treturn \"atomic.\" + this.name\n\t} else if this.section_name == BSS {\n\t\treturn \"bss.\" + this.name\n\t} else if this.section_name == DATA {\n\t\treturn \"data.\" + this.name\n\t} else if this.section_name == DEBUG_ABBREV {\n\t\treturn \"debug_abbrev.\" + this.name\n\t} else if this.section_name == DEBUG_FRAME {\n\t\treturn \"debug_frame.\" + this.name\n\t} else if this.section_name == DEBUG_INFO {\n\t\treturn \"debug_info.\" + this.name\n\t} else if this.section_name == DEBUG_LINE {\n\t\treturn \"debug_line.\" + this.name\n\t} else if this.section_name == DEBUG_LOC {\n\t\treturn \"debug_loc.\" + this.name\n\t} else if this.section_name == DEBUG_RANGES {\n\t\treturn \"debug_ranges.\" + this.name\n\t} else if this.section_name == DEBUG_STR {\n\t\treturn \"debug_str.\" + this.name\n\t} else if this.section_name == DPU_HOST {\n\t\treturn \"dpu_host.\" + this.name\n\t} else if this.section_name == MRAM {\n\t\treturn \"mram.\" + this.name\n\t} else if this.section_name == RODATA {\n\t\treturn \"rodata.\" + this.name\n\t} else if this.section_name == STACK_SIZES {\n\t\treturn \"stack_sizes.\" + this.name\n\t} else if this.section_name == TEXT {\n\t\treturn \"text.\" + this.name\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lex_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype LexJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *LexJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *LexJob) Execute() {\n\tfmt.Printf(\"Lexing %s...\\n\", this.relocatable.Path())\n\n\tlexer_ := new(lexer.Lexer)\n\tlexer_.Init()\n\n\ttoken_stream := lexer_.Lex(this.relocatable.Path())\n\tthis.relocatable.SetTokenStream(token_stream)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/keyword_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype KeywordFactory struct {\n\tkeywords map[string]TokenType\n}\n\nfunc (this *KeywordFactory) Init() {\n\tthis.keywords = make(map[string]TokenType, 0)\n}\n\nfunc (this *KeywordFactory) AddKeyword(keyword string, token_type TokenType) {\n\tthis.keywords[keyword] = token_type\n}\n\nfunc (this *KeywordFactory) IsTokenizable(word string) bool {\n\t_, found := this.keywords[word]\n\treturn found\n}\n\nfunc (this *KeywordFactory) Tokenize(word string) *Token {\n\tif _, found := this.keywords[word]; !found {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\ttoken_type := this.keywords[word]\n\n\ttoken := new(Token)\n\ttoken.Init(token_type, \"\")\n\treturn token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/lexer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Lexer struct {\n\ttokenizer *Tokenizer\n}\n\nfunc (this *Lexer) Init() {\n\tthis.tokenizer = new(Tokenizer)\n\tthis.tokenizer.Init()\n}\n\nfunc (this *Lexer) Lex(path string) *TokenStream {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tfor _, line := range file_scanner.ReadLines() {\n\t\ttoken_stream.Merge(this.Tokenize(line))\n\n\t\tnew_line := new(Token)\n\t\tnew_line.Init(NEW_LINE, \"\")\n\n\t\ttoken_stream.Append(new_line)\n\t}\n\n\tend_of_file := new(Token)\n\tend_of_file.Init(END_OF_FILE, \"\")\n\n\ttoken_stream.Append(end_of_file)\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) Tokenize(line string) *TokenStream {\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tprev_pos := 0\n\tfor prev_pos < len(line) {\n\t\ttoken, length := this.FindTokenWithMaxLength(line, prev_pos)\n\n\t\tif token != nil {\n\t\t\ttoken_stream.Append(token)\n\t\t}\n\n\t\tprev_pos += length\n\t}\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) FindTokenWithMaxLength(line string, prev_pos int) (*Token, int) {\n\tif prev_pos < 0 {\n\t\terr := errors.New(\"prev pos < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.IsWhiteSpace(string(line[prev_pos])) {\n\t\treturn nil, 1\n\t}\n\n\tif prev_pos+2 < len(line) && this.IsComment(line[prev_pos:prev_pos+2]) {\n\t\treturn nil, len(line) - prev_pos\n\t}\n\n\tif this.IsQuote(string(line[prev_pos])) {\n\t\tnext_quote_pos := this.FindNextQuote(line, prev_pos+1)\n\n\t\tword := line[prev_pos : next_quote_pos+1]\n\n\t\ttoken := this.tokenizer.Tokenize(word)\n\n\t\treturn token, next_quote_pos - prev_pos + 1\n\t}\n\n\tfor i := prev_pos + 1; i <= len(line); i++ {\n\t\tword := line[prev_pos:i]\n\n\t\tif i+1 <= len(line) {\n\t\t\tnext_word := line[prev_pos : i+1]\n\n\t\t\tif this.tokenizer.IsTokenizable(word) && !this.tokenizer.IsTokenizable(next_word) {\n\t\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\t\treturn token, i - prev_pos\n\t\t\t} else {\n\t\t\t\tcontinue\n\t\t\t}\n\t\t} else {\n\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\treturn token, i - prev_pos\n\t\t}\n\t}\n\n\terr := errors.New(\"line is not further tokenizable\")\n\tpanic(err)\n}\n\nfunc (this *Lexer) IsWhiteSpace(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \" \" || word == \"\\t\" || word == \"\\n\"\n}\n\nfunc (this *Lexer) IsComment(word string) bool {\n\tif len(word) != 2 {\n\t\terr := errors.New(\"word size != 2\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \"//\"\n}\n\nfunc (this *Lexer) IsQuote(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \"\\\"\"\n}\n\nfunc (this *Lexer) FindNextQuote(line string, pos int) int {\n\tfor i := pos; i < len(line); i++ {\n\t\tif this.IsQuote(string(line[i])) {\n\t\t\treturn i\n\t\t}\n\t}\n\n\terr := errors.New(\"line does not have the next quote\")\n\tpanic(err)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/regex.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"regexp\"\n)\n\ntype Regex struct {\n\texpr  string\n\tregex *regexp.Regexp\n\n\ttoken_type TokenType\n}\n\nfunc (this *Regex) Init(expr string, token_type TokenType) {\n\tthis.expr = expr\n\n\tregex, err := regexp.Compile(expr)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.regex = regex\n\n\tthis.token_type = token_type\n}\n\nfunc (this *Regex) Expr() string {\n\treturn this.expr\n}\n\nfunc (this *Regex) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Regex) IsTokenizable(word string) bool {\n\treturn this.regex.MatchString(word)\n}\n\nfunc (this *Regex) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not matched\")\n\t\tpanic(err)\n\t}\n\n\ttoken := new(Token)\n\ttoken.Init(this.token_type, word)\n\treturn token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/regex_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype RegexFactory struct {\n\tregexes []*Regex\n}\n\nfunc (this *RegexFactory) Init() {\n\tthis.regexes = make([]*Regex, 0)\n}\n\nfunc (this *RegexFactory) HasRegex(expr string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.Expr() == expr {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) AddRegex(expr string, token_type TokenType) {\n\tif this.HasRegex(expr) {\n\t\terr := errors.New(\"regex already exists\")\n\t\tpanic(err)\n\t}\n\n\tregex := new(Regex)\n\tregex.Init(expr, token_type)\n\n\tthis.regexes = append(this.regexes, regex)\n}\n\nfunc (this *RegexFactory) IsTokenizable(word string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\ttoken := new(Token)\n\t\t\ttoken.Init(regex.TokenType(), word)\n\t\t\treturn token\n\t\t}\n\t}\n\n\treturn nil\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/token.go",
    "content": "package lexer\n\ntype TokenType int\n\nconst (\n\tEND_OF_FILE TokenType = iota\n\n\tNEW_LINE\n\n\tIDENTIFIER\n\tPOSITIVIE_NUMBER\n\tHEX_NUMBER\n\tSTRING\n\tGP_REG\n\tPAIR_REG\n\n\tACQUIRE\n\tRELEASE\n\tBOOT\n\tRESUME\n\n\tADD\n\tADDC\n\tAND\n\tANDN\n\tASR\n\tCMPB4\n\tLSL\n\tLSL1\n\tLSL1X\n\tLSLX\n\tLSR\n\tLSR1\n\tLSR1X\n\tLSRX\n\tMUL_SH_SH\n\tMUL_SH_SL\n\tMUL_SH_UH\n\tMUL_SH_UL\n\tMUL_SL_SH\n\tMUL_SL_SL\n\tMUL_SL_UH\n\tMUL_SL_UL\n\tMUL_UH_UH\n\tMUL_UH_UL\n\tMUL_UL_UH\n\tMUL_UL_UL\n\tNAND\n\tNOR\n\tNXOR\n\tOR\n\tORN\n\tROL\n\tROR\n\tRSUB\n\tRSUBC\n\tSUB\n\tSUBC\n\tXOR\n\tCALL\n\tHASH\n\n\tCAO\n\tCLO\n\tCLS\n\tCLZ\n\tEXTSB\n\tEXTSH\n\tEXTUB\n\tEXTUH\n\tSATS\n\tTIME_CFG\n\n\tDIV_STEP\n\tMUL_STEP\n\n\tLSL_ADD\n\tLSL_SUB\n\tLSR_ADD\n\tROL_ADD\n\n\tTIME\n\tNOP\n\n\tSTOP\n\n\tFAULT\n\n\tMOVD\n\tSWAPD\n\n\tLBS\n\tLBU\n\tLD\n\tLHS\n\tLHU\n\tLW\n\n\tSB\n\tSB_ID\n\tSD\n\tSD_ID\n\tSH\n\tSH_ID\n\tSW\n\tSW_ID\n\n\tLDMA\n\tLDMAI\n\tSDMA\n\n\tMOVE\n\tNEG\n\tNOT\n\tBKP\n\n\tJEQ\n\tJNEQ\n\tJZ\n\tJNZ\n\tJLTU\n\tJGTU\n\tJLEU\n\tJGEU\n\tJLTS\n\tJGTS\n\tJLES\n\tJGES\n\tJUMP\n\n\tS\n\tU\n\n\tATOMIC\n\tBSS\n\tDATA\n\tDEBUG_ABBREV\n\tDEBUG_FRAME\n\tDEBUG_INFO\n\tDEBUG_LINE\n\tDEBUG_LOC\n\tDEBUG_RANGES\n\tDEBUG_STR\n\tDPU_HOST\n\tMRAM\n\tRODATA\n\tSTACK_SIZES\n\tTEXT\n\n\tPROGBITS\n\tNOBITS\n\n\tFUNCTION\n\tOBJECT\n\n\tTRUE\n\tFALSE\n\tZ\n\tNZ\n\tE\n\tO\n\tPL\n\tMI\n\tOV\n\tNOV\n\tC\n\tNC\n\tSZ\n\tSNZ\n\tSPL\n\tSMI\n\tSO\n\tSE\n\tNC5\n\tNC6\n\tNC7\n\tNC8\n\tNC9\n\tNC10\n\tNC11\n\tNC12\n\tNC13\n\tNC14\n\tMAX\n\tNMAX\n\tSH32\n\tNSH32\n\tEQ\n\tNEQ\n\tLTU\n\tLEU\n\tGTU\n\tGEU\n\tLTS\n\tLES\n\tGTS\n\tGES\n\tXZ\n\tXNZ\n\tXLEU\n\tXGTU\n\tXLES\n\tXGTS\n\tSMALL\n\tLARGE\n\n\tLITTLE\n\tBIG\n\n\tZERO_REG\n\tONE\n\tID\n\tID2\n\tID4\n\tID8\n\tLNEG\n\tMNEG\n\n\tADDRSIG\n\tADDRSIG_SYM\n\tASCII\n\tASCIZ\n\tBYTE\n\tCFI_DEF_CFA_OFFSET\n\tCFI_ENDPROC\n\tCFI_OFFSET\n\tCFI_SECTIONS\n\tCFI_STARTPROC\n\tFILE\n\tGLOBL\n\tLOC\n\tLONG\n\tP2ALIGN\n\tQUAD\n\tSECTION\n\tSET\n\tSHORT\n\tSIZE\n\tTYPE\n\tWEAK\n\tZERO_DIRECTIVE\n\n\tIS_STMT\n\tPROLOGUE_END\n\n\tCOLON\n\tCOMMA\n\tPLUS\n\tMINUS\n)\n\ntype Token struct {\n\ttoken_type TokenType\n\tattribute  string\n}\n\nfunc (this *Token) Init(token_type TokenType, attribute string) {\n\tthis.token_type = token_type\n\tthis.attribute = attribute\n}\n\nfunc (this *Token) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Token) Attribute() string {\n\treturn this.attribute\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/token_stream.go",
    "content": "package lexer\n\ntype TokenStream struct {\n\ttokens []*Token\n}\n\nfunc (this *TokenStream) Init() {\n\tthis.tokens = make([]*Token, 0)\n}\n\nfunc (this *TokenStream) Size() int {\n\treturn len(this.tokens)\n}\n\nfunc (this *TokenStream) Get(pos int) *Token {\n\treturn this.tokens[pos]\n}\n\nfunc (this *TokenStream) Append(token *Token) {\n\tthis.tokens = append(this.tokens, token)\n}\n\nfunc (this *TokenStream) Merge(token_stream *TokenStream) {\n\tfor i := 0; i < token_stream.Size(); i++ {\n\t\tthis.Append(token_stream.Get(i))\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/lexer/tokenizer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype Tokenizer struct {\n\tkeyword_factory *KeywordFactory\n\tregex_factory   *RegexFactory\n}\n\nfunc (this *Tokenizer) Init() {\n\tthis.InitKeywordFactory()\n\tthis.InitRegexFactory()\n}\n\nfunc (this *Tokenizer) InitKeywordFactory() {\n\tthis.keyword_factory = new(KeywordFactory)\n\tthis.keyword_factory.Init()\n\n\tthis.keyword_factory.AddKeyword(\"acquire\", ACQUIRE)\n\tthis.keyword_factory.AddKeyword(\"release\", RELEASE)\n\tthis.keyword_factory.AddKeyword(\"boot\", BOOT)\n\tthis.keyword_factory.AddKeyword(\"resume\", RESUME)\n\n\tthis.keyword_factory.AddKeyword(\"add\", ADD)\n\tthis.keyword_factory.AddKeyword(\"addc\", ADDC)\n\tthis.keyword_factory.AddKeyword(\"and\", AND)\n\tthis.keyword_factory.AddKeyword(\"andn\", ANDN)\n\tthis.keyword_factory.AddKeyword(\"asr\", ASR)\n\tthis.keyword_factory.AddKeyword(\"cmpb4\", CMPB4)\n\tthis.keyword_factory.AddKeyword(\"lsl\", LSL)\n\tthis.keyword_factory.AddKeyword(\"lsl1\", LSL1)\n\tthis.keyword_factory.AddKeyword(\"lsl1x\", LSL1X)\n\tthis.keyword_factory.AddKeyword(\"lslx\", LSLX)\n\tthis.keyword_factory.AddKeyword(\"lsr\", LSR)\n\tthis.keyword_factory.AddKeyword(\"lsr1\", LSR1)\n\tthis.keyword_factory.AddKeyword(\"lsr1x\", LSR1X)\n\tthis.keyword_factory.AddKeyword(\"lsrx\", LSRX)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_sh\", MUL_SH_SH)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_sl\", MUL_SH_SL)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_uh\", MUL_SH_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_ul\", MUL_SH_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_sh\", MUL_SL_SH)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_sl\", MUL_SL_SL)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_uh\", MUL_SL_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_ul\", MUL_SL_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_uh_uh\", MUL_UH_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_uh_ul\", MUL_UH_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_ul_uh\", MUL_UL_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_ul_ul\", MUL_UL_UL)\n\tthis.keyword_factory.AddKeyword(\"nand\", NAND)\n\tthis.keyword_factory.AddKeyword(\"nor\", NOR)\n\tthis.keyword_factory.AddKeyword(\"nxor\", NXOR)\n\tthis.keyword_factory.AddKeyword(\"or\", OR)\n\tthis.keyword_factory.AddKeyword(\"orn\", ORN)\n\tthis.keyword_factory.AddKeyword(\"rol\", ROL)\n\tthis.keyword_factory.AddKeyword(\"ror\", ROR)\n\tthis.keyword_factory.AddKeyword(\"rsub\", RSUB)\n\tthis.keyword_factory.AddKeyword(\"rsubc\", RSUBC)\n\tthis.keyword_factory.AddKeyword(\"sub\", SUB)\n\tthis.keyword_factory.AddKeyword(\"subc\", SUBC)\n\tthis.keyword_factory.AddKeyword(\"xor\", XOR)\n\tthis.keyword_factory.AddKeyword(\"call\", CALL)\n\tthis.keyword_factory.AddKeyword(\"hash\", HASH)\n\tthis.keyword_factory.AddKeyword(\"cao\", CAO)\n\tthis.keyword_factory.AddKeyword(\"clo\", CLO)\n\tthis.keyword_factory.AddKeyword(\"cls\", CLS)\n\tthis.keyword_factory.AddKeyword(\"clz\", CLZ)\n\tthis.keyword_factory.AddKeyword(\"extsb\", EXTSB)\n\tthis.keyword_factory.AddKeyword(\"extsh\", EXTSH)\n\tthis.keyword_factory.AddKeyword(\"extub\", EXTUB)\n\tthis.keyword_factory.AddKeyword(\"extuh\", EXTUH)\n\tthis.keyword_factory.AddKeyword(\"sats\", SATS)\n\tthis.keyword_factory.AddKeyword(\"time_cfg\", TIME_CFG)\n\n\tthis.keyword_factory.AddKeyword(\"div_step\", DIV_STEP)\n\tthis.keyword_factory.AddKeyword(\"mul_step\", MUL_STEP)\n\n\tthis.keyword_factory.AddKeyword(\"lsl_add\", LSL_ADD)\n\tthis.keyword_factory.AddKeyword(\"lsl_sub\", LSL_SUB)\n\tthis.keyword_factory.AddKeyword(\"lsr_add\", LSR_ADD)\n\tthis.keyword_factory.AddKeyword(\"rol_add\", ROL_ADD)\n\n\tthis.keyword_factory.AddKeyword(\"time\", TIME)\n\tthis.keyword_factory.AddKeyword(\"nop\", NOP)\n\n\tthis.keyword_factory.AddKeyword(\"stop\", STOP)\n\tthis.keyword_factory.AddKeyword(\"fault\", FAULT)\n\n\tthis.keyword_factory.AddKeyword(\"movd\", MOVD)\n\tthis.keyword_factory.AddKeyword(\"swapd\", SWAPD)\n\n\tthis.keyword_factory.AddKeyword(\"lbs\", LBS)\n\tthis.keyword_factory.AddKeyword(\"lbu\", LBU)\n\tthis.keyword_factory.AddKeyword(\"ld\", LD)\n\tthis.keyword_factory.AddKeyword(\"lhs\", LHS)\n\tthis.keyword_factory.AddKeyword(\"lhu\", LHU)\n\tthis.keyword_factory.AddKeyword(\"lw\", LW)\n\n\tthis.keyword_factory.AddKeyword(\"sb\", SB)\n\tthis.keyword_factory.AddKeyword(\"sb_id\", SB_ID)\n\tthis.keyword_factory.AddKeyword(\"sd\", SD)\n\tthis.keyword_factory.AddKeyword(\"sd_id\", SD_ID)\n\tthis.keyword_factory.AddKeyword(\"sh\", SH)\n\tthis.keyword_factory.AddKeyword(\"sh_id\", SH_ID)\n\tthis.keyword_factory.AddKeyword(\"sw\", SW)\n\tthis.keyword_factory.AddKeyword(\"sw_id\", SW_ID)\n\n\tthis.keyword_factory.AddKeyword(\"ldma\", LDMA)\n\tthis.keyword_factory.AddKeyword(\"ldmai\", LDMAI)\n\tthis.keyword_factory.AddKeyword(\"sdma\", SDMA)\n\n\tthis.keyword_factory.AddKeyword(\"move\", MOVE)\n\tthis.keyword_factory.AddKeyword(\"neg\", NEG)\n\tthis.keyword_factory.AddKeyword(\"not\", NOT)\n\tthis.keyword_factory.AddKeyword(\"bkp\", BKP)\n\n\tthis.keyword_factory.AddKeyword(\"jeq\", JEQ)\n\tthis.keyword_factory.AddKeyword(\"jneq\", JNEQ)\n\tthis.keyword_factory.AddKeyword(\"jz\", JZ)\n\tthis.keyword_factory.AddKeyword(\"jnz\", JNZ)\n\tthis.keyword_factory.AddKeyword(\"jltu\", JLTU)\n\tthis.keyword_factory.AddKeyword(\"jgtu\", JGTU)\n\tthis.keyword_factory.AddKeyword(\"jleu\", JLEU)\n\tthis.keyword_factory.AddKeyword(\"jgeu\", JGEU)\n\tthis.keyword_factory.AddKeyword(\"jlts\", JLTS)\n\tthis.keyword_factory.AddKeyword(\"jgts\", JGTS)\n\tthis.keyword_factory.AddKeyword(\"jles\", JLES)\n\tthis.keyword_factory.AddKeyword(\"jges\", JGES)\n\tthis.keyword_factory.AddKeyword(\"jump\", JUMP)\n\n\tthis.keyword_factory.AddKeyword(\".s\", S)\n\tthis.keyword_factory.AddKeyword(\".u\", U)\n\n\tthis.keyword_factory.AddKeyword(\".atomic\", ATOMIC)\n\tthis.keyword_factory.AddKeyword(\".bss\", BSS)\n\tthis.keyword_factory.AddKeyword(\".data\", DATA)\n\tthis.keyword_factory.AddKeyword(\".debug_abbrev\", DEBUG_ABBREV)\n\tthis.keyword_factory.AddKeyword(\".debug_frame\", DEBUG_FRAME)\n\tthis.keyword_factory.AddKeyword(\".debug_info\", DEBUG_INFO)\n\tthis.keyword_factory.AddKeyword(\".debug_line\", DEBUG_LINE)\n\tthis.keyword_factory.AddKeyword(\".debug_loc\", DEBUG_LOC)\n\tthis.keyword_factory.AddKeyword(\".debug_ranges\", DEBUG_RANGES)\n\tthis.keyword_factory.AddKeyword(\".debug_str\", DEBUG_STR)\n\tthis.keyword_factory.AddKeyword(\".dpu_host\", DPU_HOST)\n\tthis.keyword_factory.AddKeyword(\".mram\", MRAM)\n\tthis.keyword_factory.AddKeyword(\".rodata\", RODATA)\n\tthis.keyword_factory.AddKeyword(\".stack_sizes\", STACK_SIZES)\n\tthis.keyword_factory.AddKeyword(\".text\", TEXT)\n\tthis.keyword_factory.AddKeyword(\".file\", FILE)\n\tthis.keyword_factory.AddKeyword(\".section\", SECTION)\n\n\tthis.keyword_factory.AddKeyword(\"@progbits\", PROGBITS)\n\tthis.keyword_factory.AddKeyword(\"@nobits\", NOBITS)\n\tthis.keyword_factory.AddKeyword(\"@function\", FUNCTION)\n\tthis.keyword_factory.AddKeyword(\"@object\", OBJECT)\n\n\tthis.keyword_factory.AddKeyword(\"true\", TRUE)\n\tthis.keyword_factory.AddKeyword(\"false\", FALSE)\n\tthis.keyword_factory.AddKeyword(\"z\", Z)\n\tthis.keyword_factory.AddKeyword(\"nz\", NZ)\n\tthis.keyword_factory.AddKeyword(\"e\", E)\n\tthis.keyword_factory.AddKeyword(\"o\", O)\n\tthis.keyword_factory.AddKeyword(\"pl\", PL)\n\tthis.keyword_factory.AddKeyword(\"mi\", MI)\n\tthis.keyword_factory.AddKeyword(\"ov\", OV)\n\tthis.keyword_factory.AddKeyword(\"nov\", NOV)\n\tthis.keyword_factory.AddKeyword(\"c\", C)\n\tthis.keyword_factory.AddKeyword(\"nc\", NC)\n\tthis.keyword_factory.AddKeyword(\"sz\", SZ)\n\tthis.keyword_factory.AddKeyword(\"snz\", SNZ)\n\tthis.keyword_factory.AddKeyword(\"spl\", SPL)\n\tthis.keyword_factory.AddKeyword(\"smi\", SMI)\n\tthis.keyword_factory.AddKeyword(\"so\", SO)\n\tthis.keyword_factory.AddKeyword(\"se\", SE)\n\tthis.keyword_factory.AddKeyword(\"nc5\", NC5)\n\tthis.keyword_factory.AddKeyword(\"nc6\", NC6)\n\tthis.keyword_factory.AddKeyword(\"nc7\", NC7)\n\tthis.keyword_factory.AddKeyword(\"nc8\", NC8)\n\tthis.keyword_factory.AddKeyword(\"nc9\", NC9)\n\tthis.keyword_factory.AddKeyword(\"nc10\", NC10)\n\tthis.keyword_factory.AddKeyword(\"nc11\", NC11)\n\tthis.keyword_factory.AddKeyword(\"nc12\", NC12)\n\tthis.keyword_factory.AddKeyword(\"nc13\", NC13)\n\tthis.keyword_factory.AddKeyword(\"nc14\", NC14)\n\tthis.keyword_factory.AddKeyword(\"max\", MAX)\n\tthis.keyword_factory.AddKeyword(\"nmax\", NMAX)\n\tthis.keyword_factory.AddKeyword(\"sh32\", SH32)\n\tthis.keyword_factory.AddKeyword(\"nsh32\", NSH32)\n\tthis.keyword_factory.AddKeyword(\"eq\", EQ)\n\tthis.keyword_factory.AddKeyword(\"neq\", NEQ)\n\tthis.keyword_factory.AddKeyword(\"ltu\", LTU)\n\tthis.keyword_factory.AddKeyword(\"leu\", LEU)\n\tthis.keyword_factory.AddKeyword(\"gtu\", GTU)\n\tthis.keyword_factory.AddKeyword(\"geu\", GEU)\n\tthis.keyword_factory.AddKeyword(\"lts\", LTS)\n\tthis.keyword_factory.AddKeyword(\"les\", LES)\n\tthis.keyword_factory.AddKeyword(\"gts\", GTS)\n\tthis.keyword_factory.AddKeyword(\"ges\", GES)\n\tthis.keyword_factory.AddKeyword(\"xz\", XZ)\n\tthis.keyword_factory.AddKeyword(\"xnz\", XNZ)\n\tthis.keyword_factory.AddKeyword(\"xleu\", XLEU)\n\tthis.keyword_factory.AddKeyword(\"xgtu\", XGTU)\n\tthis.keyword_factory.AddKeyword(\"xles\", XLES)\n\tthis.keyword_factory.AddKeyword(\"xgts\", XGTS)\n\tthis.keyword_factory.AddKeyword(\"small\", SMALL)\n\tthis.keyword_factory.AddKeyword(\"large\", LARGE)\n\n\tthis.keyword_factory.AddKeyword(\"!little\", LITTLE)\n\tthis.keyword_factory.AddKeyword(\"!big\", BIG)\n\n\tthis.keyword_factory.AddKeyword(\"zero\", ZERO_REG)\n\tthis.keyword_factory.AddKeyword(\"one\", ONE)\n\tthis.keyword_factory.AddKeyword(\"id\", ID)\n\tthis.keyword_factory.AddKeyword(\"id2\", ID2)\n\tthis.keyword_factory.AddKeyword(\"id4\", ID4)\n\tthis.keyword_factory.AddKeyword(\"id8\", ID8)\n\tthis.keyword_factory.AddKeyword(\"lneg\", LNEG)\n\tthis.keyword_factory.AddKeyword(\"mneg\", MNEG)\n\n\tthis.keyword_factory.AddKeyword(\".addrsig\", ADDRSIG)\n\tthis.keyword_factory.AddKeyword(\".addrsig_sym\", ADDRSIG_SYM)\n\tthis.keyword_factory.AddKeyword(\".ascii\", ASCII)\n\tthis.keyword_factory.AddKeyword(\".asciz\", ASCIZ)\n\tthis.keyword_factory.AddKeyword(\".byte\", BYTE)\n\tthis.keyword_factory.AddKeyword(\".cfi_def_cfa_offset\", CFI_DEF_CFA_OFFSET)\n\tthis.keyword_factory.AddKeyword(\".cfi_endproc\", CFI_ENDPROC)\n\tthis.keyword_factory.AddKeyword(\".cfi_offset\", CFI_OFFSET)\n\tthis.keyword_factory.AddKeyword(\".cfi_sections\", CFI_SECTIONS)\n\tthis.keyword_factory.AddKeyword(\".cfi_startproc\", CFI_STARTPROC)\n\tthis.keyword_factory.AddKeyword(\".globl\", GLOBL)\n\tthis.keyword_factory.AddKeyword(\".loc\", LOC)\n\tthis.keyword_factory.AddKeyword(\".long\", LONG)\n\tthis.keyword_factory.AddKeyword(\".p2align\", P2ALIGN)\n\tthis.keyword_factory.AddKeyword(\".quad\", QUAD)\n\tthis.keyword_factory.AddKeyword(\".set\", SET)\n\tthis.keyword_factory.AddKeyword(\".short\", SHORT)\n\tthis.keyword_factory.AddKeyword(\".size\", SIZE)\n\tthis.keyword_factory.AddKeyword(\".type\", TYPE)\n\tthis.keyword_factory.AddKeyword(\".weak\", WEAK)\n\tthis.keyword_factory.AddKeyword(\".zero\", ZERO_DIRECTIVE)\n\n\tthis.keyword_factory.AddKeyword(\"is_stmt\", IS_STMT)\n\tthis.keyword_factory.AddKeyword(\"prologue_end\", PROLOGUE_END)\n\n\tthis.keyword_factory.AddKeyword(\":\", COLON)\n\tthis.keyword_factory.AddKeyword(\",\", COMMA)\n\tthis.keyword_factory.AddKeyword(\"+\", PLUS)\n\tthis.keyword_factory.AddKeyword(\"-\", MINUS)\n}\n\nfunc (this *Tokenizer) InitRegexFactory() {\n\tthis.regex_factory = new(RegexFactory)\n\tthis.regex_factory.Init()\n\n\tthis.regex_factory.AddRegex(\"^(r)([0-9]*)$\", GP_REG)\n\tthis.regex_factory.AddRegex(\"^(d)([0-9]*)$\", PAIR_REG)\n\n\tthis.regex_factory.AddRegex(\"^([A-Za-z_.])([A-Za-z0-9_]*)$\", IDENTIFIER)\n\n\tthis.regex_factory.AddRegex(\"^([0-9]*)$\", POSITIVIE_NUMBER)\n\tthis.regex_factory.AddRegex(\"^(0x)([0-9]*)$\", HEX_NUMBER)\n\n\tthis.regex_factory.AddRegex(\"^(\\\")(.*)(\\\")$\", STRING)\n}\n\nfunc (this *Tokenizer) IsTokenizable(word string) bool {\n\treturn this.keyword_factory.IsTokenizable(word) || this.regex_factory.IsTokenizable(word)\n}\n\nfunc (this *Tokenizer) Tokenize(word string) *Token {\n\tif this.keyword_factory.IsTokenizable(word) {\n\t\treturn this.keyword_factory.Tokenize(word)\n\t} else if this.regex_factory.IsTokenizable(word) {\n\t\treturn this.regex_factory.Tokenize(word)\n\t} else {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/linker.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"os\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/core\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/logic\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Linker struct {\n\tcommand_line_parser *misc.CommandLineParser\n\n\troot_dirpath           string\n\tbin_dirpath            string\n\tbenchmark              string\n\tnum_simulation_threads int\n\n\tbenchmark_relocatable *kernel.Relocatable\n\tsdk_relocatables      map[string]*kernel.Relocatable\n\n\texecutable *kernel.Executable\n\n\tlinker_script *logic.LinkerScript\n}\n\nfunc (this *Linker) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n\n\tthis.root_dirpath = command_line_parser.StringParameter(\"root_dirpath\")\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\tthis.num_simulation_threads = int(command_line_parser.IntParameter(\"num_simulation_threads\"))\n\n\tthis.InitBenchmarkRelocatable()\n\tthis.InitSdkRelocatables()\n\n\tthis.executable = new(kernel.Executable)\n\tthis.executable.Init(this.benchmark)\n\n\tthis.linker_script = new(logic.LinkerScript)\n\tthis.linker_script.Init(command_line_parser)\n}\n\nfunc (this *Linker) InitBenchmarkRelocatable() {\n\tbenchmark_build_dirpath := filepath.Join(this.root_dirpath, \"benchmark\", \"build\")\n\n\tassembly_path := filepath.Join(\n\t\tbenchmark_build_dirpath,\n\t\tthis.benchmark,\n\t\t\"dpu\",\n\t\t\"CMakeFiles\",\n\t\tfmt.Sprintf(\"%s_device.dir\", this.benchmark),\n\t\t\"task.c.o\",\n\t)\n\n\tthis.benchmark_relocatable = new(kernel.Relocatable)\n\tthis.benchmark_relocatable.Init(this.benchmark)\n\tthis.benchmark_relocatable.SetPath(assembly_path)\n}\n\nfunc (this *Linker) InitSdkRelocatables() {\n\tthis.sdk_relocatables = make(map[string]*kernel.Relocatable, 0)\n\n\tsdk_build_dirpath := filepath.Join(this.root_dirpath, \"sdk\", \"build\")\n\n\tsdk_build_dir_entries, sdk_build_dir_read_err := os.ReadDir(sdk_build_dirpath)\n\n\tif sdk_build_dir_read_err != nil {\n\t\tpanic(sdk_build_dir_read_err)\n\t}\n\n\tfor _, sdk_build_dir_entry := range sdk_build_dir_entries {\n\t\tif sdk_build_dir_entry.IsDir() && sdk_build_dir_entry.Name() != \"CMakeFiles\" {\n\t\t\tsdk_lib_dirpath := filepath.Join(\n\t\t\t\tsdk_build_dirpath,\n\t\t\t\tsdk_build_dir_entry.Name(),\n\t\t\t\t\"CMakeFiles\",\n\t\t\t\tsdk_build_dir_entry.Name()+\".dir\",\n\t\t\t)\n\n\t\t\tsdk_lib_dir_entries, sdk_lib_dir_read_err := os.ReadDir(sdk_lib_dirpath)\n\n\t\t\tif sdk_lib_dir_read_err != nil {\n\t\t\t\tpanic(sdk_lib_dir_read_err)\n\t\t\t}\n\n\t\t\tfor _, sdk_lib_dir_entry := range sdk_lib_dir_entries {\n\t\t\t\tassembly_path := filepath.Join(sdk_lib_dirpath, sdk_lib_dir_entry.Name())\n\n\t\t\t\tlib_dir_name := filepath.Base(sdk_lib_dirpath)\n\t\t\t\tsdk_relocatable_name := lib_dir_name[:len(lib_dir_name)-4] + \".\" + sdk_lib_dir_entry.Name()[:len(sdk_lib_dir_entry.Name())-4]\n\n\t\t\t\tsdk_relocatable := new(kernel.Relocatable)\n\t\t\t\tsdk_relocatable.Init(sdk_relocatable_name)\n\t\t\t\tsdk_relocatable.SetPath(assembly_path)\n\n\t\t\t\tthis.sdk_relocatables[sdk_relocatable_name] = sdk_relocatable\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Linker) Link() {\n\tthis.Lex()\n\tthis.Parse()\n\tthis.AnalyzeLiveness()\n\tthis.MakeExecutable()\n\tthis.LoadExecutable()\n\tthis.DumpExecutable()\n}\n\nfunc (this *Linker) Lex() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tbenchmark_lex_job := new(LexJob)\n\tbenchmark_lex_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_lex_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_lex_job := new(LexJob)\n\t\tsdk_lex_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_lex_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) Parse() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tbenchmark_parse_job := new(ParseJob)\n\tbenchmark_parse_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_parse_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_parse_job := new(ParseJob)\n\t\tsdk_parse_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_parse_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) AnalyzeLiveness() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tbenchmark_analyze_liveness_job := new(AnalyzeLivenessJob)\n\tbenchmark_analyze_liveness_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_analyze_liveness_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_analyze_liveness_job := new(AnalyzeLivenessJob)\n\t\tsdk_analyze_liveness_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_analyze_liveness_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) MakeExecutable() {\n\tfmt.Printf(\"Resolving symbols of %s...\\n\", this.executable.Name())\n\n\tthis.executable.SetBenchmarkRelocatable(this.benchmark_relocatable)\n\tthis.ResolveSymbols()\n\n\texecutable_path := filepath.Join(this.bin_dirpath, \"main.S\")\n\n\tfmt.Printf(\"Dumping the executable to %s...\\n\", this.executable.Path())\n\n\tthis.executable.SetPath(executable_path)\n\tthis.executable.DumpAssembly()\n}\n\nfunc (this *Linker) HasResolved() bool {\n\tfor unresolved_symbol, _ := range this.executable.Liveness().UnresolvedSymbols() {\n\t\tif !this.linker_script.HasLinkerConstant(unresolved_symbol) {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *Linker) ResolveSymbols() {\n\tthis.executable.AddSdkRelocatable(this.sdk_relocatables[\"misc.crt0\"])\n\n\tfor !this.HasResolved() {\n\t\tfor unresolved_symbol, _ := range this.executable.Liveness().UnresolvedSymbols() {\n\t\t\tif !this.linker_script.HasLinkerConstant(unresolved_symbol) {\n\t\t\t\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\t\t\t\tif _, found := sdk_relocatable.Liveness().GlobalSymbols()[unresolved_symbol]; found {\n\t\t\t\t\t\tthis.executable.AddSdkRelocatable(sdk_relocatable)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Linker) LoadExecutable() {\n\tfmt.Println(\"Re-lexing executable\")\n\tlexer_ := new(lexer.Lexer)\n\tlexer_.Init()\n\ttoken_stream := lexer_.Lex(this.executable.Path())\n\tthis.executable.SetTokenStream(token_stream)\n\n\tfmt.Println(\"Re-parsing executable...\")\n\tparser_ := new(parser.Parser)\n\tparser_.Init()\n\tast := parser_.Parse(token_stream)\n\tthis.executable.SetAst(ast)\n\n\tfmt.Println(\"Assigning labels...\")\n\tlabel_assigner := new(logic.LabelAssigner)\n\tlabel_assigner.Init()\n\tlabel_assigner.Assign(this.executable)\n\n\tfmt.Println(\"Assigning addresses..\")\n\tthis.linker_script.Assign(this.executable)\n\n\tfmt.Println(\"Setting alias labels...\")\n\tset_assigner := new(logic.SetAssigner)\n\tset_assigner.Init()\n\tset_assigner.Assign(this.executable)\n\n\tfmt.Println(\"Assigning instructions...\")\n\tinstruction_assigner := new(logic.InstructionAssigner)\n\tinstruction_assigner.Init(this.linker_script)\n\tinstruction_assigner.Assign(this.executable)\n}\n\nfunc (this *Linker) DumpExecutable() {\n\tthis.linker_script.DumpValues(filepath.Join(this.bin_dirpath, \"values.txt\"))\n\tthis.executable.DumpAddresses(filepath.Join(this.bin_dirpath, \"addresses.txt\"))\n\tthis.executable.DumpAtomic(filepath.Join(this.bin_dirpath, \"atomic.bin\"))\n\tthis.executable.DumpIram(filepath.Join(this.bin_dirpath, \"iram.bin\"))\n\tthis.executable.DumpWram(filepath.Join(this.bin_dirpath, \"wram.bin\"))\n\tthis.executable.DumpMram(filepath.Join(this.bin_dirpath, \"mram.bin\"))\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/instruction_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/kernel/directive\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype InstructionAssigner struct {\n\texecutable    *kernel.Executable\n\twalker        *parser.Walker\n\tlinker_script *LinkerScript\n}\n\nfunc (this *InstructionAssigner) Init(linker_script *LinkerScript) {\n\tthis.linker_script = linker_script\n\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(stmt.ASCII, this.WalkAsciiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ASCIZ, this.WalkAscizStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BYTE, this.WalkByteStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_PROGRAM_COUNTER, this.WalkLongProgramCounterStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_SECTION_NAME, this.WalkLongSectionNameStmt)\n\tthis.walker.RegisterStmtCallback(stmt.QUAD, this.WalkQuadStmt)\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SHORT, this.WalkShortStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_DOUBLE_NUMBER, this.WalkZeroDoubleNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_SINGLE_NUMBER, this.WalkZeroSingleNumberStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.CI, this.WalkCiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DMA_RRI, this.WalkDmaRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DRDICI, this.WalkDrdiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.EDRI, this.WalkEdriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERID, this.WalkEridStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERII, this.WalkEriiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERIR, this.WalkErirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERRI, this.WalkErriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.I, this.WalkIStmt)\n\tthis.walker.RegisterStmtCallback(stmt.NOP, this.WalkNopStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RCI, this.WalkRciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RICI, this.WalkRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRCI, this.WalkRirciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRC, this.WalkRircStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIR, this.WalkRirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRCI, this.WalkRrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRC, this.WalkRrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRICI, this.WalkRriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRIC, this.WalkRricStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRI, this.WalkRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRCI, this.WalkRrrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRC, this.WalkRrrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRICI, this.WalkRrriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRI, this.WalkRrriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRR, this.WalkRrrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RR, this.WalkRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.R, this.WalkRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.S_ERRI, this.WalkSErriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RCI, this.WalkSRciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRCI, this.WalkSRirciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRC, this.WalkSRircStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRCI, this.WalkSRrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRC, this.WalkSRrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRICI, this.WalkSRriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRIC, this.WalkSRricStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRI, this.WalkSRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRCI, this.WalkSRrrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRC, this.WalkSRrrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRICI, this.WalkSRrriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRI, this.WalkSRrriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRR, this.WalkSRrrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RR, this.WalkSRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_R, this.WalkSRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.BKP, this.WalkBkpStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BOOT_RI, this.WalkBootRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RI, this.WalkCallRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RR, this.WalkCallRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DIV_STEP_DRDI, this.WalkDivStepDrdiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RII, this.WalkJeqRiiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RRI, this.WalkJeqRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JNZ_RI, this.WalkJnzRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_I, this.WalkJumpIStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_R, this.WalkJumpRStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_RRI, this.WalkLbsRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_S_RRI, this.WalkLbsSRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LD_DRI, this.WalkLdDriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVD_DD, this.WalkMovdDdStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RICI, this.WalkMoveRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RI, this.WalkMoveRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RICI, this.WalkMoveSRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RI, this.WalkMoveSRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RII, this.WalkSbIdRiiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RI, this.WalkSbIdRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_RIR, this.WalkSbRirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SD_RID, this.WalkSdRidStmt)\n\tthis.walker.RegisterStmtCallback(stmt.STOP, this.WalkStopStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TIME_CFG_R, this.WalkTimeCfgRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *InstructionAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *InstructionAssigner) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tascii_stmt := stmt_.AsciiStmt()\n\ttoken := ascii_stmt.Token()\n\tattribute := token.Attribute()\n\tcharacters := attribute[1 : len(attribute)-1]\n\n\t// TODO(bongjoon.hyun@gmail.com): decode octal code\n\n\tascii_directive := new(directive.AsciiDirective)\n\tascii_directive.Init(characters)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(ascii_directive)\n}\n\nfunc (this *InstructionAssigner) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tasciz_stmt := stmt_.AscizStmt()\n\ttoken := asciz_stmt.Token()\n\tattribute := token.Attribute()\n\tcharacters := attribute[1 : len(attribute)-1]\n\n\tasciz_directive := new(directive.AscizDirective)\n\tasciz_directive.Init(characters)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(asciz_directive)\n}\n\nfunc (this *InstructionAssigner) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tbyte_stmt := stmt_.ByteStmt()\n\n\tvalue := this.EvaluateProgramCounter(byte_stmt.Expr())\n\n\tbyte_directive := new(directive.ByteDirective)\n\tbyte_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(byte_directive)\n}\n\nfunc (this *InstructionAssigner) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tlong_program_counter_stmt := stmt_.LongProgramCounterStmt()\n\n\tvalue := this.EvaluateProgramCounter(long_program_counter_stmt.Expr())\n\n\tlong_directive := new(directive.LongDirective)\n\tlong_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(long_directive)\n}\n\nfunc (this *InstructionAssigner) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tlong_section_name_stmt := stmt_.LongSectionNameStmt()\n\n\tvalue := this.EvaluateSectionName(long_section_name_stmt.Expr())\n\n\tlong_directive := new(directive.LongDirective)\n\tlong_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(long_directive)\n}\n\nfunc (this *InstructionAssigner) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tquad_stmt := stmt_.QuadStmt()\n\n\tvalue := this.EvaluateProgramCounter(quad_stmt.Expr())\n\n\tquad_directive := new(directive.QuadDirective)\n\tquad_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(quad_directive)\n}\n\nfunc (this *InstructionAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tshort_stmt := stmt_.ShortStmt()\n\n\tvalue := this.EvaluateProgramCounter(short_stmt.Expr())\n\n\tshort_directive := new(directive.ShortDirective)\n\tshort_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(short_directive)\n}\n\nfunc (this *InstructionAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\tsize := this.EvaluateProgramCounter(zero_double_number_stmt.Expr1())\n\tvalue := this.EvaluateProgramCounter(zero_double_number_stmt.Expr2())\n\n\tzero_directive := new(directive.ZeroDirective)\n\tzero_directive.Init(size, value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(zero_directive)\n}\n\nfunc (this *InstructionAssigner) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\tsize := this.EvaluateProgramCounter(zero_single_number_stmt.Expr())\n\n\tzero_directive := new(directive.ZeroDirective)\n\tzero_directive.Init(size, 0)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(zero_directive)\n}\n\nfunc (this *InstructionAssigner) WalkCiStmt(stmt_ *stmt.Stmt) {\n\tci_stmt := stmt_.CiStmt()\n\n\top_code := this.ConvertCiOpCode(ci_stmt.OpCode())\n\tcondition := this.ConvertCondition(ci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(ci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitCi(op_code, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDdciStmt(stmt_ *stmt.Stmt) {\n\tddci_stmt := stmt_.DdciStmt()\n\n\top_code := this.ConvertDdciOpCode(ddci_stmt.OpCode())\n\tdc := this.ConvertPairReg(ddci_stmt.Dc())\n\tdb := this.ConvertPairReg(ddci_stmt.Db())\n\tcondition := this.ConvertCondition(ddci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(ddci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDdci(op_code, dc, db, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDmaRriStmt(stmt_ *stmt.Stmt) {\n\tdma_rri_stmt := stmt_.DmaRriStmt()\n\n\top_code := this.ConvertDmaRriOpCode(dma_rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(dma_rri_stmt.Ra())\n\trb := this.ConvertSrcReg(dma_rri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(dma_rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDmaRri(op_code, ra, rb, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDrdiciStmt(stmt_ *stmt.Stmt) {\n\tdrdici_stmt := stmt_.DrdiciStmt()\n\n\top_code := this.ConvertDrdiciOpCode(drdici_stmt.OpCode())\n\tdc := this.ConvertPairReg(drdici_stmt.Dc())\n\tra := this.ConvertSrcReg(drdici_stmt.Ra())\n\tdb := this.ConvertPairReg(drdici_stmt.Db())\n\timm := this.EvaluateProgramCounter(drdici_stmt.Imm())\n\tcondition := this.ConvertCondition(drdici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(drdici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDrdici(op_code, dc, ra, db, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEdriStmt(stmt_ *stmt.Stmt) {\n\tedri_stmt := stmt_.EdriStmt()\n\n\top_code := this.ConvertLoadOpCode(edri_stmt.OpCode())\n\tendian := this.ConvertEndian(edri_stmt.Endian())\n\tdc := this.ConvertPairReg(edri_stmt.Dc())\n\tra := this.ConvertSrcReg(edri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(edri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitEdri(op_code, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEridStmt(stmt_ *stmt.Stmt) {\n\terid_stmt := stmt_.EridStmt()\n\n\top_code := this.ConvertStoreOpCode(erid_stmt.OpCode())\n\tendian := this.ConvertEndian(erid_stmt.Endian())\n\tra := this.ConvertSrcReg(erid_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erid_stmt.Off())\n\tdb := this.ConvertPairReg(erid_stmt.Db())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErid(op_code, endian, ra, off, db)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEriiStmt(stmt_ *stmt.Stmt) {\n\terii_stmt := stmt_.EriiStmt()\n\n\top_code := this.ConvertStoreOpCode(erii_stmt.OpCode())\n\tendian := this.ConvertEndian(erii_stmt.Endian())\n\tra := this.ConvertSrcReg(erii_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erii_stmt.Off())\n\timm := this.EvaluateProgramCounter(erii_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkErirStmt(stmt_ *stmt.Stmt) {\n\terir_stmt := stmt_.ErirStmt()\n\n\top_code := this.ConvertStoreOpCode(erir_stmt.OpCode())\n\tendian := this.ConvertEndian(erir_stmt.Endian())\n\tra := this.ConvertSrcReg(erir_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erir_stmt.Off())\n\trb := this.ConvertSrcReg(erir_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErir(op_code, endian, ra, off, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkErriStmt(stmt_ *stmt.Stmt) {\n\terri_stmt := stmt_.ErriStmt()\n\n\top_code := this.ConvertLoadOpCode(erri_stmt.OpCode())\n\tendian := this.ConvertEndian(erri_stmt.Endian())\n\trc := this.ConvertGpReg(erri_stmt.Rc())\n\tra := this.ConvertSrcReg(erri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErri(op_code, endian, rc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkIStmt(stmt_ *stmt.Stmt) {\n\ti_stmt := stmt_.IStmt()\n\n\top_code := this.ConvertIOpCode(i_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(i_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitI(op_code, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkNopStmt(stmt_ *stmt.Stmt) {\n\tnop_stmt := stmt_.NopStmt()\n\n\top_code := this.ConvertROpCode(nop_stmt.OpCode())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZ(op_code)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRciStmt(stmt_ *stmt.Stmt) {\n\trci_stmt := stmt_.RciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rci_stmt.Rc())\n\n\top_code := this.ConvertROpCode(rci_stmt.OpCode())\n\tcondition := this.ConvertCondition(rci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rci_stmt.Rc())\n\n\t\tinstruction_.InitRci(op_code, rc, condition, pc)\n\t} else {\n\t\tinstruction_.InitZci(op_code, condition, pc)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRiciStmt(stmt_ *stmt.Stmt) {\n\trici_stmt := stmt_.RiciStmt()\n\n\top_code := this.ConvertRiciOpCode(rici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rici_stmt.Imm())\n\tcondition := this.ConvertCondition(rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRirciStmt(stmt_ *stmt.Stmt) {\n\trirci_stmt := stmt_.RirciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rirci_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rirci_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rirci_stmt.Imm())\n\tra := this.ConvertSrcReg(rirci_stmt.Ra())\n\tcondition := this.ConvertCondition(rirci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rirci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rirci_stmt.Rc())\n\n\t\tinstruction_.InitRirci(op_code, rc, imm, ra, condition, pc)\n\t} else {\n\t\tinstruction_.InitZirci(op_code, imm, ra, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRircStmt(stmt_ *stmt.Stmt) {\n\trirc_stmt := stmt_.RircStmt()\n\n\tis_zero_reg := this.IsZeroReg(rirc_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rirc_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rirc_stmt.Imm())\n\tra := this.ConvertSrcReg(rirc_stmt.Ra())\n\tcondition := this.ConvertCondition(rirc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rirc_stmt.Rc())\n\n\t\tinstruction_.InitRirc(op_code, rc, imm, ra, condition)\n\t} else {\n\t\tinstruction_.InitZirc(op_code, imm, ra, condition)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRirStmt(stmt_ *stmt.Stmt) {\n\trir_stmt := stmt_.RirStmt()\n\n\tis_zero_reg := this.IsZeroReg(rir_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rir_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rir_stmt.Imm())\n\tra := this.ConvertSrcReg(rir_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rir_stmt.Rc())\n\n\t\tinstruction_.InitRir(op_code, rc, imm, ra)\n\t} else {\n\t\tinstruction_.InitZir(op_code, imm, ra)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrciStmt(stmt_ *stmt.Stmt) {\n\trrci_stmt := stmt_.RrciStmt()\n\n\top_code := this.ConvertRrOpCode(rrci_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrci_stmt.Ra())\n\tcondition := this.ConvertCondition(rrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t} else if op_code == instruction.SUB {\n\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRirci(op_code, rc, imm, ra, condition, pc)\n\t} else if op_code == instruction.XOR {\n\t\tis_zero_reg := this.IsZeroReg(rrci_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t\t} else {\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t\t}\n\t} else {\n\t\tis_zero_reg := this.IsZeroReg(rrci_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\n\t\t\tinstruction_.InitRrci(op_code, rc, ra, condition, pc)\n\t\t} else {\n\t\t\tinstruction_.InitZrci(op_code, ra, condition, pc)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrcStmt(stmt_ *stmt.Stmt) {\n\trrc_stmt := stmt_.RrcStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrc_stmt.Rc())\n\n\top_code := this.ConvertRrOpCode(rrc_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrc_stmt.Ra())\n\tcondition := this.ConvertCondition(rrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrc_stmt.Rc())\n\n\t\tinstruction_.InitRrc(op_code, rc, ra, condition)\n\t} else {\n\t\tinstruction_.InitZrc(op_code, ra, condition)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRriciStmt(stmt_ *stmt.Stmt) {\n\trrici_stmt := stmt_.RriciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrici_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rrici_stmt.Imm())\n\tcondition := this.ConvertCondition(rrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrici_stmt.Rc())\n\n\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRricStmt(stmt_ *stmt.Stmt) {\n\trric_stmt := stmt_.RricStmt()\n\n\tis_zero_reg := this.IsZeroReg(rric_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rric_stmt.OpCode())\n\tra := this.ConvertSrcReg(rric_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rric_stmt.Imm())\n\tcondition := this.ConvertCondition(rric_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rric_stmt.Rc())\n\n\t\tif condition != cc.FALSE {\n\t\t\tinstruction_.InitRric(op_code, rc, ra, imm, condition)\n\t\t} else {\n\t\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t\t}\n\t} else {\n\t\tif condition != cc.FALSE {\n\t\t\tinstruction_.InitZric(op_code, ra, imm, condition)\n\t\t} else {\n\t\t\tinstruction_.InitZrif(op_code, ra, imm, condition)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRriStmt(stmt_ *stmt.Stmt) {\n\trri_stmt := stmt_.RriStmt()\n\n\tis_zero_reg := this.IsZeroReg(rri_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(rri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.ANDN || op_code == instruction.NAND || op_code == instruction.NOR ||\n\t\top_code == instruction.NXOR ||\n\t\top_code == instruction.ORN {\n\t\trc := this.ConvertGpReg(rri_stmt.Rc())\n\t\tcondition := cc.FALSE\n\n\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t} else if !is_zero_reg {\n\t\trc := this.ConvertGpReg(rri_stmt.Rc())\n\n\t\tinstruction_.InitRri(op_code, rc, ra, imm)\n\t} else {\n\t\tinstruction_.InitZri(op_code, ra, imm)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrciStmt(stmt_ *stmt.Stmt) {\n\trrrci_stmt := stmt_.RrrciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrci_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrrci_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrci_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrci_stmt.Rb())\n\tcondition := this.ConvertCondition(rrrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrci_stmt.Rc())\n\n\t\tinstruction_.InitRrrci(op_code, rc, ra, rb, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrrci(op_code, ra, rb, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrcStmt(stmt_ *stmt.Stmt) {\n\trrrc_stmt := stmt_.RrrcStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrc_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrrc_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrc_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrc_stmt.Rb())\n\tcondition := this.ConvertCondition(rrrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrc_stmt.Rc())\n\n\t\tinstruction_.InitRrrc(op_code, rc, ra, rb, condition)\n\t} else {\n\t\tinstruction_.InitZrrc(op_code, ra, rb, condition)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrriciStmt(stmt_ *stmt.Stmt) {\n\trrrici_stmt := stmt_.RrriciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrici_stmt.Rc())\n\n\top_code := this.ConvertRrriOpCode(rrrici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrici_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrici_stmt.Rb())\n\timm := this.EvaluateProgramCounter(rrrici_stmt.Imm())\n\tcondition := this.ConvertCondition(rrrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrici_stmt.Rc())\n\n\t\tinstruction_.InitRrrici(op_code, rc, ra, rb, imm, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrrici(op_code, ra, rb, imm, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrriStmt(stmt_ *stmt.Stmt) {\n\trrri_stmt := stmt_.RrriStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrri_stmt.Rc())\n\n\top_code := this.ConvertRrriOpCode(rrri_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrri_stmt.Ra())\n\trb := this.ConvertSrcReg(rrri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(rrri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrri_stmt.Rc())\n\n\t\tinstruction_.InitRrri(op_code, rc, ra, rb, imm)\n\t} else {\n\t\tinstruction_.InitZrri(op_code, ra, rb, imm)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrStmt(stmt_ *stmt.Stmt) {\n\trrr_stmt := stmt_.RrrStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrr_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrr_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrr_stmt.Ra())\n\trb := this.ConvertSrcReg(rrr_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrr_stmt.Rc())\n\n\t\tinstruction_.InitRrr(op_code, rc, ra, rb)\n\t} else {\n\t\tinstruction_.InitZrr(op_code, ra, rb)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrStmt(stmt_ *stmt.Stmt) {\n\trr_stmt := stmt_.RrStmt()\n\n\top_code := this.ConvertRrOpCode(rr_stmt.OpCode())\n\tra := this.ConvertSrcReg(rr_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\timm := int64(0)\n\t\tcondition := cc.FALSE\n\n\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t} else if op_code == instruction.SUB {\n\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRir(op_code, rc, imm, ra)\n\t} else if op_code == instruction.XOR {\n\t\tis_zero_reg := this.IsZeroReg(rr_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitRri(op_code, rc, ra, imm)\n\t\t} else {\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitZri(op_code, ra, imm)\n\t\t}\n\t} else {\n\t\tis_zero_reg := this.IsZeroReg(rr_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\n\t\t\tinstruction_.InitRr(op_code, rc, ra)\n\t\t} else {\n\t\t\tinstruction_.InitZr(op_code, ra)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRStmt(stmt_ *stmt.Stmt) {\n\tr_stmt := stmt_.RStmt()\n\n\tis_zero_reg := this.IsZeroReg(r_stmt.Rc())\n\n\top_code := this.ConvertROpCode(r_stmt.OpCode())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(r_stmt.Rc())\n\n\t\tinstruction_.InitR(op_code, rc)\n\t} else {\n\t\tinstruction_.InitZ(op_code)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSErriStmt(stmt_ *stmt.Stmt) {\n\ts_erri_stmt := stmt_.SErriStmt()\n\n\top_code := this.ConvertLoadOpCode(s_erri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_erri_stmt.Suffix(), instruction.ERRI)\n\tendian := this.ConvertEndian(s_erri_stmt.Endian())\n\tdc := this.ConvertPairReg(s_erri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_erri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(s_erri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSErri(op_code, suffix, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRciStmt(stmt_ *stmt.Stmt) {\n\ts_rci_stmt := stmt_.SRciStmt()\n\n\top_code := this.ConvertROpCode(s_rci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rci_stmt.Suffix(), instruction.RCI)\n\tdc := this.ConvertPairReg(s_rci_stmt.Dc())\n\tcondition := this.ConvertCondition(s_rci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRci(op_code, suffix, dc, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRirciStmt(stmt_ *stmt.Stmt) {\n\ts_rirci_stmt := stmt_.SRirciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rirci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rirci_stmt.Suffix(), instruction.RIRCI)\n\tdc := this.ConvertPairReg(s_rirci_stmt.Dc())\n\timm := this.EvaluateProgramCounter(s_rirci_stmt.Imm())\n\tra := this.ConvertSrcReg(s_rirci_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rirci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rirci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRirci(op_code, suffix, dc, imm, ra, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRircStmt(stmt_ *stmt.Stmt) {\n\ts_rirc_stmt := stmt_.SRircStmt()\n\n\top_code := this.ConvertRriOpCode(s_rirc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rirc_stmt.Suffix(), instruction.RIRC)\n\tdc := this.ConvertPairReg(s_rirc_stmt.Dc())\n\timm := this.EvaluateProgramCounter(s_rirc_stmt.Imm())\n\tra := this.ConvertSrcReg(s_rirc_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rirc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRirc(op_code, suffix, dc, imm, ra, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrciStmt(stmt_ *stmt.Stmt) {\n\ts_rrci_stmt := stmt_.SRrciStmt()\n\n\top_code := this.ConvertRrOpCode(s_rrci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrci_stmt.Suffix(), instruction.RRCI)\n\tdc := this.ConvertPairReg(s_rrci_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrci_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\tif suffix == instruction.S_RRCI {\n\t\t\tsuffix = instruction.S_RRICI\n\t\t\timm := int64(0)\n\n\t\t\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\t\t} else {\n\t\t\tsuffix = instruction.U_RRICI\n\t\t\timm := int64(0)\n\n\t\t\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\t\t}\n\t} else {\n\t\tinstruction_.InitSRrci(op_code, suffix, dc, ra, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrcStmt(stmt_ *stmt.Stmt) {\n\ts_rrc_stmt := stmt_.SRrcStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrc_stmt.Suffix(), instruction.RRC)\n\tdc := this.ConvertPairReg(s_rrc_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrc_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrc(op_code, suffix, dc, ra, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRriciStmt(stmt_ *stmt.Stmt) {\n\ts_rrici_stmt := stmt_.SRriciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrici_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrici_stmt.Suffix(), instruction.RRICI)\n\tdc := this.ConvertPairReg(s_rrici_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rrici_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRricStmt(stmt_ *stmt.Stmt) {\n\ts_rric_stmt := stmt_.SRricStmt()\n\n\top_code := this.ConvertRriOpCode(s_rric_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rric_stmt.Suffix(), instruction.RRIC)\n\tdc := this.ConvertPairReg(s_rric_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rric_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rric_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rric_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif condition != cc.FALSE {\n\t\tinstruction_.InitSRric(op_code, suffix, dc, ra, imm, condition)\n\t} else {\n\t\tinstruction_.InitSRrif(op_code, suffix, dc, ra, imm, condition)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRriStmt(stmt_ *stmt.Stmt) {\n\ts_rri_stmt := stmt_.SRriStmt()\n\n\top_code := this.ConvertRriOpCode(s_rri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rri_stmt.Suffix(), instruction.RRI)\n\tdc := this.ConvertPairReg(s_rri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRri(op_code, suffix, dc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrciStmt(stmt_ *stmt.Stmt) {\n\ts_rrrci_stmt := stmt_.SRrrciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrci_stmt.Suffix(), instruction.RRRCI)\n\tdc := this.ConvertPairReg(s_rrrci_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrci_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrci_stmt.Rb())\n\tcondition := this.ConvertCondition(s_rrrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrci(op_code, suffix, dc, ra, rb, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrcStmt(stmt_ *stmt.Stmt) {\n\ts_rrrc_stmt := stmt_.SRrrcStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrc_stmt.Suffix(), instruction.RRRC)\n\tdc := this.ConvertPairReg(s_rrrc_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrc_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrc_stmt.Rb())\n\tcondition := this.ConvertCondition(s_rrrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrc(op_code, suffix, dc, ra, rb, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrriciStmt(stmt_ *stmt.Stmt) {\n\ts_rrrici_stmt := stmt_.SRrriciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrici_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrici_stmt.Suffix(), instruction.RRRICI)\n\tdc := this.ConvertPairReg(s_rrrici_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrici_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrici_stmt.Rb())\n\timm := this.EvaluateProgramCounter(s_rrrici_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rrrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrici(op_code, suffix, dc, ra, rb, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrriStmt(stmt_ *stmt.Stmt) {\n\ts_rrri_stmt := stmt_.SRrriStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrri_stmt.Suffix(), instruction.RRRI)\n\tdc := this.ConvertPairReg(s_rrri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrri_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(s_rrri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrri(op_code, suffix, dc, ra, rb, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrStmt(stmt_ *stmt.Stmt) {\n\ts_rrr_stmt := stmt_.SRrrStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrr_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrr_stmt.Suffix(), instruction.RRR)\n\tdc := this.ConvertPairReg(s_rrr_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrr_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrr_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrr(op_code, suffix, dc, ra, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrStmt(stmt_ *stmt.Stmt) {\n\ts_rr_stmt := stmt_.SRrStmt()\n\n\top_code := this.ConvertRrOpCode(s_rr_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rr_stmt.Suffix(), instruction.RR)\n\tdc := this.ConvertPairReg(s_rr_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rr_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\tif suffix == instruction.S_RR {\n\t\t\timm := int64(0)\n\t\t\tcondition := cc.FALSE\n\n\t\t\tinstruction_.InitSRrif(op_code, instruction.S_RRIF, dc, ra, imm, condition)\n\t\t} else if suffix == instruction.U_RR {\n\t\t\timm := int64(0)\n\t\t\tcondition := cc.FALSE\n\n\t\t\tinstruction_.InitSRrif(op_code, instruction.U_RRIF, dc, ra, imm, condition)\n\t\t} else {\n\t\t\terr := errors.New(\"suffix is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\tinstruction_.InitSRr(op_code, suffix, dc, ra)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRStmt(stmt_ *stmt.Stmt) {\n\ts_r_stmt := stmt_.SRStmt()\n\n\top_code := this.ConvertRriOpCode(s_r_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_r_stmt.Suffix(), instruction.R)\n\tdc := this.ConvertPairReg(s_r_stmt.Dc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSR(op_code, suffix, dc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkBkpStmt(stmt_ *stmt.Stmt) {\n\top_code := instruction.FAULT\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitI(op_code, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkBootRiStmt(stmt_ *stmt.Stmt) {\n\tboot_ri_stmt := stmt_.BootRiStmt()\n\n\top_code := this.ConvertRiciOpCode(boot_ri_stmt.OpCode())\n\tra := this.ConvertSrcReg(boot_ri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(boot_ri_stmt.Imm())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkCallRiStmt(stmt_ *stmt.Stmt) {\n\tcall_ri_stmt := stmt_.CallRiStmt()\n\n\top_code := instruction.CALL\n\trc := this.ConvertGpReg(call_ri_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(call_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkCallRrStmt(stmt_ *stmt.Stmt) {\n\tcall_rr_stmt := stmt_.CallRrStmt()\n\n\top_code := instruction.CALL\n\trc := this.ConvertGpReg(call_rr_stmt.Rc())\n\tra := this.ConvertSrcReg(call_rr_stmt.Ra())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDivStepDrdiStmt(stmt_ *stmt.Stmt) {\n\tdiv_step_drdi_stmt := stmt_.DivStepDrdiStmt()\n\n\top_code := this.ConvertDrdiciOpCode(div_step_drdi_stmt.OpCode())\n\tdc := this.ConvertPairReg(div_step_drdi_stmt.Dc())\n\tra := this.ConvertSrcReg(div_step_drdi_stmt.Ra())\n\tdb := this.ConvertPairReg(div_step_drdi_stmt.Db())\n\timm := this.EvaluateProgramCounter(div_step_drdi_stmt.Imm())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDrdici(op_code, dc, ra, db, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJeqRiiStmt(stmt_ *stmt.Stmt) {\n\tjeq_rii_stmt := stmt_.JeqRiiStmt()\n\n\top_code := this.ConvertJumpOpCode(jeq_rii_stmt.OpCode())\n\tra := this.ConvertSrcReg(jeq_rii_stmt.Ra())\n\timm := this.EvaluateProgramCounter(jeq_rii_stmt.Imm())\n\tcondition := this.ConvertJumpCondition(jeq_rii_stmt.OpCode())\n\tpc := this.EvaluateProgramCounter(jeq_rii_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJeqRriStmt(stmt_ *stmt.Stmt) {\n\tjeq_rri_stmt := stmt_.JeqRriStmt()\n\n\top_code := this.ConvertJumpOpCode(jeq_rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(jeq_rri_stmt.Ra())\n\trb := this.ConvertSrcReg(jeq_rri_stmt.Rb())\n\tcondition := this.ConvertJumpCondition(jeq_rri_stmt.OpCode())\n\tpc := this.EvaluateProgramCounter(jeq_rri_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZrrci(op_code, ra, rb, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJnzRiStmt(stmt_ *stmt.Stmt) {\n\tjnz_ri_stmt := stmt_.JnzRiStmt()\n\n\top_code := this.ConvertJumpOpCode(jnz_ri_stmt.OpCode())\n\tra := this.ConvertSrcReg(jnz_ri_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.SUB {\n\t\timm := int64(0)\n\t\tcondition := this.ConvertJumpCondition(jnz_ri_stmt.OpCode())\n\t\tpc := this.EvaluateProgramCounter(jnz_ri_stmt.Pc())\n\n\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t} else if op_code == instruction.CALL {\n\t\timm := this.EvaluateProgramCounter(jnz_ri_stmt.Pc())\n\n\t\tinstruction_.InitZri(op_code, ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJumpIStmt(stmt_ *stmt.Stmt) {\n\tjump_i_stmt := stmt_.JumpIStmt()\n\n\top_code := instruction.CALL\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(jump_i_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZri(op_code, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJumpRStmt(stmt_ *stmt.Stmt) {\n\tjump_r_stmt := stmt_.JumpRStmt()\n\n\top_code := instruction.CALL\n\tra := this.ConvertSrcReg(jump_r_stmt.Ra())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZri(op_code, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLbsRriStmt(stmt_ *stmt.Stmt) {\n\tlbs_rri_stmt := stmt_.LbsRriStmt()\n\n\top_code := this.ConvertLoadOpCode(lbs_rri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\trc := this.ConvertGpReg(lbs_rri_stmt.Rc())\n\tra := this.ConvertSrcReg(lbs_rri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(lbs_rri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErri(op_code, endian, rc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLbsSRriStmt(stmt_ *stmt.Stmt) {\n\tlbs_s_rri_stmt := stmt_.LbsSRriStmt()\n\n\top_code := this.ConvertLoadOpCode(lbs_s_rri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(lbs_s_rri_stmt.Suffix(), instruction.ERRI)\n\tendian := instruction.LITTLE\n\tdc := this.ConvertPairReg(lbs_s_rri_stmt.Dc())\n\tra := this.ConvertSrcReg(lbs_s_rri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(lbs_s_rri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSErri(op_code, suffix, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLdDriStmt(stmt_ *stmt.Stmt) {\n\tld_dri_stmt := stmt_.LdDriStmt()\n\n\top_code := this.ConvertLoadOpCode(ld_dri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tdc := this.ConvertPairReg(ld_dri_stmt.Dc())\n\tra := this.ConvertSrcReg(ld_dri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(ld_dri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitEdri(op_code, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMovdDdStmt(stmt_ *stmt.Stmt) {\n\tmovd_dd_stmt := stmt_.MovdDdStmt()\n\n\top_code := this.ConvertDdciOpCode(movd_dd_stmt.OpCode())\n\tdc := this.ConvertPairReg(movd_dd_stmt.Dc())\n\tdb := this.ConvertPairReg(movd_dd_stmt.Db())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDdci(op_code, dc, db, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveRiciStmt(stmt_ *stmt.Stmt) {\n\tmove_rici_stmt := stmt_.MoveRiciStmt()\n\n\top_code := instruction.OR\n\trc := this.ConvertGpReg(move_rici_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_rici_stmt.Imm())\n\tcondition := this.ConvertCondition(move_rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(move_rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveRiStmt(stmt_ *stmt.Stmt) {\n\tmove_ri_stmt := stmt_.MoveRiStmt()\n\n\top_code := instruction.OR\n\trc := this.ConvertGpReg(move_ri_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveSRiciStmt(stmt_ *stmt.Stmt) {\n\tmove_s_rici_stmt := stmt_.MoveSRiciStmt()\n\n\top_code := instruction.OR\n\tsuffix := this.ConvertSuffix(move_s_rici_stmt.Suffix(), instruction.RRICI)\n\tdc := this.ConvertPairReg(move_s_rici_stmt.Dc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_s_rici_stmt.Imm())\n\tcondition := this.ConvertCondition(move_s_rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(move_s_rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveSRiStmt(stmt_ *stmt.Stmt) {\n\tmove_s_ri_stmt := stmt_.MoveSRiStmt()\n\n\t// NOTE(bongjoon.hyun@gmail.com): move.s is implemented by using and.s:rki\n\top_code := instruction.AND\n\tsuffix := this.ConvertSuffix(move_s_ri_stmt.Suffix(), instruction.RRI)\n\tdc := this.ConvertPairReg(move_s_ri_stmt.Dc())\n\n\tlneg_reg := new(reg_descriptor.SpRegDescriptor)\n\t*lneg_reg = reg_descriptor.LNEG\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(lneg_reg)\n\n\timm := this.EvaluateProgramCounter(move_s_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRri(op_code, suffix, dc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbIdRiiStmt(stmt_ *stmt.Stmt) {\n\tsb_id_rii_stmt := stmt_.SbIdRiiStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_id_rii_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_id_rii_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_id_rii_stmt.Off())\n\timm := this.EvaluateProgramCounter(sb_id_rii_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbIdRiStmt(stmt_ *stmt.Stmt) {\n\tsb_id_ri_stmt := stmt_.SbIdRiStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_id_ri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_id_ri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_id_ri_stmt.Off())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbRirStmt(stmt_ *stmt.Stmt) {\n\tsb_rir_stmt := stmt_.SbRirStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_rir_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_rir_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_rir_stmt.Off())\n\trb := this.ConvertSrcReg(sb_rir_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErir(op_code, endian, ra, off, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSdRidStmt(stmt_ *stmt.Stmt) {\n\tsb_rid_stmt := stmt_.SdRidStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_rid_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_rid_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_rid_stmt.Off())\n\tdb := this.ConvertPairReg(sb_rid_stmt.Db())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErid(op_code, endian, ra, off, db)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkStopStmt(stmt_ *stmt.Stmt) {\n\top_code := instruction.STOP\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitCi(op_code, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkTimeCfgRStmt(stmt_ *stmt.Stmt) {\n\ttime_cfg_r_stmt := stmt_.TimeCfgRStmt()\n\n\top_code := instruction.TIME_CFG\n\tra := this.ConvertSrcReg(time_cfg_r_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZr(op_code, ra)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tlabel_name := token.Attribute()\n\n\tif label_name != \"__sys_used_mram_end\" {\n\t\tthis.executable.CurSection().CheckoutLabel(label_name)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n\nfunc (this *InstructionAssigner) ConvertCiOpCode(op_code *expr.Expr) instruction.OpCode {\n\tci_op_code_expr := op_code.CiOpCodeExpr()\n\n\ttoken_type := ci_op_code_expr.Token().TokenType()\n\tif token_type == lexer.STOP {\n\t\treturn instruction.STOP\n\t} else {\n\t\terr := errors.New(\"CI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDdciOpCode(op_code *expr.Expr) instruction.OpCode {\n\tddci_op_code_expr := op_code.DdciOpCodeExpr()\n\n\ttoken_type := ddci_op_code_expr.Token().TokenType()\n\tif token_type == lexer.MOVD {\n\t\treturn instruction.MOVD\n\t} else if token_type == lexer.SWAPD {\n\t\treturn instruction.SWAPD\n\t} else {\n\t\terr := errors.New(\"DDCI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDmaRriOpCode(op_code *expr.Expr) instruction.OpCode {\n\tdma_rri_op_code_expr := op_code.DmaRriOpCodeExpr()\n\n\ttoken_type := dma_rri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LDMA {\n\t\treturn instruction.LDMA\n\t} else if token_type == lexer.LDMAI {\n\t\treturn instruction.LDMAI\n\t} else if token_type == lexer.SDMA {\n\t\treturn instruction.SDMA\n\t} else {\n\t\terr := errors.New(\"DMA_RRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDrdiciOpCode(op_code *expr.Expr) instruction.OpCode {\n\tdrdici_op_code_expr := op_code.DrdiciOpCodeExpr()\n\n\ttoken_type := drdici_op_code_expr.Token().TokenType()\n\tif token_type == lexer.DIV_STEP {\n\t\treturn instruction.DIV_STEP\n\t} else if token_type == lexer.MUL_STEP {\n\t\treturn instruction.MUL_STEP\n\t} else {\n\t\terr := errors.New(\"DRDICI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertIOpCode(op_code *expr.Expr) instruction.OpCode {\n\ti_op_code_expr := op_code.IOpCodeExpr()\n\n\ttoken_type := i_op_code_expr.Token().TokenType()\n\tif token_type == lexer.FAULT {\n\t\treturn instruction.FAULT\n\t} else {\n\t\terr := errors.New(\"I op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRiciOpCode(op_code *expr.Expr) instruction.OpCode {\n\trici_op_code_expr := op_code.RiciOpCodeExpr()\n\n\ttoken_type := rici_op_code_expr.Token().TokenType()\n\tif token_type == lexer.ACQUIRE {\n\t\treturn instruction.ACQUIRE\n\t} else if token_type == lexer.RELEASE {\n\t\treturn instruction.RELEASE\n\t} else if token_type == lexer.BOOT {\n\t\treturn instruction.BOOT\n\t} else if token_type == lexer.RESUME {\n\t\treturn instruction.RESUME\n\t} else {\n\t\terr := errors.New(\"I op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertROpCode(op_code *expr.Expr) instruction.OpCode {\n\tr_op_code_expr := op_code.ROpCodeExpr()\n\n\ttoken_type := r_op_code_expr.Token().TokenType()\n\tif token_type == lexer.TIME {\n\t\treturn instruction.TIME\n\t} else if token_type == lexer.NOP {\n\t\treturn instruction.NOP\n\t} else {\n\t\terr := errors.New(\"R op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRrOpCode(op_code *expr.Expr) instruction.OpCode {\n\trr_op_code_expr := op_code.RrOpCodeExpr()\n\n\ttoken_type := rr_op_code_expr.Token().TokenType()\n\tif token_type == lexer.CAO {\n\t\treturn instruction.CAO\n\t} else if token_type == lexer.CLO {\n\t\treturn instruction.CLO\n\t} else if token_type == lexer.CLS {\n\t\treturn instruction.CLS\n\t} else if token_type == lexer.CLZ {\n\t\treturn instruction.CLZ\n\t} else if token_type == lexer.EXTSB {\n\t\treturn instruction.EXTSB\n\t} else if token_type == lexer.EXTSH {\n\t\treturn instruction.EXTSH\n\t} else if token_type == lexer.EXTUB {\n\t\treturn instruction.EXTUB\n\t} else if token_type == lexer.EXTUH {\n\t\treturn instruction.EXTUH\n\t} else if token_type == lexer.SATS {\n\t\treturn instruction.SATS\n\t} else if token_type == lexer.TIME_CFG {\n\t\treturn instruction.TIME_CFG\n\t} else if token_type == lexer.MOVE {\n\t\treturn instruction.OR\n\t} else if token_type == lexer.NEG {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.NOT {\n\t\treturn instruction.XOR\n\t} else {\n\t\terr := errors.New(\"RR op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRriOpCode(op_code *expr.Expr) instruction.OpCode {\n\trri_op_code_expr := op_code.RriOpCodeExpr()\n\n\ttoken_type := rri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.ADD {\n\t\treturn instruction.ADD\n\t} else if token_type == lexer.ADDC {\n\t\treturn instruction.ADDC\n\t} else if token_type == lexer.AND {\n\t\treturn instruction.AND\n\t} else if token_type == lexer.ANDN {\n\t\treturn instruction.ANDN\n\t} else if token_type == lexer.ASR {\n\t\treturn instruction.ASR\n\t} else if token_type == lexer.CMPB4 {\n\t\treturn instruction.CMPB4\n\t} else if token_type == lexer.LSL {\n\t\treturn instruction.LSL\n\t} else if token_type == lexer.LSL1 {\n\t\treturn instruction.LSL1\n\t} else if token_type == lexer.LSL1X {\n\t\treturn instruction.LSL1X\n\t} else if token_type == lexer.LSLX {\n\t\treturn instruction.LSLX\n\t} else if token_type == lexer.LSR {\n\t\treturn instruction.LSR\n\t} else if token_type == lexer.LSR1 {\n\t\treturn instruction.LSR1\n\t} else if token_type == lexer.LSR1X {\n\t\treturn instruction.LSR1X\n\t} else if token_type == lexer.LSRX {\n\t\treturn instruction.LSRX\n\t} else if token_type == lexer.MUL_SH_SH {\n\t\treturn instruction.MUL_SH_SH\n\t} else if token_type == lexer.MUL_SH_SL {\n\t\treturn instruction.MUL_SH_SL\n\t} else if token_type == lexer.MUL_SH_UH {\n\t\treturn instruction.MUL_SH_UH\n\t} else if token_type == lexer.MUL_SH_UL {\n\t\treturn instruction.MUL_SH_UL\n\t} else if token_type == lexer.MUL_SL_SH {\n\t\treturn instruction.MUL_SL_SH\n\t} else if token_type == lexer.MUL_SL_SL {\n\t\treturn instruction.MUL_SL_SL\n\t} else if token_type == lexer.MUL_SL_UH {\n\t\treturn instruction.MUL_SL_UH\n\t} else if token_type == lexer.MUL_SL_UL {\n\t\treturn instruction.MUL_SL_UL\n\t} else if token_type == lexer.MUL_UH_UH {\n\t\treturn instruction.MUL_UH_UH\n\t} else if token_type == lexer.MUL_UH_UL {\n\t\treturn instruction.MUL_UH_UL\n\t} else if token_type == lexer.MUL_UL_UH {\n\t\treturn instruction.MUL_UL_UH\n\t} else if token_type == lexer.MUL_UL_UL {\n\t\treturn instruction.MUL_UL_UL\n\t} else if token_type == lexer.NAND {\n\t\treturn instruction.NAND\n\t} else if token_type == lexer.NOR {\n\t\treturn instruction.NOR\n\t} else if token_type == lexer.NXOR {\n\t\treturn instruction.NXOR\n\t} else if token_type == lexer.OR {\n\t\treturn instruction.OR\n\t} else if token_type == lexer.ORN {\n\t\treturn instruction.ORN\n\t} else if token_type == lexer.ROL {\n\t\treturn instruction.ROL\n\t} else if token_type == lexer.ROR {\n\t\treturn instruction.ROR\n\t} else if token_type == lexer.RSUB {\n\t\treturn instruction.RSUB\n\t} else if token_type == lexer.RSUBC {\n\t\treturn instruction.RSUBC\n\t} else if token_type == lexer.SUB {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.SUBC {\n\t\treturn instruction.SUBC\n\t} else if token_type == lexer.XOR {\n\t\treturn instruction.XOR\n\t} else if token_type == lexer.CALL {\n\t\treturn instruction.CALL\n\t} else if token_type == lexer.HASH {\n\t\treturn instruction.HASH\n\t} else {\n\t\terr := errors.New(\"RRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRrriOpCode(op_code *expr.Expr) instruction.OpCode {\n\trrri_op_code_expr := op_code.RrriOpCodeExpr()\n\n\ttoken_type := rrri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LSL_ADD {\n\t\treturn instruction.LSL_ADD\n\t} else if token_type == lexer.LSL_SUB {\n\t\treturn instruction.LSL_SUB\n\t} else if token_type == lexer.LSR_ADD {\n\t\treturn instruction.LSR_ADD\n\t} else if token_type == lexer.ROL_ADD {\n\t\treturn instruction.ROL_ADD\n\t} else {\n\t\terr := errors.New(\"RRRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertLoadOpCode(op_code *expr.Expr) instruction.OpCode {\n\tload_op_code_expr := op_code.LoadOpCodeExpr()\n\n\ttoken_type := load_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LBS {\n\t\treturn instruction.LBS\n\t} else if token_type == lexer.LBU {\n\t\treturn instruction.LBU\n\t} else if token_type == lexer.LD {\n\t\treturn instruction.LD\n\t} else if token_type == lexer.LHS {\n\t\treturn instruction.LHS\n\t} else if token_type == lexer.LHU {\n\t\treturn instruction.LHU\n\t} else if token_type == lexer.LW {\n\t\treturn instruction.LW\n\t} else {\n\t\terr := errors.New(\"load op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertStoreOpCode(op_code *expr.Expr) instruction.OpCode {\n\tstore_op_code_expr := op_code.StoreOpCodeExpr()\n\n\ttoken_type := store_op_code_expr.Token().TokenType()\n\tif token_type == lexer.SB {\n\t\treturn instruction.SB\n\t} else if token_type == lexer.SB_ID {\n\t\treturn instruction.SB_ID\n\t} else if token_type == lexer.SD {\n\t\treturn instruction.SD\n\t} else if token_type == lexer.SD_ID {\n\t\treturn instruction.SD_ID\n\t} else if token_type == lexer.SH {\n\t\treturn instruction.SH\n\t} else if token_type == lexer.SH_ID {\n\t\treturn instruction.SH_ID\n\t} else if token_type == lexer.SW {\n\t\treturn instruction.SW\n\t} else if token_type == lexer.SW_ID {\n\t\treturn instruction.SW_ID\n\t} else {\n\t\terr := errors.New(\"store op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertJumpOpCode(op_code *expr.Expr) instruction.OpCode {\n\tjump_op_code_expr := op_code.JumpOpCodeExpr()\n\n\ttoken_type := jump_op_code_expr.Token().TokenType()\n\tif token_type == lexer.JEQ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGES {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGEU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGTS {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGTU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLES {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLEU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLTS {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLTU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JNEQ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JNZ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JUMP {\n\t\treturn instruction.CALL\n\t} else if token_type == lexer.JZ {\n\t\treturn instruction.SUB\n\t} else {\n\t\terr := errors.New(\"jump op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertSuffix(\n\tsuffix *expr.Expr,\n\tbase instruction.Suffix,\n) instruction.Suffix {\n\tsuffix_expr := suffix.SuffixExpr()\n\n\ttoken_type := suffix_expr.Token().TokenType()\n\tif token_type == lexer.S {\n\t\tif base == instruction.ERRI {\n\t\t\treturn instruction.S_ERRI\n\t\t} else if base == instruction.RCI {\n\t\t\treturn instruction.S_RCI\n\t\t} else if base == instruction.RIRCI {\n\t\t\treturn instruction.S_RIRCI\n\t\t} else if base == instruction.RIRC {\n\t\t\treturn instruction.S_RIRC\n\t\t} else if base == instruction.RRCI {\n\t\t\treturn instruction.S_RRCI\n\t\t} else if base == instruction.RRC {\n\t\t\treturn instruction.S_RRC\n\t\t} else if base == instruction.RRICI {\n\t\t\treturn instruction.S_RRICI\n\t\t} else if base == instruction.RRIC {\n\t\t\treturn instruction.S_RRIC\n\t\t} else if base == instruction.RRI {\n\t\t\treturn instruction.S_RRI\n\t\t} else if base == instruction.RRRCI {\n\t\t\treturn instruction.S_RRRCI\n\t\t} else if base == instruction.RRRC {\n\t\t\treturn instruction.S_RRRC\n\t\t} else if base == instruction.RRRICI {\n\t\t\treturn instruction.S_RRRICI\n\t\t} else if base == instruction.RRRI {\n\t\t\treturn instruction.S_RRRI\n\t\t} else if base == instruction.RRR {\n\t\t\treturn instruction.S_RRR\n\t\t} else if base == instruction.RR {\n\t\t\treturn instruction.S_RR\n\t\t} else if base == instruction.R {\n\t\t\treturn instruction.S_R\n\t\t} else {\n\t\t\terr := errors.New(\"base is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if token_type == lexer.U {\n\t\tif base == instruction.ERRI {\n\t\t\treturn instruction.U_ERRI\n\t\t} else if base == instruction.RCI {\n\t\t\treturn instruction.U_RCI\n\t\t} else if base == instruction.RIRCI {\n\t\t\treturn instruction.U_RIRCI\n\t\t} else if base == instruction.RIRC {\n\t\t\treturn instruction.U_RIRC\n\t\t} else if base == instruction.RRCI {\n\t\t\treturn instruction.U_RRCI\n\t\t} else if base == instruction.RRC {\n\t\t\treturn instruction.U_RRC\n\t\t} else if base == instruction.RRICI {\n\t\t\treturn instruction.U_RRICI\n\t\t} else if base == instruction.RRIC {\n\t\t\treturn instruction.U_RRIC\n\t\t} else if base == instruction.RRI {\n\t\t\treturn instruction.U_RRI\n\t\t} else if base == instruction.RRRCI {\n\t\t\treturn instruction.U_RRRCI\n\t\t} else if base == instruction.RRRC {\n\t\t\treturn instruction.U_RRRC\n\t\t} else if base == instruction.RRRICI {\n\t\t\treturn instruction.U_RRRICI\n\t\t} else if base == instruction.RRRI {\n\t\t\treturn instruction.U_RRRI\n\t\t} else if base == instruction.RRR {\n\t\t\treturn instruction.U_RRR\n\t\t} else if base == instruction.RR {\n\t\t\treturn instruction.U_RR\n\t\t} else if base == instruction.R {\n\t\t\treturn instruction.U_R\n\t\t} else {\n\t\t\terr := errors.New(\"base is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertGpReg(expr_ *expr.Expr) *reg_descriptor.GpRegDescriptor {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\tindex, err := strconv.Atoi(src_reg_expr.Token().Attribute()[1:])\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\tgp_reg_descriptor.Init(index)\n\treturn gp_reg_descriptor\n}\n\nfunc (this *InstructionAssigner) ConvertSrcReg(expr_ *expr.Expr) *reg_descriptor.SrcRegDescriptor {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\ttoken := src_reg_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.GP_REG {\n\t\tgp_reg_descriptor := this.ConvertGpReg(expr_)\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitGpRegDescriptor(gp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ZERO_REG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ZERO\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ONE {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ONE\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID2 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID2\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID4 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID4\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID8 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID8\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.LNEG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.LNEG\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.MNEG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.MNEG\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else {\n\t\terr := errors.New(\"src reg is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertPairReg(\n\ttoken *lexer.Token,\n) *reg_descriptor.PairRegDescriptor {\n\tindex, err := strconv.Atoi(token.Attribute()[1:])\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tpair_reg_descriptor := new(reg_descriptor.PairRegDescriptor)\n\tpair_reg_descriptor.Init(index)\n\treturn pair_reg_descriptor\n}\n\nfunc (this *InstructionAssigner) ConvertCondition(expr_ *expr.Expr) cc.Condition {\n\tcondition_expr := expr_.ConditionExpr()\n\n\ttoken := condition_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.TRUE {\n\t\treturn cc.TRUE\n\t} else if token_type == lexer.FALSE {\n\t\treturn cc.FALSE\n\t} else if token_type == lexer.Z {\n\t\treturn cc.Z\n\t} else if token_type == lexer.NZ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.E {\n\t\treturn cc.E\n\t} else if token_type == lexer.O {\n\t\treturn cc.O\n\t} else if token_type == lexer.PL {\n\t\treturn cc.PL\n\t} else if token_type == lexer.MI {\n\t\treturn cc.MI\n\t} else if token_type == lexer.OV {\n\t\treturn cc.OV\n\t} else if token_type == lexer.NOV {\n\t\treturn cc.NOV\n\t} else if token_type == lexer.C {\n\t\treturn cc.C\n\t} else if token_type == lexer.NC {\n\t\treturn cc.NC\n\t} else if token_type == lexer.SZ {\n\t\treturn cc.SZ\n\t} else if token_type == lexer.SNZ {\n\t\treturn cc.SNZ\n\t} else if token_type == lexer.SPL {\n\t\treturn cc.SPL\n\t} else if token_type == lexer.SMI {\n\t\treturn cc.SMI\n\t} else if token_type == lexer.SO {\n\t\treturn cc.SO\n\t} else if token_type == lexer.SE {\n\t\treturn cc.SE\n\t} else if token_type == lexer.NC5 {\n\t\treturn cc.NC5\n\t} else if token_type == lexer.NC6 {\n\t\treturn cc.NC6\n\t} else if token_type == lexer.NC7 {\n\t\treturn cc.NC7\n\t} else if token_type == lexer.NC8 {\n\t\treturn cc.NC8\n\t} else if token_type == lexer.NC9 {\n\t\treturn cc.NC9\n\t} else if token_type == lexer.NC10 {\n\t\treturn cc.NC10\n\t} else if token_type == lexer.NC11 {\n\t\treturn cc.NC11\n\t} else if token_type == lexer.NC12 {\n\t\treturn cc.NC12\n\t} else if token_type == lexer.NC13 {\n\t\treturn cc.NC13\n\t} else if token_type == lexer.NC14 {\n\t\treturn cc.NC14\n\t} else if token_type == lexer.MAX {\n\t\treturn cc.MAX\n\t} else if token_type == lexer.NMAX {\n\t\treturn cc.NMAX\n\t} else if token_type == lexer.SH32 {\n\t\treturn cc.SH32\n\t} else if token_type == lexer.NSH32 {\n\t\treturn cc.NSH32\n\t} else if token_type == lexer.EQ {\n\t\treturn cc.EQ\n\t} else if token_type == lexer.NEQ {\n\t\treturn cc.NEQ\n\t} else if token_type == lexer.LTU {\n\t\treturn cc.LTU\n\t} else if token_type == lexer.LEU {\n\t\treturn cc.LEU\n\t} else if token_type == lexer.GTU {\n\t\treturn cc.GTU\n\t} else if token_type == lexer.GEU {\n\t\treturn cc.GEU\n\t} else if token_type == lexer.LTS {\n\t\treturn cc.LTS\n\t} else if token_type == lexer.LES {\n\t\treturn cc.LES\n\t} else if token_type == lexer.GTS {\n\t\treturn cc.GTS\n\t} else if token_type == lexer.GES {\n\t\treturn cc.GES\n\t} else if token_type == lexer.XZ {\n\t\treturn cc.XZ\n\t} else if token_type == lexer.XNZ {\n\t\treturn cc.XNZ\n\t} else if token_type == lexer.XLEU {\n\t\treturn cc.XLEU\n\t} else if token_type == lexer.XGTU {\n\t\treturn cc.XGTU\n\t} else if token_type == lexer.XLES {\n\t\treturn cc.XLES\n\t} else if token_type == lexer.XGTS {\n\t\treturn cc.XGTS\n\t} else if token_type == lexer.SMALL {\n\t\treturn cc.SMALL\n\t} else if token_type == lexer.LARGE {\n\t\treturn cc.LARGE\n\t} else {\n\t\terr := errors.New(\"condition is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertEndian(expr_ *expr.Expr) instruction.Endian {\n\tendian_expr := expr_.EndianExpr()\n\n\ttoken := endian_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.LITTLE {\n\t\treturn instruction.LITTLE\n\t} else if token_type == lexer.BIG {\n\t\treturn instruction.BIG\n\t} else {\n\t\terr := errors.New(\"endian is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertJumpCondition(op_code *expr.Expr) cc.Condition {\n\tjump_op_code_expr := op_code.JumpOpCodeExpr()\n\n\ttoken_type := jump_op_code_expr.Token().TokenType()\n\tif token_type == lexer.JEQ {\n\t\treturn cc.Z\n\t} else if token_type == lexer.JGES {\n\t\treturn cc.GES\n\t} else if token_type == lexer.JGEU {\n\t\treturn cc.GEU\n\t} else if token_type == lexer.JGTS {\n\t\treturn cc.GTS\n\t} else if token_type == lexer.JGTU {\n\t\treturn cc.GTU\n\t} else if token_type == lexer.JLES {\n\t\treturn cc.LES\n\t} else if token_type == lexer.JLEU {\n\t\treturn cc.LEU\n\t} else if token_type == lexer.JLTS {\n\t\treturn cc.LTS\n\t} else if token_type == lexer.JLTU {\n\t\treturn cc.LTU\n\t} else if token_type == lexer.JNEQ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.JNZ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.JZ {\n\t\treturn cc.Z\n\t} else {\n\t\terr := errors.New(\"jump op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateProgramCounter(expr_ *expr.Expr) int64 {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\n\tchild_expr := program_counter_expr.Expr()\n\tchild_expr_type := child_expr.ExprType()\n\tif child_expr_type == expr.PRIMARY {\n\t\treturn this.EvaluatePrimary(child_expr)\n\t} else if child_expr_type == expr.NEGATIVE_NUMBER {\n\t\treturn this.EvaluateNegativeNumber(child_expr)\n\t} else if child_expr_type == expr.BINARY_ADD {\n\t\treturn this.EvaluateBinaryAdd(child_expr)\n\t} else if child_expr_type == expr.BINARY_SUB {\n\t\treturn this.EvaluateBinarySub(child_expr)\n\t} else {\n\t\terr := errors.New(\"program counter expr is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluatePrimary(expr_ *expr.Expr) int64 {\n\tprimary_expr := expr_.PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.POSITIVIE_NUMBER {\n\t\treturn this.EvaluatePositiveNumber(token)\n\t} else if token_type == lexer.HEX_NUMBER {\n\t\treturn this.EvaluateHexNumber(token)\n\t} else if token_type == lexer.IDENTIFIER {\n\t\treturn this.EvaluateIdentifier(token)\n\t} else {\n\t\terr := errors.New(\"primary expr is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluatePositiveNumber(token *lexer.Token) int64 {\n\tvalue, err := strconv.ParseInt(token.Attribute(), 10, 64)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn value\n}\n\nfunc (this *InstructionAssigner) EvaluateHexNumber(token *lexer.Token) int64 {\n\tattribute := token.Attribute()\n\tvar value int64\n\tvar err error\n\tif attribute[:2] == \"0x\" {\n\t\tvalue, err = strconv.ParseInt(attribute[2:], 16, 64)\n\t} else {\n\t\tvalue, err = strconv.ParseInt(attribute, 16, 64)\n\t}\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn value\n}\n\nfunc (this *InstructionAssigner) EvaluateIdentifier(token *lexer.Token) int64 {\n\tname := token.Attribute()\n\n\tlabel := this.executable.Label(name)\n\tlinker_constant := this.linker_script.LinkerConstant(name)\n\n\tif label != nil {\n\t\tif linker_constant != nil {\n\t\t\terr := errors.New(\"label and linker constant both exist\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\treturn label.Address()\n\t} else if linker_constant != nil {\n\t\treturn linker_constant.Value()\n\t} else {\n\t\terr := errors.New(\"label and linker constant do not exist\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateNegativeNumber(expr_ *expr.Expr) int64 {\n\tnegative_number_expr := expr_.NegativeNumberExpr()\n\n\treturn -this.EvaluatePositiveNumber(negative_number_expr.Token())\n}\n\nfunc (this *InstructionAssigner) EvaluateBinaryAdd(expr_ *expr.Expr) int64 {\n\tbinary_add_expr := expr_.BinaryAddExpr()\n\n\tis_operand1_nr_tasklets := binary_add_expr.Operand1().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tAttribute() ==\n\t\t\"NR_TASKLETS\"\n\tis_operand2_number := binary_add_expr.Operand2().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tTokenType() !=\n\t\tlexer.IDENTIFIER\n\tif !is_operand1_nr_tasklets && is_operand2_number {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand1(),\n\t\t) + iram_data_size*this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand2(),\n\t\t)\n\t} else {\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand1(),\n\t\t) + this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand2(),\n\t\t)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateBinarySub(expr_ *expr.Expr) int64 {\n\tbinary_sub_expr := expr_.BinarySubExpr()\n\n\tis_operand1_nr_tasklets := binary_sub_expr.Operand1().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tAttribute() ==\n\t\t\"NR_TASKLETS\"\n\tis_operand2_number := binary_sub_expr.Operand2().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tTokenType() !=\n\t\tlexer.IDENTIFIER\n\tif !is_operand1_nr_tasklets && is_operand2_number {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand1(),\n\t\t) - iram_data_size*this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand2(),\n\t\t)\n\t} else {\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand1(),\n\t\t) - this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand2(),\n\t\t)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateSectionName(expr_ *expr.Expr) int64 {\n\tsection_name := this.ConvertSectionName(expr_)\n\tname := \"\"\n\n\treturn this.executable.Section(section_name, name).Address()\n}\n\nfunc (this *InstructionAssigner) IsZeroReg(expr_ *expr.Expr) bool {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\treturn src_reg_expr.Token().TokenType() == lexer.ZERO_REG\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/label_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype LabelAssigner struct {\n\texecutable *kernel.Executable\n\twalker     *parser.Walker\n}\n\nfunc (this *LabelAssigner) Init() {\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(stmt.ASCII, this.WalkAsciiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ASCIZ, this.WalkAscizStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BYTE, this.WalkByteStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_PROGRAM_COUNTER, this.WalkLongProgramCounterStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_SECTION_NAME, this.WalkLongSectionNameStmt)\n\tthis.walker.RegisterStmtCallback(stmt.QUAD, this.WalkQuadStmt)\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SHORT, this.WalkShortStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_DOUBLE_NUMBER, this.WalkZeroDoubleNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_SINGLE_NUMBER, this.WalkZeroSingleNumberStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.CI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DDCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DMA_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DRDICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.EDRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERID, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.I, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.NOP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRIC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.S_ERRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRIC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.BKP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BOOT_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DIV_STEP_DRDI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JNZ_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_I, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_R, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_S_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LD_DRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVD_DD, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_RIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SD_RID, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.STOP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TIME_CFG_R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *LabelAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *LabelAssigner) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tascii_stmt := stmt_.AsciiStmt()\n\ttoken := ascii_stmt.Token()\n\tattribute := token.Attribute()\n\n\t// TODO(bongjoon.hyun@gmail.com): decode octal code\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + int64(len(attribute)) - 2)\n}\n\nfunc (this *LabelAssigner) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tasciz_stmt := stmt_.AscizStmt()\n\ttoken := asciz_stmt.Token()\n\tattribute := token.Attribute()\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + int64(len(attribute)) - 1)\n}\n\nfunc (this *LabelAssigner) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 1)\n}\n\nfunc (this *LabelAssigner) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 4)\n}\n\nfunc (this *LabelAssigner) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 4)\n}\n\nfunc (this *LabelAssigner) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 8)\n}\n\nfunc (this *LabelAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\tsection_flags := this.ConvertSectionFlags(section_identifier_number_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_identifier_number_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\tsection_flags := this.ConvertSectionFlags(section_identifier_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_identifier_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\tsection_flags := this.ConvertSectionFlags(section_stack_sizes_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_stack_sizes_stmt.Expr1())\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\tsection_flags := this.ConvertSectionFlags(section_string_number_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_string_number_stmt.Expr2())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\tsection_flags := this.ConvertSectionFlags(section_string_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_string_stmt.Expr2())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 2)\n}\n\nfunc (this *LabelAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\tsection_flags := make(map[kernel.SectionFlag]bool, 0)\n\tsection_type := kernel.PROGBITS\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\tprogram_counter_expr := zero_double_number_stmt.Expr1().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tattribute := token.Attribute()\n\n\tsize, err := strconv.ParseInt(attribute, 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + size)\n}\n\nfunc (this *LabelAssigner) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\tprogram_counter_expr := zero_single_number_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tattribute := token.Attribute()\n\n\tsize, err := strconv.ParseInt(attribute, 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + size)\n}\n\nfunc (this *LabelAssigner) WalkInstructionStmt(stmt_ *stmt.Stmt) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_width := config_loader.IramDataWidth()\n\tinstruction_size := int64(iram_data_width / 8)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + instruction_size)\n}\n\nfunc (this *LabelAssigner) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tlabel_name := token.Attribute()\n\n\tif label_name != \"__sys_used_mram_end\" {\n\t\tif this.executable.CurSection().Label(label_name) == nil {\n\t\t\tthis.executable.CurSection().AppendLabel(label_name)\n\t\t}\n\n\t\tthis.executable.CurSection().CheckoutLabel(label_name)\n\t}\n}\n\nfunc (this *LabelAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LabelAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n\nfunc (this *LabelAssigner) ConvertSectionFlags(token *lexer.Token) map[kernel.SectionFlag]bool {\n\tattribute := token.Attribute()\n\n\tsection_flags := make(map[kernel.SectionFlag]bool, 0)\n\tfor i := 1; i < len(attribute)-1; i++ {\n\t\tif attribute[i] == 'a' {\n\t\t\tsection_flags[kernel.ALLOC] = true\n\t\t} else if attribute[i] == 'w' {\n\t\t\tsection_flags[kernel.WRITE] = true\n\t\t} else if attribute[i] == 'x' {\n\t\t\tsection_flags[kernel.EXECINSTR] = true\n\t\t} else if attribute[i] == 'o' {\n\t\t\tsection_flags[kernel.LINK_ORDER] = true\n\t\t} else if attribute[i] == 'M' {\n\t\t\tsection_flags[kernel.MERGE] = true\n\t\t} else if attribute[i] == 'S' {\n\t\t\tsection_flags[kernel.STRINGS] = true\n\t\t} else {\n\t\t\terr := errors.New(\"section flag is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\treturn section_flags\n}\n\nfunc (this *LabelAssigner) ConvertSectionType(expr_ *expr.Expr) kernel.SectionType {\n\tsection_type_expr := expr_.SectionTypeExpr()\n\ttoken := section_type_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tif token_type == lexer.PROGBITS {\n\t\treturn kernel.PROGBITS\n\t} else if token_type == lexer.NOBITS {\n\t\treturn kernel.NOBITS\n\t} else {\n\t\terr := errors.New(\"section type is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/linker_constant.go",
    "content": "package logic\n\ntype LinkerConstant struct {\n\tname  string\n\tvalue int64\n}\n\nfunc (this *LinkerConstant) Init(name string) {\n\tthis.name = name\n\tthis.value = 0\n}\n\nfunc (this *LinkerConstant) Name() string {\n\treturn this.name\n}\n\nfunc (this *LinkerConstant) Value() int64 {\n\treturn this.value\n}\n\nfunc (this *LinkerConstant) SetValue(value int64) {\n\tthis.value = value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/linker_script.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"math\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype LinkerScript struct {\n\tcommand_line_parser *misc.CommandLineParser\n\n\tnum_tasklets           int\n\tmin_access_granularity int64\n\n\tlinker_constants map[string]*LinkerConstant\n}\n\nfunc (this *LinkerScript) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\n\tthis.linker_constants = make(map[string]*LinkerConstant, 0)\n\n\tthis.InitLinkerConstants()\n}\n\nfunc (this *LinkerScript) Assign(executable *kernel.Executable) {\n\tthis.AssignAtomic(executable)\n\tthis.AssignIram(executable)\n\tthis.AssignWram(executable)\n\tthis.AssignMram(executable)\n}\n\nfunc (this *LinkerScript) HasLinkerConstant(name string) bool {\n\t_, found := this.linker_constants[name]\n\treturn found\n}\n\nfunc (this *LinkerScript) LinkerConstant(name string) *LinkerConstant {\n\treturn this.linker_constants[name]\n}\n\nfunc (this *LinkerScript) InitLinkerConstants() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmax_num_tasklets := config_loader.MaxNumTasklets()\n\tstack_size := config_loader.StackSize()\n\n\tthis.linker_constants[\"NR_TASKLETS\"] = new(LinkerConstant)\n\tthis.linker_constants[\"NR_TASKLETS\"].Init(\"NR_TASKLETS\")\n\tthis.linker_constants[\"NR_TASKLETS\"].SetValue(int64(this.num_tasklets))\n\n\tfor i := 0; i < max_num_tasklets; i++ {\n\t\tstack_size_tasklet := \"STACK_SIZE_TASKLET_\" + strconv.Itoa(i)\n\n\t\tthis.linker_constants[stack_size_tasklet] = new(LinkerConstant)\n\t\tthis.linker_constants[stack_size_tasklet].Init(stack_size_tasklet)\n\t\tthis.linker_constants[stack_size_tasklet].SetValue(stack_size)\n\t}\n\n\tthis.linker_constants[\"__atomic_start_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_start_addr\"].Init(\"__atomic_start_addr\")\n\n\tthis.linker_constants[\"__atomic_used_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_used_addr\"].Init(\"__atomic_used_addr\")\n\n\tthis.linker_constants[\"__atomic_end_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_end_addr\"].Init(\"__atomic_end_addr\")\n\n\tthis.linker_constants[\"__rodata_start_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__rodata_start_addr\"].Init(\"__rodata_start_addr\")\n\n\tthis.linker_constants[\"__rodata_end_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__rodata_end_addr\"].Init(\"__rodata_end_addr\")\n\n\tfor i := 0; i < max_num_tasklets; i++ {\n\t\tsys_stack_thread := \"__sys_stack_thread_\" + strconv.Itoa(i)\n\n\t\tthis.linker_constants[sys_stack_thread] = new(LinkerConstant)\n\t\tthis.linker_constants[sys_stack_thread].Init(sys_stack_thread)\n\t}\n\n\tthis.linker_constants[\"__sw_cache_buffer\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sw_cache_buffer\"].Init(\"__sw_cache_buffer\")\n\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"].Init(\"__sys_heap_pointer_reset\")\n\n\tthis.linker_constants[\"__sys_used_mram_end\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sys_used_mram_end\"].Init(\"__sys_used_mram_end\")\n}\n\nfunc (this *LinkerScript) AssignAtomic(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.AtomicOffset()\n\n\tthis.linker_constants[\"__atomic_start_addr\"].SetValue(cur_address)\n\n\tthis.linker_constants[\"__atomic_used_addr\"].SetValue(cur_address)\n\n\tfor section, _ := range executable.Sections(kernel.ATOMIC) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tthis.linker_constants[\"__atomic_end_addr\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.AtomicOffset()+config_loader.AtomicSize() {\n\t\terr := errors.New(\"address is larger than the atomic end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignIram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.IramOffset()\n\n\tbootstrap := executable.Section(kernel.TEXT, \"__bootstrap\")\n\tif bootstrap == nil {\n\t\terr := errors.New(\"bootstrap is not found\")\n\t\tpanic(err)\n\t}\n\n\tbootstrap.SetAddress(cur_address)\n\tcur_address += bootstrap.Size()\n\n\ttext_default := executable.Section(kernel.TEXT, \"\")\n\tif text_default != nil {\n\t\ttext_default.SetAddress(cur_address)\n\t\tcur_address += text_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.TEXT) {\n\t\tif section.Name() != \"__bootstrap\" && section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tif cur_address >= config_loader.IramOffset()+config_loader.IramSize() {\n\t\terr := errors.New(\"address is larger than the IRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignWram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.WramOffset()\n\n\tsys_zero := executable.Section(kernel.DATA, \"__sys_zero\")\n\tif sys_zero != nil {\n\t\tsys_zero.SetAddress(cur_address)\n\t\tcur_address += sys_zero.Size()\n\t}\n\n\timmediate_memory := executable.Section(kernel.DATA, \"immediate_memory\")\n\tif immediate_memory != nil {\n\t\timmediate_memory.SetAddress(cur_address)\n\t\tcur_address += immediate_memory.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DATA) {\n\t\tif strings.Contains(section.Name(), \"immediate_memory.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tthis.linker_constants[\"__rodata_start_addr\"].SetValue(cur_address)\n\n\trodata_default := executable.Section(kernel.RODATA, \"\")\n\tif rodata_default != nil {\n\t\trodata_default.SetAddress(cur_address)\n\t\tcur_address += rodata_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.RODATA) {\n\t\tif section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tthis.linker_constants[\"__rodata_end_addr\"].SetValue(cur_address)\n\n\tbss_default := executable.Section(kernel.BSS, \"\")\n\tif bss_default != nil {\n\t\tbss_default.SetAddress(cur_address)\n\t\tcur_address += bss_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.BSS) {\n\t\tif section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tsys_keep := executable.Section(kernel.DATA, \"__sys_keep\")\n\tif sys_keep != nil {\n\t\tsys_keep.SetAddress(cur_address)\n\t\tcur_address += sys_keep.Size()\n\t}\n\n\tdata_default := executable.Section(kernel.DATA, \"\")\n\tif data_default != nil {\n\t\tdata_default.SetAddress(cur_address)\n\t\tcur_address += data_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DATA) {\n\t\tif section.Name() != \"__sys_zero\" &&\n\t\t\tsection.Name() != \"__sys_keep\" &&\n\t\t\t!strings.Contains(section.Name(), \"immediate_memory\") &&\n\t\t\tsection.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.__sys_host\" section\n\n\tdpu_host := executable.Section(kernel.DPU_HOST, \"\")\n\tif dpu_host != nil {\n\t\tdpu_host.SetAddress(cur_address)\n\t\tcur_address += dpu_host.Size()\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.__sys_profilng\" section\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.stacks\" section\n\n\tfor i := 0; i < config_loader.MaxNumTasklets(); i++ {\n\t\tsys_stack_thread := \"__sys_stack_thread_\" + strconv.Itoa(i)\n\t\tthis.linker_constants[sys_stack_thread].SetValue(cur_address)\n\n\t\tstack_size_tasklet := \"STACK_SIZE_TASKLET_\" + strconv.Itoa(i)\n\t\tcur_address += this.linker_constants[stack_size_tasklet].Value()\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.sw_cache\" section\n\n\tthis.linker_constants[\"__sw_cache_buffer\"].SetValue(cur_address)\n\tcur_address += int64(8 * config_loader.MaxNumTasklets())\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.heap_pointer_reset\" section\n\n\tcur_address = int64(\n\t\tmath.Ceil(float64(cur_address)/float64(this.min_access_granularity)),\n\t) * int64(\n\t\tthis.min_access_granularity,\n\t)\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.WramOffset()+config_loader.WramSize() {\n\t\terr := errors.New(\"address is larger than the WRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignMram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.MramOffset()\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_ABBREV) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_FRAME) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_INFO) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_LINE) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_LOC) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_RANGES) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_STR) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.STACK_SIZES) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tnoinit := executable.Section(kernel.MRAM, \"noinit\")\n\tif noinit != nil {\n\t\tnoinit.SetAddress(cur_address)\n\t\tcur_address += noinit.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.\") &&\n\t\t\t!strings.Contains(section.Name(), \"noinit.keep\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tnoinit_keep := executable.Section(kernel.MRAM, \"noinit.keep\")\n\tif noinit_keep != nil {\n\t\tnoinit_keep.SetAddress(cur_address)\n\t\tcur_address += noinit_keep.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.keep\") &&\n\t\t\t!strings.Contains(section.Name(), \"noinit.keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tmram_default := executable.Section(kernel.MRAM, \"\")\n\tif mram_default != nil {\n\t\tmram_default.SetAddress(cur_address)\n\t\tcur_address += mram_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif section.Name() != \"\" &&\n\t\t\t!strings.Contains(section.Name(), \"noinit\") &&\n\t\t\t!strings.Contains(section.Name(), \"keep\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"keep\") &&\n\t\t\t!strings.Contains(section.Name(), \"keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tcur_address = int64(\n\t\tmath.Ceil(float64(cur_address)/float64(this.min_access_granularity)),\n\t) * this.min_access_granularity\n\n\tthis.linker_constants[\"__sys_used_mram_end\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.MramOffset()+config_loader.MramSize() {\n\t\terr := errors.New(\"address is larger than the MRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) DumpValues(path string) {\n\tlines := make([]string, 0)\n\n\tfor _, linker_constant := range this.linker_constants {\n\t\tline := fmt.Sprintf(\"%s: %d\", linker_constant.Name(), linker_constant.Value())\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/liveness_analyzer.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype LivenessAnalyzer struct {\n\tliveness *kernel.Liveness\n\twalker   *parser.Walker\n}\n\nfunc (this *LivenessAnalyzer) Init() {\n\tthis.liveness = new(kernel.Liveness)\n\tthis.liveness.Init()\n\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterExprCallback(expr.PRIMARY, this.WalkPrimaryExpr)\n\tthis.walker.RegisterStmtCallback(stmt.GLOBAL, this.WalkGlobalStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SET, this.WalkSetStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *LivenessAnalyzer) Analyze(relocatable *kernel.Relocatable) *kernel.Liveness {\n\tthis.walker.Walk(relocatable.Ast())\n\treturn this.liveness\n}\n\nfunc (this *LivenessAnalyzer) WalkPrimaryExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"expr type is not primary\")\n\t\tpanic(err)\n\t}\n\n\tprimary_expr := expr_.PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\tif token.TokenType() == lexer.IDENTIFIER {\n\t\tthis.liveness.AddUse(token.Attribute())\n\t}\n}\n\nfunc (this *LivenessAnalyzer) WalkGlobalStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.GLOBAL {\n\t\terr := errors.New(\"stmt type is not global\")\n\t\tpanic(err)\n\t}\n\n\tglobal_stmt := stmt_.GlobalStmt()\n\n\tprogram_counter_expr := global_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\tif attribute != \"__sys_used_mram_end\" {\n\t\tthis.liveness.AddGlobalSymbol(attribute)\n\t}\n}\n\nfunc (this *LivenessAnalyzer) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SET {\n\t\terr := errors.New(\"stmt type is not set\")\n\t\tpanic(err)\n\t}\n\n\tset_stmt := stmt_.SetStmt()\n\n\tprogram_counter_expr1 := set_stmt.Expr1().ProgramCounterExpr()\n\tprogram_counter_expr2 := set_stmt.Expr2().ProgramCounterExpr()\n\n\tprimary_expr1 := program_counter_expr1.Expr().PrimaryExpr()\n\tprimary_expr2 := program_counter_expr2.Expr().PrimaryExpr()\n\n\ttoken1 := primary_expr1.Token()\n\ttoken2 := primary_expr2.Token()\n\n\tif token1.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token1 type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tif token2.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token2 type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.liveness.AddDef(token1.Attribute())\n\tthis.liveness.AddUse(token2.Attribute())\n}\n\nfunc (this *LivenessAnalyzer) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LABEL {\n\t\terr := errors.New(\"stmt type is not label\")\n\t\tpanic(err)\n\t}\n\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\tif attribute != \"__sys_used_mram_end\" {\n\t\tthis.liveness.AddDef(attribute)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/logic/set_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype SetAssigner struct {\n\texecutable *kernel.Executable\n\twalker     *parser.Walker\n}\n\nfunc (this *SetAssigner) Init() {\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n}\n\nfunc (this *SetAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *SetAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tset_stmt := stmt_.SetStmt()\n\n\tprogram_counter_expr1 := set_stmt.Expr1().ProgramCounterExpr()\n\tprogram_counter_expr2 := set_stmt.Expr2().ProgramCounterExpr()\n\n\tprimary_expr1 := program_counter_expr1.Expr().PrimaryExpr()\n\tprimary_expr2 := program_counter_expr2.Expr().PrimaryExpr()\n\n\ttoken1 := primary_expr1.Token()\n\ttoken2 := primary_expr2.Token()\n\n\tattribute1 := token1.Attribute()\n\tattribute2 := token2.Attribute()\n\n\tsrc_label := this.executable.CurSection().Label(attribute1)\n\n\tif this.executable.CurSection().Label(attribute2) == nil {\n\t\tthis.executable.CurSection().AppendLabel(attribute2)\n\t}\n\n\tdst_label := this.executable.CurSection().Label(attribute2)\n\n\tdst_label.SetAddress(src_label.Address())\n}\n\nfunc (this *SetAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *SetAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parse_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/linker/kernel\"\n\t\"uPIMulator/src/linker/parser\"\n)\n\ntype ParseJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *ParseJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *ParseJob) Execute() {\n\tfmt.Printf(\"Parsing %s...\\n\", this.relocatable.Path())\n\n\tparser_ := new(parser.Parser)\n\tparser_.Init()\n\n\tast := parser_.Parse(this.relocatable.TokenStream())\n\tthis.relocatable.SetAst(ast)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/ast.go",
    "content": "package parser\n\nimport (\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype Ast struct {\n\tstmts []*stmt.Stmt\n}\n\nfunc (this *Ast) Init(stmts []*stmt.Stmt) {\n\tthis.stmts = stmts\n}\n\nfunc (this *Ast) Size() int {\n\treturn len(this.stmts)\n}\n\nfunc (this *Ast) Get(pos int) *stmt.Stmt {\n\treturn this.stmts[pos]\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/binary_add_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BinaryAddExpr struct {\n\toperand1 *Expr\n\toperand2 *Expr\n}\n\nfunc (this *BinaryAddExpr) Init(operand1 *Expr, operand2 *Expr) {\n\tif operand1.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand1 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tif operand2.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand2 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand1 = operand1\n\tthis.operand2 = operand2\n}\n\nfunc (this *BinaryAddExpr) Operand1() *Expr {\n\treturn this.operand1\n}\n\nfunc (this *BinaryAddExpr) Operand2() *Expr {\n\treturn this.operand2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/binary_sub_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BinarySubExpr struct {\n\toperand1 *Expr\n\toperand2 *Expr\n}\n\nfunc (this *BinarySubExpr) Init(operand1 *Expr, operand2 *Expr) {\n\tif operand1.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand1 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tif operand2.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand2 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand1 = operand1\n\tthis.operand2 = operand2\n}\n\nfunc (this *BinarySubExpr) Operand1() *Expr {\n\treturn this.operand1\n}\n\nfunc (this *BinarySubExpr) Operand2() *Expr {\n\treturn this.operand2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/ci_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype CiOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *CiOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.STOP {\n\t\terr := errors.New(\"token type is not a CI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *CiOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/condition_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype ConditionExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *ConditionExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.TRUE &&\n\t\ttoken_type != lexer.FALSE &&\n\t\ttoken_type != lexer.Z &&\n\t\ttoken_type != lexer.NZ &&\n\t\ttoken_type != lexer.E &&\n\t\ttoken_type != lexer.O &&\n\t\ttoken_type != lexer.PL &&\n\t\ttoken_type != lexer.MI &&\n\t\ttoken_type != lexer.OV &&\n\t\ttoken_type != lexer.NOV &&\n\t\ttoken_type != lexer.C &&\n\t\ttoken_type != lexer.NC &&\n\t\ttoken_type != lexer.SZ &&\n\t\ttoken_type != lexer.SNZ &&\n\t\ttoken_type != lexer.SPL &&\n\t\ttoken_type != lexer.SMI &&\n\t\ttoken_type != lexer.SO &&\n\t\ttoken_type != lexer.SE &&\n\t\ttoken_type != lexer.NC5 &&\n\t\ttoken_type != lexer.NC6 &&\n\t\ttoken_type != lexer.NC7 &&\n\t\ttoken_type != lexer.NC8 &&\n\t\ttoken_type != lexer.NC9 &&\n\t\ttoken_type != lexer.NC10 &&\n\t\ttoken_type != lexer.NC11 &&\n\t\ttoken_type != lexer.NC12 &&\n\t\ttoken_type != lexer.NC13 &&\n\t\ttoken_type != lexer.NC14 &&\n\t\ttoken_type != lexer.MAX &&\n\t\ttoken_type != lexer.NMAX &&\n\t\ttoken_type != lexer.SH32 &&\n\t\ttoken_type != lexer.NSH32 &&\n\t\ttoken_type != lexer.EQ &&\n\t\ttoken_type != lexer.NEQ &&\n\t\ttoken_type != lexer.LTU &&\n\t\ttoken_type != lexer.LEU &&\n\t\ttoken_type != lexer.GTU &&\n\t\ttoken_type != lexer.GEU &&\n\t\ttoken_type != lexer.LTS &&\n\t\ttoken_type != lexer.LES &&\n\t\ttoken_type != lexer.GTS &&\n\t\ttoken_type != lexer.GES &&\n\t\ttoken_type != lexer.XZ &&\n\t\ttoken_type != lexer.XNZ &&\n\t\ttoken_type != lexer.XLEU &&\n\t\ttoken_type != lexer.XGTU &&\n\t\ttoken_type != lexer.XLES &&\n\t\ttoken_type != lexer.XGTS &&\n\t\ttoken_type != lexer.SMALL &&\n\t\ttoken_type != lexer.LARGE {\n\t\terr := errors.New(\"token type is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *ConditionExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/ddci_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype DdciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DdciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.MOVD && token_type != lexer.SWAPD {\n\t\terr := errors.New(\"token type is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DdciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/dma_rri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype DmaRriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DmaRriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LDMA && token_type != lexer.LDMAI && token_type != lexer.SDMA {\n\t\terr := errors.New(\"token type is not a DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DmaRriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/drdici_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype DrdiciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DrdiciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.DIV_STEP && token_type != lexer.MUL_STEP {\n\t\terr := errors.New(\"token type is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DrdiciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/endian_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype EndianExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *EndianExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LITTLE &&\n\t\ttoken_type != lexer.BIG {\n\t\terr := errors.New(\"token type is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *EndianExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/expr.go",
    "content": "package expr\n\nimport (\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype ExprType int\n\nconst (\n\tCI_OP_CODE ExprType = iota\n\tDDCI_OP_CODE\n\tDMA_RRI_OP_CODE\n\tDRDICI_OP_CODE\n\tI_OP_CODE\n\tJUMP_OP_CODE\n\tLOAD_OP_CODE\n\tR_OP_CODE\n\tRICI_OP_CODE\n\tRR_OP_CODE\n\tRRI_OP_CODE\n\tRRRI_OP_CODE\n\tSTORE_OP_CODE\n\n\tSUFFIX\n\tCONDITION\n\tENDIAN\n\n\tSECTION_NAME\n\tSECTION_TYPE\n\n\tSYMBOL_TYPE\n\n\tNEGATIVE_NUMBER\n\tPRIMARY\n\tBINARY_ADD\n\tBINARY_SUB\n\tPROGRAM_COUNTER\n\n\tSRC_REG\n)\n\ntype Expr struct {\n\texpr_type ExprType\n\n\tci_op_code_expr      *CiOpCodeExpr\n\tddci_op_code_expr    *DdciOpCodeExpr\n\tdma_rri_op_code_expr *DmaRriOpCodeExpr\n\tdrdici_op_code_expr  *DrdiciOpCodeExpr\n\ti_op_code_expr       *IOpCodeExpr\n\tjump_op_code_expr    *JumpOpCodeExpr\n\tload_op_code_expr    *LoadOpCodeExpr\n\tr_op_code_expr       *ROpCodeExpr\n\trici_op_code_expr    *RiciOpCodeExpr\n\trr_op_code_expr      *RrOpCodeExpr\n\trri_op_code_expr     *RriOpCodeExpr\n\trrri_op_code_expr    *RrriOpCodeExpr\n\tstore_op_code_expr   *StoreOpCodeExpr\n\n\tsuffix_expr    *SuffixExpr\n\tcondition_expr *ConditionExpr\n\tendian_expr    *EndianExpr\n\n\tsection_name_expr *SectionNameExpr\n\tsection_type_expr *SectionTypeExpr\n\n\tsymbol_type_expr *SymbolTypeExpr\n\n\tnegative_number_expr *NegativeNumberExpr\n\tprimary_expr         *PrimaryExpr\n\tbinary_add_expr      *BinaryAddExpr\n\tbinary_sub_expr      *BinarySubExpr\n\tprogram_counter_expr *ProgramCounterExpr\n\n\tsrc_reg_expr *SrcRegExpr\n}\n\nfunc (this *Expr) InitCiOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = CI_OP_CODE\n\n\tthis.ci_op_code_expr = new(CiOpCodeExpr)\n\tthis.ci_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDdciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DDCI_OP_CODE\n\n\tthis.ddci_op_code_expr = new(DdciOpCodeExpr)\n\tthis.ddci_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDmaRriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DMA_RRI_OP_CODE\n\n\tthis.dma_rri_op_code_expr = new(DmaRriOpCodeExpr)\n\tthis.dma_rri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDrdiciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DRDICI_OP_CODE\n\n\tthis.drdici_op_code_expr = new(DrdiciOpCodeExpr)\n\tthis.drdici_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitIOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = I_OP_CODE\n\n\tthis.i_op_code_expr = new(IOpCodeExpr)\n\tthis.i_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitJumpOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = JUMP_OP_CODE\n\n\tthis.jump_op_code_expr = new(JumpOpCodeExpr)\n\tthis.jump_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitLoadOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = LOAD_OP_CODE\n\n\tthis.load_op_code_expr = new(LoadOpCodeExpr)\n\tthis.load_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitROpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = R_OP_CODE\n\n\tthis.r_op_code_expr = new(ROpCodeExpr)\n\tthis.r_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRiciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RICI_OP_CODE\n\n\tthis.rici_op_code_expr = new(RiciOpCodeExpr)\n\tthis.rici_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRrOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RR_OP_CODE\n\n\tthis.rr_op_code_expr = new(RrOpCodeExpr)\n\tthis.rr_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RRI_OP_CODE\n\n\tthis.rri_op_code_expr = new(RriOpCodeExpr)\n\tthis.rri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRrriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RRRI_OP_CODE\n\n\tthis.rrri_op_code_expr = new(RrriOpCodeExpr)\n\tthis.rrri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitStoreOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = STORE_OP_CODE\n\n\tthis.store_op_code_expr = new(StoreOpCodeExpr)\n\tthis.store_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitSuffixExpr(token *lexer.Token) {\n\tthis.expr_type = SUFFIX\n\n\tthis.suffix_expr = new(SuffixExpr)\n\tthis.suffix_expr.Init(token)\n}\n\nfunc (this *Expr) InitConditionExpr(token *lexer.Token) {\n\tthis.expr_type = CONDITION\n\n\tthis.condition_expr = new(ConditionExpr)\n\tthis.condition_expr.Init(token)\n}\n\nfunc (this *Expr) InitEndianExpr(token *lexer.Token) {\n\tthis.expr_type = ENDIAN\n\n\tthis.endian_expr = new(EndianExpr)\n\tthis.endian_expr.Init(token)\n}\n\nfunc (this *Expr) InitSectionNameExpr(token *lexer.Token) {\n\tthis.expr_type = SECTION_NAME\n\n\tthis.section_name_expr = new(SectionNameExpr)\n\tthis.section_name_expr.Init(token)\n}\n\nfunc (this *Expr) InitSectionTypeExpr(token *lexer.Token) {\n\tthis.expr_type = SECTION_TYPE\n\n\tthis.section_type_expr = new(SectionTypeExpr)\n\tthis.section_type_expr.Init(token)\n}\n\nfunc (this *Expr) InitSymbolTypeExpr(token *lexer.Token) {\n\tthis.expr_type = SYMBOL_TYPE\n\n\tthis.symbol_type_expr = new(SymbolTypeExpr)\n\tthis.symbol_type_expr.Init(token)\n}\n\nfunc (this *Expr) InitNegativeNumberExpr(token *lexer.Token) {\n\tthis.expr_type = NEGATIVE_NUMBER\n\n\tthis.negative_number_expr = new(NegativeNumberExpr)\n\tthis.negative_number_expr.Init(token)\n}\n\nfunc (this *Expr) InitPrimaryExpr(token *lexer.Token) {\n\tthis.expr_type = PRIMARY\n\n\tthis.primary_expr = new(PrimaryExpr)\n\tthis.primary_expr.Init(token)\n}\n\nfunc (this *Expr) InitBinaryAddExpr(operand1 *Expr, operand2 *Expr) {\n\tthis.expr_type = BINARY_ADD\n\n\tthis.binary_add_expr = new(BinaryAddExpr)\n\tthis.binary_add_expr.Init(operand1, operand2)\n}\n\nfunc (this *Expr) InitBinarySubExpr(operand1 *Expr, operand2 *Expr) {\n\tthis.expr_type = BINARY_SUB\n\n\tthis.binary_sub_expr = new(BinarySubExpr)\n\tthis.binary_sub_expr.Init(operand1, operand2)\n}\n\nfunc (this *Expr) InitProgramCounterExpr(expr *Expr) {\n\tthis.expr_type = PROGRAM_COUNTER\n\n\tthis.program_counter_expr = new(ProgramCounterExpr)\n\tthis.program_counter_expr.Init(expr)\n}\n\nfunc (this *Expr) InitSrcRegExpr(token *lexer.Token) {\n\tthis.expr_type = SRC_REG\n\n\tthis.src_reg_expr = new(SrcRegExpr)\n\tthis.src_reg_expr.Init(token)\n}\n\nfunc (this *Expr) ExprType() ExprType {\n\treturn this.expr_type\n}\n\nfunc (this *Expr) CiOpCodeExpr() *CiOpCodeExpr {\n\treturn this.ci_op_code_expr\n}\n\nfunc (this *Expr) DdciOpCodeExpr() *DdciOpCodeExpr {\n\treturn this.ddci_op_code_expr\n}\n\nfunc (this *Expr) DmaRriOpCodeExpr() *DmaRriOpCodeExpr {\n\treturn this.dma_rri_op_code_expr\n}\n\nfunc (this *Expr) DrdiciOpCodeExpr() *DrdiciOpCodeExpr {\n\treturn this.drdici_op_code_expr\n}\n\nfunc (this *Expr) IOpCodeExpr() *IOpCodeExpr {\n\treturn this.i_op_code_expr\n}\n\nfunc (this *Expr) JumpOpCodeExpr() *JumpOpCodeExpr {\n\treturn this.jump_op_code_expr\n}\n\nfunc (this *Expr) LoadOpCodeExpr() *LoadOpCodeExpr {\n\treturn this.load_op_code_expr\n}\n\nfunc (this *Expr) ROpCodeExpr() *ROpCodeExpr {\n\treturn this.r_op_code_expr\n}\n\nfunc (this *Expr) RiciOpCodeExpr() *RiciOpCodeExpr {\n\treturn this.rici_op_code_expr\n}\n\nfunc (this *Expr) RrOpCodeExpr() *RrOpCodeExpr {\n\treturn this.rr_op_code_expr\n}\n\nfunc (this *Expr) RriOpCodeExpr() *RriOpCodeExpr {\n\treturn this.rri_op_code_expr\n}\n\nfunc (this *Expr) RrriOpCodeExpr() *RrriOpCodeExpr {\n\treturn this.rrri_op_code_expr\n}\n\nfunc (this *Expr) StoreOpCodeExpr() *StoreOpCodeExpr {\n\treturn this.store_op_code_expr\n}\n\nfunc (this *Expr) SuffixExpr() *SuffixExpr {\n\treturn this.suffix_expr\n}\n\nfunc (this *Expr) ConditionExpr() *ConditionExpr {\n\treturn this.condition_expr\n}\n\nfunc (this *Expr) EndianExpr() *EndianExpr {\n\treturn this.endian_expr\n}\n\nfunc (this *Expr) SectionNameExpr() *SectionNameExpr {\n\treturn this.section_name_expr\n}\n\nfunc (this *Expr) SectionTypeExpr() *SectionTypeExpr {\n\treturn this.section_type_expr\n}\n\nfunc (this *Expr) SymbolTypeExpr() *SymbolTypeExpr {\n\treturn this.symbol_type_expr\n}\n\nfunc (this *Expr) NegativeNumberExpr() *NegativeNumberExpr {\n\treturn this.negative_number_expr\n}\n\nfunc (this *Expr) PrimaryExpr() *PrimaryExpr {\n\treturn this.primary_expr\n}\n\nfunc (this *Expr) BinaryAddExpr() *BinaryAddExpr {\n\treturn this.binary_add_expr\n}\n\nfunc (this *Expr) BinarySubExpr() *BinarySubExpr {\n\treturn this.binary_sub_expr\n}\n\nfunc (this *Expr) ProgramCounterExpr() *ProgramCounterExpr {\n\treturn this.program_counter_expr\n}\n\nfunc (this *Expr) SrcRegExpr() *SrcRegExpr {\n\treturn this.src_reg_expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/i_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype IOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *IOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.FAULT && token_type != lexer.BKP {\n\t\terr := errors.New(\"token type is not an I op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *IOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/jump_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype JumpOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *JumpOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.JEQ &&\n\t\ttoken_type != lexer.JNEQ &&\n\t\ttoken_type != lexer.JZ &&\n\t\ttoken_type != lexer.JNZ &&\n\t\ttoken_type != lexer.JLTU &&\n\t\ttoken_type != lexer.JGTU &&\n\t\ttoken_type != lexer.JLEU &&\n\t\ttoken_type != lexer.JGEU &&\n\t\ttoken_type != lexer.JLTS &&\n\t\ttoken_type != lexer.JGTS &&\n\t\ttoken_type != lexer.JLES &&\n\t\ttoken_type != lexer.JGES &&\n\t\ttoken_type != lexer.JUMP {\n\t\terr := errors.New(\"token type is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *JumpOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/load_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype LoadOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *LoadOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LBS &&\n\t\ttoken_type != lexer.LBU &&\n\t\ttoken_type != lexer.LD &&\n\t\ttoken_type != lexer.LHS &&\n\t\ttoken_type != lexer.LHU &&\n\t\ttoken_type != lexer.LW {\n\t\terr := errors.New(\"token type is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *LoadOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/negative_number_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype NegativeNumberExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *NegativeNumberExpr) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.POSITIVIE_NUMBER {\n\t\terr := errors.New(\"token type is not positive number\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *NegativeNumberExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/primary_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype PrimaryExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *PrimaryExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.POSITIVIE_NUMBER && token_type != lexer.HEX_NUMBER &&\n\t\ttoken_type != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not positive number, hex number, nor identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *PrimaryExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/program_counter_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype ProgramCounterExpr struct {\n\texpr *Expr\n}\n\nfunc (this *ProgramCounterExpr) Init(expr *Expr) {\n\texpr_type := expr.ExprType()\n\n\tif expr_type != PRIMARY && expr_type != NEGATIVE_NUMBER && expr_type != BINARY_ADD &&\n\t\texpr_type != BINARY_SUB {\n\t\terr := errors.New(\"expr type is not primary, negative number, binary add, nor binary sub\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr\n}\n\nfunc (this *ProgramCounterExpr) Expr() *Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/r_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype ROpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *ROpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.TIME && token_type != lexer.NOP {\n\t\terr := errors.New(\"token type is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *ROpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/rici_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype RiciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RiciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ACQUIRE &&\n\t\ttoken_type != lexer.RELEASE &&\n\t\ttoken_type != lexer.BOOT &&\n\t\ttoken_type != lexer.RESUME {\n\t\terr := errors.New(\"token type is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RiciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/rr_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype RrOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RrOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.CAO &&\n\t\ttoken_type != lexer.CLO &&\n\t\ttoken_type != lexer.CLS &&\n\t\ttoken_type != lexer.CLZ &&\n\t\ttoken_type != lexer.EXTSB &&\n\t\ttoken_type != lexer.EXTSH &&\n\t\ttoken_type != lexer.EXTUB &&\n\t\ttoken_type != lexer.EXTUH &&\n\t\ttoken_type != lexer.SATS &&\n\t\ttoken_type != lexer.TIME_CFG &&\n\t\ttoken_type != lexer.MOVE &&\n\t\ttoken_type != lexer.NEG &&\n\t\ttoken_type != lexer.NOT {\n\t\terr := errors.New(\"token type is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RrOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/rri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype RriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ADD &&\n\t\ttoken_type != lexer.ADDC &&\n\t\ttoken_type != lexer.AND &&\n\t\ttoken_type != lexer.ANDN &&\n\t\ttoken_type != lexer.ASR &&\n\t\ttoken_type != lexer.CMPB4 &&\n\t\ttoken_type != lexer.LSL &&\n\t\ttoken_type != lexer.LSL1 &&\n\t\ttoken_type != lexer.LSL1X &&\n\t\ttoken_type != lexer.LSLX &&\n\t\ttoken_type != lexer.LSR &&\n\t\ttoken_type != lexer.LSR1 &&\n\t\ttoken_type != lexer.LSR1X &&\n\t\ttoken_type != lexer.LSRX &&\n\t\ttoken_type != lexer.MUL_SH_SH &&\n\t\ttoken_type != lexer.MUL_SH_SL &&\n\t\ttoken_type != lexer.MUL_SH_UH &&\n\t\ttoken_type != lexer.MUL_SH_UL &&\n\t\ttoken_type != lexer.MUL_SL_SH &&\n\t\ttoken_type != lexer.MUL_SL_SL &&\n\t\ttoken_type != lexer.MUL_SL_UH &&\n\t\ttoken_type != lexer.MUL_SL_UL &&\n\t\ttoken_type != lexer.MUL_UH_UH &&\n\t\ttoken_type != lexer.MUL_UH_UL &&\n\t\ttoken_type != lexer.MUL_UL_UH &&\n\t\ttoken_type != lexer.MUL_UL_UL &&\n\t\ttoken_type != lexer.NAND &&\n\t\ttoken_type != lexer.NOR &&\n\t\ttoken_type != lexer.NXOR &&\n\t\ttoken_type != lexer.OR &&\n\t\ttoken_type != lexer.ORN &&\n\t\ttoken_type != lexer.ROL &&\n\t\ttoken_type != lexer.ROR &&\n\t\ttoken_type != lexer.RSUB &&\n\t\ttoken_type != lexer.RSUBC &&\n\t\ttoken_type != lexer.SUB &&\n\t\ttoken_type != lexer.SUBC &&\n\t\ttoken_type != lexer.XOR &&\n\t\ttoken_type != lexer.CALL {\n\t\terr := errors.New(\"token type is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/rrri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype RrriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RrriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LSL_ADD &&\n\t\ttoken_type != lexer.LSL_SUB &&\n\t\ttoken_type != lexer.LSR_ADD &&\n\t\ttoken_type != lexer.ROL_ADD {\n\t\terr := errors.New(\"token type is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RrriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/section_name_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype SectionNameExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SectionNameExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ATOMIC &&\n\t\ttoken_type != lexer.BSS &&\n\t\ttoken_type != lexer.DATA &&\n\t\ttoken_type != lexer.DEBUG_ABBREV &&\n\t\ttoken_type != lexer.DEBUG_FRAME &&\n\t\ttoken_type != lexer.DEBUG_INFO &&\n\t\ttoken_type != lexer.DEBUG_LINE &&\n\t\ttoken_type != lexer.DEBUG_LOC &&\n\t\ttoken_type != lexer.DEBUG_RANGES &&\n\t\ttoken_type != lexer.DEBUG_STR &&\n\t\ttoken_type != lexer.DPU_HOST &&\n\t\ttoken_type != lexer.MRAM &&\n\t\ttoken_type != lexer.RODATA &&\n\t\ttoken_type != lexer.STACK_SIZES &&\n\t\ttoken_type != lexer.TEXT {\n\t\terr := errors.New(\"token type is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SectionNameExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/section_type_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype SectionTypeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SectionTypeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.PROGBITS && token_type != lexer.NOBITS {\n\t\terr := errors.New(\"token type is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SectionTypeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/src_reg_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype SrcRegExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SrcRegExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.GP_REG &&\n\t\ttoken_type != lexer.ZERO_REG &&\n\t\ttoken_type != lexer.ONE &&\n\t\ttoken_type != lexer.ID &&\n\t\ttoken_type != lexer.ID2 &&\n\t\ttoken_type != lexer.ID4 &&\n\t\ttoken_type != lexer.ID8 &&\n\t\ttoken_type != lexer.LNEG &&\n\t\ttoken_type != lexer.MNEG {\n\t\terr := errors.New(\"token type is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SrcRegExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/store_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype StoreOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *StoreOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.SB &&\n\t\ttoken_type != lexer.SB_ID &&\n\t\ttoken_type != lexer.SD &&\n\t\ttoken_type != lexer.SD_ID &&\n\t\ttoken_type != lexer.SH &&\n\t\ttoken_type != lexer.SH_ID &&\n\t\ttoken_type != lexer.SW &&\n\t\ttoken_type != lexer.SW_ID {\n\t\terr := errors.New(\"token type is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *StoreOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/suffix_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype SuffixExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SuffixExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.S && token_type != lexer.U {\n\t\terr := errors.New(\"token type is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SuffixExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/expr/symbol_type.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype SymbolTypeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SymbolTypeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.FUNCTION && token_type != lexer.OBJECT {\n\t\terr := errors.New(\"token type is not a symbol type\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SymbolTypeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/parser.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype Parser struct {\n\tstack *Stack\n\ttable *Table\n}\n\nfunc (this *Parser) Init() {\n\tthis.stack = new(Stack)\n\tthis.stack.Init()\n\n\tthis.table = new(Table)\n\tthis.table.Init(this.stack)\n\n\tthis.RegisterAccessExpr()\n\tthis.RegisterConcatExpr()\n\tthis.RegisterBinaryAddExpr()\n\tthis.RegisterBinarySubExpr()\n\tthis.RegisterCiOpCodeExpr()\n\tthis.RegisterConditionExpr()\n\tthis.RegisterDdciOpCodeExpr()\n\tthis.RegisterDmaRriOpCodeExpr()\n\tthis.RegisterDrdiciOpCodeExpr()\n\tthis.RegisterEndianExpr()\n\tthis.RegisterIOpCodeExpr()\n\tthis.RegisterJumpOpCodeExpr()\n\tthis.RegisterLoadOpCodeExpr()\n\tthis.RegisterNegativeNumberExpr()\n\tthis.RegisterPrimaryExpr()\n\tthis.RegisterProgramCounterExpr()\n\tthis.RegisterROpCodeExpr()\n\tthis.RegisterRiciOpCodeExpr()\n\tthis.RegisterRrOpCodeExpr()\n\tthis.RegisterRriOpCodeExpr()\n\tthis.RegisterRrriOpCodeExpr()\n\tthis.RegisterSectionNameExpr()\n\tthis.RegisterSectionTypeExpr()\n\tthis.RegisterSrcRegExpr()\n\tthis.RegisterStoreOpCodeExpr()\n\tthis.RegisterSuffixExpr()\n\tthis.RegisterSymbolTypeExpr()\n\n\tthis.RegisterAddrsigStmt()\n\tthis.RegisterAddrsigSymStmt()\n\tthis.RegisterAsciiStmt()\n\tthis.RegisterAscizStmt()\n\tthis.RegisterByteStmt()\n\tthis.RegisterCfiDefCfaOffsetStmt()\n\tthis.RegisterCfiEndprocStmt()\n\tthis.RegisterCfiOffsetStmt()\n\tthis.RegisterCfiSectionsStmt()\n\tthis.RegisterCfiStartprocStmt()\n\tthis.RegisterFileNumberStmt()\n\tthis.RegisterFileStringStmt()\n\tthis.RegisterGlobalStmt()\n\tthis.RegisterLocIsStmtStmt()\n\tthis.RegisterLocNumberStmt()\n\tthis.RegisterLocPrologueEndStmt()\n\tthis.RegisterLongProgramCounterStmt()\n\tthis.RegisterLongSectionNameStmt()\n\tthis.RegisterP2AlignStmt()\n\tthis.RegisterQuadStmt()\n\tthis.RegisterSectionIdentifierNumberStmt()\n\tthis.RegisterSectionIdentifierStmt()\n\tthis.RegisterSectionStackSizesStmt()\n\tthis.RegisterSectionStringNumberStmt()\n\tthis.RegisterSectionStringStmt()\n\tthis.RegisterSetStmt()\n\tthis.RegisterShortStmt()\n\tthis.RegisterSizeStmt()\n\tthis.RegisterTextStmt()\n\tthis.RegisterTypeStmt()\n\tthis.RegisterWeakStmt()\n\tthis.RegisterZeroDoubleNumberStmt()\n\tthis.RegisterZeroSingleNumberStmt()\n\n\tthis.RegisterCiStmt()\n\tthis.RegisterDdciStmt()\n\tthis.RegisterDmaRriStmt()\n\tthis.RegisterDrdiciStmt()\n\tthis.RegisterEdriStmt()\n\tthis.RegisterEriiStmt()\n\tthis.RegisterErirStmt()\n\tthis.RegisterErriStmt()\n\tthis.RegisterIStmt()\n\tthis.RegisterRciStmt()\n\tthis.RegisterRiciStmt()\n\tthis.RegisterRirciStmt()\n\tthis.RegisterRircStmt()\n\tthis.RegisterRirStmt()\n\tthis.RegisterRrciStmt()\n\tthis.RegisterRrcStmt()\n\tthis.RegisterRriciStmt()\n\tthis.RegisterRricStmt()\n\tthis.RegisterRriStmt()\n\tthis.RegisterRrrciStmt()\n\tthis.RegisterRrrcStmt()\n\tthis.RegisterRrriciStmt()\n\tthis.RegisterRrriStmt()\n\tthis.RegisterRrrStmt()\n\tthis.RegisterRrStmt()\n\tthis.RegisterRStmt()\n\n\tthis.RegisterSErriStmt()\n\tthis.RegisterSRciStmt()\n\tthis.RegisterSRirciStmt()\n\tthis.RegisterSRrciStmt()\n\tthis.RegisterSRrcStmt()\n\tthis.RegisterSRriciStmt()\n\tthis.RegisterSRricStmt()\n\tthis.RegisterSRriStmt()\n\tthis.RegisterSRrrciStmt()\n\tthis.RegisterSRrrcStmt()\n\tthis.RegisterSRrriciStmt()\n\tthis.RegisterSRrriStmt()\n\tthis.RegisterSRrrStmt()\n\tthis.RegisterSRrStmt()\n\tthis.RegisterSRStmt()\n\n\tthis.RegisterNopStmt()\n\tthis.RegisterBkpStmt()\n\tthis.RegisterBootRiStmt()\n\tthis.RegisterCallRiStmt()\n\tthis.RegisterCallRrStmt()\n\tthis.RegisterDivStepDrdiStmt()\n\tthis.RegisterJeqRiiStmt()\n\tthis.RegisterJeqRriStmt()\n\tthis.RegisterJnzRiStmt()\n\tthis.RegisterJumpIStmt()\n\tthis.RegisterJumpRStmt()\n\tthis.RegisterLbsRriStmt()\n\tthis.RegisterLbsSRriStmt()\n\tthis.RegisterLdDriStmt()\n\tthis.RegisterMovdDdStmt()\n\tthis.RegisterMoveRiciStmt()\n\tthis.RegisterMoveRiStmt()\n\tthis.RegisterMoveSRiciStmt()\n\tthis.RegisterMoveSRiStmt()\n\tthis.RegisterSbIdRiiStmt()\n\tthis.RegisterSbIdRiStmt()\n\tthis.RegisterSbRirStmt()\n\tthis.RegisterSdRidStmt()\n\tthis.RegisterStopStmt()\n\tthis.RegisterTimeCfgRStmt()\n\n\tthis.RegisterLabelStmt()\n}\n\nfunc (this *Parser) Parse(token_stream *lexer.TokenStream) *Ast {\n\tfor pos := 0; pos < token_stream.Size(); pos++ {\n\t\ttoken := token_stream.Get(pos)\n\n\t\tthis.ReduceExpr(token)\n\n\t\tif token.TokenType() != lexer.NEW_LINE {\n\t\t\tstack_item := new(StackItem)\n\t\t\tstack_item.InitToken(token)\n\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tthis.ReduceStmt(token)\n\n\t\t\tif !this.stack.AreStmts() {\n\t\t\t\terr := errors.New(\"stack are not stmts\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n\n\tif !this.stack.CanAccept() {\n\t\terr := errors.New(\"stack cannot be accepted\")\n\t\tpanic(err)\n\t}\n\n\treturn this.stack.Accept()\n}\n\nfunc (this *Parser) ReduceExpr(token *lexer.Token) {\n\tfor {\n\t\treducible_expr_rule, stack_items := this.table.FindReducibleExprRule(token)\n\n\t\tif reducible_expr_rule != nil {\n\t\t\tstack_item := reducible_expr_rule.Reduce(stack_items, token)\n\n\t\t\tthis.stack.Pop(len(stack_items))\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nfunc (this *Parser) ReduceStmt(token *lexer.Token) {\n\tfor {\n\t\treducible_stmt_rule, stack_items := this.table.FindReducibleStmtRule(token)\n\n\t\tif reducible_stmt_rule != nil {\n\t\t\tstack_item := reducible_stmt_rule.Reduce(stack_items, token)\n\n\t\t\tthis.stack.Pop(len(stack_items))\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nfunc (this *Parser) RegisterAccessExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.IDENTIFIER &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken1 := stack_items[0].Token()\n\t\ttoken2 := stack_items[1].Token()\n\n\t\tattribute := token1.Attribute() + token2.Attribute()\n\n\t\ttoken := new(lexer.Token)\n\t\ttoken.Init(lexer.IDENTIFIER, attribute)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitToken(token)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterConcatExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.NEGATIVE_NUMBER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[1].Expr()\n\n\t\tnegative_number_expr := operand2.NegativeNumberExpr()\n\t\ttoken := negative_number_expr.Token()\n\n\t\tprimary_expr := new(expr.Expr)\n\t\tprimary_expr.InitPrimaryExpr(token)\n\n\t\tbinary_sub_expr := new(expr.Expr)\n\t\tbinary_sub_expr.InitBinarySubExpr(operand1, primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_sub_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterBinaryAddExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PLUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PRIMARY {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[2].Expr()\n\n\t\tbinary_add_expr := new(expr.Expr)\n\t\tbinary_add_expr.InitBinaryAddExpr(operand1, operand2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_add_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterBinarySubExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PRIMARY {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[2].Expr()\n\n\t\tbinary_sub_expr := new(expr.Expr)\n\t\tbinary_sub_expr.InitBinarySubExpr(operand1, operand2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_sub_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterCiOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.STOP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tci_op_code_expr := new(expr.Expr)\n\t\tci_op_code_expr.InitCiOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(ci_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDdciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.MOVD || token_type == lexer.SWAPD {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tddci_op_code_expr := new(expr.Expr)\n\t\tddci_op_code_expr.InitDdciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(ddci_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDmaRriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LDMA || token_type == lexer.LDMAI || token_type == lexer.SDMA {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tdma_rri_op_code_expr := new(expr.Expr)\n\t\tdma_rri_op_code_expr.InitDmaRriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(dma_rri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDrdiciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.DIV_STEP || token_type == lexer.MUL_STEP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tdrdici_op_code_expr := new(expr.Expr)\n\t\tdrdici_op_code_expr.InitDrdiciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(drdici_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterConditionExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.TRUE ||\n\t\t\t\t\ttoken_type == lexer.FALSE ||\n\t\t\t\t\ttoken_type == lexer.Z ||\n\t\t\t\t\ttoken_type == lexer.NZ ||\n\t\t\t\t\ttoken_type == lexer.E ||\n\t\t\t\t\ttoken_type == lexer.O ||\n\t\t\t\t\ttoken_type == lexer.PL ||\n\t\t\t\t\ttoken_type == lexer.MI ||\n\t\t\t\t\ttoken_type == lexer.OV ||\n\t\t\t\t\ttoken_type == lexer.NOV ||\n\t\t\t\t\ttoken_type == lexer.C ||\n\t\t\t\t\ttoken_type == lexer.NC ||\n\t\t\t\t\ttoken_type == lexer.SZ ||\n\t\t\t\t\ttoken_type == lexer.SNZ ||\n\t\t\t\t\ttoken_type == lexer.SPL ||\n\t\t\t\t\ttoken_type == lexer.SMI ||\n\t\t\t\t\ttoken_type == lexer.SO ||\n\t\t\t\t\ttoken_type == lexer.SE ||\n\t\t\t\t\ttoken_type == lexer.NC5 ||\n\t\t\t\t\ttoken_type == lexer.NC5 ||\n\t\t\t\t\ttoken_type == lexer.NC6 ||\n\t\t\t\t\ttoken_type == lexer.NC7 ||\n\t\t\t\t\ttoken_type == lexer.NC8 ||\n\t\t\t\t\ttoken_type == lexer.NC9 ||\n\t\t\t\t\ttoken_type == lexer.NC10 ||\n\t\t\t\t\ttoken_type == lexer.NC11 ||\n\t\t\t\t\ttoken_type == lexer.NC12 ||\n\t\t\t\t\ttoken_type == lexer.NC13 ||\n\t\t\t\t\ttoken_type == lexer.NC14 ||\n\t\t\t\t\ttoken_type == lexer.MAX ||\n\t\t\t\t\ttoken_type == lexer.NMAX ||\n\t\t\t\t\ttoken_type == lexer.SH32 ||\n\t\t\t\t\ttoken_type == lexer.NSH32 ||\n\t\t\t\t\ttoken_type == lexer.EQ ||\n\t\t\t\t\ttoken_type == lexer.NEQ ||\n\t\t\t\t\ttoken_type == lexer.LTU ||\n\t\t\t\t\ttoken_type == lexer.LEU ||\n\t\t\t\t\ttoken_type == lexer.GTU ||\n\t\t\t\t\ttoken_type == lexer.GEU ||\n\t\t\t\t\ttoken_type == lexer.LTS ||\n\t\t\t\t\ttoken_type == lexer.LES ||\n\t\t\t\t\ttoken_type == lexer.GTS ||\n\t\t\t\t\ttoken_type == lexer.GES ||\n\t\t\t\t\ttoken_type == lexer.XZ ||\n\t\t\t\t\ttoken_type == lexer.XNZ ||\n\t\t\t\t\ttoken_type == lexer.XLEU ||\n\t\t\t\t\ttoken_type == lexer.XGTU ||\n\t\t\t\t\ttoken_type == lexer.XLES ||\n\t\t\t\t\ttoken_type == lexer.XGTS ||\n\t\t\t\t\ttoken_type == lexer.SMALL ||\n\t\t\t\t\ttoken_type == lexer.LARGE {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tcondition_expr := new(expr.Expr)\n\t\tcondition_expr.InitConditionExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(condition_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterEndianExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LITTLE || token_type == lexer.BIG {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tendian_expr := new(expr.Expr)\n\t\tendian_expr.InitEndianExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(endian_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterIOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.FAULT || token_type == lexer.BKP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\ti_op_code_expr := new(expr.Expr)\n\t\ti_op_code_expr.InitIOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(i_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.JEQ ||\n\t\t\t\t\ttoken_type == lexer.JNEQ ||\n\t\t\t\t\ttoken_type == lexer.JZ ||\n\t\t\t\t\ttoken_type == lexer.JNZ ||\n\t\t\t\t\ttoken_type == lexer.JLTU ||\n\t\t\t\t\ttoken_type == lexer.JGTU ||\n\t\t\t\t\ttoken_type == lexer.JLEU ||\n\t\t\t\t\ttoken_type == lexer.JGEU ||\n\t\t\t\t\ttoken_type == lexer.JLTS ||\n\t\t\t\t\ttoken_type == lexer.JGTS ||\n\t\t\t\t\ttoken_type == lexer.JLES ||\n\t\t\t\t\ttoken_type == lexer.JGES ||\n\t\t\t\t\ttoken_type == lexer.JUMP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tjump_op_code_expr := new(expr.Expr)\n\t\tjump_op_code_expr.InitJumpOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(jump_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterLoadOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LBS ||\n\t\t\t\t\ttoken_type == lexer.LBU ||\n\t\t\t\t\ttoken_type == lexer.LD ||\n\t\t\t\t\ttoken_type == lexer.LHS ||\n\t\t\t\t\ttoken_type == lexer.LHU ||\n\t\t\t\t\ttoken_type == lexer.LW {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tload_op_code_expr := new(expr.Expr)\n\t\tload_op_code_expr.InitLoadOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(load_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterNegativeNumberExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.POSITIVIE_NUMBER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tnegativer_number_expr := new(expr.Expr)\n\t\tnegativer_number_expr.InitNegativeNumberExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(negativer_number_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExpr() {\n\tprecedence := map[lexer.TokenType]bool{lexer.IDENTIFIER: true}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.POSITIVIE_NUMBER || token_type == lexer.HEX_NUMBER || token_type == lexer.IDENTIFIER {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.Expr)\n\t\tprimary_expr.InitPrimaryExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(primary_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterProgramCounterExpr() {\n\tprecedence := map[lexer.TokenType]bool{lexer.PLUS: true, lexer.MINUS: true}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR {\n\t\t\t\texpr_type := stack_items[0].Expr().ExprType()\n\n\t\t\t\tif expr_type == expr.PRIMARY ||\n\t\t\t\t\texpr_type == expr.NEGATIVE_NUMBER ||\n\t\t\t\t\texpr_type == expr.BINARY_ADD ||\n\t\t\t\t\texpr_type == expr.BINARY_SUB {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[0].Expr()\n\n\t\tprogram_counter_expr := new(expr.Expr)\n\t\tprogram_counter_expr.InitProgramCounterExpr(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(program_counter_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterROpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.TIME || token_type == lexer.NOP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tr_op_code_expr := new(expr.Expr)\n\t\tr_op_code_expr.InitROpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(r_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRiciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ACQUIRE ||\n\t\t\t\t\ttoken_type == lexer.RELEASE ||\n\t\t\t\t\ttoken_type == lexer.BOOT ||\n\t\t\t\t\ttoken_type == lexer.RESUME {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trici_op_code_expr := new(expr.Expr)\n\t\trici_op_code_expr.InitRiciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rici_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRrOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.CAO ||\n\t\t\t\t\ttoken_type == lexer.CLO ||\n\t\t\t\t\ttoken_type == lexer.CLS ||\n\t\t\t\t\ttoken_type == lexer.CLZ ||\n\t\t\t\t\ttoken_type == lexer.EXTSB ||\n\t\t\t\t\ttoken_type == lexer.EXTSH ||\n\t\t\t\t\ttoken_type == lexer.EXTUB ||\n\t\t\t\t\ttoken_type == lexer.EXTUH ||\n\t\t\t\t\ttoken_type == lexer.SATS ||\n\t\t\t\t\ttoken_type == lexer.TIME_CFG ||\n\t\t\t\t\ttoken_type == lexer.MOVE ||\n\t\t\t\t\ttoken_type == lexer.NEG ||\n\t\t\t\t\ttoken_type == lexer.NOT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trr_op_code_expr := new(expr.Expr)\n\t\trr_op_code_expr.InitRrOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rr_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ADD ||\n\t\t\t\t\ttoken_type == lexer.ADDC ||\n\t\t\t\t\ttoken_type == lexer.AND ||\n\t\t\t\t\ttoken_type == lexer.ANDN ||\n\t\t\t\t\ttoken_type == lexer.ASR ||\n\t\t\t\t\ttoken_type == lexer.CMPB4 ||\n\t\t\t\t\ttoken_type == lexer.LSL ||\n\t\t\t\t\ttoken_type == lexer.LSL1 ||\n\t\t\t\t\ttoken_type == lexer.LSL1X ||\n\t\t\t\t\ttoken_type == lexer.LSLX ||\n\t\t\t\t\ttoken_type == lexer.LSR ||\n\t\t\t\t\ttoken_type == lexer.LSR1 ||\n\t\t\t\t\ttoken_type == lexer.LSR1X ||\n\t\t\t\t\ttoken_type == lexer.LSRX ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_SH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_SL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_SH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_SL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_UH_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_UH_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_UL_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_UL_UL ||\n\t\t\t\t\ttoken_type == lexer.NAND ||\n\t\t\t\t\ttoken_type == lexer.NOR ||\n\t\t\t\t\ttoken_type == lexer.NXOR ||\n\t\t\t\t\ttoken_type == lexer.OR ||\n\t\t\t\t\ttoken_type == lexer.ORN ||\n\t\t\t\t\ttoken_type == lexer.ROL ||\n\t\t\t\t\ttoken_type == lexer.ROR ||\n\t\t\t\t\ttoken_type == lexer.RSUB ||\n\t\t\t\t\ttoken_type == lexer.RSUBC ||\n\t\t\t\t\ttoken_type == lexer.SUB ||\n\t\t\t\t\ttoken_type == lexer.SUBC ||\n\t\t\t\t\ttoken_type == lexer.XOR ||\n\t\t\t\t\ttoken_type == lexer.CALL {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trri_op_code_expr := new(expr.Expr)\n\t\trri_op_code_expr.InitRriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LSL_ADD ||\n\t\t\t\t\ttoken_type == lexer.LSL_SUB ||\n\t\t\t\t\ttoken_type == lexer.LSR_ADD ||\n\t\t\t\t\ttoken_type == lexer.ROL_ADD {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trrri_op_code_expr := new(expr.Expr)\n\t\trrri_op_code_expr.InitRrriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rrri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterStoreOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.SB ||\n\t\t\t\t\ttoken_type == lexer.SB_ID ||\n\t\t\t\t\ttoken_type == lexer.SD ||\n\t\t\t\t\ttoken_type == lexer.SD_ID ||\n\t\t\t\t\ttoken_type == lexer.SH ||\n\t\t\t\t\ttoken_type == lexer.SH_ID ||\n\t\t\t\t\ttoken_type == lexer.SW ||\n\t\t\t\t\ttoken_type == lexer.SW_ID {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tstore_op_code_expr := new(expr.Expr)\n\t\tstore_op_code_expr.InitStoreOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(store_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSuffixExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.S || token_type == lexer.U {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsuffix_expr := new(expr.Expr)\n\t\tsuffix_expr.InitSuffixExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(suffix_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionNameExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ATOMIC ||\n\t\t\t\t\ttoken_type == lexer.BSS ||\n\t\t\t\t\ttoken_type == lexer.DATA ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_ABBREV ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_FRAME ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_INFO ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_LINE ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_LOC ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_RANGES ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_STR ||\n\t\t\t\t\ttoken_type == lexer.DPU_HOST ||\n\t\t\t\t\ttoken_type == lexer.MRAM ||\n\t\t\t\t\ttoken_type == lexer.RODATA ||\n\t\t\t\t\ttoken_type == lexer.STACK_SIZES ||\n\t\t\t\t\ttoken_type == lexer.TEXT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsection_name_expr := new(expr.Expr)\n\t\tsection_name_expr.InitSectionNameExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(section_name_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionTypeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.PROGBITS || token_type == lexer.NOBITS {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsection_type_expr := new(expr.Expr)\n\t\tsection_type_expr.InitSectionTypeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(section_type_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSrcRegExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.GP_REG ||\n\t\t\t\t\ttoken_type == lexer.ZERO_REG ||\n\t\t\t\t\ttoken_type == lexer.ONE ||\n\t\t\t\t\ttoken_type == lexer.ID ||\n\t\t\t\t\ttoken_type == lexer.ID2 ||\n\t\t\t\t\ttoken_type == lexer.ID4 ||\n\t\t\t\t\ttoken_type == lexer.ID8 ||\n\t\t\t\t\ttoken_type == lexer.LNEG ||\n\t\t\t\t\ttoken_type == lexer.MNEG {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsrc_reg_expr := new(expr.Expr)\n\t\tsrc_reg_expr.InitSrcRegExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(src_reg_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSymbolTypeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.FUNCTION || token_type == lexer.OBJECT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsymbol_type_expr := new(expr.Expr)\n\t\tsymbol_type_expr.InitSymbolTypeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(symbol_type_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterAddrsigStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ADDRSIG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\taddrsig_stmt := new(stmt.Stmt)\n\t\taddrsig_stmt.InitAddrsigStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(addrsig_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAddrsigSymStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ADDRSIG_SYM &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\taddrsig_sym_stmt := new(stmt.Stmt)\n\t\taddrsig_sym_stmt.InitAddrsigSymStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(addrsig_sym_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAsciiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ASCII &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tascii_stmt := new(stmt.Stmt)\n\t\tascii_stmt.InitAsciiStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ascii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAscizStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ASCIZ &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tasciz_stmt := new(stmt.Stmt)\n\t\tasciz_stmt.InitAscizStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(asciz_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterByteStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.BYTE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tbyte_stmt := new(stmt.Stmt)\n\t\tbyte_stmt.InitByteStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(byte_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiDefCfaOffsetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_DEF_CFA_OFFSET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tcfi_def_cfa_offset_stmt := new(stmt.Stmt)\n\t\tcfi_def_cfa_offset_stmt.InitCfiDefCfaOffsetStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_def_cfa_offset_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiEndprocStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_ENDPROC {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcfi_endproc_stmt := new(stmt.Stmt)\n\t\tcfi_endproc_stmt.InitCfiEndprocStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_endproc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiOffsetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_OFFSET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tcfi_offset_stmt := new(stmt.Stmt)\n\t\tcfi_offset_stmt.InitCfiOffsetStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_offset_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiSectionsStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_SECTIONS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tcfi_sections_stmt := new(stmt.Stmt)\n\t\tcfi_sections_stmt.InitCfiSectionsStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_sections_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiStartprocStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_STARTPROC {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcfi_startproc_stmt := new(stmt.Stmt)\n\t\tcfi_startproc_stmt.InitCfiStartprocStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_startproc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterFileNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.FILE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\t\ttoken1 := stack_items[2].Token()\n\t\ttoken2 := stack_items[3].Token()\n\n\t\tfile_number_stmt := new(stmt.Stmt)\n\t\tfile_number_stmt.InitFileNumberStmt(expr_, token1, token2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(file_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterFileStringStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.FILE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tfile_string_stmt := new(stmt.Stmt)\n\t\tfile_string_stmt.InitFileStringStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(file_string_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterGlobalStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.GLOBL &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tglobal_stmt := new(stmt.Stmt)\n\t\tglobal_stmt.InitGlobalStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(global_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocIsStmtStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.IS_STMT &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\t\texpr4 := stack_items[5].Expr()\n\n\t\tloc_is_stmt_stmt := new(stmt.Stmt)\n\t\tloc_is_stmt_stmt.InitLocIsStmtStmt(expr1, expr2, expr3, expr4)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_is_stmt_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\n\t\tloc_number_stmt := new(stmt.Stmt)\n\t\tloc_number_stmt.InitLocNumberStmt(expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocPrologueEndStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.PROLOGUE_END {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\n\t\tloc_prologue_end_stmt := new(stmt.Stmt)\n\t\tloc_prologue_end_stmt.InitLocPrologueEndStmt(expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_prologue_end_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLongProgramCounterStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LONG &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tlong_program_counter_stmt := new(stmt.Stmt)\n\t\tlong_program_counter_stmt.InitLongProgramCounterStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(long_program_counter_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLongSectionNameStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LONG &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tlong_section_name_stmt := new(stmt.Stmt)\n\t\tlong_section_name_stmt.InitLongSectionNameStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(long_section_name_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterP2AlignStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.P2ALIGN &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tp2align_stmt := new(stmt.Stmt)\n\t\tp2align_stmt.InitP2AlignStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(p2align_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterQuadStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.QUAD &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tquad_stmt := new(stmt.Stmt)\n\t\tquad_stmt.InitQuadStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(quad_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionIdentifierNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\ttoken := stack_items[4].Token()\n\t\texpr3 := stack_items[6].Expr()\n\t\texpr4 := stack_items[8].Expr()\n\n\t\tsection_identifier_number_stmt := new(stmt.Stmt)\n\t\tsection_identifier_number_stmt.InitSectionIdentifierNumberStmt(\n\t\t\texpr1,\n\t\t\texpr2,\n\t\t\ttoken,\n\t\t\texpr3,\n\t\t\texpr4,\n\t\t)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_identifier_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionIdentifierStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SECTION_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\ttoken := stack_items[4].Token()\n\t\texpr3 := stack_items[6].Expr()\n\n\t\tsection_identifier_stmt := new(stmt.Stmt)\n\t\tsection_identifier_stmt.InitSectionIdentifierStmt(expr1, expr2, token, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_identifier_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStackSizesStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[3].Token()\n\t\texpr1 := stack_items[5].Expr()\n\t\texpr2 := stack_items[7].Expr()\n\t\texpr3 := stack_items[8].Expr()\n\n\t\tsection_stack_sizes_stmt := new(stmt.Stmt)\n\t\tsection_stack_sizes_stmt.InitSectionStackSizesStmt(token, expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_stack_sizes_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStringNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\ttoken := stack_items[3].Token()\n\t\texpr2 := stack_items[5].Expr()\n\t\texpr3 := stack_items[7].Expr()\n\n\t\tsection_string_number_stmt := new(stmt.Stmt)\n\t\tsection_string_number_stmt.InitSectionStringNumberStmt(expr1, token, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_string_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStringStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\ttoken := stack_items[3].Token()\n\t\texpr2 := stack_items[5].Expr()\n\n\t\tsection_string_stmt := new(stmt.Stmt)\n\t\tsection_string_stmt.InitSectionStringStmt(expr1, token, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_string_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tset_stmt := new(stmt.Stmt)\n\t\tset_stmt.InitSetStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(set_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterShortStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SHORT &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tshort_stmt := new(stmt.Stmt)\n\t\tshort_stmt.InitShortStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(short_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSizeStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SIZE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tsize_stmt := new(stmt.Stmt)\n\t\tsize_stmt.InitSizeStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(size_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTextStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\texpr_ := stack_items[0].Expr()\n\t\t\t\tif expr_.SectionNameExpr().Token().TokenType() == lexer.TEXT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttext_stmt := new(stmt.Stmt)\n\t\ttext_stmt.InitTextStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(text_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.TYPE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SYMBOL_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\ttype_stmt := new(stmt.Stmt)\n\t\ttype_stmt.InitTypeStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(type_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterWeakStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.WEAK &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tweak_stmt := new(stmt.Stmt)\n\t\tweak_stmt.InitWeakStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(weak_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterZeroDoubleNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ZERO_DIRECTIVE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tzero_double_number_stmt := new(stmt.Stmt)\n\t\tzero_double_number_stmt.InitZeroDoubleNumberStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(zero_double_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterZeroSingleNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ZERO_DIRECTIVE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tzero_single_number_stmt := new(stmt.Stmt)\n\t\tzero_single_number_stmt.InitZeroSingleNumberStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(zero_single_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.CI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tcondition := stack_items[1].Expr()\n\t\tpc := stack_items[3].Expr()\n\n\t\tci_stmt := new(stmt.Stmt)\n\t\tci_stmt.InitCiStmt(op_code, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDdciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DDCI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tdb := stack_items[3].Token()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\tddci_stmt := new(stmt.Stmt)\n\t\tddci_stmt.InitDdciStmt(op_code, dc, db, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ddci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDmaRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DMA_RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\trb := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tdma_rri_stmt := new(stmt.Stmt)\n\t\tdma_rri_stmt.InitDmaRriStmt(op_code, ra, rb, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(dma_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDrdiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 12 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DRDICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[10].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[10].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[11].StackItemType() == EXPR &&\n\t\t\t\tstack_items[11].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\t\timm := stack_items[7].Expr()\n\t\tcondition := stack_items[9].Expr()\n\t\tpc := stack_items[11].Expr()\n\n\t\tdrdici_stmt := new(stmt.Stmt)\n\t\tdrdici_stmt.InitDrdiciStmt(op_code, dc, ra, db, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(drdici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEdriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tdc := stack_items[3].Token()\n\t\tra := stack_items[5].Expr()\n\t\toff := stack_items[7].Expr()\n\n\t\tedri_stmt := new(stmt.Stmt)\n\t\tedri_stmt.InitEdriStmt(op_code, endian, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(edri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEridStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\tdb := stack_items[7].Token()\n\n\t\tedri_stmt := new(stmt.Stmt)\n\t\tedri_stmt.InitEridStmt(op_code, endian, ra, off, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(edri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEriiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\n\t\terii_stmt := new(stmt.Stmt)\n\t\terii_stmt.InitEriiStmt(op_code, endian, ra, off, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterErirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\trb := stack_items[7].Expr()\n\n\t\terir_stmt := new(stmt.Stmt)\n\t\terir_stmt.InitErirStmt(op_code, endian, ra, off, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterErriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\trc := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\toff := stack_items[7].Expr()\n\n\t\terri_stmt := new(stmt.Stmt)\n\t\terri_stmt.InitErriStmt(op_code, endian, rc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterIStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.I_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\timm := stack_items[1].Expr()\n\n\t\ti_stmt := new(stmt.Stmt)\n\t\ti_stmt.InitIStmt(op_code, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(i_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tcondition := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\trci_stmt := new(stmt.Stmt)\n\t\trci_stmt.InitRciStmt(op_code, rc, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\trici_stmt := new(stmt.Stmt)\n\t\trici_stmt.InitRiciStmt(op_code, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRirciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trirci_stmt := new(stmt.Stmt)\n\t\trirci_stmt.InitRirciStmt(op_code, rc, imm, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rirci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRircStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trirc_stmt := new(stmt.Stmt)\n\t\trirc_stmt.InitRircStmt(op_code, rc, imm, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rirc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\n\t\trir_stmt := new(stmt.Stmt)\n\t\trir_stmt.InitRirStmt(op_code, rc, imm, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\trrci_stmt := new(stmt.Stmt)\n\t\trrci_stmt.InitRrciStmt(op_code, rc, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\n\t\trrc_stmt := new(stmt.Stmt)\n\t\trrc_stmt.InitRrcStmt(op_code, rc, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trrici_stmt := new(stmt.Stmt)\n\t\trrici_stmt.InitRriciStmt(op_code, rc, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRricStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trric_stmt := new(stmt.Stmt)\n\t\trric_stmt.InitRricStmt(op_code, rc, ra, imm, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rric_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\n\t\trri_stmt := new(stmt.Stmt)\n\t\trri_stmt.InitRriStmt(op_code, rc, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trrrci_stmt := new(stmt.Stmt)\n\t\trrrci_stmt.InitRrrciStmt(op_code, rc, ra, rb, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trrrc_stmt := new(stmt.Stmt)\n\t\trrrc_stmt.InitRrrcStmt(op_code, rc, ra, rb, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 12 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[10].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[10].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[11].StackItemType() == EXPR &&\n\t\t\t\tstack_items[11].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\t\tcondition := stack_items[9].Expr()\n\t\tpc := stack_items[11].Expr()\n\n\t\trrrici_stmt := new(stmt.Stmt)\n\t\trrrici_stmt.InitRrriciStmt(op_code, rc, ra, rb, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\n\t\trrri_stmt := new(stmt.Stmt)\n\t\trrri_stmt.InitRrriStmt(op_code, rc, ra, rb, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\n\t\trrr_stmt := new(stmt.Stmt)\n\t\trrr_stmt.InitRrrStmt(op_code, rc, ra, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\n\t\trr_stmt := new(stmt.Stmt)\n\t\trr_stmt.InitRrStmt(op_code, rc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\n\t\tr_stmt := new(stmt.Stmt)\n\t\tr_stmt.InitRStmt(op_code, rc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSErriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tendian := stack_items[2].Expr()\n\t\tdc := stack_items[4].Token()\n\t\tra := stack_items[6].Expr()\n\t\toff := stack_items[8].Expr()\n\n\t\ts_erri_stmt := new(stmt.Stmt)\n\t\ts_erri_stmt.InitSErriStmt(op_code, suffix, endian, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_erri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tcondition := stack_items[4].Expr()\n\t\tpc := stack_items[6].Expr()\n\n\t\ts_rci_stmt := new(stmt.Stmt)\n\t\ts_rci_stmt.InitSRciStmt(op_code, suffix, dc, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRirciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tra := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rirci_stmt := new(stmt.Stmt)\n\t\ts_rirci_stmt.InitSRirciStmt(op_code, suffix, dc, imm, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rirci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRircStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tra := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\n\t\ts_rirc_stmt := new(stmt.Stmt)\n\t\ts_rirc_stmt.InitSRircStmt(op_code, suffix, dc, imm, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rirc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\t\tpc := stack_items[8].Expr()\n\n\t\ts_rrci_stmt := new(stmt.Stmt)\n\t\ts_rrci_stmt.InitSRrciStmt(op_code, suffix, dc, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\n\t\ts_rrc_stmt := new(stmt.Stmt)\n\t\ts_rrc_stmt.InitSRrcStmt(op_code, suffix, dc, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rrici_stmt := new(stmt.Stmt)\n\t\ts_rrici_stmt.InitSRriciStmt(op_code, suffix, dc, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRricStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\n\t\ts_rric_stmt := new(stmt.Stmt)\n\t\ts_rric_stmt.InitSRricStmt(op_code, suffix, dc, ra, imm, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rric_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\n\t\ts_rri_stmt := new(stmt.Stmt)\n\t\ts_rri_stmt.InitSRriStmt(op_code, suffix, dc, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rrrci_stmt := new(stmt.Stmt)\n\t\ts_rrrci_stmt.InitSRrrciStmt(op_code, suffix, dc, ra, rb, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\ts_rrrc_stmt := new(stmt.Stmt)\n\t\ts_rrrc_stmt.InitSRrrcStmt(op_code, suffix, dc, ra, rb, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 13 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[11].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[11].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[12].StackItemType() == EXPR &&\n\t\t\t\tstack_items[12].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\timm := stack_items[8].Expr()\n\t\tcondition := stack_items[10].Expr()\n\t\tpc := stack_items[12].Expr()\n\n\t\ts_rrrici_stmt := new(stmt.Stmt)\n\t\ts_rrrici_stmt.InitSRrriciStmt(op_code, suffix, dc, ra, rb, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\timm := stack_items[8].Expr()\n\n\t\ts_rrri_stmt := new(stmt.Stmt)\n\t\ts_rrri_stmt.InitSRrriStmt(op_code, suffix, dc, ra, rb, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\n\t\ts_rrr_stmt := new(stmt.Stmt)\n\t\ts_rrr_stmt.InitSRrrStmt(op_code, suffix, dc, ra, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\n\t\ts_rr_stmt := new(stmt.Stmt)\n\t\ts_rr_stmt.InitSRrStmt(op_code, suffix, dc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\n\t\ts_r_stmt := new(stmt.Stmt)\n\t\ts_r_stmt.InitSRStmt(op_code, suffix, dc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterNopStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\tif op_code.ROpCodeExpr().Token().TokenType() != lexer.NOP {\n\t\t\terr := errors.New(\"op code is not NOP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tnop_stmt := new(stmt.Stmt)\n\t\tnop_stmt.InitNopStmt(op_code)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(nop_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterBkpStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.I_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\tif op_code.IOpCodeExpr().Token().TokenType() != lexer.BKP {\n\t\t\terr := errors.New(\"op code is not BKP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbkp_stmt := new(stmt.Stmt)\n\t\tbkp_stmt.InitBkpStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(bkp_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterBootRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RiciOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.BOOT && token_type != lexer.RESUME {\n\t\t\terr := errors.New(\"op code is not BOOT nor RESUME\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tboot_ri_stmt := new(stmt.Stmt)\n\t\tboot_ri_stmt.InitBootRiStmt(op_code, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(boot_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCallRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RriOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.CALL {\n\t\t\terr := errors.New(\"op code is not CALL\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tcall_ri_stmt := new(stmt.Stmt)\n\t\tcall_ri_stmt.InitCallRiStmt(rc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(call_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCallRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RriOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.CALL {\n\t\t\terr := errors.New(\"op code is not CALL\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tcall_rr_stmt := new(stmt.Stmt)\n\t\tcall_rr_stmt.InitCallRrStmt(rc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(call_rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDivStepDrdiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DRDICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\t\tpc := stack_items[7].Expr()\n\n\t\tdiv_step_drdi_stmt := new(stmt.Stmt)\n\t\tdiv_step_drdi_stmt.InitDivStepDrdiStmt(op_code, dc, ra, db, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(div_step_drdi_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJeqRiiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tjeq_rii_stmt := new(stmt.Stmt)\n\t\tjeq_rii_stmt.InitJeqRiiStmt(op_code, ra, imm, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jeq_rii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJeqRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\trb := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tjeq_rri_stmt := new(stmt.Stmt)\n\t\tjeq_rri_stmt.InitJeqRriStmt(op_code, ra, rb, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jeq_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJnzRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\tpc := stack_items[3].Expr()\n\n\t\tjnz_ri_stmt := new(stmt.Stmt)\n\t\tjnz_ri_stmt.InitJnzRiStmt(op_code, ra, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jnz_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpIStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tpc := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.JumpOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.JUMP {\n\t\t\terr := errors.New(\"op code is not JUMP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tjump_i_stmt := new(stmt.Stmt)\n\t\tjump_i_stmt.InitJumpIStmt(pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jump_i_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.JumpOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.JUMP {\n\t\t\terr := errors.New(\"op code is not JUMP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tjump_r_stmt := new(stmt.Stmt)\n\t\tjump_r_stmt.InitJumpRStmt(ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jump_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLbsRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\n\t\tlbs_rri_stmt := new(stmt.Stmt)\n\t\tlbs_rri_stmt.InitLbsRriStmt(op_code, rc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(lbs_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLbsSRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\toff := stack_items[6].Expr()\n\n\t\tlbs_s_rri_stmt := new(stmt.Stmt)\n\t\tlbs_s_rri_stmt.InitLbsSRriStmt(op_code, suffix, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(lbs_s_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLdDriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\n\t\tld_dri_stmt := new(stmt.Stmt)\n\t\tld_dri_stmt.InitLdDriStmt(op_code, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ld_dri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMovdDdStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DDCI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tdb := stack_items[3].Token()\n\n\t\tmovd_dd_stmt := new(stmt.Stmt)\n\t\tmovd_dd_stmt.InitMovdDdStmt(op_code, dc, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(movd_dd_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_rici_stmt := new(stmt.Stmt)\n\t\tmove_rici_stmt.InitMoveRiciStmt(rc, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_ri_stmt := new(stmt.Stmt)\n\t\tmove_ri_stmt.InitMoveRiStmt(rc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveSRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\t\tpc := stack_items[8].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_s_rici_stmt := new(stmt.Stmt)\n\t\tmove_s_rici_stmt.InitMoveSRiciStmt(suffix, dc, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_s_rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveSRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_s_ri_stmt := new(stmt.Stmt)\n\t\tmove_s_ri_stmt.InitMoveSRiStmt(suffix, dc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_s_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbIdRiiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\n\t\tsb_id_rii_stmt := new(stmt.Stmt)\n\t\tsb_id_rii_stmt.InitSbIdRiiStmt(op_code, ra, off, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_id_rii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbIdRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\n\t\tsb_id_ri_stmt := new(stmt.Stmt)\n\t\tsb_id_ri_stmt.InitSbIdRiStmt(op_code, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_id_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbRirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\n\t\tsb_rir_stmt := new(stmt.Stmt)\n\t\tsb_rir_stmt.InitSbRirStmt(op_code, ra, off, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_rir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSdRidStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\n\t\tsd_rid_stmt := new(stmt.Stmt)\n\t\tsd_rid_stmt.InitSdRidStmt(op_code, ra, off, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sd_rid_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterStopStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.CI_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\ttoken_type := op_code.CiOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.STOP {\n\t\t\terr := errors.New(\"op code is not STOP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tstop_stmt := new(stmt.Stmt)\n\t\tstop_stmt.InitStopStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stop_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTimeCfgRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.TIME_CFG {\n\t\t\terr := errors.New(\"op code is not TIME_CFG\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\ttime_cfg_r_stmt := new(stmt.Stmt)\n\t\ttime_cfg_r_stmt.InitTimeCfgRStmt(ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(time_cfg_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLabelStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.COLON {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[0].Expr()\n\n\t\tlabel_stmt := new(stmt.Stmt)\n\t\tlabel_stmt.InitLabelStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(label_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/rule.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype Reducible func([]*StackItem) bool\ntype Reduce func([]*StackItem) *StackItem\n\ntype Rule struct {\n\tprecedence map[lexer.TokenType]bool\n\n\treducible Reducible\n\treduce    Reduce\n}\n\nfunc (this *Rule) Init(precedence map[lexer.TokenType]bool, reducible Reducible, reduce Reduce) {\n\tthis.precedence = precedence\n\tthis.reducible = reducible\n\tthis.reduce = reduce\n}\n\nfunc (this *Rule) IsReducible(stack_items []*StackItem, token *lexer.Token) bool {\n\tif _, found := this.precedence[token.TokenType()]; found {\n\t\treturn false\n\t} else {\n\t\treturn this.reducible(stack_items)\n\t}\n}\n\nfunc (this *Rule) Reduce(stack_items []*StackItem, token *lexer.Token) *StackItem {\n\tif !this.IsReducible(stack_items, token) {\n\t\terr := errors.New(\"stack items are not reducible\")\n\t\tpanic(err)\n\t}\n\n\treturn this.reduce(stack_items)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stack.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype Stack struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *Stack) Init() {\n\tthis.stack_items = make([]*StackItem, 0)\n}\n\nfunc (this *Stack) Push(stack_item *StackItem) {\n\tthis.stack_items = append(this.stack_items, stack_item)\n}\n\nfunc (this *Stack) Pop(num int) {\n\tthis.stack_items = this.stack_items[:len(this.stack_items)-num]\n}\n\nfunc (this *Stack) Front(num int) []*StackItem {\n\tstack_items := make([]*StackItem, 0)\n\tfor i := 0; i < num; i++ {\n\t\tstack_item := this.stack_items[len(this.stack_items)-num+i]\n\t\tstack_items = append(stack_items, stack_item)\n\t}\n\treturn stack_items\n}\n\nfunc (this *Stack) NonStmtSize() int {\n\tnon_stmt_size := 0\n\tfor i := len(this.stack_items) - 1; i >= 0; i-- {\n\t\tstack_item := this.stack_items[i]\n\n\t\tif stack_item.StackItemType() != STMT {\n\t\t\tnon_stmt_size++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn non_stmt_size\n}\n\nfunc (this *Stack) AreStmts() bool {\n\tfor _, stack_item := range this.stack_items {\n\t\tif stack_item.StackItemType() == STMT {\n\t\t\tcontinue\n\t\t} else {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *Stack) CanAccept() bool {\n\tfor i, stack_item := range this.stack_items {\n\t\tif i < len(this.stack_items)-1 {\n\t\t\tif stack_item.StackItemType() == STMT {\n\t\t\t\tcontinue\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t} else {\n\t\t\tif stack_item.StackItemType() == TOKEN && stack_item.Token().TokenType() == lexer.END_OF_FILE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Stack) Accept() *Ast {\n\tif !this.CanAccept() {\n\t\terr := errors.New(\"stack cannot be accepted\")\n\t\tpanic(err)\n\t}\n\n\tstmts := make([]*stmt.Stmt, 0)\n\tfor i := 0; i < len(this.stack_items)-1; i++ {\n\t\tstmts = append(stmts, this.stack_items[i].Stmt())\n\t}\n\n\tast := new(Ast)\n\tast.Init(stmts)\n\n\treturn ast\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stack_item.go",
    "content": "package parser\n\nimport (\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype StackItemType int\n\nconst (\n\tTOKEN StackItemType = iota\n\tEXPR\n\tSTMT\n)\n\ntype StackItem struct {\n\tstack_item_type StackItemType\n\n\ttoken *lexer.Token\n\texpr  *expr.Expr\n\tstmt  *stmt.Stmt\n}\n\nfunc (this *StackItem) InitToken(token *lexer.Token) {\n\tthis.stack_item_type = TOKEN\n\n\tthis.token = token\n}\n\nfunc (this *StackItem) InitExpr(expr *expr.Expr) {\n\tthis.stack_item_type = EXPR\n\n\tthis.expr = expr\n}\n\nfunc (this *StackItem) InitStmt(stmt *stmt.Stmt) {\n\tthis.stack_item_type = STMT\n\n\tthis.stmt = stmt\n}\n\nfunc (this *StackItem) StackItemType() StackItemType {\n\treturn this.stack_item_type\n}\n\nfunc (this *StackItem) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *StackItem) Expr() *expr.Expr {\n\treturn this.expr\n}\n\nfunc (this *StackItem) Stmt() *stmt.Stmt {\n\treturn this.stmt\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/addrsig_stmt.go",
    "content": "package directive\n\ntype AddrsigStmt struct {\n}\n\nfunc (this *AddrsigStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/addrsig_sym_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype AddrsigSymStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *AddrsigSymStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *AddrsigSymStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/ascii_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype AsciiStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *AsciiStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *AsciiStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/asciz_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype AscizStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *AscizStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *AscizStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/byte_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ByteStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ByteStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ByteStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/cfi_def_cfa_offset_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CfiDefCfaOffsetStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *CfiDefCfaOffsetStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *CfiDefCfaOffsetStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/cfi_endproc.go",
    "content": "package directive\n\ntype CfiEndprocStmt struct {\n}\n\nfunc (this *CfiEndprocStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/cfi_offset_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CfiOffsetStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *CfiOffsetStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *CfiOffsetStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *CfiOffsetStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/cfi_sections_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CfiSectionsStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *CfiSectionsStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *CfiSectionsStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/cfi_startproc_stmt.go",
    "content": "package directive\n\ntype CfiStartprocStmt struct {\n}\n\nfunc (this *CfiStartprocStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/file_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype FileNumberStmt struct {\n\texpr   *expr.Expr\n\ttoken1 *lexer.Token\n\ttoken2 *lexer.Token\n}\n\nfunc (this *FileNumberStmt) Init(expr_ *expr.Expr, token1 *lexer.Token, token2 *lexer.Token) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token1.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token1 is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif token2.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token2 is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n\tthis.token1 = token1\n\tthis.token2 = token2\n}\n\nfunc (this *FileNumberStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n\nfunc (this *FileNumberStmt) Token1() *lexer.Token {\n\treturn this.token1\n}\n\nfunc (this *FileNumberStmt) Token2() *lexer.Token {\n\treturn this.token2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/file_string_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype FileStringStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *FileStringStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *FileStringStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/global_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype GlobalStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *GlobalStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *GlobalStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/loc_is_stmt_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LocIsStmtStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n\texpr4 *expr.Expr\n}\n\nfunc (this *LocIsStmtStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr4.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr4 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n\tthis.expr4 = expr4\n}\n\nfunc (this *LocIsStmtStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocIsStmtStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocIsStmtStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n\nfunc (this *LocIsStmtStmt) Expr4() *expr.Expr {\n\treturn this.expr4\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/loc_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LocNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *LocNumberStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *LocNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/loc_prologue_end_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LocPrologueEndStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *LocPrologueEndStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *LocPrologueEndStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocPrologueEndStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocPrologueEndStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/long_program_counter.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LongProgramCounterStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LongProgramCounterStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LongProgramCounterStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/long_section_name_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LongSectionNameStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LongSectionNameStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LongSectionNameStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/p2_align_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype P2AlignStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *P2AlignStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *P2AlignStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/quad_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype QuadStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *QuadStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *QuadStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/section_identifier_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SectionIdentifierNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\ttoken *lexer.Token\n\texpr3 *expr.Expr\n\texpr4 *expr.Expr\n}\n\nfunc (this *SectionIdentifierNumberStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr3 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr4.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr4 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.token = token\n\tthis.expr3 = expr3\n\tthis.expr4 = expr4\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionIdentifierNumberStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr4() *expr.Expr {\n\treturn this.expr4\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/section_identifier_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SectionIdentifierStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\ttoken *lexer.Token\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionIdentifierStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr3 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.token = token\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionIdentifierStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionIdentifierStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionIdentifierStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionIdentifierStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/section_stack_sizes_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SectionStackSizesStmt struct {\n\ttoken *lexer.Token\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionStackSizesStmt) Init(\n\ttoken *lexer.Token,\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr1.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr1 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr2 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionStackSizesStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStackSizesStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStackSizesStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionStackSizesStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/section_string_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SectionStringNumberStmt struct {\n\texpr1 *expr.Expr\n\ttoken *lexer.Token\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionStringNumberStmt) Init(\n\texpr1 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr2 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.token = token\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionStringNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStringNumberStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStringNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionStringNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/section_string_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SectionStringStmt struct {\n\texpr1 *expr.Expr\n\ttoken *lexer.Token\n\texpr2 *expr.Expr\n}\n\nfunc (this *SectionStringStmt) Init(expr1 *expr.Expr, token *lexer.Token, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr2 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.token = token\n\tthis.expr2 = expr2\n}\n\nfunc (this *SectionStringStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStringStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStringStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/set_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SetStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *SetStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *SetStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SetStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/short_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ShortStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ShortStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ShortStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/size_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SizeStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *SizeStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *SizeStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SizeStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/text_stmt.go",
    "content": "package directive\n\ntype TextStmt struct {\n}\n\nfunc (this *TextStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/type_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype TypeStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *TypeStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SYMBOL_TYPE {\n\t\terr := errors.New(\"expr is not a symbol type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr2\n}\n\nfunc (this *TypeStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *TypeStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/weak_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype WeakStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *WeakStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *WeakStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/zero_double_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ZeroDoubleNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *ZeroDoubleNumberStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *ZeroDoubleNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *ZeroDoubleNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/directive/zero_single_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ZeroSingleNumberStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ZeroSingleNumberStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ZeroSingleNumberStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/ci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CiStmt struct {\n\top_code   *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *CiStmt) Init(op_code *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.CI_OP_CODE {\n\t\terr := errors.New(\"op code is not a CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *CiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *CiStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *CiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/ddci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype DdciStmt struct {\n\top_code   *expr.Expr\n\tdc        *lexer.Token\n\tdb        *lexer.Token\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *DdciStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tdb *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DDCI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.db = db\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *DdciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DdciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DdciStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DdciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *DdciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/dma_rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype DmaRriStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *DmaRriStmt) Init(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.DMA_RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *DmaRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DmaRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DmaRriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *DmaRriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/drdici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype DrdiciStmt struct {\n\top_code   *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tdb        *lexer.Token\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *DrdiciStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DRDICI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *DrdiciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DrdiciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DrdiciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DrdiciStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DrdiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *DrdiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *DrdiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/edri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype EdriStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *EdriStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *EdriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EdriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EdriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *EdriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EdriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/erid_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype EridStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\tdb      *lexer.Token\n}\n\nfunc (this *EridStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.db = db\n}\n\nfunc (this *EridStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EridStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EridStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EridStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *EridStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/erii_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype EriiStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *EriiStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.imm = imm\n}\n\nfunc (this *EriiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EriiStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EriiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EriiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *EriiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/erir_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ErirStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *ErirStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\trb *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.rb = rb\n}\n\nfunc (this *ErirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *ErirStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *ErirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *ErirStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *ErirStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/erri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype ErriStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *ErriStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *ErriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *ErriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *ErriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *ErriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *ErriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/i_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype IStmt struct {\n\top_code *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *IStmt) Init(op_code *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.I_OP_CODE {\n\t\terr := errors.New(\"op code is not an I op code\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.imm = imm\n}\n\nfunc (this *IStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *IStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/nop_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype NopStmt struct {\n\top_code *expr.Expr\n}\n\nfunc (this *NopStmt) Init(op_code *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n}\n\nfunc (this *NopStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/r_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n}\n\nfunc (this *RStmt) Init(op_code *expr.Expr, rc *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n}\n\nfunc (this *RStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RciStmt) Init(op_code *expr.Expr, rc *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RiciStmt struct {\n\top_code   *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RiciStmt) Init(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RICI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RiciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RiciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rir_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RirStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\timm     *expr.Expr\n\tra      *expr.Expr\n}\n\nfunc (this *RirStmt) Init(op_code *expr.Expr, rc *expr.Expr, imm *expr.Expr, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n}\n\nfunc (this *RirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RirStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RirStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rirc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RircStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RircStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *RircStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RircStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RircStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RircStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RircStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rirci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RirciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RirciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RirciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RirciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RirciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RirciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RirciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RirciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n}\n\nfunc (this *RrStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *RrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrcStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RrcStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, condition *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *RrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrcStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *RriStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *RriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rric_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RricStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RricStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n}\n\nfunc (this *RricStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RricStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RricStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RricStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RricStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RriciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RriciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RriciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrrStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *RrrStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, rb *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *RrrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrrcStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RrrcStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n}\n\nfunc (this *RrrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrcStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrcStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrrciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrrciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *RrriStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *RrriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/rrrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype RrriciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrriciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrriciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrriciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RrriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_erri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SErriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tendian  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *SErriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.endian = endian\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *SErriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SErriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SErriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *SErriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SErriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SErriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_r_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n}\n\nfunc (this *SRStmt) Init(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n}\n\nfunc (this *SRStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rirc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRircStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRircStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *SRircStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRircStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRircStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRircStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRircStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRircStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rirci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRirciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRirciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRirciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRirciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRirciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRirciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRirciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRirciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRirciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n}\n\nfunc (this *SRrStmt) Init(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n}\n\nfunc (this *SRrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrcStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRrcStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *SRrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrcStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrcStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SRriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *SRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rric_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRricStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRricStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n}\n\nfunc (this *SRricStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRricStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRricStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRricStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRricStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRricStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRriciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRriciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRriciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRriciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrrStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *SRrrStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *SRrrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrrcStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRrrcStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n}\n\nfunc (this *SRrrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrcStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrcStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrcStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrrciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrrciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SRrriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *SRrriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/instruction/s_rrrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SRrriciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrriciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrriciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrriciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrriciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRrriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/label_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LabelStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LabelStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LabelStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/stmt.go",
    "content": "package stmt\n\nimport (\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt/directive\"\n\t\"uPIMulator/src/linker/parser/stmt/instruction\"\n\t\"uPIMulator/src/linker/parser/stmt/sugar\"\n)\n\ntype StmtType int\n\nconst (\n\tADDRSIG StmtType = iota\n\tADDRSIG_SYM\n\tASCII\n\tASCIZ\n\tBYTE\n\tCFI_DEF_CFA_OFFSET\n\tCFI_ENDPROC\n\tCFI_OFFSET\n\tCFI_SECTIONS\n\tCFI_STARTPROC\n\tFILE_NUMBER\n\tFILE_STRING\n\tGLOBAL\n\tLOC_IS_STMT\n\tLOC_NUMBER\n\tLOC_PROLOGUE_END\n\tLONG_PROGRAM_COUNTER\n\tLONG_SECTION_NAME\n\tP2_ALIGN\n\tQUAD\n\tSECTION_IDENTIFIER_NUMBER\n\tSECTION_IDENTIFIER\n\tSECTION_STACK_SIZES\n\tSECTION_STRING_NUMBER\n\tSECTION_STRING\n\tSET\n\tSHORT\n\tSIZE\n\tTEXT\n\tTYPE\n\tWEAK\n\tZERO_SINGLE_NUMBER\n\tZERO_DOUBLE_NUMBER\n\n\tRICI\n\tRRI\n\tRRIC\n\tRRICI\n\tRRR\n\tRRRC\n\tRRRCI\n\n\tS_RRI\n\tS_RRIC\n\tS_RRICI\n\tS_RRR\n\tS_RRRC\n\tS_RRRCI\n\n\tRR\n\tRRC\n\tRRCI\n\n\tS_RR\n\tS_RRC\n\tS_RRCI\n\n\tDRDICI\n\n\tRRRI\n\tRRRICI\n\n\tS_RRRI\n\tS_RRRICI\n\n\tRIR\n\tRIRC\n\tRIRCI\n\n\tS_RIRC\n\tS_RIRCI\n\n\tR\n\tRCI\n\n\tS_R\n\tS_RCI\n\n\tCI\n\tI\n\n\tDDCI\n\n\tERRI\n\tEDRI\n\tS_ERRI\n\n\tERII\n\tERIR\n\tERID\n\n\tDMA_RRI\n\n\tNOP\n\n\tMOVE_RI\n\tMOVE_RICI\n\tMOVE_S_RI\n\tMOVE_S_RICI\n\n\tJEQ_RII\n\tJEQ_RRI\n\tJNZ_RI\n\tJUMP_I\n\tJUMP_R\n\n\tDIV_STEP_DRDI\n\tBOOT_RI\n\tSTOP\n\tCALL_RI\n\tCALL_RR\n\tBKP\n\tMOVD_DD\n\tTIME_CFG_R\n\tLBS_RRI\n\tLBS_S_RRI\n\tLD_DRI\n\tSB_RIR\n\tSB_ID_RII\n\tSB_ID_RI\n\tSD_RID\n\n\tLABEL\n)\n\ntype Stmt struct {\n\tstmt_type StmtType\n\n\taddrsig_stmt                   *directive.AddrsigStmt\n\taddrsig_sym_stmt               *directive.AddrsigSymStmt\n\tascii_stmt                     *directive.AsciiStmt\n\tasciz_stmt                     *directive.AscizStmt\n\tbyte_stmt                      *directive.ByteStmt\n\tcfi_def_cfa_offset_stmt        *directive.CfiDefCfaOffsetStmt\n\tcfi_endproc_stmt               *directive.CfiEndprocStmt\n\tcfi_offset_stmt                *directive.CfiOffsetStmt\n\tcfi_sections_stmt              *directive.CfiSectionsStmt\n\tcfi_startproc_stmt             *directive.CfiStartprocStmt\n\tfile_number_stmt               *directive.FileNumberStmt\n\tfile_string_stmt               *directive.FileStringStmt\n\tglobal_stmt                    *directive.GlobalStmt\n\tloc_is_stmt_stmt               *directive.LocIsStmtStmt\n\tloc_number_stmt                *directive.LocNumberStmt\n\tloc_prologue_end_stmt          *directive.LocPrologueEndStmt\n\tlong_program_counter_stmt      *directive.LongProgramCounterStmt\n\tlong_section_name_stmt         *directive.LongSectionNameStmt\n\tp2_align_stmt                  *directive.P2AlignStmt\n\tquad_stmt                      *directive.QuadStmt\n\tsection_identifier_number_stmt *directive.SectionIdentifierNumberStmt\n\tsection_identifier_stmt        *directive.SectionIdentifierStmt\n\tsection_stack_sizes_stmt       *directive.SectionStackSizesStmt\n\tsection_string_number_stmt     *directive.SectionStringNumberStmt\n\tsection_string_stmt            *directive.SectionStringStmt\n\tset_stmt                       *directive.SetStmt\n\tshort_stmt                     *directive.ShortStmt\n\tsize_stmt                      *directive.SizeStmt\n\ttext_stmt                      *directive.TextStmt\n\ttype_stmt                      *directive.TypeStmt\n\tweak_stmt                      *directive.WeakStmt\n\tzero_single_number_stmt        *directive.ZeroSingleNumberStmt\n\tzero_double_number_stmt        *directive.ZeroDoubleNumberStmt\n\n\tci_stmt      *instruction.CiStmt\n\tddci_stmt    *instruction.DdciStmt\n\tdma_rri_stmt *instruction.DmaRriStmt\n\tdrdici_stmt  *instruction.DrdiciStmt\n\tedri_stmt    *instruction.EdriStmt\n\terid_stmt    *instruction.EridStmt\n\terii_stmt    *instruction.EriiStmt\n\terir_stmt    *instruction.ErirStmt\n\terri_stmt    *instruction.ErriStmt\n\ti_stmt       *instruction.IStmt\n\tnop_stmt     *instruction.NopStmt\n\tr_stmt       *instruction.RStmt\n\trci_stmt     *instruction.RciStmt\n\trici_stmt    *instruction.RiciStmt\n\trir_stmt     *instruction.RirStmt\n\trirc_stmt    *instruction.RircStmt\n\trirci_stmt   *instruction.RirciStmt\n\trr_stmt      *instruction.RrStmt\n\trrc_stmt     *instruction.RrcStmt\n\trrci_stmt    *instruction.RrciStmt\n\trri_stmt     *instruction.RriStmt\n\trric_stmt    *instruction.RricStmt\n\trrici_stmt   *instruction.RriciStmt\n\trrr_stmt     *instruction.RrrStmt\n\trrrc_stmt    *instruction.RrrcStmt\n\trrrci_stmt   *instruction.RrrciStmt\n\trrri_stmt    *instruction.RrriStmt\n\trrrici_stmt  *instruction.RrriciStmt\n\n\ts_erri_stmt   *instruction.SErriStmt\n\ts_r_stmt      *instruction.SRStmt\n\ts_rci_stmt    *instruction.SRciStmt\n\ts_rirc_stmt   *instruction.SRircStmt\n\ts_rirci_stmt  *instruction.SRirciStmt\n\ts_rr_stmt     *instruction.SRrStmt\n\ts_rrc_stmt    *instruction.SRrcStmt\n\ts_rrci_stmt   *instruction.SRrciStmt\n\ts_rri_stmt    *instruction.SRriStmt\n\ts_rric_stmt   *instruction.SRricStmt\n\ts_rrici_stmt  *instruction.SRriciStmt\n\ts_rrr_stmt    *instruction.SRrrStmt\n\ts_rrrc_stmt   *instruction.SRrrcStmt\n\ts_rrrci_stmt  *instruction.SRrrciStmt\n\ts_rrri_stmt   *instruction.SRrriStmt\n\ts_rrrici_stmt *instruction.SRrriciStmt\n\n\tbkp_stmt           *sugar.BkpStmt\n\tboot_ri_stmt       *sugar.BootRiStmt\n\tcall_ri_stmt       *sugar.CallRiStmt\n\tcall_rr_stmt       *sugar.CallRrStmt\n\tdiv_step_drdi_stmt *sugar.DivStepDrdiStmt\n\tjeq_rii_stmt       *sugar.JeqRiiStmt\n\tjeq_rri_stmt       *sugar.JeqRriStmt\n\tjnz_ri_stmt        *sugar.JnzRiStmt\n\tjump_i_stmt        *sugar.JumpIStmt\n\tjump_r_stmt        *sugar.JumpRStmt\n\tlbs_rri_stmt       *sugar.LbsRriStmt\n\tlbs_s_rri_stmt     *sugar.LbsSRriStmt\n\tld_dri_stmt        *sugar.LdDriStmt\n\tmovd_dd_stmt       *sugar.MovdDdStmt\n\tmove_ri_stmt       *sugar.MoveRiStmt\n\tmove_rici_stmt     *sugar.MoveRiciStmt\n\tmove_s_ri_stmt     *sugar.MoveSRiStmt\n\tmove_s_rici_stmt   *sugar.MoveSRiciStmt\n\tsb_id_ri_stmt      *sugar.SbIdRiStmt\n\tsb_id_rii_stmt     *sugar.SbIdRiiStmt\n\tsb_rir_stmt        *sugar.SbRirStmt\n\tsd_rid_stmt        *sugar.SdRidStmt\n\tstop_stmt          *sugar.StopStmt\n\ttime_cfg_r_stmt    *sugar.TimeCfgRStmt\n\n\tlabel_stmt *LabelStmt\n}\n\nfunc (this *Stmt) InitAddrsigStmt() {\n\tthis.stmt_type = ADDRSIG\n\n\tthis.addrsig_stmt = new(directive.AddrsigStmt)\n\tthis.addrsig_stmt.Init()\n}\n\nfunc (this *Stmt) InitAddrsigSymStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = ADDRSIG_SYM\n\n\tthis.addrsig_sym_stmt = new(directive.AddrsigSymStmt)\n\tthis.addrsig_sym_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitAsciiStmt(token *lexer.Token) {\n\tthis.stmt_type = ASCII\n\n\tthis.ascii_stmt = new(directive.AsciiStmt)\n\tthis.ascii_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitAscizStmt(token *lexer.Token) {\n\tthis.stmt_type = ASCIZ\n\n\tthis.asciz_stmt = new(directive.AscizStmt)\n\tthis.asciz_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitByteStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = BYTE\n\n\tthis.byte_stmt = new(directive.ByteStmt)\n\tthis.byte_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiDefCfaOffsetStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = CFI_DEF_CFA_OFFSET\n\n\tthis.cfi_def_cfa_offset_stmt = new(directive.CfiDefCfaOffsetStmt)\n\tthis.cfi_def_cfa_offset_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiEndprocStmt() {\n\tthis.stmt_type = CFI_ENDPROC\n\n\tthis.cfi_endproc_stmt = new(directive.CfiEndprocStmt)\n\tthis.cfi_endproc_stmt.Init()\n}\n\nfunc (this *Stmt) InitCfiOffsetStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = CFI_OFFSET\n\n\tthis.cfi_offset_stmt = new(directive.CfiOffsetStmt)\n\tthis.cfi_offset_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitCfiSectionsStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = CFI_SECTIONS\n\n\tthis.cfi_sections_stmt = new(directive.CfiSectionsStmt)\n\tthis.cfi_sections_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiStartprocStmt() {\n\tthis.stmt_type = CFI_STARTPROC\n\n\tthis.cfi_startproc_stmt = new(directive.CfiStartprocStmt)\n\tthis.cfi_startproc_stmt.Init()\n}\n\nfunc (this *Stmt) InitFileNumberStmt(expr_ *expr.Expr, token1 *lexer.Token, token2 *lexer.Token) {\n\tthis.stmt_type = FILE_NUMBER\n\n\tthis.file_number_stmt = new(directive.FileNumberStmt)\n\tthis.file_number_stmt.Init(expr_, token1, token2)\n}\n\nfunc (this *Stmt) InitFileStringStmt(token *lexer.Token) {\n\tthis.stmt_type = FILE_STRING\n\n\tthis.file_string_stmt = new(directive.FileStringStmt)\n\tthis.file_string_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitGlobalStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = GLOBAL\n\n\tthis.global_stmt = new(directive.GlobalStmt)\n\tthis.global_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitLocIsStmtStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tthis.stmt_type = LOC_IS_STMT\n\n\tthis.loc_is_stmt_stmt = new(directive.LocIsStmtStmt)\n\tthis.loc_is_stmt_stmt.Init(expr1, expr2, expr3, expr4)\n}\n\nfunc (this *Stmt) InitLocNumberStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = LOC_NUMBER\n\n\tthis.loc_number_stmt = new(directive.LocNumberStmt)\n\tthis.loc_number_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitLocPrologueEndStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = LOC_PROLOGUE_END\n\n\tthis.loc_prologue_end_stmt = new(directive.LocPrologueEndStmt)\n\tthis.loc_prologue_end_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitLongProgramCounterStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LONG_PROGRAM_COUNTER\n\n\tthis.long_program_counter_stmt = new(directive.LongProgramCounterStmt)\n\tthis.long_program_counter_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitLongSectionNameStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LONG_SECTION_NAME\n\n\tthis.long_section_name_stmt = new(directive.LongSectionNameStmt)\n\tthis.long_section_name_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitP2AlignStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = P2_ALIGN\n\n\tthis.p2_align_stmt = new(directive.P2AlignStmt)\n\tthis.p2_align_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitQuadStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = QUAD\n\n\tthis.quad_stmt = new(directive.QuadStmt)\n\tthis.quad_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitSectionIdentifierNumberStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_IDENTIFIER_NUMBER\n\n\tthis.section_identifier_number_stmt = new(directive.SectionIdentifierNumberStmt)\n\tthis.section_identifier_number_stmt.Init(expr1, expr2, token, expr3, expr4)\n}\n\nfunc (this *Stmt) InitSectionIdentifierStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_IDENTIFIER\n\n\tthis.section_identifier_stmt = new(directive.SectionIdentifierStmt)\n\tthis.section_identifier_stmt.Init(expr1, expr2, token, expr3)\n}\n\nfunc (this *Stmt) InitSectionStackSizesStmt(\n\ttoken *lexer.Token,\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_STACK_SIZES\n\n\tthis.section_stack_sizes_stmt = new(directive.SectionStackSizesStmt)\n\tthis.section_stack_sizes_stmt.Init(token, expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitSectionStringNumberStmt(\n\texpr1 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_STRING_NUMBER\n\n\tthis.section_string_number_stmt = new(directive.SectionStringNumberStmt)\n\tthis.section_string_number_stmt.Init(expr1, token, expr2, expr3)\n}\n\nfunc (this *Stmt) InitSectionStringStmt(expr1 *expr.Expr, token *lexer.Token, expr2 *expr.Expr) {\n\tthis.stmt_type = SECTION_STRING\n\n\tthis.section_string_stmt = new(directive.SectionStringStmt)\n\tthis.section_string_stmt.Init(expr1, token, expr2)\n}\n\nfunc (this *Stmt) InitSetStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = SET\n\n\tthis.set_stmt = new(directive.SetStmt)\n\tthis.set_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitShortStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = SHORT\n\n\tthis.short_stmt = new(directive.ShortStmt)\n\tthis.short_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitSizeStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = SIZE\n\n\tthis.size_stmt = new(directive.SizeStmt)\n\tthis.size_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitTextStmt() {\n\tthis.stmt_type = TEXT\n\n\tthis.text_stmt = new(directive.TextStmt)\n\tthis.text_stmt.Init()\n}\n\nfunc (this *Stmt) InitTypeStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = TYPE\n\n\tthis.type_stmt = new(directive.TypeStmt)\n\tthis.type_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitWeakStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = WEAK\n\n\tthis.weak_stmt = new(directive.WeakStmt)\n\tthis.weak_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitZeroSingleNumberStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = ZERO_SINGLE_NUMBER\n\n\tthis.zero_single_number_stmt = new(directive.ZeroSingleNumberStmt)\n\tthis.zero_single_number_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitZeroDoubleNumberStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = ZERO_DOUBLE_NUMBER\n\n\tthis.zero_double_number_stmt = new(directive.ZeroDoubleNumberStmt)\n\tthis.zero_double_number_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitCiStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = CI\n\n\tthis.ci_stmt = new(instruction.CiStmt)\n\tthis.ci_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitDdciStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tdb *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = DDCI\n\n\tthis.ddci_stmt = new(instruction.DdciStmt)\n\tthis.ddci_stmt.Init(op_code, dc, db, condition, pc)\n}\n\nfunc (this *Stmt) InitDmaRriStmt(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = DMA_RRI\n\n\tthis.dma_rri_stmt = new(instruction.DmaRriStmt)\n\tthis.dma_rri_stmt.Init(op_code, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitDrdiciStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = DRDICI\n\n\tthis.drdici_stmt = new(instruction.DrdiciStmt)\n\tthis.drdici_stmt.Init(op_code, dc, ra, db, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitEdriStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = EDRI\n\n\tthis.edri_stmt = new(instruction.EdriStmt)\n\tthis.edri_stmt.Init(op_code, endian, dc, ra, off)\n}\n\nfunc (this *Stmt) InitEridStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tthis.stmt_type = ERID\n\n\tthis.erid_stmt = new(instruction.EridStmt)\n\tthis.erid_stmt.Init(op_code, endian, ra, off, db)\n}\n\nfunc (this *Stmt) InitEriiStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = ERII\n\n\tthis.erii_stmt = new(instruction.EriiStmt)\n\tthis.erii_stmt.Init(op_code, endian, ra, off, imm)\n}\n\nfunc (this *Stmt) InitErirStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\trb *expr.Expr,\n) {\n\tthis.stmt_type = ERIR\n\n\tthis.erir_stmt = new(instruction.ErirStmt)\n\tthis.erir_stmt.Init(op_code, endian, ra, off, rb)\n}\n\nfunc (this *Stmt) InitErriStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = ERRI\n\n\tthis.erri_stmt = new(instruction.ErriStmt)\n\tthis.erri_stmt.Init(op_code, endian, rc, ra, off)\n}\n\nfunc (this *Stmt) InitIStmt(op_code *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = I\n\n\tthis.i_stmt = new(instruction.IStmt)\n\tthis.i_stmt.Init(op_code, imm)\n}\n\nfunc (this *Stmt) InitNopStmt(op_code *expr.Expr) {\n\tthis.stmt_type = NOP\n\n\tthis.nop_stmt = new(instruction.NopStmt)\n\tthis.nop_stmt.Init(op_code)\n}\n\nfunc (this *Stmt) InitRStmt(op_code *expr.Expr, rc *expr.Expr) {\n\tthis.stmt_type = R\n\n\tthis.r_stmt = new(instruction.RStmt)\n\tthis.r_stmt.Init(op_code, rc)\n}\n\nfunc (this *Stmt) InitRciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RCI\n\n\tthis.rci_stmt = new(instruction.RciStmt)\n\tthis.rci_stmt.Init(op_code, rc, condition, pc)\n}\n\nfunc (this *Stmt) InitRiciStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RICI\n\n\tthis.rici_stmt = new(instruction.RiciStmt)\n\tthis.rici_stmt.Init(op_code, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitRirStmt(op_code *expr.Expr, rc *expr.Expr, imm *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = RIR\n\n\tthis.rir_stmt = new(instruction.RirStmt)\n\tthis.rir_stmt.Init(op_code, rc, imm, ra)\n}\n\nfunc (this *Stmt) InitRircStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RIRC\n\n\tthis.rirc_stmt = new(instruction.RircStmt)\n\tthis.rirc_stmt.Init(op_code, rc, imm, ra, condition)\n}\n\nfunc (this *Stmt) InitRirciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RIRCI\n\n\tthis.rirci_stmt = new(instruction.RirciStmt)\n\tthis.rirci_stmt.Init(op_code, rc, imm, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitRrStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = RR\n\n\tthis.rr_stmt = new(instruction.RrStmt)\n\tthis.rr_stmt.Init(op_code, rc, ra)\n}\n\nfunc (this *Stmt) InitRrcStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRC\n\n\tthis.rrc_stmt = new(instruction.RrcStmt)\n\tthis.rrc_stmt.Init(op_code, rc, ra, condition)\n}\n\nfunc (this *Stmt) InitRrciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRCI\n\n\tthis.rrci_stmt = new(instruction.RrciStmt)\n\tthis.rrci_stmt.Init(op_code, rc, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitRriStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = RRI\n\n\tthis.rri_stmt = new(instruction.RriStmt)\n\tthis.rri_stmt.Init(op_code, rc, ra, imm)\n}\n\nfunc (this *Stmt) InitRricStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRIC\n\n\tthis.rric_stmt = new(instruction.RricStmt)\n\tthis.rric_stmt.Init(op_code, rc, ra, imm, condition)\n}\n\nfunc (this *Stmt) InitRriciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRICI\n\n\tthis.rrici_stmt = new(instruction.RriciStmt)\n\tthis.rrici_stmt.Init(op_code, rc, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitRrrStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, rb *expr.Expr) {\n\tthis.stmt_type = RRR\n\n\tthis.rrr_stmt = new(instruction.RrrStmt)\n\tthis.rrr_stmt.Init(op_code, rc, ra, rb)\n}\n\nfunc (this *Stmt) InitRrrcStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRRC\n\n\tthis.rrrc_stmt = new(instruction.RrrcStmt)\n\tthis.rrrc_stmt.Init(op_code, rc, ra, rb, condition)\n}\n\nfunc (this *Stmt) InitRrrciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRRCI\n\n\tthis.rrrci_stmt = new(instruction.RrrciStmt)\n\tthis.rrrci_stmt.Init(op_code, rc, ra, rb, condition, pc)\n}\n\nfunc (this *Stmt) InitRrriStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = RRRI\n\n\tthis.rrri_stmt = new(instruction.RrriStmt)\n\tthis.rrri_stmt.Init(op_code, rc, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitRrriciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRRICI\n\n\tthis.rrrici_stmt = new(instruction.RrriciStmt)\n\tthis.rrrici_stmt.Init(op_code, rc, ra, rb, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSErriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = S_ERRI\n\n\tthis.s_erri_stmt = new(instruction.SErriStmt)\n\tthis.s_erri_stmt.Init(op_code, suffix, endian, dc, ra, off)\n}\n\nfunc (this *Stmt) InitSRStmt(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token) {\n\tthis.stmt_type = S_R\n\n\tthis.s_r_stmt = new(instruction.SRStmt)\n\tthis.s_r_stmt.Init(op_code, suffix, dc)\n}\n\nfunc (this *Stmt) InitSRciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RCI\n\n\tthis.s_rci_stmt = new(instruction.SRciStmt)\n\tthis.s_rci_stmt.Init(op_code, suffix, dc, condition, pc)\n}\n\nfunc (this *Stmt) InitSRircStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RIRC\n\n\tthis.s_rirc_stmt = new(instruction.SRircStmt)\n\tthis.s_rirc_stmt.Init(op_code, suffix, dc, imm, ra, condition)\n}\n\nfunc (this *Stmt) InitSRirciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RIRCI\n\n\tthis.s_rirci_stmt = new(instruction.SRirciStmt)\n\tthis.s_rirci_stmt.Init(op_code, suffix, dc, imm, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n) {\n\tthis.stmt_type = S_RR\n\n\tthis.s_rr_stmt = new(instruction.SRrStmt)\n\tthis.s_rr_stmt.Init(op_code, suffix, dc, ra)\n}\n\nfunc (this *Stmt) InitSRrcStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRC\n\n\tthis.s_rrc_stmt = new(instruction.SRrcStmt)\n\tthis.s_rrc_stmt.Init(op_code, suffix, dc, ra, condition)\n}\n\nfunc (this *Stmt) InitSRrciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRCI\n\n\tthis.s_rrci_stmt = new(instruction.SRrciStmt)\n\tthis.s_rrci_stmt.Init(op_code, suffix, dc, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitSRriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = S_RRI\n\n\tthis.s_rri_stmt = new(instruction.SRriStmt)\n\tthis.s_rri_stmt.Init(op_code, suffix, dc, ra, imm)\n}\n\nfunc (this *Stmt) InitSRricStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRIC\n\n\tthis.s_rric_stmt = new(instruction.SRricStmt)\n\tthis.s_rric_stmt.Init(op_code, suffix, dc, ra, imm, condition)\n}\n\nfunc (this *Stmt) InitSRriciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRICI\n\n\tthis.s_rrici_stmt = new(instruction.SRriciStmt)\n\tthis.s_rrici_stmt.Init(op_code, suffix, dc, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrrStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n) {\n\tthis.stmt_type = S_RRR\n\n\tthis.s_rrr_stmt = new(instruction.SRrrStmt)\n\tthis.s_rrr_stmt.Init(op_code, suffix, dc, ra, rb)\n}\n\nfunc (this *Stmt) InitSRrrcStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRC\n\n\tthis.s_rrrc_stmt = new(instruction.SRrrcStmt)\n\tthis.s_rrrc_stmt.Init(op_code, suffix, dc, ra, rb, condition)\n}\n\nfunc (this *Stmt) InitSRrrciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRCI\n\n\tthis.s_rrrci_stmt = new(instruction.SRrrciStmt)\n\tthis.s_rrrci_stmt.Init(op_code, suffix, dc, ra, rb, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRI\n\n\tthis.s_rrri_stmt = new(instruction.SRrriStmt)\n\tthis.s_rrri_stmt.Init(op_code, suffix, dc, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitSRrriciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRICI\n\n\tthis.s_rrrici_stmt = new(instruction.SRrriciStmt)\n\tthis.s_rrrici_stmt.Init(op_code, suffix, dc, ra, rb, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitBkpStmt() {\n\tthis.stmt_type = BKP\n\n\tthis.bkp_stmt = new(sugar.BkpStmt)\n\tthis.bkp_stmt.Init()\n}\n\nfunc (this *Stmt) InitBootRiStmt(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = BOOT_RI\n\n\tthis.boot_ri_stmt = new(sugar.BootRiStmt)\n\tthis.boot_ri_stmt.Init(op_code, ra, imm)\n}\n\nfunc (this *Stmt) InitCallRiStmt(rc *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = CALL_RI\n\n\tthis.call_ri_stmt = new(sugar.CallRiStmt)\n\tthis.call_ri_stmt.Init(rc, imm)\n}\n\nfunc (this *Stmt) InitCallRrStmt(rc *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = CALL_RR\n\n\tthis.call_rr_stmt = new(sugar.CallRrStmt)\n\tthis.call_rr_stmt.Init(rc, ra)\n}\n\nfunc (this *Stmt) InitDivStepDrdiStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = DIV_STEP_DRDI\n\n\tthis.div_step_drdi_stmt = new(sugar.DivStepDrdiStmt)\n\tthis.div_step_drdi_stmt.Init(op_code, dc, ra, db, imm)\n}\n\nfunc (this *Stmt) InitJeqRiiStmt(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JEQ_RII\n\n\tthis.jeq_rii_stmt = new(sugar.JeqRiiStmt)\n\tthis.jeq_rii_stmt.Init(op_code, ra, imm, pc)\n}\n\nfunc (this *Stmt) InitJeqRriStmt(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JEQ_RRI\n\n\tthis.jeq_rri_stmt = new(sugar.JeqRriStmt)\n\tthis.jeq_rri_stmt.Init(op_code, ra, rb, pc)\n}\n\nfunc (this *Stmt) InitJnzRiStmt(op_code *expr.Expr, ra *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JNZ_RI\n\n\tthis.jnz_ri_stmt = new(sugar.JnzRiStmt)\n\tthis.jnz_ri_stmt.Init(op_code, ra, pc)\n}\n\nfunc (this *Stmt) InitJumpIStmt(pc *expr.Expr) {\n\tthis.stmt_type = JUMP_I\n\n\tthis.jump_i_stmt = new(sugar.JumpIStmt)\n\tthis.jump_i_stmt.Init(pc)\n}\n\nfunc (this *Stmt) InitJumpRStmt(ra *expr.Expr) {\n\tthis.stmt_type = JUMP_R\n\n\tthis.jump_r_stmt = new(sugar.JumpRStmt)\n\tthis.jump_r_stmt.Init(ra)\n}\n\nfunc (this *Stmt) InitLbsRriStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tthis.stmt_type = LBS_RRI\n\n\tthis.lbs_rri_stmt = new(sugar.LbsRriStmt)\n\tthis.lbs_rri_stmt.Init(op_code, rc, ra, off)\n}\n\nfunc (this *Stmt) InitLbsSRriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = LBS_S_RRI\n\n\tthis.lbs_s_rri_stmt = new(sugar.LbsSRriStmt)\n\tthis.lbs_s_rri_stmt.Init(op_code, suffix, dc, ra, off)\n}\n\nfunc (this *Stmt) InitLdDriStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = LD_DRI\n\n\tthis.ld_dri_stmt = new(sugar.LdDriStmt)\n\tthis.ld_dri_stmt.Init(op_code, dc, ra, off)\n}\n\nfunc (this *Stmt) InitMovdDdStmt(op_code *expr.Expr, dc *lexer.Token, db *lexer.Token) {\n\tthis.stmt_type = MOVD_DD\n\n\tthis.movd_dd_stmt = new(sugar.MovdDdStmt)\n\tthis.movd_dd_stmt.Init(op_code, dc, db)\n}\n\nfunc (this *Stmt) InitMoveRiStmt(rc *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = MOVE_RI\n\n\tthis.move_ri_stmt = new(sugar.MoveRiStmt)\n\tthis.move_ri_stmt.Init(rc, imm)\n}\n\nfunc (this *Stmt) InitMoveRiciStmt(\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = MOVE_RICI\n\n\tthis.move_rici_stmt = new(sugar.MoveRiciStmt)\n\tthis.move_rici_stmt.Init(rc, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitMoveSRiStmt(suffix *expr.Expr, dc *lexer.Token, imm *expr.Expr) {\n\tthis.stmt_type = MOVE_S_RI\n\n\tthis.move_s_ri_stmt = new(sugar.MoveSRiStmt)\n\tthis.move_s_ri_stmt.Init(suffix, dc, imm)\n}\n\nfunc (this *Stmt) InitMoveSRiciStmt(\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = MOVE_S_RICI\n\n\tthis.move_s_rici_stmt = new(sugar.MoveSRiciStmt)\n\tthis.move_s_rici_stmt.Init(suffix, dc, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSbIdRiStmt(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tthis.stmt_type = SB_ID_RI\n\n\tthis.sb_id_ri_stmt = new(sugar.SbIdRiStmt)\n\tthis.sb_id_ri_stmt.Init(op_code, ra, off)\n}\n\nfunc (this *Stmt) InitSbIdRiiStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = SB_ID_RII\n\n\tthis.sb_id_rii_stmt = new(sugar.SbIdRiiStmt)\n\tthis.sb_id_rii_stmt.Init(op_code, ra, off, imm)\n}\n\nfunc (this *Stmt) InitSbRirStmt(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, rb *expr.Expr) {\n\tthis.stmt_type = SB_RIR\n\n\tthis.sb_rir_stmt = new(sugar.SbRirStmt)\n\tthis.sb_rir_stmt.Init(op_code, ra, off, rb)\n}\n\nfunc (this *Stmt) InitSdRidStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tthis.stmt_type = SD_RID\n\n\tthis.sd_rid_stmt = new(sugar.SdRidStmt)\n\tthis.sd_rid_stmt.Init(op_code, ra, off, db)\n}\n\nfunc (this *Stmt) InitStopStmt() {\n\tthis.stmt_type = STOP\n\n\tthis.stop_stmt = new(sugar.StopStmt)\n\tthis.stop_stmt.Init()\n}\n\nfunc (this *Stmt) InitTimeCfgRStmt(ra *expr.Expr) {\n\tthis.stmt_type = TIME_CFG_R\n\n\tthis.time_cfg_r_stmt = new(sugar.TimeCfgRStmt)\n\tthis.time_cfg_r_stmt.Init(ra)\n}\n\nfunc (this *Stmt) InitLabelStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LABEL\n\n\tthis.label_stmt = new(LabelStmt)\n\tthis.label_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) StmtType() StmtType {\n\treturn this.stmt_type\n}\n\nfunc (this *Stmt) AddrsigStmt() *directive.AddrsigStmt {\n\treturn this.addrsig_stmt\n}\n\nfunc (this *Stmt) AddrsigSymStmt() *directive.AddrsigSymStmt {\n\treturn this.addrsig_sym_stmt\n}\n\nfunc (this *Stmt) AsciiStmt() *directive.AsciiStmt {\n\treturn this.ascii_stmt\n}\n\nfunc (this *Stmt) AscizStmt() *directive.AscizStmt {\n\treturn this.asciz_stmt\n}\n\nfunc (this *Stmt) ByteStmt() *directive.ByteStmt {\n\treturn this.byte_stmt\n}\n\nfunc (this *Stmt) CfiDefCfaOffsetStmt() *directive.CfiDefCfaOffsetStmt {\n\treturn this.cfi_def_cfa_offset_stmt\n}\n\nfunc (this *Stmt) CfiEndprocStmt() *directive.CfiEndprocStmt {\n\treturn this.cfi_endproc_stmt\n}\n\nfunc (this *Stmt) CfiOffsetStmt() *directive.CfiOffsetStmt {\n\treturn this.cfi_offset_stmt\n}\n\nfunc (this *Stmt) CfiSectionsStmt() *directive.CfiSectionsStmt {\n\treturn this.cfi_sections_stmt\n}\n\nfunc (this *Stmt) CfiStartprocStmt() *directive.CfiStartprocStmt {\n\treturn this.cfi_startproc_stmt\n}\n\nfunc (this *Stmt) FileNumberStmt() *directive.FileNumberStmt {\n\treturn this.file_number_stmt\n}\n\nfunc (this *Stmt) FileStringStmt() *directive.FileStringStmt {\n\treturn this.file_string_stmt\n}\n\nfunc (this *Stmt) GlobalStmt() *directive.GlobalStmt {\n\treturn this.global_stmt\n}\n\nfunc (this *Stmt) LocIsStmtStmt() *directive.LocIsStmtStmt {\n\treturn this.loc_is_stmt_stmt\n}\n\nfunc (this *Stmt) LocNumberStmt() *directive.LocNumberStmt {\n\treturn this.loc_number_stmt\n}\n\nfunc (this *Stmt) LocPrologueEndStmt() *directive.LocPrologueEndStmt {\n\treturn this.loc_prologue_end_stmt\n}\n\nfunc (this *Stmt) LongProgramCounterStmt() *directive.LongProgramCounterStmt {\n\treturn this.long_program_counter_stmt\n}\n\nfunc (this *Stmt) LongSectionNameStmt() *directive.LongSectionNameStmt {\n\treturn this.long_section_name_stmt\n}\n\nfunc (this *Stmt) P2AlignStmt() *directive.P2AlignStmt {\n\treturn this.p2_align_stmt\n}\n\nfunc (this *Stmt) QuadStmt() *directive.QuadStmt {\n\treturn this.quad_stmt\n}\n\nfunc (this *Stmt) SectionIdentifierNumberStmt() *directive.SectionIdentifierNumberStmt {\n\treturn this.section_identifier_number_stmt\n}\n\nfunc (this *Stmt) SectionIdentifierStmt() *directive.SectionIdentifierStmt {\n\treturn this.section_identifier_stmt\n}\n\nfunc (this *Stmt) SectionStackSizesStmt() *directive.SectionStackSizesStmt {\n\treturn this.section_stack_sizes_stmt\n}\n\nfunc (this *Stmt) SectionStringNumberStmt() *directive.SectionStringNumberStmt {\n\treturn this.section_string_number_stmt\n}\n\nfunc (this *Stmt) SectionStringStmt() *directive.SectionStringStmt {\n\treturn this.section_string_stmt\n}\n\nfunc (this *Stmt) SetStmt() *directive.SetStmt {\n\treturn this.set_stmt\n}\n\nfunc (this *Stmt) ShortStmt() *directive.ShortStmt {\n\treturn this.short_stmt\n}\n\nfunc (this *Stmt) SizeStmt() *directive.SizeStmt {\n\treturn this.size_stmt\n}\n\nfunc (this *Stmt) TextStmt() *directive.TextStmt {\n\treturn this.text_stmt\n}\n\nfunc (this *Stmt) TypeStmt() *directive.TypeStmt {\n\treturn this.type_stmt\n}\n\nfunc (this *Stmt) WeakStmt() *directive.WeakStmt {\n\treturn this.weak_stmt\n}\n\nfunc (this *Stmt) ZeroSingleNumberStmt() *directive.ZeroSingleNumberStmt {\n\treturn this.zero_single_number_stmt\n}\n\nfunc (this *Stmt) ZeroDoubleNumberStmt() *directive.ZeroDoubleNumberStmt {\n\treturn this.zero_double_number_stmt\n}\n\nfunc (this *Stmt) CiStmt() *instruction.CiStmt {\n\treturn this.ci_stmt\n}\n\nfunc (this *Stmt) DdciStmt() *instruction.DdciStmt {\n\treturn this.ddci_stmt\n}\n\nfunc (this *Stmt) DmaRriStmt() *instruction.DmaRriStmt {\n\treturn this.dma_rri_stmt\n}\n\nfunc (this *Stmt) DrdiciStmt() *instruction.DrdiciStmt {\n\treturn this.drdici_stmt\n}\n\nfunc (this *Stmt) EdriStmt() *instruction.EdriStmt {\n\treturn this.edri_stmt\n}\n\nfunc (this *Stmt) EridStmt() *instruction.EridStmt {\n\treturn this.erid_stmt\n}\n\nfunc (this *Stmt) EriiStmt() *instruction.EriiStmt {\n\treturn this.erii_stmt\n}\n\nfunc (this *Stmt) ErirStmt() *instruction.ErirStmt {\n\treturn this.erir_stmt\n}\n\nfunc (this *Stmt) ErriStmt() *instruction.ErriStmt {\n\treturn this.erri_stmt\n}\n\nfunc (this *Stmt) IStmt() *instruction.IStmt {\n\treturn this.i_stmt\n}\n\nfunc (this *Stmt) NopStmt() *instruction.NopStmt {\n\treturn this.nop_stmt\n}\n\nfunc (this *Stmt) RStmt() *instruction.RStmt {\n\treturn this.r_stmt\n}\n\nfunc (this *Stmt) RciStmt() *instruction.RciStmt {\n\treturn this.rci_stmt\n}\n\nfunc (this *Stmt) RiciStmt() *instruction.RiciStmt {\n\treturn this.rici_stmt\n}\n\nfunc (this *Stmt) RirStmt() *instruction.RirStmt {\n\treturn this.rir_stmt\n}\n\nfunc (this *Stmt) RircStmt() *instruction.RircStmt {\n\treturn this.rirc_stmt\n}\n\nfunc (this *Stmt) RirciStmt() *instruction.RirciStmt {\n\treturn this.rirci_stmt\n}\n\nfunc (this *Stmt) RrStmt() *instruction.RrStmt {\n\treturn this.rr_stmt\n}\n\nfunc (this *Stmt) RrcStmt() *instruction.RrcStmt {\n\treturn this.rrc_stmt\n}\n\nfunc (this *Stmt) RrciStmt() *instruction.RrciStmt {\n\treturn this.rrci_stmt\n}\n\nfunc (this *Stmt) RriStmt() *instruction.RriStmt {\n\treturn this.rri_stmt\n}\n\nfunc (this *Stmt) RricStmt() *instruction.RricStmt {\n\treturn this.rric_stmt\n}\n\nfunc (this *Stmt) RriciStmt() *instruction.RriciStmt {\n\treturn this.rrici_stmt\n}\n\nfunc (this *Stmt) RrrStmt() *instruction.RrrStmt {\n\treturn this.rrr_stmt\n}\n\nfunc (this *Stmt) RrrcStmt() *instruction.RrrcStmt {\n\treturn this.rrrc_stmt\n}\n\nfunc (this *Stmt) RrrciStmt() *instruction.RrrciStmt {\n\treturn this.rrrci_stmt\n}\n\nfunc (this *Stmt) RrriStmt() *instruction.RrriStmt {\n\treturn this.rrri_stmt\n}\n\nfunc (this *Stmt) RrriciStmt() *instruction.RrriciStmt {\n\treturn this.rrrici_stmt\n}\n\nfunc (this *Stmt) SErriStmt() *instruction.SErriStmt {\n\treturn this.s_erri_stmt\n}\n\nfunc (this *Stmt) SRStmt() *instruction.SRStmt {\n\treturn this.s_r_stmt\n}\n\nfunc (this *Stmt) SRciStmt() *instruction.SRciStmt {\n\treturn this.s_rci_stmt\n}\n\nfunc (this *Stmt) SRircStmt() *instruction.SRircStmt {\n\treturn this.s_rirc_stmt\n}\n\nfunc (this *Stmt) SRirciStmt() *instruction.SRirciStmt {\n\treturn this.s_rirci_stmt\n}\n\nfunc (this *Stmt) SRrStmt() *instruction.SRrStmt {\n\treturn this.s_rr_stmt\n}\n\nfunc (this *Stmt) SRrcStmt() *instruction.SRrcStmt {\n\treturn this.s_rrc_stmt\n}\n\nfunc (this *Stmt) SRrciStmt() *instruction.SRrciStmt {\n\treturn this.s_rrci_stmt\n}\n\nfunc (this *Stmt) SRriStmt() *instruction.SRriStmt {\n\treturn this.s_rri_stmt\n}\n\nfunc (this *Stmt) SRricStmt() *instruction.SRricStmt {\n\treturn this.s_rric_stmt\n}\n\nfunc (this *Stmt) SRriciStmt() *instruction.SRriciStmt {\n\treturn this.s_rrici_stmt\n}\n\nfunc (this *Stmt) SRrrStmt() *instruction.SRrrStmt {\n\treturn this.s_rrr_stmt\n}\n\nfunc (this *Stmt) SRrrcStmt() *instruction.SRrrcStmt {\n\treturn this.s_rrrc_stmt\n}\n\nfunc (this *Stmt) SRrrciStmt() *instruction.SRrrciStmt {\n\treturn this.s_rrrci_stmt\n}\n\nfunc (this *Stmt) SRrriStmt() *instruction.SRrriStmt {\n\treturn this.s_rrri_stmt\n}\n\nfunc (this *Stmt) SRrriciStmt() *instruction.SRrriciStmt {\n\treturn this.s_rrrici_stmt\n}\n\nfunc (this *Stmt) BkpStmt() *sugar.BkpStmt {\n\treturn this.bkp_stmt\n}\n\nfunc (this *Stmt) BootRiStmt() *sugar.BootRiStmt {\n\treturn this.boot_ri_stmt\n}\n\nfunc (this *Stmt) CallRiStmt() *sugar.CallRiStmt {\n\treturn this.call_ri_stmt\n}\n\nfunc (this *Stmt) CallRrStmt() *sugar.CallRrStmt {\n\treturn this.call_rr_stmt\n}\n\nfunc (this *Stmt) DivStepDrdiStmt() *sugar.DivStepDrdiStmt {\n\treturn this.div_step_drdi_stmt\n}\n\nfunc (this *Stmt) JeqRiiStmt() *sugar.JeqRiiStmt {\n\treturn this.jeq_rii_stmt\n}\n\nfunc (this *Stmt) JeqRriStmt() *sugar.JeqRriStmt {\n\treturn this.jeq_rri_stmt\n}\n\nfunc (this *Stmt) JnzRiStmt() *sugar.JnzRiStmt {\n\treturn this.jnz_ri_stmt\n}\n\nfunc (this *Stmt) JumpIStmt() *sugar.JumpIStmt {\n\treturn this.jump_i_stmt\n}\n\nfunc (this *Stmt) JumpRStmt() *sugar.JumpRStmt {\n\treturn this.jump_r_stmt\n}\n\nfunc (this *Stmt) LbsRriStmt() *sugar.LbsRriStmt {\n\treturn this.lbs_rri_stmt\n}\n\nfunc (this *Stmt) LbsSRriStmt() *sugar.LbsSRriStmt {\n\treturn this.lbs_s_rri_stmt\n}\n\nfunc (this *Stmt) LdDriStmt() *sugar.LdDriStmt {\n\treturn this.ld_dri_stmt\n}\n\nfunc (this *Stmt) MovdDdStmt() *sugar.MovdDdStmt {\n\treturn this.movd_dd_stmt\n}\n\nfunc (this *Stmt) MoveRiStmt() *sugar.MoveRiStmt {\n\treturn this.move_ri_stmt\n}\n\nfunc (this *Stmt) MoveRiciStmt() *sugar.MoveRiciStmt {\n\treturn this.move_rici_stmt\n}\n\nfunc (this *Stmt) MoveSRiStmt() *sugar.MoveSRiStmt {\n\treturn this.move_s_ri_stmt\n}\n\nfunc (this *Stmt) MoveSRiciStmt() *sugar.MoveSRiciStmt {\n\treturn this.move_s_rici_stmt\n}\n\nfunc (this *Stmt) SbIdRiStmt() *sugar.SbIdRiStmt {\n\treturn this.sb_id_ri_stmt\n}\n\nfunc (this *Stmt) SbIdRiiStmt() *sugar.SbIdRiiStmt {\n\treturn this.sb_id_rii_stmt\n}\n\nfunc (this *Stmt) SbRirStmt() *sugar.SbRirStmt {\n\treturn this.sb_rir_stmt\n}\n\nfunc (this *Stmt) SdRidStmt() *sugar.SdRidStmt {\n\treturn this.sd_rid_stmt\n}\n\nfunc (this *Stmt) StopStmt() *sugar.StopStmt {\n\treturn this.stop_stmt\n}\n\nfunc (this *Stmt) TimeCfgRStmt() *sugar.TimeCfgRStmt {\n\treturn this.time_cfg_r_stmt\n}\n\nfunc (this *Stmt) LabelStmt() *LabelStmt {\n\treturn this.label_stmt\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/bkp_stmt.go",
    "content": "package sugar\n\ntype BkpStmt struct {\n}\n\nfunc (this *BkpStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/boot_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype BootRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *BootRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.RICI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *BootRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *BootRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *BootRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/call_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CallRiStmt struct {\n\trc  *expr.Expr\n\timm *expr.Expr\n}\n\nfunc (this *CallRiStmt) Init(rc *expr.Expr, imm *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n}\n\nfunc (this *CallRiStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *CallRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/call_rr_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype CallRrStmt struct {\n\trc *expr.Expr\n\tra *expr.Expr\n}\n\nfunc (this *CallRrStmt) Init(rc *expr.Expr, ra *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *CallRrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *CallRrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/div_step_drdi_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype DivStepDrdiStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\tdb      *lexer.Token\n\timm     *expr.Expr\n}\n\nfunc (this *DivStepDrdiStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DRDICI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\tthis.imm = imm\n}\n\nfunc (this *DivStepDrdiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DivStepDrdiStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DivStepDrdiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DivStepDrdiStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DivStepDrdiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/jeq_rii_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype JeqRiiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JeqRiiStmt) Init(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.pc = pc\n}\n\nfunc (this *JeqRiiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JeqRiiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JeqRiiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *JeqRiiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/jeq_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype JeqRriStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JeqRriStmt) Init(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.pc = pc\n}\n\nfunc (this *JeqRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JeqRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JeqRriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *JeqRriStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/jnz_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype JnzRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JnzRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.pc = pc\n}\n\nfunc (this *JnzRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JnzRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JnzRiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/jump_i_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype JumpIStmt struct {\n\tpc *expr.Expr\n}\n\nfunc (this *JumpIStmt) Init(pc *expr.Expr) {\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.pc = pc\n}\n\nfunc (this *JumpIStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/jump_r_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype JumpRStmt struct {\n\tra *expr.Expr\n}\n\nfunc (this *JumpRStmt) Init(ra *expr.Expr) {\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.ra = ra\n}\n\nfunc (this *JumpRStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/lbs_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LbsRriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LbsRriStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LbsRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LbsRriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *LbsRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LbsRriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/lbs_s_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LbsSRriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LbsSRriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LbsSRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LbsSRriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *LbsSRriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *LbsSRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LbsSRriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/ld_dri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype LdDriStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LdDriStmt) Init(op_code *expr.Expr, dc *lexer.Token, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LdDriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LdDriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *LdDriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LdDriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/movd_dd_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype MovdDdStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tdb      *lexer.Token\n}\n\nfunc (this *MovdDdStmt) Init(op_code *expr.Expr, dc *lexer.Token, db *lexer.Token) {\n\tif op_code.ExprType() != expr.DDCI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.db = db\n}\n\nfunc (this *MovdDdStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *MovdDdStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MovdDdStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/move_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype MoveRiStmt struct {\n\trc  *expr.Expr\n\timm *expr.Expr\n}\n\nfunc (this *MoveRiStmt) Init(rc *expr.Expr, imm *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n}\n\nfunc (this *MoveRiStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *MoveRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/move_rici_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype MoveRiciStmt struct {\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *MoveRiciStmt) Init(rc *expr.Expr, imm *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *MoveRiciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *MoveRiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *MoveRiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *MoveRiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/move_s_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype MoveSRiStmt struct {\n\tsuffix *expr.Expr\n\tdc     *lexer.Token\n\timm    *expr.Expr\n}\n\nfunc (this *MoveSRiStmt) Init(suffix *expr.Expr, dc *lexer.Token, imm *expr.Expr) {\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n}\n\nfunc (this *MoveSRiStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *MoveSRiStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MoveSRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/move_s_rici_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype MoveSRiciStmt struct {\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *MoveSRiciStmt) Init(\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *MoveSRiciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *MoveSRiciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MoveSRiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *MoveSRiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *MoveSRiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/sb_id_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SbIdRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *SbIdRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *SbIdRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbIdRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbIdRiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/sb_id_rii_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SbIdRiiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SbIdRiiStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.imm = imm\n}\n\nfunc (this *SbIdRiiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbIdRiiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbIdRiiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SbIdRiiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/sb_rir_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SbRirStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *SbRirStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, rb *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.rb = rb\n}\n\nfunc (this *SbRirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbRirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbRirStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SbRirStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/sd_rid_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype SdRidStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\tdb      *lexer.Token\n}\n\nfunc (this *SdRidStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, db *lexer.Token) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.db = db\n}\n\nfunc (this *SdRidStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SdRidStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SdRidStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SdRidStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/stop_stmt.go",
    "content": "package sugar\n\ntype StopStmt struct {\n}\n\nfunc (this *StopStmt) Init() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/stmt/sugar/time_cfg_r_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n)\n\ntype TimeCfgRStmt struct {\n\tra *expr.Expr\n}\n\nfunc (this *TimeCfgRStmt) Init(ra *expr.Expr) {\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.ra = ra\n}\n\nfunc (this *TimeCfgRStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/table.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/lexer\"\n)\n\ntype Table struct {\n\texpr_rules []*Rule\n\tstmt_rules []*Rule\n\n\tstack *Stack\n}\n\nfunc (this *Table) Init(stack *Stack) {\n\tthis.expr_rules = make([]*Rule, 0)\n\tthis.stmt_rules = make([]*Rule, 0)\n\n\tthis.stack = stack\n}\n\nfunc (this *Table) AddExprRule(rule *Rule) {\n\tthis.expr_rules = append(this.expr_rules, rule)\n}\n\nfunc (this *Table) AddStmtRule(rule *Rule) {\n\tthis.stmt_rules = append(this.stmt_rules, rule)\n}\n\nfunc (this *Table) FindReducibleExprRule(token *lexer.Token) (*Rule, []*StackItem) {\n\tfor num := this.stack.NonStmtSize(); num > 0; num-- {\n\t\tstack_items := this.stack.Front(num)\n\n\t\tfor _, expr_rule := range this.expr_rules {\n\t\t\tif expr_rule.IsReducible(stack_items, token) {\n\t\t\t\treturn expr_rule, stack_items\n\t\t\t}\n\t\t}\n\t}\n\treturn nil, []*StackItem{}\n}\n\nfunc (this *Table) FindReducibleStmtRule(token *lexer.Token) (*Rule, []*StackItem) {\n\tif token.TokenType() != lexer.NEW_LINE {\n\t\terr := errors.New(\"token is not a new line\")\n\t\tpanic(err)\n\t}\n\n\tnum := this.stack.NonStmtSize()\n\tstack_items := this.stack.Front(num)\n\n\tfor _, stmt_rule := range this.stmt_rules {\n\t\tif stmt_rule.IsReducible(stack_items, token) {\n\t\t\treturn stmt_rule, stack_items\n\t\t}\n\t}\n\treturn nil, []*StackItem{}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/linker/parser/walker.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/parser/expr\"\n\t\"uPIMulator/src/linker/parser/stmt\"\n)\n\ntype ExprCallback func(*expr.Expr)\ntype StmtCallback func(*stmt.Stmt)\n\ntype Walker struct {\n\texpr_callbacks map[expr.ExprType]ExprCallback\n\tstmt_callbacks map[stmt.StmtType]StmtCallback\n}\n\nfunc (this *Walker) Init() {\n\tthis.expr_callbacks = make(map[expr.ExprType]ExprCallback, 0)\n\tthis.stmt_callbacks = make(map[stmt.StmtType]StmtCallback, 0)\n}\n\nfunc (this *Walker) RegisterExprCallback(expr_type expr.ExprType, expr_callback ExprCallback) {\n\tif _, found := this.expr_callbacks[expr_type]; found {\n\t\terr := errors.New(\"expr callbak is already registered\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr_callbacks[expr_type] = expr_callback\n}\n\nfunc (this *Walker) RegisterStmtCallback(stmt_type stmt.StmtType, stmt_callback StmtCallback) {\n\tif _, found := this.stmt_callbacks[stmt_type]; found {\n\t\terr := errors.New(\"stmt callbak is already registered\")\n\t\tpanic(err)\n\t}\n\n\tthis.stmt_callbacks[stmt_type] = stmt_callback\n}\n\nfunc (this *Walker) Walk(ast *Ast) {\n\tfor i := 0; i < ast.Size(); i++ {\n\t\tstmt_ := ast.Get(i)\n\n\t\tstmt_type := stmt_.StmtType()\n\t\tif stmt_type == stmt.ASCII {\n\t\t\tthis.WalkAsciiStmt(stmt_)\n\t\t} else if stmt_type == stmt.ASCIZ {\n\t\t\tthis.WalkAscizStmt(stmt_)\n\t\t} else if stmt_type == stmt.BYTE {\n\t\t\tthis.WalkByteStmt(stmt_)\n\t\t} else if stmt_type == stmt.GLOBAL {\n\t\t\tthis.WalkGlobalStmt(stmt_)\n\t\t} else if stmt_type == stmt.LONG_PROGRAM_COUNTER {\n\t\t\tthis.WalkLongProgramCounterStmt(stmt_)\n\t\t} else if stmt_type == stmt.LONG_SECTION_NAME {\n\t\t\tthis.WalkLongSectionNameStmt(stmt_)\n\t\t} else if stmt_type == stmt.P2_ALIGN {\n\t\t\tthis.WalkP2AlignStmt(stmt_)\n\t\t} else if stmt_type == stmt.QUAD {\n\t\t\tthis.WalkQuadStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_IDENTIFIER_NUMBER {\n\t\t\tthis.WalkSectionIdentifierNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_IDENTIFIER {\n\t\t\tthis.WalkSectionIdentifierStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STACK_SIZES {\n\t\t\tthis.WalkSectionStackSizesStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STRING_NUMBER {\n\t\t\tthis.WalkSectionStringNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STRING {\n\t\t\tthis.WalkSectionStringStmt(stmt_)\n\t\t} else if stmt_type == stmt.SET {\n\t\t\tthis.WalkSetStmt(stmt_)\n\t\t} else if stmt_type == stmt.SHORT {\n\t\t\tthis.WalkShortStmt(stmt_)\n\t\t} else if stmt_type == stmt.SIZE {\n\t\t\tthis.WalkSizeStmt(stmt_)\n\t\t} else if stmt_type == stmt.TEXT {\n\t\t\tthis.WalkTextStmt(stmt_)\n\t\t} else if stmt_type == stmt.ZERO_DOUBLE_NUMBER {\n\t\t\tthis.WalkZeroDoubleNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.ZERO_SINGLE_NUMBER {\n\t\t\tthis.WalkZeroSingleNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.CI {\n\t\t\tthis.WalkCiStmt(stmt_)\n\t\t} else if stmt_type == stmt.DDCI {\n\t\t\tthis.WalkDdciStmt(stmt_)\n\t\t} else if stmt_type == stmt.DMA_RRI {\n\t\t\tthis.WalkDmaRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.DRDICI {\n\t\t\tthis.WalkDrdiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.EDRI {\n\t\t\tthis.WalkEdriStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERID {\n\t\t\tthis.WalkEridStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERII {\n\t\t\tthis.WalkEriiStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERIR {\n\t\t\tthis.WalkErirStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERRI {\n\t\t\tthis.WalkErriStmt(stmt_)\n\t\t} else if stmt_type == stmt.I {\n\t\t\tthis.WalkIStmt(stmt_)\n\t\t} else if stmt_type == stmt.NOP {\n\t\t\tthis.WalkNopStmt(stmt_)\n\t\t} else if stmt_type == stmt.RCI {\n\t\t\tthis.WalkRciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RICI {\n\t\t\tthis.WalkRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIRCI {\n\t\t\tthis.WalkRirciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIRC {\n\t\t\tthis.WalkRircStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIR {\n\t\t\tthis.WalkRirStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRCI {\n\t\t\tthis.WalkRrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRC {\n\t\t\tthis.WalkRrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRICI {\n\t\t\tthis.WalkRriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRIC {\n\t\t\tthis.WalkRricStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRI {\n\t\t\tthis.WalkRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRCI {\n\t\t\tthis.WalkRrrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRC {\n\t\t\tthis.WalkRrrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRICI {\n\t\t\tthis.WalkRrriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRI {\n\t\t\tthis.WalkRrriStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRR {\n\t\t\tthis.WalkRrrStmt(stmt_)\n\t\t} else if stmt_type == stmt.RR {\n\t\t\tthis.WalkRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.R {\n\t\t\tthis.WalkRStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_ERRI {\n\t\t\tthis.WalkSErriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RCI {\n\t\t\tthis.WalkSRciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RIRCI {\n\t\t\tthis.WalkSRirciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RIRC {\n\t\t\tthis.WalkSRircStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRCI {\n\t\t\tthis.WalkSRrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRC {\n\t\t\tthis.WalkSRrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRICI {\n\t\t\tthis.WalkSRriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRIC {\n\t\t\tthis.WalkSRricStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRI {\n\t\t\tthis.WalkSRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRCI {\n\t\t\tthis.WalkSRrrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRC {\n\t\t\tthis.WalkSRrrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRICI {\n\t\t\tthis.WalkSRrriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRI {\n\t\t\tthis.WalkSRrriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRR {\n\t\t\tthis.WalkSRrrStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RR {\n\t\t\tthis.WalkSRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_R {\n\t\t\tthis.WalkSRStmt(stmt_)\n\t\t} else if stmt_type == stmt.BKP {\n\t\t\tthis.WalkBkpStmt(stmt_)\n\t\t} else if stmt_type == stmt.BOOT_RI {\n\t\t\tthis.WalkBootRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.CALL_RI {\n\t\t\tthis.WalkCallRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.CALL_RR {\n\t\t\tthis.WalkCallRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.DIV_STEP_DRDI {\n\t\t\tthis.WalkDivStepDrdiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JEQ_RII {\n\t\t\tthis.WalkJeqRiiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JEQ_RRI {\n\t\t\tthis.WalkJeqRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.JNZ_RI {\n\t\t\tthis.WalkJnzRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JUMP_I {\n\t\t\tthis.WalkJumpIStmt(stmt_)\n\t\t} else if stmt_type == stmt.JUMP_R {\n\t\t\tthis.WalkJumpRStmt(stmt_)\n\t\t} else if stmt_type == stmt.LBS_RRI {\n\t\t\tthis.WalkLbsRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.LBS_S_RRI {\n\t\t\tthis.WalkLbsSRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.LD_DRI {\n\t\t\tthis.WalkLdDriStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVD_DD {\n\t\t\tthis.WalkMovdDdStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_RICI {\n\t\t\tthis.WalkMoveRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_RI {\n\t\t\tthis.WalkMoveRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_S_RICI {\n\t\t\tthis.WalkMoveSRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_S_RI {\n\t\t\tthis.WalkMoveSRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_ID_RII {\n\t\t\tthis.WalkSbIdRiiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_ID_RI {\n\t\t\tthis.WalkSbIdRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_RIR {\n\t\t\tthis.WalkSbRirStmt(stmt_)\n\t\t} else if stmt_type == stmt.SD_RID {\n\t\t\tthis.WalkSdRidStmt(stmt_)\n\t\t} else if stmt_type == stmt.STOP {\n\t\t\tthis.WalkStopStmt(stmt_)\n\t\t} else if stmt_type == stmt.TIME_CFG_R {\n\t\t\tthis.WalkTimeCfgRStmt(stmt_)\n\t\t} else if stmt_type == stmt.LABEL {\n\t\t\tthis.WalkLabelStmt(stmt_)\n\t\t} else {\n\t\t\tcontinue\n\t\t}\n\t}\n}\n\nfunc (this *Walker) WalkBinaryAddExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.BINARY_ADD {\n\t\terr := errors.New(\"expr type is not binary add expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.BINARY_ADD]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tbinary_add_expr := expr_.BinaryAddExpr()\n\n\toperand1 := binary_add_expr.Operand1()\n\toperand2 := binary_add_expr.Operand2()\n\n\tthis.WalkPrimaryExpr(operand1)\n\tthis.WalkPrimaryExpr(operand2)\n}\n\nfunc (this *Walker) WalkBinarySubExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.BINARY_SUB {\n\t\terr := errors.New(\"expr type is not binary sub expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.BINARY_SUB]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tbinary_sub_expr := expr_.BinarySubExpr()\n\n\toperand1 := binary_sub_expr.Operand1()\n\toperand2 := binary_sub_expr.Operand2()\n\n\tthis.WalkPrimaryExpr(operand1)\n\tthis.WalkPrimaryExpr(operand2)\n}\n\nfunc (this *Walker) WalkNegativeNumberExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.NEGATIVE_NUMBER {\n\t\terr := errors.New(\"expr type is not negative number expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.NEGATIVE_NUMBER]; found {\n\t\texpr_callback(expr_)\n\t}\n}\n\nfunc (this *Walker) WalkPrimaryExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"expr type is not primary\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.PRIMARY]; found {\n\t\texpr_callback(expr_)\n\t}\n}\n\nfunc (this *Walker) WalkProgramCounterExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr type is not program counter expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.PROGRAM_COUNTER]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\n\tchild_expr := program_counter_expr.Expr()\n\tchild_expr_type := child_expr.ExprType()\n\n\tif child_expr_type == expr.PRIMARY {\n\t\tthis.WalkPrimaryExpr(child_expr)\n\t} else if child_expr_type == expr.NEGATIVE_NUMBER {\n\t\tthis.WalkNegativeNumberExpr(child_expr)\n\t} else if child_expr_type == expr.BINARY_ADD {\n\t\tthis.WalkBinaryAddExpr(child_expr)\n\t} else if child_expr_type == expr.BINARY_SUB {\n\t\tthis.WalkBinarySubExpr(child_expr)\n\t} else {\n\t\terr := errors.New(\"child expr is not valid for a program counter expr\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Walker) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ASCII {\n\t\terr := errors.New(\"stmt type is not an ASCII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ASCII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ASCIZ {\n\t\terr := errors.New(\"stmt type is not an ASCIZ stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ASCIZ]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BYTE {\n\t\terr := errors.New(\"stmt type is not a byte stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BYTE]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tbyte_stmt := stmt_.ByteStmt()\n\n\texpr_ := byte_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkGlobalStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.GLOBAL {\n\t\terr := errors.New(\"stmt type is not a global stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.GLOBAL]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tglobal_stmt := stmt_.GlobalStmt()\n\n\texpr_ := global_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LONG_PROGRAM_COUNTER {\n\t\terr := errors.New(\"stmt type is not a long program counter stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LONG_PROGRAM_COUNTER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlong_program_counter_stmt := stmt_.LongProgramCounterStmt()\n\n\texpr_ := long_program_counter_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LONG_SECTION_NAME {\n\t\terr := errors.New(\"stmt type is not a long section name stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LONG_SECTION_NAME]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkP2AlignStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.P2_ALIGN {\n\t\terr := errors.New(\"stmt type is not a p2align stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.P2_ALIGN]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.QUAD {\n\t\terr := errors.New(\"stmt type is not a quad stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.QUAD]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tquad_stmt := stmt_.QuadStmt()\n\n\texpr_ := quad_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_IDENTIFIER_NUMBER {\n\t\terr := errors.New(\"stmt type is not a section identifier number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_IDENTIFIER_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_IDENTIFIER {\n\t\terr := errors.New(\"stmt type is not a section identifier stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_IDENTIFIER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionStackSizesStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STACK_SIZES {\n\t\terr := errors.New(\"stmt type is not a section stack sizes stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STACK_SIZES]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\nfunc (this *Walker) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STRING_NUMBER {\n\t\terr := errors.New(\"stmt type is not a section string number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STRING_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STRING {\n\t\terr := errors.New(\"stmt type is not a section string stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STRING]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SET {\n\t\terr := errors.New(\"stmt type is not a set stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SET]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tset_stmt := stmt_.SetStmt()\n\n\texpr1 := set_stmt.Expr1()\n\texpr2 := set_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SHORT {\n\t\terr := errors.New(\"stmt type is not a short stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SHORT]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tshort_stmt := stmt_.ShortStmt()\n\n\texpr_ := short_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkSizeStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SIZE {\n\t\terr := errors.New(\"stmt type is not a size stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SIZE]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsize_stmt := stmt_.SizeStmt()\n\n\texpr1 := size_stmt.Expr1()\n\texpr2 := size_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.TEXT {\n\t\terr := errors.New(\"stmt type is not a text stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.TEXT]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ZERO_DOUBLE_NUMBER {\n\t\terr := errors.New(\"stmt type is not a zero double number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ZERO_DOUBLE_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\texpr1 := zero_double_number_stmt.Expr1()\n\texpr2 := zero_double_number_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ZERO_SINGLE_NUMBER {\n\t\terr := errors.New(\"stmt type is not a zero single number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ZERO_SINGLE_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\texpr_ := zero_single_number_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkCiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CI {\n\t\terr := errors.New(\"stmt type is not a CI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tci_stmt := stmt_.CiStmt()\n\n\tpc := ci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkDdciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DDCI {\n\t\terr := errors.New(\"stmt type is not a DDCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DDCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tddci_stmt := stmt_.DdciStmt()\n\n\tpc := ddci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkDmaRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DMA_RRI {\n\t\terr := errors.New(\"stmt type is not a DMA_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DMA_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdma_rri_stmt := stmt_.DmaRriStmt()\n\n\timm := dma_rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkDrdiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DRDICI {\n\t\terr := errors.New(\"stmt type is not a DRDICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DRDICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdrdici_stmt := stmt_.DrdiciStmt()\n\n\timm := drdici_stmt.Imm()\n\tpc := drdici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkEdriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.EDRI {\n\t\terr := errors.New(\"stmt type is not an EDRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.EDRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tedri_stmt := stmt_.EdriStmt()\n\n\toff := edri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkEridStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERID {\n\t\terr := errors.New(\"stmt type is not an ERID stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERID]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terid_stmt := stmt_.EridStmt()\n\n\toff := erid_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkEriiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERII {\n\t\terr := errors.New(\"stmt type is not an ERII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terii_stmt := stmt_.EriiStmt()\n\n\toff := erii_stmt.Off()\n\timm := erii_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(off)\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkErirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERIR {\n\t\terr := errors.New(\"stmt type is not an ERIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terir_stmt := stmt_.ErirStmt()\n\n\toff := erir_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkErriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERRI {\n\t\terr := errors.New(\"stmt type is not an ERRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terri_stmt := stmt_.ErriStmt()\n\n\toff := erri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkIStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.I {\n\t\terr := errors.New(\"stmt type is not an I stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.I]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ti_stmt := stmt_.IStmt()\n\n\timm := i_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkNopStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.NOP {\n\t\terr := errors.New(\"stmt type is not a NOP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.NOP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RCI {\n\t\terr := errors.New(\"stmt type is not an RCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trci_stmt := stmt_.RciStmt()\n\n\tpc := rci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RICI {\n\t\terr := errors.New(\"stmt type is not an RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trici_stmt := stmt_.RiciStmt()\n\n\timm := rici_stmt.Imm()\n\tpc := rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRirciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIRCI {\n\t\terr := errors.New(\"stmt type is not an RIRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trirci_stmt := stmt_.RirciStmt()\n\n\timm := rirci_stmt.Imm()\n\tpc := rirci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRircStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIRC {\n\t\terr := errors.New(\"stmt type is not an RIRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trirc_stmt := stmt_.RircStmt()\n\n\timm := rirc_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIR {\n\t\terr := errors.New(\"stmt type is not an RIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trir_stmt := stmt_.RirStmt()\n\n\timm := rir_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRCI {\n\t\terr := errors.New(\"stmt type is not an RRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrci_stmt := stmt_.RrciStmt()\n\n\tpc := rrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRC {\n\t\terr := errors.New(\"stmt type is not an RRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRICI {\n\t\terr := errors.New(\"stmt type is not an RRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrici_stmt := stmt_.RriciStmt()\n\n\timm := rrici_stmt.Imm()\n\tpc := rrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRricStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRIC {\n\t\terr := errors.New(\"stmt type is not an RRIC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRIC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trric_stmt := stmt_.RricStmt()\n\n\timm := rric_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRI {\n\t\terr := errors.New(\"stmt type is not an RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trri_stmt := stmt_.RriStmt()\n\n\timm := rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRCI {\n\t\terr := errors.New(\"stmt type is not an RRRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrrci_stmt := stmt_.RrrciStmt()\n\n\tpc := rrrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRC {\n\t\terr := errors.New(\"stmt type is not an RRRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRrriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRICI {\n\t\terr := errors.New(\"stmt type is not an RRRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrrici_stmt := stmt_.RrriciStmt()\n\n\timm := rrrici_stmt.Imm()\n\tpc := rrrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRI {\n\t\terr := errors.New(\"stmt type is not an RRRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrri_stmt := stmt_.RrriStmt()\n\n\timm := rrri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRR {\n\t\terr := errors.New(\"stmt type is not an RRR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RR {\n\t\terr := errors.New(\"stmt type is not an RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.R {\n\t\terr := errors.New(\"stmt type is not an R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSErriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_ERRI {\n\t\terr := errors.New(\"stmt type is not a S_ERRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_ERRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_erri_stmt := stmt_.SErriStmt()\n\n\toff := s_erri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSRciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RCI {\n\t\terr := errors.New(\"stmt type is not a S_RCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rci_stmt := stmt_.SRciStmt()\n\n\tpc := s_rci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRirciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RIRCI {\n\t\terr := errors.New(\"stmt type is not a S_RIRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RIRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rirci_stmt := stmt_.SRirciStmt()\n\n\timm := s_rirci_stmt.Imm()\n\tpc := s_rirci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRircStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RIRC {\n\t\terr := errors.New(\"stmt type is not a S_RIRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RIRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rirc_stmt := stmt_.SRircStmt()\n\n\timm := s_rirc_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRCI {\n\t\terr := errors.New(\"stmt type is not a S_RRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrci_stmt := stmt_.SRrciStmt()\n\n\tpc := s_rrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRC {\n\t\terr := errors.New(\"stmt type is not a S_RRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRICI {\n\t\terr := errors.New(\"stmt type is not a S_RRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrici_stmt := stmt_.SRriciStmt()\n\n\timm := s_rrici_stmt.Imm()\n\tpc := s_rrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRricStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRIC {\n\t\terr := errors.New(\"stmt type is not a S_RRIC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRIC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rric_stmt := stmt_.SRricStmt()\n\n\timm := s_rric_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRI {\n\t\terr := errors.New(\"stmt type is not a S_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rri_stmt := stmt_.SRriStmt()\n\n\timm := s_rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRCI {\n\t\terr := errors.New(\"stmt type is not an S_RRRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrrci_stmt := stmt_.SRrrciStmt()\n\n\tpc := s_rrrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRC {\n\t\terr := errors.New(\"stmt type is not an S_RRRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRrriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRICI {\n\t\terr := errors.New(\"stmt type is not a S_RRRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrrici_stmt := stmt_.SRrriciStmt()\n\n\timm := s_rrrici_stmt.Imm()\n\tpc := s_rrrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRI {\n\t\terr := errors.New(\"stmt type is not a S_RRRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrri_stmt := stmt_.SRrriStmt()\n\n\timm := s_rrri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRR {\n\t\terr := errors.New(\"stmt type is not a RRR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RR {\n\t\terr := errors.New(\"stmt type is not a S_RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_R {\n\t\terr := errors.New(\"stmt type is not a S_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkBkpStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BKP {\n\t\terr := errors.New(\"stmt type is not a BKP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BKP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkBootRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BOOT_RI {\n\t\terr := errors.New(\"stmt type is not a BOOT_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BOOT_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tboot_ri_stmt := stmt_.BootRiStmt()\n\n\timm := boot_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkCallRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CALL_RI {\n\t\terr := errors.New(\"stmt type is not a CALL_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CALL_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tcall_ri_stmt := stmt_.CallRiStmt()\n\n\timm := call_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkCallRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CALL_RR {\n\t\terr := errors.New(\"stmt type is not a CALL_RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CALL_RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkDivStepDrdiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DIV_STEP_DRDI {\n\t\terr := errors.New(\"stmt type is not a DIV_STEP_DRDI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DIV_STEP_DRDI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdiv_step_drdi_stmt := stmt_.DivStepDrdiStmt()\n\n\timm := div_step_drdi_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkJeqRiiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JEQ_RII {\n\t\terr := errors.New(\"stmt type is not a JEQ_RII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JEQ_RII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjeq_rii_stmt := stmt_.JeqRiiStmt()\n\n\timm := jeq_rii_stmt.Imm()\n\tpc := jeq_rii_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJeqRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JEQ_RRI {\n\t\terr := errors.New(\"stmt type is not a JEQ_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JEQ_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjeq_rri_stmt := stmt_.JeqRriStmt()\n\n\tpc := jeq_rri_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJnzRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JNZ_RI {\n\t\terr := errors.New(\"stmt type is not a JNZ_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JNZ_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjnz_ri_stmt := stmt_.JnzRiStmt()\n\n\tpc := jnz_ri_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJumpIStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JUMP_I {\n\t\terr := errors.New(\"stmt type is not a JUMP_I stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JUMP_I]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjump_i_stmt := stmt_.JumpIStmt()\n\n\tpc := jump_i_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJumpRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JUMP_R {\n\t\terr := errors.New(\"stmt type is not a JUMP_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JUMP_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkLbsRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LBS_RRI {\n\t\terr := errors.New(\"stmt type is not a LBS_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LBS_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlbs_rri_stmt := stmt_.LbsRriStmt()\n\n\toff := lbs_rri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkLbsSRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LBS_S_RRI {\n\t\terr := errors.New(\"stmt type is not a LBS_S_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LBS_S_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlbs_s_rri_stmt := stmt_.LbsSRriStmt()\n\n\toff := lbs_s_rri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkLdDriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LD_DRI {\n\t\terr := errors.New(\"stmt type is not a LD_DRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LD_DRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tld_dri_stmt := stmt_.LdDriStmt()\n\n\toff := ld_dri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkMovdDdStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVD_DD {\n\t\terr := errors.New(\"stmt type is not a MOVD_DD stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVD_DD]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkMoveRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_RICI {\n\t\terr := errors.New(\"stmt type is not a MOVE_RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_rici_stmt := stmt_.MoveRiciStmt()\n\n\timm := move_rici_stmt.Imm()\n\tpc := move_rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkMoveRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_RI {\n\t\terr := errors.New(\"stmt type is not a MOVE_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_ri_stmt := stmt_.MoveRiStmt()\n\n\timm := move_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkMoveSRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_S_RICI {\n\t\terr := errors.New(\"stmt type is not a MOVE_S_RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_S_RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_s_rici_stmt := stmt_.MoveSRiciStmt()\n\n\timm := move_s_rici_stmt.Imm()\n\tpc := move_s_rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkMoveSRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_S_RI {\n\t\terr := errors.New(\"stmt type is not a MOVE_S_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_S_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_s_ri_stmt := stmt_.MoveSRiStmt()\n\n\timm := move_s_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSbIdRiiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_ID_RII {\n\t\terr := errors.New(\"stmt type is not a SB_ID_RII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_ID_RII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_id_rii_stmt := stmt_.SbIdRiiStmt()\n\n\toff := sb_id_rii_stmt.Off()\n\timm := sb_id_rii_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(off)\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSbIdRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_ID_RI {\n\t\terr := errors.New(\"stmt type is not a SB_ID_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_ID_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_id_ri_stmt := stmt_.SbIdRiStmt()\n\n\toff := sb_id_ri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSbRirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_RIR {\n\t\terr := errors.New(\"stmt type is not a SB_RIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_RIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_rir_stmt := stmt_.SbRirStmt()\n\n\toff := sb_rir_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSdRidStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SD_RID {\n\t\terr := errors.New(\"stmt type is not a SD_RID stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SD_RID]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsd_rid_stmt := stmt_.SdRidStmt()\n\n\toff := sd_rid_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkStopStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.STOP {\n\t\terr := errors.New(\"stmt type is not a STOP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.STOP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkTimeCfgRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.TIME_CFG_R {\n\t\terr := errors.New(\"stmt type is not a TIME_CFG_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.TIME_CFG_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LABEL {\n\t\terr := errors.New(\"stmt type is not a LABEL stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LABEL]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlabel_stmt := stmt_.LabelStmt()\n\n\texpr_ := label_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/main.go",
    "content": "package main\n\nimport (\n\t\"fmt\"\n\t\"os\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/assembler\"\n\t\"uPIMulator/src/compiler\"\n\t\"uPIMulator/src/linker\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator\"\n)\n\nfunc main() {\n\tcommand_line_parser := InitCommandLineParser()\n\tcommand_line_parser.Parse(os.Args)\n\n\tif command_line_parser.IsArgSet(\"help\") {\n\t\tfmt.Printf(\"%s\", command_line_parser.StringifyHelpMsgs())\n\t} else {\n\t\tcommand_line_validator := new(misc.CommandLineValidator)\n\t\tcommand_line_validator.Init(command_line_parser)\n\t\tcommand_line_validator.Validate()\n\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tconfig_validator := new(misc.ConfigValidator)\n\t\tconfig_validator.Init(config_loader)\n\t\tconfig_validator.Validate()\n\n\t\tbin_dirpath := command_line_parser.StringParameter(\"bin_dirpath\")\n\t\targs_filepath := filepath.Join(bin_dirpath, \"args.txt\")\n\t\toptions_filepath := filepath.Join(bin_dirpath, \"options.txt\")\n\n\t\targs_file_dumper := new(misc.FileDumper)\n\t\targs_file_dumper.Init(args_filepath)\n\t\targs_file_dumper.WriteLines([]string{command_line_parser.StringifyArgs()})\n\n\t\toptions_file_dumper := new(misc.FileDumper)\n\t\toptions_file_dumper.Init(options_filepath)\n\t\toptions_file_dumper.WriteLines([]string{command_line_parser.StringifyOptions()})\n\n\t\tcompiler_ := new(compiler.Compiler)\n\t\tcompiler_.Init(command_line_parser)\n\t\tcompiler_.Compile()\n\n\t\tlinker_ := new(linker.Linker)\n\t\tlinker_.Init(command_line_parser)\n\t\tlinker_.Link()\n\n\t\tassembler_ := new(assembler.Assembler)\n\t\tassembler_.Init(command_line_parser)\n\t\tassembler_.Assemble()\n\n\t\tsimulator_ := new(simulator.Simulator)\n\t\tsimulator_.Init(command_line_parser)\n\n\t\tfor !simulator_.IsFinished() {\n\t\t\tsimulator_.Cycle()\n\t\t}\n\n\t\tsimulator_.Dump()\n\t\tsimulator_.Fini()\n\t}\n}\n\nfunc InitCommandLineParser() *misc.CommandLineParser {\n\tcommand_line_parser := new(misc.CommandLineParser)\n\tcommand_line_parser.Init()\n\n\t// NOTE(dongjae.lee@kaist.ac.kr): Explanation of verbose level\n\t// level 0: Only prints simulation output\n\t// level 1: level 0 + prints UPMEM instruction executed per each logic cycle\n\t// level 2: level + prints UPMEM register file values per each logic cycle\n\tcommand_line_parser.AddOption(misc.INT, \"verbose\", \"0\", \"verbosity of the simulation\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_simulation_threads\", \"16\",\n\t\t\"number of simulation threads to launch\")\n\n\tcommand_line_parser.AddOption(misc.STRING, \"benchmark\", \"BS\", \"benchmark name\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_channels\", \"1\", \"number of PIM memory channels\")\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"num_ranks_per_channel\",\n\t\t\"1\",\n\t\t\"number of ranks per channel\",\n\t)\n\tcommand_line_parser.AddOption(misc.INT, \"num_dpus_per_rank\", \"1\", \"number of DPUs per rank\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_tasklets\", \"1\", \"number of tasklets\")\n\tcommand_line_parser.AddOption(misc.STRING, \"data_prep_params\", \"8192\",\n\t\t\"data preparation parameter\")\n\n\tcommand_line_parser.AddOption(\n\t\tmisc.STRING,\n\t\t\"root_dirpath\",\n\t\t\"/home/via/uPIMulator/golang/uPIMulator\",\n\t\t\"path to the root directory\",\n\t)\n\n\tcommand_line_parser.AddOption(misc.STRING, \"bin_dirpath\",\n\t\t\"/home/via/uPIMulator/golang/uPIMulator/bin\", \"path to the bin directory\")\n\n\tcommand_line_parser.AddOption(misc.STRING, \"log_dirpath\",\n\t\t\"/home/via/uPIMulator/golang/log\", \"path to the log directory\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"logic_frequency\", \"350\", \"DPU logic frequency in MHz\")\n\tcommand_line_parser.AddOption(misc.INT, \"memory_frequency\", \"2400\",\n\t\t\"DPU MRAM frequency in MHz\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_pipeline_stages\", \"14\",\n\t\t\"number of DPU logic pipeline stages\")\n\tcommand_line_parser.AddOption(misc.INT, \"num_revolver_scheduling_cycles\", \"11\",\n\t\t\"number of DPU logic revolver scheduling cycles\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"wordline_size\", \"1024\",\n\t\t\"row buffer size per single DPU's MRAM in bytes\")\n\tcommand_line_parser.AddOption(misc.INT, \"min_access_granularity\", \"8\",\n\t\t\"DPU MRAM's minimum access granularity in bytes\")\n\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"t_rcd\",\n\t\t\"32\",\n\t\t\"DPU MRAM t_rcd timing parameter [cycle]\",\n\t)\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"t_ras\",\n\t\t\"78\",\n\t\t\"DPU MRAM t_ras timing parameter [cycle]\",\n\t)\n\tcommand_line_parser.AddOption(misc.INT, \"t_rp\", \"32\", \"DPU MRAM t_rp timing parameter [cycle]\")\n\tcommand_line_parser.AddOption(misc.INT, \"t_cl\", \"32\", \"DPU MRAM t_cl timing parameter [cycle]\")\n\tcommand_line_parser.AddOption(misc.INT, \"t_bl\", \"8\", \"DPU MRAM t_bl timing parameter [cycle]\")\n\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"read_bandwidth\",\n\t\t\"1\",\n\t\t\"read bandwidth per DPU per rank [bytes/cycle]\",\n\t)\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"write_bandwidth\",\n\t\t\"3\",\n\t\t\"write bandwidth per DPU per rank [bytes/cycle]\",\n\t)\n\n\treturn command_line_parser\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/command_line_option.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"strconv\"\n)\n\ntype CommandLineOptionType int\n\nconst (\n\tBOOL = iota\n\tINT\n\tSTRING\n)\n\ntype CommandLineOption struct {\n\tcommand_line_option_type CommandLineOptionType\n\toption                   string\n\tdefault_parameter        string\n\tcustom_parameter         string\n\thelp_msg                 string\n}\n\nfunc (this *CommandLineOption) Init(\n\tcommand_line_option_type CommandLineOptionType,\n\toption string,\n\tdefault_parameter string,\n\thelp_msg string,\n) {\n\tthis.command_line_option_type = command_line_option_type\n\tthis.option = option\n\tthis.default_parameter = default_parameter\n\tthis.custom_parameter = \"\"\n\tthis.help_msg = help_msg\n}\n\nfunc (this *CommandLineOption) CommandLineOptionType() CommandLineOptionType {\n\treturn this.command_line_option_type\n}\n\nfunc (this *CommandLineOption) Option() string {\n\treturn this.option\n}\n\nfunc (this *CommandLineOption) Parameter() string {\n\tif this.custom_parameter == \"\" {\n\t\treturn this.default_parameter\n\t} else {\n\t\treturn this.custom_parameter\n\t}\n}\n\nfunc (this *CommandLineOption) HelpMsg() string {\n\treturn this.help_msg\n}\n\nfunc (this *CommandLineOption) SetCustomParameter(custom_parameter string) {\n\tif this.custom_parameter != \"\" {\n\t\terr := errors.New(\"custom parameter is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.custom_parameter = custom_parameter\n}\n\nfunc (this *CommandLineOption) BoolParameter() bool {\n\tif this.Parameter() == \"true\" {\n\t\treturn true\n\t} else if this.Parameter() == \"false\" {\n\t\treturn false\n\t} else {\n\t\terr_msg := fmt.Sprintf(\"parameter (%s) is not true or false\", this.Parameter())\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *CommandLineOption) IntParameter() int64 {\n\tint_parameter, err := strconv.ParseInt(this.Parameter(), 10, 64)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn int_parameter\n}\n\nfunc (this *CommandLineOption) StringParameter() string {\n\treturn this.Parameter()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/command_line_parser.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"slices\"\n\t\"strconv\"\n\t\"strings\"\n)\n\ntype CommandLineParser struct {\n\tcommand_line_options map[string]*CommandLineOption\n\targs                 map[string]bool\n}\n\nfunc (this *CommandLineParser) Init() {\n\tthis.command_line_options = make(map[string]*CommandLineOption, 0)\n\tthis.args = make(map[string]bool, 0)\n}\n\nfunc (this *CommandLineParser) AddOption(\n\tcommand_line_option_type CommandLineOptionType,\n\toption string,\n\tdefault_parameter string,\n\thelp_msg string,\n) {\n\tif _, found := this.command_line_options[option]; found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is already added to the parser\")\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := new(CommandLineOption)\n\tcommand_line_option.Init(command_line_option_type, option, default_parameter, help_msg)\n\tthis.command_line_options[option] = command_line_option\n}\n\nfunc (this *CommandLineParser) Parse(os_args []string) {\n\tfor i := 1; i < len(os_args); i++ {\n\t\tos_arg := os_args[i]\n\n\t\tif os_arg[0:2] == \"--\" {\n\t\t\toption := os_arg[2:]\n\t\t\tcustom_parameter := os_args[i+1]\n\n\t\t\tthis.command_line_options[option].SetCustomParameter(custom_parameter)\n\n\t\t\ti++\n\t\t} else if os_arg[0:1] == \"-\" {\n\t\t\targ := os_arg[1:]\n\n\t\t\tif _, found := this.args[arg]; found {\n\t\t\t\terr_msg := fmt.Sprintf(\"arg (%s) is already set\", arg)\n\t\t\t\terr := errors.New(err_msg)\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.args[arg] = true\n\t\t} else {\n\t\t\terr := errors.New(\"command line options are corrupted\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *CommandLineParser) BoolParameter(option string) bool {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.BoolParameter()\n}\n\nfunc (this *CommandLineParser) IntParameter(option string) int64 {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.IntParameter()\n}\n\nfunc (this *CommandLineParser) StringParameter(option string) string {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.StringParameter()\n}\n\nfunc (this *CommandLineParser) DataPrepParams() []int {\n\tstring_params := strings.Split(this.StringParameter(\"data_prep_params\"), \",\")\n\n\tdata_prep_params := make([]int, 0)\n\tfor _, string_param := range string_params {\n\t\tint_param, err := strconv.Atoi(string_param)\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tdata_prep_params = append(data_prep_params, int_param)\n\t}\n\treturn data_prep_params\n}\n\nfunc (this *CommandLineParser) IsArgSet(arg string) bool {\n\tif _, found := this.args[arg]; found {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *CommandLineParser) Options() []string {\n\toptions := make([]string, 0)\n\tfor option := range this.command_line_options {\n\t\toptions = append(options, option)\n\t}\n\n\tslices.Sort(options)\n\treturn options\n}\n\nfunc (this *CommandLineParser) Args() []string {\n\targs := make([]string, 0)\n\tfor arg := range this.args {\n\t\targs = append(args, arg)\n\t}\n\n\tslices.Sort(args)\n\treturn args\n}\n\nfunc (this *CommandLineParser) StringifyOptions() string {\n\tstr := \"OPTIONS\\n\"\n\n\tfor option, command_line_option := range this.command_line_options {\n\t\tstr += option + \"  -->  \" + command_line_option.Parameter() + \"\\n\"\n\t}\n\n\treturn str\n}\n\nfunc (this *CommandLineParser) StringifyArgs() string {\n\tstr := \"ARGS\\n\"\n\n\tfor arg := range this.args {\n\t\tstr += arg + \"\\n\"\n\t}\n\n\treturn str\n}\n\nfunc (this *CommandLineParser) StringifyHelpMsgs() string {\n\tstr := \"HELP_MSGS\\n\"\n\n\tfor option, command_line_option := range this.command_line_options {\n\t\tstr += option + \"  -->  \" + command_line_option.HelpMsg() + \"\\n\"\n\t}\n\n\treturn str\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/command_line_validator.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"os\"\n)\n\ntype CommandLineValidator struct {\n\tcommand_line_parser *CommandLineParser\n}\n\nfunc (this *CommandLineValidator) Init(command_line_parser *CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n}\n\nfunc (this *CommandLineValidator) Validate() {\n\tif this.command_line_parser.IntParameter(\"num_simulation_threads\") <= 0 {\n\t\terr := errors.New(\"num_simulation_threads <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_channels\") <= 0 {\n\t\terr := errors.New(\"num_channels <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_ranks_per_channel\") <= 0 {\n\t\terr := errors.New(\"num_ranks <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_dpus_per_rank\") <= 0 {\n\t\terr := errors.New(\"num_dpus <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_tasklets\") <= 0 {\n\t\terr := errors.New(\"num_tasklets <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif _, stat_err := os.Stat(this.command_line_parser.StringParameter(\"root_dirpath\")); os.IsNotExist(\n\t\tstat_err,\n\t) {\n\t\tfmt.Println(this.command_line_parser.StringParameter(\"root_dirpath\"))\n\n\t\terr := errors.New(\"root_dirpath does not exist\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"logic_frequency\") <= 0 {\n\t\terr := errors.New(\"logic_frequency <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"memory_frequency\") <= 0 {\n\t\terr := errors.New(\"memory_frequency <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_pipeline_stages\") <= 0 {\n\t\terr := errors.New(\"num_pipeline_stages <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_revolver_scheduling_cycles\") < 0 {\n\t\terr := errors.New(\"num_revolver_scheduling_cycles < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"wordline_size\") <= 0 {\n\t\terr := errors.New(\"wordline_size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"min_access_granularity\") <= 0 {\n\t\terr := errors.New(\"min_access_granularity <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"min_access_granularity\") <= 0 {\n\t\terr := errors.New(\"min_access_granularity <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_rcd\") < 0 {\n\t\terr := errors.New(\"t_rcd < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_ras\") < 0 {\n\t\terr := errors.New(\"t_ras < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_rp\") < 0 {\n\t\terr := errors.New(\"t_rp < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_cl\") < 0 {\n\t\terr := errors.New(\"t_cl < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_bl\") < 0 {\n\t\terr := errors.New(\"t_bl < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"read_bandwidth\") <= 0 {\n\t\terr := errors.New(\"read_bandwidth <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"write_bandwidth\") <= 0 {\n\t\terr := errors.New(\"write_bandwidth <= 0\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/config_loader.go",
    "content": "package misc\n\ntype ConfigLoader struct {\n}\n\nfunc (this *ConfigLoader) Init() {\n}\n\nfunc (this *ConfigLoader) AddressWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) AtomicDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) AtomicOffset() int64 {\n\treturn 0\n}\n\nfunc (this *ConfigLoader) AtomicSize() int64 {\n\treturn 256\n}\n\nfunc (this *ConfigLoader) IramDataWidth() int {\n\treturn 96\n}\n\nfunc (this *ConfigLoader) IramOffset() int64 {\n\treturn 384 * 1024\n}\n\nfunc (this *ConfigLoader) IramSize() int64 {\n\treturn 48 * 1024\n}\n\nfunc (this *ConfigLoader) WramDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) WramOffset() int64 {\n\treturn 512\n}\n\nfunc (this *ConfigLoader) WramSize() int64 {\n\treturn 128 * 1024\n}\n\nfunc (this *ConfigLoader) MramDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) MramOffset() int64 {\n\treturn 512 * 1024\n}\n\nfunc (this *ConfigLoader) MramSize() int64 {\n\treturn 64 * 1024 * 1024\n}\n\nfunc (this *ConfigLoader) StackSize() int64 {\n\treturn 2 * 1024\n}\n\nfunc (this *ConfigLoader) HeapSize() int64 {\n\treturn 4 * 1024\n}\n\nfunc (this *ConfigLoader) NumGpRegisters() int {\n\treturn 24\n}\n\nfunc (this *ConfigLoader) MaxNumTasklets() int {\n\treturn 24\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/config_validator.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n)\n\ntype ConfigValidator struct {\n\tconfig_loader *ConfigLoader\n}\n\nfunc (this *ConfigValidator) Init(config_loader *ConfigLoader) {\n\tthis.config_loader = config_loader\n}\n\nfunc (this *ConfigValidator) Validate() {\n\tif this.config_loader.AddressWidth() <= 0 {\n\t\terr := errors.New(\"address width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicDataWidth() <= 0 {\n\t\terr := errors.New(\"atomic data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramDataWidth() <= 0 {\n\t\terr := errors.New(\"IRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramDataWidth() <= 0 {\n\t\terr := errors.New(\"WRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramDataWidth() <= 0 {\n\t\terr := errors.New(\"MRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicOffset() < 0 {\n\t\terr := errors.New(\"atomic offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramOffset() < 0 {\n\t\terr := errors.New(\"IRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramOffset() < 0 {\n\t\terr := errors.New(\"WRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramOffset() < 0 {\n\t\terr := errors.New(\"MRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicSize() <= 0 {\n\t\terr := errors.New(\"atomic size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramSize() <= 0 {\n\t\terr := errors.New(\"IRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramSize() <= 0 {\n\t\terr := errors.New(\"WRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramSize() <= 0 {\n\t\terr := errors.New(\"MRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and IRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and WRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t) {\n\t\terr := errors.New(\"IRAM and WRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"IRAM and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"WRAM and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.StackSize() <= 0 {\n\t\terr := errors.New(\"stack size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.HeapSize() <= 0 {\n\t\terr := errors.New(\"heap size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.NumGpRegisters() <= 0 {\n\t\terr := errors.New(\"num gp registers <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MaxNumTasklets() <= 0 {\n\t\terr := errors.New(\"max num tasklets <= 0\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ConfigValidator) AreOverlapped(\n\toffset1 int64,\n\tsize1 int64,\n\toffset2 int64,\n\tsize2 int64,\n) bool {\n\tif offset1 <= offset2 && offset2 <= offset1+size1 {\n\t\treturn true\n\t} else if offset1 <= offset2+size2 && offset2+size2 <= offset1+size1 {\n\t\treturn true\n\t} else if offset2 <= offset1 && offset1 <= offset2+size2 {\n\t\treturn true\n\t} else if offset2 <= offset1+size1 && offset1+size1 <= offset2+size2 {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/file_dumper.go",
    "content": "package misc\n\nimport (\n\t\"bufio\"\n\t\"os\"\n)\n\ntype FileDumper struct {\n\tpath string\n}\n\nfunc (this *FileDumper) Init(path string) {\n\tthis.path = path\n}\n\nfunc (this *FileDumper) WriteLines(lines []string) {\n\tfile, create_err := os.Create(this.path)\n\n\tif create_err != nil {\n\t\tpanic(create_err)\n\t}\n\n\tdefer file.Close()\n\n\twriter := bufio.NewWriter(file)\n\n\tfor _, line := range lines {\n\t\t_, write_err := writer.WriteString(line + \"\\n\")\n\n\t\tif write_err != nil {\n\t\t\tpanic(write_err)\n\t\t}\n\t}\n\n\twriter.Flush()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/file_scanner.go",
    "content": "package misc\n\nimport (\n\t\"bufio\"\n\t\"os\"\n)\n\ntype FileScanner struct {\n\tpath string\n}\n\nfunc (this *FileScanner) Init(path string) {\n\tthis.path = path\n}\n\nfunc (this *FileScanner) ReadLines() []string {\n\tfile, open_err := os.Open(this.path)\n\n\tif open_err != nil {\n\t\tpanic(open_err)\n\t}\n\n\tdefer file.Close()\n\n\tscanner := bufio.NewScanner(file)\n\n\tlines := make([]string, 0)\n\tfor scanner.Scan() {\n\t\tlines = append(lines, scanner.Text())\n\t}\n\n\tif scan_err := scanner.Err(); scan_err != nil {\n\t\tpanic(scan_err)\n\t}\n\n\treturn lines\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/misc/stat_factory.go",
    "content": "package misc\n\nimport (\n\t\"fmt\"\n\t\"slices\"\n)\n\ntype StatFactory struct {\n\tname  string\n\tstats map[string]int64\n}\n\nfunc (this *StatFactory) Init(name string) {\n\tthis.name = name\n\tthis.stats = make(map[string]int64, 0)\n}\n\nfunc (this *StatFactory) Name() string {\n\treturn this.name\n}\n\nfunc (this *StatFactory) Stats() []string {\n\tstats := make([]string, 0)\n\tfor stat, _ := range this.stats {\n\t\tstats = append(stats, stat)\n\t}\n\n\tslices.Sort(stats)\n\treturn stats\n}\n\nfunc (this *StatFactory) Value(stat string) int64 {\n\treturn this.stats[stat]\n}\n\nfunc (this *StatFactory) Increment(stat string, value int64) {\n\tthis.stats[stat] += value\n}\n\nfunc (this *StatFactory) ToLines() []string {\n\tlines := make([]string, 0)\n\tfor stat, value := range this.stats {\n\t\tline := fmt.Sprintf(\"%s_%s: %d\", this.name, stat, value)\n\t\tlines = append(lines, line)\n\t}\n\treturn lines\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/channel/channel.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"sync\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n\t\"uPIMulator/src/simulator/rank\"\n)\n\ntype Channel struct {\n\tmutex sync.Mutex\n\n\tchannel_id int\n\tranks      []*rank.Rank\n\n\tread_bandwidth  int64\n\twrite_bandwidth int64\n\n\tinput_q         *ChannelMessageQ\n\tcommunication_q *ChannelMessageQ\n\tready_q         *ChannelMessageQ\n}\n\nfunc (this *Channel) Init(channel_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\n\tthis.ranks = make([]*rank.Rank, 0)\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tfor i := 0; i < num_ranks_per_channel; i++ {\n\t\trank_ := new(rank.Rank)\n\t\trank_.Init(channel_id, i, command_line_parser)\n\t\tthis.ranks = append(this.ranks, rank_)\n\t}\n\n\tthis.read_bandwidth = command_line_parser.IntParameter(\"read_bandwidth\")\n\tthis.write_bandwidth = command_line_parser.IntParameter(\"write_bandwidth\")\n\n\tthis.input_q = new(ChannelMessageQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.communication_q = new(ChannelMessageQ)\n\tthis.communication_q.Init(-1, 0)\n\n\tthis.ready_q = new(ChannelMessageQ)\n\tthis.ready_q.Init(-1, 0)\n}\n\nfunc (this *Channel) Fini() {\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Fini()\n\t}\n\n\tthis.input_q.Fini()\n\tthis.communication_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Channel) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Channel) NumRanks() int {\n\treturn len(this.ranks)\n}\n\nfunc (this *Channel) Ranks() []*rank.Rank {\n\treturn this.ranks\n}\n\nfunc (this *Channel) Dpus() []*dpu.Dpu {\n\tdpus := make([]*dpu.Dpu, 0)\n\n\tfor _, rank_ := range this.ranks {\n\t\tdpus = append(dpus, rank_.Dpus()...)\n\t}\n\n\treturn dpus\n}\n\nfunc (this *Channel) Lock() {\n\tthis.mutex.Lock()\n}\n\nfunc (this *Channel) Unlock() {\n\tthis.mutex.Unlock()\n}\n\nfunc (this *Channel) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Channel) Push(channel_message *ChannelMessage) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"channel cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(channel_message)\n}\n\nfunc (this *Channel) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Channel) Pop() *ChannelMessage {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"channel cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Channel) CanPopChannelMessage(channel_message *ChannelMessage) bool {\n\tfor i := 0; this.ready_q.CanPop(i + 1); i++ {\n\t\tcm, _ := this.ready_q.Front(i)\n\n\t\tif channel_message == cm {\n\t\t\treturn true\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *Channel) PopChannelMessage(channel_message *ChannelMessage) {\n\tif !this.CanPopChannelMessage(channel_message) {\n\t\terr := errors.New(\"channel cannot be popped with the channel message\")\n\t\tpanic(err)\n\t}\n\n\tfor i := 0; this.ready_q.CanPop(i + 1); i++ {\n\t\tcm, _ := this.ready_q.Front(i)\n\n\t\tif channel_message == cm {\n\t\t\tthis.ready_q.Remove(i)\n\t\t}\n\t}\n}\n\nfunc (this *Channel) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceCommunicationQ()\n\n\tthis.input_q.Cycle()\n\tthis.communication_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Channel) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.communication_q.CanPush(1) {\n\t\tchannel_messaage := this.input_q.Pop()\n\n\t\tvar latency int64\n\n\t\tchannel_operation := channel_messaage.ChannelOperation()\n\t\tif channel_operation == READ {\n\t\t\tlatency = channel_messaage.Size() / this.read_bandwidth\n\t\t} else if channel_operation == WRITE {\n\t\t\tlatency = channel_messaage.Size() / this.write_bandwidth\n\t\t} else {\n\t\t\terr := errors.New(\"channel operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t\tthis.communication_q.PushWithTimer(channel_messaage, latency)\n\t}\n}\n\nfunc (this *Channel) ServiceCommunicationQ() {\n\tif this.communication_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tchannel_messaage := this.communication_q.Pop()\n\n\t\trank_id := channel_messaage.RankId()\n\t\trank_ := this.ranks[rank_id]\n\n\t\tif rank_.RankId() != rank_id {\n\t\t\terr := errors.New(\"rank's rank ID != rank ID\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tdpu_ids := channel_messaage.DpuIds()\n\n\t\taddress := channel_messaage.Address()\n\t\tsize := channel_messaage.Size()\n\n\t\tchannel_operation := channel_messaage.ChannelOperation()\n\t\tif channel_operation == READ {\n\t\t\tbyte_streams := make([]*encoding.ByteStream, 0)\n\n\t\t\tfor _, dpu_id := range dpu_ids {\n\t\t\t\tbyte_stream := rank_.Read(dpu_id, address, size)\n\t\t\t\tbyte_streams = append(byte_streams, byte_stream)\n\t\t\t}\n\n\t\t\tchannel_messaage.SetByteStreams(byte_streams)\n\t\t} else if channel_operation == WRITE {\n\t\t\tfor i, _ := range dpu_ids {\n\t\t\t\tdpu_id := dpu_ids[i]\n\t\t\t\tbyte_stream := channel_messaage.ByteStreams()[i]\n\n\t\t\t\trank_.Write(dpu_id, address, byte_stream)\n\t\t\t}\n\t\t} else {\n\t\t\terr := errors.New(\"channel operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.ready_q.Push(channel_messaage)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/channel/channel_message.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype ChannelOperation int\n\nconst (\n\tREAD ChannelOperation = iota\n\tWRITE\n)\n\ntype ChannelMessage struct {\n\tchannel_operation ChannelOperation\n\tchannel_id        int\n\trank_id           int\n\tdpu_ids           []int\n\taddress           int64\n\tsize              int64\n\tbyte_streams      []*encoding.ByteStream\n}\n\nfunc (this *ChannelMessage) InitRead(\n\tchannel_id int,\n\trank_id int,\n\tdpu_ids []int,\n\taddress int64,\n\tsize int64,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tfor _, dpu_id := range dpu_ids {\n\t\tif dpu_id < 0 {\n\t\t\terr := errors.New(\"DPU ID < 0\")\n\t\t\tpanic(err)\n\t\t} else if dpu_id%8 != dpu_ids[0]%8 {\n\t\t\terr := errors.New(\"DPU ID % 8 are different\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.channel_operation = READ\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_ids = dpu_ids\n\tthis.address = address\n\tthis.size = size\n\tthis.byte_streams = make([]*encoding.ByteStream, 0)\n}\n\nfunc (this *ChannelMessage) InitWrite(\n\tchannel_id int,\n\trank_id int,\n\tdpu_ids []int,\n\taddress int64,\n\tsize int64,\n\tbyte_streams []*encoding.ByteStream,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tfor _, dpu_id := range dpu_ids {\n\t\tif dpu_id < 0 {\n\t\t\terr := errors.New(\"DPU ID < 0\")\n\t\t\tpanic(err)\n\t\t} else if dpu_id%8 != dpu_ids[0]%8 {\n\t\t\terr := errors.New(\"DPU ID % 8 are different\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tfor _, byte_stream := range byte_streams {\n\t\tif byte_stream.Size() != size {\n\t\t\terr := errors.New(\"byte stream's size != size\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.channel_operation = WRITE\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_ids = dpu_ids\n\tthis.address = address\n\tthis.size = size\n\tthis.byte_streams = byte_streams\n}\n\nfunc (this *ChannelMessage) SetByteStreams(byte_streams []*encoding.ByteStream) {\n\tfor _, byte_stream := range byte_streams {\n\t\tif byte_stream.Size() != this.size {\n\t\t\terr := errors.New(\"byte stream's size != size\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.byte_streams = byte_streams\n}\n\nfunc (this *ChannelMessage) ChannelOperation() ChannelOperation {\n\treturn this.channel_operation\n}\n\nfunc (this *ChannelMessage) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *ChannelMessage) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *ChannelMessage) DpuIds() []int {\n\treturn this.dpu_ids\n}\n\nfunc (this *ChannelMessage) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *ChannelMessage) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *ChannelMessage) ByteStreams() []*encoding.ByteStream {\n\treturn this.byte_streams\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/channel/channel_message_q.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n)\n\ntype ChannelMessageQ struct {\n\tsize  int\n\ttimer int64\n\n\tchannel_messages []*ChannelMessage\n\tcycles           []int64\n}\n\nfunc (this *ChannelMessageQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.channel_messages = make([]*ChannelMessage, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *ChannelMessageQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"channel message queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ChannelMessageQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *ChannelMessageQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *ChannelMessageQ) IsEmpty() bool {\n\treturn len(this.channel_messages) == 0\n}\n\nfunc (this *ChannelMessageQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.channel_messages) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelMessageQ) Push(channel_message *ChannelMessage) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel message queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_messages = append(this.channel_messages, channel_message)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *ChannelMessageQ) PushWithTimer(channel_message *ChannelMessage, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel message queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_messages = append(this.channel_messages, channel_message)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *ChannelMessageQ) CanPop(num_items int) bool {\n\tif len(this.channel_messages) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelMessageQ) Pop() *ChannelMessage {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"channel message queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tchannel_message := this.channel_messages[0]\n\n\tthis.channel_messages = this.channel_messages[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn channel_message\n}\n\nfunc (this *ChannelMessageQ) Front(pos int) (*ChannelMessage, int64) {\n\tif this.IsEmpty() {\n\t\terr := errors.New(\"channel message queue is empty\")\n\t\tpanic(err)\n\t}\n\n\treturn this.channel_messages[pos], this.cycles[pos]\n}\n\nfunc (this *ChannelMessageQ) Remove(pos int) {\n\tthis.channel_messages = append(this.channel_messages[:pos], this.channel_messages[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *ChannelMessageQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/cycle_job.go",
    "content": "package simulator\n\nimport (\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype CycleJob struct {\n\tdpu *dpu.Dpu\n}\n\nfunc (this *CycleJob) Init(dpu_ *dpu.Dpu) {\n\tthis.dpu = dpu_\n}\n\nfunc (this *CycleJob) Execute() {\n\tthis.dpu.Cycle()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dpu.go",
    "content": "package dpu\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu/dram\"\n\t\"uPIMulator/src/simulator/dpu/logic\"\n\t\"uPIMulator/src/simulator/dpu/sram\"\n)\n\ntype Dpu struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tlogic_frequency  int64\n\tmemory_frequency int64\n\tfrequency_ratio  float64\n\tcycles           int64\n\n\tthreads           []*logic.Thread\n\tthread_scheduler  *logic.ThreadScheduler\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\twram              *sram.Wram\n\tmram              *dram.Mram\n\toperand_collector *logic.OperandCollector\n\tmemory_controller *dram.MemoryController\n\tdma               *logic.Dma\n\tlogic             *logic.Logic\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *Dpu) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.logic_frequency = command_line_parser.IntParameter(\"logic_frequency\")\n\tthis.memory_frequency = command_line_parser.IntParameter(\"memory_frequency\")\n\tthis.frequency_ratio = float64(this.memory_frequency) / float64(this.logic_frequency)\n\tthis.cycles = 0\n\n\tthis.threads = make([]*logic.Thread, 0)\n\tnum_threads := int(command_line_parser.IntParameter(\"num_tasklets\"))\n\tfor i := 0; i < num_threads; i++ {\n\t\tthread := new(logic.Thread)\n\t\tthread.Init(i)\n\t\tthis.threads = append(this.threads, thread)\n\t}\n\n\tthis.thread_scheduler = new(logic.ThreadScheduler)\n\tthis.thread_scheduler.Init(channel_id, rank_id, dpu_id, this.threads, command_line_parser)\n\n\tthis.atomic = new(sram.Atomic)\n\tthis.atomic.Init()\n\n\tthis.iram = new(sram.Iram)\n\tthis.iram.Init()\n\n\tthis.wram = new(sram.Wram)\n\tthis.wram.Init()\n\n\tthis.mram = new(dram.Mram)\n\tthis.mram.Init(command_line_parser)\n\n\tthis.operand_collector = new(logic.OperandCollector)\n\tthis.operand_collector.Init()\n\tthis.operand_collector.ConnectWram(this.wram)\n\n\tthis.memory_controller = new(dram.MemoryController)\n\tthis.memory_controller.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\tthis.memory_controller.ConnectMram(this.mram)\n\n\tthis.dma = new(logic.Dma)\n\tthis.dma.Init()\n\tthis.dma.ConnectAtomic(this.atomic)\n\tthis.dma.ConnectIram(this.iram)\n\tthis.dma.ConnectOperandCollector(this.operand_collector)\n\tthis.dma.ConnectMemoryController(this.memory_controller)\n\n\tthis.logic = new(logic.Logic)\n\tthis.logic.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\tthis.logic.ConnectThreadScheduler(this.thread_scheduler)\n\tthis.logic.ConnectAtomic(this.atomic)\n\tthis.logic.ConnectIram(this.iram)\n\tthis.logic.ConnectOperandCollector(this.operand_collector)\n\tthis.logic.ConnectDma(this.dma)\n\n\tname := fmt.Sprintf(\"DPU%d-%d-%d\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *Dpu) Fini() {\n\tfor _, thread := range this.threads {\n\t\tthread.Fini()\n\t}\n\n\tthis.atomic.Fini()\n\tthis.iram.Fini()\n\tthis.wram.Fini()\n\tthis.mram.Fini()\n\n\tthis.operand_collector.Fini()\n\tthis.memory_controller.Fini()\n\n\tthis.logic.Fini()\n\tthis.dma.Fini()\n}\n\nfunc (this *Dpu) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Dpu) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Dpu) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *Dpu) ThreadScheduler() *logic.ThreadScheduler {\n\treturn this.thread_scheduler\n}\n\nfunc (this *Dpu) Logic() *logic.Logic {\n\treturn this.logic\n}\n\nfunc (this *Dpu) MemoryController() *dram.MemoryController {\n\treturn this.memory_controller\n}\n\nfunc (this *Dpu) Dma() *logic.Dma {\n\treturn this.dma\n}\n\nfunc (this *Dpu) Threads() []*logic.Thread {\n\treturn this.threads\n}\n\nfunc (this *Dpu) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *Dpu) Boot() {\n\tthis.thread_scheduler.Boot(0)\n}\n\nfunc (this *Dpu) IsZombie() bool {\n\tfor _, thread := range this.threads {\n\t\tif thread.ThreadState() != logic.ZOMBIE {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn this.logic.IsEmpty() && this.memory_controller.IsEmpty()\n}\n\nfunc (this *Dpu) Cycle() {\n\tfor _, thread := range this.threads {\n\t\tthread.IncrementIssueCycle()\n\t}\n\n\tthis.thread_scheduler.Cycle()\n\tthis.logic.Cycle()\n\tthis.dma.Cycle()\n\n\tnum_memory_cycles := int(this.frequency_ratio*float64(this.cycles) - this.frequency_ratio*float64(this.cycles-1))\n\tfor i := 0; i < num_memory_cycles; i++ {\n\t\tthis.memory_controller.Cycle()\n\t}\n\n\tthis.cycles++\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/dma_command.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n)\n\ntype DmaCommand struct {\n\tmemory_operation MemoryOperation\n\twram_address     *int64\n\tmram_address     *int64\n\tsize             int64\n\n\tbyte_stream *encoding.ByteStream\n\tacks        []bool\n\n\tinstruction *instruction.Instruction\n}\n\nfunc (this *DmaCommand) InitReadFromMram(mram_address int64, size int64) {\n\tthis.memory_operation = READ\n\tthis.wram_address = nil\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = nil\n}\n\nfunc (this *DmaCommand) InitWriteToMram(\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tthis.memory_operation = WRITE\n\tthis.wram_address = nil\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = nil\n}\n\nfunc (this *DmaCommand) InitReadFromMramToWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif instruction_.OpCode() != instruction.LDMA {\n\t\terr := errors.New(\"instruction's op code != LDMA\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = READ\n\n\tthis.wram_address = new(int64)\n\t*this.wram_address = wram_address\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = instruction_\n}\n\nfunc (this *DmaCommand) InitWriteToMramFromWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif instruction_.OpCode() != instruction.SDMA {\n\t\terr := errors.New(\"instruction's op code != SDMA\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = WRITE\n\n\tthis.wram_address = new(int64)\n\t*this.wram_address = wram_address\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = instruction_\n}\n\nfunc (this *DmaCommand) Fini() {\n\tif !this.IsReady() {\n\t\terr := errors.New(\"DMA command is not ready\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *DmaCommand) WramAddress() int64 {\n\tif this.wram_address == nil {\n\t\terr := errors.New(\"DMA command does not have a WRAM address\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.wram_address\n}\n\nfunc (this *DmaCommand) MramAddress() int64 {\n\tif this.mram_address == nil {\n\t\terr := errors.New(\"DMA command does not have an MRAM address\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.mram_address\n}\n\nfunc (this *DmaCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *DmaCommand) HasInstruction() bool {\n\treturn this.instruction != nil\n}\n\nfunc (this *DmaCommand) Instruction() *instruction.Instruction {\n\treturn this.instruction\n}\n\nfunc (this *DmaCommand) ByteStream(mram_address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *DmaCommand) SetByteStream(\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *DmaCommand) SetAck(mram_address int64, size int64) {\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tif this.acks[index] {\n\t\t\terr := errors.New(\"ACK is already set\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.acks[index] = true\n\t}\n}\n\nfunc (this *DmaCommand) IsReady() bool {\n\tfor _, ack := range this.acks {\n\t\tif !ack {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *DmaCommand) Index(mram_address int64) int {\n\tif mram_address < this.MramAddress() {\n\t\terr := errors.New(\"MRAM address < DMA command's MRAM address\")\n\t\tpanic(err)\n\t} else if mram_address >= this.MramAddress()+this.Size() {\n\t\terr := errors.New(\"MRAM address >= DMA command's MRAM address + DMA command's size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(mram_address - this.MramAddress())\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/dma_command_q.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n)\n\ntype DmaCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tdma_commands []*DmaCommand\n\tcycles       []int64\n}\n\nfunc (this *DmaCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.dma_commands = make([]*DmaCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *DmaCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"DMA command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *DmaCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *DmaCommandQ) IsEmpty() bool {\n\treturn len(this.dma_commands) == 0\n}\n\nfunc (this *DmaCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.dma_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Push(dma_command *DmaCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *DmaCommandQ) PushWithTimer(dma_command *DmaCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *DmaCommandQ) CanPop(num_items int) bool {\n\tif len(this.dma_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Pop() *DmaCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"DMA command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tdma_command := this.dma_commands[0]\n\n\tthis.dma_commands = this.dma_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn dma_command\n}\n\nfunc (this *DmaCommandQ) Front(pos int) (*DmaCommand, int64) {\n\tif this.IsEmpty() {\n\t\terr := errors.New(\"DMA command queue is empty\")\n\t\tpanic(err)\n\t}\n\n\treturn this.dma_commands[pos], this.cycles[pos]\n}\n\nfunc (this *DmaCommandQ) Remove(pos int) {\n\tthis.dma_commands = append(this.dma_commands[:pos], this.dma_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *DmaCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/memory_command.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype MemoryOperation int\n\nconst (\n\tACTIVATION MemoryOperation = iota\n\tREAD\n\tWRITE\n\tPRECHARGE\n)\n\ntype MemoryCommand struct {\n\tmemory_operation MemoryOperation\n\taddress          int64\n\tsize             int64\n\tbyte_stream      *encoding.ByteStream\n\tdma_command      *DmaCommand\n}\n\nfunc (this *MemoryCommand) InitActivation(memory_operation MemoryOperation, address int64) {\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = 0\n\tthis.byte_stream = nil\n\tthis.dma_command = nil\n}\n\nfunc (this *MemoryCommand) InitRead(\n\tmemory_operation MemoryOperation,\n\taddress int64,\n\tsize int64,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != READ {\n\t\terr := errors.New(\"DMA operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) InitWrite(\n\tmemory_operation MemoryOperation,\n\taddress int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != WRITE {\n\t\terr := errors.New(\"memory operation != WRITE\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != WRITE {\n\t\terr := errors.New(\"DMA operation != WRITE\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *MemoryCommand) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *MemoryCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *MemoryCommand) ByteStream() *encoding.ByteStream {\n\treturn this.byte_stream\n}\n\nfunc (this *MemoryCommand) SetByteStream(byte_stream *encoding.ByteStream) {\n\tif this.memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *MemoryCommand) DmaCommand() *DmaCommand {\n\tif this.dma_command == nil {\n\t\terr := errors.New(\"memory command does not have a DMA command\")\n\t\tpanic(err)\n\t}\n\n\treturn this.dma_command\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/memory_command_q.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n)\n\ntype MemoryCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tmemory_commands []*MemoryCommand\n\tcycles          []int64\n}\n\nfunc (this *MemoryCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.memory_commands = make([]*MemoryCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *MemoryCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *MemoryCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *MemoryCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *MemoryCommandQ) IsEmpty() bool {\n\treturn len(this.memory_commands) == 0\n}\n\nfunc (this *MemoryCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.memory_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *MemoryCommandQ) PushWithTimer(memory_command *MemoryCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *MemoryCommandQ) CanPop(num_items int) bool {\n\tif len(this.memory_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Pop() *MemoryCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"memory command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tmemory_command := this.memory_commands[0]\n\n\tthis.memory_commands = this.memory_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn memory_command\n}\n\nfunc (this *MemoryCommandQ) Front(pos int) (*MemoryCommand, int64) {\n\tif this.IsEmpty() {\n\t\terr := errors.New(\"memory command queue is empty\")\n\t\tpanic(err)\n\t}\n\n\treturn this.memory_commands[pos], this.cycles[pos]\n}\n\nfunc (this *MemoryCommandQ) Remove(pos int) {\n\tthis.memory_commands = append(this.memory_commands[:pos], this.memory_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *MemoryCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/memory_controller.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryController struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\twordline_size int64\n\n\tmemory_scheduler *MemoryScheduler\n\trow_buffer       *RowBuffer\n\tmram             *Mram\n\n\tinput_q          *DmaCommandQ\n\twait_q           *DmaCommandQ\n\tmemory_command_q *MemoryCommandQ\n\tready_q          *DmaCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *MemoryController) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.memory_scheduler = new(MemoryScheduler)\n\tthis.memory_scheduler.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.row_buffer = new(RowBuffer)\n\tthis.row_buffer.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.mram = nil\n\n\tthis.input_q = new(DmaCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.wait_q = new(DmaCommandQ)\n\tthis.wait_q.Init(-1, 0)\n\n\tthis.memory_command_q = new(MemoryCommandQ)\n\tthis.memory_command_q.Init(-1, 0)\n\n\tthis.ready_q = new(DmaCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tname := fmt.Sprintf(\"MemoryController[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *MemoryController) Fini() {\n\tthis.memory_scheduler.Fini()\n\tthis.row_buffer.Fini()\n\n\tthis.input_q.Fini()\n\tthis.wait_q.Fini()\n\tthis.memory_command_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryController) ConnectMram(mram *Mram) {\n\tif this.mram != nil {\n\t\terr := errors.New(\"MRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram = mram\n\tthis.row_buffer.ConnectMram(mram)\n}\n\nfunc (this *MemoryController) MemoryScheduler() *MemoryScheduler {\n\treturn this.memory_scheduler\n}\n\nfunc (this *MemoryController) RowBuffer() *RowBuffer {\n\treturn this.row_buffer\n}\n\nfunc (this *MemoryController) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *MemoryController) IsEmpty() bool {\n\treturn this.memory_scheduler.IsEmpty() &&\n\t\tthis.row_buffer.IsEmpty() &&\n\t\tthis.input_q.IsEmpty() &&\n\t\tthis.wait_q.IsEmpty() &&\n\t\tthis.memory_command_q.IsEmpty() &&\n\t\tthis.ready_q.IsEmpty()\n}\n\nfunc (this *MemoryController) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryController) Push(dma_command *DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory controller cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *MemoryController) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryController) Pop() *DmaCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory controller cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryController) Front() *DmaCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory controller cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tdma_command, _ := this.ready_q.Front(0)\n\treturn dma_command\n}\n\nfunc (this *MemoryController) Read(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.mram.Read(cur_wordline_address)\n\n\t\tfor i := cur_offset; i < cur_offset+cur_size; i++ {\n\t\t\tbyte_stream.Append(mram_byte_stream.Get(int(i)))\n\t\t}\n\n\t\tcur_address += cur_size\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *MemoryController) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tcur_byte_stream_offset := int64(0)\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.mram.Read(cur_wordline_address)\n\n\t\tfor i := int64(0); i < cur_size; i++ {\n\t\t\tmram_byte_stream.Set(int(i+cur_offset), byte_stream.Get(int(i+cur_byte_stream_offset)))\n\t\t}\n\n\t\tthis.mram.Write(cur_wordline_address, mram_byte_stream)\n\n\t\tcur_address += cur_size\n\t\tcur_byte_stream_offset += cur_size\n\t}\n}\n\nfunc (this *MemoryController) Flush() {\n\tthis.memory_scheduler.Flush()\n\tthis.row_buffer.Flush()\n}\n\nfunc (this *MemoryController) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceScheduler()\n\tthis.ServiceMemoryCommandQ()\n\tthis.ServiceRowBuffer()\n\tthis.ServiceWaitQ()\n\n\tthis.memory_scheduler.Cycle()\n\tthis.row_buffer.Cycle()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.memory_command_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.stat_factory.Increment(\"memory_cycle\", 1)\n}\n\nfunc (this *MemoryController) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) && this.memory_scheduler.CanPush() {\n\t\tdma_command := this.input_q.Pop()\n\t\tthis.memory_scheduler.Push(dma_command)\n\t\tthis.wait_q.Push(dma_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceScheduler() {\n\tif this.memory_scheduler.CanPop() && this.memory_command_q.CanPush(1) {\n\t\tmemory_command := this.memory_scheduler.Pop()\n\t\tthis.memory_command_q.Push(memory_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceMemoryCommandQ() {\n\tif this.memory_command_q.CanPop(1) && this.row_buffer.CanPush() {\n\t\tmemory_command := this.memory_command_q.Pop()\n\t\tthis.row_buffer.Push(memory_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceRowBuffer() {\n\tif this.row_buffer.CanPop() {\n\t\tmemory_command := this.row_buffer.Pop()\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\treturn\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\treturn\n\t\t} else if memory_operation == READ {\n\t\t\taddress := memory_command.Address()\n\t\t\tsize := memory_command.Size()\n\t\t\tbyte_stream := memory_command.ByteStream()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetByteStream(address, size, byte_stream)\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else if memory_operation == WRITE {\n\t\t\taddress := memory_command.Address()\n\t\t\tsize := memory_command.Size()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceWaitQ() {\n\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\tdma_command, _ := this.wait_q.Front(i)\n\n\t\tif dma_command.IsReady() && this.ready_q.CanPush(1) {\n\t\t\tthis.wait_q.Remove(i)\n\t\t\tthis.ready_q.Push(dma_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *MemoryController) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/memory_scheduler.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryScheduler struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tinput_q        *DmaCommandQ\n\treorder_buffer *MemoryCommandQ\n\tready_q        *MemoryCommandQ\n\n\trow_address            *int64\n\twordline_size          int64\n\tmin_access_granularity int64\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *MemoryScheduler) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.input_q = new(DmaCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.reorder_buffer = new(MemoryCommandQ)\n\tthis.reorder_buffer.Init(-1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.row_address = nil\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\n\tname := fmt.Sprintf(\"MemoryScheduler[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *MemoryScheduler) Fini() {\n\tthis.input_q.Fini()\n\tthis.reorder_buffer.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryScheduler) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *MemoryScheduler) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.reorder_buffer.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *MemoryScheduler) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryScheduler) Push(dma_command *DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory scheduler cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *MemoryScheduler) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryScheduler) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory scheduler cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryScheduler) Flush() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory scheduler cannot be flushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.row_address = nil\n}\n\nfunc (this *MemoryScheduler) Cycle() {\n\tthis.ServiceInputQ()\n\n\tif !this.ReorderFr() {\n\t\tthis.ReorderFcFs()\n\t}\n\n\tthis.input_q.Cycle()\n\tthis.reorder_buffer.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *MemoryScheduler) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tdma_command := this.input_q.Pop()\n\n\t\tthis.PopulateMemoryCommands(dma_command)\n\t}\n}\n\nfunc (this *MemoryScheduler) PopulateMemoryCommands(dma_command *DmaCommand) {\n\tbegin_address := dma_command.MramAddress()\n\tend_address := dma_command.MramAddress() + dma_command.Size()\n\n\tfor address := begin_address; address < end_address; {\n\t\twordline_address := this.WordlineAddress(address)\n\n\t\tsize := this.Min(\n\t\t\tthis.Min(\n\t\t\t\taddress+this.min_access_granularity,\n\t\t\t\twordline_address+this.wordline_size,\n\t\t\t),\n\t\t\tend_address,\n\t\t) - address\n\n\t\tmemory_operation := dma_command.MemoryOperation()\n\t\tmemory_command := new(MemoryCommand)\n\t\tif memory_operation == READ {\n\t\t\tmemory_command.InitRead(READ, address, size, dma_command)\n\t\t} else if memory_operation == WRITE {\n\t\t\tbyte_stream := dma_command.ByteStream(address, size)\n\t\t\tmemory_command.InitWrite(WRITE, address, size, byte_stream, dma_command)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.reorder_buffer.Push(memory_command)\n\n\t\taddress += size\n\t}\n}\n\nfunc (this *MemoryScheduler) ReorderFr() bool {\n\tif this.row_address != nil && this.ready_q.CanPush(1) {\n\t\tfor i := 0; this.reorder_buffer.CanPop(i + 1); i++ {\n\t\t\tmemory_command, _ := this.reorder_buffer.Front(i)\n\n\t\t\tif this.WordlineAddress(memory_command.Address()) == *this.row_address &&\n\t\t\t\tthis.ready_q.CanPush(1) {\n\t\t\t\tif i != 0 {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fr\", 1)\n\t\t\t\t} else {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fcfs\", 1)\n\t\t\t\t}\n\n\t\t\t\tthis.reorder_buffer.Remove(i)\n\t\t\t\tthis.ready_q.Push(memory_command)\n\n\t\t\t\treturn true\n\t\t\t}\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *MemoryScheduler) ReorderFcFs() bool {\n\tif this.reorder_buffer.CanPop(1) && this.row_address != nil && this.ready_q.CanPush(3) {\n\t\tmemory_command := this.reorder_buffer.Pop()\n\t\twordline_address := this.WordlineAddress(memory_command.Address())\n\n\t\tif wordline_address == *this.row_address {\n\t\t\terr := errors.New(\"FR has not worked correctly\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tprecharge := new(MemoryCommand)\n\t\tprecharge.InitActivation(PRECHARGE, *this.row_address)\n\n\t\tactivation := new(MemoryCommand)\n\t\tactivation.InitActivation(ACTIVATION, wordline_address)\n\n\t\tthis.ready_q.Push(precharge)\n\t\tthis.ready_q.Push(activation)\n\t\tthis.ready_q.Push(memory_command)\n\n\t\t*this.row_address = wordline_address\n\n\t\treturn true\n\t} else if this.reorder_buffer.CanPop(1) && this.row_address == nil && this.ready_q.CanPush(2) {\n\t\tmemory_command := this.reorder_buffer.Pop()\n\t\twordline_address := this.WordlineAddress(memory_command.Address())\n\n\t\tactivation := new(MemoryCommand)\n\t\tactivation.InitActivation(ACTIVATION, wordline_address)\n\n\t\tthis.ready_q.Push(activation)\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.row_address = new(int64)\n\t\t*this.row_address = wordline_address\n\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *MemoryScheduler) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *MemoryScheduler) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/mram.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Mram struct {\n\taddress int64\n\tsize    int64\n\n\twordline_size int64\n\twordlines     []*Wordline\n}\n\nfunc (this *Mram) Init(command_line_parser *misc.CommandLineParser) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.MramOffset()\n\tthis.size = config_loader.MramSize()\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tif this.wordline_size <= 0 {\n\t\terr := errors.New(\"wordline size <= 0\")\n\t\tpanic(err)\n\t} else if this.address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t} else if this.size%this.wordline_size != 0 {\n\t\terr := errors.New(\"size is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\tthis.wordlines = make([]*Wordline, 0)\n\tnum_wordlines := int(this.size / this.wordline_size)\n\tfor i := 0; i < num_wordlines; i++ {\n\t\twordline := new(Wordline)\n\t\twordline.Init(this.address+int64(i)*this.wordline_size, this.wordline_size)\n\t\tthis.wordlines = append(this.wordlines, wordline)\n\t}\n}\n\nfunc (this *Mram) Fini() {\n\tfor _, wordline := range this.wordlines {\n\t\twordline.Fini()\n\t}\n}\n\nfunc (this *Mram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Mram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Mram) Read(address int64) *encoding.ByteStream {\n\treturn this.wordlines[this.Index(address)].Read()\n}\n\nfunc (this *Mram) Write(address int64, byte_stream *encoding.ByteStream) {\n\tthis.wordlines[this.Index(address)].Write(byte_stream)\n}\n\nfunc (this *Mram) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < MRAM offset\")\n\t\tpanic(err)\n\t} else if address+this.wordline_size > this.address+this.size {\n\t\terr := errors.New(\"address + wordline size > MRAM offset + MRAM size\")\n\t\tpanic(err)\n\t} else if address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int((address - this.address) / this.wordline_size)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/row_buffer.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype RowBuffer struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tt_ras         int64\n\tt_rcd         int64\n\tt_cl          int64\n\tt_bl          int64\n\tt_rp          int64\n\twordline_size int64\n\n\tmram        *Mram\n\trow_address *int64\n\trow_buffer  *encoding.ByteStream\n\n\tinput_q *MemoryCommandQ\n\tready_q *MemoryCommandQ\n\n\tactivation_q *MemoryCommandQ\n\tio_q         *MemoryCommandQ\n\tbus_q        *MemoryCommandQ\n\tprecharge_q  *MemoryCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *RowBuffer) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.t_ras = command_line_parser.IntParameter(\"t_ras\")\n\tthis.t_rcd = command_line_parser.IntParameter(\"t_rcd\")\n\tthis.t_cl = command_line_parser.IntParameter(\"t_cl\")\n\tthis.t_bl = command_line_parser.IntParameter(\"t_bl\")\n\tthis.t_rp = command_line_parser.IntParameter(\"t_rp\")\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.mram = nil\n\tthis.row_address = nil\n\tthis.row_buffer = nil\n\n\tthis.input_q = new(MemoryCommandQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.activation_q = new(MemoryCommandQ)\n\tthis.activation_q.Init(1, this.t_ras)\n\n\tthis.io_q = new(MemoryCommandQ)\n\tthis.io_q.Init(1, this.t_cl)\n\n\tthis.bus_q = new(MemoryCommandQ)\n\tthis.bus_q.Init(1, this.t_bl)\n\n\tthis.precharge_q = new(MemoryCommandQ)\n\tthis.precharge_q.Init(1, this.t_rp)\n\n\tname := fmt.Sprintf(\"RowBuffer[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *RowBuffer) Fini() {\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n\tthis.activation_q.Fini()\n\tthis.io_q.Fini()\n\tthis.bus_q.Fini()\n\tthis.precharge_q.Fini()\n}\n\nfunc (this *RowBuffer) ConnectMram(mram *Mram) {\n\tif this.mram != nil {\n\t\terr := errors.New(\"MRAM is already connected\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram = mram\n}\n\nfunc (this *RowBuffer) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *RowBuffer) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.ready_q.IsEmpty() && this.activation_q.IsEmpty() &&\n\t\tthis.io_q.IsEmpty() &&\n\t\tthis.bus_q.IsEmpty() &&\n\t\tthis.precharge_q.IsEmpty()\n}\n\nfunc (this *RowBuffer) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *RowBuffer) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"row buffer cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(memory_command)\n}\n\nfunc (this *RowBuffer) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *RowBuffer) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"row buffer cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *RowBuffer) Flush() {\n\tif this.row_address != nil {\n\t\tthis.WriteToMram()\n\n\t\tthis.row_address = nil\n\t\tthis.row_buffer = nil\n\t}\n}\n\nfunc (this *RowBuffer) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceActivationQ()\n\tthis.ServiceIoQ()\n\tthis.ServiceBusQ()\n\tthis.ServicePrechargeQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.activation_q.Cycle()\n\tthis.io_q.Cycle()\n\tthis.bus_q.Cycle()\n\tthis.precharge_q.Cycle()\n}\n\nfunc (this *RowBuffer) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tmemory_command, _ := this.input_q.Front(0)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\tif this.activation_q.IsEmpty() && this.row_address == nil {\n\t\t\t\tthis.activation_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == READ {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == WRITE {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\tif this.activation_q.IsEmpty() && this.io_q.IsEmpty() && this.bus_q.IsEmpty() && this.precharge_q.IsEmpty() {\n\t\t\t\tthis.precharge_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServiceActivationQ() {\n\tif !this.activation_q.IsEmpty() {\n\t\tmemory_command, cycle := this.activation_q.Front(0)\n\n\t\tif cycle == this.t_ras-this.t_rcd {\n\t\t\tif this.row_address != nil {\n\t\t\t\terr := errors.New(\"row buffer is not precharged\")\n\t\t\t\tpanic(err)\n\t\t\t} else if memory_command.Address()%this.wordline_size != 0 {\n\t\t\t\terr := errors.New(\"memory command is not aligned with wordline size\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.row_address = new(int64)\n\t\t\t*this.row_address = memory_command.Address()\n\n\t\t\tthis.row_buffer = this.ReadFromMram()\n\t\t}\n\t}\n\n\tif this.activation_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.activation_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_activations\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceIoQ() {\n\tif this.io_q.CanPop(1) && this.bus_q.CanPush(1) {\n\t\tmemory_command := this.io_q.Pop()\n\t\tthis.bus_q.Push(memory_command)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceBusQ() {\n\tif this.bus_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.bus_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == READ {\n\t\t\tbyte_stream := this.ReadFromRowBuffer(memory_command.Address(), memory_command.Size())\n\t\t\tmemory_command.SetByteStream(byte_stream)\n\n\t\t\tthis.stat_factory.Increment(\"num_reads\", 1)\n\t\t\tthis.stat_factory.Increment(\"read_bytes\", memory_command.Size())\n\t\t} else if memory_operation == WRITE {\n\t\t\tthis.WriteToRowBuffer(memory_command.Address(), memory_command.Size(), memory_command.ByteStream())\n\n\t\t\tthis.stat_factory.Increment(\"num_writes\", 1)\n\t\t\tthis.stat_factory.Increment(\"write_bytes\", memory_command.Size())\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServicePrechargeQ() {\n\tif this.precharge_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.precharge_q.Pop()\n\n\t\taddress := memory_command.Address()\n\t\tif address%this.wordline_size != 0 {\n\t\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\t\tpanic(err)\n\t\t} else if address != *this.row_address {\n\t\t\terr := errors.New(\"address != row address\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.WriteToMram()\n\t\tthis.row_address = nil\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_precharges\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ReadFromMram() *encoding.ByteStream {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\treturn this.mram.Read(*this.row_address)\n}\n\nfunc (this *RowBuffer) ReadFromRowBuffer(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.row_buffer.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *RowBuffer) WriteToMram() {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram.Write(*this.row_address, this.row_buffer)\n}\n\nfunc (this *RowBuffer) WriteToRowBuffer(\n\taddress int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.row_buffer.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *RowBuffer) Index(address int64) int {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if address < *this.row_address {\n\t\terr := errors.New(\"address < row address\")\n\t\tpanic(err)\n\t} else if address >= *this.row_address+this.wordline_size {\n\t\terr := errors.New(\"address >= row address + wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - *this.row_address)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/dram/wordline.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Wordline struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Wordline) Init(address int64, size int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_size := int64(config_loader.MramDataWidth() / 8)\n\n\tif address < 0 {\n\t\terr := errors.New(\"address < 0\")\n\t\tpanic(err)\n\t} else if size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t} else if size%mram_data_size != 0 {\n\t\terr := errors.New(\"size is not aligned with MRAM data size\")\n\t\tpanic(err)\n\t}\n\n\tthis.address = address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Wordline) Fini() {\n}\n\nfunc (this *Wordline) Read() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < this.byte_stream.Size(); i++ {\n\t\tbyte_stream.Append(this.byte_stream.Get(int(i)))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Wordline) Write(byte_stream *encoding.ByteStream) {\n\tif this.size != byte_stream.Size() {\n\t\terr := errors.New(\"wordline's size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/alu.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Alu struct {\n}\n\nfunc (this *Alu) Init() {\n}\n\nfunc (this *Alu) Fini() {\n}\n\nfunc (this *Alu) AtomicAddressHash(operand1 int64, operand2 int64) int64 {\n\tif operand1+operand2 >= 256 {\n\t\terr := errors.New(\"operand1 + operand2 >= 256\")\n\t\tpanic(err)\n\t}\n\n\tresult, _, _ := this.Add(operand1, operand2)\n\treturn result\n}\n\nfunc (this *Alu) Add(operand1 int64, operand2 int64) (int64, bool, bool) {\n\treturn this.Addc(operand1, operand2, false)\n}\n\nfunc (this *Alu) Addc(operand1 int64, operand2 int64, carry_flag bool) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tif carry_flag {\n\t\tresult = word1.Value(word.UNSIGNED) + word2.Value(word.UNSIGNED) + 1\n\t} else {\n\t\tresult = word1.Value(word.UNSIGNED) + word2.Value(word.UNSIGNED)\n\t}\n\n\tmax_unsigned_value := this.Pow2(mram_data_width) - 1\n\n\tvar carry bool\n\tif result > max_unsigned_value {\n\t\tresult %= this.Pow2(mram_data_width)\n\t\tcarry = true\n\t} else {\n\t\tcarry = false\n\t}\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result, carry, overflow\n}\n\nfunc (this *Alu) Sub(operand1 int64, operand2 int64) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tvar carry bool\n\tif word1.Value(word.UNSIGNED) >= word2.Value(word.UNSIGNED) {\n\t\tresult = word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED)\n\t\tcarry = false\n\t} else {\n\t\tresult = this.Pow2(mram_data_width) + word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED)\n\t\tcarry = true\n\t}\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result, carry, overflow\n}\n\nfunc (this *Alu) Subc(operand1 int64, operand2 int64, carry_flag bool) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tvar carry bool\n\tif carry_flag {\n\t\tif word1.Value(word.UNSIGNED)+1 >= word2.Value(word.UNSIGNED) {\n\t\t\tresult = word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED) - 1\n\t\t\tcarry = false\n\t\t} else {\n\t\t\tresult = this.Pow2(mram_data_width) + word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED) - 1\n\t\t\tcarry = true\n\t\t}\n\t} else {\n\t\tif word1.Value(word.UNSIGNED) >= word2.Value(word.UNSIGNED) {\n\t\t\tresult = word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED)\n\t\t\tcarry = false\n\t\t} else {\n\t\t\tresult = this.Pow2(mram_data_width) + word1.Value(word.UNSIGNED) - word2.Value(word.UNSIGNED)\n\t\t\tcarry = true\n\t\t}\n\t}\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result, carry, overflow\n}\n\nfunc (this *Alu) And(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Nand(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Andn(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Or(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Nor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Orn(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Xor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else if word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Nxor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else if word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Asr(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\tmsb := word_.SignBit()\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tif msb {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Lsl(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) LslAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Lsl(operand2, shift))\n}\n\nfunc (this *Alu) LslSub(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Sub(operand1, this.Lsl(operand2, shift))\n}\n\nfunc (this *Alu) Lsl1(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Lsl1x(operand int64, shift int64) int64 {\n\terr := errors.New(\"lsl1x is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Lslx(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tif shift_value == 0 {\n\t\treturn 0\n\t} else {\n\t\treturn this.Lsr(operand, int64(mram_data_width)-shift_value)\n\t}\n}\n\nfunc (this *Alu) Lsr(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) LsrAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Lsr(operand2, shift))\n}\n\nfunc (this *Alu) Lsr1(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Lsr1x(operand int64, shift int64) int64 {\n\terr := errors.New(\"lsr1x is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Lsrx(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tif shift_value == 0 {\n\t\treturn 0\n\t} else {\n\t\treturn this.Lsl(operand, int64(mram_data_width)-shift_value)\n\t}\n}\n\nfunc (this *Alu) Rol(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tif word_.Bit(i + mram_data_width - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) RolAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Rol(operand2, shift))\n}\n\nfunc (this *Alu) Ror(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(word.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(word.UNSIGNED, 0, 5)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tif word_.Bit((i + int(shift_value)) % mram_data_width) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Cao(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tones := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(i) {\n\t\t\tones++\n\t\t}\n\t}\n\treturn ones\n}\n\nfunc (this *Alu) Clo(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tleading_ones := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(mram_data_width - 1 - i) {\n\t\t\tleading_ones++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_ones\n}\n\nfunc (this *Alu) Cls(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\tmsb := word_.SignBit()\n\n\tleading_sign_bits := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(mram_data_width-1-i) == msb {\n\t\t\tleading_sign_bits++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_sign_bits\n}\n\nfunc (this *Alu) Clz(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tleading_zeros := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word_.Bit(mram_data_width - 1 - i) {\n\t\t\tleading_zeros++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_zeros\n}\n\nfunc (this *Alu) Cmpb4(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < 4; i++ {\n\t\tbegin := 8 * i\n\t\tend := 8 * (i + 1)\n\n\t\tbyte1 := word1.BitSlice(word.UNSIGNED, begin, end)\n\t\tbyte2 := word2.BitSlice(word.UNSIGNED, begin, end)\n\n\t\tif byte1 == byte2 {\n\t\t\tresult_word.SetBitSlice(begin, end, 1)\n\t\t} else {\n\t\t\tresult_word.SetBitSlice(begin, end, 0)\n\t\t}\n\t}\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Extsb(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(word.SIGNED, 0, 8)\n}\n\nfunc (this *Alu) Extsh(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(word.SIGNED, 0, 16)\n}\n\nfunc (this *Alu) Extub(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(word.UNSIGNED, 0, 8)\n}\n\nfunc (this *Alu) Extuh(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(word.UNSIGNED, 0, 16)\n}\n\nfunc (this *Alu) MulShSh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 8, 16) * word2.BitSlice(word.SIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulShSl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 8, 16) * word2.BitSlice(word.SIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulShUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 8, 16) * word2.BitSlice(word.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulShUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 8, 16) * word2.BitSlice(word.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulSlSh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 0, 8) * word2.BitSlice(word.SIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulSlSl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 0, 8) * word2.BitSlice(word.SIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulSlUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 0, 8) * word2.BitSlice(word.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulSlUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.SIGNED, 0, 8) * word2.BitSlice(word.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.SIGNED)\n}\n\nfunc (this *Alu) MulUhUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.UNSIGNED, 8, 16) * word2.BitSlice(word.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) MulUhUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.UNSIGNED, 8, 16) * word2.BitSlice(word.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) MulUlUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.UNSIGNED, 0, 8) * word2.BitSlice(word.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) MulUlUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(word.UNSIGNED, 0, 8) * word2.BitSlice(word.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Sats(operand int64) int64 {\n\terr := errors.New(\"sats is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Hash(operand1 int64, operand2 int64) int64 {\n\terr := errors.New(\"hash is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) SignedExtension(operand int64) (int64, int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\teven_word := new(word.Word)\n\teven_word.Init(mram_data_width)\n\tif word_.SignBit() {\n\t\teven_word.SetValue(-1)\n\t}\n\n\todd_word := new(word.Word)\n\todd_word.Init(mram_data_width)\n\todd_word.SetValue(word_.Value(word.UNSIGNED))\n\n\treturn even_word.Value(word.UNSIGNED), odd_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) UnsignedExtension(operand int64) (int64, int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(word.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\teven_word := new(word.Word)\n\teven_word.Init(mram_data_width)\n\teven_word.SetValue(0)\n\n\todd_word := new(word.Word)\n\todd_word.Init(mram_data_width)\n\todd_word.SetValue(word_.Value(word.UNSIGNED))\n\n\treturn even_word.Value(word.UNSIGNED), odd_word.Value(word.UNSIGNED)\n}\n\nfunc (this *Alu) Pow2(exponent int) int64 {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/cycle_rule.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype CycleRule struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tinput_q *InstructionQ\n\twait_q  *InstructionQ\n\tready_q *InstructionQ\n\n\tscoreboard map[*instruction.Instruction]*Thread\n\treg_sets   []*RegSet\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *CycleRule) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tnum_tasklets := int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.input_q = new(InstructionQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(1, 0)\n\n\tthis.ready_q = new(InstructionQ)\n\tthis.ready_q.Init(1, 0)\n\n\tthis.scoreboard = make(map[*instruction.Instruction]*Thread, 0)\n\n\tfor i := 0; i < num_tasklets; i++ {\n\t\treg_set := new(RegSet)\n\t\treg_set.Init(i)\n\n\t\tthis.reg_sets = append(this.reg_sets, reg_set)\n\t}\n\n\tname := fmt.Sprintf(\"CycleRule[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *CycleRule) Fini() {\n\tthis.input_q.Fini()\n\tthis.wait_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *CycleRule) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *CycleRule) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.wait_q.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *CycleRule) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *CycleRule) Push(instruction_ *instruction.Instruction, thread *Thread) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"cycle rule cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(instruction_)\n\tthis.scoreboard[instruction_] = thread\n}\n\nfunc (this *CycleRule) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *CycleRule) Pop() *instruction.Instruction {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"cycle rule cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tinstruction_ := this.ready_q.Pop()\n\n\tdelete(this.scoreboard, instruction_)\n\treturn instruction_\n}\n\nfunc (this *CycleRule) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceWaitQ()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *CycleRule) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) {\n\t\tinstruction_ := this.input_q.Pop()\n\n\t\tthread_id := this.scoreboard[instruction_].ThreadId()\n\t\tthis.reg_sets[thread_id].CollectReadGpRegs(instruction_)\n\n\t\textra_cycles := this.CalculateExtraCycles(instruction_)\n\n\t\tthis.wait_q.PushWithTimer(instruction_, extra_cycles)\n\n\t\tthis.stat_factory.Increment(\"cycle_rule\", extra_cycles)\n\t}\n}\n\nfunc (this *CycleRule) ServiceWaitQ() {\n\tif this.wait_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tinstruction_ := this.wait_q.Pop()\n\t\tthis.ready_q.Push(instruction_)\n\n\t\tthread_id := this.scoreboard[instruction_].ThreadId()\n\t\tthis.reg_sets[thread_id].Clear()\n\t\tthis.reg_sets[thread_id].CollectWriteGpRegs(instruction_)\n\t}\n}\n\nfunc (this *CycleRule) CalculateExtraCycles(instruction_ *instruction.Instruction) int64 {\n\tthread_id := this.scoreboard[instruction_].ThreadId()\n\n\treg_set := this.reg_sets[thread_id]\n\n\tif reg_set.ThreadId() != thread_id {\n\t\terr := errors.New(\"reg set's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\treg_indicies := reg_set.RegIndices()\n\n\teven_counter := 0\n\todd_counter := 0\n\tfor reg_index, _ := range reg_indicies {\n\t\tif reg_index%2 == 0 {\n\t\t\teven_counter++\n\t\t} else {\n\t\t\todd_counter++\n\t\t}\n\t}\n\n\treturn int64(even_counter/2 + odd_counter/2)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/dma.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu/dram\"\n\t\"uPIMulator/src/simulator/dpu/sram\"\n)\n\ntype Dma struct {\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\toperand_collector *OperandCollector\n\tmemory_controller *dram.MemoryController\n\n\tinput_q *dram.DmaCommandQ\n\tready_q *dram.DmaCommandQ\n}\n\nfunc (this *Dma) Init() {\n\tthis.atomic = nil\n\tthis.iram = nil\n\tthis.operand_collector = nil\n\tthis.memory_controller = nil\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmax_num_tasklets := config_loader.MaxNumTasklets()\n\n\tthis.input_q = new(dram.DmaCommandQ)\n\tthis.input_q.Init(max_num_tasklets, 0)\n\n\tthis.ready_q = new(dram.DmaCommandQ)\n\tthis.ready_q.Init(max_num_tasklets, 0)\n}\n\nfunc (this *Dma) Fini() {\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Dma) ConnectAtomic(atomic *sram.Atomic) {\n\tif this.atomic != nil {\n\t\terr := errors.New(\"atomic is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.atomic = atomic\n}\n\nfunc (this *Dma) ConnectIram(iram *sram.Iram) {\n\tif this.iram != nil {\n\t\terr := errors.New(\"IRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram = iram\n}\n\nfunc (this *Dma) ConnectOperandCollector(operand_collector *OperandCollector) {\n\tif this.operand_collector != nil {\n\t\terr := errors.New(\"operand collector is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand_collector = operand_collector\n}\n\nfunc (this *Dma) ConnectMemoryController(memory_controller *dram.MemoryController) {\n\tif this.memory_controller != nil {\n\t\terr := errors.New(\"memory controller is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_controller = memory_controller\n}\n\nfunc (this *Dma) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *Dma) TransferToAtomic(address int64, byte_stream *encoding.ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tif byte_stream.Get(int(i)) != 0 {\n\t\t\terr := errors.New(\"atomic byte is not set to 0\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Dma) TransferToIram(address int64, byte_stream *encoding.ByteStream) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_offset := config_loader.IramOffset()\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif address != this.iram.Address() {\n\t\terr := errors.New(\"address != IRAM's address\")\n\t\tpanic(err)\n\t} else if byte_stream.Size()%iram_data_size != 0 {\n\t\terr := errors.New(\"byte stream's size is not aligned with IRAM data size\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram.Write(iram_offset, byte_stream)\n}\n\nfunc (this *Dma) TransferFromWram(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tvalue := this.operand_collector.Lbu(address + i)\n\t\tbyte_stream.Append(uint8(value))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Dma) TransferToWram(address int64, byte_stream *encoding.ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tthis.operand_collector.Sb(address+i, int64(value))\n\t}\n}\n\nfunc (this *Dma) TransferFromMram(address int64, size int64) *encoding.ByteStream {\n\tthis.memory_controller.Flush()\n\treturn this.memory_controller.Read(address, size)\n}\n\nfunc (this *Dma) TransferToMram(address int64, byte_stream *encoding.ByteStream) {\n\tthis.memory_controller.Write(address, byte_stream.Size(), byte_stream)\n}\n\nfunc (this *Dma) TransferFromWramToMram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := this.TransferFromWram(wram_address, size)\n\n\tdma_command := new(dram.DmaCommand)\n\tdma_command.InitWriteToMramFromWram(wram_address, mram_address, size, byte_stream, instruction_)\n\n\tthis.Push(dma_command)\n}\n\nfunc (this *Dma) TransferFromMramToWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tdma_command := new(dram.DmaCommand)\n\tdma_command.InitReadFromMramToWram(wram_address, mram_address, size, instruction_)\n\n\tthis.Push(dma_command)\n}\n\nfunc (this *Dma) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Dma) Push(dma_command *dram.DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *Dma) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Dma) Pop() *dram.DmaCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"DMA cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Dma) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n}\n\nfunc (this *Dma) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.memory_controller.CanPush() {\n\t\tdma_command := this.input_q.Pop()\n\t\tthis.memory_controller.Push(dma_command)\n\t}\n}\n\nfunc (this *Dma) ServiceReadyQ() {\n\tif this.memory_controller.CanPop() && this.ready_q.CanPush(1) {\n\t\tdma_command := this.memory_controller.Pop()\n\t\tthis.ready_q.Push(dma_command)\n\n\t\tif dma_command.MemoryOperation() == dram.READ {\n\t\t\twram_address := dma_command.WramAddress()\n\t\t\tmram_address := dma_command.MramAddress()\n\t\t\tsize := dma_command.Size()\n\t\t\tbyte_stream := dma_command.ByteStream(mram_address, size)\n\n\t\t\tthis.TransferToWram(wram_address, byte_stream)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/instruction_q.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n)\n\ntype InstructionQ struct {\n\tsize  int\n\ttimer int64\n\n\tinstructions []*instruction.Instruction\n\tcycles       []int64\n}\n\nfunc (this *InstructionQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.instructions = make([]*instruction.Instruction, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *InstructionQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"instruction queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *InstructionQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *InstructionQ) IsEmpty() bool {\n\treturn len(this.instructions) == 0\n}\n\nfunc (this *InstructionQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.instructions) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *InstructionQ) Push(instruction_ *instruction.Instruction) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"instruction queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.instructions = append(this.instructions, instruction_)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *InstructionQ) PushWithTimer(instruction_ *instruction.Instruction, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"instruction queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.instructions = append(this.instructions, instruction_)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *InstructionQ) CanPop(num_items int) bool {\n\tif len(this.instructions) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *InstructionQ) Pop() *instruction.Instruction {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"instruction queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tinstruction_ := this.instructions[0]\n\n\tthis.instructions = this.instructions[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn instruction_\n}\n\nfunc (this *InstructionQ) Front(pos int) (*instruction.Instruction, int64) {\n\tif this.IsEmpty() {\n\t\terr := errors.New(\"instruction queue is empty\")\n\t\tpanic(err)\n\t}\n\n\treturn this.instructions[pos], this.cycles[pos]\n}\n\nfunc (this *InstructionQ) Remove(pos int) {\n\tthis.instructions = append(this.instructions[:pos], this.instructions[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *InstructionQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/logic.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"math\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu/sram\"\n)\n\ntype Logic struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tnum_channels          int\n\tnum_ranks_per_channel int\n\tnum_dpus_per_rank     int\n\n\tverbose int\n\n\tmin_access_granularity int64\n\n\tthread_scheduler  *ThreadScheduler\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\toperand_collector *OperandCollector\n\tdma               *Dma\n\n\tscoreboard map[*instruction.Instruction]*Thread\n\n\tpipeline   *Pipeline\n\tcycle_rule *CycleRule\n\n\talu    *Alu\n\twait_q *InstructionQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *Logic) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.num_channels = int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.num_ranks_per_channel = int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tthis.num_dpus_per_rank = int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\n\tthis.verbose = int(command_line_parser.IntParameter(\"verbose\"))\n\n\tthis.thread_scheduler = nil\n\tthis.atomic = nil\n\tthis.iram = nil\n\tthis.operand_collector = nil\n\tthis.dma = nil\n\n\tthis.scoreboard = make(map[*instruction.Instruction]*Thread, 0)\n\n\tthis.pipeline = new(Pipeline)\n\tthis.pipeline.Init(command_line_parser)\n\n\tthis.cycle_rule = new(CycleRule)\n\tthis.cycle_rule.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.alu = new(Alu)\n\tthis.alu.Init()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(config_loader.MaxNumTasklets(), 0)\n\n\tname := fmt.Sprintf(\"Logic[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *Logic) Fini() {\n\tthis.pipeline.Fini()\n\tthis.cycle_rule.Fini()\n\n\tthis.alu.Fini()\n\tthis.wait_q.Fini()\n}\n\nfunc (this *Logic) ConnectThreadScheduler(thread_scheduler *ThreadScheduler) {\n\tif this.thread_scheduler != nil {\n\t\terr := errors.New(\"thread scheduler is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_scheduler = thread_scheduler\n}\n\nfunc (this *Logic) ConnectAtomic(atomic *sram.Atomic) {\n\tif this.atomic != nil {\n\t\terr := errors.New(\"atomic is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.atomic = atomic\n}\n\nfunc (this *Logic) ConnectIram(iram *sram.Iram) {\n\tif this.iram != nil {\n\t\terr := errors.New(\"IRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram = iram\n}\n\nfunc (this *Logic) ConnectOperandCollector(operand_collector *OperandCollector) {\n\tif this.operand_collector != nil {\n\t\terr := errors.New(\"operand collector is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand_collector = operand_collector\n}\n\nfunc (this *Logic) ConnectDma(dma *Dma) {\n\tif this.dma != nil {\n\t\terr := errors.New(\"DMA is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma = dma\n}\n\nfunc (this *Logic) CycleRule() *CycleRule {\n\treturn this.cycle_rule\n}\n\nfunc (this *Logic) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *Logic) IsEmpty() bool {\n\treturn this.pipeline.IsEmpty() && this.cycle_rule.IsEmpty() && this.wait_q.IsEmpty()\n}\n\nfunc (this *Logic) Cycle() {\n\tthis.ServiceThreadScheduler()\n\tthis.ServicePipeline()\n\tthis.ServiceCycleRule()\n\tthis.ServiceLogic()\n\tthis.ServiceDma()\n\n\tthis.pipeline.Cycle()\n\tthis.cycle_rule.Cycle()\n\n\tthis.wait_q.Cycle()\n\n\tthis.stat_factory.Increment(\"logic_cycle\", 1)\n}\n\nfunc (this *Logic) ServiceThreadScheduler() {\n\tif this.pipeline.CanPush() && this.cycle_rule.CanPush() && this.wait_q.CanPush(1) {\n\t\tthread := this.thread_scheduler.Schedule()\n\n\t\tif thread != nil {\n\t\t\tpc := thread.RegFile().ReadPcReg()\n\t\t\tinstruction_ := this.iram.Read(pc)\n\n\t\t\tthis.scoreboard[instruction_] = thread\n\n\t\t\tthis.pipeline.Push(instruction_)\n\n\t\t\tif instruction_.Suffix() != instruction.DMA_RRI {\n\t\t\t\tthis.ExecuteInstruction(instruction_)\n\t\t\t} else {\n\t\t\t\tthis.thread_scheduler.Block(thread.ThreadId())\n\t\t\t\tthread.RegFile().IncrementPcReg()\n\t\t\t\tthis.wait_q.Push(instruction_)\n\t\t\t}\n\n\t\t\tthis.stat_factory.Increment(\"num_instructions\", 1)\n\t\t}\n\n\t\tactive_tasklets := fmt.Sprintf(\"active_tasklets_%d\", this.thread_scheduler.NumIssuableThreads())\n\t\tthis.stat_factory.Increment(active_tasklets, 1)\n\t} else {\n\t\tthis.stat_factory.Increment(\"backpressure\", 1)\n\t\tthis.stat_factory.Increment(\"active_tasklets_0\", 1)\n\t}\n}\n\nfunc (this *Logic) ServicePipeline() {\n\tif this.pipeline.CanPop() && this.cycle_rule.CanPush() {\n\t\tinstruction_ := this.pipeline.Pop()\n\t\tthread := this.scoreboard[instruction_]\n\n\t\tif instruction_ != nil {\n\t\t\tthis.cycle_rule.Push(instruction_, thread)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ServiceCycleRule() {\n\tif this.cycle_rule.CanPop() {\n\t\tinstruction_ := this.cycle_rule.Pop()\n\n\t\tif instruction_.Suffix() != instruction.DMA_RRI {\n\t\t\tdelete(this.scoreboard, instruction_)\n\t\t} else {\n\t\t\tthis.ExecuteInstruction(instruction_)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ServiceLogic() {\n}\n\nfunc (this *Logic) ServiceDma() {\n\tif this.dma.CanPop() {\n\t\tdma_command := this.dma.Pop()\n\n\t\thas_waked_up := false\n\t\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.wait_q.Front(i)\n\n\t\t\tif dma_command.Instruction() == instruction_ {\n\t\t\t\tthread := this.scoreboard[instruction_]\n\n\t\t\t\tthis.thread_scheduler.Awake(thread.ThreadId())\n\n\t\t\t\tthis.wait_q.Remove(i)\n\t\t\t\tdelete(this.scoreboard, instruction_)\n\n\t\t\t\thas_waked_up = true\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\n\t\tif !has_waked_up {\n\t\t\terr := errors.New(\"DMA command has not waked up an instruction\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ExecuteInstruction(instruction_ *instruction.Instruction) {\n\tthread := this.scoreboard[instruction_]\n\n\tunique_dpu_id := this.channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + this.rank_id*this.num_dpus_per_rank + this.dpu_id\n\n\tif this.verbose >= 1 {\n\t\tfmt.Printf(\n\t\t\t\"{%d}[%d] %s\\n\",\n\t\t\tunique_dpu_id,\n\t\t\tthread.ThreadId(),\n\t\t\tinstruction_.Stringify(),\n\t\t)\n\t}\n\n\tsuffix := instruction_.Suffix()\n\n\tif suffix == instruction.RICI {\n\t\tthis.ExecuteRici(instruction_)\n\t} else if suffix == instruction.RRI {\n\t\tthis.ExecuteRri(instruction_)\n\t} else if suffix == instruction.RRIC {\n\t\tthis.ExecuteRric(instruction_)\n\t} else if suffix == instruction.RRICI {\n\t\tthis.ExecuteRrici(instruction_)\n\t} else if suffix == instruction.RRIF {\n\t\tthis.ExecuteRrif(instruction_)\n\t} else if suffix == instruction.RRR {\n\t\tthis.ExecuteRrr(instruction_)\n\t} else if suffix == instruction.RRRC {\n\t\tthis.ExecuteRrrc(instruction_)\n\t} else if suffix == instruction.RRRCI {\n\t\tthis.ExecuteRrrci(instruction_)\n\t} else if suffix == instruction.ZRI {\n\t\tthis.ExecuteZri(instruction_)\n\t} else if suffix == instruction.ZRIC {\n\t\tthis.ExecuteZric(instruction_)\n\t} else if suffix == instruction.ZRICI {\n\t\tthis.ExecuteZrici(instruction_)\n\t} else if suffix == instruction.ZRIF {\n\t\tthis.ExecuteZrif(instruction_)\n\t} else if suffix == instruction.ZRR {\n\t\tthis.ExecuteZrr(instruction_)\n\t} else if suffix == instruction.ZRRC {\n\t\tthis.ExecuteZrrc(instruction_)\n\t} else if suffix == instruction.ZRRCI {\n\t\tthis.ExecuteZrrci(instruction_)\n\t} else if suffix == instruction.S_RRI || suffix == instruction.U_RRI {\n\t\tthis.ExecuteSRri(instruction_)\n\t} else if suffix == instruction.S_RRIC || suffix == instruction.U_RRIC {\n\t\tthis.ExecuteSRric(instruction_)\n\t} else if suffix == instruction.S_RRICI || suffix == instruction.U_RRICI {\n\t\tthis.ExecuteSRrici(instruction_)\n\t} else if suffix == instruction.S_RRIF || suffix == instruction.U_RRIF {\n\t\tthis.ExecuteSRrif(instruction_)\n\t} else if suffix == instruction.S_RRR || suffix == instruction.U_RRR {\n\t\tthis.ExecuteSRrr(instruction_)\n\t} else if suffix == instruction.S_RRRC || suffix == instruction.U_RRRC {\n\t\tthis.ExecuteSRrrc(instruction_)\n\t} else if suffix == instruction.S_RRRCI || suffix == instruction.U_RRRCI {\n\t\tthis.ExecuteSRrrci(instruction_)\n\t} else if suffix == instruction.RR {\n\t\tthis.ExecuteRr(instruction_)\n\t} else if suffix == instruction.RRC {\n\t\tthis.ExecuteRrc(instruction_)\n\t} else if suffix == instruction.RRCI {\n\t\tthis.ExecuteRrci(instruction_)\n\t} else if suffix == instruction.ZR {\n\t\tthis.ExecuteZr(instruction_)\n\t} else if suffix == instruction.ZRC {\n\t\tthis.ExecuteZrc(instruction_)\n\t} else if suffix == instruction.ZRCI {\n\t\tthis.ExecuteZrci(instruction_)\n\t} else if suffix == instruction.S_RR || suffix == instruction.U_RR {\n\t\tthis.ExecuteSRr(instruction_)\n\t} else if suffix == instruction.S_RRC || suffix == instruction.U_RRC {\n\t\tthis.ExecuteSRrc(instruction_)\n\t} else if suffix == instruction.S_RRCI || suffix == instruction.U_RRCI {\n\t\tthis.ExecuteSRrci(instruction_)\n\t} else if suffix == instruction.DRDICI {\n\t\tthis.ExecuteDrdici(instruction_)\n\t} else if suffix == instruction.RRRI {\n\t\tthis.ExecuteRrri(instruction_)\n\t} else if suffix == instruction.RRRICI {\n\t\tthis.ExecuteRrrici(instruction_)\n\t} else if suffix == instruction.ZRRI {\n\t\tthis.ExecuteZrri(instruction_)\n\t} else if suffix == instruction.ZRRICI {\n\t\tthis.ExecuteZrrici(instruction_)\n\t} else if suffix == instruction.S_RRRI || suffix == instruction.U_RRRI {\n\t\tthis.ExecuteSRrri(instruction_)\n\t} else if suffix == instruction.S_RRRICI || suffix == instruction.U_RRRICI {\n\t\tthis.ExecuteSRrrici(instruction_)\n\t} else if suffix == instruction.RIR {\n\t\tthis.ExecuteRir(instruction_)\n\t} else if suffix == instruction.RIRC {\n\t\tthis.ExecuteRirc(instruction_)\n\t} else if suffix == instruction.RIRCI {\n\t\tthis.ExecuteRirci(instruction_)\n\t} else if suffix == instruction.ZIR {\n\t\tthis.ExecuteZir(instruction_)\n\t} else if suffix == instruction.ZIRC {\n\t\tthis.ExecuteZirc(instruction_)\n\t} else if suffix == instruction.ZIRCI {\n\t\tthis.ExecuteZirci(instruction_)\n\t} else if suffix == instruction.S_RIRC || suffix == instruction.U_RIRC {\n\t\tthis.ExecuteSRirc(instruction_)\n\t} else if suffix == instruction.S_RIRCI || suffix == instruction.U_RIRCI {\n\t\tthis.ExecuteSRirci(instruction_)\n\t} else if suffix == instruction.R {\n\t\tthis.ExecuteR(instruction_)\n\t} else if suffix == instruction.RCI {\n\t\tthis.ExecuteRci(instruction_)\n\t} else if suffix == instruction.Z {\n\t\tthis.ExecuteZ(instruction_)\n\t} else if suffix == instruction.ZCI {\n\t\tthis.ExecuteZci(instruction_)\n\t} else if suffix == instruction.S_R || suffix == instruction.U_R {\n\t\tthis.ExecuteSR(instruction_)\n\t} else if suffix == instruction.S_RCI || suffix == instruction.U_RCI {\n\t\tthis.ExecuteSRci(instruction_)\n\t} else if suffix == instruction.CI {\n\t\tthis.ExecuteCi(instruction_)\n\t} else if suffix == instruction.I {\n\t\tthis.ExecuteI(instruction_)\n\t} else if suffix == instruction.DDCI {\n\t\tthis.ExecuteDdci(instruction_)\n\t} else if suffix == instruction.ERRI {\n\t\tthis.ExecuteErri(instruction_)\n\t} else if suffix == instruction.S_ERRI || suffix == instruction.U_ERRI {\n\t\tthis.ExecuteSErri(instruction_)\n\t} else if suffix == instruction.EDRI {\n\t\tthis.ExecuteEdri(instruction_)\n\t} else if suffix == instruction.ERII {\n\t\tthis.ExecuteErii(instruction_)\n\t} else if suffix == instruction.ERIR {\n\t\tthis.ExecuteErir(instruction_)\n\t} else if suffix == instruction.ERID {\n\t\tthis.ExecuteErid(instruction_)\n\t} else if suffix == instruction.DMA_RRI {\n\t\tthis.ExecuteDmaRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n\n\tif this.verbose >= 2 {\n\t\tfmt.Println(this.PrintRegFile(thread))\n\t}\n}\n\nfunc (this *Logic) ExecuteRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_acquire_rici_op_code := instruction_.AcquireRiciOpCodes()[op_code]; is_acquire_rici_op_code {\n\t\tthis.ExecuteAcquireRici(instruction_)\n\t} else if _, is_release_rici_op_code := instruction_.ReleaseRiciOpCodes()[op_code]; is_release_rici_op_code {\n\t\tthis.ExecuteReleaseRici(instruction_)\n\t} else if _, is_boot_rici_op_code := instruction_.BootRiciOpCodes()[op_code]; is_boot_rici_op_code {\n\t\tthis.ExecuteBootRici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAcquireRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AcquireRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid acquire RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tatomic_address := this.alu.AtomicAddressHash(ra, imm)\n\n\tcan_acquire := this.atomic.CanAcquire(atomic_address)\n\tif can_acquire {\n\t\tthis.atomic.Acquire(atomic_address, thread.ThreadId())\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tif can_acquire {\n\t\tthis.SetAcquireCc(instruction_, 0)\n\t} else {\n\t\tthis.SetAcquireCc(instruction_, 1)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tif can_acquire {\n\t\tthis.SetFlags(instruction_, 0, false)\n\t} else {\n\t\tthis.SetFlags(instruction_, 1, false)\n\t}\n}\n\nfunc (this *Logic) ExecuteReleaseRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ReleaseRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid release RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tatomic_address := this.alu.AtomicAddressHash(ra, imm)\n\n\tcan_release := this.atomic.CanRelease(atomic_address, thread.ThreadId())\n\tif can_release {\n\t\tthis.atomic.Release(atomic_address, thread.ThreadId())\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tif can_release {\n\t\tthis.SetAcquireCc(instruction_, 0)\n\t} else {\n\t\tthis.SetAcquireCc(instruction_, 1)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tif can_release {\n\t\tthis.SetFlags(instruction_, 0, false)\n\t} else {\n\t\tthis.SetFlags(instruction_, 1, false)\n\t}\n}\n\nfunc (this *Logic) ExecuteBootRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.BootRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid boot RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tthread_id := int(this.alu.AtomicAddressHash(ra, imm))\n\n\tthread.RegFile().ClearConditions()\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.BOOT {\n\t\tcan_boot := this.thread_scheduler.Boot(thread_id)\n\t\tif can_boot {\n\t\t\tthis.SetBootCc(instruction_, ra, 0)\n\t\t\tthis.SetFlags(instruction_, 0, false)\n\t\t} else {\n\t\t\tthis.SetBootCc(instruction_, ra, 1)\n\t\t\tthis.SetFlags(instruction_, 1, false)\n\t\t}\n\t} else if op_code == instruction.RESUME {\n\t\tcan_resume := this.thread_scheduler.Awake(thread_id)\n\t\tif can_resume {\n\t\t\tthis.SetBootCc(instruction_, ra, 0)\n\t\t\tthis.SetFlags(instruction_, 0, false)\n\t\t} else {\n\t\t\tthis.SetBootCc(instruction_, ra, 1)\n\t\t\tthis.SetFlags(instruction_, 1, false)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddRri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrRri(instruction_)\n\t} else if _, is_call_rri_op_code := instruction_.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.ExecuteCallRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteCallRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CallRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid call RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif imm == 0 {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else {\n\t\tresult, carry, _ = this.alu.Add(ra*iram_data_size, imm)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tpc := thread.RegFile().ReadPcReg()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), pc+iram_data_size)\n\n\tthread.RegFile().WritePcReg(result)\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rric_op_code := instruction_.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.ExecuteAddRric(instruction_)\n\t} else if _, is_asrc_rric_op_code := instruction_.AsrRricOpCodes()[op_code]; is_asrc_rric_op_code {\n\t\tthis.ExecuteAsrRric(instruction_)\n\t} else if _, is_sub_rric_op_code := instruction_.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.ExecuteSubRric(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, imm, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddRrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndRrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrRrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubRrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, rb, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tif op_code != instruction.CALL {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\t\tthread.RegFile().IncrementPcReg()\n\t} else {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tpc := thread.RegFile().ReadPcReg()\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), pc+iram_data_size)\n\t\tthread.RegFile().WritePcReg(result)\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrc_op_code := instruction_.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tthis.ExecuteAddRrrc(instruction_)\n\t} else if _, is_rsub_rrrc_op_code := instruction_.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tthis.ExecuteRsubRrrc(instruction_)\n\t} else if _, is_sub_rrrc_op_code := instruction_.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\tthis.ExecuteSubRrrc(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRsubRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, ra, rb, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSubRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, rb, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrci_op_code := instruction_.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tthis.ExecuteAddRrrci(instruction_)\n\t} else if _, is_and_rrrci_op_code := instruction_.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tthis.ExecuteAndRrrci(instruction_)\n\t} else if _, is_asr_rrrci_op_code := instruction_.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tthis.ExecuteAsrRrrci(instruction_)\n\t} else if _, is_mul_rrrci_op_code := instruction_.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tthis.ExecuteMulRrrci(instruction_)\n\t} else if _, is_rsub_rrrci_op_code := instruction_.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tthis.ExecuteRsubRrrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetMulNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRsubRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, overflow = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, rb, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddZri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrZri(instruction_)\n\t} else if _, is_call_rri_op_code := instruction_.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.ExecuteCallZri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteCallZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CallRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid call RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif imm == 0 {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else {\n\t\tresult, carry, _ = this.alu.Add(ra*iram_data_size, imm)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WritePcReg(result)\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rric_op_code := instruction_.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.ExecuteAddZric(instruction_)\n\t} else if _, is_asrc_rric_op_code := instruction_.AsrRricOpCodes()[op_code]; is_asrc_rric_op_code {\n\t\tthis.ExecuteAsrZric(instruction_)\n\t} else if _, is_sub_rric_op_code := instruction_.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.ExecuteSubZric(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, imm, result, carry, overflow)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddZrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndZrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrZrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubZrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIF {\n\t\terr := errors.New(\"suffix is not ZRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRR {\n\t\terr := errors.New(\"suffix is not ZRR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, rb, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tif op_code != instruction.CALL {\n\t\tthread.RegFile().IncrementPcReg()\n\t} else {\n\t\tthread.RegFile().WritePcReg(result)\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrc_op_code := instruction_.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tthis.ExecuteAddZrrc(instruction_)\n\t} else if _, is_rsub_rrrc_op_code := instruction_.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tthis.ExecuteRsubZrrc(instruction_)\n\t} else if _, is_sub_rrrc_op_code := instruction_.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\tthis.ExecuteSubZrrc(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRsubZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, ra, rb, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSubZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, rb, result, carry, overflow)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrci_op_code := instruction_.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tthis.ExecuteAddZrrci(instruction_)\n\t} else if _, is_and_rrrci_op_code := instruction_.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tthis.ExecuteAndZrrci(instruction_)\n\t} else if _, is_asr_rrrci_op_code := instruction_.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tthis.ExecuteAsrZrrci(instruction_)\n\t} else if _, is_mul_rrrci_op_code := instruction_.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tthis.ExecuteMulZrrci(instruction_)\n\t} else if _, is_rsub_rrrci_op_code := instruction_.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tthis.ExecuteRsubZrrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetMulNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRsubZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, overflow = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, rb, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddSRri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrSRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRric(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRric is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddSRrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndSRrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrSRrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubSRrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRIF && instruction_.Suffix() != instruction.U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRIF {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRIF {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrr(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrr is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_cao_rrci_op_code := instruction_.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tthis.ExecuteCaoRrci(instruction_)\n\t} else if _, is_extsb_rrci_op_code := instruction_.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tthis.ExecuteExtsbRrci(instruction_)\n\t} else if _, is_time_cfg_rrci_op_code := instruction_.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\tthis.ExecuteTimeCfgRrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteCaoRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CaoRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid cao RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetCountNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteExtsbRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ExtsbRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid extsb RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteTimeCfgRrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteTimeCfgRrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteZr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteZrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_cao_rrci_op_code := instruction_.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tthis.ExecuteCaoZrci(instruction_)\n\t} else if _, is_extsb_rrci_op_code := instruction_.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tthis.ExecuteExtsbZrci(instruction_)\n\t} else if _, is_time_cfg_rrci_op_code := instruction_.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\tthis.ExecuteTimeCfgZrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteCaoZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CaoRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid cao RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetCountNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteExtsbZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ExtsbRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid extsb RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteTimeCfgZrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteTimeCfgZrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRr(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRr is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_div_step_drdici_op_code := instruction_.DivStepDrdiciOpCodes()[op_code]; is_div_step_drdici_op_code {\n\t\tthis.ExecuteDivStepDrdici(instruction_)\n\t} else if _, is_mul_step_drdici_op_code := instruction_.MulStepDrdiciOpCodes()[op_code]; is_mul_step_drdici_op_code {\n\t\tthis.ExecuteMulStepDrdici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteDivStepDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DivStepDrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid div_step DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), word.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tdbo_word := new(word.Word)\n\tdbo_word.Init(mram_data_width)\n\tdbo_word.SetValue(dbo)\n\n\tra_shift_value := this.alu.Lsl(ra, imm)\n\tra_shift_word := new(word.Word)\n\tra_shift_word.Init(mram_data_width)\n\tra_shift_word.SetValue(ra_shift_value)\n\n\tresult, _, _ := this.alu.Sub(dbo, ra_shift_value)\n\n\tvar dce int64\n\tvar dco int64\n\tif dbo_word.Value(word.UNSIGNED) >= ra_shift_word.Value(word.UNSIGNED) {\n\t\tdce = this.alu.Lsl1(dbe, 1)\n\t\tdco = result\n\t} else {\n\t\tdce = this.alu.Lsl(dbe, 1)\n\t\tdco = thread.RegFile().ReadGpReg(instruction_.Dc().OddRegDescriptor(), word.SIGNED)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivCc(instruction_, ra)\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dce)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dco)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulStepDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulStepDrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul_step DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), word.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tresult1 := this.alu.Lsr(dbe, 1)\n\tresult2, _, _ := this.alu.Sub(this.alu.And(dbe, 1), 1)\n\n\tvar dco int64\n\tif result2 == 0 {\n\t\tdco, _, _ = this.alu.Add(dbo, this.alu.Lsl(ra, imm))\n\t} else {\n\t\tdco = thread.RegFile().ReadGpReg(instruction_.Dc().OddRegDescriptor(), word.SIGNED)\n\t}\n\n\tdce := this.alu.Lsr(dbe, 1)\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetBootCc(instruction_, ra, result1)\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dce)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dco)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result1, false)\n}\n\nfunc (this *Logic) ExecuteRrri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivNzCc(instruction_, ra)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivNzCc(instruction_, ra)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrici(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrici is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRirc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RircOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, imm, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRirci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, imm, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZirc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RircOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, imm, ra, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZirci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, imm, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRirc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRirc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRirci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRirci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteR(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteR is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteRci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteZ(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ROpCodes()[instruction_.OpCode()]; !found &&\n\t\tinstruction_.OpCode() != instruction.NOP {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.Z {\n\t\terr := errors.New(\"suffix is not Z\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteZci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteZci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSR(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSR is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteCi(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CiOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tthis.thread_scheduler.Sleep(thread.ThreadId())\n\n\tthread.RegFile().ClearConditions()\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteI(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteI is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteDdci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_movd_ddci_op_code := instruction_.MovdDdciOpCodes()[op_code]; is_movd_ddci_op_code {\n\t\tthis.ExecuteMovdDdci(instruction_)\n\t} else if _, is_swapd_ddci_op_code := instruction_.SwapdDdciOpCodes()[op_code]; is_swapd_ddci_op_code {\n\t\tthis.ExecuteSwapdDdciRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteMovdDdci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MovdDdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid movd DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), word.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), word.SIGNED)\n\n\tthread.RegFile().ClearConditions()\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dbe)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dbo)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteSwapdDdciRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SwapdDdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid movd DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), word.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), word.SIGNED)\n\n\tthread.RegFile().ClearConditions()\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dbo)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dbe)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteErri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ErriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\toff := instruction_.Off().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LBS {\n\t\tresult = this.operand_collector.Lbs(address)\n\t} else if op_code == instruction.LBU {\n\t\tresult = this.operand_collector.Lbu(address)\n\t} else if op_code == instruction.LHS {\n\t\tresult = this.operand_collector.Lhs(address)\n\t} else if op_code == instruction.LHU {\n\t\tresult = this.operand_collector.Lhu(address)\n\t} else if op_code == instruction.LW {\n\t\tresult = this.operand_collector.Lw(address)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteSErri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSErri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteEdri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EdriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\toff := instruction_.Off().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tvar even int64\n\tvar odd int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LD {\n\t\teven, odd = this.operand_collector.Ld(address)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErii(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EriiOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\toff := instruction_.Off().Value()\n\timm := instruction_.Imm().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SB {\n\t\tthis.operand_collector.Sb(address, imm)\n\t} else if op_code == instruction.SB_ID {\n\t\tthis.operand_collector.Sb(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SH {\n\t\tthis.operand_collector.Sh(address, imm)\n\t} else if op_code == instruction.SH_ID {\n\t\tthis.operand_collector.Sh(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SW {\n\t\tthis.operand_collector.Sw(address, imm)\n\t} else if op_code == instruction.SW_ID {\n\t\tthis.operand_collector.Sw(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SD {\n\t\teven, odd := this.alu.UnsignedExtension(imm)\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else if op_code == instruction.SD_ID {\n\t\teven, odd := this.alu.UnsignedExtension(this.alu.Or(int64(thread.ThreadId()), imm))\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ErirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\toff := instruction_.Off().Value()\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\trb_word := new(word.Word)\n\trb_word.Init(config_loader.MramDataWidth())\n\trb_word.SetValue(rb)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SB {\n\t\tthis.operand_collector.Sb(address, rb_word.BitSlice(word.UNSIGNED, 0, 8))\n\t} else if op_code == instruction.SH {\n\t\tthis.operand_collector.Sh(address, rb_word.BitSlice(word.UNSIGNED, 0, 16))\n\t} else if op_code == instruction.SW {\n\t\tthis.operand_collector.Sw(address, rb_word.BitSlice(word.UNSIGNED, 0, 32))\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErid(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EridOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\toff := instruction_.Off().Value()\n\teven, odd := thread.RegFile().ReadPairReg(instruction_.Db(), word.SIGNED)\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SD {\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_ldma_dma_rri_op_code := instruction_.LdmaDmaRriOpCodes()[op_code]; is_ldma_dma_rri_op_code {\n\t\tthis.ExecuteLdmaDmaRri(instruction_)\n\t} else if _, is_ldmai_dma_rri_op_code := instruction_.LdmaiDmaRriOpCodes()[op_code]; is_ldmai_dma_rri_op_code {\n\t\tthis.ExecuteLdmaiDmaRri(instruction_)\n\t} else if _, is_sdma_dma_rri_op_code := instruction_.SdmaDmaRriOpCodes()[op_code]; is_sdma_dma_rri_op_code {\n\t\tthis.ExecuteSdmaDmaRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteLdmaDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.LdmaDmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ldma DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_end_address := config_loader.WramOffset() + config_loader.WramSize()\n\twram_end_address_width := int(math.Floor(math.Log2(float64(wram_end_address))) + 1)\n\twram_mask := this.Pow2(wram_end_address_width) - 1\n\twram_address := this.alu.And(ra, wram_mask)\n\n\tmram_end_address := config_loader.MramOffset() + config_loader.MramSize()\n\tmram_end_address_width := int(math.Floor(math.Log2(float64(mram_end_address))) + 1)\n\tmram_mask := this.Pow2(mram_end_address_width) - 1\n\tmram_address := this.alu.And(rb, mram_mask)\n\n\tsize := (1 + this.alu.And(imm+this.alu.And(this.alu.Lsr(ra, 24), 255), 255)) * this.min_access_granularity\n\n\tthis.dma.TransferFromMramToWram(wram_address, mram_address, size, instruction_)\n\n\tthread.RegFile().ClearConditions()\n}\n\nfunc (this *Logic) ExecuteLdmaiDmaRri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteLdmaiDmaRri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSdmaDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SdmaDmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sdma DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), word.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), word.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_end_address := config_loader.WramOffset() + config_loader.WramSize()\n\twram_end_address_width := int(math.Floor(math.Log2(float64(wram_end_address))) + 1)\n\twram_mask := this.Pow2(wram_end_address_width) - 1\n\twram_address := this.alu.And(ra, wram_mask)\n\n\tmram_end_address := config_loader.MramOffset() + config_loader.MramSize()\n\tmram_end_address_width := int(math.Floor(math.Log2(float64(mram_end_address))) + 1)\n\tmram_mask := this.Pow2(mram_end_address_width) - 1\n\tmram_address := this.alu.And(rb, mram_mask)\n\n\tsize := (1 + this.alu.And(imm+this.alu.And(this.alu.Lsr(ra, 24), 255), 255)) * this.min_access_granularity\n\n\tthis.dma.TransferFromWramToMram(wram_address, mram_address, size, instruction_)\n\n\tthread.RegFile().ClearConditions()\n}\n\nfunc (this *Logic) SetAcquireCc(instruction_ *instruction.Instruction, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n}\n\nfunc (this *Logic) SetAddNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tresult_word := new(word.Word)\n\tresult_word.Init(config_loader.MramDataWidth())\n\tresult_word.SetValue(result)\n\n\tif result_word.Bit(6) {\n\t\tthread.RegFile().SetCondition(cc.NC5)\n\t}\n\n\tif result_word.Bit(7) {\n\t\tthread.RegFile().SetCondition(cc.NC6)\n\t}\n\n\tif result_word.Bit(8) {\n\t\tthread.RegFile().SetCondition(cc.NC7)\n\t}\n\n\tif result_word.Bit(9) {\n\t\tthread.RegFile().SetCondition(cc.NC8)\n\t}\n\n\tif result_word.Bit(10) {\n\t\tthread.RegFile().SetCondition(cc.NC9)\n\t}\n\n\tif result_word.Bit(11) {\n\t\tthread.RegFile().SetCondition(cc.NC10)\n\t}\n\n\tif result_word.Bit(12) {\n\t\tthread.RegFile().SetCondition(cc.NC11)\n\t}\n\n\tif result_word.Bit(13) {\n\t\tthread.RegFile().SetCondition(cc.NC12)\n\t}\n\n\tif result_word.Bit(14) {\n\t\tthread.RegFile().SetCondition(cc.NC13)\n\t}\n\n\tif result_word.Bit(15) {\n\t\tthread.RegFile().SetCondition(cc.NC14)\n\t}\n}\n\nfunc (this *Logic) SetBootCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetCountNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif result == int64(config_loader.MramDataWidth()) {\n\t\tthread.RegFile().SetCondition(cc.MAX)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NMAX)\n\t}\n}\n\nfunc (this *Logic) SetDivCc(instruction_ *instruction.Instruction, operand1 int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetDivNzCc(instruction_ *instruction.Instruction, operand1 int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetExtSubSetCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tif word1.Value(word.UNSIGNED) < word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) <= word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LEU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) > word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) >= word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GEU)\n\t}\n\n\tif word1.Value(word.SIGNED) < word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTS)\n\t}\n\n\tif word1.Value(word.SIGNED) <= word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LES)\n\t}\n\n\tif word1.Value(word.SIGNED) > word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTS)\n\t}\n\n\tif word1.Value(word.SIGNED) >= word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GES)\n\t}\n\n\tif carry || thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XLEU)\n\t}\n\n\tif carry || !thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XGTU)\n\t}\n\n\tif thread.RegFile().ReadFlagReg(instruction.ZERO) && (result < 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XLES)\n\t}\n\n\tif !thread.RegFile().ReadFlagReg(instruction.ZERO) && (result >= 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XGTS)\n\t}\n}\n\nfunc (this *Logic) SetImmShiftNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif result%2 == 0 {\n\t\tthread.RegFile().SetCondition(cc.E)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.O)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1%2 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SE)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SO)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetLogNzCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetLogSetCc(instruction_ *instruction.Instruction, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n}\n\nfunc (this *Logic) SetMulNzCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tif result < 256 {\n\t\tthread.RegFile().SetCondition(cc.SMALL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.LARGE)\n\t}\n}\n\nfunc (this *Logic) SetSubNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(word.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(word.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tif word1.Value(word.UNSIGNED) < word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) <= word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LEU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) > word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTU)\n\t}\n\n\tif word1.Value(word.UNSIGNED) >= word2.Value(word.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GEU)\n\t}\n\n\tif word1.Value(word.SIGNED) < word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTS)\n\t}\n\n\tif word1.Value(word.SIGNED) <= word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LES)\n\t}\n\n\tif word1.Value(word.SIGNED) > word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTS)\n\t}\n\n\tif word1.Value(word.SIGNED) >= word2.Value(word.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GES)\n\t}\n\n\tif carry || thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XLEU)\n\t}\n\n\tif carry || !thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XGTU)\n\t}\n\n\tif thread.RegFile().ReadFlagReg(instruction.ZERO) && (result < 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XLES)\n\t}\n\n\tif !thread.RegFile().ReadFlagReg(instruction.ZERO) && (result >= 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XGTS)\n\t}\n}\n\nfunc (this *Logic) SetSubSetCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n}\n\nfunc (this *Logic) SetFlags(instruction_ *instruction.Instruction, result int64, carry bool) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetFlag(instruction.ZERO)\n\t} else {\n\t\tthread.RegFile().ClearFlag(instruction.ZERO)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetFlag(instruction.CARRY)\n\t} else {\n\t\tthread.RegFile().ClearFlag(instruction.CARRY)\n\t}\n}\n\nfunc (this *Logic) Pow2(exponent int) int64 {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n\nfunc (this *Logic) PrintRegFile(thread *Thread) string {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tlines := \"\"\n\tfor i := 0; i < config_loader.NumGpRegisters(); i++ {\n\t\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\t\tgp_reg_descriptor.Init(i)\n\n\t\tlines += fmt.Sprintf(\n\t\t\t\"r%d: %d\\n\",\n\t\t\ti,\n\t\t\tthread.RegFile().ReadGpReg(gp_reg_descriptor, word.SIGNED),\n\t\t)\n\t}\n\treturn lines\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/operand_collector.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/simulator/dpu/sram\"\n)\n\ntype OperandCollector struct {\n\twram *sram.Wram\n}\n\nfunc (this *OperandCollector) Init() {\n\tthis.wram = nil\n}\n\nfunc (this *OperandCollector) Fini() {\n}\n\nfunc (this *OperandCollector) ConnectWram(wram *sram.Wram) {\n\tif this.wram != nil {\n\t\terr := errors.New(\"wram is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.wram = wram\n}\n\nfunc (this *OperandCollector) Lbs(address int64) int64 {\n\tbyte_stream := this.wram.Read(address, 1)\n\n\tvalue := int64(byte_stream.Get(0))\n\n\tword_ := new(word.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\treturn word_.Value(word.SIGNED)\n}\n\nfunc (this *OperandCollector) Lbu(address int64) int64 {\n\tbyte_stream := this.wram.Read(address, 1)\n\n\tvalue := int64(byte_stream.Get(0))\n\n\tword_ := new(word.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\treturn word_.Value(word.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Lhs(address int64) int64 {\n\tword_ := new(word.Word)\n\tword_.Init(16)\n\tword_.SetBitSlice(0, 8, this.Lbs(address))\n\tword_.SetBitSlice(8, 16, this.Lbs(address+1))\n\treturn word_.Value(word.SIGNED)\n}\n\nfunc (this *OperandCollector) Lhu(address int64) int64 {\n\tword_ := new(word.Word)\n\tword_.Init(16)\n\tword_.SetBitSlice(0, 8, this.Lbu(address))\n\tword_.SetBitSlice(8, 16, this.Lbu(address+1))\n\treturn word_.Value(word.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Lw(address int64) int64 {\n\tword_ := new(word.Word)\n\tword_.Init(32)\n\tword_.SetBitSlice(0, 8, this.Lbu(address))\n\tword_.SetBitSlice(8, 16, this.Lbu(address+1))\n\tword_.SetBitSlice(16, 24, this.Lbu(address+2))\n\tword_.SetBitSlice(24, 32, this.Lbu(address+3))\n\treturn word_.Value(word.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Ld(address int64) (int64, int64) {\n\treturn this.Lw(address + 4), this.Lw(address)\n}\n\nfunc (this *OperandCollector) Sb(address int64, value int64) {\n\tword_ := new(word.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\tbyte_stream.Append(uint8(word_.Value(word.UNSIGNED)))\n\n\tthis.wram.Write(address, 1, byte_stream)\n}\n\nfunc (this *OperandCollector) Sh(address int64, value int64) {\n\tword_ := new(word.Word)\n\tword_.Init(16)\n\tword_.SetValue(value)\n\n\tthis.Sb(address, word_.BitSlice(word.UNSIGNED, 0, 8))\n\tthis.Sb(address+1, word_.BitSlice(word.UNSIGNED, 8, 16))\n}\n\nfunc (this *OperandCollector) Sw(address int64, value int64) {\n\tword_ := new(word.Word)\n\tword_.Init(32)\n\tword_.SetValue(value)\n\n\tthis.Sb(address, word_.BitSlice(word.UNSIGNED, 0, 8))\n\tthis.Sb(address+1, word_.BitSlice(word.UNSIGNED, 8, 16))\n\tthis.Sb(address+2, word_.BitSlice(word.UNSIGNED, 16, 24))\n\tthis.Sb(address+3, word_.BitSlice(word.UNSIGNED, 24, 32))\n}\n\nfunc (this *OperandCollector) Sd(address int64, even int64, odd int64) {\n\tthis.Sw(address+4, even)\n\tthis.Sw(address, odd)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/pipeline.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Pipeline struct {\n\tnum_pipeline_stages int\n\n\tinput_q *InstructionQ\n\twait_q  *InstructionQ\n\tready_q *InstructionQ\n}\n\nfunc (this *Pipeline) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.num_pipeline_stages = int(command_line_parser.IntParameter(\"num_pipeline_stages\"))\n\n\tthis.input_q = new(InstructionQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(this.num_pipeline_stages-1, 0)\n\tfor this.wait_q.CanPush(1) {\n\t\tthis.wait_q.Push(nil)\n\t}\n\n\tthis.ready_q = new(InstructionQ)\n\tthis.ready_q.Init(1, 0)\n\tfor this.ready_q.CanPush(1) {\n\t\tthis.ready_q.Push(nil)\n\t}\n}\n\nfunc (this *Pipeline) Fini() {\n\tthis.input_q.Fini()\n\n\tfor this.wait_q.CanPop(1) {\n\t\tif this.wait_q.Pop() != nil {\n\t\t\terr := errors.New(\"wait queue is not empty\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\tthis.wait_q.Fini()\n\n\tfor this.ready_q.CanPop(1) {\n\t\tif this.ready_q.Pop() != nil {\n\t\t\terr := errors.New(\"ready queue is not empty\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Pipeline) IsEmpty() bool {\n\treturn this.IsInputQEmpty() && this.IsWaitQEmpty() && this.IsReadyQEmpty()\n}\n\nfunc (this *Pipeline) IsInputQEmpty() bool {\n\treturn this.input_q.IsEmpty()\n}\n\nfunc (this *Pipeline) IsWaitQEmpty() bool {\n\tif this.wait_q.IsEmpty() {\n\t\treturn true\n\t} else {\n\t\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.wait_q.Front(i)\n\n\t\t\tif instruction_ != nil {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\n\t\treturn true\n\t}\n}\n\nfunc (this *Pipeline) IsReadyQEmpty() bool {\n\tif this.ready_q.IsEmpty() {\n\t\treturn true\n\t} else {\n\t\tfor i := 0; this.ready_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.ready_q.Front(i)\n\n\t\t\tif instruction_ != nil {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *Pipeline) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Pipeline) Push(instruction_ *instruction.Instruction) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"pipeline cannot be pushed\")\n\t\tpanic(err)\n\t} else if instruction_ == nil {\n\t\terr := errors.New(\"instruction == nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(instruction_)\n}\n\nfunc (this *Pipeline) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Pipeline) Pop() *instruction.Instruction {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"pipeline cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Pipeline) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceWaitQ()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Pipeline) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) {\n\t\tinstruction_ := this.input_q.Pop()\n\t\tthis.wait_q.Push(instruction_)\n\t} else if this.wait_q.CanPush(1) {\n\t\tthis.wait_q.Push(nil)\n\t}\n}\n\nfunc (this *Pipeline) ServiceWaitQ() {\n\tif this.wait_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tinstruction_ := this.wait_q.Pop()\n\t\tthis.ready_q.Push(instruction_)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/reg_set.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n)\n\ntype RegSet struct {\n\tthread_id int\n\n\tprev_write_gp_reg_set map[*reg_descriptor.GpRegDescriptor]bool\n\tcur_read_gp_reg_set   map[*reg_descriptor.GpRegDescriptor]bool\n}\n\nfunc (this *RegSet) Init(thread_id int) {\n\tif thread_id < 0 {\n\t\terr := errors.New(\"thread ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = thread_id\n\n\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n}\n\nfunc (this *RegSet) ThreadId() int {\n\treturn this.thread_id\n}\n\nfunc (this *RegSet) CollectReadGpRegs(instruction_ *instruction.Instruction) {\n\tsuffix := instruction_.Suffix()\n\tif suffix == instruction.RICI ||\n\t\tsuffix == instruction.RRI ||\n\t\tsuffix == instruction.RRIC ||\n\t\tsuffix == instruction.RRICI ||\n\t\tsuffix == instruction.RRIF ||\n\t\tsuffix == instruction.ZRI ||\n\t\tsuffix == instruction.ZRIC ||\n\t\tsuffix == instruction.ZRICI ||\n\t\tsuffix == instruction.ZRIF ||\n\t\tsuffix == instruction.S_RRI ||\n\t\tsuffix == instruction.U_RRI ||\n\t\tsuffix == instruction.S_RRIC ||\n\t\tsuffix == instruction.U_RRIC ||\n\t\tsuffix == instruction.S_RRICI ||\n\t\tsuffix == instruction.U_RRICI ||\n\t\tsuffix == instruction.S_RRIF ||\n\t\tsuffix == instruction.U_RRIF ||\n\t\tsuffix == instruction.RR ||\n\t\tsuffix == instruction.RRC ||\n\t\tsuffix == instruction.RRCI ||\n\t\tsuffix == instruction.ZR ||\n\t\tsuffix == instruction.ZRC ||\n\t\tsuffix == instruction.ZRCI ||\n\t\tsuffix == instruction.S_RR ||\n\t\tsuffix == instruction.U_RR ||\n\t\tsuffix == instruction.S_RRC ||\n\t\tsuffix == instruction.U_RRC ||\n\t\tsuffix == instruction.S_RRCI ||\n\t\tsuffix == instruction.U_RRCI ||\n\t\tsuffix == instruction.RIR ||\n\t\tsuffix == instruction.RIRC ||\n\t\tsuffix == instruction.RIRCI ||\n\t\tsuffix == instruction.ZIR ||\n\t\tsuffix == instruction.ZIRC ||\n\t\tsuffix == instruction.ZIRCI ||\n\t\tsuffix == instruction.S_RIRC ||\n\t\tsuffix == instruction.U_RIRC ||\n\t\tsuffix == instruction.S_RIRCI ||\n\t\tsuffix == instruction.U_RIRCI ||\n\t\tsuffix == instruction.ERRI ||\n\t\tsuffix == instruction.S_ERRI || suffix == instruction.U_ERRI ||\n\t\tsuffix == instruction.EDRI ||\n\t\tsuffix == instruction.ERII {\n\t\tif instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\t\t}\n\t} else if suffix == instruction.RRR ||\n\t\tsuffix == instruction.RRRC ||\n\t\tsuffix == instruction.RRRCI ||\n\t\tsuffix == instruction.ZRR ||\n\t\tsuffix == instruction.ZRRC ||\n\t\tsuffix == instruction.ZRRCI ||\n\t\tsuffix == instruction.S_RRR ||\n\t\tsuffix == instruction.U_RRR ||\n\t\tsuffix == instruction.S_RRRC ||\n\t\tsuffix == instruction.U_RRRC ||\n\t\tsuffix == instruction.S_RRRCI ||\n\t\tsuffix == instruction.U_RRRCI ||\n\t\tsuffix == instruction.RRRI ||\n\t\tsuffix == instruction.RRRICI ||\n\t\tsuffix == instruction.ZRRI ||\n\t\tsuffix == instruction.ZRRICI ||\n\t\tsuffix == instruction.S_RRRI ||\n\t\tsuffix == instruction.U_RRRI ||\n\t\tsuffix == instruction.S_RRRICI ||\n\t\tsuffix == instruction.U_RRRICI ||\n\t\tsuffix == instruction.ERIR ||\n\t\tsuffix == instruction.DMA_RRI {\n\t\tif instruction_.Ra().IsGpRegDescriptor() && instruction_.Rb().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Rb().GpRegDescriptor()] = true\n\t\t} else if instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t} else if instruction_.Rb().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Rb().GpRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\t\t}\n\t} else if suffix == instruction.DRDICI || suffix == instruction.ERID {\n\t\tif instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t\t}\n\n\t} else if suffix == instruction.R ||\n\t\tsuffix == instruction.RCI ||\n\t\tsuffix == instruction.Z ||\n\t\tsuffix == instruction.ZCI ||\n\t\tsuffix == instruction.S_R ||\n\t\tsuffix == instruction.U_R ||\n\t\tsuffix == instruction.S_RCI ||\n\t\tsuffix == instruction.U_RCI ||\n\t\tsuffix == instruction.CI ||\n\t\tsuffix == instruction.I {\n\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\t} else if suffix == instruction.DDCI {\n\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RegSet) CollectWriteGpRegs(instruction_ *instruction.Instruction) {\n\tsuffix := instruction_.Suffix()\n\tif suffix == instruction.RICI ||\n\t\tsuffix == instruction.ZRI ||\n\t\tsuffix == instruction.ZRIC ||\n\t\tsuffix == instruction.ZRICI ||\n\t\tsuffix == instruction.ZRIF ||\n\t\tsuffix == instruction.ZRR ||\n\t\tsuffix == instruction.ZRRC ||\n\t\tsuffix == instruction.ZRRCI ||\n\t\tsuffix == instruction.ZR ||\n\t\tsuffix == instruction.ZRC ||\n\t\tsuffix == instruction.ZRCI ||\n\t\tsuffix == instruction.ZRRI ||\n\t\tsuffix == instruction.ZRRICI ||\n\t\tsuffix == instruction.ZIR ||\n\t\tsuffix == instruction.ZIRC ||\n\t\tsuffix == instruction.ZIRCI ||\n\t\tsuffix == instruction.Z ||\n\t\tsuffix == instruction.ZCI ||\n\t\tsuffix == instruction.CI ||\n\t\tsuffix == instruction.I ||\n\t\tsuffix == instruction.ERII ||\n\t\tsuffix == instruction.ERIR ||\n\t\tsuffix == instruction.ERID ||\n\t\tsuffix == instruction.DMA_RRI {\n\t\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\t} else if suffix == instruction.RRI ||\n\t\tsuffix == instruction.RRIC ||\n\t\tsuffix == instruction.RRICI ||\n\t\tsuffix == instruction.RRIF ||\n\t\tsuffix == instruction.RRR ||\n\t\tsuffix == instruction.RRRC ||\n\t\tsuffix == instruction.RRRCI ||\n\t\tsuffix == instruction.RR ||\n\t\tsuffix == instruction.RRC ||\n\t\tsuffix == instruction.RRCI ||\n\t\tsuffix == instruction.RRRI ||\n\t\tsuffix == instruction.RRRICI ||\n\t\tsuffix == instruction.RIR ||\n\t\tsuffix == instruction.RIRC ||\n\t\tsuffix == instruction.RIRCI ||\n\t\tsuffix == instruction.R ||\n\t\tsuffix == instruction.RCI ||\n\t\tsuffix == instruction.ERRI {\n\t\tthis.prev_write_gp_reg_set[instruction_.Rc()] = true\n\t} else if suffix == instruction.S_RRI ||\n\t\tsuffix == instruction.U_RRI ||\n\t\tsuffix == instruction.S_RRIC ||\n\t\tsuffix == instruction.U_RRIC ||\n\t\tsuffix == instruction.S_RRICI ||\n\t\tsuffix == instruction.U_RRICI ||\n\t\tsuffix == instruction.S_RRIF ||\n\t\tsuffix == instruction.U_RRIF ||\n\t\tsuffix == instruction.S_RRR ||\n\t\tsuffix == instruction.U_RRR ||\n\t\tsuffix == instruction.S_RRRC ||\n\t\tsuffix == instruction.U_RRRC ||\n\t\tsuffix == instruction.S_RRRCI ||\n\t\tsuffix == instruction.U_RRRCI ||\n\t\tsuffix == instruction.S_RR ||\n\t\tsuffix == instruction.U_RR ||\n\t\tsuffix == instruction.S_RRC ||\n\t\tsuffix == instruction.U_RRC ||\n\t\tsuffix == instruction.S_RRCI ||\n\t\tsuffix == instruction.U_RRCI ||\n\t\tsuffix == instruction.DRDICI ||\n\t\tsuffix == instruction.S_RRRI ||\n\t\tsuffix == instruction.U_RRRI ||\n\t\tsuffix == instruction.S_RRRICI ||\n\t\tsuffix == instruction.U_RRRICI ||\n\t\tsuffix == instruction.S_RIRC ||\n\t\tsuffix == instruction.U_RIRC ||\n\t\tsuffix == instruction.S_RIRCI ||\n\t\tsuffix == instruction.U_RIRCI ||\n\t\tsuffix == instruction.S_R ||\n\t\tsuffix == instruction.U_R ||\n\t\tsuffix == instruction.DDCI ||\n\t\tsuffix == instruction.S_ERRI ||\n\t\tsuffix == instruction.U_ERRI ||\n\t\tsuffix == instruction.EDRI {\n\t\tthis.prev_write_gp_reg_set[instruction_.Dc().EvenRegDescriptor()] = true\n\t\tthis.prev_write_gp_reg_set[instruction_.Dc().OddRegDescriptor()] = true\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RegSet) Clear() {\n\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool, 0)\n}\n\nfunc (this *RegSet) RegIndices() map[int]bool {\n\treg_indices := make(map[int]bool, 0)\n\n\tfor gp_reg_descriptor, _ := range this.prev_write_gp_reg_set {\n\t\treg_indices[gp_reg_descriptor.Index()] = true\n\t}\n\n\tfor gp_reg_descriptor, _ := range this.cur_read_gp_reg_set {\n\t\treg_indices[gp_reg_descriptor.Index()] = true\n\t}\n\n\treturn reg_indices\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/thread.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu/reg\"\n)\n\ntype ThreadState int\n\nconst (\n\tEMBRYO ThreadState = iota\n\tRUNNABLE\n\tSLEEP\n\tBLOCK\n\tZOMBIE\n)\n\ntype Thread struct {\n\tthread_id    int\n\tthread_state ThreadState\n\treg_file     *reg.RegFile\n\tissue_cycle  int64\n}\n\nfunc (this *Thread) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif thread_id < 0 {\n\t\terr := errors.New(\"thread ID < 0\")\n\t\tpanic(err)\n\t} else if thread_id >= config_loader.MaxNumTasklets() {\n\t\terr := errors.New(\"thread ID >= max number of tasklets\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = thread_id\n\tthis.thread_state = EMBRYO\n\n\tthis.reg_file = new(reg.RegFile)\n\tthis.reg_file.Init(thread_id)\n\n\tthis.issue_cycle = 0\n}\n\nfunc (this *Thread) Fini() {\n\tif this.thread_state != ZOMBIE {\n\t\terr := errors.New(\"thread state is not zombie\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Thread) ThreadId() int {\n\treturn this.thread_id\n}\n\nfunc (this *Thread) ThreadState() ThreadState {\n\treturn this.thread_state\n}\n\nfunc (this *Thread) SetThreadState(thread_state ThreadState) {\n\tthis.thread_state = thread_state\n}\n\nfunc (this *Thread) RegFile() *reg.RegFile {\n\treturn this.reg_file\n}\n\nfunc (this *Thread) IssueCycle() int64 {\n\treturn this.issue_cycle\n}\n\nfunc (this *Thread) IncrementIssueCycle() {\n\tthis.issue_cycle++\n}\n\nfunc (this *Thread) ResetIssueCycle() {\n\tthis.issue_cycle = 0\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/thread_q.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n)\n\ntype ThreadQ struct {\n\tsize  int\n\ttimer int64\n\n\tthreads []*Thread\n\tcycles  []int64\n}\n\nfunc (this *ThreadQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.threads = make([]*Thread, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *ThreadQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"thread queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *ThreadQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *ThreadQ) IsEmpty() bool {\n\treturn len(this.threads) == 0\n}\n\nfunc (this *ThreadQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.threads) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *ThreadQ) Push(thread *Thread) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"thread queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.threads = append(this.threads, thread)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *ThreadQ) PushWithTimer(thread *Thread, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"thread queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.threads = append(this.threads, thread)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *ThreadQ) CanPop(num_items int) bool {\n\tif len(this.threads) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *ThreadQ) Pop() *Thread {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"thread queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.threads[0]\n\n\tthis.threads = this.threads[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn thread\n}\n\nfunc (this *ThreadQ) Front(pos int) (*Thread, int64) {\n\tif this.IsEmpty() {\n\t\terr := errors.New(\"thread queue is empty\")\n\t\tpanic(err)\n\t}\n\n\treturn this.threads[pos], this.cycles[pos]\n}\n\nfunc (this *ThreadQ) Remove(pos int) {\n\tthis.threads = append(this.threads[:pos], this.threads[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *ThreadQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/logic/thread_scheduler.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype ThreadScheduler struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tnum_revolver_scheduling_cycles int64\n\n\tthreads  []*Thread\n\tthread_q *ThreadQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *ThreadScheduler) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tthreads []*Thread,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.num_revolver_scheduling_cycles = command_line_parser.IntParameter(\n\t\t\"num_revolver_scheduling_cycles\",\n\t)\n\n\tthis.threads = threads\n\n\tthis.thread_q = new(ThreadQ)\n\tthis.thread_q.Init(len(this.threads), 0)\n\tfor _, thread := range threads {\n\t\tthis.thread_q.Push(thread)\n\t}\n\n\tname := fmt.Sprintf(\"ThreadScheduler[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *ThreadScheduler) Fini() {\n\tfor this.thread_q.CanPop(1) {\n\t\tthis.thread_q.Pop()\n\t}\n\n\tthis.thread_q.Fini()\n}\n\nfunc (this *ThreadScheduler) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *ThreadScheduler) NumIssuableThreads() int {\n\tnum_issuable_threads := 0\n\n\tfor _, thread := range this.threads {\n\t\tif thread.ThreadState() == RUNNABLE {\n\t\t\tnum_issuable_threads++\n\t\t}\n\t}\n\n\treturn num_issuable_threads\n}\n\nfunc (this *ThreadScheduler) Schedule() *Thread {\n\tvar is_blocked bool\n\tis_blocked = false\n\tfor i := 0; i < this.thread_q.Size(); i++ {\n\t\tthread := this.thread_q.Pop()\n\t\tthis.thread_q.Push(thread)\n\n\t\tif thread.IssueCycle() >= this.num_revolver_scheduling_cycles {\n\t\t\tif thread.ThreadState() == RUNNABLE {\n\t\t\t\tthread.ResetIssueCycle()\n\n\t\t\t\tthis.stat_factory.Increment(\"breakdown_run\", 1)\n\n\t\t\t\treturn thread\n\t\t\t} else if thread.ThreadState() == BLOCK {\n\t\t\t\tis_blocked = true\n\t\t\t}\n\t\t}\n\t}\n\n\tif is_blocked {\n\t\tthis.stat_factory.Increment(\"breakdown_dma\", 1)\n\t} else {\n\t\tthis.stat_factory.Increment(\"breakdown_etc\", 1)\n\t}\n\n\treturn nil\n}\n\nfunc (this *ThreadScheduler) Boot(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == EMBRYO {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == ZOMBIE {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not bootable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Sleep(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == RUNNABLE {\n\t\tthread.SetThreadState(SLEEP)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not sleepable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Block(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == RUNNABLE {\n\t\tthread.SetThreadState(BLOCK)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not blockable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Awake(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == EMBRYO {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == SLEEP {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == BLOCK {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not awakable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Shutdown(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == SLEEP {\n\t\tthread.SetThreadState(ZOMBIE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not shotdownable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Cycle() {\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/condition_reg.go",
    "content": "package reg\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/linker/kernel/instruction/cc\"\n)\n\ntype ConditionReg struct {\n\tconditions map[cc.Condition]bool\n}\n\nfunc (this *ConditionReg) Init() {\n\tthis.conditions = make(map[cc.Condition]bool, 0)\n\n\tthis.ClearConditions()\n}\n\nfunc (this *ConditionReg) Fini() {\n}\n\nfunc (this *ConditionReg) Condition(condition cc.Condition) bool {\n\tif condition == cc.TRUE {\n\t\treturn true\n\t} else if condition == cc.FALSE {\n\t\treturn false\n\t} else {\n\t\treturn this.conditions[condition]\n\t}\n}\n\nfunc (this *ConditionReg) SetCondition(condition cc.Condition) {\n\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\terr := errors.New(\"condition is true or false\")\n\t\tpanic(err)\n\t}\n\n\tthis.conditions[condition] = true\n}\n\nfunc (this *ConditionReg) ClearCondition(condition cc.Condition) {\n\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\terr := errors.New(\"condition is true or false\")\n\t\tpanic(err)\n\t}\n\n\tthis.conditions[condition] = false\n}\n\nfunc (this *ConditionReg) ClearConditions() {\n\tfor i := 0; i <= int(cc.LARGE); i++ {\n\t\tcondition := cc.Condition(i)\n\n\t\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\t\tcontinue\n\t\t} else {\n\t\t\tthis.conditions[condition] = false\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/exception_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/linker/kernel/instruction\"\n)\n\ntype ExceptionReg struct {\n\texceptions map[instruction.Exception]bool\n}\n\nfunc (this *ExceptionReg) Init() {\n\tthis.exceptions = make(map[instruction.Exception]bool, 0)\n\n\tthis.ClearExceptions()\n}\n\nfunc (this *ExceptionReg) Fini() {\n}\n\nfunc (this *ExceptionReg) Exception(exception instruction.Exception) bool {\n\treturn this.exceptions[exception]\n}\n\nfunc (this *ExceptionReg) SetException(exception instruction.Exception) {\n\tthis.exceptions[exception] = true\n}\n\nfunc (this *ExceptionReg) ClearException(exception instruction.Exception) {\n\tthis.exceptions[exception] = false\n}\n\nfunc (this *ExceptionReg) ClearExceptions() {\n\tfor i := 0; i <= int(instruction.NOT_PROFILING); i++ {\n\t\texception := instruction.Exception(i)\n\n\t\tthis.exceptions[exception] = false\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/flag_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/linker/kernel/instruction\"\n)\n\ntype FlagReg struct {\n\tflags map[instruction.Flag]bool\n}\n\nfunc (this *FlagReg) Init() {\n\tthis.flags = make(map[instruction.Flag]bool, 0)\n\n\tthis.ClearFlags()\n}\n\nfunc (this *FlagReg) Fini() {\n}\n\nfunc (this *FlagReg) Flag(flag instruction.Flag) bool {\n\treturn this.flags[flag]\n}\n\nfunc (this *FlagReg) SetFlag(flag instruction.Flag) {\n\tthis.flags[flag] = true\n}\n\nfunc (this *FlagReg) ClearFlag(flag instruction.Flag) {\n\tthis.flags[flag] = false\n}\n\nfunc (this *FlagReg) ClearFlags() {\n\tfor i := 0; i <= int(instruction.CARRY); i++ {\n\t\tflag := instruction.Flag(i)\n\n\t\tthis.flags[flag] = false\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/gp_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype GpReg struct {\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor\n\tword              *word.Word\n}\n\nfunc (this *GpReg) Init(index int) {\n\tthis.gp_reg_descriptor = new(reg_descriptor.GpRegDescriptor)\n\tthis.gp_reg_descriptor.Init(index)\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.word = new(word.Word)\n\tthis.word.Init(config_loader.MramDataWidth())\n}\n\nfunc (this *GpReg) Fini() {\n}\n\nfunc (this *GpReg) Index() int {\n\treturn this.gp_reg_descriptor.Index()\n}\n\nfunc (this *GpReg) Read(representation word.Representation) int64 {\n\treturn this.word.Value(representation)\n}\n\nfunc (this *GpReg) Write(value int64) {\n\tthis.word.SetValue(value)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/pc_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype PcReg struct {\n\tword *word.Word\n}\n\nfunc (this *PcReg) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.word = new(word.Word)\n\tthis.word.Init(config_loader.AddressWidth())\n}\n\nfunc (this *PcReg) Fini() {\n}\n\nfunc (this *PcReg) Read() int64 {\n\treturn this.word.Value(word.UNSIGNED)\n}\n\nfunc (this *PcReg) Write(value int64) {\n\tthis.word.SetValue(value)\n}\n\nfunc (this *PcReg) Increment() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tthis.Write(this.Read() + iram_data_size)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/reg_file.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype RegFile struct {\n\tgp_regs       []*GpReg\n\tsp_reg        *SpReg\n\tpc_reg        *PcReg\n\tcondition_reg *ConditionReg\n\tflag_reg      *FlagReg\n\texception_reg *ExceptionReg\n}\n\nfunc (this *RegFile) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.gp_regs = make([]*GpReg, 0)\n\tfor i := 0; i < config_loader.NumGpRegisters(); i++ {\n\t\tgp_reg := new(GpReg)\n\t\tgp_reg.Init(i)\n\n\t\tthis.gp_regs = append(this.gp_regs, gp_reg)\n\t}\n\n\tthis.sp_reg = new(SpReg)\n\tthis.sp_reg.Init(thread_id)\n\n\tthis.pc_reg = new(PcReg)\n\tthis.pc_reg.Init()\n\n\tthis.condition_reg = new(ConditionReg)\n\tthis.condition_reg.Init()\n\n\tthis.flag_reg = new(FlagReg)\n\tthis.flag_reg.Init()\n\n\tthis.exception_reg = new(ExceptionReg)\n\tthis.exception_reg.Init()\n}\n\nfunc (this *RegFile) Fini() {\n\tfor _, gp_reg := range this.gp_regs {\n\t\tgp_reg.Fini()\n\t}\n\n\tthis.sp_reg.Fini()\n\tthis.pc_reg.Fini()\n\tthis.condition_reg.Fini()\n\tthis.flag_reg.Fini()\n\tthis.exception_reg.Fini()\n}\n\nfunc (this *RegFile) ReadGpReg(\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n\trepresentation word.Representation,\n) int64 {\n\treturn this.gp_regs[gp_reg_descriptor.Index()].Read(representation)\n}\n\nfunc (this *RegFile) ReadSpReg(\n\tsp_reg_descriptor *reg_descriptor.SpRegDescriptor,\n\trepresentation word.Representation,\n) int64 {\n\treturn this.sp_reg.Read(sp_reg_descriptor, representation)\n}\n\nfunc (this *RegFile) ReadPairReg(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n\trepresentation word.Representation,\n) (int64, int64) {\n\teven := this.ReadGpReg(pair_reg_descriptor.EvenRegDescriptor(), representation)\n\todd := this.ReadGpReg(pair_reg_descriptor.OddRegDescriptor(), word.UNSIGNED)\n\n\treturn even, odd\n}\n\nfunc (this *RegFile) ReadSrcReg(\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n\trepresentation word.Representation,\n) int64 {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\treturn this.ReadGpReg(src_reg_descriptor.GpRegDescriptor(), representation)\n\t} else {\n\t\treturn this.ReadSpReg(src_reg_descriptor.SpRegDescriptor(), representation)\n\t}\n}\n\nfunc (this *RegFile) ReadPcReg() int64 {\n\treturn this.pc_reg.Read()\n}\n\nfunc (this *RegFile) ReadConditionReg(condition cc.Condition) bool {\n\treturn this.condition_reg.Condition(condition)\n}\n\nfunc (this *RegFile) ReadFlagReg(flag instruction.Flag) bool {\n\treturn this.flag_reg.Flag(flag)\n}\n\nfunc (this *RegFile) ReadExceptionReg(exception instruction.Exception) bool {\n\treturn this.exception_reg.Exception(exception)\n}\n\nfunc (this *RegFile) WriteGpReg(gp_reg_descriptor *reg_descriptor.GpRegDescriptor, value int64) {\n\tthis.gp_regs[gp_reg_descriptor.Index()].Write(value)\n}\n\nfunc (this *RegFile) WritePairReg(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n\teven int64,\n\todd int64,\n) {\n\tthis.WriteGpReg(pair_reg_descriptor.EvenRegDescriptor(), even)\n\tthis.WriteGpReg(pair_reg_descriptor.OddRegDescriptor(), odd)\n}\n\nfunc (this *RegFile) WritePcReg(value int64) {\n\tthis.pc_reg.Write(value)\n}\n\nfunc (this *RegFile) IncrementPcReg() {\n\tthis.pc_reg.Increment()\n}\n\nfunc (this *RegFile) SetCondition(condition cc.Condition) {\n\tthis.condition_reg.SetCondition(condition)\n}\n\nfunc (this *RegFile) ClearCondition(condition cc.Condition) {\n\tthis.condition_reg.ClearCondition(condition)\n}\n\nfunc (this *RegFile) ClearConditions() {\n\tthis.condition_reg.ClearConditions()\n}\n\nfunc (this *RegFile) SetFlag(flag instruction.Flag) {\n\tthis.flag_reg.SetFlag(flag)\n}\n\nfunc (this *RegFile) ClearFlag(flag instruction.Flag) {\n\tthis.flag_reg.ClearFlag(flag)\n}\n\nfunc (this *RegFile) ClearFlags() {\n\tthis.flag_reg.ClearFlags()\n}\n\nfunc (this *RegFile) SetException(exception instruction.Exception) {\n\tthis.exception_reg.SetException(exception)\n}\n\nfunc (this *RegFile) ClearException(exception instruction.Exception) {\n\tthis.exception_reg.ClearException(exception)\n}\n\nfunc (this *RegFile) ClearExceptions() {\n\tthis.exception_reg.ClearExceptions()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/reg/sp_reg.go",
    "content": "package reg\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/word\"\n\t\"uPIMulator/src/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype SpReg struct {\n\tzero *word.Word\n\tone  *word.Word\n\tlneg *word.Word\n\tmneg *word.Word\n\tid   *word.Word\n\tid2  *word.Word\n\tid4  *word.Word\n\tid8  *word.Word\n}\n\nfunc (this *SpReg) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.zero = new(word.Word)\n\tthis.zero.Init(config_loader.MramDataWidth())\n\tthis.zero.SetValue(0)\n\n\tthis.one = new(word.Word)\n\tthis.one.Init(config_loader.MramDataWidth())\n\tthis.one.SetValue(1)\n\n\tthis.lneg = new(word.Word)\n\tthis.lneg.Init(config_loader.MramDataWidth())\n\tthis.lneg.SetValue(-1)\n\n\tthis.mneg = new(word.Word)\n\tthis.mneg.Init(config_loader.MramDataWidth())\n\tthis.mneg.SetValue(int64(this.mneg.Width()) - 1)\n\n\tthis.id = new(word.Word)\n\tthis.id.Init(config_loader.MramDataWidth())\n\tthis.id.SetValue(int64(thread_id))\n\n\tthis.id2 = new(word.Word)\n\tthis.id2.Init(config_loader.MramDataWidth())\n\tthis.id2.SetValue(int64(2 * thread_id))\n\n\tthis.id4 = new(word.Word)\n\tthis.id4.Init(config_loader.MramDataWidth())\n\tthis.id4.SetValue(int64(4 * thread_id))\n\n\tthis.id8 = new(word.Word)\n\tthis.id8.Init(config_loader.MramDataWidth())\n\tthis.id8.SetValue(int64(8 * thread_id))\n}\n\nfunc (this *SpReg) Fini() {\n}\n\nfunc (this *SpReg) Read(\n\tsp_reg_descriptor *reg_descriptor.SpRegDescriptor,\n\trepresentation word.Representation,\n) int64 {\n\tif *sp_reg_descriptor == reg_descriptor.ZERO {\n\t\treturn this.zero.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ONE {\n\t\treturn this.one.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.LNEG {\n\t\treturn this.lneg.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.MNEG {\n\t\treturn this.mneg.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID {\n\t\treturn this.id.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID2 {\n\t\treturn this.id2.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID4 {\n\t\treturn this.id4.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID8 {\n\t\treturn this.id8.Value(representation)\n\t} else {\n\t\terr := errors.New(\"sp reg descriptor is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/sram/atomic.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Atomic struct {\n\taddress int64\n\tsize    int64\n\n\tlocks []*Lock\n}\n\nfunc (this *Atomic) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.AtomicOffset()\n\tthis.size = config_loader.AtomicSize()\n\n\tthis.locks = make([]*Lock, 0)\n\tfor i := int64(0); i < this.size; i++ {\n\t\tlock := new(Lock)\n\t\tlock.Init()\n\n\t\tthis.locks = append(this.locks, lock)\n\t}\n}\n\nfunc (this *Atomic) Fini() {\n\tfor _, lock := range this.locks {\n\t\tlock.Fini()\n\t}\n}\n\nfunc (this *Atomic) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Atomic) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Atomic) CanAcquire(address int64) bool {\n\treturn this.locks[this.Index(address)].CanAcquire()\n}\n\nfunc (this *Atomic) Acquire(address int64, thread_id int) {\n\tthis.locks[this.Index(address)].Acquire(thread_id)\n}\n\nfunc (this *Atomic) CanRelease(address int64, thread_id int) bool {\n\treturn this.locks[this.Index(address)].CanRelease(thread_id)\n}\n\nfunc (this *Atomic) Release(address int64, thread_id int) {\n\tthis.locks[this.Index(address)].Release(thread_id)\n}\n\nfunc (this *Atomic) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < atomic offset\")\n\t\tpanic(err)\n\t} else if address >= this.address+this.size {\n\t\terr := errors.New(\"address >= atomic offset + atomic size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/sram/iram.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Iram struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Iram) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.IramOffset()\n\tthis.size = config_loader.IramSize()\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < this.size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Iram) Fini() {\n}\n\nfunc (this *Iram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Iram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Iram) Read(address int64) *instruction.Instruction {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\tfor i := int64(0); i < iram_data_size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.Decode(byte_stream)\n\treturn instruction_\n}\n\nfunc (this *Iram) Write(address int64, byte_stream *encoding.ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *Iram) Index(address int64) int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif address < this.address {\n\t\terr := errors.New(\"address < IRAM offset\")\n\t\tpanic(err)\n\t} else if address+iram_data_size > this.address+this.size {\n\t\terr := errors.New(\"address >= IRAM offset + IRAM size\")\n\t\tpanic(err)\n\t}\n\n\tif (address-this.address)%iram_data_size != 0 {\n\t\terr := errors.New(\"addresses are not aligned with IRAM data size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/sram/lock.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n)\n\ntype Lock struct {\n\tthread_id *int\n}\n\nfunc (this *Lock) Init() {\n\tthis.thread_id = nil\n}\n\nfunc (this *Lock) Fini() {\n\tif this.thread_id != nil {\n\t\terr := errors.New(\"thread ID != nil\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Lock) CanAcquire() bool {\n\treturn this.thread_id == nil\n}\n\nfunc (this *Lock) Acquire(thread_id int) {\n\tif !this.CanAcquire() {\n\t\terr := errors.New(\"lock cannot be acquired\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = new(int)\n\t*this.thread_id = thread_id\n}\n\nfunc (this *Lock) CanRelease(thread_id int) bool {\n\treturn this.thread_id == nil || *this.thread_id == thread_id\n}\n\nfunc (this *Lock) Release(thread_id int) {\n\tif !this.CanRelease(thread_id) {\n\t\terr := errors.New(\"lock cannot be released\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = nil\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/dpu/sram/wram.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Wram struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Wram) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.WramOffset()\n\tthis.size = config_loader.WramSize()\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < this.size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Wram) Fini() {\n}\n\nfunc (this *Wram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Wram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Wram) Read(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Wram) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *Wram) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < WRAM offset\")\n\t\tpanic(err)\n\t} else if address >= this.address+this.size {\n\t\terr := errors.New(\"address >= WRAM offset + WRAM size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/channel_transfer_read_job.go",
    "content": "package host\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/simulator/channel\"\n)\n\ntype ChannelTransferReadJob struct {\n\tchannel_message *channel.ChannelMessage\n\n\tbyte_streams []*encoding.ByteStream\n\n\tchannel *channel.Channel\n}\n\nfunc (this *ChannelTransferReadJob) Init(\n\tchannel_message *channel.ChannelMessage,\n\tbyte_streams []*encoding.ByteStream,\n\tchannel_ *channel.Channel,\n) {\n\tif channel_message.ChannelOperation() != channel.READ {\n\t\terr := errors.New(\"channel operation is not read\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_message = channel_message\n\tthis.byte_streams = byte_streams\n\tthis.channel = channel_\n}\n\nfunc (this *ChannelTransferReadJob) Execute() {\n\tthis.channel.Lock()\n\n\tthis.channel.Push(this.channel_message)\n\n\tfor !this.channel.CanPopChannelMessage(this.channel_message) {\n\t\tthis.channel.Cycle()\n\t}\n\n\tthis.channel.PopChannelMessage(this.channel_message)\n\n\tthis.CompareByteStreams(this.byte_streams, this.channel_message.ByteStreams())\n\n\tthis.channel.Unlock()\n}\n\nfunc (this *ChannelTransferReadJob) CompareByteStreams(\n\tbyte_streams_1 []*encoding.ByteStream,\n\tbyte_streams_2 []*encoding.ByteStream,\n) {\n\tif len(byte_streams_1) != len(byte_streams_2) {\n\t\terr := errors.New(\"byte streams 1's length != byte streams 2's length\")\n\t\tpanic(err)\n\t}\n\n\tfor i := 0; i < len(byte_streams_1); i++ {\n\t\tbyte_stream_1 := byte_streams_1[i]\n\t\tbyte_stream_2 := byte_streams_2[i]\n\n\t\tif byte_stream_1.Size() != byte_stream_2.Size() {\n\t\t\terr := errors.New(\"byte stream 1's size != byte stream 2's size\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tfor j := int64(0); j < byte_stream_1.Size(); j++ {\n\t\t\tif byte_stream_1.Get(int(j)) != byte_stream_2.Get(int(j)) {\n\t\t\t\terr := errors.New(\"bytes are different\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/channel_transfer_write_job.go",
    "content": "package host\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/simulator/channel\"\n)\n\ntype ChannelTransferWriteJob struct {\n\tchannel_message *channel.ChannelMessage\n\n\tchannel *channel.Channel\n}\n\nfunc (this *ChannelTransferWriteJob) Init(\n\tchannel_message *channel.ChannelMessage,\n\tchannel_ *channel.Channel,\n) {\n\tif channel_message.ChannelOperation() != channel.WRITE {\n\t\terr := errors.New(\"channel operation is not write\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_message = channel_message\n\tthis.channel = channel_\n}\n\nfunc (this *ChannelTransferWriteJob) Execute() {\n\tthis.channel.Lock()\n\n\tthis.channel.Push(this.channel_message)\n\n\tfor !this.channel.CanPopChannelMessage(this.channel_message) {\n\t\tthis.channel.Cycle()\n\t}\n\n\tthis.channel.PopChannelMessage(this.channel_message)\n\n\tthis.channel.Unlock()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/chunk.go",
    "content": "package host\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/abi/encoding\"\n)\n\ntype ChunkType int\n\nconst (\n\tINPUT_DPU_HOST ChunkType = iota\n\tOUTPUT_DPU_HOST\n\tINPUT_DPU_MRAM_HEAP_POINTER_NAME\n\tOUTPUT_DPU_MRAM_HEAP_POINTER_NAME\n)\n\ntype Chunk struct {\n\tchunk_type ChunkType\n\n\tname   *string\n\toffset *int64\n\n\texecution int\n\tdpu_id    int\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Chunk) Init(filename string, byte_stream *encoding.ByteStream) {\n\tif this.IsInputDpuHost(filename) {\n\t\tthis.InitInputDpuHost(filename)\n\t} else if this.IsOutputDpuHost(filename) {\n\t\tthis.InitOutputDpuHost(filename)\n\t} else if this.IsInputDpuMramHeapPointerName(filename) {\n\t\tthis.InitInputDpuMramHeapPointerName(filename)\n\t} else if this.IsOutputDpuMramHeapPointerName(filename) {\n\t\tthis.InitOutputDpuMramHeapPointerName(filename)\n\t} else {\n\t\terr := errors.New(\"filename cannot be parsed\")\n\t\tpanic(err)\n\t}\n\n\tthis.byte_stream = byte_stream\n}\n\nfunc (this *Chunk) IsInputDpuHost(filename string) bool {\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tif words[0] == \"input\" &&\n\t\t!(words[1] == \"dpu\" &&\n\t\t\twords[2] == \"mram\" &&\n\t\t\twords[3] == \"heap\" &&\n\t\t\twords[4] == \"pointer\" &&\n\t\t\twords[5] == \"name\") {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *Chunk) IsOutputDpuHost(filename string) bool {\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tif words[0] == \"output\" &&\n\t\t!(words[1] == \"dpu\" &&\n\t\t\twords[2] == \"mram\" &&\n\t\t\twords[3] == \"heap\" &&\n\t\t\twords[4] == \"pointer\" &&\n\t\t\twords[5] == \"name\") {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *Chunk) IsInputDpuMramHeapPointerName(filename string) bool {\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tif words[0] == \"input\" &&\n\t\twords[1] == \"dpu\" &&\n\t\twords[2] == \"mram\" &&\n\t\twords[3] == \"heap\" &&\n\t\twords[4] == \"pointer\" &&\n\t\twords[5] == \"name\" {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *Chunk) IsOutputDpuMramHeapPointerName(filename string) bool {\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tif words[0] == \"output\" &&\n\t\twords[1] == \"dpu\" &&\n\t\twords[2] == \"mram\" &&\n\t\twords[3] == \"heap\" &&\n\t\twords[4] == \"pointer\" &&\n\t\twords[5] == \"name\" {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *Chunk) InitInputDpuHost(filename string) {\n\tif !this.IsInputDpuHost(filename) {\n\t\terr := errors.New(\"filename is not input DPU host\")\n\t\tpanic(err)\n\t}\n\n\tthis.chunk_type = INPUT_DPU_HOST\n\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tthis.name = new(string)\n\t*this.name = strings.Join(words[1:len(words)-2], \"_\")\n\n\tvar err error\n\tthis.execution, err = strconv.Atoi(words[len(words)-2])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.dpu_id, err = strconv.Atoi(words[len(words)-1])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Chunk) InitOutputDpuHost(filename string) {\n\tif !this.IsOutputDpuHost(filename) {\n\t\terr := errors.New(\"filename is not output DPU host\")\n\t\tpanic(err)\n\t}\n\n\tthis.chunk_type = OUTPUT_DPU_HOST\n\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tthis.name = new(string)\n\t*this.name = strings.Join(words[1:len(words)-2], \"_\")\n\n\tvar err error\n\tthis.execution, err = strconv.Atoi(words[len(words)-2])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.dpu_id, err = strconv.Atoi(words[len(words)-1])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Chunk) InitInputDpuMramHeapPointerName(filename string) {\n\tif !this.IsInputDpuMramHeapPointerName(filename) {\n\t\terr := errors.New(\"filename is not input DPU MRAM heap pointer name\")\n\t\tpanic(err)\n\t}\n\n\tthis.chunk_type = INPUT_DPU_MRAM_HEAP_POINTER_NAME\n\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tvar err error\n\tthis.offset = new(int64)\n\t*this.offset, err = strconv.ParseInt(words[len(words)-3], 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.execution, err = strconv.Atoi(words[len(words)-2])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.dpu_id, err = strconv.Atoi(words[len(words)-1])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Chunk) InitOutputDpuMramHeapPointerName(filename string) {\n\tif !this.IsOutputDpuMramHeapPointerName(filename) {\n\t\terr := errors.New(\"filename is not output DPU MRAM heap pointer name\")\n\t\tpanic(err)\n\t}\n\n\tthis.chunk_type = OUTPUT_DPU_MRAM_HEAP_POINTER_NAME\n\n\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\tvar err error\n\tthis.offset = new(int64)\n\t*this.offset, err = strconv.ParseInt(words[len(words)-3], 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.execution, err = strconv.Atoi(words[len(words)-2])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.dpu_id, err = strconv.Atoi(words[len(words)-1])\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Chunk) ChunkType() ChunkType {\n\treturn this.chunk_type\n}\n\nfunc (this *Chunk) Name() string {\n\tif this.name == nil {\n\t\terr := errors.New(\"name == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.name\n}\n\nfunc (this *Chunk) Offset() int64 {\n\tif this.offset == nil {\n\t\terr := errors.New(\"offset == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.offset\n}\n\nfunc (this *Chunk) Execution() int {\n\treturn this.execution\n}\n\nfunc (this *Chunk) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *Chunk) ByteStream() *encoding.ByteStream {\n\treturn this.byte_stream\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/cycle_job.go",
    "content": "package host\n\nimport (\n\t\"uPIMulator/src/simulator/dpu\"\n\t\"uPIMulator/src/simulator/dpu/logic\"\n)\n\ntype CycleJob struct {\n\tsys_end int64\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *CycleJob) Init(sys_end int64, dpu_ *dpu.Dpu) {\n\tthis.sys_end = sys_end\n\tthis.dpu = dpu_\n}\n\nfunc (this *CycleJob) Execute() {\n\tthreads := this.dpu.Threads()\n\n\tfor _, thread := range threads {\n\t\tif thread.RegFile().ReadPcReg() == this.sys_end && thread.ThreadState() == logic.SLEEP {\n\t\t\tthis.dpu.ThreadScheduler().Shutdown(thread.ThreadId())\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/dma_transfer_to_atomic_job.go",
    "content": "package host\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype DmaTransferToAtomicJob struct {\n\tatomic *encoding.ByteStream\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DmaTransferToAtomicJob) Init(atomic *encoding.ByteStream, dpu_ *dpu.Dpu) {\n\tthis.atomic = atomic\n\tthis.dpu = dpu_\n}\n\nfunc (this *DmaTransferToAtomicJob) Execute() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.dpu.Dma().TransferToAtomic(config_loader.AtomicOffset(), this.atomic)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/dma_transfer_to_iram_job.go",
    "content": "package host\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype DmaTransferToIramJob struct {\n\tiram *encoding.ByteStream\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DmaTransferToIramJob) Init(iram *encoding.ByteStream, dpu_ *dpu.Dpu) {\n\tthis.iram = iram\n\tthis.dpu = dpu_\n}\n\nfunc (this *DmaTransferToIramJob) Execute() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.dpu.Dma().TransferToIram(config_loader.IramOffset(), this.iram)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/dma_transfer_to_mram_job.go",
    "content": "package host\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype DmaTransferToMramJob struct {\n\tmram *encoding.ByteStream\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DmaTransferToMramJob) Init(mram *encoding.ByteStream, dpu_ *dpu.Dpu) {\n\tthis.mram = mram\n\tthis.dpu = dpu_\n}\n\nfunc (this *DmaTransferToMramJob) Execute() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.dpu.Dma().TransferToMram(config_loader.MramOffset(), this.mram)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/dma_transfer_to_wram_job.go",
    "content": "package host\n\nimport (\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype DmaTransferToWramJob struct {\n\twram *encoding.ByteStream\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DmaTransferToWramJob) Init(wram *encoding.ByteStream, dpu_ *dpu.Dpu) {\n\tthis.wram = wram\n\tthis.dpu = dpu_\n}\n\nfunc (this *DmaTransferToWramJob) Execute() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.dpu.Dma().TransferToWram(config_loader.WramOffset(), this.wram)\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/host/host.go",
    "content": "package host\n\nimport (\n\t\"errors\"\n\t\"os\"\n\t\"path/filepath\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/core\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/channel\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype Host struct {\n\tbin_dirpath string\n\n\tnum_simulation_threads int\n\n\tbenchmark             string\n\tnum_channels          int\n\tnum_ranks_per_channel int\n\tnum_dpus_per_rank     int\n\tnum_tasklets          int\n\n\taddresses map[string]int64\n\tvalues    map[string]int64\n\n\tatomic *encoding.ByteStream\n\tiram   *encoding.ByteStream\n\twram   *encoding.ByteStream\n\tmram   *encoding.ByteStream\n\n\tnum_executions int\n\n\tinput_dpu_host  []*Chunk\n\toutput_dpu_host []*Chunk\n\n\tinput_dpu_mram_heap_pointer_name  []*Chunk\n\toutput_dpu_mram_heap_pointer_name []*Chunk\n\n\tchannels []*channel.Channel\n}\n\nfunc (this *Host) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\n\tthis.num_simulation_threads = int(command_line_parser.IntParameter(\"num_simulation_threads\"))\n\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\tthis.num_channels = int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.num_ranks_per_channel = int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tthis.num_dpus_per_rank = int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.channels = make([]*channel.Channel, 0)\n\n\tthis.InitAddresses()\n\tthis.InitValues()\n\tthis.InitAtomic()\n\tthis.InitIram()\n\tthis.InitWram()\n\tthis.InitMram()\n\tthis.InitNumExecutions()\n\tthis.InitChunks()\n}\n\nfunc (this *Host) InitAddresses() {\n\tpath := filepath.Join(this.bin_dirpath, \"addresses.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tlines := file_scanner.ReadLines()\n\n\tthis.addresses = make(map[string]int64, 0)\n\n\tfor _, line := range lines {\n\t\twords := strings.Split(line, \":\")\n\n\t\tname := words[0]\n\t\taddress, err := strconv.ParseInt(words[1][1:], 10, 64)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.addresses[name] = address\n\t}\n}\n\nfunc (this *Host) InitValues() {\n\tpath := filepath.Join(this.bin_dirpath, \"values.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tlines := file_scanner.ReadLines()\n\n\tthis.values = make(map[string]int64, 0)\n\n\tfor _, line := range lines {\n\t\twords := strings.Split(line, \":\")\n\n\t\tname := words[0]\n\t\taddress, err := strconv.ParseInt(words[1][1:], 10, 64)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.values[name] = address\n\t}\n}\n\nfunc (this *Host) InitAtomic() {\n\tpath := filepath.Join(this.bin_dirpath, \"atomic.bin\")\n\n\tthis.atomic = this.InitByteStream(path)\n}\n\nfunc (this *Host) InitIram() {\n\tpath := filepath.Join(this.bin_dirpath, \"iram.bin\")\n\n\tthis.iram = this.InitByteStream(path)\n}\n\nfunc (this *Host) InitWram() {\n\tpath := filepath.Join(this.bin_dirpath, \"wram.bin\")\n\n\tthis.wram = this.InitByteStream(path)\n}\n\nfunc (this *Host) InitMram() {\n\tpath := filepath.Join(this.bin_dirpath, \"mram.bin\")\n\n\tthis.mram = this.InitByteStream(path)\n}\n\nfunc (this *Host) InitNumExecutions() {\n\tpath := filepath.Join(this.bin_dirpath, \"num_executions.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tlines := file_scanner.ReadLines()\n\n\tif len(lines) != 1 {\n\t\terr := errors.New(\"lines' length != 1\")\n\t\tpanic(err)\n\t}\n\n\tvar err error\n\tthis.num_executions, err = strconv.Atoi(lines[0])\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Host) InitChunks() {\n\tentries, bin_dir_read_err := os.ReadDir(this.bin_dirpath)\n\n\tif bin_dir_read_err != nil {\n\t\tpanic(bin_dir_read_err)\n\t}\n\n\tthis.input_dpu_host = make([]*Chunk, 0)\n\tthis.output_dpu_host = make([]*Chunk, 0)\n\tthis.input_dpu_mram_heap_pointer_name = make([]*Chunk, 0)\n\tthis.output_dpu_mram_heap_pointer_name = make([]*Chunk, 0)\n\n\tfor _, entry := range entries {\n\t\tfilename := entry.Name()\n\n\t\twords := strings.Split(strings.Split(filename, \".\")[0], \"_\")\n\n\t\tif words[0] == \"input\" || words[0] == \"output\" {\n\t\t\tbyte_stream := this.InitByteStream(filepath.Join(this.bin_dirpath, filename))\n\n\t\t\tchunk := new(Chunk)\n\t\t\tchunk.Init(filename, byte_stream)\n\n\t\t\tif chunk.ChunkType() == INPUT_DPU_HOST {\n\t\t\t\tthis.input_dpu_host = append(this.input_dpu_host, chunk)\n\t\t\t} else if chunk.ChunkType() == OUTPUT_DPU_HOST {\n\t\t\t\tthis.output_dpu_host = append(this.output_dpu_host, chunk)\n\t\t\t} else if chunk.ChunkType() == INPUT_DPU_MRAM_HEAP_POINTER_NAME {\n\t\t\t\tthis.input_dpu_mram_heap_pointer_name = append(this.input_dpu_mram_heap_pointer_name, chunk)\n\t\t\t} else if chunk.ChunkType() == OUTPUT_DPU_MRAM_HEAP_POINTER_NAME {\n\t\t\t\tthis.output_dpu_mram_heap_pointer_name = append(this.output_dpu_mram_heap_pointer_name, chunk)\n\t\t\t} else {\n\t\t\t\tchunk_type_err := errors.New(\"chunk type is not valid\")\n\t\t\t\tpanic(chunk_type_err)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Host) InitByteStream(path string) *encoding.ByteStream {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\tlines := file_scanner.ReadLines()\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, line := range lines {\n\t\tvalue, err := strconv.Atoi(line)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbyte_stream.Append(uint8(value))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Host) Fini() {\n}\n\nfunc (this *Host) ConnectChannels(channels []*channel.Channel) {\n\tthis.channels = channels\n}\n\nfunc (this *Host) NumExecutions() int {\n\treturn this.num_executions\n}\n\nfunc (this *Host) Dpus() []*dpu.Dpu {\n\tdpus := make([]*dpu.Dpu, 0)\n\n\tfor _, channel_ := range this.channels {\n\t\tdpus = append(dpus, channel_.Dpus()...)\n\t}\n\n\treturn dpus\n}\n\nfunc (this *Host) IsZombie() bool {\n\tdpus := this.Dpus()\n\n\tfor _, dpu_ := range dpus {\n\t\tif !dpu_.IsZombie() {\n\t\t\treturn false\n\t\t}\n\t}\n\n\treturn true\n}\n\nfunc (this *Host) Load() {\n\tthis.DmaTransferToAtomic()\n\tthis.DmaTransferToIram()\n\tthis.DmaTransferToWram()\n\tthis.DmaTransferToMram()\n}\n\nfunc (this *Host) Schedule(execution int) {\n\t// TODO(bongjoon.hyun@gmail.com): fix this\n\tif this.benchmark == \"TRNS\" {\n\t\tthis.Load()\n\t}\n\n\tthis.ChannelTransferInputDpuHost(execution)\n\tthis.ChannelTransferInputDpuMramHeapPointerName(execution)\n}\n\nfunc (this *Host) Check(execution int) {\n\tthis.ChannelTransferOutputDpuHost(execution)\n\tthis.ChannelTransferOutputDpuMramHeapPointerName(execution)\n}\n\nfunc (this *Host) Launch() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tdpus := this.Dpus()\n\n\tfor _, dpu_ := range dpus {\n\t\tthreads := dpu_.Threads()\n\n\t\tfor _, thread := range threads {\n\t\t\tbootstrap := config_loader.IramOffset()\n\t\t\tthread.RegFile().WritePcReg(bootstrap)\n\t\t}\n\n\t\tdpu_.Boot()\n\t}\n}\n\nfunc (this *Host) DmaTransferToAtomic() {\n\tdpus := this.Dpus()\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tfor _, dpu_ := range dpus {\n\t\tdma_transfer_to_atomic_job := new(DmaTransferToAtomicJob)\n\t\tdma_transfer_to_atomic_job.Init(this.atomic, dpu_)\n\n\t\tthread_pool.Enque(dma_transfer_to_atomic_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) DmaTransferToIram() {\n\tdpus := this.Dpus()\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tfor _, dpu_ := range dpus {\n\t\tdma_transfer_to_iram_job := new(DmaTransferToIramJob)\n\t\tdma_transfer_to_iram_job.Init(this.iram, dpu_)\n\n\t\tthread_pool.Enque(dma_transfer_to_iram_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) DmaTransferToWram() {\n\tdpus := this.Dpus()\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tfor _, dpu_ := range dpus {\n\t\tdma_transfer_to_wram_job := new(DmaTransferToWramJob)\n\t\tdma_transfer_to_wram_job.Init(this.wram, dpu_)\n\n\t\tthread_pool.Enque(dma_transfer_to_wram_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) DmaTransferToMram() {\n\tdpus := this.Dpus()\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tfor _, dpu_ := range dpus {\n\t\tdma_transfer_to_mram_job := new(DmaTransferToMramJob)\n\t\tdma_transfer_to_mram_job.Init(this.mram, dpu_)\n\n\t\tthread_pool.Enque(dma_transfer_to_mram_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) ChannelTransferInputDpuHost(execution int) {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tpointers := this.FindInputDpuHostPointers(execution)\n\n\tfor pointer, _ := range pointers {\n\t\tif _, found := this.addresses[pointer]; !found {\n\t\t\terr := errors.New(\"pointer is not found\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\taddress := this.addresses[pointer]\n\n\t\tfor _, channel_ := range this.channels {\n\t\t\tchannel_id := channel_.ChannelId()\n\t\t\tranks := channel_.Ranks()\n\n\t\t\tfor _, rank_ := range ranks {\n\t\t\t\trank_id := rank_.RankId()\n\t\t\t\tdpus := rank_.Dpus()\n\n\t\t\t\tfor i := 0; i < 8; i++ {\n\t\t\t\t\tdpu_ids := make([]int, 0)\n\t\t\t\t\tbyte_streams := make([]*encoding.ByteStream, 0)\n\n\t\t\t\t\tfor _, dpu_ := range dpus {\n\t\t\t\t\t\tdpu_id := dpu_.DpuId()\n\t\t\t\t\t\tunique_dpu_id := channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + rank_id*this.num_dpus_per_rank + dpu_id\n\n\t\t\t\t\t\tif dpu_id%8 == i {\n\t\t\t\t\t\t\tchunk := this.FindInputDpuHostChunk(pointer, execution, unique_dpu_id)\n\n\t\t\t\t\t\t\tdpu_ids = append(dpu_ids, dpu_id)\n\t\t\t\t\t\t\tbyte_streams = append(byte_streams, chunk.ByteStream())\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif len(byte_streams) != 0 && byte_streams[0].Size() != 0 {\n\t\t\t\t\t\tchannel_message := new(channel.ChannelMessage)\n\t\t\t\t\t\tchannel_message.InitWrite(\n\t\t\t\t\t\t\tchannel_.ChannelId(),\n\t\t\t\t\t\t\trank_.RankId(),\n\t\t\t\t\t\t\tdpu_ids,\n\t\t\t\t\t\t\taddress,\n\t\t\t\t\t\t\tbyte_streams[0].Size(),\n\t\t\t\t\t\t\tbyte_streams,\n\t\t\t\t\t\t)\n\n\t\t\t\t\t\tchannel_transfer_write_job := new(ChannelTransferWriteJob)\n\t\t\t\t\t\tchannel_transfer_write_job.Init(channel_message, channel_)\n\n\t\t\t\t\t\tthread_pool.Enque(channel_transfer_write_job)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) ChannelTransferOutputDpuHost(execution int) {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tpointers := this.FindOutputDpuHostPointers(execution)\n\n\tfor pointer, _ := range pointers {\n\t\tif _, found := this.addresses[pointer]; !found {\n\t\t\terr := errors.New(\"pointer is not found\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\taddress := this.addresses[pointer]\n\n\t\tfor _, channel_ := range this.channels {\n\t\t\tchannel_id := channel_.ChannelId()\n\t\t\tranks := channel_.Ranks()\n\n\t\t\tfor _, rank_ := range ranks {\n\t\t\t\trank_id := rank_.RankId()\n\t\t\t\tdpus := rank_.Dpus()\n\n\t\t\t\tfor i := 0; i < 8; i++ {\n\t\t\t\t\tdpu_ids := make([]int, 0)\n\t\t\t\t\tbyte_streams := make([]*encoding.ByteStream, 0)\n\n\t\t\t\t\tfor _, dpu_ := range dpus {\n\t\t\t\t\t\tdpu_id := dpu_.DpuId()\n\t\t\t\t\t\tunique_dpu_id := channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + rank_id*this.num_dpus_per_rank + dpu_id\n\n\t\t\t\t\t\tif dpu_id%8 == i {\n\t\t\t\t\t\t\tchunk := this.FindOutputDpuHostChunk(pointer, execution, unique_dpu_id)\n\n\t\t\t\t\t\t\tdpu_ids = append(dpu_ids, dpu_id)\n\t\t\t\t\t\t\tbyte_streams = append(byte_streams, chunk.ByteStream())\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif len(byte_streams) != 0 && byte_streams[0].Size() != 0 {\n\t\t\t\t\t\tchannel_message := new(channel.ChannelMessage)\n\t\t\t\t\t\tchannel_message.InitRead(\n\t\t\t\t\t\t\tchannel_.ChannelId(),\n\t\t\t\t\t\t\trank_.RankId(),\n\t\t\t\t\t\t\tdpu_ids,\n\t\t\t\t\t\t\taddress,\n\t\t\t\t\t\t\tbyte_streams[0].Size(),\n\t\t\t\t\t\t)\n\n\t\t\t\t\t\tchannel_transfer_read_job := new(ChannelTransferReadJob)\n\t\t\t\t\t\tchannel_transfer_read_job.Init(channel_message, byte_streams, channel_)\n\n\t\t\t\t\t\tthread_pool.Enque(channel_transfer_read_job)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) ChannelTransferInputDpuMramHeapPointerName(execution int) {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tif _, found := this.values[\"__sys_used_mram_end\"]; !found {\n\t\terr := errors.New(\"__sys_used_mram_end is not found\")\n\t\tpanic(err)\n\t}\n\n\tsys_used_mram_end := this.values[\"__sys_used_mram_end\"]\n\n\toffsets := this.FindInputDpuMramHeapPointerNameOffsets(execution)\n\n\tfor offset, _ := range offsets {\n\t\taddress := sys_used_mram_end + offset\n\n\t\tfor _, channel_ := range this.channels {\n\t\t\tchannel_id := channel_.ChannelId()\n\t\t\tranks := channel_.Ranks()\n\n\t\t\tfor _, rank_ := range ranks {\n\t\t\t\trank_id := rank_.RankId()\n\t\t\t\tdpus := rank_.Dpus()\n\n\t\t\t\tfor i := 0; i < 8; i++ {\n\t\t\t\t\tdpu_ids := make([]int, 0)\n\t\t\t\t\tbyte_streams := make([]*encoding.ByteStream, 0)\n\n\t\t\t\t\tfor _, dpu_ := range dpus {\n\t\t\t\t\t\tdpu_id := dpu_.DpuId()\n\t\t\t\t\t\tunique_dpu_id := channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + rank_id*this.num_dpus_per_rank + dpu_id\n\n\t\t\t\t\t\tif dpu_id%8 == i {\n\t\t\t\t\t\t\tchunk := this.FindInputDpuMramHeapPointerNameChunk(\n\t\t\t\t\t\t\t\toffset,\n\t\t\t\t\t\t\t\texecution,\n\t\t\t\t\t\t\t\tunique_dpu_id,\n\t\t\t\t\t\t\t)\n\n\t\t\t\t\t\t\tdpu_ids = append(dpu_ids, dpu_id)\n\t\t\t\t\t\t\tbyte_streams = append(byte_streams, chunk.ByteStream())\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif len(byte_streams) != 0 && byte_streams[0].Size() != 0 {\n\t\t\t\t\t\tchannel_message := new(channel.ChannelMessage)\n\t\t\t\t\t\tchannel_message.InitWrite(\n\t\t\t\t\t\t\tchannel_.ChannelId(),\n\t\t\t\t\t\t\trank_.RankId(),\n\t\t\t\t\t\t\tdpu_ids,\n\t\t\t\t\t\t\taddress,\n\t\t\t\t\t\t\tbyte_streams[0].Size(),\n\t\t\t\t\t\t\tbyte_streams,\n\t\t\t\t\t\t)\n\n\t\t\t\t\t\tchannel_transfer_write_job := new(ChannelTransferWriteJob)\n\t\t\t\t\t\tchannel_transfer_write_job.Init(channel_message, channel_)\n\n\t\t\t\t\t\tthread_pool.Enque(channel_transfer_write_job)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Host) ChannelTransferOutputDpuMramHeapPointerName(execution int) {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tif _, found := this.values[\"__sys_used_mram_end\"]; !found {\n\t\terr := errors.New(\"__sys_used_mram_end is not found\")\n\t\tpanic(err)\n\t}\n\n\tsys_used_mram_end := this.values[\"__sys_used_mram_end\"]\n\n\toffsets := this.FindOutputDpuMramHeapPointerNameOffsets(execution)\n\n\tfor offset, _ := range offsets {\n\t\taddress := sys_used_mram_end + offset\n\n\t\tfor _, channel_ := range this.channels {\n\t\t\tchannel_id := channel_.ChannelId()\n\t\t\tranks := channel_.Ranks()\n\n\t\t\tfor _, rank_ := range ranks {\n\t\t\t\trank_id := rank_.RankId()\n\t\t\t\tdpus := rank_.Dpus()\n\n\t\t\t\tfor i := 0; i < 8; i++ {\n\t\t\t\t\tdpu_ids := make([]int, 0)\n\t\t\t\t\tbyte_streams := make([]*encoding.ByteStream, 0)\n\n\t\t\t\t\tfor _, dpu_ := range dpus {\n\t\t\t\t\t\tdpu_id := dpu_.DpuId()\n\t\t\t\t\t\tunique_dpu_id := channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + rank_id*this.num_dpus_per_rank + dpu_id\n\n\t\t\t\t\t\tif dpu_id%8 == i {\n\t\t\t\t\t\t\tchunk := this.FindOutputDpuMramHeapPointerNameChunk(\n\t\t\t\t\t\t\t\toffset,\n\t\t\t\t\t\t\t\texecution,\n\t\t\t\t\t\t\t\tunique_dpu_id,\n\t\t\t\t\t\t\t)\n\n\t\t\t\t\t\t\tdpu_ids = append(dpu_ids, dpu_id)\n\t\t\t\t\t\t\tbyte_streams = append(byte_streams, chunk.ByteStream())\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tif len(byte_streams) != 0 && byte_streams[0].Size() != 0 {\n\t\t\t\t\t\tchannel_message := new(channel.ChannelMessage)\n\t\t\t\t\t\tchannel_message.InitRead(\n\t\t\t\t\t\t\tchannel_.ChannelId(),\n\t\t\t\t\t\t\trank_.RankId(),\n\t\t\t\t\t\t\tdpu_ids,\n\t\t\t\t\t\t\taddress,\n\t\t\t\t\t\t\tbyte_streams[0].Size(),\n\t\t\t\t\t\t)\n\n\t\t\t\t\t\tchannel_transfer_read_job := new(ChannelTransferReadJob)\n\t\t\t\t\t\tchannel_transfer_read_job.Init(channel_message, byte_streams, channel_)\n\n\t\t\t\t\t\tthread_pool.Enque(channel_transfer_read_job)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tthread_pool.Start()\n\t}\n}\n\nfunc (this *Host) FindInputDpuHostPointers(execution int) map[string]bool {\n\tpointers := make(map[string]bool, 0)\n\n\tfor _, chunk := range this.input_dpu_host {\n\t\tif chunk.Execution() == execution {\n\t\t\tpointers[chunk.Name()] = true\n\t\t}\n\t}\n\n\treturn pointers\n}\n\nfunc (this *Host) FindOutputDpuHostPointers(execution int) map[string]bool {\n\tpointers := make(map[string]bool, 0)\n\n\tfor _, chunk := range this.output_dpu_host {\n\t\tif chunk.Execution() == execution {\n\t\t\tpointers[chunk.Name()] = true\n\t\t}\n\t}\n\n\treturn pointers\n}\n\nfunc (this *Host) FindInputDpuMramHeapPointerNameOffsets(execution int) map[int64]bool {\n\toffsets := make(map[int64]bool, 0)\n\n\tfor _, chunk := range this.input_dpu_mram_heap_pointer_name {\n\t\tif chunk.Execution() == execution {\n\t\t\toffsets[chunk.Offset()] = true\n\t\t}\n\t}\n\n\treturn offsets\n}\n\nfunc (this *Host) FindOutputDpuMramHeapPointerNameOffsets(execution int) map[int64]bool {\n\toffsets := make(map[int64]bool, 0)\n\n\tfor _, chunk := range this.output_dpu_mram_heap_pointer_name {\n\t\tif chunk.Execution() == execution {\n\t\t\toffsets[chunk.Offset()] = true\n\t\t}\n\t}\n\n\treturn offsets\n}\n\nfunc (this *Host) FindInputDpuHostChunk(pointer string, execution int, dpu_id int) *Chunk {\n\tfor _, chunk := range this.input_dpu_host {\n\t\tif chunk.Name() == pointer && chunk.Execution() == execution && chunk.DpuId() == dpu_id {\n\t\t\treturn chunk\n\t\t}\n\t}\n\n\terr := errors.New(\"chunk is not found\")\n\tpanic(err)\n}\n\nfunc (this *Host) FindOutputDpuHostChunk(pointer string, execution int, dpu_id int) *Chunk {\n\tfor _, chunk := range this.output_dpu_host {\n\t\tif chunk.Name() == pointer && chunk.Execution() == execution && chunk.DpuId() == dpu_id {\n\t\t\treturn chunk\n\t\t}\n\t}\n\n\terr := errors.New(\"chunk is not found\")\n\tpanic(err)\n}\n\nfunc (this *Host) FindInputDpuMramHeapPointerNameChunk(\n\toffset int64,\n\texecution int,\n\tdpu_id int,\n) *Chunk {\n\tfor _, chunk := range this.input_dpu_mram_heap_pointer_name {\n\t\tif chunk.Offset() == offset && chunk.Execution() == execution && chunk.DpuId() == dpu_id {\n\t\t\treturn chunk\n\t\t}\n\t}\n\n\terr := errors.New(\"chunk is not found\")\n\tpanic(err)\n}\n\nfunc (this *Host) FindOutputDpuMramHeapPointerNameChunk(\n\toffset int64,\n\texecution int,\n\tdpu_id int,\n) *Chunk {\n\tfor _, chunk := range this.output_dpu_mram_heap_pointer_name {\n\t\tif chunk.Offset() == offset && chunk.Execution() == execution && chunk.DpuId() == dpu_id {\n\t\t\treturn chunk\n\t\t}\n\t}\n\n\terr := errors.New(\"chunk is not found\")\n\tpanic(err)\n}\n\nfunc (this *Host) Cycle() {\n\tif _, found := this.addresses[\"__sys_end\"]; !found {\n\t\terr := errors.New(\"__sys_end is not found\")\n\t\tpanic(err)\n\t}\n\n\tsys_end := this.addresses[\"__sys_end\"]\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tdpus := this.Dpus()\n\n\tfor _, dpu_ := range dpus {\n\t\tcycle_job := new(CycleJob)\n\t\tcycle_job.Init(sys_end, dpu_)\n\n\t\tthread_pool.Enque(cycle_job)\n\t}\n\n\tthread_pool.Start()\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/rank/rank.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/abi/encoding\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/dpu\"\n)\n\ntype Rank struct {\n\tchannel_id int\n\trank_id    int\n\n\tdpus []*dpu.Dpu\n}\n\nfunc (this *Rank) Init(channel_id int, rank_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\n\tthis.dpus = make([]*dpu.Dpu, 0)\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tfor i := 0; i < num_dpus_per_rank; i++ {\n\t\tdpu_ := new(dpu.Dpu)\n\t\tdpu_.Init(channel_id, rank_id, i, command_line_parser)\n\n\t\tthis.dpus = append(this.dpus, dpu_)\n\t}\n}\n\nfunc (this *Rank) Fini() {\n\tfor _, dpu_ := range this.dpus {\n\t\tdpu_.Fini()\n\t}\n}\n\nfunc (this *Rank) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Rank) NumDpus() int {\n\treturn len(this.dpus)\n}\n\nfunc (this *Rank) Dpus() []*dpu.Dpu {\n\treturn this.dpus\n}\n\nfunc (this *Rank) Read(dpu_id int, address int64, size int64) *encoding.ByteStream {\n\tdpu_ := this.dpus[dpu_id]\n\n\tif dpu_.DpuId() != dpu_id {\n\t\terr := errors.New(\"DPU's DPU ID != DPU ID\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif config_loader.WramOffset() <= address &&\n\t\taddress+size <= config_loader.WramOffset()+config_loader.WramSize() {\n\t\treturn dpu_.Dma().TransferFromWram(address, size)\n\t} else if config_loader.MramOffset() <= address && address+size <= config_loader.MramOffset()+config_loader.MramSize() {\n\t\treturn dpu_.Dma().TransferFromMram(address, size)\n\t} else {\n\t\terr := errors.New(\"address does not fall under WRAM nor MRAM region\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Rank) Write(dpu_id int, address int64, byte_stream *encoding.ByteStream) {\n\tdpu_ := this.dpus[dpu_id]\n\n\tif dpu_.DpuId() != dpu_id {\n\t\terr := errors.New(\"DPU's DPU ID != DPU ID\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif config_loader.WramOffset() <= address &&\n\t\taddress+byte_stream.Size() <= config_loader.WramOffset()+config_loader.WramSize() {\n\t\tdpu_.Dma().TransferToWram(address, byte_stream)\n\t} else if config_loader.MramOffset() <= address && address+byte_stream.Size() <= config_loader.MramOffset()+config_loader.MramSize() {\n\t\tdpu_.Dma().TransferToMram(address, byte_stream)\n\t} else {\n\t\terr := errors.New(\"address does not fall under WRAM nor MRAM region\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang/uPIMulator/src/simulator/simulator.go",
    "content": "package simulator\n\nimport (\n\t\"fmt\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/core\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/simulator/channel\"\n\t\"uPIMulator/src/simulator/host\"\n)\n\ntype Simulator struct {\n\thost     *host.Host\n\tchannels []*channel.Channel\n\n\tbin_dirpath            string\n\tnum_simulation_threads int\n\texecution              int\n\n\tverbose int\n}\n\nfunc (this *Simulator) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.host = new(host.Host)\n\tthis.host.Init(command_line_parser)\n\n\tthis.verbose = int(command_line_parser.IntParameter(\"verbose\"))\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.channels = make([]*channel.Channel, 0)\n\tfor i := 0; i < num_channels; i++ {\n\t\tchannel_ := new(channel.Channel)\n\t\tchannel_.Init(i, command_line_parser)\n\n\t\tthis.channels = append(this.channels, channel_)\n\t}\n\n\tthis.host.ConnectChannels(this.channels)\n\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\tthis.num_simulation_threads = int(command_line_parser.IntParameter(\"num_simulation_threads\"))\n\tthis.execution = 0\n\n\tthis.host.Load()\n\tthis.host.Schedule(this.execution)\n\tthis.host.Launch()\n}\n\nfunc (this *Simulator) Fini() {\n\tthis.host.Fini()\n\n\tfor _, channel_ := range this.channels {\n\t\tchannel_.Fini()\n\t}\n}\n\nfunc (this *Simulator) IsFinished() bool {\n\treturn this.execution == this.host.NumExecutions()\n}\n\nfunc (this *Simulator) Cycle() {\n\tthis.host.Cycle()\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init(this.num_simulation_threads)\n\n\tdpus := this.host.Dpus()\n\tfor _, dpu_ := range dpus {\n\t\tcycle_job := new(CycleJob)\n\t\tcycle_job.Init(dpu_)\n\n\t\tthread_pool.Enque(cycle_job)\n\t}\n\n\tthread_pool.Start()\n\n\tif this.host.IsZombie() {\n\t\tfmt.Printf(\"execution (%d) is finished...\\n\", this.execution)\n\n\t\tthis.host.Check(this.execution)\n\t\tthis.execution++\n\n\t\tif !this.IsFinished() {\n\t\t\tthis.host.Schedule(this.execution)\n\t\t\tthis.host.Launch()\n\t\t}\n\t}\n\n\tif this.verbose >= 1 {\n\t\tfmt.Println(\"system is cycling...\")\n\t}\n}\n\nfunc (this *Simulator) Dump() {\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(filepath.Join(this.bin_dirpath, \"log.txt\"))\n\n\tlines := make([]string, 0)\n\n\tdpus := this.host.Dpus()\n\tfor _, dpu_ := range dpus {\n\t\tlines = append(lines, dpu_.StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.ThreadScheduler().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.Logic().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.Logic().CycleRule().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().MemoryScheduler().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().RowBuffer().StatFactory().ToLines()...)\n\t}\n\n\tfile_dumper.WriteLines(lines)\n}\n"
  },
  {
    "path": "golang_vm/README.md",
    "content": "# ⚙️ Install and Build\n## Usage Mode\nuPIMulator currently operates in an execution-driven mode.\nThe typical workflow involves the following steps:\n\n1. **Compilation and Linking:** Compile and link your application code to generate device-side binary files.\n2. **Host-Side Interpretation:** The host-side virtual machine interprets the host code, orchestrating interactions with the device-side cycle-level simulator.\n3. **Simulation and Results:** The simulator executes the device-side binary and provides detailed cycle-level simulation results.\n\nWe are actively exploring new usage modes and features to enhance uPIMulator's flexibility.\n\n## Prerequisites\n- Go Compiler: uPIMulator requires Go version 1.21.5 or higher.\nYou can download and install Go from the [official website](https://go.dev/doc/install).\n\n- Docker: Please ensure that Docker is installed on your system.\n\n    - Docker Group Membership: Your Ubuntu user account needs to be a member of the docker group.\n\n- Tested Environment: uPIMulator has been thoroughly tested on Ubuntu 18.04 with an Intel CPU. \nWhile we strive for compatibility across different environments, optimal performance and functionality are ensured within the tested setup.\n\nIf you encounter issues in unsupported environments, please report them via GitHub Issues.\nWe appreciate your feedback as we continue to improve and expand uPIMulator's compatibility.\n\n## Install\n```bash\ncd /path/to/uPIMulator/script\n\npython3 build.py\n```\n\n### Verification\nUpon successfully installing and building, the uPIMulator executable will be located in the `/path/to/uPIMulator/build` directory.\n\nPlease ensure that you replace `/path/to/uPIMulator` with the actual path where you cloned or downloaded the uPIMulator repository.\n\nIf you encounter any difficulties during the installation or build process, or if the executable is not found in the expected location, please refer to the troubleshooting section of the documentation or feel free to open an issue on our GitHub repository.\n\n# 🧪 Running the PrIM Benchmark Suite\n## Validation with PrIM Benchmark Suite\nuPIMulator's accuracy and functionality have been validated using PrIM, an open-source UPMEM-PIM benchmark suite comprising 16 data-intensive workloads across diverse application domains (linear algebra, graph processing, neural networks, etc.).\n\nAmong the 16 benchmarks, uPIMulator successfully simulates 13 without modifications. The remaining three (BFS, SpMV, NW) presented challenges due to minor bugs or their reliance on undisclosed UPMEM SDK functions, hindering their simulation and debugging within uPIMulator. Consequently, these three benchmarks are currently excluded from the exemplar benchmarks provided in this repository.\n\nWe are actively working to address these limitations and expand uPIMulator's compatibility with the full PrIM benchmark suite in future releases.\n\n## Running a Simulation\nWe'll use the VA (vector addition) benchmark to illustrate the simulation process.\nPlease note that the initial simulation might take approximately 30 minutes.\n\n### Execution\nTo initiate a simulation, provide the following:\n\n- **Benchmark name:** Specify the desired benchmark (e.g., `VA`).\n- **Number of tasklets:** Define the number of tasklets to be utilized.\n- **Output directory path:** Indicate the absolute path to the directory where you want to store binary files, log files, and other simulation artifacts. \n\nYou can further customize the simulation by utilizing command-line options to adjust various parameters.\n\n### Simulation Output\nDetailed simulation results will be written to `/path/to/bin/log.txt`.\n\n> **Note:** Be sure to replace `/path/to/bin` with the absolute path to your chosen output directory.\n\n### Important Notes\n- **Create Output Directory:** Prior to running the simulation, manually create an empty directory at the specified `bin_dirpath` before running the simulation. \n- **Absolute Paths:**  Always provide absolute paths for both `root_dirpath` (the repository's root directory) and `bin_dirpath`.\n\n```bash\ncd /path/to/uPIMulator\n\nrm -rf bin\n\nmkdir bin\n\n./build/uPIMulator --root_dirpath /path/to/uPIMulator --bin_dirpath /path/to/uPIMulator/bin --benchmark VA --num_channels 1 --num_ranks_per_channel 1 --num_dpus_per_rank 1 --num_tasklets 16 --data_prep_params 1024\n```\n\nYou can experiment with different benchmarks and configurations to explore uPIMulator's capabilities.\n\n# 🗒️ List of Parameters and Logs\n## Configuration and Output\nThe uPIMulator framework offers flexibility through command-line arguments and generates a log.txt file to present comprehensive simulation results.\nThis documentation provides detailed explanations for each parameter and the structure of the log output, aiding in understanding and interpreting the simulation data.\n\n## 🪂 Parameters\n### Parameter Types\nuPIMulator utilizes two distinct parameter categories:\n\n- **Command-Line Parameters:** The `CommandLineParser` struct processes command-line arguments, configuring both the host-side virtual machine and the device-side UPMEM-PIM simulator before simulation commences.\nThese parameters directly influence the simulation setup and execution.\n\n- **Configuration Parameters:** The `ConfigLoader` struct manages additional parameters that are less likely to affect the simulation results directly. \nThese may include settings like IRAM address offsets or MRAM size, primarily influencing the simulated environment's configuration.\n\n| Command Line Arguments | Meaning |\n| --- | --- |\n| verbose | Runtime simulation status monitoring level (0: no monitoring, 1: restricted monitoring, 2: full monitoring) |\n| benchmark | Benchmark name |\n| num_channels | Number of PIM memory channels |\n| num_ranks_per_channel | Number of ranks per PIM memory channel |\n| num_dpus_per_rank | Number of DPUs per PIM memory rank |\n| num_vm_channels | Number of conventional memory channels attached to the host |\n| num_vm_ranks_per_channel | Number of ranks per conventional memory channel attached to the host |\n| num_vm_banks_per_rank | Number of DRAM banks per conventional memory rank attached to the host |\n| num_tasklets | Number of tasklets per DPU when running the benchmark |\n| data_prep_params | Value that configures the input size of the benchmark |\n| root_dirpath | Absolute path to the root directory of uPIMulator |\n| bin_dirpath | Absolute path to the bin directory where binary files and log files are dumped |\n| logic_frequency | DPU logic frequency in MHz |\n| memory_frequency | Operating frequency of PIM and conventional memory |\n| num_pipeline_stages | Number of DPU logic pipeline stages |\n| num_revolver_scheduling_cycles | Number of DPU logic revolver scheduling cycles in DPU's logic operating frequency |\n| wordline_size | Row buffer size per single DPU's MRAM and conventional DRAM bank in bytes |\n| min_access_granularity | Minimum access granularity in bytes of DPU's MRAM and conventional DRAM's bank |\n| t_rcd | t_RCD timing parameter of DPU's MRAM and conventional DRAM's bank in cycles in memory operating frequency |\n| t_ras | t_RAS timing parameter of DPU's MRAM and conventional DRAM's bank in cycles in memory operating frequency |\n| t_rp | t_RP timing parameter of DPU's MRAM and conventional DRAM's bank in cycles in memory operating frequency |\n| t_cl | t_CL timing parameter of DPU's MRAM and conventional DRAM's bank in cycles in memory operating frequency |\n| t_bl | t_BL timing parameter of DPU's MRAM and conventional DRAM's bank in cycles in memory operating frequency |\n\n| ConfigLoader Parameters | Meaning |\n| --- | --- |\n| AddressWidth | Bit width of all addresses (e.g., 32-bit machine or 64-bit machine) |\n| AtomicDataWidth | DPU's atomic region's bit width of all data |\n| AtomicOffset | Offset address of DPU's atomic region in DPU's physical address space |\n| AtomicSize | Size in bytes of DPU's atomic region |\n| IramDataWidth | DPU's IRAM's bit width of all data |\n| IramOffset | Offset address of DPU's IRAM in DPU's physical address space |\n| IramSize | Size in bytes of DPU's IRAM |\n| WramDataWidth | DPU's WRAM's bit width of all data |\n| WramOffset | Offset address of DPU's WRAM in DPU's physical address space |\n| WramSize | Size in bytes of DPU's WRAM |\n| MramDataWidth | DPU's MRAM's bit width of all data |\n| MramOffset | Offset address of DPU's MRAM in DPU's physical address space |\n| MramSize | Size in bytes of DPU's MRAM |\n| StackSize | A single DPU's stack size in bytes for each tasklet |\n| HeapSize | A single DPU's heap size in bytes |\n| NumGpRegisters | Number of general-purpose registers of a single DPU's each tasklet |\n| MaxNumTasklets | Max number of tasklets per each DPU |\n| VmBankOffset | Offset address of each bank of the virtual machine interpreting host-side benchmark code |\n| VmBankSize | Size in bytes of the virtual machine's each bank |\n| VmBg0 | Bit location of the first bank group bit for the virtual machine's DRAM address mapping |\n| VmBg1 | Bit location of the second bank group  bit for the virtual machine's DRAM address mapping |\n| VmBank | Bit locations of the bank  bits for the virtual machine's DRAM address mapping |\n| VmMemorySize | Initial memory size of the virtual machine |\n| GarbageCollectionThreshold | Number of bytecode executed before starting garbage collection in the virtual machine |\n\n## 🪵 Logs\n## Simulation Logging\n- **Log Storage and Output:** uPIMulator temporarily stores simulation logs within the `StatFactory` struct.\nUpon completion, these logs are written to a file named `log.txt` located in the designated `bin` directory. \n\n- **Custom Log Monitoring:** To track additional simulation behaviors, you can extend the `StatFactory` struct to include new log entries.\nEnsure that these new entries are incorporated into the `Dump` function within the `System` struct to facilitate their inclusion in the final log output. \n\n| Logs | Meaning |\n| --- | --- |\n| ThreadScheduler[X_Y_Z]_breakdown_etc | Number of DPU logic cycles of the DPU not being able to issue an instruction due to revolver pipeline in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| ThreadScheduler[X_Y_Z]_breakdown_run | Number of DPU logic cycles of the DPU being able to issue an instruction in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| ThreadScheduler[X_Y_Z]_breakdown_dma | Number of DPU logic cycles of the DPU not being able to issue an instruction due to data is not ready from MRAM in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| Logic[X_Y_Z]_backpressure | Number of DPU logic cycles of the DPU not being able to issue an instruction due to register file conflicts in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| Logic[X_Y_Z]_active_tasklets_N | Number of DPU logic cycles when number of N tasklets are active in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| Logic[X_Y_Z]_logic_cycle | Number of DPU logic cycles elapsed during PIM kernel execution in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| Logic[X_Y_Z]_num_instructions | Number of instructions executed by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| CycleRule[X_Y_Z]_cycle_rule | Total number of DPU logic cycles resolving register file conflicts for all threads in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| MemoryController[X_Y_Z]_memory_cycle | Number of MRAM memory cycles ticked in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| MemoryScheduler[X_Y_Z]_num_fr | Number of reordered memory commands thanks to FR-FCFS memory scheduling policy in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| MemoryScheduler[X_Y_Z]_num_fcfs | Number of non-reordered memory commands in the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_num_activations | Number of ACTIVATION memory commands received by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_num_precharges | Number of PRECHARGE memory commands received by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_num_reads | Number of READ memory commands received by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_num_writes | Number of WRITE memory commands received by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_read_bytes | Total number of bytes read by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| RowBuffer[X_Y_Z]_write_bytes | Total number of bytes written by the DPU with channel ID of X, rank ID of Y, and DPU ID of Z |\n| VmBank[X_Y_Z]_vm_memory_cycle | Number of host-side conventional DRAM memory cycles ticked by the DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| MemoryScheduler_num_fr | Number of reordered memory commands thanks to FR-FCFS memory scheduling policy in the host-attached memory controller in the virtual machine |\n| MemoryScheduler_num_fcfs | Number of non-reordered memory commands in the host-attached memory controller in the virtual machine |\n| VmRowBuffer[X_Y_Z]_num_activations | Number of ACTIVATION memory commands received by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| VmRowBuffer[X_Y_Z]_num_precharges | Number of PRECHARGE memory commands received by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| VmRowBuffer[X_Y_Z]_num_reads | Number of READ memory commands received by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| VmRowBuffer[X_Y_Z]_num_writes | Number of WRITE memory commands received by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| VmRowBuffer[X_Y_Z]_read_bytes | Total number of bytes read by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n| VmRowBuffer[X_Y_Z]_write_bytes | Total number of bytes written by the virtual machine's DRAM bank with channel ID of X, rank ID of Y, and bank ID of Z |\n\n# 🪑 Benchmark Addition\n## Adding Custom Benchmarks\nIn addition to the provided PrIM benchmarks, uPIMulator allows you to integrate your own benchmarks, especially if you have access to UPMEM-PIM hardware and your code runs successfully on the actual device.\n\nTo incorporate your benchmark, you'll need to adapt your codebase to a format that uPIMulator's virtual machine can interpret. Detailed guidance on this process can be found in the **\"Interpretable C Grammar\"** section within this documentation.\n\nTo add a custom benchmark beyond the existing PrIM suite, adhere to the following guidelines:\n\n1. **Benchmark Location:** Place your new benchmark within the `benchmark` directory.\n\n2. **UPMEM-C Language:** The benchmark code must be written in UPMEM-C, a modified C language specifically designed for UPMEM-PIM programming, similar to CUDA for NVIDIA GPUs. Refer to the UPMEM SDK documentation for comprehensive instructions on the UPMEM programming model.\n\n3. **File Structure and Naming:** Maintain the same file hierarchy and naming conventions used in the PrIM benchmarks (e.g., `VA/host/app.c` and `VA/dpu/task.c`).\n\n4. **CMakeLists.txt:** Include a `CMakeLists.txt` file within your benchmark's directory hierarchy, mirroring the structure used in the PrIM examples.\nThis is essential as uPIMulator's interpreter and linker automatically detect and compile benchmarks using these `CMakeLists.txt` files.\n\n> **Note:** These structural requirements ensure seamless integration with uPIMulator's build and execution processes.\n\n# 🏊 Delving into the Host-Side Virtual Machine\n## Host-Side Virtual Machine and Interpretable C Grammar\nThe host-side virtual machine interprets host-side code written in a subset of C, eliminating the need for manual input/output data preparation.\n\n## Interpretable C Grammar\nuPIMulator's interpreter, responsible for generating bytecode for the virtual machine, consists of three components: the lexer, the parser, and the code generator.\n\n### Supported Data Types\n- `char`\n- `short`\n- `int`\n- `long` (64-bit integers in the uPIMulator's virtual machine)\n\n### Limitations and Exceptions\nWhile the interpreter strives to handle standard C grammar, certain features are currently unsupported due to the virtual machine's constraints:\n\n- **Comments:** Any kind of comments (`//` or `/* */`) are not allowed.\n- **Header Files:** Including header files will be ignored.\n- **Linking:** The host-side virtual machine does not support linking.\nAll code must reside in a single file named `app.c` within the benchmark directory.\n- **`#define` Directives:**\n    - `#define NUM_DPUS`, `#define NUM_TASKLETS`, and `#define DATA_PREP_PARAMS` will be replaced with their corresponding command-line arguments (i.e., `--num_dpus`, `--num_tasklets`, `--data_prep_params`).\n    - Other `#define` directives will have their right-hand side (rvalue) evaluated and assigned.\n    The rvalue must be a single number.\n- **Macro Functions:** Macro functions are not permitted.\n- **Conditional Compilation:** Constructs like `#if`, `#ifdef`, etc., are not supported.\n- **Data Types and Keywords:**\n    - `bool`, `static`, `unsigned`, `union`, `enum`, `const`, and `typedef` keywords are not supported.\n- **Struct Initialization:** \n    - Struct variables must be initialized using `malloc` (e.g., `struct foo_t bar = malloc(sizeof(struct foo_t));`).\n    - `sizeof` expressions cannot infer variable types by name.\n    - Direct struct initialization (e.g., `struct foo_t bar = {1, 2};`) is not supported.\n- **Expressions and Operators:**\n    - Assignment statements (`a = 2`) and increment/decrement operators (`i++`, `--j`) do not evaluate to expressions.\n    - The virtual machine evaluates all expressions, even in short-circuit logical operations (e.g., both `expr_a` and `expr_b` will be evaluated in `expr_a || expr_b`, even if `expr_a` is true).\n- **Other Restrictions:**\n    - Array declarations (`int a[10];`) and `switch-case` statements are not allowed.\n    - Nested pointers (`int** p;`) and pointer arithmetic (`p + 1`) are not supported.\n    - Curly braces are mandatory for control flow structures (e.g., `if (foo) bar();` is invalid).\n    - Type casting (e.g., `(int *) p`) is not permitted.\n    - The `main` function should not have any arguments (`int main() {...}`).\n    - Standard library calls, except for `malloc` and `free`, are not supported (e.g., `printf` cannot be used).\n    - Only the following UPMEM SDK library functions are supported: `dpu_alloc`, `dpu_load`, `dpu_prepare`, `dpu_push_xfer`, `dpu_copy_to`, `dpu_copy_from`, `dpu_launch`, and `dpu_free`.\n    - `float` and `double` types are not supported.\n\nPlease adhere to these guidelines when writing host-side code for uPIMulator. We are continuously working to expand the supported C grammar and features in future releases.\n\n## 🏗️ Virtual Machine Overview\n<img src=\"../assets/uPIMulatorVM_overview.png\" width=\"1000\">\n\n### Host-Side Interpreter and Virtual Machine Architecture\nuPIMulator employs a streamlined host-side interpreter and virtual machine to facilitate the interpretation of C code.\nWhile this approach offers benefits in terms of simplicity and ease of use, it also entails certain limitations, as outlined in the **\"Interpretable C Grammar\"** section above.\nConsequently, some modifications to your host-side C code may be necessary to ensure compatibility with uPIMulator's interpreter and virtual machine.\n\n### Interpreter\nThe interpreter follows a three-stage process to generate bytecode, which is subsequently executed by the virtual machine:\n\n1. **Lexical Analysis (Lexer):**  The lexer breaks down the C source code into a stream of tokens.\n\n2. **Syntax Analysis (Parser):**  The parser constructs an Abstract Syntax Tree (AST) from the token stream, representing the code's structure.\n\n3. **Code Generation (Codegen):**  The codegen translates the AST into bytecode instructions for the virtual machine.\n\n> **Note:** The interpreter currently lacks type checking capabilities.\n> To ensure type safety, we strongly recommend utilizing a C compiler (such as GCC) to identify any compilation errors before attempting simulation with uPIMulator.\n\n### Virtual Machine\nThe virtual machine executes the generated bytecode sequentially, similar to other virtual machines like the Java Virtual Machine (JVM) or Python Virtual Machine.\nIt operates using a stack-based architecture, where data is manipulated on the stack rather than in registers.\n\nA basic mark-and-sweep garbage collector is implemented within the virtual machine. We are actively exploring enhancements to the garbage collection and memory management mechanisms to further optimize performance.\n\nWe are committed to ongoing development and improvement of the interpreter and virtual machine to provide a more robust and efficient simulation environment.\n\n### 💿 Bytecode\n#### Bytecode and Data Types\n- **Bytecode:** Bytecode serves as the fundamental instruction set for the virtual machine, representing the compiled form of the host-side C code.\n- **Data Types:** Within the virtual machine environment, the long data type is represented as an 8-byte integer.\n\n| Bytecode | Meaning | Arg1 | Arg2 | Str1 | Str2 |\n| --- | --- | --- | --- | --- | --- |\n| NEW_SCOPE | Creates a new scope that stores symbols for the new block statement |  |  |  |  |\n| DELETE_SCOPE | Deletes the last scope when exiting a block statement |  |  |  |  |\n| PUSH_CHAR | Push a char type or char type pointer object onto the stack | Value |  |  |  |\n| PUSH_SHORT | Push a short type or short type pointer object onto the stack | Value |  |  |  |\n| PUSH_INT | Push an int type or int type pointer object onto the stack | Value |  |  |  |\n| PUSH_LONG | Push a long type or long type pointer object onto the stack | Value |  |  |  |\n| PUSH_STRING | Push a string type or string type pointer object onto the stack |  |  | Characters |  |\n| POP | Pop an object from the stack |  |  |  |  |\n| BEGIN_STRUCT | Start registering a custom data structure (i.e., C struct), aka skeleton, to the virtual machine's registry |  |  | struct type name |  |\n| APPEND_VOID | Append a void type or void type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field name |  |\n| APPEND_CHAR | Append a char type or char type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field name |  |\n| APPEND_SHORT | Append a short type or short type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field name |  |\n| APPEND_INT | Append an int type or int type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field name |  |\n| APPEND_LONG | Append a long type or long type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field name |  |\n| APPEND_STRUCT | Append a struct type or struct type pointer field to the recently registered skeleton | Number of stars (i.e., *) |  | Field's struct type name | Field name |\n| END_STRUCT | End registering a skeleton to the virtual machine's registry |  |  |  |  |\n| NEW_GLOBAL_VOID | Creates a void type or void type pointer global symbol in the global scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_GLOBAL_CHAR | Creates a char type or char type pointer global symbol in the global scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_GLOBAL_SHORT | Creates a short type or short type pointer global symbol in the global scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_GLOBAL_INT | Creates an int type or int type pointer global symbol in the global scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_GLOBAL_LONG | Creates a long type or long type pointer global symbol in the global scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_VOID | Creates a void type or void type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_CHAR | Creates a char type or char type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_SHORT | Creates a short type or short type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_INT | Creates an int type or int type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_LONG | Creates a long type or long type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_FAST_STRUCT | Creates a struct type or struct type pointer fast (i.e., local) symbol in the fast scope | Number of stars (i.e., *) |  | struct type name | Identifier name |\n| NEW_ARG_VOID | Creates a void type or void type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_ARG_CHAR | Creates a char type or char type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_ARG_SHORT | Creates a short type or short type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_ARG_INT | Creates an int type or int type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_ARG_LONG | Creates a long type or long type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | Identifier name |  |\n| NEW_ARG_STRUCT | Creates a struct type or struct type pointer argument symbol in the argument scope upon function call | Number of stars (i.e., *) |  | struct type name | Identifier name |\n| NEW_RETURN_VOID | Creates a void type or void type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| NEW_RETURN_CHAR | Creates a char type or char type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| NEW_RETURN_SHORT | Creates a short type or short type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| NEW_RETURN_INT | Creates a int type or int type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| NEW_RETURN_LONG | Creates a long type or long type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| NEW_RETURN_STRUCT | Creates a struct type or struct type pointer in the return stack upon function return | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_VOID | Push the size of the void type or void type pointer on the stack | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_CHAR | Push the size of the char type or char type pointer on the stack | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_SHORT | Push the size of the short type or short type pointer on the stack | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_INT | Push the size of the int type or int type pointer on the stack | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_LONG | Push the size of the long type or long type pointer on the stack | Number of stars (i.e., *) |  |  |  |\n| SIZE_OF_STRUCT | Push the size of the struct type or struct type pointer on the stack | Number of stars (i.e., *) |  | struct type name |  |\n| GET_IDENTIFIER | Push the object of the symbol from global or fast scopes with identifier name on the stack |  |  | Identifier name |  |\n| GET_ARG_IDENTIFIER | Push the object of the symbol from argument scope with identifier name on the stack |  |  | Identifier name |  |\n| GET_SUBSCRIPT | Push an object of an array item on the stack |  |  |  |  |\n| GET_ACCESS | Push an object of a skeleton's field on the stack |  |  |  |  |\n| GET_REFERENCE | Push an object of a pointer to skeleton's field on the stack |  |  |  |  |\n| GET_ADDRESS | Push an address of an object on the stack |  |  |  |  |\n| GET_VALUE | Push reference of an object on the stack |  |  |  |  |\n| ALLOC | Allocates an object when calling C malloc function |  |  |  |  |\n| FREE | Deallocates an object when calling C free function |  |  |  |  |\n| ASSERT | Assert if the top of stack item is zero |  |  |  |  |\n| ADD | Add two stack items on the top and push the result on the stack |  |  |  |  |\n| SUB | Subtract two stack items on the top and push the result on the stack |  |  |  |  |\n| MUL | Multiply two stack items on the top and push the result on the stack |  |  |  |  |\n| DIV | Divide two stack items on the top and push the result on the stack |  |  |  |  |\n| MOD | Conduct a modular operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| LSHIFT | Conduct a shift-to-the-left operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| RSHIFT | Conduct a shift-to-the-right operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| NEGATE | Conduct a logical not operation for top of the stack item on the top and push the result on the stack |  |  |  |  |\n| TILDE | Conduct a bitwise not operation for top of the stack item on the top and push the result on the stack |  |  |  |  |\n| SQRT | Conduct a square root operation for top of the stack item on the top and push the result on the stack |  |  |  |  |\n| BITWISE_AND | Conduct a bitwise and operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| BITWISE_XOR | Conduct a bitwise xor operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| BITWISE_OR | Conduct a bitwise or operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| LOGICAL_AND | Conduct a logical and operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| LOGICAL_OR | Conduct a logical xor operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| LOGICAL_NOT | Conduct a logical not operation for top of the stack item on the top and push the result on the stack |  |  |  |  |\n| EQ | Conduct an equality operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| NOT_EQ | Conduct an not-equality operation for two stack items on the top and push the result on the stack |  |  |  |  |\n| CONDITIONAL | Conduct a conditional operation for three stack items on the top and push the result on the stack |  |  |  |  |\n| ASSIGN | Assign the value of object of the top of the stack to the object in the second to the top of the stack |  |  |  |  |\n| ASSIGN_STAR | Conduct a multiplication operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_DIV | Conduct a division operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_MOD | Conduct a modular operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_ADD | Conduct an addition operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_SUB | Conduct a Subtraction operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_LSHIFT | Conduct a shift-to-the-left operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_RSHIFT | Conduct a shift-to-the-right operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_BITWISE_AND | Conduct a bitwise and operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_BITWISE_XOR | Conduct a bitwise xor operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_BITWISE_OR | Conduct a bitwise or operation for two stack items on the top and assign the value to the object in the second top of the stack |  |  |  |  |\n| ASSIGN_PLUS_PLUS | Increment by one of the stack item on the top and assign the value to the object |  |  |  |  |\n| ASSIGN_MINUS_MINUS | Decrement by one of the stack item on the top and assign the value to the object |  |  |  |  |\n| ASSIGN_RETURN | Assign the value of the object in the top of the stack to the stack item on the top of the return stack |  |  |  |  |\n| JUMP | Jump to a label by changing the program counter (PC) |  |  | label name |  |\n| JUMP_IF_ZERO | Jump to a label if the value on the top of the stack is zero by changing the program counter (PC) |  |  |  |  |\n| JUMP_IF_NONZERO | Jump to a label if the value on the top of the stack is non-zero by changing the program counter (PC) |  |  |  |  |\n| CALL | Call a function by changing the program counter (PC) and pass function arguments |  |  |  |  |\n| RETURN | Return from a function and pass the value from return stack to the stack if exists |  |  |  |  |\n| NOP | Do nothing |  |  |  |  |\n| DPU_ALLOC | Allocate a single DPU | DPU ID |  |  |  |\n| DPU_LOAD | Load PIM kernel to the allocated DPUs | DPU ID |  | Benchmark name |  |\n| DPU_PREPARE | Prepare for a data transfer between the virtual machine and DPUs |  |  |  |  |\n| DPU_TRANSFER | Transfer the prepared data between the virtual machine and DPUs |  |  |  |  |\n| DPU_LAUNCH | Launch the loaded PIM kernel to the allocated DPUs |  |  |  |  |\n| DPU_FREE | Deallocate DPUs |  |  |  |  |\n\n### 🧠 Memory Management in uPIMulator's Virtual Machine\nuPIMulator's virtual machine employs a dynamic memory management system to handle objects, arenas, and data transfers within the simulated environment.\n\n#### Key Components\n- **Object:** The fundamental unit of memory, representing a typed data entity with an address and size.\n- **Arena:** Manages the allocation and deallocation of objects using a pool structure. \n    - **Pool:** Maintains a list of objects and provides allocation/deallocation functionalities.\n    Currently employs a best-fit algorithm for allocation, which we plan to optimize for improved efficiency.\n    - **Arena:**  Provides wrapper functions for `Pool` operations, such as `NewInt` for allocating and initializing integer objects.\n- **Memory:** A byte stream storing the actual data for all objects, with `Read` and `Write` APIs for data access.\n- **PC (Program Counter):**  Tracks the current execution point within the bytecode for each encountered label.\n- **Stack and Return Stack:** \n    - **Stack:** Maintains a stack of `StackItem` structs, each encapsulating a `TypeVariable` (specifying the data type), address, and size.\n    - **Return Stack:** Similar to the stack, but specifically used for storing return values from function calls.\n- **Scope:**\n    - **Scope Chain:**  Manages a chain (FIFO queue) of `Scope` structs, each associating symbol names with their runtime objects.\n    - **Scope Types:**\n        - `global`:  Holds globally defined symbols and those defined by `#define` macros.\n        - `fast`:  Stores locally defined symbols within block statements, forming a chain of fast scopes as new blocks are encountered.\n        - `arg`:  Contains symbols passed as arguments during function calls, transferred to the fast scope after the call.\n- **Type System:** A dynamic type system where each stack item's type is specified by a `TypeVariable`. \nCustom struct types are dynamically registered and tracked using `Skeleton` and `Registry` structs.\n- **Frame:** \n    - **Frame Chain:**  Manages a chain of `Frame` structs, each created upon jumping to a new label.\n    - **Frame Structure:** Encapsulates a stack, return stack, scope chain, arguments scope, and PC for managing program execution context.\n- **DRAM:** Simulates the timing of host-side DRAM accesses.\nEmploys a channel-rank-bank hierarchy and a FR-FCFS scheduling policy.\nKey components include:\n    - `TransferCommand`: Encapsulates information for DMA transfers between host and device memory.\n    - `MemoryController`: Translates `TransferCommand` into `MemoryCommand` sequences using `MemoryMapping` and `MemoryScheduler`.\n    - `MemoryMapping`: Maps virtual machine addresses to physical DRAM locations (channel, rank, bank, bank address).\n    - `MemoryScheduler`: Generates `MemoryCommand` (`ACTIVATE`, `READ`, `WRITE`, `PRECHARGE`) sequences and manages open rows.\n    - `RowBuffer`: Models the timing behavior of a DRAM bank, including activation delays, read/write latencies, and precharge time.\n\n#### Cycle Function Calls\nThe virtual machine invokes `Cycle` functions during data transfers between host and device memory or during PIM kernel execution. \n\n- **Memory Transfers:** Only the `Cycle` functions of the involved memories are called; DPU logic is not simulated.\n- **PIM Kernel Execution:** The PIM memory's `Cycle` function is called throughout the entire execution, encompassing both kernel computation and data transfers.\n\nSpecific cycle counts (e.g., `Logic[X_Y_Z]_logic_cycle`, `VmBank[X_Y_Z]_vm_memory_cycle`, `MemoryController[X_Y_Z]_memory_cycle`) can be multiplied by their respective clock frequencies to estimate wall clock times.\n\nWe are continuously refining and enhancing the memory management and simulation mechanisms within uPIMulator. Please refer to the documentation for more in-depth technical details and stay tuned for future updates!\n\n# 🏭 Delving into the Device-side UPMEM-PIM Simulator\n## Device-Side UPMEM-PIM Simulator\nThe device-side component of uPIMulator accurately models the behavior and timing characteristics of UPMEM-PIM hardware.\nThis enables detailed cycle-level simulations of PIM-based computations and memory interactions, providing insights into performance and potential optimizations.\n\n## 🏗️ UPMEM-PIM Simulator Overview\n<img src=\"../assets/uPIMulatorVM_overview.png\" width=\"1000\">\n\n## Device-Side UPMEM-PIM Simulator\nThe device-side UPMEM-PIM simulator exclusively supports execution-driven simulation, employing a producer-consumer model within its hardware components. \n\n## Core Structure\n- **Initialization and Destruction:** All hardware components are initialized using an `Init` function and deconstructed using a `Fini` function. \n- **Communication:** Components interact via `Push` and `Pop` functions to send requests (e.g., `DmaCommand`, `MemoryCommand`) and receive responses, utilizing corresponding queue structures (e.g., `DmaCommandQ`, `MemoryCommandQ`). \n- **Cycle-Level Simulation:** Each component possesses a `Cycle` function defining its single-cycle behavior.\nParent components invoke the `Cycle` functions of their child components (e.g., `MemoryController` calls `RowBuffer`'s `Cycle` function).\n\n## Key Components\n### Compiler\nThe simulator's compiler utilizes a Docker container to compile benchmark code and the UPMEM SDK using `dpu-upmem-dpurte-clang`, generating assembly code for the linker.\n\n### Linker\nThe linker comprises three stages:\n\n1. **Lexer:** Converts UPMEM assembly source code into a token stream.\n2. **Parser:**  Transforms the token stream into an Abstract Syntax Tree (AST).\n3. **Logic:**  Implements four algorithms guided by the linker script (`uPIMulator/sdk/misc/dpu.lds`) to determine memory assignments for code sections. \n    - **Liveness Analysis (`LivenessAnalyzer`):**  Analyzes the AST to establish linking relationships between benchmark and SDK library labels.\n    - **Executable Generation (`MakeExecutable`):** Aggregates assembly files into a single `main.S` file, which is then lexed and parsed into a unified AST.\n    - **Label Sizing (`LabelAssigner`):** Traverses the AST to calculate the size of each label.\n    - **Address Assignment (`LinkerScript`):** Assigns addresses to labels based on their sizes and the linker script.\n    - **Encoding:** Encodes instructions within each label into binary format, generating separate files for each memory type (e.g., `atomic.bin`, `iram.bin`, `wram.bin`, and `mram.bin`).\n\n### Simulator\nThe simulator receives the linker's output files and input/output data from the host-side virtual machine to emulate UPMEM-PIM behavior and timing.\nIt consists of two primary simulation domains:\n\n- **Logic (`uPIMulator/src/device/simulator/dpu/logic.go`):** Evaluates instructions, updates architectural states, and manages threads and their scheduling.\n- **Memory (`uPIMulator/src/device/simulator/dpu/dram.go`):**  Handles data read/write operations, modeling DRAM bank timing using parameters like `t_RAS`, `t_RCD`, `t_CL`, `t_BL`, and `t_RP`.\n\n#### Logic Details\n- **Threads and Thread Scheduler:**\n    - Multiple threads execute PIM kernel portions concurrently, each with its register file and PC.\n    - Thread states: `EMBRYO`, `RUNNABLE`, `SLEEP`, `BLOCK`, and `ZOMBIE`.\n    - Round-robin scheduling with a minimum 11-cycle dispatch interval.\n\n- **Logic (`Logic` struct):** \n    - Fetches instructions from the `ThreadScheduler`, processes them through the `Pipeline` and `CycleRule`, and executes them to update architectural states.\n    - `Pipeline`: Models the 14-stage DPU pipeline.\n    - `CycleRule`:  Calculates delays to resolve register file conflicts.\n    - `ExecuteFooBar` functions: Perform arithmetic operations, update conditions/flags/PC.\n\n#### Memory Details\n- **DMA (`Dma` struct):**  Handles DMA transfers between WRAM and MRAM based on `DmaCommand` from the `Logic`.\n- **Memory Controller (`MemoryController` struct):**  \n    - Receives `DmaCommand` from `Dma`.\n    - Utilizes `MemoryScheduler` to convert `DmaCommand` into `MemoryCommand` sequences.\n- **Memory Scheduler (`MemoryScheduler` struct):** \n    - Generates `MemoryCommand` (`ACTIVATE`, `READ`, `WRITE`, `PRECHARGE`) and manages open rows using FR-FCFS scheduling.\n- **Row Buffer (`RowBuffer` struct):** \n    - Models MRAM bank timing, including activation, read/write latencies, and precharge delays.\n\n# 🎩 Adding Custom Host-Side API\n## Extending the Host-Side API\nuPIMulator allows you to introduce custom host-side APIs to the virtual machine, enhancing its functionality and adaptability.\nWe'll illustrate this process using the example of adding a `DPU_ASSERT` API, which verifies the success of DPU-related function calls.\nNote that in the current uPIMulator implementation, these calls always succeed, so `DPU_ASSERT` has no operational effect.\nHowever, it serves as a valuable demonstration of the API extension mechanism.\n\n## Steps to Add a New Host-Side API\nExtending the host-side API involves modifications to several components:\n\n1. **Bytecode Definition:** Introduce a new bytecode instruction to represent the API call.\n2. **Interpreter's Codegen:** Implement code generation logic to emit the new bytecode when encountering the API in the host-side C code.\n3. **Virtual Machine:**  Implement the corresponding behavior for the new bytecode within the virtual machine's execution loop.\n\nThe following sections will provide code snippets and explanations for each step, guiding you through the process of seamlessly integrating your custom API into uPIMulator. \n\n## Step 1: Define the New Bytecode Opcode\nThe initial step in adding a custom host-side API involves defining a new opcode to represent the API call within uPIMulator's bytecode.\n\n### Location\nThe source code for bytecode opcodes resides in the `uPIMulator/src/host/interpreter/abi` directory.\n\n### Modification\n- Open the relevant file (`op_code.go`) and locate the `OpCode` enumeration.\n- Add a new entry for your custom API, in this case, `DPU_ASSERT`, ensuring its placement aligns with the existing opcode naming conventions.\n\n### Example Code Snippet\n\n```go\ntype OpCode int\n\nconst (\n    // ... other existing opcodes ...\n\n    DPU_ASSERT // New opcode for DPU_ASSERT API\n)\n```\n\nBy introducing this new opcode, you establish a unique identifier for the `DPU_ASSERT` API call within the bytecode, paving the way for subsequent steps in the API extension process. \n\n## Step 2: Implement Code Generation for the New API\nOnce the bytecode opcode is defined, the next step involves modifying the interpreter's code generation logic to emit the new bytecode whenever the corresponding API call is encountered in the host-side C code.\n\n### Location\nThe source code for the code generator resides in the `uPIMulator/src/host/interpreter/codegen` directory.\n\n### Modification\n- Open the `codegen.go` file and locate the `CodegenPostfixExpr` function.\n- Within this function, add a new case to handle the `DPU_ASSERT` function call. This case should perform the following:\n    1. Evaluate the function arguments.\n    2. Emit the newly defined `DPU_ASSERT` bytecode instruction.\n\n###  Example Code Snippet\n\n```go\n// ... other existing cases ...\nelse if func_name == \"DPU_ASSERT\" {\n    for i := 0; i < postfix_expr.ArgList().Length(); i++ {\n        this.CodegenExpr(postfix_expr.ArgList().Get(i))\n    }\n\n    this.relocatable.NewBytecode(abi.DPU_ASSERT, []int64{}, []string{})\n}\n// ... other existing cases ...\n```\n\nThis modification ensures that whenever the `DPU_ASSERT` function is called in the host-side C code, the code generator will emit the corresponding bytecode instruction, enabling the virtual machine to handle it appropriately.\n\n## Step 3: Implement Virtual Machine Handling for the New API\nThe final step involves incorporating the handling of the new bytecode instruction into the virtual machine's execution loop.\n\n### Location\nThe virtual machine's core logic resides in the `uPIMulator/src/host/vm/virtual_machine.go` file.\n\n### Modification\n- Locate the `Advance` function within `virtual_machine.go`. This function is responsible for parsing and executing bytecode instructions.\n- After the bytecode parsing logic, add a new case to handle the `DPU_ASSERT` opcode. \n- Within this case, define the desired behavior for the `DpuAssert` function. In the current context, where DPU-related calls always succeed, this function might simply perform a no-op (no operation) or log a message indicating a successful assertion.\n\n### Example Code Snippet\n\n```go\n// ... other existing cases ...\nelse if bytecode.OpCode() == abi.DPU_ASSERT {\n    this.DpuAssert()\n} \n// ... other existing cases ...\n\n// ... other existing cases ...\nfunc (this *VirtualMachine) DpuAssert() {\n}\n// ... other existing cases ...\n```\n\nWith this modification in place, the virtual machine will execute the `DpuAssert` function whenever it encounters the `DPU_ASSERT` bytecode, effectively integrating your new host-side API into uPIMulator's functionality.\n\nPlease note that the provided code snippet is illustrative; the actual implementation of `DpuAssert` will depend on the specific behavior you wish to associate with the `DPU_ASSERT` API.\n\n# 🎸 Adding custom device-side instructions\n## Extending the UPMEM-PIM ISA with Custom Instructions\nuPIMulator provides the capability to introduce new custom instructions to the UPMEM-PIM ISA, enabling exploration of architectural extensions and potential performance enhancements.\nWe will demonstrate this process by adding a `mul` instruction for 32-bit integer multiplication.\nWhile the original ISA achieves this through a sequence of `mul_step` instructions, the new `mul` instruction streamlines the operation into a single instruction.\n\n## Steps to Add a New Instruction\nIncorporating a new instruction into the UPMEM-PIM ISA within uPIMulator necessitates modifications to the following components:\n\n1. **Linker's Lexer and Parser:** Extend the lexer and parser to recognize and handle the new instruction's syntax.\n2. **Linker's Logic:**  Implement the corresponding behavior and logic for the new instruction within the linker.\n3. **UPMEM-PIM SDK (Optional):**  In certain cases, modifications to the UPMEM-PIM SDK might be necessary to support the new instruction at the software level.\n\nThe following sections will provide code snippets and explanations for each step, guiding you through the process of seamlessly integrating your custom instruction into uPIMulator.\n\n## Step 1: Modify the Assembly Code\nThe initial step involves incorporating the new `mul` instruction into the relevant assembly file.\nCurrently, UPMEM-PIM handles 32-bit integer multiplication using a sequence of `mul_step` instructions defined in `uPIMulator/sdk/syslib/mul32.c`.\nThese instructions are compiled into the object file `uPIMulator/sdk/build/syslib/CMakeFiles/syslib.dir/mulsi32.c.o`. \n\nWithin this assembly file, you can replace the series of `mul_step` instructions with a single `mul` instruction at the appropriate location (likely Line 22). This modification prepares the assembly code to utilize the new instruction once it is fully supported by the linker and simulator.\n\n```assembly\n__mulsi3:                               // @__mulsi3\n.Lfunc_begin0:\n\t.file\t1 \"/root/uPIMulator/sdk\" \"syslib/mul32.c\"\n\t.loc\t1 9 0                           // syslib/mul32.c:9:0\n\t.cfi_sections .debug_frame\n\t.cfi_startproc\n// %bb.0:\n\t//DEBUG_VALUE: __mulsi3:a <- $r0\n\t//DEBUG_VALUE: __mulsi3:a <- $r0\n\t//DEBUG_VALUE: __mulsi3:b <- $r1\n\t//DEBUG_VALUE: __mulsi3:b <- $r1\n\t.cfi_def_cfa_offset 0\n\t.loc\t1 11 5 prologue_end             // syslib/mul32.c:11:5\n\t// inline asm\n\tjgtu r1, r0, __mulsi3_swap\n\tmove r2, r0\n\tmove r0, r1, true, __mulsi3_start\n__mulsi3_swap:\n\tmove r2, r1\n\tmove r0, r0\n__mulsi3_start:\n\tmul r1, r0, r2\n__mulsi3_exit:\n\tmove r0, r1\n```\n\n## Step 2: Extend the Linker's Lexer\nTo enable the linker to recognize the new `mul` instruction, we need to extend its lexer to include the corresponding token.\n\n### Location\nThe source code defining the linker's tokens is located in the file `uPIMulator/src/device/linker/lexer/token.go`.\n\n### Modification\nWithin this file, add a new token representing the `mul` token to the enumeration (likely around Line 11), ensuring consistent naming and placement with the existing tokens.\n\n### Example Code Snippet\n\n```go\ntype TokenType int\n\nconst (\n    // ... other existing tokens ...\n\n    MUL // New opcode for mul instruction\n)\n```\n\nThis modification equips the lexer with the ability to identify the `mul` instruction during the lexical analysis phase, paving the way for its subsequent parsing and handling within the linker.\n\n## Step 3: Update the Tokenizer\nAfter introducing the new token to the lexer, we need to configure the tokenizer to recognize and process it correctly.\n\n### Location\nThe tokenizer's source code is found in the file `uPIMulator/src/device/linker/lexer/tokenizer.go`.\n\n### Modification\nWithin this file, register the new `MUL` token (likely around Line 10) to ensure the tokenizer can identify and classify it during lexical analysis.\n\n### Example Code Snippet\n\n```go\nfunc (this *Tokenizer) InitKeywordFactory() {\n\t// ... other token registrations ...\n\n\tthis.keyword_factory.AddKeyword(\"mul\", MUL)\n\n    // ... other token registrations ...\n}\n```\n\nThis step completes the integration of the new token into the lexer and tokenizer, enabling them to correctly handle the `mul` instruction during the initial stages of the linking process.\n\n## Step 4: Enhance the Parser to Handle the New Instruction\nNext, we need to modify the parser to correctly parse and interpret the `mul` instruction.\n\n### Location\nThe `mul` instruction has a suffix of `RRR`, indicating that it operates on three registers: one destination register and two source registers. \nThe relevant parsing logic for RRR-type instructions is located in the file `uPIMulator/src/device/linker/parser/expr/rrr_op_code_expr.go`.\n\n### Modification\nWithin this file, add the `MUL` opcode to the appropriate switch case or conditional statement that handles RRR-type instructions. \n\n> **Note:** The exact location for adding the opcode might vary depending on the specific structure of the parser code.\n> If your instruction has a different suffix, you might need to modify a different expression file accordingly.\n\n### Example Code Snippet\n\n```go\nfunc (this *RriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.MUL &&\n\t\ttoken_type != lexer.ADD &&\n    \n    // ... continue checking the opcode\n```\n\nThis modification enables the parser to recognize and process the `mul` instruction, extracting its operands and preparing it for further handling by the linker's logic.\n\n## Step 5: Register the New Opcode with the Parser\nTo ensure the parser can correctly handle the `MUL` instruction, we need to explicitly register its opcode within the `Parser` struct.\n\n### Location\nThe `Parser` struct is defined in the file `uPIMulator/src/device/linker/parser/parser.go`.\n\n### Modification\nLocate the initialization or setup logic for the `Parser` struct, and add the `MUL` opcode to the relevant collection or mapping that tracks supported opcodes (likely around Line 11).\n\n### Example Code Snippet\n\n```go\nfunc (this *Parser) RegisterRriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.MUL ||\n\t\t\t\t\ttoken_type == lexer.ADD ||\n\n    // ... continue ...\n```\n\nThis registration step informs the parser about the existence of the `MUL` opcode, allowing it to invoke the appropriate parsing logic when encountering the `mul` instruction in the assembly code.\n\nPlease proceed to the next step or feel free to ask any questions! \n\n## Step 6: Implement Instruction Encoding\nTo enable the linker to generate the correct binary representation for the new `mul` instruction, we need to define its encoding scheme.\n\n### Location\nThe instruction encoding logic is located in the file `uPIMulator/src/device/linker/kernel/instruction/op_code.go`.\n\n### Modification\nWithin this file, add the `MUL` opcode to the appropriate data structure or mapping that associates opcodes with their binary encodings (likely around Line 7).\nEnsure that the encoding adheres to the established conventions for UPMEM-PIM instructions.\n\n### Example Code Snippet\n\n```go\ntype OpCode int\n\nconst (\n\t// ... other existing opcodes ...\n\n\tMUL\n\n    // ... other existing opcodes ...\n}\n```\n\nThis modification equips the linker with the necessary information to translate the `mul` instruction into its corresponding binary representation during the final encoding phase.\n\n## Step 7: Update Instruction Handling\nTo ensure proper handling of the `MUL` instruction within the simulator, we need to inform the `Instruction` struct about its RRR-type nature and provide a string representation for verbose logging.\n\n### Location\nThe `Instruction` struct and related functions are defined in the file `uPIMulator/src/device/linker/kernel/instruction/instruction.go`.\n\n### Modifications\n1. **RRR Opcode Identification:**\n    - Locate the `RrrOpCodes` function within `instruction.go`.\n    - Add the `MUL` opcode to the list of RRR opcodes (likely around Line 3).\n\n2. **Opcode Stringification (Optional):**\n    - If you desire verbose logging of the `MUL` instruction, locate the `StringifyOpcode` function.\n    - Add a case to handle the `MUL` opcode, returning its string representation (e.g., \"MUL\") (likely around Lines 8-10).\n\n### Example Code Snippets\n\n```go\nfunc (this *Instruction) RrrOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMUL:      true,\n\t\tADD:      true,\n        // ... other existing opcodes ...\n    }\n}\n\nfunc (this *Instruction) StringifyOpCode() string {\n\t// ... other existing opcodes ...\n    else if this.op_code == MUL {\n\t\treturn \"mul\"\n\t}\n    // ... other existing opcodes ...\n```\n\nThese modifications ensure that the `Instruction` struct correctly identifies and handles the `MUL` instruction as an RRR-type operation, and optionally provides a human-readable string representation for verbose logging purposes.\n\n## Step 8: Associate the Token with the Instruction Opcode\nWith the lexer, parser, and encoding in place, we need to establish the connection between the `MUL` token and its corresponding `MUL` opcode within the `InstructionAssigner` struct.\n\n### Location\nThe `InstructionAssigner` struct is defined in the file `uPIMulator/src/device/linker/logic/instruction_assigner.go`.\n\n### Modification\nLocate the appropriate mapping or data structure within the `InstructionAssigner` that associates tokens with opcodes.\nAdd an entry to link the `MUL` token with the `MUL` opcode (likely around Lines 5-7).\n\n### Example Code Snippet**\n\n```go\nfunc (this *InstructionAssigner) ConvertRriOpCode(op_code *expr.Expr) instruction.OpCode {\n\trri_op_code_expr := op_code.RriOpCodeExpr()\n\n\ttoken_type := rri_op_code_expr.Token().TokenType()\n\t\n    // ... other existing opcodes ...\n    else if token_type == lexer.MUL {\n\t\treturn instruction.MUL\n\t}\n    // ... other existing opcodes ...\n}\n```\n\nThis association enables the `InstructionAssigner` to correctly translate the `MUL` token encountered during parsing into the corresponding `MUL` opcode when constructing `Instruction` structs for the simulator.\n\n## Step 9: Implement Instruction Behavior\nNow, we'll define the functional behavior of the new `mul` instruction, which is to perform a multiplication operation.\n\n### Location\nThe core arithmetic logic unit (ALU) operations are typically implemented within the `Alu` struct, located in the file `uPIMulator/src/device/simulator/dpu/logic/alu.go`.\n\n### Modification\nWithin this file, add a new function or method to the `Alu` struct to handle the `MUL` opcode. This function should implement the 32-bit integer multiplication logic.\n\n### Example Code Snippet**\n\n```go\nfunc (this *Alu) Mul(operand1 int64, operand2 int64) {\n    return operand1 * operand2\n}\n```\n\nThis addition equips the ALU with the capability to execute the `mul` instruction, performing the desired multiplication operation when encountered during simulation.\n\n## Step 10: Integrate the Instruction into the Logic\nThe final step is to incorporate the newly defined `mul` instruction handling into the main simulation logic.\n\n### Location\nThe core simulation logic is encapsulated within the `Logic` struct, found in the file `uPIMulator/src/device/simulator/dpu/logic/logic.go`.\n\n### Modification\nLocate the section within the `Logic` struct's execution loop where instructions are dispatched and executed. Add a case to handle the `MUL` opcode, invoking the `ExecuteMul` function you defined in the `Alu` struct. \n\n### Example Code Snippet**\n\n```go\nfunc (this *Logic) ExecuteRrr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.MUL {\n\t\tresult = this.alu.Mul(ra, rb)\n        carry = false\n\t}\n    \n    // ... continue ...\n}\n```\n\nThis integration ensures that when the `MUL` instruction is encountered during simulation, the `Logic` struct will delegate its execution to the `Alu` struct's `Mul` function, effectively incorporating the new instruction's behavior into the overall simulation flow.\n\nCongratulations! You have now successfully added a custom instruction to the UPMEM-PIM ISA within uPIMulator. \n\nFeel free to ask any further questions or seek clarification on any aspect of the process! \n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\nPROBLEM_SIZE ?= 2\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DPROBLEM_SIZE=${PROBLEM_SIZE}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -i 262144\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/cpu/Makefile",
    "content": "all:\n\tgcc bs_omp.c -o bs_omp -fopenmp\nrun:\n\t./bs_omp 262144 16777216\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/cpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./bs_omp 2048576 16777216\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/cpu/bs_omp.c",
    "content": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n#include <stdint.h>\n#include \"timer.h\"\n\n#define DTYPE uint64_t\n/*\n* @brief creates a \"test file\" by filling a bufferwith values\n*/\nvoid create_test_file(DTYPE * input, uint64_t  nr_elements, DTYPE * querys, uint64_t n_querys) {\n\n  uint64_t max = UINT64_MAX;\n  uint64_t min = 0;\n\n  srand(time(NULL));\n\n  input[0] = 1;\n  for (uint64_t i = 1; i < nr_elements; i++) {\n        input[i] = input[i - 1] + (rand() % 10) + 1;\n  }\n\n  for(uint64_t i = 0; i < n_querys; i++)\n  {\n\tquerys[i] = input[rand() % (nr_elements - 2)];\n  }\n}\n\n/**\n* @brief compute output in the host\n*/\nuint64_t binarySearch(DTYPE * input, uint64_t input_size, DTYPE* querys, unsigned n_querys)\n{\n\n\tuint64_t found = -1;\n\tuint64_t q, r, l, m;\n\t\n       #pragma omp parallel for private(q,r,l,m)\n     \tfor(q = 0; q < n_querys; q++)\n      \t{\n\t\tl = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) \n\t\t{\n\t    \t\tm = l + (r - l) / 2;\n\n\t    \t\t// Check if x is present at mid\n\t     \t\tif (input[m] == querys[q])\n\t\t\t{\t\n\t\t    \t\tfound += m;\n\t\t\t\tbreak;\n\t\t\t}\n\t    \t\t// If x greater, ignore left half\n\t    \t\tif (input[m] < querys[q])\n\t\t\t    \tl = m + 1;\n\n\t    \t\t// If x is smaller, ignore right half\n\t\t\telse\n\t\t    \t\tr = m - 1;\n\t\t\n\t\t}\n       \t}\n\n      \treturn found;\n}\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    Timer timer;\n    uint64_t input_size = atol(argv[1]);\n    uint64_t n_querys = atol(argv[2]);\n\n    printf(\"Vector size: %lu, num searches: %lu\\n\", input_size, n_querys);\n\t\n    DTYPE * input = malloc((input_size) * sizeof(DTYPE));\n    DTYPE * querys = malloc((n_querys) * sizeof(DTYPE));\n\n    DTYPE result_host = -1;\n\n    // Create an input file with arbitrary data.\n    create_test_file(input, input_size, querys, n_querys);\n\t\n    start(&timer, 0, 0);\n    result_host = binarySearch(input, input_size - 1, querys, n_querys);   \n    stop(&timer, 0);\n\n\n    int status = (result_host);\n    if (status) {\n        printf(\"[OK] Execution time: \");\n\tprint(&timer, 0, 1);\n\tprintf(\"ms.\\n\");\n    } else {\n        printf(\"[ERROR]\\n\");\n    }\n    free(input);\n\n\n    return status ? 0 : 1;\n}\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/cpu/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/Makefile",
    "content": "all:\n\tnvcc -arch=sm_30 -m64 -Xcompiler -fPIC -shared -o cu_binary_search.so binary_search.cu -std=c++11\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    python3 run.py\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/binary_search.cu",
    "content": "#include <cuda.h>\r\n#include <limits.h>\r\n#include \"binary_search.h\"\r\n\r\n#include <chrono>\r\n#include <iostream>\r\n\r\n#define BLOCKDIM 512\r\n#define SEARCH_CHUNK 16\r\n#define BLOCK_CHUNK (BLOCKDIM*SEARCH_CHUNK)\r\n\r\n\r\n__global__ void search_kernel(const long int *arr,\r\n    const long int len, const long int *querys, const long int num_querys, long int *res, bool *flag)\r\n{\r\n    int search;\r\n    if(*flag == false) {\r\n        int tid = threadIdx.x;\r\n        __shared__ int s_arr[BLOCK_CHUNK];\r\n\r\n        /* Since each value is being copied to shared memory, the rest of the\r\n        following uncommented code is unncessary, since a direct comparison\r\n        can be done at the time of copy below. */\r\n        // for(int i = 0; i < BLOCKDIM; ++i) {\r\n        //     int shared_loc = i*SEARCH_CHUNK + tid;\r\n        //     int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n        //     if(arr[global_loc] == search) {\r\n        //         *flag = true;\r\n        //         *res = global_loc;\r\n        //     }\r\n        //     __syncthreads();\r\n        // }\r\n\r\n        /* Copy chunk of array that this entire block of threads will read\r\n        from the slower global memory to the faster shared memory. */\r\n        for(long int i = 0; i < SEARCH_CHUNK; ++i) {\r\n            int shared_loc = tid*SEARCH_CHUNK + i;\r\n            int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n\r\n            /* Make sure to stay within the bounds of the global array,\r\n            else assign a dummy value. */\r\n            if(global_loc < len) {\r\n              s_arr[shared_loc] = arr[global_loc];\r\n            }\r\n            else {\r\n              s_arr[shared_loc] = INT_MAX;\r\n            }\r\n        }\r\n        __syncthreads();\r\n\r\n        for(long int i = 0; i < num_querys; i++)\r\n        {\r\n            search = querys[i];\r\n            /* For each runtime, set the initial search range. */\r\n            int L = 0;\r\n            int R = SEARCH_CHUNK - 1;\r\n            int m = (L + R) / 2;\r\n\r\n            /* Pointer to the part of the shared array for this runtime. */\r\n            int *s_ptr = &s_arr[tid*SEARCH_CHUNK];\r\n\r\n            /* Each runtime will search a chunk of the block array.\r\n            Many blocks will not find a solution so the search must\r\n            be allowed to fail on a per block basis. The loop will\r\n            break (fail) when L >= R. */\r\n            while(L <= R && *flag == false)\r\n            {\r\n                if(s_ptr[m] < search) {\r\n                    L = m + 1;\r\n                }\r\n                else if(s_ptr[m] > search) {\r\n                    R = m - 1;\r\n                }\r\n                else {\r\n                    *flag = true;\r\n                    *res = m += tid*SEARCH_CHUNK + BLOCK_CHUNK * blockIdx.x;\r\n                }\r\n\r\n                m = (L + R) / 2;\r\n            }\r\n        }\r\n    }\r\n}\r\n\r\n\r\n\r\nint binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys)\r\n{\r\n    long int *d_arr, *d_querys, *d_res;\r\n    bool *d_flag;\r\n\r\n    size_t arr_size = len * sizeof(long int);\r\n    size_t querys_size = num_querys * sizeof(long int);\r\n    size_t res_size = sizeof(long int);\r\n    size_t flag_size = sizeof(bool);\r\n\r\n    cudaMalloc(&d_arr, arr_size);\r\n    cudaMalloc(&d_querys, querys_size);\r\n    cudaMalloc(&d_res, res_size);\r\n    cudaMalloc(&d_flag, flag_size);\r\n\r\n    cudaMemcpy(d_arr, arr, arr_size, cudaMemcpyHostToDevice);\r\n    cudaMemcpy(d_querys, querys, querys_size, cudaMemcpyHostToDevice);\r\n    cudaMemset(d_flag, 0, flag_size);\r\n\r\n    /* Set res value to -1, so that if the function returns -1, that\r\n    indicates an algorithm failure. */\r\n    cudaMemset(d_res, -0x1, res_size);\r\n\r\n    int blockSize = BLOCKDIM;\r\n    int gridSize = (len-1)/BLOCK_CHUNK + 1;\r\n\r\n    auto start = std::chrono::high_resolution_clock::now();\r\n    search_kernel<<<gridSize,blockSize>>>(d_arr, len, d_querys, num_querys ,d_res, d_flag);\r\n    cudaDeviceSynchronize();\r\n    auto end = std::chrono::high_resolution_clock::now();\r\n    std::cout << \"Kernel Time: \" <<\r\n        std::chrono::duration_cast<std::chrono::milliseconds>(end-start).count() <<\r\n        \" ms\" << std::endl;\r\n\r\n    long int res;\r\n    cudaMemcpy(&res, d_res, res_size, cudaMemcpyDeviceToHost);\r\n\r\n    return res;\r\n}\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/binary_search.h",
    "content": "#ifndef BINARY_SEARCH_H\r\n#define BINARY_SEARCH_H\r\n\r\n#ifdef _WIN32\r\n  #include <windows.h>\r\n  #define DLL_EXPORT __declspec(dllexport)\r\n#else\r\n  #define DLL_EXPORT\r\n#endif\r\n\r\n\r\nextern \"C\" {\r\n\r\n    int DLL_EXPORT binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys);\r\n\r\n}\r\n\r\n#endif /* BINARY_SEARCH_H */\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/cpu_lib.py",
    "content": "# -*- coding: utf-8 -*-\n\n\ndef binary_search(arr, search):\n\n    L = 0\n    R = len(arr)\n\n    while L <= R:\n\n        if L > R:\n            return -1  # Error code 1\n\n        m = (L + R) / 2\n        if arr[m] < search:\n            L = m + 1\n        elif arr[m] > search:\n            R = m - 1\n        else:\n            return m\n\n    return -2  # Error code 2\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/cu_lib_import.py",
    "content": "# -*- coding: utf-8 -*-\r\n\r\n__all__ = [\r\n    \"binary_search\",\r\n]\r\n\r\n\r\nimport os.path as path\r\nimport platform\r\nfrom ctypes import *\r\n\r\nfrom numpy.ctypeslib import load_library, ndpointer\r\n\r\n## Load the DLL\r\nif platform.system() == \"Linux\":\r\n    cuda_lib = load_library(\"cu_binary_search.so\", path.dirname(path.realpath(__file__)))\r\nelif platform.system() == \"Windows\":\r\n    cuda_lib = load_library(\"cu_binary_search.dll\", path.dirname(path.realpath(__file__)))\r\n\r\n\r\n## Define argtypes for all functions to import\r\nargtype_defs = {\r\n    \"binary_search\": [ndpointer(\"i8\"), c_int, ndpointer(\"i8\"), c_int],\r\n}\r\n\r\n\r\n## Import functions from DLL\r\nfor func, argtypes in argtype_defs.items():\r\n    locals().update({func: cuda_lib[func]})\r\n    locals()[func].argtypes = argtypes\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/baselines/gpu/run.py",
    "content": "# -*- coding: utf-8 -*-\n\nimport time\n\nimport numpy as np\n\n# Local Imports\nfrom cu_lib_import import binary_search as gpu_search\n\n# Set an array label to create\narr_len = 2048576\nnum_querys = 16777216\n\n# Dummy array created\narr = np.arange(0, arr_len, 1).astype(\"i8\")\n\n# Random search querys created\nquerys = np.random.randint(1, arr_len, num_querys)\n\n# GPU search function call\nt0 = time.time()\nres_gpu = gpu_search(arr, len(arr), querys, len(querys))\nprint(\"Total GPU Time: %i ms\" % ((time.time() - t0) * 1e003))\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/dpu/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/BS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(BS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/dpu/task.c",
    "content": "/*\n* Binary Search with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include <perfcounter.h>\n#include \"common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Search\nDTYPE __attribute__ ((noinline)) search(DTYPE *bufferA, DTYPE searching_for) {\n  DTYPE found = -2;\n  if(bufferA[0] <= searching_for)\n  {\n    found = -1;\n    for (uint32_t i = 0; i < BLOCK_SIZE / sizeof(DTYPE); i++){\n      if(bufferA[i] == searching_for)\n      {\n        found = i;\n        break;\n      }\n    }\n  }\n  return found;\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n  // Kernel\n  return kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n  unsigned int tasklet_id = me();\n  #if PRINT\n  printf(\"tasklet_id = %u\\n\", tasklet_id);\n  #endif\n  if(tasklet_id == 0){\n    mem_reset(); // Reset the heap\n  }\n  // Barrier\n  barrier_wait(&my_barrier);\n\n  DTYPE searching_for, found;\n  uint64_t input_size = DPU_INPUT_ARGUMENTS.input_size;\n\n  // Address of the current processing block in MRAM\n  uint32_t start_mram_block_addr_A       = (uint32_t) DPU_MRAM_HEAP_POINTER;\n  uint32_t start_mram_block_addr_aux     = start_mram_block_addr_A;\n  uint32_t end_mram_block_addr_A         = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n  uint32_t current_mram_block_addr_query = end_mram_block_addr_A + tasklet_id * (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS) * sizeof(DTYPE);\n\n  // Initialize a local cache to store the MRAM block\n  DTYPE *cache_A     = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_A = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_B = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n  dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n  // TODO(bongjoon.hyun@gmail.com): original PrIM benchmark uses uint64_t for targets' type\n  for(uint32_t targets = 0; targets < (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS); targets++)\n  {\n    found = -1;\n\n    mram_read((__mram_ptr void const *) current_mram_block_addr_query, &searching_for, 8);\n    current_mram_block_addr_query += 8;\n\n    bool end = false;\n\n    // Initialize input vector boundaries\n    start_mram_block_addr_A    = (uint32_t) DPU_MRAM_HEAP_POINTER;\n    start_mram_block_addr_aux  = start_mram_block_addr_A;\n    end_mram_block_addr_A      = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n\n    uint32_t current_mram_block_addr_A = start_mram_block_addr_A;\n\n    // Bring first and last values to WRAM\n    mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_aux_A, BLOCK_SIZE);\n    mram_read((__mram_ptr void const *) (end_mram_block_addr_A - BLOCK_SIZE * sizeof(DTYPE)),   cache_aux_B, BLOCK_SIZE);\n\n    current_mram_block_addr_A = (start_mram_block_addr_A + end_mram_block_addr_A) / 2;\n    while(!end)\n    {\n      // Load cache with current MRAM block\n      mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n\n      // Search inside block\n      found = search(cache_A, searching_for);\n\n      // If found > -1, we found the searching_for query\n      if(found > -1)\n      {\n        result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        break;\n      }\n\n      // If found == -2, we need to discard right part of the input vector\n      if(found == -2)\n      {\n        end_mram_block_addr_A     = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + start_mram_block_addr_A) / 2;\n      }\n\n      // If found == -1, we need to discard left part of the input vector\n      else if (found == -1)\n      {\n        start_mram_block_addr_A   = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + end_mram_block_addr_A) / 2;\n      }\n\n      // Start boundary check\n      if(current_mram_block_addr_A < (start_mram_block_addr_aux + BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          end = true;\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n\n      // End boundary check\n      if(current_mram_block_addr_A > (end_mram_block_addr_A - BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) end_mram_block_addr_A - BLOCK_SIZE, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n    }\n  }\n  return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\nstruct dpu_arguments_t{\n\tlong input_size;\n\tlong slice_per_dpu;\n\tint kernel;\n};\n\nstruct dpu_results_t {\n    long found;\n};\n\nvoid create_test_file(long * input, long * querys, long  nr_elements, long nr_querys) {\n\tinput[0] = 1;\n\tfor (long i = 1; i < nr_elements; i++) {\n\t\tinput[i] = input[i - 1] + 1;\n\t}\n\tfor (long i = 0; i < nr_querys; i++) {\n\t\tquerys[i] = i;\n\t}\n}\n\nlong binarySearch(long * input, long * querys, long input_size, long num_querys)\n{\n\tlong result = -1;\n\tlong r;\n\tfor(long q = 0; q < num_querys; q++)\n\t{\n\t\tlong l = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) {\n\t\t\tlong m = l + (r - l) / 2;\n\n\t\t\tif (input[m] == querys[q]) {\n\t\t\t    result = m;\n\t\t\t}\n\n\t\t\tif (input[m] < querys[q]) {\n\t\t\t    l = m + 1;\n\t\t\t} else {\n\t\t\t    r = m - 1;\n\t\t\t}\n\t\t}\n\t}\n\treturn result;\n}\n\nint main() {\n\tstruct dpu_set_t dpu_set;\n\tstruct dpu_set_t dpu;\n\tint nr_of_dpus = NUM_DPUS;\n\tlong input_size = DATA_PREP_PARAMS;\n\tlong num_querys = DATA_PREP_PARAMS / 8;\n\tlong result_host = -1;\n\tlong result_dpu  = -1;\n\n\tdpu_alloc(NUM_DPUS, NULL, &dpu_set);\n\tdpu_load(dpu_set, DPU_BINARY, NULL);\n\n\tif(num_querys % (nr_of_dpus * NUM_TASKLETS)) {\n\t    num_querys = num_querys + (nr_of_dpus * NUM_TASKLETS - num_querys % (nr_of_dpus * NUM_TASKLETS));\n    }\n    \n\tassert(num_querys % (nr_of_dpus * NUM_TASKLETS) == 0);\n\n\tlong * input  = malloc((input_size) * sizeof(long));\n\tlong * querys = malloc((num_querys) * sizeof(long));\n\n\tcreate_test_file(input, querys, input_size, num_querys);\n\n\tresult_host = binarySearch(input, querys, input_size - 1, num_querys);\n\n\tlong slice_per_dpu          = num_querys / nr_of_dpus;\n\tstruct dpu_arguments_t input_arguments;\n\tinput_arguments.input_size = input_size;\n\tinput_arguments.slice_per_dpu = slice_per_dpu;\n\tinput_arguments.kernel = 0;\n\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        dpu_prepare_xfer(dpu, &input_arguments);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        dpu_prepare_xfer(dpu, input);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size * sizeof(long), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        dpu_prepare_xfer(dpu, &querys[slice_per_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size * sizeof(long), slice_per_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        for(int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++)\n        {\n            if(results_retrieve[i * NUM_TASKLETS + each_tasklet].found > result_dpu)\n            {\n                result_dpu = results_retrieve[i * NUM_TASKLETS + each_tasklet].found;\n            }\n        }\n    }\n\n\tint status = (result_dpu == result_host);\n\tassert(status);\n\n\tfree(input);\n\tdpu_free(dpu_set);\n\n\treturn status ? 0 : 1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifdef TL\n#define TASKLETS_INITIALIZER TASKLETS(TL, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU TL\n#else\n#define TASKLETS_INITIALIZER TASKLETS(16, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU 16\n#endif\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int64_t\n\n// Vector size\n#define INPUT_SIZE 2048576\n\ntypedef struct {\n\tuint64_t input_size;\n\tuint64_t slice_per_dpu;\n\tenum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    DTYPE found;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n  long  num_querys;\n  unsigned   n_warmup;\n  unsigned   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    problem size (default=2 queries)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.num_querys    = PROBLEM_SIZE;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"h:i:w:e:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.num_querys    = atol(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break; \n\tdefault:\n        \tfprintf(stderr, \"\\nUnrecognized option!\\n\");\n        \tusage();\n        \texit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n  #endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/BS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\nproject(benchmark)\n\nadd_subdirectory(BS)\nadd_subdirectory(GEMV)\nadd_subdirectory(HST-L)\nadd_subdirectory(HST-S)\nadd_subdirectory(MLP)\nadd_subdirectory(RED)\nadd_subdirectory(SCAN-RSS)\nadd_subdirectory(SCAN-SSA)\nadd_subdirectory(SEL)\nadd_subdirectory(TRNS)\nadd_subdirectory(TS)\nadd_subdirectory(UNI)\nadd_subdirectory(VA)\nadd_subdirectory(VA_SIMPLE)\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/cpu/Makefile",
    "content": "all:\n\t\tgcc -o gemv -fopenmp gemv_openmp.c \n\nclean:\n\t\trm gemv\n\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/cpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/cpu/gemv_openmp.c",
    "content": "#include <stdlib.h>\n#include <stdio.h>\n#include \"../../support/timer.h\"\n#include \"gemv_utils.h\"\n\nint main(int argc, char *argv[])\n{\n  const size_t rows = 20480;\n  const size_t cols = 8192;\n\n  double **A, *b, *x;\n\n  b = (double*) malloc(sizeof(double)*rows);\n  x = (double*) malloc(sizeof(double)*cols);\n\n  allocate_dense(rows, cols, &A);\n\n  make_hilbert_mat(rows,cols, &A);\n\n#pragma omp parallel\n    {\n#pragma omp for\n    for (size_t i = 0; i < cols; i++) {\n      x[i] = (double) i+1 ;\n    }\n\n#pragma omp for\n    for (size_t i = 0; i < rows; i++) {\n      b[i] = (double) 0.0;\n    }\n    }\n\n  Timer timer;\n  start(&timer, 0, 0);\n\n\n   gemv(A, x, rows, cols, &b);\n   \n   stop(&timer, 0);\n\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n#if 0\n  print_vec(x, rows);\n  print_mat(A, rows, cols);\n  print_vec(b, rows);\n#endif\n\n  printf(\"sum(x) = %f, sum(Ax) = %f\\n\", sum_vec(x,cols), sum_vec(b,rows));\n  return 0;\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i ++ )\n  for (size_t j = 0; j < cols; j ++ ) {\n    (*b)[i] = (*b)[i] + A[i][j]*x[j];\n  }\n}\n\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      (*A)[i][j] = 1.0/( (double) i + (double) j + 1.0);\n    }\n  }\n}\n\ndouble sum_vec(double* vec, size_t rows) {\n  double sum = 0.0;\n#pragma omp parallel for reduction(+:sum)\n  for (int i = 0; i < rows; i++) sum = sum + vec[i];\n  return sum;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/cpu/gemv_utils.h",
    "content": "void allocate_dense(size_t rows,size_t  cols, double*** dense) {\n\n  *dense = malloc(sizeof(double)*rows);\n  **dense = malloc(sizeof(double)*rows*cols);\n\n  for (size_t i=0; i < rows; i++ ) {\n    (*dense)[i] = (*dense)[0] + i*cols;\n  }\n\n}\n\nvoid print_mat(double** A, size_t rows, size_t cols) {\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      printf(\"%f \", A[i][j]);\n    }\n    printf(\"\\n\");\n  }\n}\n\nvoid print_vec(double* b, size_t rows) {\n  for (size_t i = 0; i < rows; i++) {\n    printf(\"%f\\n\", b[i]);\n  }\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b);\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A);\ndouble sum_vec(double* vec, size_t rows);\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc gemv.cu -I/usr/local/cuda/include -lm -o gemv\n\nclean:\n\trm gemv\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/gpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/baselines/gpu/gemv.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n\n#define THREAD 128\n\n#define T int\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\nstruct timeval tv;\ngettimeofday(&tv, NULL);\nreturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n/* for CPU */\nint i, j;\nint *bdim, *c, *ans, *h_ans;\n//double start, stop;\n//double cpu_time, gpu_time;\nint n = 8192;\nint m = 20480;\n\nbdim = (T*)malloc(sizeof(T) *m*n);\nc = (T*)malloc(sizeof(T) *n);\nans = (T*)malloc(sizeof(T) *m);\nh_ans = (T*)malloc(sizeof(T) *m);\n\n/* for GPU */\nT *d_bdim, *d_c, *d_ans;\ncudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\ncudaMalloc((void **)&d_c, sizeof(T)*n);\ncudaMalloc((void **)&d_ans, sizeof(T)*m);\n\nfor(i = 0; i < n; i++)\n{\nc[i] = 1;\nfor(j = 0; j < m; j++)\nbdim[i*m+j] = 1;\n}\n\n//start = gettime();\ncgemv(m, n, bdim, c, ans);\n//stop = gettime();\n//cpu_time=stop - start;\n\n// Event creation\ncudaEvent_t start, stop;\ncudaEventCreate(&start);\ncudaEventCreate(&stop);\nfloat time1 = 0;\n\n\ncudaMemcpy(d_bdim, bdim, sizeof(T)*m*n, cudaMemcpyHostToDevice);\ncudaMemcpy(d_c, c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n// Start timer\ncudaEventRecord( start, 0 );\n//start = gettime();\ngemv<<<m, THREAD>>>(m, n, d_bdim, d_c, d_ans);\n//stop = gettime();\n// End timer\ncudaEventRecord( stop, 0 );\ncudaEventSynchronize( stop );\ncudaEventElapsedTime( &time1, start, stop );\n\n//gpu_time=stop - start;\n\ncudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\n//printf(\"cpu_time : %.6f[sec]\\n\",cpu_time);\n//printf(\"gpu_time : %.6f[sec]\\n\",gpu_time);\n//printf(\"%f x\\n\", cpu_time / gpu_time);\n\n\nfor(i = 0; i < m; i++)\nprintf(\"%d -- %d\\n\", ans[i], h_ans[i]);\n\nprintf(\"Execution time = %f ms\\n\", time1);\n\n\nfree(bdim);\nfree(c);\nfree(ans);\nfree(h_ans);\ncudaFree(d_bdim);\ncudaFree(d_c);\ncudaFree(d_ans);\n\nreturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\nint i;\nint div = n/THREAD;\n__shared__ T tmp[THREAD];\n\ntmp[threadIdx.x] = 0.0;\n\nfor(i = 0; i < div; i++)\n{\ntmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n}\nif(threadIdx.x < m%THREAD)\ntmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n__syncthreads();\n\nfor(i = THREAD / 2; i > 31; i = i / 2)\n{\nif(threadIdx.x < i)\ntmp[threadIdx.x] += tmp[threadIdx.x + i];\n__syncthreads();\n}\n\nif(threadIdx.x < 16)\n{\ntmp[threadIdx.x] += tmp[threadIdx.x + 16];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 8];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 4];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 2];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 1];\n__syncthreads();\n}\n\n\nif(threadIdx.x == 0)\nd_ans[blockIdx.x] = tmp[0];\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\nint i, j;\n\nfor(i = 0; i < m; i++)\nfor(j = 0; j < n; j++)\nd_ans[i] += adim[i*n+j] * b[j];\n\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/GEMV/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(GEMV_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\nstruct dpu_arguments_t {\n    int n_size;\n    int n_size_pad;\n    int nr_rows;\n    int max_rows;\n};\n\nstruct dpu_info_t {\n  int rows_per_dpu;\n  int rows_per_dpu_pad;\n  int prev_rows_dpu;\n};\n\nvoid init_data(int* A, int* B, int m_size, int n_size) {\n\tfor (int i = 0; i < m_size * n_size; i++)\n\t{\n\t\tA[i] = i % 50;\n\t}\n\n\tfor (int i = 0; i < n_size; i++)\n\t{\n\t\tB[i] = i % 50;\n\t}\n}\n\nvoid gemv_host(int* C, int* A, int* B, int m_size, int n_size) {\n\tfor (int i = 0; i < m_size; i++)\n\t{\n\t\tC[i] = 0;\n\t}\n\n\tfor (int m = 0; m < m_size; m++) {\n\t\tfor (int n = 0; n < n_size; n++)\n\t\t{\n\t\t\tC[m] += A[m * n_size + n] * B[n];\n\t\t}\n\t}\n}\n\nint main() {\n    int* A;\n    int* B;\n    int* C;\n    int* C_dpu;\n\n\tstruct dpu_set_t dpu_set;\n\tstruct dpu_set_t dpu;\n\tint nr_of_dpus = NUM_DPUS;\n\n\tdpu_alloc(NR_DPUS, NULL, &dpu_set);\n\tdpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int i;\n\tint m_size = DATA_PREP_PARAMS;\n\tint n_size = 64;\n\n\tstruct dpu_info_t* dpu_info = malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tstruct dpu_arguments_t *input_args = malloc(nr_of_dpus * sizeof(struct dpu_arguments_t));\n\tint max_rows_per_dpu = 0;\n\tint n_size_pad = n_size;\n\tif(n_size % 2 == 1)\n\t{\n\t\tn_size_pad++;\n\t}\n\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tint rows_per_dpu;\n\t\tint prev_rows_dpu = 0;\n\t\tint chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tint rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows) {\n\t\t\trows_per_dpu++;\n\t\t}\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows) {\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t\t}\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\tint rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) {\n\t\t\trows_per_dpu_pad++;\n        }\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu) {\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n        }\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = malloc(max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(int));\n\tB = malloc(n_size_pad * sizeof(int));\n\tC = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(int));\n\n\tinit_data(A, B, m_size, n_size);\n\n\tgemv_host(C, A, B, m_size, n_size);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        input_args[i].max_rows = max_rows_per_dpu;\n\n        dpu_prepare_xfer(dpu, &input_args[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &A[dpu_info[i].prev_rows_dpu * n_size]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, B);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) , n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    C_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(int));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &C_dpu[i * max_rows_per_dpu]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) + n_size_pad * sizeof(int), max_rows_per_dpu * sizeof(int), DPU_XFER_DEFAULT);\n\n\tint status = 1;\n\n\ti = 0;\n\tfor (int n = 0; n < nr_of_dpus; n++) {\n\t\tfor (int j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = 0;\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\n\tassert(status);\n\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tdpu_free(dpu_set);\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n    uint32_t rows_per_dpu;\n    uint32_t rows_per_dpu_pad;\n    uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=8192 elements)\"\n            \"\\n    -n <I>    n_size (default=8192 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 8192;\n    p.n_size        = 8192;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/GEMV/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nNR_HISTO ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_NR_DPUS_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${NR_DPUS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DNR_HISTO=${NR_HISTO} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(NR_HISTO 1)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/HST-L/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DNR_HISTO=${NR_HISTO}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(HST-L_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/dpu/task.c",
    "content": "/*\n* Histogram (HST-L) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n#include <atomic_bit.h>\n#include <mutex.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\nATOMIC_BIT_INIT(barriers_mutexes)[NR_HISTO];\nbarrier_t barriers[NR_HISTO];\n\n// Mutex\nmutex_id_t my_mutex[NR_HISTO];\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, uint32_t histo_id, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = (input[j] * bins) >> DEPTH;\n        mutex_lock(my_mutex[histo_id]);\n        histo[d] += 1;\n        mutex_unlock(my_mutex[histo_id]);\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    unsigned int l_tasklet_id = tasklet_id / NR_HISTO;\n    unsigned int nr_l_tasklet = NR_TASKLETS / NR_HISTO;\n    unsigned int my_histo_id = tasklet_id & (NR_HISTO - 1);\n\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n        // Initialize barriers\n        for (unsigned int each_barrier = 0; each_barrier < NR_HISTO; each_barrier++) {\n            barriers[each_barrier].wait_queue = 0xff;\n            barriers[each_barrier].count = nr_l_tasklet;\n            barriers[each_barrier].initial_count = nr_l_tasklet;\n            barriers[each_barrier].lock = (uint8_t) &ATOMIC_BIT_GET(barriers_mutexes)[each_barrier];\n        }\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    if (tasklet_id < NR_HISTO){ // Allocate DPU histogram\n        uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n        message[tasklet_id] = histo;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    uint32_t *my_histo = message[my_histo_id];\n\n    // Initialize local histogram\n    for(unsigned int i = l_tasklet_id; i < bins; i += nr_l_tasklet){\n        my_histo[i] = 0;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(my_histo, bins, cache_A, my_histo_id, l_size_bytes >> DIV);\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\n        for (unsigned int j = 0; j < NR_HISTO; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n    \t        mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define DEPTH 12\n\nstruct dpu_arguments_t {\n    int size;\n    int transfer_size;\n    int bins;\n\tint kernel;\n};\n\nvoid read_input(int* A, int input_size) {\n    for (int i = 0; i < input_size; i++) {\n        A[i] = i % 4096;\n    }\n}\n\nvoid histogram_host(int* histo, int* A, int bins, int nr_elements, int exp, int nr_of_dpus) {\n    if(!exp){\n        for (int i = 0; i < nr_of_dpus; i++) {\n            for (int j = 0; j < nr_elements; j++) {\n                int d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (int j = 0; j < nr_elements; j++) {\n            int d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    int* A;\n    int* histo_host;\n    int* histo;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n\n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int input_size = DATA_PREP_PARAMS;\n\n    int input_size_8bytes =  ((input_size * sizeof(int)) % 8) != 0 ? roundup(input_size, 8) : input_size;\n    int input_size_dpu = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_8bytes = ((input_size_dpu * sizeof(int)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu;\n\n    int bins = 256;\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    int *bufferA = A;\n    histo_host = malloc(bins * sizeof(int));\n    histo = malloc(nr_of_dpus * bins * sizeof(int));\n\n    read_input(A, input_size);\n\n    for (int i = 0; i < bins; i++) {\n        histo_host[i] = 0;\n    }\n\n    for (int i = 0; i < nr_of_dpus * bins; i++) {\n        histo[i] = 0;\n    }\n\n    histogram_host(histo_host, A, bins, input_size, 1, nr_of_dpus);\n\n    int kernel = 0;\n    struct dpu_arguments_t* input_arguments = malloc(NUM_DPUS * sizeof(struct dpu_arguments_t));\n    for(int i=0; i<nr_of_dpus-1; i++) {\n        input_arguments[i].size=input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].bins=bins;\n        input_arguments[i].kernel=kernel;\n    }\n    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NUM_DPUS-1)) * sizeof(int);\n    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(int);\n    input_arguments[nr_of_dpus-1].bins=bins;\n    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &histo[bins * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(int), bins * sizeof(int), DPU_XFER_DEFAULT);\n\n    for(int i = 1; i < nr_of_dpus; i++){\n        for(int j = 0; j < bins; j++){\n            histo[j] += histo[j + i * bins];\n        }\n    }\n\n    int status = 1;\n    for (int j = 0; j < bins; j++) {\n        if(histo_host[j] != histo[j]){\n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(histo_host);\n    free(histo);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n\t        NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n\t\t    wait\n            ./bin/host_code -w 2 -e 5 -b ${b} > profile/HSTL_${b}_tl${k}_dpu${i}.txt\n\t\t    wait\n\t\t    make clean\n\t\t    wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-L/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o hist -fopenmp app_baseline.c \n\nclean:\n\trm hist\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/cpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hist -y 1006632960 -t 4\n\nFor more options:\n\n    ./hsti -h\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/cpu/app_baseline.c",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n* The macros DPU_BINARY and NR_TASKLETS are directly\n* used in the static functions, and are not passed as arguments of these functions.\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  n_threads;\n}Params;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus, int t) {\n\n    omp_set_num_threads(t);\n\n    if(!exp){\n        #pragma omp parallel for\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        #pragma omp parallel for\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            #pragma omp atomic update\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Params ---------------------------------------------------------------------\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n    p.exp           = 1;\n    p.file_name     = \"../../input/image_VanHateren.iml\";\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    uint32_t nr_of_dpus;\n    \n    const unsigned int input_size = p.input_size; // Size of input image\n    if(!p.exp)\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n    else\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    if(!p.exp)\n        histo_host = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n        histo_host = malloc(p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    read_input(A, p);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n\tif(!p.exp)\n            memset(histo_host, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n            memset(histo_host, 0, p.bins * sizeof(unsigned int));\n\n    histogram_host(histo_host, A, p.bins, input_size, p.exp, nr_of_dpus, p.n_threads);\n\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L/usr/local/cuda/lib64 -lm\n\nINC=-I/usr/local/cuda/include\n\nDEP=kernel.cpp kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/partitioner.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cpp kernel.cu\nEXE=hsti\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hsti -n 1006632960 -g 512\n\nFor more options:\n\n    ./hsti -h\n\n\nNote:\nThe input folder contains one image from Van Hateren's natural image database \n(http://www.kyb.tuebingen.mpg.de/?id=227). Image pixels are 12-bit depth. Thus, \nfor calculation of the B-bin histogram of an image, the corresponding histogram \nbin is computed as ((pixel * B) >> 12).\nMonochrome images from other databases or synthetic images can also be used. The \nread input function (in main.cpp) might need to be changed accordingly. If image \npixels are b-bit depth and the histogram contains B bins, the histogram bin will \nbe computed as ((pixel * B) >> b).\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include \"support/partitioner.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads--------------------------------------------------------------------------------------\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int n_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *worklist\n#endif\n    ) {\n    std::vector<std::thread> cpu_threads;\n    for(int k = 0; k < n_threads; k++) {\n        cpu_threads.push_back(std::thread([=]() {\n\n#ifdef CUDA_8_0\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads, worklist);\n#else\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads);\n#endif\n\n            unsigned int Hs[bins];\n            // Local histogram initialization\n            for(int i = 0; i < bins; i++) {\n                Hs[i] = 0;\n            }\n\n            for(int i = cpu_first(&p); cpu_more(&p); i = cpu_next(&p)) {\n                for(int j = 0; j < chunk; j++) {\n                    // Read pixel\n                    unsigned int d = ((data[i * chunk + j] * bins) >> 12);\n\n                    // Vote in histogram\n                    Hs[d]++;\n                }\n            }\n\n            // Merge to global histogram\n            for(int i = 0; i < bins; i++) {\n                (&histo[i])->fetch_add(Hs[i]);\n            }\n\n        }));\n    }\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#define _CUDA_COMPILER_\n\n#include \"support/common.h\"\n#include \"support/partitioner.h\"\n\n// CUDA kernel ------------------------------------------------------------------------------------------\n__global__ void Histogram_kernel(int size, int bins, int n_tasks, float alpha, unsigned int *data,\n    unsigned int *histo\n#ifdef CUDA_8_0\n    , int *worklist\n#endif\n    ) {\n\n    extern __shared__ unsigned int l_mem[];\n    unsigned int* l_histo = l_mem;\n#ifdef CUDA_8_0\n    int* l_tmp = (int*)&l_histo[bins];\n#endif\n    \n#ifdef CUDA_8_0\n    Partitioner p = partitioner_create(n_tasks, alpha, worklist, l_tmp);\n#else\n    Partitioner p = partitioner_create(n_tasks, alpha);\n#endif\n    \n    // Block and runtime index\n    const int bx = blockIdx.x;\n    const int tx = threadIdx.x;\n    const int bD = blockDim.x;\n    const int gD = gridDim.x;\n\n    // Sub-histograms initialization\n    for(int pos = tx; pos < bins; pos += bD) {\n        l_histo[pos] = 0;\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Main loop\n    for(int i = gpu_first(&p); gpu_more(&p); i = gpu_next(&p)) {\n    \n        // Global memory read\n        unsigned int d = data[i * bD + tx];\n\n        // Atomic vote in shared memory\n        atomicAdd(&l_histo[((d * bins) >> 12)], 1);\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Merge per-block histograms and write to global memory\n    for(int pos = tx; pos < bins; pos += bD) {\n// Atomic addition in global memory\n#ifdef CUDA_8_0\n        atomicAdd_system(histo + pos, l_histo[pos]);\n#else\n        atomicAdd(histo + pos, l_histo[pos]);\n#endif\n    }\n}\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n    ){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    Histogram_kernel<<<dimGrid, dimBlock, l_mem_size>>>(size, bins, n_tasks, alpha, \n        data, histo\n#ifdef CUDA_8_0\n        , worklist\n#endif\n        );\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda_runtime.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int num_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *wl\n#endif\n    );\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n\t\t);\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int   device;\n    int   n_gpu_threads;\n    int   n_gpu_blocks;\n    int   n_threads;\n    int   n_warmup;\n    int   n_reps;\n    float alpha;\n    int   in_size;\n    int   n_bins;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 256;\n        n_gpu_blocks = 16;\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        alpha         = 0.2;\n        in_size       = 1536 * 1024 * 640;\n        n_bins        = 256;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:a:n:b:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'a': alpha         = atof(optarg); break;\n            case 'n': in_size       = atoi(optarg); break;\n            case 'b': n_bins        = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        if(alpha == 0.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n        } else if(alpha == 1.0) {\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else if(alpha > 0.0 && alpha < 1.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else {\n#ifdef CUDA_8_0\n            assert((n_gpu_threads > 0 && n_gpu_blocks > 0 || n_threads > 0) && \"Invalid # of host + device workers!\");\n#else\n            assert(0 && \"Illegal value for -a\");\n#endif\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./hsti [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=256)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    -a <A>    fraction of input elements to process on host (default=0.2)\"\n#ifdef CUDA_8_0\n                \"\\n              NOTE: Dynamic partitioning used when <A> is not between 0.0 and 1.0\"\n#else\n                \"\\n              NOTE: <A> must be between 0.0 and 1.0\"\n#endif\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n                \"\\n    -n <N>    input size (default=1572864, i.e., 1536x1024)\"\n                \"\\n    -b <B>    # of bins in histogram (default=256)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(unsigned int *input, const Params &p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, \"./input/image_VanHateren.iml\");\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(int y = 0; y < p.in_size; y++) {\n            int fr   = fread(&temp, sizeof(unsigned short), 1, File);\n            input[y] = (unsigned int)ByteSwap16(temp);\n            if(input[y] >= 4096)\n                input[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate buffers\n    timer.start(\"Allocation\");\n    int n_tasks = divceil(p.in_size, p.n_gpu_threads);\n#ifdef CUDA_8_0\n    unsigned int *h_in;\n    cudaStatus = cudaMallocManaged(&h_in, p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo;\n    cudaStatus = cudaMallocManaged(&h_histo, p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    d_in     = h_in;\n    std::atomic_uint *d_histo  = h_histo;\n    std::atomic_int * worklist;\n    cudaStatus = cudaMallocManaged(&worklist, sizeof(std::atomic_int));\n#else\n    unsigned int *    h_in          = (unsigned int *)malloc(p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo       = (std::atomic_uint *)malloc(p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    h_histo_merge = (unsigned int *)malloc(p.n_bins * sizeof(unsigned int));\n    unsigned int *    d_in;\n    cudaStatus = cudaMalloc((void**)&d_in, p.in_size * sizeof(unsigned int));\n    unsigned int *    d_histo;\n    cudaStatus = cudaMalloc((void**)&d_histo, p.n_bins * sizeof(unsigned int));\n    ALLOC_ERR(h_in, h_histo, h_histo_merge);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in, p);\n#ifdef CUDA_8_0\n    for(int i = 0; i < p.n_bins; i++) {\n        h_histo[i].store(0);\n    }\n#else\n    memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n#endif\n    cudaDeviceSynchronize();\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n\n#ifndef CUDA_8_0\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    cudaStatus = cudaMemcpy(d_in, h_in, p.in_size * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaDeviceSynchronize();\n    CUDA_ERR();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n#endif\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n#ifdef CUDA_8_0\n        if(p.alpha < 0.0 || p.alpha > 1.0) { // Dynamic partitioning\n            worklist[0].store(0);\n        }\n        for(int i = 0; i < p.n_bins; i++) {\n            h_histo[i].store(0);\n        }\n#else\n        memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n        cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n        cudaDeviceSynchronize();\n        CUDA_ERR();\n#endif\n\n        if(rep >= p.n_warmup)\n            timer.start(\"Kernel\");\n\n        p.n_gpu_blocks = p.in_size / p.n_gpu_threads;\n\n        // Launch GPU threads\n        // Kernel launch\n        if(p.n_gpu_blocks > 0) {\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n            cudaStatus = call_Histogram_kernel(p.n_gpu_blocks, p.n_gpu_threads, p.in_size, p.n_bins, n_tasks, \n                p.alpha, d_in, (unsigned int*)d_histo, p.n_bins * sizeof(unsigned int)\n#ifdef CUDA_8_0\n                + sizeof(int), (int*)worklist\n#endif\n                );\n            CUDA_ERR();\n        }\n\n        // Launch CPU threads\n        std::thread main_thread(run_cpu_threads, h_histo, h_in, p.in_size, p.n_bins, p.n_threads, p.n_gpu_threads,\n            n_tasks, p.alpha\n#ifdef CUDA_8_0\n            , worklist\n#endif\n            );\n\n        cudaDeviceSynchronize();\n        main_thread.join();\n\n        if(rep >= p.n_warmup)\n            timer.stop(\"Kernel\");\n    }\n    timer.print(\"Kernel\", p.n_reps);\n\n#ifndef CUDA_8_0\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    cudaStatus = cudaMemcpy(h_histo_merge, d_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyDeviceToHost);\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    for(unsigned int i = 0; i < p.n_bins; ++i) {\n        h_histo_merge[i] += (unsigned int)h_histo[i];\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n#endif\n\n    // Verify answer\n#ifdef CUDA_8_0\n    verify((unsigned int *)h_histo, h_in, p.in_size, p.n_bins);\n#else\n    verify((unsigned int *)h_histo_merge, h_in, p.in_size, p.n_bins);\n#endif\n\n    // Free memory\n    timer.start(\"Deallocation\");\n#ifdef CUDA_8_0\n    cudaStatus = cudaFree(h_in);\n    cudaStatus = cudaFree(h_histo);\n    cudaStatus = cudaFree(worklist);\n#else\n    free(h_in);\n    free(h_histo);\n    free(h_histo_merge);\n    cudaStatus = cudaFree(d_in);\n    cudaStatus = cudaFree(d_histo);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Kernel\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/support/partitioner.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#ifndef _PARTITIONER_H_\r\n#define _PARTITIONER_H_\r\n\r\n#ifndef _CUDA_COMPILER_\r\n#include <iostream>\r\n#endif\r\n\r\n#if !defined(_CUDA_COMPILER_) && defined(CUDA_8_0)\r\n#include <atomic>\r\n#endif\r\n\r\n// Partitioner definition -----------------------------------------------------\r\n\r\ntypedef struct Partitioner {\r\n\r\n    int n_tasks;\r\n    int cut;\r\n    int current;\r\n#ifndef _CUDA_COMPILER_\r\n    int thread_id;\r\n    int n_threads;\r\n#endif\r\n\r\n\r\n#ifdef CUDA_8_0\r\n    // CUDA 8.0 support for dynamic partitioning\r\n    int strategy;\r\n#ifdef _CUDA_COMPILER_\r\n    int *worklist;\r\n    int *tmp;\r\n#else\r\n    std::atomic_int *worklist;\r\n#endif\r\n#endif\r\n\r\n} Partitioner;\r\n\r\n// Partitioning strategies\r\n#define STATIC_PARTITIONING 0\r\n#define DYNAMIC_PARTITIONING 1\r\n\r\n// Create a partitioner -------------------------------------------------------\r\n\r\n#ifdef _CUDA_COMPILER_\r\n__device__\r\n#endif\r\ninline Partitioner partitioner_create(int n_tasks, float alpha\r\n#ifndef _CUDA_COMPILER_\r\n    , int thread_id, int n_threads\r\n#endif\r\n#ifdef CUDA_8_0\r\n#ifdef _CUDA_COMPILER_\r\n    , int *worklist\r\n    , int *tmp\r\n#else\r\n    , std::atomic_int *worklist\r\n#endif\r\n#endif\r\n    ) {\r\n    Partitioner p;\r\n    p.n_tasks = n_tasks;\r\n#ifndef _CUDA_COMPILER_\r\n    p.thread_id = thread_id;\r\n    p.n_threads = n_threads;\r\n#endif\r\n    if(alpha >= 0.0 && alpha <= 1.0) {\r\n        p.cut = p.n_tasks * alpha;\r\n#ifdef CUDA_8_0\r\n        p.strategy = STATIC_PARTITIONING;\r\n#endif\r\n    } else {\r\n#ifdef CUDA_8_0\r\n        p.strategy = DYNAMIC_PARTITIONING;\r\n        p.worklist = worklist;\r\n#ifdef _CUDA_COMPILER_\r\n        p.tmp = tmp;\r\n#endif\r\n#endif\r\n    }\r\n    return p;\r\n}\r\n\r\n// Partitioner iterators: first() ---------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->thread_id;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->cut + blockIdx.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: more() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline bool cpu_more(const Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        return (p->current < p->n_tasks);\r\n    } else\r\n#endif\r\n    {\r\n        return (p->current < p->cut);\r\n    }\r\n}\r\n\r\n#else\r\n\r\n__device__ inline bool gpu_more(const Partitioner *p) {\r\n    return (p->current < p->n_tasks);\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: next() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + p->n_threads;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + gridDim.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n#include <string.h>\n\ninline int compare_output(unsigned int *outp, unsigned int *outpCPU, int bins) {\n    for(int i = 0; i < bins; i++) {\n        if(outp[i] != outpCPU[i]) {\n            printf(\"Test failed\\n\");\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential implementation for comparison purposes\ninline void HistogramCPU(unsigned int *histo, unsigned int *data, int size, int bins) {\n    for(int i = 0; i < size; i++) {\n        // Read pixel\n        unsigned int d = ((data[i] * bins) >> 12);\n        // Vote in histogram\n        histo[d]++;\n    }\n}\n\ninline void verify(unsigned int *histo, unsigned int *input, int size, int bins) {\n    unsigned int *gold = (unsigned int *)malloc(bins * sizeof(unsigned int));\n    memset(gold, 0, bins * sizeof(unsigned int));\n    HistogramCPU(gold, input, size, bins);\n    compare_output(histo, gold, bins);\n    free(gold);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/HST-S/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(HST-S_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/dpu/task.c",
    "content": "/*\n* Histogram (HST-S) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = input[j];\n        histo[(d * bins) >> DEPTH] += 1;\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n\n    // Initialize local histogram\n    for(unsigned int i = 0; i < bins; i++){\n        histo[i] = 0;\n    }\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(histo, bins, cache_A, l_size_bytes >> DIV);\n\n    }\n    message[tasklet_id] = histo;\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\t\t\n        for (unsigned int j = 0; j < NR_TASKLETS; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n                mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define DEPTH 12\n\nstruct dpu_arguments_t {\n    int size;\n    int transfer_size;\n    int bins;\n\tint kernel;\n};\n\nvoid read_input(int* A, int input_size) {\n    for (int i = 0; i < input_size; i++) {\n        A[i] = i % 4096;\n    }\n}\n\nvoid histogram_host(int* histo, int* A, int bins, int nr_elements, int exp, int nr_of_dpus) {\n    if(!exp){\n        for (int i = 0; i < nr_of_dpus; i++) {\n            for (int j = 0; j < nr_elements; j++) {\n                int d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (int j = 0; j < nr_elements; j++) {\n            int d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    int* A;\n    int* histo_host;\n    int* histo;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n   \n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int input_size = DATA_PREP_PARAMS;\n\n    int input_size_8bytes =  ((input_size * sizeof(int)) % 8) != 0 ? roundup(input_size, 8) : input_size;\n    int input_size_dpu = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_8bytes = ((input_size_dpu * sizeof(int)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu;\n\n    int bins = 256;\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    int *bufferA = A;\n    histo_host = malloc(bins * sizeof(int));\n    histo = malloc(nr_of_dpus * bins * sizeof(int));\n\n    read_input(A, input_size);\n\n    for (int i = 0; i < bins; i++) {\n        histo_host[i] = 0;\n    }\n\n    for (int i = 0; i < nr_of_dpus * bins; i++) {\n        histo[i] = 0;\n    }\n\n    histogram_host(histo_host, A, bins, input_size, 1, nr_of_dpus);\n\n    int kernel = 0;\n    struct dpu_arguments_t* input_arguments = malloc(NUM_DPUS * sizeof(struct dpu_arguments_t));\n    for(int i=0; i<nr_of_dpus-1; i++) {\n        input_arguments[i].size=input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].bins=bins;\n        input_arguments[i].kernel=kernel;\n    }\n    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NUM_DPUS-1)) * sizeof(int);\n    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(int);\n    input_arguments[nr_of_dpus-1].bins=bins;\n    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &histo[bins * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(int), bins * sizeof(int), DPU_XFER_DEFAULT);\n\n    for(int i = 1; i < nr_of_dpus; i++){\n        for(int j = 0; j < bins; j++){\n            histo[j] += histo[j + i * bins];\n        }\n    }\n\n    int status = 1;\n    for (int j = 0; j < bins; j++) {\n        if(histo_host[j] != histo[j]){\n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(histo_host);\n    free(histo);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n            NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n            wait\n            ./bin/host_code -w 2 -e 5 -b ${b} -x 1 > profile/HSTS_${b}_tl${k}_dpu${i}.txt\n            wait\n            make clean\n            wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/HST-S/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/cpu/Makefile",
    "content": "all:\n\tgcc mlp_openmp.c -o mlp_openmp -fopenmp -std=c99\nrun:\n\t./mlp_openmp\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/cpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp_openmp\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/cpu/mlp_openmp.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include \"../../support/timer.h\"\n#include \"../../support/common.h\"\n\nT** A;\nT* B;\nT* C;\n\n// Create input arrays\nstatic void init_data(T** A, T* B, unsigned int m_size, unsigned int n_size){\n    for (unsigned int l = 0; l < NUM_LAYERS; l++)\n\t\tfor (unsigned int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l][i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l][i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\tfor (unsigned int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t}\n}\n\n// Compute output in the host\nstatic void mlp_host(T* C, T** A, T* B, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\t#pragma omp parallel for\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl][m * n_size + n] * B[n];\n\t\t\t}\n\t\t\tC[m] = max(0, C[m]);\n\t\t}\n\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\nstatic uint64_t mlp_host_sum(uint64_t n_size, uint64_t m_size) {\n  uint64_t sum = 0;\n  for (uint64_t m = 0; m < n_size; m++){\n    sum += B[m];\n  }\n  return sum;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  char* dpu_type;\n  int   nr_of_ranks;\n  int   input_size_n;\n  int   input_size_m;\n  int   n_warmup;\n  int   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -d <D>    DPU type (default=fsim)\"\n    \"\\n    -r <R>    # of ranks (default=2)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    input size (default=8M elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.dpu_type      = \"fsim\";\n    p.nr_of_ranks   = 1;\n    p.input_size_n  = 1 << 9;\n    p.input_size_m  = 1 << 9;\n    p.n_warmup      = 2;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:r:i:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'd': p.dpu_type        = optarg; break;\n        case 'r': p.nr_of_ranks     = atoi(optarg); break;\n        case 'n': p.input_size_n    = atoi(optarg); break;\n        case 'm': p.input_size_m    = atoi(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(p.nr_of_ranks > 0 && \"Invalid # of ranks!\");\n\n    return p;\n  }\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n    uint64_t n_size = 8192;\n    uint64_t m_size = 20480;\n\n    Timer timer;\n    A = malloc(NUM_LAYERS * sizeof(T*));\n    for(int l = 0; l < NUM_LAYERS; l++)\n        A[l] = malloc(n_size*m_size*sizeof(unsigned int));\n    B = malloc(m_size*sizeof(unsigned int));\n    C = malloc(m_size*sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    init_data(A, B, m_size, n_size);\n\n    start(&timer, 0, 1);\n    mlp_host(C, A, B, n_size, m_size);\n    stop(&timer, 0);\n\n    uint32_t sum = mlp_host_sum(n_size, m_size);\n   \n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    printf(\"SUM = %d \\n\", sum);\n\n    for(int l = 0; l < NUM_LAYERS; l++)\n        free(A[l]);\n    free(A);\n    free(B);\n    free(C);\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc mlp.cu -I/usr/local/cuda/include -lm -o mlp\n\nclean:\n\trm mlp\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/gpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/baselines/gpu/mlp.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n#include \"../../support/common.h\"\n\n#define THREAD 128\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\n\tstruct timeval tv;\n\tgettimeofday(&tv, NULL);\n\treturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n\t/* for CPU */\n\tint i, j;\n\tT **bdim; \n\tT *c, *ans, *h_ans, *h_c;\n\tint n = 8192;\n\tint m = 20480;\n\n\tbdim = (T**) malloc(NUM_LAYERS * sizeof(T*));\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tbdim[l] = (T*)malloc(sizeof(T)*m*n);\n\tc = (T*)malloc(sizeof(T) *n);\n\th_c = (T*)malloc(sizeof(T) *n);\n\tans = (T*)malloc(sizeof(T) *m);\n\th_ans = (T*)malloc(sizeof(T) *m);\n\n\t/* for GPU */\n\tT *d_bdim; \n\tT *d_c, *d_ans;\n\tcudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\n\tcudaMalloc((void **)&d_c, sizeof(T)*n);\n\tcudaMalloc((void **)&d_ans, sizeof(T)*m);\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(i % 50 < 48)\n\t\t{\n\t\t\tc[i] = 0;\n\t\t\th_c[i] = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tc[i] = i % 2;\n\t\t\th_c[i] = i % 2;\n\t\t}\n\t}\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfor(i = 0; i < n; i++)\n\t\t{\n\t\t\tfor(j = 0; j < m; j++){\n\t\t\t\tif(j % 100 < 98)\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = 0;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = (l + i) % 2;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tfor(j = 0; j < m; j++){\n\t\tans[j] = 0;\n\t\th_ans[j] = 0;\n\t}\n\t// Computation on the host for verification\n\tT* vector = c;\n\tT* output = ans;\n\tT* matrix;\n\tint mm = m;\n\tint nn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tmatrix = bdim[l];\n\t\tcgemv(mm, nn, matrix, vector, output);\n\t\tvector = output;\n                h_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\t// Event creation\n\tcudaEvent_t start, stop;\n\tcudaEventCreate(&start);\n\tcudaEventCreate(&stop);\n\tfloat time1 = 0;\n\tfloat time2 = 0;\n\tcudaMemcpy(d_ans, h_ans, sizeof(T)*m, cudaMemcpyHostToDevice);\n\tcudaMemcpy(d_c, h_c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n\tvector = d_c;\n\toutput = d_ans;\n\tmm = m;\n\tnn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tcudaMemcpy(d_bdim, bdim[l], sizeof(T)*m*n, cudaMemcpyHostToDevice);\n\t\tmatrix = d_bdim;\n\t\t// Start timer\n\t\tcudaEventRecord( start, 0 );\n\t\tgemv<<<mm, THREAD>>>(mm, nn, matrix, vector, output);\n\t\t// End timer\n\t\tcudaEventRecord( stop, 0 );\n\t\tcudaEventSynchronize( stop );\n\t\tcudaEventElapsedTime( &time2, start, stop );\n\t\ttime1 += time2;\n\t\tvector = output;\n\t\td_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\tcudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\tcudaMemcpy(h_c, d_c, sizeof(T)*n, cudaMemcpyDeviceToHost);\n\n\tfor(i = 0; i < m; i++)\n\t{\n\t\tif(ans[i] != h_ans[i])\n\t\tprintf(\"ERROR in Ans %d -> %d -- %d\\n\", i, ans[i], h_ans[i]);\n        }\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(c[i] != h_c[i])\n\t\tprintf(\"ERROR in C %d -> %d -- %d\\n\", i, c[i], h_c[i]);\n\t}\n\tprintf(\"Execution time = %f ms\\n\", time1);\n\n\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfree(bdim[l]);\n\n\n\tfree(bdim);\n\tfree(c);\n\tfree(ans);\n\tfree(h_c);\n\tcudaFree(d_bdim);\n\tcudaFree(d_c);\n\tcudaFree(d_ans);\n\tcudaEventDestroy(start);\n\tcudaEventDestroy(stop);\n\n\treturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\n\tint i;\n\tint div = n/THREAD;\n\t__shared__ T tmp[THREAD];\n\n\ttmp[threadIdx.x] = 0.0;\n\n\tfor(i = 0; i < div; i++){\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n\t}\n\tif(threadIdx.x < m%THREAD)\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n\t__syncthreads();\n\n\tfor(i = THREAD / 2; i > 31; i = i / 2)\n\t{\n\t\tif(threadIdx.x < i)\n\t\t\ttmp[threadIdx.x] += tmp[threadIdx.x + i];\n\t\t__syncthreads();\n\t}\n\n\tif(threadIdx.x < 16)\n\t{\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 16];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 8];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 4];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 2];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 1];\n\t\t__syncthreads();\n\t}\n\n\n\tif(threadIdx.x == 0)\n\t\td_ans[blockIdx.x] = max(0, tmp[0]);\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\n\tint i, j;\n\n\tfor(i = 0; i < m; i++){\n\t\tfor(j = 0; j < n; j++)\n\t\t\td_ans[i] += adim[i*n+j] * b[j];\n\t\td_ans[i] = max(0, d_ans[i]);\n\t}\n\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/MLP/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(MLP_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define NUM_LAYERS 3\n\nstruct dpu_arguments_t {\n    int n_size;\n    int n_size_pad;\n    int nr_rows;\n    int max_rows;\n};\n\nstruct dpu_info_t {\n  int rows_per_dpu;\n  int rows_per_dpu_pad;\n  int prev_rows_dpu;\n};\n\nvoid init_data(int* A, int* B, int* B_host, int m_size, int n_size) {\n\tfor (int l = 0; l < NUM_LAYERS; l++) {\n\t\tfor (int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l * m_size * n_size + i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l * m_size * n_size + i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t\tB_host[i] = B[i];\n\t}\n}\n\nvoid mlp_host(int* C, int* A, int* B, int m_size, int n_size) {\n\tfor (int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\tfor (int m = 0; m < m_size; m++){\n\t\t\tfor (int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl * m_size + n_size + m * n_size + n] * B[n];\n\t\t\t}\n\n\t\t\tif (C[m] < 0) {\n\t\t\t    C[m] = 0;\n\t\t\t}\n\t\t}\n\t\tfor (int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\nint main() {\n    int* A;\n    int* B;\n    int* B_host;\n    int* B_tmp;\n    int* C;\n    int* C_dpu;\n\n\tstruct dpu_set_t dpu_set;\n\tstruct dpu_set_t dpu;\n\tint nr_of_dpus = NUM_DPUS;\n\n\tdpu_alloc(NR_DPUS, NULL, &dpu_set);\n\tdpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int i;\n    int l;\n\tint m_size = DATA_PREP_PARAMS;\n\tint n_size = DATA_PREP_PARAMS;\n\n\tstruct dpu_info_t* dpu_info = malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tstruct dpu_arguments_t *input_args = malloc(nr_of_dpus * sizeof(struct dpu_arguments_t));\n\tint max_rows_per_dpu = 0;\n\tint n_size_pad = n_size;\n\tif(n_size % 2 == 1){\n\t\tn_size_pad++;\n\t}\n\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tint rows_per_dpu;\n\t\tint prev_rows_dpu = 0;\n\t\tint chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tint rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows) {\n\t\t\trows_per_dpu++;\n\t\t}\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows) {\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t\t}\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\tint rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) {\n\t\t\trows_per_dpu_pad++;\n\t\t}\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu) {\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n\t\t}\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = malloc(NUM_LAYERS * max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(int));\n\tB = malloc(n_size * sizeof(int));\n\tB_host = malloc(n_size * sizeof(int));\n\tC = malloc(m_size * sizeof(int));\n\tC_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(int));\n\tB_tmp = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(int));\n\n\tinit_data(A, B, B_host, m_size, n_size);\n\tmlp_host(C, A, B_host, m_size, n_size);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        input_args[i].max_rows = max_rows_per_dpu;\n        dpu_prepare_xfer(dpu, &input_args[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &A[dpu_info[i].prev_rows_dpu * n_size]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, B);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) , n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    for(int lay = 1; lay < NUM_LAYERS; lay++){\n        i = 0;\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, &C_dpu[i * max_rows_per_dpu]);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) + n_size_pad * sizeof(int), max_rows_per_dpu * sizeof(int), DPU_XFER_DEFAULT);\n\n        for (int n = 0; n < nr_of_dpus; n++) {\n            for (int j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n                B_tmp[i] = C_dpu[n * max_rows_per_dpu + j];\n                i++;\n            }\n        }\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, B_tmp);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) , n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, &A[lay * max_rows_per_dpu * nr_of_dpus * n_size_pad + dpu_info[i].prev_rows_dpu * n_size]);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(int), DPU_XFER_DEFAULT);\n\n        dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n    }\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &C_dpu[i * max_rows_per_dpu]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(int) + n_size_pad * sizeof(int), max_rows_per_dpu * sizeof(int), DPU_XFER_DEFAULT);\n\n\tint status = 1;\n\ti = 0;\n\tfor (int n = 0; n < nr_of_dpus; n++) {\n\t\tfor (int j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = 0;\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\n\tassert(status);\n\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tdpu_free(dpu_set);\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n  uint32_t rows_per_dpu;\n  uint32_t rows_per_dpu_pad;\n  uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n#define NUM_LAYERS 3 \n#define max(x, y) (x > y ? x : y)\n#define min(x, y) (x < y ? x : y)\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=2048 elements)\"\n            \"\\n    -n <I>    n_size (default=2048 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 163840;\n    p.n_size        = 4096;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/MLP/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nVERSION ?= SINGLE\nSYNC ?= HAND\nTYPE ?= INT64\nENERGY ?= 0\nPERF ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_VERSION_$(4)_SYNC_$(5)_TYPE_$(6).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${VERSION},${SYNC},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DENERGY=${ENERGY} -DPERF=${PERF}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DPERF=${PERF}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -w 0 -e 1 -i 6553600 -x 1\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/cpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000 -t 4\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 1;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\t\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        thrust::omp::vector<T> d_input(input_size);\n        memcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        count = thrust::reduce(thrust::omp::par, d_input.begin(), d_input.end());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n        h_output = d_input;\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/gpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 160 * 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        count = thrust::reduce(d_input.begin(),d_input.end());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n\tcudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\nSET(VERSION SINGLE)\r\nSET(SYNC HAND)\r\nSET(PERF 0)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/RED/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DPERF=${PERF}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(RED_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/dpu/task.c",
    "content": "/*\n* Reduction with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input, unsigned int l_size){\n    T output = 0;\n    for (unsigned int j = 0; j < l_size; j++){\n        output += input[j];\n    }\n    return output;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n#if PERF\n        perfcounter_config(COUNT_CYCLES, true);\n#endif\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n#if PERF && !PERF_SYNC\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n#if !PERF_SYNC // COMMENT OUT TO COMPARE SYNC PRIMITIVES (Experiment in Appendix)\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\t\t\n        // Reduction in each tasklet\n        l_count += reduction(cache_A, l_size_bytes >> DIV);\n\n    }\n#endif\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n#ifdef TREE // Tree-based reduction\n#ifdef BARRIER\n    // Barrier\n    barrier_wait(&my_barrier);\n#endif\n\n    #pragma unroll\n    for (unsigned int offset = 1; offset < NR_TASKLETS; offset <<= 1){\n\n        if((tasklet_id & (2*offset - 1)) == 0){\n#ifndef BARRIER\n            // Wait\n            handshake_wait_for(tasklet_id + offset);\n#endif\n            message[tasklet_id] += message[tasklet_id + offset];\n        }\n\n#ifdef BARRIER\n        // Barrier\n        barrier_wait(&my_barrier);\n#else\n        else if ((tasklet_id & (offset - 1)) == 0){ // Ensure that wait and notify are in pair\n            // Notify\n            handshake_notify();\n        }\n#endif\n\n    }\n\n#else  // Single-thread reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0)\n        #pragma unroll\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n#endif\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    // Total count in this DPU\n    if(tasklet_id == 0){\n        result->t_count = message[tasklet_id];\n    }\n\n#if PERF && !PERF_SYNC\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\nstruct dpu_arguments_t{\n    int size;\n\tint kernel;\n    long t_count;\n};\n\nstruct dpu_results_t{\n    long cycles;\n    long t_count;\n};\n\nvoid read_input(long* A, int nr_elements) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i % 100;\n    }\n}\n\nlong reduction_host(long* A, int nr_elements) {\n    long count = 0;\n    for (int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    long* A;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n\n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int input_size = DATA_PREP_PARAMS;\n    int input_size_8bytes = ((input_size * sizeof(long)) % 8) != 0 ? roundup(input_size, 8) : input_size;\n    int input_size_dpu = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_8bytes = ((input_size_dpu * sizeof(long)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu;\n\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(long));\n    long *bufferA = A;\n    long count = 0;\n    long count_host = 0;\n\n    read_input(A, input_size);\n\n    count_host = reduction_host(A, input_size);\n\n    count = 0;\n    int kernel = 0;\n    struct dpu_arguments_t* input_arguments = malloc(NUM_DPUS * sizeof(struct dpu_arguments_t));\n    for(int i=0; i<nr_of_dpus-1; i++) {\n        input_arguments[i].size=input_size_dpu_8bytes * sizeof(long);\n        input_arguments[i].kernel=kernel;\n    }\n    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NUM_DPUS-1)) * sizeof(long);\n    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results = malloc(nr_of_dpus * sizeof(struct dpu_results_t));\n    long* results_count = malloc(nr_of_dpus * sizeof(long));\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(each_tasklet == 0) {\n                results[i].t_count = results_retrieve[i * NUM_TASKLETS + each_tasklet].t_count;\n            }\n        }\n\n        count += results[i].t_count;\n    }\n\n    int status = 1;\n    if(count != count_host) {\n        status = 0;\n    }\n\n    assert(status);\n\n    free(A);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor j in BARRIER HAND\n\tdo \t\n\t\tfor k in 1 2 4 8 16\n\t\tdo\n\t\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=TREE SYNC=$j make all\n\t\t\twait\n            ./bin/host_code -w 2 -e 10 -i 2097152 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n            #./bin/host_code -w 2 -e 10 -i 2048 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\n\t\tdone\n\tdone\ndone\n\nfor i in 1 \ndo\n    for k in 1 2 4 8 16\n\tdo\n\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=SINGLE make all\n\t\twait\n        ./bin/host_code -w 2 -e 10 -i 2097152 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n        #./bin/host_code -w 2 -e 10 -i 2048 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n\t\twait\n\t\tmake clean\n\t\twait\n\tdone\ndone\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n    T t_count;\n} dpu_results_t;\n\n#ifndef PERF\n#define PERF 0 // Use perfcounters?\n#endif\n#ifndef PERF_SYNC\n#define PERF_SYNC 0 // Use perfcounters to time sync primitives?\n#endif\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=6553600 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/RED/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200 -t 4\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size =  p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        memcpy(thrust::raw_pointer_cast(&h_output[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        thrust::exclusive_scan(thrust::omp::par, h_output.begin(),h_output.end(),h_output.begin());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            //printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=640 * 3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1258291200;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        thrust::exclusive_scan(d_input.begin(),d_input.end(),d_input.begin());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n        cudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SCAN-RSS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SCAN-RSS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Reduce-scan-scan)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input){\n    T output = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output += input[j];\n    }\n    return output;\n}\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Reduction\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Reduction in each tasklet\n        l_count += reduction(cache_A);\n\n    }\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n    // Single-runtime reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0){\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n        // Total count in this DPU\n        result->t_count = message[0];\n    }\n\n    return 0;\n}\n\n// Scan\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\t\t\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define REGS 128\n\nstruct dpu_arguments_t {\n    int size;\n    int kernel;\n    long t_count;\n};\n\nstruct dpu_results_t {\n    long t_count;\n};\n\nvoid read_input(long* A, int nr_elements, int nr_elements_round) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i % 100;\n    }\n    for (int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\nvoid scan_host(long* C, long* A, int nr_elements) {\n    C[0] = A[0];\n    for (int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    int* A;\n    long* C;\n    long* C2;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n\n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    long accum = 0;\n\n    int input_size = DATA_PREP_PARAMS;\n    int input_size_dpu_ = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_round = (input_size_dpu_ % (NUM_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NUM_TASKLETS * REGS)) : input_size_dpu_;\n\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    long *bufferA = A;\n    long *bufferC = C2;\n\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    scan_host(C, A, input_size);\n\n    int input_size_dpu = input_size_dpu_round;\n    int kernel = 0;\n    struct dpu_arguments_t input_arguments;\n    input_arguments.size = input_size_dpu * sizeof(long);\n    input_arguments.kernel = kernel;\n    input_arguments.t_count = 0;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results = malloc(nr_of_dpus * sizeof(struct dpu_results_t));\n    long* results_scan = malloc(nr_of_dpus * sizeof(long));\n\n    accum = 0;\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(each_tasklet == 0) {\n                results[i].t_count = results_retrieve[i * NUM_TASKLETS + each_tasklet].t_count;\n            }\n        }\n\n        long temp = results[i].t_count;\n        results_scan[i] = accum;\n        accum += temp;\n    }\n\n    kernel = 1;\n    struct dpu_arguments_t* input_arguments_2 = malloc(NUM_DPUS * sizeof(struct dpu_arguments_t));\n    for(int i=0; i<nr_of_dpus; i++) {\n        input_arguments_2[i].size=input_size_dpu * sizeof(long);\n        input_arguments_2[i].kernel=kernel;\n        input_arguments_2[i].t_count=results_scan[i];\n    }\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments_2[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferC[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(long), input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    int status = 1;\n    for (int i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(C);\n    free(C2);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 VERSION=SINGLE make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-RSS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT64)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SCAN-SSA/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SCAN-SSA_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Scan-scan-add)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Scan-(handshake)scan\nint main_kernel1() {\n#if 1 // Comment out for appendix experiment\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\n#endif\n    return 0;\n}\n\n// Add\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    T t_count = DPU_INPUT_ARGUMENTS.t_count;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_A, BLOCK_SIZE);\n\n        // Add in each tasklet\n        add_(cache_A, t_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define REGS 128\n\nstruct dpu_arguments_t {\n    int size;\n    int kernel;\n    long t_count;\n};\n\nstruct dpu_results_t {\n    long t_count;\n};\n\nvoid read_input(long* A, int nr_elements, int nr_elements_round) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i % 100;\n    }\n    for (int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\nvoid scan_host(long* C, long* A, int nr_elements) {\n    C[0] = A[0];\n    for (int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    int* A;\n    long* C;\n    long* C2;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n\n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    long accum = 0;\n\n    int input_size = DATA_PREP_PARAMS;\n    int input_size_dpu_ = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_round = (input_size_dpu_ % (NUM_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NUM_TASKLETS * REGS)) : input_size_dpu_;\n\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    long *bufferA = A;\n    long *bufferC = C2;\n\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    scan_host(C, A, input_size);\n\n    int input_size_dpu = input_size_dpu_round;\n    int kernel = 0;\n    struct dpu_arguments_t input_arguments;\n    input_arguments.size = input_size_dpu * sizeof(long);\n    input_arguments.kernel = kernel;\n    input_arguments.t_count = 0;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results = malloc(nr_of_dpus * sizeof(struct dpu_results_t));\n    long* results_scan = malloc(nr_of_dpus * sizeof(long));\n\n    accum = 0;\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(each_tasklet == NUM_TASKLETS - 1) {\n                results[i].t_count = results_retrieve[i * NUM_TASKLETS + each_tasklet].t_count;\n            }\n        }\n\n        long temp = results[i].t_count;\n        results_scan[i] = accum;\n        accum += temp;\n    }\n\n    kernel = 1;\n    struct dpu_arguments_t* input_arguments_2 = malloc(NUM_DPUS * sizeof(struct dpu_arguments_t));\n    for(int i=0; i<nr_of_dpus; i++) {\n        input_arguments_2[i].size=input_size_dpu * sizeof(long);\n        input_arguments_2[i].kernel=kernel;\n        input_arguments_2[i].t_count=results_scan[i];\n    }\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments_2[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferC[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(long), input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    int status = 1;\n    for (int i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(C);\n    free(C2);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SCAN-SSA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o sel -fopenmp app_baseline.c \n\nclean:\n\trm sel\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/cpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./sel -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic uint64_t *A;\nstatic uint64_t *B;\nstatic uint64_t *C;\nstatic uint64_t *C2;\nstatic int pos;\n\nbool pred(const uint64_t x){\n  return (x % 2) == 0;\n}\n\n\nvoid  *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    B = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    C = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        A[i] = i+1;\n        B[i] = 0;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic int select_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(!pred(A[my])) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n    return pos;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    char* dpu_type;\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -d <D>    DPU type (default=fsim)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=2)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=5)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = select_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n    \n    free(A);\n    free(B);\n    free(C);\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc select.cu -I/usr/local/cuda/include -lm -o select -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm select\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/gpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./select 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays (Note: Sample predicate is only for INT)\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__global__ void select_remove_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(!pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n\n__global__ void select_copy_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/baselines/gpu/select.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n\n// Sample predicate for partition (only for INT)\nstruct is_even{\n  __host__ __device__\n  bool operator()(const T &x){\n    return (x % 2) == 0;\n  }\n};\n\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_copy_if(T* output, T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(pred(input[i])){\n\t  output[pos] = input[i];\n      pos++;\n    }\n  }\n}\nvoid cpu_remove_if(T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(!pred(input[i])){\n\t  input[pos] = input[i];\n      pos++;\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Select on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n  float time3 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n  T *h_D = (T*)malloc(size);\n\n  // Allocate the device input vector A and output vector B\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n  T *d_B = NULL;\n  cudaMalloc((void **)&d_B, size);\n\n#define WARMUP 2\n#define REP 10\n  unsigned int flagM1 = 0;\n  unsigned int flagM2 = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++)\n        h_A[i] = i % 2 != 0 ? i:i+1;\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x] % 2 != 0){\n            h_A[x] = x * 2;\n            m--;\n        }\n    }\n\n#if PRINT\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    const int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Copy_if)\n    select_copy_if<<<num_wg, ldim>>>(d_B, d_A, numElements, d_flags, is_even());\n\n    cudaMemcpy(&flagM1, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // Stop timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM1) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Copy_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Atomic flags\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Remove_if)\n    select_remove_if<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags, is_even()); \n\n    cudaMemcpy(&flagM2, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time3 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time3 / REP;\n      double bw = (double)((numElements + flagM2) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Remove_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);\n  cudaMemcpy(h_C, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_copy_if(h_D, h_A, numElements, is_even());\n  cpu_remove_if(h_A, numElements, is_even());\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_D+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM1 - 1; ++i){\n      if (h_B[i] != h_D[i]){\n          fprintf(stderr, \"Copy_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  for (int i = 0; i < flagM2 - 1; ++i){\n      if (h_C[i] != h_A[i]){\n          fprintf(stderr, \"Remove_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaFree(d_B);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n  free(h_D);\n\n  return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/SEL/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(SEL_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/dpu/task.c",
    "content": "/*\n* Select with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nuint32_t message_partial_count;\n\n// SEL in each tasklet\nunsigned int __attribute__ ((noinline)) select(T *output, T *input){\n    unsigned int pos = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        if(!pred(input[j])) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nunsigned int __attribute__ ((noinline)) handshake_sync(unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = 0;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // SELECT in each tasklet\n        uint32_t l_count = select(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint32_t p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + p_count) * sizeof(T)), l_count * sizeof(T));\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define REGS 128\n\nstruct dpu_arguments_t{\n    int size;\n    int kernel;\n};\n\nstruct dpu_results_t {\n    int t_count;\n};\n\nvoid read_input(long* A, int nr_elements, int nr_elements_round) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i + 1;\n    }\n    for (int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\nint pred (long x) {\n  return (x % 2) == 0;\n}\n\nint select_host(long* C, long* A, int nr_elements) {\n    int pos = 0;\n    for (int i = 0; i < nr_elements; i++) {\n        if(!pred(A[i])) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    long* A;\n    long* C;\n    long* C2;\n    \n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus;\n\n    dpu_alloc(NUM_DPUS, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n    nr_of_dpus = NUM_DPUS;\n\n    int accum = 0;\n    int total_count = 0;\n\n    int input_size = DATA_PREP_PARAMS;\n    int input_size_dpu_ = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_round = (input_size_dpu_ % (NUM_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NUM_TASKLETS * REGS)) : input_size_dpu_;\n\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    long *bufferA = A;\n    long *bufferC = C2;\n\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    total_count = select_host(C, A, input_size);\n\n    int input_size_dpu = input_size_dpu_round;\n    int kernel = 0;\n    struct dpu_arguments_t input_arguments;\n    input_arguments.size = input_size_dpu * sizeof(long);\n    input_arguments.kernel = kernel;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results = malloc(nr_of_dpus * sizeof(struct dpu_results_t));\n    int* results_scan = malloc(nr_of_dpus * sizeof(int));\n\n    accum = 0;\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(each_tasklet == NUM_TASKLETS - 1){\n                results[i].t_count = results_retrieve[i * NUM_TASKLETS + each_tasklet].t_count;\n            }\n        }\n\n        int temp = results[i].t_count;\n        results_scan[i] = accum;\n        accum += temp;\n    }\n\n    DPU_FOREACH (dpu_set, dpu, i) {\n        dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(long), &bufferC[results_scan[i]], results[i].t_count * sizeof(long));\n    }\n\n    free(results_scan);\n\n    int status = 1;\n    if(accum != total_count) {\n        status = 0;\n    }\n    for (int i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(C);\n    free(C2);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Sample predicate\nbool pred(const T x){\n  return (x % 2) == 0;\n}\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/SEL/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=g++\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -lm -pthread\n\nDEP=kernel.cpp kernel.h main.cpp support/common.h support/setup.h support/timer.h \nSRC=main.cpp kernel.cpp\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 \n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   data[b];\n            T   backup[b];\n            int done;\n            int m = A * B - 1;\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < m) {\n                int next_in_cycle = (gid * A) - m * (gid / B);\n                if(next_in_cycle == gid) {\n                    // Dynamic fetch\n                    gid = (head)->fetch_add(1);\n                    continue;\n                }\n                for(int i = 0; i < b; i++) {\n                    data[i] = input[gid * b + i];\n                }\n                //make sure the read is not cached\n                done = (finished + gid)->load();\n                for(; done == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n                    for(int i = 0; i < b; i++) {\n                        backup[i] = input[next_in_cycle * b + i];\n                    }\n                    done = (finished + next_in_cycle)->exchange(1);\n                    if(!done) {\n                        for(int i = 0; i < b; i++) {\n                            input[next_in_cycle * b + i] = data[i];\n                        }\n                    }\n                    for(int i = 0; i < b; i++) {\n                        data[i] = backup[i];\n                    }\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n            }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_010(T *input, std::atomic_int* head, int a, int b, int tiles, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   tile[a * b];\n            int m = a * b - 1;\n\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < tiles) {\n                T* input_array = input + a * b * gid;\n                for (int j = 0; j < a * b; j++) {\n                    int next = (j * a)-m*(j/b);\n                    tile[next] = input_array[j];\n                }\n                for (int j = 0; j < a * b; j++) {\n                    input_array[j] = tile[j];\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n\t\t    }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads);\nvoid run_cpu_threads_010(T *input, std::atomic_int *head, int m, int n, int tiles, int threads);\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int M_;\n    int m;\n    int N_;\n    int n;\n\n    Params(int argc, char **argv) {\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"ht:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n\t\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    Timer        timer;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 1\");\n        // Launch CPU threads\n        std::thread main_thread_1(run_cpu_threads_100, h_in_out, h_finished, h_head, M_ * m, N_, n, p.n_threads); //M_ * m * N_);\n        main_thread_1.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 1\");\n\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 2\");\n        // Launch CPU threads\n        std::thread main_thread_2(run_cpu_threads_010, h_in_out, h_head, m, n, M_ * N_, p.n_threads);\n        main_thread_2.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 2\");\n\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 3\");\n        // Launch CPU threads\n        for(int i = 0; i < N_; i++){\n            std::thread main_thread_3(run_cpu_threads_100, h_in_out + i * M_ * n * m, h_finished + i * M_ * n, h_head + i, M_, n, m, p.n_threads); //M_ * n);\n            main_thread_3.join();\n\t\t}\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 3\");\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Verify answer\n    //verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    free(h_in_backup);\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T double\n#else\n#define T float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/support/setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, struct timeval> startTime;\r\n    map<string, struct timeval> stopTime;\r\n    map<string, double>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            time[name] = 0.0;\r\n        }\r\n        gettimeofday(&startTime[name], NULL);\r\n    }\r\n\r\n    void stop(string name) {\r\n        gettimeofday(&stopTime[name], NULL);\r\n        time[name] += (stopTime[name].tv_sec - startTime[name].tv_sec) * 1000000.0 +\r\n                      (stopTime[name].tv_usec - startTime[name].tv_usec);\r\n    }\r\n\r\n\t\tvoid print(string name, int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / (1000 * REP)); }\r\n};\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/cpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L$/usr/local/cuda/lib64/ -lm\n\nINC=-I/usr/local/cuda/include/\n\nDEP=kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cu\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 -i 64\n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/common.h\"\n\nextern __shared__ int l_mem[];\n\n// GPU kernel ------------------------------------------------------------------------------------------\n__global__ void PTTWAC_soa_asta(int A, int B, int b, T *input, int *finished, int *head) {\n\n    int* done = l_mem;\n    int* gid_ = &done[1];\n\n    const int tid = threadIdx.x;\n    int       m   = A * B - 1;\n\n    if(tid == 0) // Dynamic fetch\n        gid_[0] = atomicAdd(&head[0], 1);\n    __syncthreads();\n\n    while(gid_[0] < m) {\n        int next_in_cycle = (gid_[0] * A) - m * (gid_[0] / B);\n        if(next_in_cycle == gid_[0]) {\n            if(tid == 0) // Dynamic fetch\n                gid_[0] = atomicAdd(&head[0], 1);\n            __syncthreads();\n            continue;\n        }\n        T   data1, data2, data3, data4;\n        int i = tid;\n        if(i < b)\n            data1 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data2 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data3 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data4 = input[gid_[0] * b + i];\n\n        if(tid == 0) {\n            //make sure the read is not cached\n            done[0] = atomicAdd(&finished[gid_[0]], 0);\n        }\n        __syncthreads();\n\n        for(; done[0] == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n            T backup1, backup2, backup3, backup4;\n            i = tid;\n            if(i < b)\n                backup1 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup2 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup3 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup4 = input[next_in_cycle * b + i];\n\n            if(tid == 0) {\n                done[0] = atomicExch(&finished[next_in_cycle], (int)1);\n            }\n            __syncthreads();\n\n            if(!done[0]) {\n                i = tid;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data1;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data2;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data3;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data4;\n            }\n            i = tid;\n            if(i < b)\n                data1 = backup1;\n            i += blockDim.x;\n            if(i < b)\n                data2 = backup2;\n            i += blockDim.x;\n            if(i < b)\n                data3 = backup3;\n            i += blockDim.x;\n            if(i < b)\n                data4 = backup4;\n        }\n\n        if(tid == 0) // Dynamic fetch\n            gid_[0] = atomicAdd(&head[0], 1);\n        __syncthreads();\n    }\n}\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    PTTWAC_soa_asta<<<dimGrid, dimBlock, l_mem_size>>>(A, B, b, input, \n        finished, head);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n\n__global__ void BS_marshal(T *input, int tile_size, int width) {\n\n  T* tile = (T*)l_mem;\n\n  int tidx = threadIdx.x;\n  int m = width*tile_size-1;\n  int bid = blockIdx.x;\n\n  input += tile_size*width*bid;\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    int next = (i * tile_size)-m*(i/width);\n    tile[next] = input[i];\n  }\n  __syncthreads();\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    input[i] = tile[i];\n  }\n}\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    BS_marshal<<<dimGrid, dimBlock, l_mem_size>>>(input, m, n);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"cuda_runtime.h\"\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size);\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size);\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int device;\n    int n_gpu_threads;\n    int n_gpu_blocks;\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int   M_;\n    int   m;\n    int   N_;\n    int   n;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 64;\n        n_gpu_blocks = 16;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        assert((n_gpu_threads > 0 && n_gpu_blocks > 0)\n            && \"TRNS only runs on CPU-only or GPU-only: './trns -g 0' or './trns -t 0'\");\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=64)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n\t\t        \"\\nBenchmark-specific options:\"\n\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T * d_in_out;\n    int * d_finished;\n    int * d_head;\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMalloc((void**)&d_in_out, in_size * sizeof(T));\n        cudaStatus = cudaMalloc((void**)&d_finished, (p.n_gpu_blocks != 0) ? sizeof(int) * finished_size : 0);\n        cudaStatus = cudaMalloc((void**)&d_head, (p.n_gpu_blocks != 0) ? N_ * sizeof(int) : 0);\n        CUDA_ERR();\n    }\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n        CUDA_ERR();\n    }\n    cudaDeviceSynchronize();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\t\tcudaDeviceSynchronize();\n\n        // Launch GPU threads\n        if(p.n_gpu_blocks > 0) {\n            // Kernel launch\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n\n            cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 1\");\n            // Step 1\n            cudaStatus = call_PTTWAC_soa_asta(M_ * m * N_, p.n_gpu_threads, M_ * m, N_, n,\n                d_in_out, (int*)d_finished, (int*)d_head, sizeof(int) + sizeof(int));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 1\");\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 2\");\n            // Step 2\n            cudaStatus = call_BS_marshal(M_ * N_, p.n_gpu_threads, m, n, d_in_out, m * n * sizeof(T));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 2\");\n\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n            // start timer\n            if(rep >= p.n_warmup)\n                timer.start(\"Step 3\");\n            // Step 3\n            for(int i = 0; i < N_; i++){\n                cudaStatus = call_PTTWAC_soa_asta(M_ * n, p.n_gpu_threads, M_, n, m,\n                    d_in_out + i * M_ * n * m, (int*)d_finished + i * M_ * n, (int*)d_head + i, sizeof(int) + sizeof(int));\n                CUDA_ERR();\n            }\n            // end timer\n            if(rep >= p.n_warmup)\n                timer.stop(\"Step 3\");\n\n        }\n\n        cudaDeviceSynchronize();\n\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(h_in_out, d_in_out, in_size * sizeof(T), cudaMemcpyDeviceToHost);\n        CUDA_ERR();\n        cudaDeviceSynchronize();\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n\n    // Verify answer\n    verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaFree(d_in_out);\n        cudaStatus = cudaFree(d_finished);\n        cudaStatus = cudaFree(d_head);\n        CUDA_ERR();\n    }\n    free(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Step 1\");\n    timer.release(\"Step 2\");\n    timer.release(\"Step 3\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T long int // double\n#else\n#define T int // float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/dpu/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/TRNS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(TRNS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/dpu/task.c",
    "content": "/*\n* 3-step matrix transposition with multiple tasklets\n* Acks: Stefano Ballarin (P&S PIM Fall 2020)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <mutex.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\nuint32_t curr_tile = 0; // protected by MUTEX\nuint32_t get_tile();\nvoid read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\nvoid write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\n_Bool get_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n_Bool get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Mutexes\nMUTEX_INIT(tile_mutex);\nMUTEX_INIT(done_mutex);\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Step 2: 0010\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER; // A in MRAM\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n\n    T* data = (T*) mem_alloc(m * n * sizeof(T));\n    T* backup = (T*) mem_alloc(m * n * sizeof(T));\n\n    for(unsigned int tile = tasklet_id; tile < M_; tile += NR_TASKLETS){\n        read_tile_step2(A, tile * m * n, data, m, n);\n        for (unsigned int i = 0; i < m * n; i++){\n            backup[(i * m) - (m * n - 1) * (i / n)] = data[i];\n        }\n        write_tile_step2(A, tile * m * n, backup, m, n);\n    }\n\n    return 0;\n}\n\n// Step 3: 0100\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t done_array = (uint32_t)(DPU_MRAM_HEAP_POINTER + M_ * m * n * sizeof(T));\n\n    const uint32_t tile_max = M_ * n - 1; // Tile id upper bound\n\n    T* data = (T*)mem_alloc(sizeof(T) * m);\n    T* backup = (T*)mem_alloc(sizeof(T) * m);\n    T* read_done = (T*)mem_alloc(sizeof(T));\n\n    uint32_t tile;\n    _Bool done;\n\n    tile = get_tile();\n\n    while (tile < tile_max){\n        uint32_t next_in_cycle = ((tile * M_) - tile_max * (tile / n));\n        if (next_in_cycle == tile){\n            tile = get_tile();\n            continue;\n        }\n        read_tile_step3(A, tile * m, data, m);\n\n        done = get_done(done_array, tile, read_done);\n        for(; done == 0; next_in_cycle = ((next_in_cycle * M_) - tile_max * (next_in_cycle / n))){\n            read_tile_step3(A, next_in_cycle * m, backup, m);\n\n            done = get_and_set_done(done_array, next_in_cycle, read_done);\n\n            if(!done) {\n                write_tile_step3(A, next_in_cycle * m, data, m);\n            }\n            for(uint32_t i = 0; i < m; i++){\n                data[i] = backup[i];\n            }\n        }\n        tile = get_tile();\n    }\n\t\t\n    return 0;\n}\n\n// Auxiliary functions\nuint32_t __attribute__ ((noinline)) get_tile(){\n    mutex_lock(tile_mutex);\n    uint32_t value = curr_tile;\n    curr_tile++;\n    mutex_unlock(tile_mutex);\n    return value;\n}\n\nvoid __attribute__ ((noinline)) read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_read((__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), variable + (m * n - rest) * sizeof(T), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_write(variable + (m * n - rest) * sizeof(T), (__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_read((__mram_ptr void*)(A + offset * sizeof(T)), variable, sizeof(T) * m);\n}\n\nvoid __attribute__ ((noinline)) write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_write(variable, (__mram_ptr void*)(A + offset * sizeof(T)), sizeof(T) * m);\n}\n\n_Bool __attribute__ ((noinline)) get_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n\n_Bool __attribute__ ((noinline))get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    *read_done |= (0x01 << (address % sizeof(T)));\n    mram_write(read_done, (__mram_ptr void*)(done_array_step3 + address), sizeof(T));\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\nstruct dpu_arguments_t {\n    int m;\n    int n;\n    int M_;\n    int kernel;\n};\n\nvoid read_input(long* A, int nr_elements) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i % 100;\n    }\n}\n\nvoid trns_host(long* input, int A, int B, int b){\n   long* output = malloc(sizeof(long) * A * B * b);\n   int next;\n   for (int j = 0; j < b; j++){\n      for (int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\nint main() {\n    long* A_host;\n    long* A_backup;\n    long* A_result;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n\n    int nr_of_dpus = NUM_DPUS;\n\n    int N_ = 64;\n    int n = 8;\n    int M_ = DATA_PREP_PARAMS;\n    int m = 4;\n\n    A_host = malloc(M_ * m * N_ * n * sizeof(long));\n    A_backup = malloc(M_ * m * N_ * n * sizeof(long));\n    A_result = malloc(M_ * m * N_ * n * sizeof(long));\n    char* done_host = malloc(M_ * n * sizeof(char));\n\n    for (int i = 0; i < M_ * n; i++) {\n        done_host[i] = 0;\n    }\n\n    read_input(A_host, M_ * m * N_ * n);\n\n    for (int i = 0; i < M_ * m * N_ * n; i++) {\n        A_backup[i] = A_host[i];\n    }\n\n    trns_host(A_host, M_ * m, N_ * n, 1);\n\n    int curr_dpu = 0;\n    int active_dpus;\n    int active_dpus_before = 0;\n    int first_round = 1;\n\n    while(curr_dpu < N_){\n        if((N_ - curr_dpu) > NUM_DPUS){\n            active_dpus = NUM_DPUS;\n        } else {\n            active_dpus = (N_ - curr_dpu);\n        }\n\n        if((active_dpus_before != active_dpus) && (!(first_round))){\n            dpu_free(dpu_set);\n            dpu_alloc(active_dpus, NULL, &dpu_set);\n            dpu_load(dpu_set, DPU_BINARY, NULL);\n\n            nr_of_dpus = active_dpus;\n        } else if (first_round){\n            dpu_alloc(active_dpus, NULL, &dpu_set);\n            dpu_load(dpu_set, DPU_BINARY, NULL);\n\n            nr_of_dpus = active_dpus;\n        }\n\n        for(int j = 0; j < M_ * m; j++){\n            DPU_FOREACH(dpu_set, dpu, i) {\n                dpu_prepare_xfer(dpu, &A_backup[j * N_ * n + n * (i + curr_dpu)]);\n            }\n            dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, sizeof(long) * j * n, sizeof(long) * n, DPU_XFER_DEFAULT);\n        }\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, done_host);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, M_ * m * n * sizeof(long), (M_ * n) / 8 == 0 ? 8 : M_ * n, DPU_XFER_DEFAULT);\n\n        int kernel = 0;\n        struct dpu_arguments_t input_arguments;\n        input_arguments.m = m;\n        input_arguments.n = n;\n        input_arguments.M_ = M_;\n        input_arguments.kernel = kernel;\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, &input_arguments);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n        dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n        kernel = 1;\n        struct dpu_arguments_t input_arguments2;\n        input_arguments2.m = m;\n        input_arguments2.n = n;\n        input_arguments2.M_ = M_;\n        input_arguments2.kernel = kernel;\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, &input_arguments2);\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n        dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            dpu_prepare_xfer(dpu, &A_result[curr_dpu * m * n * M_]);\n            curr_dpu++;\n        }\n        dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, sizeof(long) * m * n * M_, DPU_XFER_DEFAULT);\n\n        if(first_round){\n            first_round = 0;\n        }\n    }\n\n    dpu_free(dpu_set);\n\n    int status = 1;\n    for (int i = 0; i < M_ * m * N_ * n; i++) {\n        if(A_host[i] != A_result[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A_host);\n    free(A_backup);\n    free(A_result);\n    free(done_host);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int64_t\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t m;\n    uint32_t n;\n    uint32_t M_;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   M_;\n    unsigned int   m;\n    unsigned int   N_;\n    unsigned int   n;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -m <I>    m (default=16 elements)\"\n        \"\\n    -n <I>    n (default=8 elements)\"\n        \"\\n    -o <I>    M_ (default=12288 elements)\"\n        \"\\n    -p <I>    N_ (default=1 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.M_            = 12288;\n    p.m             = 16;\n    p.N_            = 1;\n    p.n             = 8;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:x:m:n:o:p:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'm': p.m             = atoi(optarg); break;\n        case 'n': p.n             = atoi(optarg); break;\n        case 'o': p.M_            = atoi(optarg); break;\n        case 'p': p.N_            = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TRNS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -lm\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -n 131072\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/TS/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(TS_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/dpu/task.c",
    "content": "/*\n * STREAMP implementation of Matrix Profile with multiple tasklets\n *\n */\n\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include \"common.h\"\n\n#define DOTPIP BLOCK_SIZE / sizeof(DTYPE)\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_result_t DPU_RESULTS[NR_TASKLETS];\n\n// Dot product\nvoid __attribute__ ((noinline)) dot_product(DTYPE *vectorA, DTYPE *vectorA_aux, DTYPE *vectorB, DTYPE * result) {\n\n\tfor(uint32_t i = 0; i <  BLOCK_SIZE / sizeof(DTYPE); i++)\n\t{\n\t\tfor(uint32_t j = 0; j < DOTPIP; j++)\n\t\t{\n\t\t\tif((j + i) > BLOCK_SIZE / sizeof(DTYPE) - 1)\n\t\t\t{\n\t\t\t\tresult[j] += vectorA_aux[(j + i) - BLOCK_SIZE / sizeof(DTYPE)]  * vectorB[i];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tresult[j] += vectorA[j + i] * vectorB[i];\n\t\t\t}\n\t\t}\n\t}\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n\t// Kernel\n\treturn kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif(tasklet_id == 0){\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\t// Input arguments\n\tuint32_t query_length  = DPU_INPUT_ARGUMENTS.query_length;\n\tDTYPE query_mean       = DPU_INPUT_ARGUMENTS.query_mean;\n\tDTYPE query_std        = DPU_INPUT_ARGUMENTS.query_std;\n\tuint32_t slice_per_dpu = DPU_INPUT_ARGUMENTS.slice_per_dpu;\n\n\t// Boundaries for current tasklet\n\tuint32_t myStartElem = tasklet_id  * (slice_per_dpu / (NR_TASKLETS));\n\tuint32_t myEndElem   = myStartElem + (slice_per_dpu / (NR_TASKLETS)) - 1;\n\n\t// Check time series limit\n\tif(myEndElem > slice_per_dpu - query_length) myEndElem = slice_per_dpu - query_length;\n\n\t// Starting address of the current processing block in MRAM\n\tuint32_t mem_offset = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t// Starting address of the query subsequence\n\tuint32_t current_mram_block_addr_query = (uint32_t)(mem_offset);\n\tmem_offset += query_length * sizeof(DTYPE);\n\n\t// Starting address of the time series slice\n\tmem_offset += myStartElem * sizeof(DTYPE);\n\tuint32_t starting_offset_ts = mem_offset;\n\tuint32_t current_mram_block_addr_TS = (uint32_t) mem_offset;\n\n\t// Starting address of the time series means\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSMean = (uint32_t)(mem_offset);\n\n\t// Starting address of the time series standard deviations\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSSigma = (uint32_t)(mem_offset);\n\n\t// Initialize local caches to store the MRAM blocks\n\tDTYPE *cache_TS       = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TS_aux   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_query    = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSMean   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSSigma  = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_dotprods = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n\t// Create result structure pointer\n\tdpu_result_t *result = &DPU_RESULTS[tasklet_id];\n\n\t// Auxiliary variables\n\tDTYPE distance;\n\tDTYPE min_distance = DTYPE_MAX;\n\tuint32_t min_index = 0;\n\n\n\tfor(uint32_t i = myStartElem; i < myEndElem; i+= (BLOCK_SIZE / sizeof(DTYPE)))\n\t{\n\t\tfor(uint32_t d = 0; d < DOTPIP; d++)\n\t\t\tcache_dotprods[d] = 0;\n\n\t\tcurrent_mram_block_addr_TS    = (uint32_t) starting_offset_ts + (i - myStartElem) * sizeof(DTYPE);\n\t\tcurrent_mram_block_addr_query = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t\tfor(uint32_t j = 0; j < (query_length) / (BLOCK_SIZE / sizeof(DTYPE)); j++)\n\t\t{\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS, cache_TS, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS + BLOCK_SIZE, cache_TS_aux, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_query, cache_query, BLOCK_SIZE);\n\n\t\t\tcurrent_mram_block_addr_TS    += BLOCK_SIZE;\n\t\t\tcurrent_mram_block_addr_query += BLOCK_SIZE;\n\t\t\tdot_product(cache_TS, cache_TS_aux, cache_query, cache_dotprods);\n\t\t}\n\n\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSMean, cache_TSMean, BLOCK_SIZE);\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSSigma, cache_TSSigma, BLOCK_SIZE);\n\t\tcurrent_mram_block_addr_TSMean  += BLOCK_SIZE;\n\t\tcurrent_mram_block_addr_TSSigma += BLOCK_SIZE;\n\n\t\tfor (uint32_t k = 0; k < (BLOCK_SIZE / sizeof(DTYPE)); k++)\n\t\t{\n\t\t\tdistance = 2 * ((DTYPE) query_length - (cache_dotprods[k] - (DTYPE) query_length * cache_TSMean[k]\n\t\t\t\t\t\t* query_mean) / (cache_TSSigma[k] * query_std));\n\n\t\t\tif(distance < min_distance)\n\t\t\t{\n\t\t\t\tmin_distance =  distance;\n\t\t\t\tmin_index    =  i + k;\n\t\t\t}\n\t\t}\n\t}\n\n\t// Save the result\n\tresult->minValue = min_distance;\n\tresult->minIndex = min_index;\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n#include <time.h>\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 64\n\n#define MAX_DATA_VAL 127\n\nstruct dpu_arguments_t {\n\tint ts_length;\n    int query_length;\n    int query_mean;\n    int query_std;\n    int slice_per_dpu;\n    int exclusion_zone;\n    int kernel;\n};\n\nstruct dpu_result_t {\n    int minValue;\n    int minIndex;\n    int maxValue;\n    int maxIndex;\n};\n\nint *create_test_file(int* tSeries, int* query, int ts_elements, int query_elements) {\n\tfor (int i = 0; i < ts_elements; i++)\n\t{\n\t\ttSeries[i] = i % MAX_DATA_VAL;\n\t}\n\n\tfor (int i = 0; i < query_elements; i++)\n\t{\n\t\tquery[i] = i % MAX_DATA_VAL;\n\t}\n\n\treturn tSeries;\n}\n\nvoid streamp(int* tSeries, int* AMean, int* ASigma, int *minHost, int *minHostIdx, int ProfileLength,\n\t\tint* query, int queryLength, int queryMean, int queryStdDeviation)\n{\n\tint distance;\n\tint dotprod;\n\t*minHost    = 2147483647;\n\t*minHostIdx = 0;\n\n\tfor (int subseq = 0; subseq < ProfileLength; subseq++)\n\t{\n\t\tdotprod = 0;\n\t\tfor(int j = 0; j < queryLength; j++)\n\t\t{\n\t\t\tdotprod += tSeries[j + subseq] * query[j];\n\t\t}\n\n\t\tdistance = 2 * (queryLength - (dotprod - queryLength * AMean[subseq] * queryMean) / (ASigma[subseq] * queryStdDeviation));\n\n\t\tif(distance < *minHost)\n\t\t{\n\t\t\t*minHost = distance;\n\t\t\t*minHostIdx = subseq;\n\t\t}\n\t}\n}\n\nvoid compute_ts_statistics(int* tSeries, int* AMean, int* ASigma, int timeSeriesLength, int ProfileLength, int queryLength)\n{\n\tint* ACumSum = malloc(sizeof(int) * timeSeriesLength);\n\tACumSum[0] = tSeries[0];\n\tfor (int i = 1; i < timeSeriesLength; i++) {\n\t\tACumSum[i] = tSeries[i] + ACumSum[i - 1];\n\t}\n\n\tint* ASqCumSum = malloc(sizeof(int) * timeSeriesLength);\n\tASqCumSum[0] = tSeries[0] * tSeries[0];\n\tfor (int i = 1; i < timeSeriesLength; i++) {\n\t\tASqCumSum[i] = tSeries[i] * tSeries[i] + ASqCumSum[i - 1];\n    }\n\n\tint* ASum = malloc(sizeof(int) * ProfileLength);\n\tASum[0] = ACumSum[queryLength - 1];\n\tfor (int i = 0; i < timeSeriesLength - queryLength; i++) {\n\t\tASum[i + 1] = ACumSum[queryLength + i] - ACumSum[i];\n    }\n\n\tint* ASumSq = malloc(sizeof(int) * ProfileLength);\n\tASumSq[0] = ASqCumSum[queryLength - 1];\n\tfor (int i = 0; i < timeSeriesLength - queryLength; i++) {\n\t\tASumSq[i + 1] = ASqCumSum[queryLength + i] - ASqCumSum[i];\n    }\n\n\tint * AMean_tmp = malloc(sizeof(int) * ProfileLength);\n\tfor (int i = 0; i < ProfileLength; i++) {\n\t\tAMean_tmp[i] = ASum[i] / queryLength;\n    }\n\n\tint* ASigmaSq = malloc(sizeof(int) * ProfileLength);\n\tfor (int i = 0; i < ProfileLength; i++) {\n\t\tASigmaSq[i] = ASumSq[i] / queryLength - AMean[i] * AMean[i];\n    }\n\n\tfor (int i = 0; i < ProfileLength; i++)\n\t{\n\t\tASigma[i] = sqrt(ASigmaSq[i]);\n\t\tAMean[i]  = AMean_tmp[i];\n\t}\n\n\tfree(ACumSum);\n\tfree(ASqCumSum);\n\tfree(ASum);\n\tfree(ASumSq);\n\tfree(ASigmaSq);\n\tfree(AMean_tmp);\n}\n\nint main() {\n    int* tSeries = malloc((1 << 15) * sizeof(int));\n    int* query = malloc((1 << 15) * sizeof(int));\n    int* AMean = malloc((1 << 15) * sizeof(int));\n    int* ASigma = malloc((1 << 15) * sizeof(int));\n    int* minHost = malloc(sizeof(int));\n    int* minHostIdx = malloc(sizeof(int));\n\n\tstruct dpu_set_t dpu_set;\n\tstruct dpu_set_t dpu;\n\tint nr_of_dpus = NUM_DPUS;\n\n\tdpu_alloc(NUM_DPUS, NULL, &dpu_set);\n\tdpu_load(dpu_set, DPU_BINARY, NULL);\n\n\tint ts_size = DATA_PREP_PARAMS;\n\tint query_length = 64;\n\n\tif(ts_size % (nr_of_dpus * NUM_TASKLETS*query_length)) {\n\t\tts_size = ts_size +  (nr_of_dpus * NUM_TASKLETS * query_length - ts_size % (nr_of_dpus * NUM_TASKLETS*query_length));\n    }\n\n\tcreate_test_file(tSeries, query, ts_size, query_length);\n\tcompute_ts_statistics(tSeries, AMean, ASigma, ts_size, ts_size - query_length, query_length);\n\n\tint query_mean;\n\tint queryMean = 0;\n\tfor(int i = 0; i < query_length; i++) {\n\t    queryMean += query[i];\n\t}\n\tqueryMean /= query_length;\n\tquery_mean = queryMean;\n\n\tint query_std;\n\tint queryStdDeviation;\n\tint queryVariance = 0;\n\tfor(int i = 0; i < query_length; i++)\n\t{\n\t\tqueryVariance += (query[i] - queryMean) * (query[i] - queryMean);\n\t}\n\tqueryVariance /= query_length;\n\tqueryStdDeviation = sqrt(queryVariance);\n\tquery_std = queryStdDeviation;\n\n\tint *bufferTS     = tSeries;\n\tint *bufferQ      = query;\n\tint *bufferAMean  = AMean;\n\tint *bufferASigma = ASigma;\n\n\tint slice_per_dpu = ts_size / nr_of_dpus;\n\n\tint kernel = 0;\n\tstruct dpu_arguments_t input_arguments;\n    input_arguments.ts_length = ts_size;\n    input_arguments.query_length = query_length;\n    input_arguments.query_mean = query_mean;\n    input_arguments.query_std = query_std;\n    input_arguments.slice_per_dpu = slice_per_dpu;\n    input_arguments.exclusion_zone = 0;\n    input_arguments.kernel = kernel;\n\n\tstruct dpu_result_t result;\n\tresult.minValue = 2147483647;\n\tresult.minIndex = 0;\n\tresult.maxValue = 0;\n\tresult.maxIndex = 0;\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        input_arguments.exclusion_zone = 0;\n\n        dpu_copy_to(dpu, \"DPU_INPUT_ARGUMENTS\", 0, &input_arguments, sizeof(struct dpu_arguments_t));\n    }\n\n    int mem_offset = 0;\n    DPU_FOREACH(dpu_set, dpu, i)\n    {\n        dpu_prepare_xfer(dpu, bufferQ);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, query_length * sizeof(int), DPU_XFER_DEFAULT);\n\n    mem_offset += query_length * sizeof(int);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferTS[slice_per_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset,(slice_per_dpu + query_length)*sizeof(int), DPU_XFER_DEFAULT);\n\n    mem_offset += ((slice_per_dpu + query_length) * sizeof(int));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferAMean[slice_per_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(int), DPU_XFER_DEFAULT);\n\n    mem_offset += ((slice_per_dpu + query_length) * sizeof(int));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferASigma[slice_per_dpu * i]);\n    }\n\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_result_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_result_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_result_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(results_retrieve[i * NUM_TASKLETS + each_tasklet].minValue < result.minValue && results_retrieve[i * NUM_TASKLETS + each_tasklet].minValue > 0)\n            {\n                result.minValue = results_retrieve[i * NUM_TASKLETS + each_tasklet].minValue;\n                result.minIndex = results_retrieve[i * NUM_TASKLETS + each_tasklet].minIndex + (i * slice_per_dpu);\n            }\n\n        }\n    }\n\n    streamp(tSeries, AMean, ASigma, minHost, minHostIdx, ts_size - query_length - 1, query, query_length, query_mean, query_std);\n\n\tint status = (*minHost == result.minValue);\n\tassert(status);\n\n\tdpu_free(dpu_set);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int32_t\n#define DTYPE_MAX INT32_MAX\n\ntypedef struct  {\n\tuint32_t ts_length;\n    uint32_t query_length;\n    DTYPE query_mean;\n    DTYPE query_std;\n    uint32_t slice_per_dpu;\n    int32_t exclusion_zone;\n    enum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n}dpu_arguments_t;\n\ntypedef struct  {\n    DTYPE minValue;\n    uint32_t minIndex;\n    DTYPE maxValue;\n    uint32_t maxIndex;\n}dpu_result_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  unsigned long  input_size_n;\n  unsigned long  input_size_m;\n  int  n_warmup;\n  int  n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -n <n>    n (TS length. Default=64K elements)\"\n    \"\\n    -m <m>    m (Query length. Default=256 elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size_n  = 1 << 16;\n    p.input_size_m  = 1 << 8;\n\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:n:m:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'n': p.input_size_n  = atol(optarg); break;\n        case 'm': p.input_size_m  = atol(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/TS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/CMakeLists.txt",
    "content": "#add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o uni -fopenmp app_baseline.c \n\nclean:\n\trm uni\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/cpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./uni -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/cpu/app_baseline.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\n#define T int64_t\n\nstatic int pos;\n\nstatic T *A;\nstatic T *B;\nstatic T *C;\nstatic T *C2;\n\n// Create a \"test file\"\nstatic T *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (T*) malloc(nr_elements * sizeof(T));\n    B = (T*) malloc(nr_elements * sizeof(T));\n    C = (T*) malloc(nr_elements * sizeof(T));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        //A[i] = i+1;\n        //A[i] = i%2==0?i+1:i;\n        A[i] = i%2==0?i:i+1;\n        B[i] = 0;\n    }\n\n    return A;\n}\n\n// Compute output in the host\nstatic int unique_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(A[my] != A[my-1]) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n\n    return pos;\n}\n\n// Params \ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:i:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n// Main\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = unique_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n    return 0;\n  }\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc unique.cu -I/usr/local/cuda/include -lm -o unique -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm unique\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/gpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./unique 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__device__ T warp_up(T reg, int delta){\n  __shared__ volatile T R[L_DIM];\n\n  R[threadIdx.x] = reg;\n\n  return (lane_id() - delta >= 0 ? R[threadIdx.x - delta] : 0);\n}\n__device__ T __shuffle_up(T* matrix, int my_s, int pos, T regi, int i){\n#if (__CUDA_ARCH__ >= 300 )\n  T p = __shfl_up(regi, 1);\n#else\n  T p = warp_up(regi, 1);\n#endif\n  if(lane_id() == 0 && i > 0)\n    p = matrix[pos - 1]; \n  if(lane_id() == 0 && threadIdx.x != 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s > 0 && threadIdx.x == 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s == 0 && threadIdx.x == 0 && i == 0)\n    p = -1;\n  return p;\n}\n\n__global__ void unique(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(reg[j] != __shuffle_up(matrix, my_s, pos, reg[j], j))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/baselines/gpu/unique.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_unique(T* output, T* input, int elements){\n  int j = 0;\n  output[j] = input[j];\n  j++;\n  for (int i = 1; i < elements; i++){\n    if (input[i] != input[i-1]){\n      output[j] = input[i];\n      j++;\t\t\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Unique on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n\n  // Allocate the device input vector A\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n\n#define WARMUP 0\n#define REP 1\n  int value1 = 0;\n  int value2 = 1;\n  int value3 = 2;\n  int value4 = 3;\n  unsigned int flagM = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++){\n    \th_A[i] = value1;\n        if(i >= numElements/4 && i < numElements/2) h_A[i] = value2;\n        if(i >= numElements/2 && i < 3*numElements/4) h_A[i] = value3;\n        if(i >= 3*numElements/4 && i < numElements) h_A[i] = value4;\n    }\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x]==value1 || h_A[x]==value2 || h_A[x]==value3 || h_A[x]==value4){\n    \t    h_A[x] = x+2;\n            m--;\n        }\n    }\n\n#if PRINT\n    printf(\"\\n\");\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch\n    unique<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags);\n\n    cudaMemcpy(&flagM, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_unique(h_C, h_A, numElements);\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_C+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM - 1; ++i){\n      if (h_B[i] != h_C[i]){\n          fprintf(stderr, \"Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n\n  return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/UNI/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(UNI_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/dpu/task.c",
    "content": "/*\n* Unique with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nT        message_value[NR_TASKLETS];\nuint32_t message_offset[NR_TASKLETS];\nuint32_t message_partial_count;\nT        message_last_from_last;\n\n// UNI in each tasklet\nunsigned int __attribute__ ((noinline)) unique(T *output, T *input){\n    unsigned int pos = 0;\n    output[pos] = input[pos];\n    pos++;\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        if(input[j] != input[j - 1]) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nuint3 __attribute__ ((noinline)) handshake_sync(T *output, unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count, o_count, offset;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n        offset = (message_value[tasklet_id] == output[0])?1:0;\n        o_count = message_offset[tasklet_id];\n    }\n    else{\n        p_count = 0;\n        offset = (message_last_from_last == output[0])?1:0;\n        o_count = 0;\n    }\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        message_value[tasklet_id + 1] = output[l_count - 1];\n        message_offset[tasklet_id + 1] = o_count + offset;\n        handshake_notify();\n    }\n    uint3 result = {p_count, o_count, offset}; \n    return result;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1){\n        message_partial_count = 0;\n        message_last_from_last = 0xFFFFFFFF; // A value that is not in the input array\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    unsigned int i = 0; // Iteration count\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // UNI in each tasklet\n        unsigned int l_count = unique(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint3 po_count = handshake_sync(cache_B, l_count, tasklet_id);\n\n        // Write cache to current MRAM block\n        mram_write(&cache_B[po_count.z], (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + po_count.x - po_count.y) * sizeof(T)), l_count * sizeof(T));\n\n        // First\n        if(tasklet_id == 0 && i == 0){\n            result->first = cache_B[0];\n        }\n        \n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            message_last_from_last = cache_B[l_count - 1];\n            result->last = cache_B[l_count - 1];\n            result->t_count = message_partial_count + po_count.x + l_count - po_count.y - po_count.z;\n            message_partial_count = result->t_count;\n        }\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        i++;\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\nstruct dpu_arguments_t {\n    int size;\n\tint kernel;\n};\n\nstruct dpu_results_t{\n    long t_count;\n    long first;\n    long last;\n};\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 1024\n\n#define REGS 128\n\nvoid read_input(long* A, int nr_elements, int nr_elements_round) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i%2==0?i:i+1;\n    }\n    for (int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = A[nr_elements - 1];\n    }\n}\n\nint unique_host(long* C, long* A, int nr_elements) {\n    int pos = 0;\n    C[pos] = A[pos];\n    pos++;\n    for(int i = 1; i < nr_elements; i++) {\n        if(A[i] != A[i-1]) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    long* A;\n    long* C;\n    long* C2;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n    int nr_of_dpus = NUM_DPUS;\n\n    dpu_alloc(nr_of_dpus, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int i = 0;\n    int accum = 0;\n    int total_count = 0;\n\n    int input_size = DATA_PREP_PARAMS;\n    int input_size_dpu_ = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_round = (input_size_dpu_ % (NUM_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NUM_TASKLETS * REGS)) : input_size_dpu_;\n\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(long));\n    long *bufferA = A;\n    long *bufferC = C2;\n\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    total_count = unique_host(C, A, input_size);\n\n    int input_size_dpu = input_size_dpu_round;\n    int kernel = 0;\n    struct dpu_arguments_t* input_arguments = malloc(sizeof(struct dpu_arguments_t));\n    input_arguments->size = input_size_dpu * sizeof(long);\n    input_arguments->kernel = kernel;\n\n    i = 0;\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, input_arguments);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(long), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    struct dpu_results_t* results = malloc(nr_of_dpus * sizeof(struct dpu_results_t));\n    int* results_scan = malloc(nr_of_dpus * sizeof(int));\n    int* offset = malloc(nr_of_dpus * sizeof(int));\n    int* offset_scan = malloc(nr_of_dpus * sizeof(int));\n    i = 0;\n    accum = 0;\n\n    struct dpu_results_t* results_retrieve = malloc(nr_of_dpus * NUM_TASKLETS * sizeof(struct dpu_results_t));\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &results_retrieve[i * NUM_TASKLETS]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NUM_TASKLETS * sizeof(struct dpu_results_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        for (int each_tasklet = 0; each_tasklet < NUM_TASKLETS; each_tasklet++) {\n            if(each_tasklet == 0){\n                results[i].first = results_retrieve[i * NUM_TASKLETS + each_tasklet].first;\n            }\n\n            if(each_tasklet == NUM_TASKLETS - 1){\n                results[i].t_count = results_retrieve[i * NUM_TASKLETS + each_tasklet].t_count;\n                results[i].last = results_retrieve[i * NUM_TASKLETS + each_tasklet].last;\n            }\n        }\n\n        if(i != 0){\n            if(results[i].first == results[i - 1].last) {\n                offset[i] = 1;\n            }\n\n            offset_scan[i] += offset[i];\n        }\n\n        int temp = results[i].t_count - offset[i];\n        results_scan[i] = accum;\n        accum += temp;\n    }\n\n    i = 0;\n    DPU_FOREACH (dpu_set, dpu, i) {\n        dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(long), &bufferC[results_scan[i] - offset_scan[i]], results[i].t_count * sizeof(long));\n    }\n\n    free(results_scan);\n    free(offset);\n    free(offset_scan);\n\n    int status = 1;\n    if(accum != total_count) {\n        status = 0;\n        break;\n    }\n\n    for (i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(A);\n    free(C);\n    free(C2);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Data type\n#define T int64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n    T first;\n    T last;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\ntypedef struct{unsigned int x; unsigned int y; unsigned int z;} uint3;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/UNI/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/CMakeLists.txt",
    "content": "# add_subdirectory(host)\r\nadd_subdirectory(dpu)"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nTYPE ?= INT32\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o ${HOST_TARGET}.bin ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o va -fopenmp app_baseline.c \n\nclean:\n\trm va\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/cpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va -t 4\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic int32_t *A;\nstatic int32_t *B;\nstatic int32_t *C;\nstatic int32_t *C2; \n\n/**\n* @brief creates a \"test file\" by filling a buffer of 64MB with pseudo-random values\n* @param nr_elements how many 32-bit elements we want the file to be\n* @return the buffer address\n*/\nvoid  *create_test_file(unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    A = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    B = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    C = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    \n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = (int) (rand());\n        B[i] = (int) (rand());\n    }\n\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void vector_addition_host(unsigned int nr_elements, int t) {\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for (int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16777216;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads        = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    vector_addition_host(file_size, p.n_threads);\n\t\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n\n   return 0;\n }\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc vec_add.cu -I/usr/local/cuda/include -lm -o va\n\nclean:\n\trm va\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/gpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/baselines/gpu/vec_add.cu",
    "content": "/* File:     vec_add.cu\n * Purpose:  Implement vector addition on a gpu using cuda\n *\n * Compile:  nvcc [-g] [-G] -o vec_add vec_add.cu\n * Run:      ./vec_add\n */\n\n#include <stdio.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <math.h>\n\n__global__ void Vec_add(unsigned int x[], unsigned int y[], unsigned int z[], int n) {\n    int thread_id = blockIdx.x * blockDim.x + threadIdx.x;\n    if (thread_id < n){\n        z[thread_id] = x[thread_id] + y[thread_id];\n    }\n}\n\n\nint main(int argc, char* argv[]) {\n    int n, m;\n    unsigned int *h_x, *h_y, *h_z;\n    unsigned int *d_x, *d_y, *d_z;\n    size_t size;\n\n    /* Define vector length */\n    n = 2621440;\n    m = 320;\n    size = m * n * sizeof(unsigned int);\n\n    // Allocate memory for the vectors on host memory.\n    h_x = (unsigned int*) malloc(size);\n    h_y = (unsigned int*) malloc(size);\n    h_z = (unsigned int*) malloc(size);\n\n    for (int i = 0; i < n * m; i++) {\n        h_x[i] = i+1;\n        h_y[i] = n-i;\n    }\n\n    printf(\"Input size = %d\\n\", n * m);\n\n    // Print original vectors.\n    /*printf(\"h_x = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_x[i]);\n    }\n    printf(\"\\n\\n\");\n    printf(\"h_y = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_y[i]);\n    }\n    printf(\"\\n\\n\");*/\n\n    // Event creation\n    cudaEvent_t start, stop;\n    cudaEventCreate(&start);\n    cudaEventCreate(&stop);\n    float time1 = 0;\n\n    /* Allocate vectors in device memory */\n    cudaMalloc(&d_x, size);\n    cudaMalloc(&d_y, size);\n    cudaMalloc(&d_z, size);\n\n    /* Copy vectors from host memory to device memory */\n    cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);\n    cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);\n    \n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    /* Kernel Call */\n    Vec_add<<<(n * m) / 256, 256>>>(d_x, d_y, d_z, n * m);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n\n    cudaMemcpy(h_z, d_z, size, cudaMemcpyDeviceToHost);\n    /*printf(\"The sum is: \\n\");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_z[i]);\n    }\n    printf(\"\\n\");*/\n\n    printf(\"Execution time = %f ms\\n\", time1);\n\n    /* Free device memory */\n    cudaFree(d_x);\n    cudaFree(d_y);\n    cudaFree(d_z);\n    /* Free host memory */\n    free(h_x);\n    free(h_y);\n    free(h_z);\n\n    return 0;\n}  /* main */\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/dpu/CMakeLists.txt",
    "content": "SET(BL 10)\r\nSET(TYPE INT32)\r\n\r\nset(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\r\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/VA/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\")\r\n\r\nfile(GLOB_RECURSE SRCS *.c)\r\n\r\nadd_executable(VA_device ${SRCS})\r\n\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/dpu/task.c",
    "content": "/*\n* Vector addition with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// vector_addition: Computes the vector addition of a cached block \nvoid __attribute__ ((noinline)) vector_addition(T *bufferB, T *bufferA, unsigned int l_size) {\n    for (unsigned int i = 0; i < l_size; i++){\n        bufferB[i] += bufferA[i];\n    }\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, l_size_bytes);\n\n        // Computer vector addition\n        vector_addition(cache_B, cache_A, l_size_bytes >> DIV);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), l_size_bytes);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/host/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/usr/bin/gcc\")\nset(CMAKE_C_FLAGS \"-std=c99 -O3\")\n\nfind_package(PkgConfig REQUIRED)\npkg_check_modules(DPU REQUIRED dpu)\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_executable(VA_host ${SRCS})\n\ntarget_link_libraries(VA_host ${DPU_LIBRARIES})\ntarget_include_directories(VA_host PUBLIC ${DPU_INCLUDE_DIRS})\ntarget_compile_options(VA_host PUBLIC ${DPU_CFLAGS_OTHER})\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/host/app.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\nstruct dpu_arguments_t {\n    int size;\n    int transfer_size;\n    int kernel;\n};\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 1024\n\nvoid read_input(int* A, int* B, int nr_elements) {\n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = i;\n        B[i] = i;\n    }\n}\n\nvoid vector_addition_host(int* C, int* A, int* B, int nr_elements) {\n    for (int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\nint roundup(int n, int m) {\n    return ((n / m) * m + m);\n}\n\nint divceil(int n, int m) {\n    return ((n-1) / m + 1);\n}\n\nint main() {\n    int BL = 10;\n    int BLOCK_SIZE_LOG2 = BL;\n    int BLOCK_SIZE = (1 << BLOCK_SIZE_LOG2);\n\n    int* A;\n    int* B;\n    int* C;\n    int* C2;\n\n    struct dpu_set_t dpu_set;\n    struct dpu_set_t dpu;\n\n    int nr_of_dpus = NUM_DPUS;\n    int input_size = DATA_PREP_PARAMS;\n\n    dpu_alloc(nr_of_dpus, NULL, &dpu_set);\n    dpu_load(dpu_set, DPU_BINARY, NULL);\n\n    int i = 0;\n\n    int input_size_8bytes = ((input_size * sizeof(int)) % 8) != 0 ? roundup(input_size, 8) : input_size;\n    int input_size_dpu = divceil(input_size, nr_of_dpus);\n    int input_size_dpu_8bytes = ((input_size_dpu * sizeof(int)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu;\n\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    B = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    C = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    C2 = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(int));\n    int *bufferA = A;\n    int *bufferB = B;\n    int *bufferC = C2;\n\n    read_input(A, B, input_size);\n\n    vector_addition_host(C, A, B, input_size);\n\n    int kernel = 0;\n    struct dpu_arguments_t* input_arguments = malloc(sizeof(struct dpu_arguments_t) * nr_of_dpus);\n    for(i=0; i<nr_of_dpus-1; i++) {\n        input_arguments[i].size = input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].transfer_size = input_size_dpu_8bytes * sizeof(int);\n        input_arguments[i].kernel = kernel;\n    }\n    input_arguments[nr_of_dpus-1].size = (input_size_8bytes - input_size_dpu_8bytes * (nr_of_dpus-1)) * sizeof(int);\n    input_arguments[nr_of_dpus-1].transfer_size = input_size_dpu_8bytes * sizeof(int);\n    input_arguments[nr_of_dpus-1].kernel = kernel;\n\n    i = 0;\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &input_arguments[i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(struct dpu_arguments_t), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferA[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(int), DPU_XFER_DEFAULT);\n\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferB[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(int), input_size_dpu_8bytes * sizeof(int), DPU_XFER_DEFAULT);\n\n    dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n    i = 0;\n    DPU_FOREACH(dpu_set, dpu, i) {\n        dpu_prepare_xfer(dpu, &bufferC[input_size_dpu_8bytes * i]);\n    }\n    dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(int), input_size_dpu_8bytes * sizeof(int), DPU_XFER_DEFAULT);\n\n    int status = 1;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = 0;\n            break;\n        }\n    }\n\n    assert(status);\n\n    free(input_arguments);\n    free(A);\n    free(B);\n    free(C);\n    free(C2);\n    dpu_free(dpu_set);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2621440 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2621440;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA_SIMPLE/CMakeLists.txt",
    "content": "# add_subdirectory(host)\nadd_subdirectory(dpu)\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA_SIMPLE/dpu/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-w -I/root/uPIMulator/benchmark/VA/support -O2 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_executable(VA_SIMPLE_device ${SRCS})\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA_SIMPLE/dpu/task.c",
    "content": "#include <alloc.h>\n#include <barrier.h>\n#include <defs.h>\n#include <mram.h>\n\n__host int size_per_dpu;\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nvoid vector_addition(int *A, int *B, int *C, int size_per_tasklet) {\n  for (int i = 0; i < size_per_tasklet / sizeof(int); i++) {\n    C[i] = A[i] + B[i];\n  }\n}\n\nint main() {\n  int tasklet_id = me();\n  if (tasklet_id == 0) {\n    mem_reset();\n  }\n  barrier_wait(&my_barrier);\n\n  int size_per_tasklet = size_per_dpu / NR_TASKLETS;\n\n  int *A_mram = (int *)(DPU_MRAM_HEAP_POINTER + tasklet_id * size_per_tasklet);\n  int *B_mram = (int *)(DPU_MRAM_HEAP_POINTER + size_per_dpu + tasklet_id * size_per_tasklet);\n  int *C_mram = (int *)(DPU_MRAM_HEAP_POINTER + 2 * size_per_dpu + tasklet_id * size_per_tasklet);\n\n  int *A_wram = (int *)mem_alloc(size_per_tasklet);\n  int *B_wram = (int *)mem_alloc(size_per_tasklet);\n  int *C_wram = (int *)mem_alloc(size_per_tasklet);\n\n  mram_read((__mram_ptr void *)A_mram, A_wram, size_per_tasklet);\n  mram_read((__mram_ptr void *)B_mram, B_wram, size_per_tasklet);\n\n  vector_addition(A_wram, B_wram, C_wram, size_per_tasklet);\n\n  mram_write(C_wram, (__mram_ptr void *)C_mram, size_per_tasklet);\n\n  return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA_SIMPLE/host/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/usr/bin/gcc\")\nset(CMAKE_C_FLAGS \"-std=c99 -O3\")\n\nfind_package(PkgConfig REQUIRED)\npkg_check_modules(DPU REQUIRED dpu)\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_executable(VA_SIMPLE_host ${SRCS})\n\ntarget_link_libraries(VA_SIMPLE_host ${DPU_LIBRARIES})\ntarget_include_directories(VA_SIMPLE_host PUBLIC ${DPU_INCLUDE_DIRS})\ntarget_compile_options(VA_SIMPLE_host PUBLIC ${DPU_CFLAGS_OTHER})\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/VA_SIMPLE/host/app.c",
    "content": "#include <dpu.h>\n#include <stdlib.h>\n#include <assert.h>\n\n#define VECTOR_SIZE 1024\n\n#define NUM_DPUS 1\n#define NUM_TASKLETS 1\n#define DATA_PREP_PARAMS 1024\n\nstruct vector_t {\n  int size;\n  int* data;\n};\n\nstruct vector_t* vector_init(int size);\nvoid vector_prep(struct vector_t* vector);\nvoid vector_add(struct vector_t* a, struct vector_t *b, struct vector_t* c);\nvoid vector_equal(struct vector_t* a, struct vector_t* b);\n\nint main() {\n  struct dpu_set_t dpu_set;\n  struct dpu_set_t dpu;\n\n  dpu_alloc(NUM_DPUS, nullptr, &dpu_set);\n\n  dpu_load(dpu_set, \"../device/device\", nullptr);\n\n  struct vector_t *A = vector_init(VECTOR_SIZE);\n  struct vector_t *B = vector_init(VECTOR_SIZE);\n  struct vector_t *C_host = vector_init(VECTOR_SIZE);\n  struct vector_t *C_device = vector_init(VECTOR_SIZE);\n\n  vector_prep(A);\n  vector_prep(B);\n\n  vector_add(A, B, C_host);\n\n  int size_per_dpu = (VECTOR_SIZE / NUM_DPUS) * sizeof(int);\n  int i;\n\n  DPU_FOREACH(dpu_set, dpu, i) { dpu_prepare_xfer(dpu, &size_per_dpu); }\n  dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"size_per_dpu\", 0, sizeof(int), DPU_XFER_DEFAULT);\n\n  DPU_FOREACH(dpu_set, dpu, i) { dpu_prepare_xfer(dpu, &(A->data[(size_per_dpu / sizeof(int)) * i])); }\n  dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, size_per_dpu, DPU_XFER_DEFAULT);\n\n  DPU_FOREACH(dpu_set, dpu, i) { dpu_prepare_xfer(dpu, &(B->data[(size_per_dpu / sizeof(int)) * i])); }\n  dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, size_per_dpu, size_per_dpu, DPU_XFER_DEFAULT);\n\n  dpu_launch(dpu_set, DPU_SYNCHRONOUS);\n\n  DPU_FOREACH(dpu_set, dpu, i) { dpu_prepare_xfer(dpu, &(C_device->data[(size_per_dpu / sizeof(int)) * i])); }\n  dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, 2 * size_per_dpu, size_per_dpu, DPU_XFER_DEFAULT);\n\n  vector_equal(C_host, C_device);\n\n  return 0;\n}\n\nstruct vector_t* vector_init(int size) {\n  struct vector_t* vector = malloc(sizeof(struct vector_t));\n\n  vector->size = size;\n  vector->data = malloc(VECTOR_SIZE * sizeof(int));\n\n  return vector;\n}\n\nvoid vector_prep(struct vector_t* vector) {\n  for (int i = 0; i < vector->size; i++) {\n    vector->data[i] = i;\n  }\n}\n\nvoid vector_add(struct vector_t* a, struct vector_t* b, struct vector_t* c) {\n  assert(a->size == b->size);\n  assert(a->size == c->size);\n\n  for (int i = 0; i < c->size; i++) {\n    c->data[i] = a->data[i] + b->data[i];\n  }\n}\n\nvoid vector_equal(struct vector_t *a, struct vector_t *b) {\n  assert(a->size == b->size);\n\n  for (int i = 0; i < a->size; i++) {\n    assert(a->data[i] == b->data[i]);\n  }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/benchmark/build.py",
    "content": "import os\nimport shutil\nimport subprocess\nimport argparse\n\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\"--num_dpus\", type=int, default=1)\n    parser.add_argument(\"--num_tasklets\", type=int, default=1)\n    args = parser.parse_args()\n\n    benchmark_dir_path = os.path.dirname(__file__)\n\n    build_dir_path = os.path.join(benchmark_dir_path, \"build\")\n\n    if os.path.exists(build_dir_path):\n        shutil.rmtree(build_dir_path)\n    os.makedirs(build_dir_path)\n\n    subprocess.run(\n        [\n            \"cmake\",\n            \"-D\",\n            f\"NR_DPUS={args.num_dpus}\",\n            \"-D\"\n            f\"NR_TASKLETS={args.num_tasklets}\",\n            \"-S\",\n            benchmark_dir_path,\n            \"-B\",\n            build_dir_path,\n            \"-G\",\n            \"Ninja\",\n        ]\n    )\n    subprocess.run([\"ninja\", \"-C\", build_dir_path])\n"
  },
  {
    "path": "golang_vm/uPIMulator/docker/Dockerfile",
    "content": "FROM ubuntu:22.04\r\n\r\nENV DEBIAN_FRONTEND=noninteractive\r\n\r\nRUN apt update\r\nRUN apt install -y git\r\nRUN apt install -y wget\r\nRUN apt install -y cmake\r\nRUN apt install -y ninja-build\r\nRUN apt install -y pkg-config\r\nRUN apt install -y python3\r\nRUN apt install -y python3-pip\r\n\r\n# UPMEM SDK\r\nWORKDIR /root\r\nRUN wget sdk-releases.upmem.com/2023.2.0/ubuntu_22.04/upmem-2023.2.0-Linux-x86_64.tar.gz\r\nRUN tar -zxvf upmem-2023.2.0-Linux-x86_64.tar.gz\r\nRUN echo \"source /root/upmem-2023.2.0-Linux-x86_64/upmem_env.sh\" > /root/.bashrc\r\n\r\nWORKDIR /root/uPIMulator\r\n"
  },
  {
    "path": "golang_vm/uPIMulator/go.mod",
    "content": "module uPIMulator\n\ngo 1.21.5\n"
  },
  {
    "path": "golang_vm/uPIMulator/script/build.py",
    "content": "import os\nimport shutil\nimport subprocess\n\n\nif __name__ == \"__main__\":\n    script_dirpath = os.path.dirname(__file__)\n\n    build_dirpath = os.path.join(script_dirpath, \"..\", \"build\")\n    src_dirpath = os.path.join(script_dirpath, \"..\", \"src\")\n\n    if os.path.exists(build_dirpath):\n        shutil.rmtree(build_dirpath)\n    os.makedirs(build_dirpath)\n\n    binary_filepath = os.path.join(build_dirpath, \"uPIMulator\")\n\n    subprocess.run([\"go\", \"build\", \"-C\", src_dirpath, \"-o\", binary_filepath])\n"
  },
  {
    "path": "golang_vm/uPIMulator/script/format.py",
    "content": "import os\nimport subprocess\n\n\nif __name__ == \"__main__\":\n    script_dirpath = os.path.dirname(__file__)\n\n    src_dirpath = os.path.join(script_dirpath, \"..\", \"src\")\n\n    subprocess.run([\"gofmt\", \"-l\", src_dirpath])\n    subprocess.run([\"golines\", \"-w\", src_dirpath])\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\nproject(sdk)\n\nadd_subdirectory(misc)\nadd_subdirectory(stdlib)\nadd_subdirectory(syslib)\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/build.py",
    "content": "import os\nimport shutil\nimport subprocess\nimport argparse\n\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\"--num_tasklets\", type=int, default=1)\n    args = parser.parse_args()\n\n    sdk_dir_path = os.path.dirname(__file__)\n\n    build_dir_path = os.path.join(sdk_dir_path, \"build\")\n\n    if os.path.exists(build_dir_path):\n        shutil.rmtree(build_dir_path)\n    os.makedirs(build_dir_path)\n\n    subprocess.run(\n        [\n            \"cmake\",\n            \"-D\",\n            f\"NR_TASKLETS={args.num_tasklets}\",\n            \"-S\",\n            sdk_dir_path,\n            \"-B\",\n            build_dir_path,\n            \"-G\",\n            \"Ninja\",\n        ]\n    )\n    subprocess.run([\"ninja\", \"-C\", build_dir_path])\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(misc ${SRCS})\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/accessMramFromDpu.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    // Preconditions:\n    //  - MRAM offset is a multiple of 8\n    //  - Buffer size is a multiple of 8\n\n    __asm__ volatile(\"  sd zero, 0, d0\\n\" // Saving context\n                     \"  sd zero, 8, d2\\n\"\n                     \"  or r0, zero, 0, ?xnz, . + 2\\n\"\n                     \"  or r0, r0, 0x2\\n\"\n                     \"  addc r0, r0, 0\\n\"\n                     \"  sw zero, 16, r0\\n\"\n                     \"  lw r0, zero, 20\\n\" // MRAM offset, must be patched by the Host\n                     \"resume_start:\\n\"\n                     \"  lw r1, zero, 24\\n\" // Buffer size, must be patched by the Host\n                     \"  move r2, 32\\n\" // Wram offset\n                     \"  move r3, 2048\\n\" // Transfer size\n                     \"  transfer_loop:\\n\"\n                     \"  jltu r1, r3, last_transfer\\n\"\n                     \"  ldma r2, r0, 255\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r3\\n\"\n                     \"  add r2, r2, r3\\n\"\n                     \"  sub r1, r1, r3, true, transfer_loop\\n\"\n                     \"last_transfer:\\n\"\n                     \"  jz r1, end\\n\"\n                     \"  lsr r3, r1, 3\\n\"\n                     \"  add r3, r3, -1\\n\"\n                     \"  lsl_add r2, r2, r3, 24\\n\"\n                     \"  ldma r2, r0, 0\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r1\\n\"\n                     \"end:\\n\"\n                     \"  lw r2, zero, 28\\n\" // Restoring context if needed\n                     \"  jnz r2, . + 2\\n\"\n                     \"  stop true, resume_start\\n\"\n                     \"  ld d2, zero, 8\\n\"\n                     \"  lw r0, zero, 16\\n\"\n                     \"  add r1, r0, r0\\n\"\n                     \"  add r0, r0, r1\\n\"\n                     \"  call zero, r0, . + 1\\n\"\n                     \"  add r0, zero, 0x00000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 0\n                     \"  add r0, mneg, 0x80000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 1\n                     \"  add r0, zero, 0x00000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 0\n                     \"  add r0, mneg, 0x80000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 1\n    );\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/coreDump.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"core dump\" program, used by debugging processes to fetch each\n * runtime register and the atomic bits.\n * The program should be booted once on runtime 0.\n *\n * The output in WRAM has the following form:\n *  - byte 0..255 = atomic bits : each bit is stored into an individual byte\n *  - byte 256..2559 = work registers\n *  - byte 2560..2555 = flags\n *\n * Only the runtime 0 fills in the atomic bits part of the output.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0), d0\\n\"\n        \"  or r0, zero, 0, ?xnz, no_z_flag\\n\"\n        \"  or r0, r0, 0x2\\n\"\n        \"  no_z_flag:\\n\"\n        \"  addc r0, r0, 0\\n\"\n        \"  sw id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12), r0\\n\"\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1), d2\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2), d4\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3), d6\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4), d8\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5), d10\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6), d12\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7), d14\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8), d16\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9), d18\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10), d20\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11), d22\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  sb r0, 0, 0xFF\\n\"\n        \"  acquire r0, 0, nz, atomic_next\\n\"\n        \"  sb r0, 0, 0x00\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/crt0.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <macro_utils.h>\n#include <attributes.h>\n#include <stdint.h>\n#include <dpuruntime.h>\n\n__mram_noinit uint8_t __sys_used_mram_end[0];\n\nuint64_t __sys_null_pointer __attribute__((used, section(\".data.__sys_zero\"))) = 0ULL;\n\nuint32_t __lower_data(\"thread_profiling\") thread_profiling[NR_THREADS];\nuint32_t perfcounter_end_value;\n\n#define DECLARE_STACK(x)                                                                                                         \\\n    extern uint32_t __sys_stack_thread_##x;                                                                                      \\\n    extern uint32_t STACK_SIZE_TASKLET_##x;\n#define SET_STACK_TABLE_PTR(x)                                                                                                   \\\n    [x] = { .stack_ptr = (uint32_t)&__sys_stack_thread_##x, .stack_size = (uint32_t)&STACK_SIZE_TASKLET_##x },\n\n__FOR_EACH_THREAD(DECLARE_STACK);\n\nthread_stack_t __keep __dma_aligned __SP_TABLE__[NR_THREADS] = { __FOR_EACH_THREAD(SET_STACK_TABLE_PTR) };\n\n__host const volatile uint32_t CLOCKS_PER_SEC;\n\n__host const volatile uint32_t error_storage;\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"), no_instrument_function)) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jnz id, __sys_start_thread\\n\"\n        __CONFIG_PERFCOUNTER_ENTRY__\n        \"  sd zero, \" __STR(__STDOUT_BUFFER_STATE) \", 0\\n\"\n        \"  move r23, \" __STR(__atomic_end_addr) \"\\n\"\n        \"__sys_atomic_bit_clear:\\n\"\n        \"  jeq r23, \" __STR(__atomic_used_addr) \", __sys_start_thread\\n\"\n        \"  release r23, 0, nz, . + 1\\n\"\n        \"  add r23, r23, -1, true, __sys_atomic_bit_clear\\n\"\n        \"__sys_start_thread:\\n\"\n        \"  jeq id, NR_TASKLETS - 1, . + 2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d22, id8, \" __STR(__SP_TABLE__) \"\\n\"\n        \"  call r23, main\\n\"\n        \".globl __sys_end\\n\"\n        \"__sys_end:\\n\"\n        __SAVE_PERFCOUNTER_ENTRY__\n        \"  stop true, __sys_end\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/dpu.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Default linker script for DPU programs.\n * The bootstrap sequence is generated by the studio as __bootstrap.\n * The two DPU memories (IRAM and WRAM) are mapped on two different\n * \"virtual\" spaces:\n *  - IRAM: starts at address 0x80000000, which may imply fixups\n *    when loading and debugging of programs\n *  - WRAM: exposed as is at address 0x00000000\n *\n * In addition, the run-time environment information is stored into\n * a virtual physical space at 0x40000000.\n */\nENTRY(__bootstrap)\nMEMORY {\n    iram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n    mram (wa) : ORIGIN = 0x08000000, LENGTH = 64M\n    wram (wa) : ORIGIN = 0x00000000, LENGTH = 64K\n    atomic (r) : ORIGIN = 0xF0000000, LENGTH = 256\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text.__bootstrap)\n    *(.text)\n    *(.text.*) \n  } > iram\n\n  /*\n   * Atomic bits 'allocator'\n   */\n  .atomic (NOLOAD) : {\n    __atomic_start_addr = .;\n    . = . + 200;\n    __atomic_used_addr = .;\n    *(.atomic)\n    __atomic_end_addr = .;\n  } > atomic\n\n  /*\n   * Locate every other section as data.\n   */\n  .data : {\n    KEEP(*(.data.__sys_zero))\n    . += MAX(8, .);\n    /* WRAM accessible using loads and stores with immediate 11-bit offsets */\n    *(.data.immediate_memory .data.immediate_memory.*)\n    HIDDEN(__imm_mem_end = .);\n    ASSERT(__imm_mem_end < 2048, \"immediate memory not accessible with 11-bit address\")\n    __rodata_start_addr = .;\n    *(.rodata .rodata.*)\n    __rodata_end_addr = .;\n    *(.bss .bss.*)\n    *(COMMON)\n    /* Data that we want to keep even there seems to be no use,\n     * usually because host may need it.\n     */\n    KEEP(*(.data.__sys_keep))\n    *(.data .data.*)\n    . = ALIGN(8);\n  } > wram\n\n  .data.__sys_host : {\n    . = ALIGN(8);\n    KEEP(*(.dpu_host))\n  } > wram\n\n  .data.__sys_profiling : {\n    . = ALIGN(4);\n    KEEP(*(.dpu_profiling))\n  } > wram\n\n  .data.stacks (NOLOAD) : {\n    ASSERT(NR_TASKLETS >= 0 && NR_TASKLETS <= 24, \"NR_TASKLETS should be in the range: [0; 24]\")\n    ASSERT(((STACK_SIZE_TASKLET_0  % 8 == 0) && (STACK_SIZE_TASKLET_0  > 0)) || (NR_TASKLETS <= 0 ), \"STACK_SIZE_TASKLET_0  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_1  % 8 == 0) && (STACK_SIZE_TASKLET_1  > 0)) || (NR_TASKLETS <= 1 ), \"STACK_SIZE_TASKLET_1  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_2  % 8 == 0) && (STACK_SIZE_TASKLET_2  > 0)) || (NR_TASKLETS <= 2 ), \"STACK_SIZE_TASKLET_2  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_3  % 8 == 0) && (STACK_SIZE_TASKLET_3  > 0)) || (NR_TASKLETS <= 3 ), \"STACK_SIZE_TASKLET_3  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_4  % 8 == 0) && (STACK_SIZE_TASKLET_4  > 0)) || (NR_TASKLETS <= 4 ), \"STACK_SIZE_TASKLET_4  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_5  % 8 == 0) && (STACK_SIZE_TASKLET_5  > 0)) || (NR_TASKLETS <= 5 ), \"STACK_SIZE_TASKLET_5  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_6  % 8 == 0) && (STACK_SIZE_TASKLET_6  > 0)) || (NR_TASKLETS <= 6 ), \"STACK_SIZE_TASKLET_6  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_7  % 8 == 0) && (STACK_SIZE_TASKLET_7  > 0)) || (NR_TASKLETS <= 7 ), \"STACK_SIZE_TASKLET_7  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_8  % 8 == 0) && (STACK_SIZE_TASKLET_8  > 0)) || (NR_TASKLETS <= 8 ), \"STACK_SIZE_TASKLET_8  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_9  % 8 == 0) && (STACK_SIZE_TASKLET_9  > 0)) || (NR_TASKLETS <= 9 ), \"STACK_SIZE_TASKLET_9  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_10 % 8 == 0) && (STACK_SIZE_TASKLET_10 > 0)) || (NR_TASKLETS <= 10), \"STACK_SIZE_TASKLET_10 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_11 % 8 == 0) && (STACK_SIZE_TASKLET_11 > 0)) || (NR_TASKLETS <= 11), \"STACK_SIZE_TASKLET_11 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_12 % 8 == 0) && (STACK_SIZE_TASKLET_12 > 0)) || (NR_TASKLETS <= 12), \"STACK_SIZE_TASKLET_12 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_13 % 8 == 0) && (STACK_SIZE_TASKLET_13 > 0)) || (NR_TASKLETS <= 13), \"STACK_SIZE_TASKLET_13 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_14 % 8 == 0) && (STACK_SIZE_TASKLET_14 > 0)) || (NR_TASKLETS <= 14), \"STACK_SIZE_TASKLET_14 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_15 % 8 == 0) && (STACK_SIZE_TASKLET_15 > 0)) || (NR_TASKLETS <= 15), \"STACK_SIZE_TASKLET_15 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_16 % 8 == 0) && (STACK_SIZE_TASKLET_16 > 0)) || (NR_TASKLETS <= 16), \"STACK_SIZE_TASKLET_16 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_17 % 8 == 0) && (STACK_SIZE_TASKLET_17 > 0)) || (NR_TASKLETS <= 17), \"STACK_SIZE_TASKLET_17 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_18 % 8 == 0) && (STACK_SIZE_TASKLET_18 > 0)) || (NR_TASKLETS <= 18), \"STACK_SIZE_TASKLET_18 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_19 % 8 == 0) && (STACK_SIZE_TASKLET_19 > 0)) || (NR_TASKLETS <= 19), \"STACK_SIZE_TASKLET_19 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_20 % 8 == 0) && (STACK_SIZE_TASKLET_20 > 0)) || (NR_TASKLETS <= 20), \"STACK_SIZE_TASKLET_20 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_21 % 8 == 0) && (STACK_SIZE_TASKLET_21 > 0)) || (NR_TASKLETS <= 21), \"STACK_SIZE_TASKLET_21 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_22 % 8 == 0) && (STACK_SIZE_TASKLET_22 > 0)) || (NR_TASKLETS <= 22), \"STACK_SIZE_TASKLET_22 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_23 % 8 == 0) && (STACK_SIZE_TASKLET_23 > 0)) || (NR_TASKLETS <= 23), \"STACK_SIZE_TASKLET_23 should be a multiple of 8 and > 0\")\n    ASSERT((NR_TASKLETS > 0 ) || (STACK_SIZE_TASKLET_0  == 0) , \"STACK_SIZE_TASKLET_0  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 1 ) || (STACK_SIZE_TASKLET_1  == 0) , \"STACK_SIZE_TASKLET_1  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 2 ) || (STACK_SIZE_TASKLET_2  == 0) , \"STACK_SIZE_TASKLET_2  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 3 ) || (STACK_SIZE_TASKLET_3  == 0) , \"STACK_SIZE_TASKLET_3  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 4 ) || (STACK_SIZE_TASKLET_4  == 0) , \"STACK_SIZE_TASKLET_4  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 5 ) || (STACK_SIZE_TASKLET_5  == 0) , \"STACK_SIZE_TASKLET_5  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 6 ) || (STACK_SIZE_TASKLET_6  == 0) , \"STACK_SIZE_TASKLET_6  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 7 ) || (STACK_SIZE_TASKLET_7  == 0) , \"STACK_SIZE_TASKLET_7  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 8 ) || (STACK_SIZE_TASKLET_8  == 0) , \"STACK_SIZE_TASKLET_8  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 9 ) || (STACK_SIZE_TASKLET_9  == 0) , \"STACK_SIZE_TASKLET_9  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 10) || (STACK_SIZE_TASKLET_10 == 0) , \"STACK_SIZE_TASKLET_10 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 11) || (STACK_SIZE_TASKLET_11 == 0) , \"STACK_SIZE_TASKLET_11 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 12) || (STACK_SIZE_TASKLET_12 == 0) , \"STACK_SIZE_TASKLET_12 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 13) || (STACK_SIZE_TASKLET_13 == 0) , \"STACK_SIZE_TASKLET_13 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 14) || (STACK_SIZE_TASKLET_14 == 0) , \"STACK_SIZE_TASKLET_14 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 15) || (STACK_SIZE_TASKLET_15 == 0) , \"STACK_SIZE_TASKLET_15 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 16) || (STACK_SIZE_TASKLET_16 == 0) , \"STACK_SIZE_TASKLET_16 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 17) || (STACK_SIZE_TASKLET_17 == 0) , \"STACK_SIZE_TASKLET_17 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 18) || (STACK_SIZE_TASKLET_18 == 0) , \"STACK_SIZE_TASKLET_18 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 19) || (STACK_SIZE_TASKLET_19 == 0) , \"STACK_SIZE_TASKLET_19 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 20) || (STACK_SIZE_TASKLET_20 == 0) , \"STACK_SIZE_TASKLET_20 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 21) || (STACK_SIZE_TASKLET_21 == 0) , \"STACK_SIZE_TASKLET_21 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 22) || (STACK_SIZE_TASKLET_22 == 0) , \"STACK_SIZE_TASKLET_22 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 23) || (STACK_SIZE_TASKLET_23 == 0) , \"STACK_SIZE_TASKLET_23 should be equal to 0 as the tasklet is not active\")\n    . = ALIGN(8);\n    __sys_stack_thread_0  = .;\n    . += STACK_SIZE_TASKLET_0;\n    __sys_stack_thread_1  = .;\n    . += STACK_SIZE_TASKLET_1;\n    __sys_stack_thread_2  = .;\n    . += STACK_SIZE_TASKLET_2;\n    __sys_stack_thread_3  = .;\n    . += STACK_SIZE_TASKLET_3;\n    __sys_stack_thread_4  = .;\n    . += STACK_SIZE_TASKLET_4;\n    __sys_stack_thread_5  = .;\n    . += STACK_SIZE_TASKLET_5;\n    __sys_stack_thread_6  = .;\n    . += STACK_SIZE_TASKLET_6;\n    __sys_stack_thread_7  = .;\n    . += STACK_SIZE_TASKLET_7;\n    __sys_stack_thread_8  = .;\n    . += STACK_SIZE_TASKLET_8;\n    __sys_stack_thread_9  = .;\n    . += STACK_SIZE_TASKLET_9;\n    __sys_stack_thread_10 = .;\n    . += STACK_SIZE_TASKLET_10;\n    __sys_stack_thread_11 = .;\n    . += STACK_SIZE_TASKLET_11;\n    __sys_stack_thread_12 = .;\n    . += STACK_SIZE_TASKLET_12;\n    __sys_stack_thread_13 = .;\n    . += STACK_SIZE_TASKLET_13;\n    __sys_stack_thread_14 = .;\n    . += STACK_SIZE_TASKLET_14;\n    __sys_stack_thread_15 = .;\n    . += STACK_SIZE_TASKLET_15;\n    __sys_stack_thread_16 = .;\n    . += STACK_SIZE_TASKLET_16;\n    __sys_stack_thread_17 = .;\n    . += STACK_SIZE_TASKLET_17;\n    __sys_stack_thread_18 = .;\n    . += STACK_SIZE_TASKLET_18;\n    __sys_stack_thread_19 = .;\n    . += STACK_SIZE_TASKLET_19;\n    __sys_stack_thread_20 = .;\n    . += STACK_SIZE_TASKLET_20;\n    __sys_stack_thread_21 = .;\n    . += STACK_SIZE_TASKLET_21;\n    __sys_stack_thread_22 = .;\n    . += STACK_SIZE_TASKLET_22;\n    __sys_stack_thread_23 = .;\n    . += STACK_SIZE_TASKLET_23;\n    . = ALIGN(8);\n  } > wram\n\n\n  .data.sw_cache (NOLOAD): {\n    . = ALIGN(8);\n    __sw_cache_buffer = .;\n    . += 8 * NR_TASKLETS;\n  } > wram\n\n  .data.heap_pointer_reset (NOLOAD) : {\n    /* Start of heap: must be aligned on DMA size.\n     * Stored as a symbol \"__reset_heap_pointer\", so that\n     * the bootstrap just moves the value into a register to\n     * initialize heap pointer at each reboot.\n     */\n    . = ALIGN(8);\n    PROVIDE(__sys_heap_pointer_reset = .);\n  } > wram\n\n  .mram.noinit (NOLOAD) : {\n    *(.mram.noinit .mram.noinit.*)\n    KEEP(*(.mram.noinit.keep .mram.noinit.keep.*))\n  } > mram\n\n  .mram : {\n    *(.mram .mram.*)\n    KEEP(*(.mram.keep .mram.keep.*))\n    . = ALIGN(8);\n    __sys_used_mram_end = .;\n  } > mram\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/internalStateReset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The strict minimum to reset the internal state of the DPU (that can only be changed by a DPU program).\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sub r0, \" __STR(NR_ATOMIC_BITS) \" - 1, id\\n\"\n        \"before_release:\\n\"\n        // Resetting Atomic bits\n        \"  release r0, 0, nz, after_release\\n\"\n        \"after_release:\\n\"\n        \"  sub r0, r0, \" __STR(NR_THREADS) \", pl, before_release\\n\"\n        // Resetting Zero and Carry flags + Preparing configuration for perfcounter register\n        \"  add r0, zero, 7\\n\"\n        // Resetting Performance Counter\n        \"  time_cfg zero, r0\\n\"\n        // Resetting Pc\n        \"  stop true, 0\\n\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/linkerScript.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Simple linker script for embedded programs.\n */\nENTRY(__bootstrap)\nMEMORY {\n\tiram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text)\n  } > iram\n}\n\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/restoreRegisters.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"restore registers\" program, is used by debugging processes to restore every registers of every runtime.\n * The program should be booted once on runtime 0.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d2,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1)\\n\"\n        \"  ld d4,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2)\\n\"\n        \"  ld d6,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3)\\n\"\n        \"  ld d8,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4)\\n\"\n        \"  ld d10, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5)\\n\"\n        \"  ld d12, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6)\\n\"\n        \"  ld d14, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7)\\n\"\n        \"  ld d16, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8)\\n\"\n        \"  ld d18, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9)\\n\"\n        \"  ld d20, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10)\\n\"\n        \"  ld d22, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11)\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  lbu r1, r0, 0\\n\"\n        \"  jz r1, atomic_release\\n\"\n        \"  acquire r0, 0, true, atomic_next\\n\"\n        \"atomic_release:\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/misc/restore_carry_and_zero_flag.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"macro_utils.h\"\n\n/* clang-format off */\n#define __RESTORE_CARRY_AND_ZERO_FLAG(x) \\\n        \"add r0, zero, 0x00000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 0 */ \\\n        \"add r0, mneg, 0x80000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 1 */ \\\n        \"add r0, zero, 0x00000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 1, C = 0 */ \\\n        \"add r0, mneg, 0x80000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" // ... restore Z = 1, C = 1 */\n\n#define RESTORE_CARRY_AND_ZERO_FLAG \\\n        \"  lw r0,  id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12)\\n\" \\\n        \"  add r1, r0,  r0\\n\" \\\n        \"  add r0, r0,  r1\\n\" /* r0 =  3 * r0 (each line of ending_routines is 3 instructions) */ \\\n        \"  or  r1, id8, 0 \\n\" \\\n        \"  add r1, id4, r1\\n\" /* r1 = 12 * id (there are 12 instructions per runtime in ending_routines) */ \\\n        \"  add r0, r0,  r1\\n\" /* r0 = r0 + r1 (compute the offset (in number of instructions) to jump to) */ \\\n        \"  call zero, r0, ending_routines\\n\" \\\n        \"ending_routines:\\n\" \\\n        __FOR_EACH_THREAD(__RESTORE_CARRY_AND_ZERO_FLAG)\n\n/* clang-format on */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(stdlib ${SRCS})\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/abort.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n\nvoid\nabort()\n{\n    halt();\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/assert.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ASSERT_H_\n#define _DPUSYSCORE_ASSERT_H_\n\n/**\n * @file assert.h\n * @brief Provides a way to verify assumptions with <code>assert</code>.\n */\n\n#define static_assert _Static_assert\n\n#ifdef NDEBUG\n\n/**\n * @def assert\n * @hideinitializer\n * @brief When NDEBUG is defined, <code>assert</code> is not available and calling it will do nothing.\n */\n#define assert(ignore) ((void)0)\n\n#else\n\n#include <dpufault.h>\n#include <macro_utils.h>\n\n/**\n * @def assert\n * @hideinitializer\n * @brief Verify the assumption of the specified expression, resulting in a fault if it fails.\n *\n * @param expression the assumption to verify\n * @throws FAULT_ASSERT_FAILED when the assertion failed\n * @todo add a diagnostic message to the log, if it exists, when the assertion fails\n */\n#define assert(expression)                                                                                                       \\\n    do {                                                                                                                         \\\n        if (!(expression)) {                                                                                                     \\\n            __asm__ volatile(\"fault \" __STR(__FAULT_ASSERT_FAILED__));                                                           \\\n        }                                                                                                                        \\\n    } while (0)\n\n#endif /* NDEBUG */\n\n#endif /* _DPUSYSCORE_ASSERT_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/atoi.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nint\natoi(const char *nptr)\n{\n    int result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/atol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nlong\natol(const char *nptr)\n{\n    long result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/ctype.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_CTYPE_H_\n#define _DPUSYSCORE_CTYPE_H_\n\n/**\n * @file ctype.h\n * @brief Provides useful functions for testing and mapping characters.\n */\n\n/**\n * @brief Checks whether the specified character is a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisdigit(int c)\n{\n    return (c >= '0') && (c <= '9');\n}\n\n/**\n * @brief Checks whether the specified character is a lowercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int islower(c) { return (c >= 'a') && (c <= 'z'); }\n\n/**\n * @brief Checks whether the specified character is an uppercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is an uppercase letter (using 0 as false and anything else as true).\n */\nstatic inline int isupper(c) { return (c >= 'A') && (c <= 'Z'); }\n\n/**\n * @brief Checks whether the specified character is a letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter (using 0 as false and anything else as true).\n */\nstatic inline int\nisalpha(int c)\n{\n    return islower(c) || isupper(c);\n}\n\n/**\n * @brief Checks whether the specified character is a letter or a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter or a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisalnum(int c)\n{\n    return isalpha(c) || isdigit(c);\n}\n\n/**\n * @brief Checks whether the specified character is a control character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a control character (using 0 as false and anything else as true).\n */\nstatic inline int\niscntrl(int c)\n{\n    return (c <= 0x1f) || (c == 0x7f);\n}\n\n/**\n * @brief Checks whether the specified character is printable.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is printable (using 0 as false and anything else as true).\n */\nstatic inline int\nisprint(int c)\n{\n    return !iscntrl(c);\n}\n\n/**\n * @brief Checks whether the specified character has graphical representation using locale.\n\n * @param c an unsigned char or EOF\n * @return Whether the character has graphical representation using locale (using 0 as false and anything else as true).\n */\nstatic inline int\nisgraph(int c)\n{\n    return isprint(c) && (c != ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a punctuation character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a punctuation character (using 0 as false and anything else as true).\n */\nstatic inline int\nispunct(int c)\n{\n    return (c >= '!' && c <= '/') || (c >= ':' && c <= '@') || (c >= '[' && c <= '`') || (c >= '{' && c <= '~');\n}\n\n/**\n * @brief Checks whether the specified character is a white-space.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a white-space (using 0 as false and anything else as true).\n */\nstatic inline int\nisspace(int c)\n{\n    return (c >= 0x9 && c <= 0xd) || (c == ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a hexadecimal digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a hexadecimal digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisxdigit(int c)\n{\n    return isdigit(c) || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f');\n}\n\n/**\n * @brief Checks whether the specified character is a blank character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a blank character (using 0 as false and anything else as true).\n */\nstatic inline int\nisblank(int c)\n{\n    return c == ' ' || c == '\\t';\n}\n\n/**\n * @brief Converts the specified character to a lowercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The lowercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntolower(int c)\n{\n    return isupper(c) ? (c + 0x20) : c;\n}\n\n/**\n * @brief Converts the specified character to a uppercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The uppercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntoupper(int c)\n{\n    return islower(c) ? (c - 0x20) : c;\n}\n\n#endif /* _DPUSYSCORE_CTYPE_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/errno.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nint __errno[NR_THREADS];\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/errno.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ERRNO_H_\n#define _DPUSYSCORE_ERRNO_H_\n\n#include <defs.h>\n\n/**\n * @file errno.h\n * @brief Defines the system error numbers.\n */\n\n// errno is an array indexed on the tasklet id rather than\n// a single integer.\nextern int __errno[];\n\n// Mimic errno variable as an index to __errno.\n// Defined in such a way that users can't override errno.\n#define errno (*(__errno + me()))\n\n/**\n * @def E2BIG\n * @brief  Argument list too long.\n */\n#define E2BIG 1\n/**\n * @def EACCES\n * @brief  Permission denied.\n */\n#define EACCES 2\n/**\n * @def EADDRINUSE\n * @brief  Address in use.\n */\n#define EADDRINUSE 3\n/**\n * @def EADDRNOTAVAIL\n * @brief  Address not available.\n */\n#define EADDRNOTAVAIL 4\n/**\n * @def EAFNOSUPPORT\n * @brief  Address family not supported.\n */\n#define EAFNOSUPPORT 5\n/**\n * @def EAGAIN\n * @brief  Resource unavailable, try again.\n */\n#define EAGAIN 6\n/**\n * @def EALREADY\n * @brief  Connection already in progress.\n */\n#define EALREADY 7\n/**\n * @def EBADF\n * @brief  Bad file descriptor.\n */\n#define EBADF 8\n/**\n * @def EBADMSG\n * @brief  Bad message.\n */\n#define EBADMSG 9\n/**\n * @def EBUSY\n * @brief  Device or resource busy.\n */\n#define EBUSY 10\n/**\n * @def ECANCELED\n * @brief  Operation canceled.\n */\n#define ECANCELED 11\n/**\n * @def ECHILD\n * @brief  No child processes.\n */\n#define ECHILD 12\n/**\n * @def ECONNABORTED\n * @brief  Connection aborted.\n */\n#define ECONNABORTED 13\n/**\n * @def ECONNREFUSED\n * @brief  Connection refused.\n */\n#define ECONNREFUSED 14\n/**\n * @def ECONNRESET\n * @brief  Connection reset.\n */\n#define ECONNRESET 15\n/**\n * @def EDEADLK\n * @brief  Resource deadlock would occur.\n */\n#define EDEADLK 16\n/**\n * @def EDESTADDRREQ\n * @brief  Destination address required.\n */\n#define EDESTADDRREQ 17\n/**\n * @def EDOM\n * @brief  Mathematics argument out of domain of function.\n */\n#define EDOM 18\n/**\n * @def EDQUOT\n * @brief  Reserved.\n */\n#define EDQUOT 19\n/**\n * @def EEXIST\n * @brief  File exists.\n */\n#define EEXIST 20\n/**\n * @def EFAULT\n * @brief  Bad address.\n */\n#define EFAULT 21\n/**\n * @def EFBIG\n * @brief  File too large.\n */\n#define EFBIG 22\n/**\n * @def EHOSTUNREACH\n * @brief  Host is unreachable.\n */\n#define EHOSTUNREACH 23\n/**\n * @def EIDRM\n * @brief  Identifier removed.\n */\n#define EIDRM 24\n/**\n * @def EILSEQ\n * @brief  Illegal byte sequence.\n */\n#define EILSEQ 25\n/**\n * @def EINPROGRESS\n * @brief  Operation in progress.\n */\n#define EINPROGRESS 26\n/**\n * @def EINTR\n * @brief  Interrupted function.\n */\n#define EINTR 27\n/**\n * @def EINVAL\n * @brief  Invalid argument.\n */\n#define EINVAL 28\n/**\n * @def EIO\n * @brief  I/O error.\n */\n#define EIO 29\n/**\n * @def EISCONN\n * @brief  Socket is connected.\n */\n#define EISCONN 30\n/**\n * @def EISDIR\n * @brief  Is a directory.\n */\n#define EISDIR 31\n/**\n * @def ELOOP\n * @brief  Too many levels of symbolic links.\n */\n#define ELOOP 32\n/**\n * @def EMFILE\n * @brief  File descriptor value too large.\n */\n#define EMFILE 33\n/**\n * @def EMLINK\n * @brief  Too many links.\n */\n#define EMLINK 34\n/**\n * @def EMSGSIZE\n * @brief  Message too large.\n */\n#define EMSGSIZE 35\n/**\n * @def EMULTIHOP\n * @brief  Reserved.\n */\n#define EMULTIHOP 36\n/**\n * @def ENAMETOOLONG\n * @brief  Filename too long.\n */\n#define ENAMETOOLONG 37\n/**\n * @def ENETDOWN\n * @brief  Network is down.\n */\n#define ENETDOWN 38\n/**\n * @def ENETRESET\n * @brief  Connection aborted by network.\n */\n#define ENETRESET 39\n/**\n * @def ENETUNREACH\n * @brief  Network unreachable.\n */\n#define ENETUNREACH 40\n/**\n * @def ENFILE\n * @brief  Too many files open in system.\n */\n#define ENFILE 41\n/**\n * @def ENOBUFS\n * @brief  No buffer space available.\n */\n#define ENOBUFS 42\n/**\n * @def ENODATA\n * @brief  No message is available on the STREAM head read queue.\n */\n#define ENODATA 43\n/**\n * @def ENODEV\n * @brief  No such device.\n */\n#define ENODEV 44\n/**\n * @def ENOENT\n * @brief  No such file or directory.\n */\n#define ENOENT 45\n/**\n * @def ENOEXEC\n * @brief  Executable file format error.\n */\n#define ENOEXEC 46\n/**\n * @def ENOLCK\n * @brief  No locks available.\n */\n#define ENOLCK 47\n/**\n * @def ENOLINK\n * @brief  Reserved.\n */\n#define ENOLINK 48\n/**\n * @def ENOMEM\n * @brief  Not enough space.\n */\n#define ENOMEM 49\n/**\n * @def ENOMSG\n * @brief  No message of the desired type.\n */\n#define ENOMSG 50\n/**\n * @def ENOPROTOOPT\n * @brief  Protocol not available.\n */\n#define ENOPROTOOPT 51\n/**\n * @def ENOSPC\n * @brief  No space left on device.\n */\n#define ENOSPC 52\n/**\n * @def ENOSR\n * @brief  No STREAM resources.\n */\n#define ENOSR 53\n/**\n * @def ENOSTR\n * @brief  Not a STREAM.\n */\n#define ENOSTR 54\n/**\n * @def ENOSYS\n * @brief  Function not supported.\n */\n#define ENOSYS 55\n/**\n * @def ENOTCONN\n * @brief  The socket is not connected.\n */\n#define ENOTCONN 56\n/**\n * @def ENOTDIR\n * @brief  Not a directory or a symbolic link to a directory.\n */\n#define ENOTDIR 57\n/**\n * @def ENOTEMPTY\n * @brief  Directory not empty.\n */\n#define ENOTEMPTY 58\n/**\n * @def ENOTRECOVERABLE\n * @brief  State not recoverable.\n */\n#define ENOTRECOVERABLE 59\n/**\n * @def ENOTSOCK\n * @brief  Not a socket.\n */\n#define ENOTSOCK 60\n/**\n * @def ENOTSUP\n * @brief  Not supported.\n */\n#define ENOTSUP 61\n/**\n * @def ENOTTY\n * @brief  Inappropriate I/O control operation.\n */\n#define ENOTTY 62\n/**\n * @def ENXIO\n * @brief  No such device or address.\n */\n#define ENXIO 63\n/**\n * @def EOPNOTSUPP\n * @brief  Operation not supported on socket.\n */\n#define EOPNOTSUPP ENOTSUP\n/**\n * @def EOVERFLOW\n * @brief  Value too large to be stored in data type.\n */\n#define EOVERFLOW 65\n/**\n * @def EOWNERDEAD\n * @brief  Previous owner died.\n */\n#define EOWNERDEAD 66\n/**\n * @def EPERM\n * @brief  Operation not permitted.\n */\n#define EPERM 67\n/**\n * @def EPIPE\n * @brief  Broken pipe.\n */\n#define EPIPE 68\n/**\n * @def EPROTO\n * @brief  Protocol error.\n */\n#define EPROTO 69\n/**\n * @def EPROTONOSUPPORT\n * @brief  Protocol not supported.\n */\n#define EPROTONOSUPPORT 70\n/**\n * @def EPROTOTYPE\n * @brief  Protocol wrong type for socket.\n */\n#define EPROTOTYPE 71\n/**\n * @def ERANGE\n * @brief  Result too large.\n */\n#define ERANGE 72\n/**\n * @def EROFS\n * @brief  Read-only file system.\n */\n#define EROFS 73\n/**\n * @def ESPIPE\n * @brief  Invalid seek.\n */\n#define ESPIPE 74\n/**\n * @def ESRCH\n * @brief  No such process.\n */\n#define ESRCH 75\n/**\n * @def ESTALE\n * @brief  Reserved.\n */\n#define ESTALE 76\n/**\n * @def ETIME\n * @brief  Stream ioctl() timeout.\n */\n#define ETIME 77\n/**\n * @def ETIMEDOUT\n * @brief  Connection timed out.\n */\n#define ETIMEDOUT 78\n/**\n * @def ETXTBSY\n * @brief  Text file busy.\n */\n#define ETXTBSY 79\n/**\n * @def EWOULDBLOCK\n * @brief  Operation would block.\n */\n#define EWOULDBLOCK ENOTSUP\n/**\n * @def EXDEV\n * @brief  Cross-device link.\n */\n#define EXDEV 81\n\n#endif /* _DPUSYSCORE_ERRNO_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/exit.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include \"defs.h\"\n#include \"stdlib.h\"\n\n#define unreachable() __builtin_unreachable()\n\nvoid\nexit(int __attribute__((unused)) status)\n{\n    __asm__ volatile(\"stop true, __sys_end\");\n    unreachable();\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/inttypes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_INTTYPES_H_\n#define _DPUSYSCORE_INTTYPES_H_\n\n/**\n * @file inttypes.h\n * @brief Extends stdint.h.\n */\n\n#include <stdint.h>\n\ntypedef struct {\n    intmax_t quot;\n    intmax_t rem;\n} imaxdiv_t;\n\nstatic inline intmax_t\nimaxabs(intmax_t x)\n{\n    return (x < 0) ? -x : x;\n}\n\nstatic inline imaxdiv_t\nimaxdiv(intmax_t numer, intmax_t denom)\n{\n    imaxdiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/* Macros for printing format specifiers.  */\n\n/* Decimal notation.  */\n#define PRId8 \"d\"\n#define PRId16 \"d\"\n#define PRId32 \"d\"\n#define PRId64 \"ld\"\n\n#define PRIdLEAST8 \"d\"\n#define PRIdLEAST16 \"d\"\n#define PRIdLEAST32 \"d\"\n#define PRIdLEAST64 \"ld\"\n\n#define PRIdFAST8 \"d\"\n#define PRIdFAST16 \"d\"\n#define PRIdFAST32 \"d\"\n#define PRIdFAST64 \"ld\"\n\n#define PRIi8 \"i\"\n#define PRIi16 \"i\"\n#define PRIi32 \"i\"\n#define PRIi64 \"li\"\n\n#define PRIiLEAST8 \"i\"\n#define PRIiLEAST16 \"i\"\n#define PRIiLEAST32 \"i\"\n#define PRIiLEAST64 \"li\"\n\n#define PRIiFAST8 \"i\"\n#define PRIiFAST16 \"i\"\n#define PRIiFAST32 \"i\"\n#define PRIiFAST64 \"li\"\n\n/* Octal notation.  */\n#define PRIo8 \"o\"\n#define PRIo16 \"o\"\n#define PRIo32 \"o\"\n#define PRIo64 \"lo\"\n\n#define PRIoLEAST8 \"o\"\n#define PRIoLEAST16 \"o\"\n#define PRIoLEAST32 \"o\"\n#define PRIoLEAST64 \"lo\"\n\n#define PRIoFAST8 \"o\"\n#define PRIoFAST16 \"o\"\n#define PRIoFAST32 \"o\"\n#define PRIoFAST64 \"lo\"\n\n/* Unsigned integers.  */\n#define PRIu8 \"u\"\n#define PRIu16 \"u\"\n#define PRIu32 \"u\"\n#define PRIu64 \"lu\"\n\n#define PRIuLEAST8 \"u\"\n#define PRIuLEAST16 \"u\"\n#define PRIuLEAST32 \"u\"\n#define PRIuLEAST64 \"lu\"\n\n#define PRIuFAST8 \"u\"\n#define PRIuFAST16 \"u\"\n#define PRIuFAST32 \"u\"\n#define PRIuFAST64 \"lu\"\n\n/* lowercase hexadecimal notation.  */\n#define PRIx8 \"x\"\n#define PRIx16 \"x\"\n#define PRIx32 \"x\"\n#define PRIx64 \"lx\"\n\n#define PRIxLEAST8 \"x\"\n#define PRIxLEAST16 \"x\"\n#define PRIxLEAST32 \"x\"\n#define PRIxLEAST64 \"lx\"\n\n#define PRIxFAST8 \"x\"\n#define PRIxFAST16 \"x\"\n#define PRIxFAST32 \"x\"\n#define PRIxFAST64 \"lx\"\n\n/* UPPERCASE hexadecimal notation.  */\n#define PRIX8 \"X\"\n#define PRIX16 \"X\"\n#define PRIX32 \"X\"\n#define PRIX64 \"lX\"\n\n#define PRIXLEAST8 \"X\"\n#define PRIXLEAST16 \"X\"\n#define PRIXLEAST32 \"X\"\n#define PRIXLEAST64 \"lX\"\n\n#define PRIXFAST8 \"X\"\n#define PRIXFAST16 \"X\"\n#define PRIXFAST32 \"X\"\n#define PRIXFAST64 \"lX\"\n\n/* Macros for printing `intmax_t' and `uintmax_t'.  */\n#define PRIdMAX \"ld\"\n#define PRIiMAX \"li\"\n#define PRIoMAX \"lo\"\n#define PRIuMAX \"lu\"\n#define PRIxMAX \"lx\"\n#define PRIXMAX \"lX\"\n\n/* Macros for printing `intptr_t' and `uintptr_t'.  */\n#define PRIdPTR \"d\"\n#define PRIiPTR \"i\"\n#define PRIoPTR \"o\"\n#define PRIuPTR \"u\"\n#define PRIxPTR \"x\"\n#define PRIXPTR \"X\"\n\n#endif /* _DPUSYSCORE_INTTYPES_H_ */"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/iso646.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ISO646_H_\n#define _DPUSYSCORE_ISO646_H_\n\n/**\n * @file iso646.h\n * @brief Alternative spellings for operators not supported by the ISO646 standard character set.\n */\n\n/**\n * @def and\n * @brief Logical AND.\n */\n#define and &&\n/**\n * @def and_eq\n * @brief Bitwise AND accumulation.\n */\n#define and_eq &=\n/**\n * @def bitand\n * @brief Bitwise AND.\n */\n#define bitand &\n/**\n * @def bitor\n * @brief Bitwise OR.\n */\n#define bitor |\n/**\n * @def compl\n * @brief Bitwise NOT.\n */\n#define compl ~\n/**\n * @def not\n * @brief Logical NOT.\n */\n#define not !\n/**\n * @def not_eq\n * @brief Difference.\n */\n#define not_eq !=\n/**\n * @def or\n * @brief Logical OR.\n */\n#define or ||\n/**\n * @def or_eq\n * @brief Bitwise OR accumulation.\n */\n#define or_eq |=\n/**\n * @def xor\n * @brief Bitwise XOR.\n */\n#define xor ^\n/**\n * @def xor_eq\n * @brief Bitwise XOR accumulation.\n */\n#define xor_eq ^=\n\n#endif /* _DPUSYSCORE_ISO646_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/limits.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_LIMITS_H_\n#define _DPUSYSCORE_LIMITS_H_\n\n#define SCHAR_MAX (0x0000007f)\n#define SHRT_MAX (0x00007fff)\n#define INT_MAX (0x7fffffff)\n#define LONG_MAX (0x7fffffffffffffffl)\n#define LLONG_MAX (0x7fffffffffffffffl)\n\n#define SCHAR_MIN (-SCHAR_MAX - 1)\n#define SHRT_MIN (-SHRT_MAX - 1)\n#define INT_MIN (-INT_MAX - 1)\n#define LONG_MIN (-LONG_MAX - 1)\n#define LLONG_MIN (-LLONG_MAX - 1)\n\n#define UCHAR_MAX (SCHAR_MAX * 2 + 1)\n#define USHRT_MAX (SHRT_MAX * 2 + 1)\n#define UINT_MAX (INT_MAX * 2U + 1U)\n#define ULONG_MAX (LONG_MAX * 2UL + 1UL)\n#define ULLONG_MAX (LLONG_MAX * 2UL + 1UL)\n\n#ifdef __CHAR_UNSIGNED__ /* -funsigned-char */\n#define CHAR_MIN 0\n#define CHAR_MAX UCHAR_MAX\n#else\n#define CHAR_MIN SCHAR_MIN\n#define CHAR_MAX SCHAR_MAX\n#endif\n\n/* The maximum number of bytes in a multi-byte character.  */\n#define MB_LEN_MAX 16\n\n/* Limits of integral types */\n\n/**\n * @def CHAR_BIT\n * @hideinitializer\n * @brief The number of bits in a char type.\n */\n#define CHAR_BIT (8)\n\n/**\n * @def WORD_BIT\n * @hideinitializer\n * @brief The number of bits in a word type.\n */\n#define WORD_BIT (32)\n\n/**\n * @def LONG_BIT\n * @hideinitializer\n * @brief The number of bits in a pseudo-long type.\n */\n#define LONG_BIT (32)\n\n/* Minimum of signed integral types */\n\n/**\n * @def INT8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MIN (-0x7f - 1)\n\n/**\n * @def INT16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MIN (-0x7fff - 1)\n\n/**\n * @def INT32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MIN (-0x7fffffff - 1)\n\n/**\n * @def INT64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types */\n\n/**\n * @def INT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MAX (0x7f)\n/**\n * @def INT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MAX (0x7fff)\n/**\n * @def INT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MAX (0x7fffffff)\n/**\n * @def INT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types */\n\n/**\n * @def UINT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint8_t</code>.\n */\n#define UINT8_MAX (0xff)\n/**\n * @def UINT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint16_t</code>.\n */\n#define UINT16_MAX (0xffff)\n/**\n * @def UINT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint32_t</code>.\n */\n#define UINT32_MAX (0xffffffff)\n/**\n * @def UINT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint64_t</code>.\n */\n#define UINT64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MIN (-0x7f - 1)\n/**\n * @def INT_LEAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MIN (-0x7fff - 1)\n/**\n * @def INT_LEAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_LEAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MAX (0x7f)\n/**\n * @def INT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MAX (0x7fff)\n/**\n * @def INT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MAX (0x7fffffff)\n/**\n * @def INT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types having a minimum size */\n\n/**\n * @def UINT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least8_t</code>.\n */\n#define UINT_LEAST8_MAX (0xff)\n/**\n * @def UINT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least16_t</code>.\n */\n#define UINT_LEAST16_MAX (0xffff)\n/**\n * @def UINT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least32_t</code>.\n */\n#define UINT_LEAST32_MAX (0xffffffff)\n/**\n * @def UINT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least64_t</code>.\n */\n#define UINT_LEAST64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MIN (-0x7f - 1)\n/**\n * @def INT_FAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MAX (0x7f)\n/**\n * @def INT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MAX (0x7fffffff)\n/**\n * @def INT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MAX (0x7fffffff)\n/**\n * @def INT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of fast unsigned integral types having a minimum size */\n\n/**\n * @def UINT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast8_t</code>.\n */\n#define UINT_FAST8_MAX (0xff)\n/**\n * @def UINT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast16_t</code>.\n */\n#define UINT_FAST16_MAX (0xffffffffU)\n/**\n * @def UINT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast32_t</code>.\n */\n#define UINT_FAST32_MAX (0xffffffffU)\n/**\n * @def UINT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast64_t</code>.\n */\n#define UINT_FAST64_MAX (0xffffffffffffffffUL)\n\n/* Limits for integral types holding void* pointers */\n\n/**\n * @def INTPTR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MIN (-0x7fffffff - 1)\n/**\n * @def INTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MAX (0x7fffffff)\n/**\n * @def UINTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintptr_t</code>.\n */\n#define UINTPTR_MAX (0xffffffffU)\n\n/* Limits of greatest-width integer types */\n\n/**\n * @def INTMAX_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MIN (-0x7fffffffffffffffLL - 1)\n/**\n * @def INTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MAX (0x7fffffffffffffffLL)\n/**\n * @def UINTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintmax_t</code>.\n */\n#define UINTMAX_MAX (0xffffffffffffffffULL)\n\n/* Limits of others integer types */\n\n/**\n * @def PTRDIFF_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MIN (-0x7fffffff - 1)\n/**\n * @def PTRDIFF_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MAX (0x7fffffff)\n\n/**\n * @def SIZE_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>size_t</code>.\n * @see size_t\n */\n#define SIZE_MAX (0xffffffffU)\n\n/**\n * @def WCHAR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MIN (-0x7fffffff - 1)\n/**\n * @def WCHAR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MAX (0x7fffffff)\n\n/**\n * @def WINT_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MIN (0u)\n/**\n * @def WINT_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MAX (0xffffffffu)\n\n/* Macros for integer constant expressions */\n\n/* Signed */\n\n/**\n * @def INT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least8_t</code>\n */\n#define INT8_C(value) value\n/**\n * @def INT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least16_t</code>\n */\n#define INT16_C(value) value\n/**\n * @def INT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least32_t</code>\n */\n#define INT32_C(value) value\n/**\n * @def INT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least64_t</code>\n */\n#define INT64_C(value) value##LL\n\n/* Unsigned */\n\n/**\n * @def UINT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least8_t</code>\n */\n#define UINT8_C(value) value##U\n/**\n * @def UINT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least16_t</code>\n */\n#define UINT16_C(value) value##U\n/**\n * @def UINT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least32_t</code>\n */\n#define UINT32_C(value) value##U\n/**\n * @def UINT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least64_t</code>\n */\n#define UINT64_C(value) value##ULL\n\n/* Maximum types */\n\n/**\n * @def INTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>intmax_t</code>\n */\n#define INTMAX_C(value) value##LL\n/**\n * @def UINTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uintmax_t</code>\n */\n#define UINTMAX_C(value) value##ULL\n\n#endif /* _DPUSYSCORE_LIMITS_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nvoid *\nmemchr(const void *area, int character, size_t size)\n{\n    const char *ptr = (const char *)area;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        if (ptr[each_byte] == character) {\n            return (void *)(ptr + each_byte);\n        }\n    }\n\n    return NULL;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nint\nmemcmp(const void *area1, const void *area2, size_t size)\n{\n    const unsigned char *ptr1 = (const unsigned char *)area1;\n    const unsigned char *ptr2 = (const unsigned char *)area2;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        int diff = ptr1[each_byte] - ptr2[each_byte];\n        if (diff != 0) {\n            return diff;\n        }\n    }\n\n    return 0;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\n__attribute__((used)) void *\n__memcpy_wram_4align(void *dest, const void *src, size_t len)\n{\n    uint32_t *dw = (uint32_t *)dest;\n    uint32_t *sw = (uint32_t *)src;\n\n    for (uint32_t i = 0; i < (len / sizeof(uint32_t)); ++i) {\n        dw[i] = sw[i];\n    }\n    return dest;\n}\n\nvoid *\nmemcpy(void *dest, const void *src, size_t len)\n{\n    uint8_t *d = (uint8_t *)dest;\n    const uint8_t *s = (const uint8_t *)src;\n    uint32_t *dw;\n    const uint32_t *sw;\n    uint8_t *head;\n    uint8_t *const tail = (uint8_t *)dest + len;\n    /* Set 'body' to the last word boundary */\n    uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);\n\n    if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n        /* Misaligned. no body, no tail. */\n        head = tail;\n    } else {\n        /* Aligned */\n        if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))\n            /* len is shorter than the first word boundary */\n            head = tail;\n        else\n            /* Set 'head' to the first word boundary */\n            head = (uint8_t *)(((uintptr_t)d + 3) & ~3);\n    }\n\n    /* Copy head */\n    uint32_t head_len = head - d;\n    if (head_len != 0) {\n        for (uint32_t i = 0; i < head_len; ++i)\n            d[i] = s[i];\n    }\n\n    /* Copy body */\n    dw = (uint32_t *)(d + head_len);\n    sw = (uint32_t *)(s + head_len);\n\n    uint32_t body_len = (body < dw) ? 0 : body - dw;\n    if (body_len != 0) {\n        __memcpy_wram_4align(dw, sw, body_len * sizeof(uint32_t));\n    }\n\n    /* Copy tail */\n    d = (uint8_t *)(dw + body_len);\n    s = (const uint8_t *)(sw + body_len);\n    uint32_t tail_len = tail - d;\n    if (tail_len != 0) {\n        for (uint32_t i = 0; i < tail_len; ++i)\n            d[i] = s[i];\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mw(__mram_ptr void *dest, const void *src, size_t len)\n{\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n\n    if (destOff != 0) {\n        size_t part = MIN(remaining, MRAM_CACHE_SIZE - destOff);\n        mram_read(dest, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache + destOff, src, part);\n        mram_write(destCache, dest, MRAM_CACHE_SIZE);\n        remaining -= part;\n        idx += part;\n    }\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_write(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            memcpy(destCache, src + idx, MRAM_CACHE_SIZE);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache, src + idx, remaining);\n        mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) void *\n__memcpy_wm(void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n    size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n\n    mram_read(src, srcCache, MRAM_CACHE_SIZE);\n    memcpy(dest, srcCache + srcOff, part);\n    remaining -= part;\n    idx += part;\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(dest + idx, srcCache, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n        memcpy(dest + idx, srcCache, remaining);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mm(__mram_ptr void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    if (srcOff == destOff) {\n        uint32_t idx = 0;\n\n        if (destOff != 0) {\n            size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, part);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            remaining -= part;\n            idx += part;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            mram_write(srcCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache, srcCache, remaining);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n        }\n    } else {\n        uint32_t srcIdx = 0;\n        uint32_t destIdx = 0;\n        size_t initLen = MIN(remaining, MRAM_CACHE_SIZE - MIN(destOff, srcOff));\n\n        if (initLen == remaining) {\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, remaining);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            return dest;\n        }\n\n        mram_read(src, srcCache, MRAM_CACHE_SIZE);\n        srcIdx += MRAM_CACHE_SIZE;\n\n        if (destOff != 0) {\n            mram_read(dest, destCache, DMA_ALIGNED(destOff));\n\n            if (destOff > srcOff) {\n                size_t part = MRAM_CACHE_SIZE - destOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n\n                srcOff += part;\n            } else {\n                size_t part = MRAM_CACHE_SIZE - srcOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx += MRAM_CACHE_SIZE;\n\n                size_t part2 = srcOff - destOff;\n                memcpy(destCache + destOff + part, srcCache, part2);\n\n                srcOff = part2;\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            destIdx += MRAM_CACHE_SIZE;\n            remaining -= MRAM_CACHE_SIZE - destOff;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n            mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx += MRAM_CACHE_SIZE;\n\n            size_t part2 = srcOff;\n            memcpy(destCache + part, srcCache, part2);\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            destIdx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + destIdx, destCache, MRAM_CACHE_SIZE);\n\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n\n            if (remaining > part) {\n                size_t part2 = remaining - part;\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + part, srcCache, part2);\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n        }\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memmove.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <string.h>\n#include <stdint.h>\n\nvoid *\nmemmove(void *dest, const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return memcpy(dest, src, len);\n    } else {\n        /* Need to copy from tail because there is overlap. */\n        char *d = (char *)dest + len;\n        const char *s = (const char *)src + len;\n        uint32_t *dw;\n        const uint32_t *sw;\n        char *head;\n        char *const tail = (char *)dest;\n        /* Set 'body' to the last word boundary */\n        uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3);\n\n        if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n            /* Misaligned. no body, no tail. */\n            head = tail;\n        } else {\n            /* Aligned */\n            if ((uintptr_t)tail > ((uintptr_t)d & ~3))\n                /* Shorter than the first word boundary */\n                head = tail;\n            else\n                /* Set 'head' to the first word boundary */\n                head = (char *)((uintptr_t)d & ~3);\n        }\n\n        /* Copy head */\n        uint32_t head_len = d - head;\n        for (int32_t i = head_len - 1; i >= 0; --i)\n            d[i - head_len] = s[i - head_len];\n\n        /* Copy body */\n        dw = (uint32_t *)(d - head_len);\n        sw = (uint32_t *)(s - head_len);\n\n        uint32_t body_len = (dw < body) ? 0 : dw - body;\n        for (int32_t i = body_len - 1; i >= 0; --i)\n            dw[i - body_len] = sw[i - body_len];\n\n        /* Copy tail */\n        d = (char *)(dw - body_len);\n        s = (const char *)(sw - body_len);\n\n        uint32_t tail_len = d - tail;\n        for (int32_t i = tail_len - 1; i >= 0; --i)\n            d[i - tail_len] = s[i - tail_len];\n\n        return dest;\n    }\n}\n\n__mram_ptr void *\n__memmove_mm(__mram_ptr void *dest, __mram_ptr const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return (__mram_ptr void *)memcpy(dest, src, len);\n    } else {\n        uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        void *srcCache = (void *)srcCache64;\n        void *destCache = (void *)destCache64;\n\n        __mram_ptr const void *srcIdx = src + len;\n        __mram_ptr void *dstIdx = dest + len;\n        uint32_t remaining = len;\n\n        uint32_t srcOff = ((uintptr_t)srcIdx) & DMA_OFF_MASK;\n        uint32_t dstOff = ((uintptr_t)dstIdx) & DMA_OFF_MASK;\n\n        if (srcOff == dstOff) {\n            size_t part = MIN(remaining, srcOff);\n            uint32_t off = srcOff - part;\n\n            if (dstOff != 0) {\n                srcIdx -= srcOff;\n                dstIdx -= dstOff;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, part);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= part;\n            }\n\n            srcIdx -= MRAM_CACHE_SIZE;\n            dstIdx -= MRAM_CACHE_SIZE;\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                mram_write(srcCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= MRAM_CACHE_SIZE;\n                srcIdx -= MRAM_CACHE_SIZE;\n                dstIdx -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                uint32_t off = MRAM_CACHE_SIZE - remaining;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, remaining);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        } else {\n            size_t initLen = MIN(remaining, MIN(dstOff, srcOff));\n\n            if (initLen == remaining) {\n                mram_read(dest, destCache, MRAM_CACHE_SIZE);\n                mram_read(src, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + dstOff - remaining, srcCache + srcOff - remaining, remaining);\n                mram_write(destCache, dest, MRAM_CACHE_SIZE);\n                return dest;\n            }\n\n            mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx -= MRAM_CACHE_SIZE;\n\n            if (dstOff != 0) {\n                size_t part = DMA_ALIGNED(dstOff);\n                mram_read(dstIdx, destCache + MRAM_CACHE_SIZE - part, part);\n\n                if (srcOff > dstOff) {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n                    memcpy(destCache, srcCache + srcOff - part, part);\n                    srcOff -= part;\n                } else {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                    memcpy(destCache + dstOff - part, srcCache, part);\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    srcIdx -= MRAM_CACHE_SIZE;\n\n                    size_t part2 = dstOff - part;\n                    memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n\n                    srcOff = MRAM_CACHE_SIZE - part2;\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n            }\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx -= MRAM_CACHE_SIZE;\n\n                size_t part2 = MRAM_CACHE_SIZE - part;\n                memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n\n                if (remaining > part) {\n                    size_t part2 = remaining - part;\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    memcpy(destCache + MRAM_CACHE_SIZE - remaining, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        }\n\n        return dest;\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memmram_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_MEMMRAM_UTILS_H_\n#define _DPUSYSCORE_MEMMRAM_UTILS_H_\n\n#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))\n#define ALIGN(x, a) ALIGN_MASK((x), (a)-1)\n#define DMA_ALIGNMENT 8\n#define DMA_OFF_MASK (DMA_ALIGNMENT - 1)\n#define DMA_ALIGNED(x) ALIGN(x, DMA_ALIGNMENT)\n\n#define MIN(a, b) ((a) < (b) ? (a) : (b))\n\n#define MRAM_CACHE_SIZE 8\n\n#endif /* _DPUSYSCORE_MEMMRAM_UTILS_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/memset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\nstatic void *\n__memset_wram_1align(void *dest, int c, size_t len)\n{\n    uint8_t *dest8 = (uint8_t *)(dest);\n    for (uint32_t i = 0; i < (len); ++i) {\n        dest8[i] = (c);\n    }\n    return dest;\n}\n\ntypedef uint32_t memset_wram_t;\n/* Requisite:\n *  - dest: align on 4 bytes\n *  - len: mutiple of 4 bytes\n */\nvoid *__attribute__((used)) __memset_wram_4align(void *dest, int c, size_t len)\n{\n    uint32_t cccc;\n    memset_wram_t *dest32 = (memset_wram_t *)dest;\n\n    c &= 0xff; /* Clear upper bits before ORing below */\n    cccc = c | (c << 8) | (c << 16) | (c << 24);\n\n    for (uint32_t i = 0; i < len / sizeof(memset_wram_t); ++i) {\n        dest32[i] = cccc;\n    }\n\n    return dest;\n}\n\nvoid *\nmemset(void *dest, int c, size_t len)\n{\n    const uint32_t align = sizeof(memset_wram_t);\n    const uint32_t align_off_mask = (align - 1);\n    uint32_t align_offset = ((uintptr_t)dest) & align_off_mask;\n    uint8_t *d = (uint8_t *)dest;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = align - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        __memset_wram_1align(d, c, head_len);\n\n        len -= head_len;\n        d += head_len;\n    }\n\n    /* memset body */\n    if (len >= align) {\n        size_t body_len = len & (~align_off_mask);\n\n        __memset_wram_4align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        __memset_wram_1align(d, c, len);\n    }\n\n    return dest;\n}\n\n#define MEMSET_MRAM_CACHE_SIZE (8)\n/* Requisite:\n *  - dest: align on 8 bytes\n *  - len: mutiple of 8 bytes\n */\n__attribute__((used)) __mram_ptr void *\n__memset_mram_8align(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n\n    __memset_wram_4align(cache, c, MEMSET_MRAM_CACHE_SIZE);\n\n    for (uint32_t idx = 0; idx < len; idx += MEMSET_MRAM_CACHE_SIZE) {\n        mram_write(cache, dest + idx, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memset_mram(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n    __mram_ptr uint8_t *d = (__mram_ptr uint8_t *)((uintptr_t)dest & (~DMA_OFF_MASK));\n    uint32_t align_offset = ((uintptr_t)dest) & DMA_OFF_MASK;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = MEMSET_MRAM_CACHE_SIZE - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache + align_offset, c, head_len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n\n        len -= head_len;\n        d += MEMSET_MRAM_CACHE_SIZE;\n    }\n\n    /* memset body */\n    if (len >= MRAM_CACHE_SIZE) {\n        size_t body_len = len & (~(MEMSET_MRAM_CACHE_SIZE - 1));\n\n        __memset_mram_8align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache, c, len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdalign.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDALIGN_H_\n#define _DPUSYSCORE_STDALIGN_H_\n\n/**\n * @file stdalign.h\n * @brief Defines align macros.\n */\n\n/**\n * @def alignas\n * @brief _Alignas specifier.\n */\n#define alignas _Alignas\n\n/**\n * @def alignof\n * @brief _Alignof operator.\n */\n#define alignof _Alignof\n\n/**\n * @def __alignas_is_defined\n * @brief Whether the alignas macro is defined.\n */\n#define __alignas_is_defined 1\n\n/**\n * @def __alignof_is_defined\n * @brief Whether the alignof macro is defined.\n */\n#define __alignof_is_defined 1\n\n#endif /* _DPUSYSCORE_STDALIGN_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdarg.h",
    "content": "/*===---- stdarg.h - Variable argument handling ----------------------------===\n *\n * Copyright (c) 2008 Eli Friedman\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __STDARG_H\n#define __STDARG_H\n\n#ifndef _VA_LIST\ntypedef __builtin_va_list va_list;\n#define _VA_LIST\n#endif\n#define va_start(ap, param) __builtin_va_start(ap, param)\n#define va_end(ap) __builtin_va_end(ap)\n#define va_arg(ap, type) __builtin_va_arg(ap, type)\n\n/* GCC always defines __va_copy, but does not define va_copy unless in c99 mode\n * or -ansi is not specified, since it was not part of C90.\n */\n#define __va_copy(d, s) __builtin_va_copy(d, s)\n\n#if __STDC_VERSION__ >= 199901L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__)\n#define va_copy(dest, src) __builtin_va_copy(dest, src)\n#endif\n\n#ifndef __GNUC_VA_LIST\n#define __GNUC_VA_LIST 1\ntypedef __builtin_va_list __gnuc_va_list;\n#endif\n\n#endif /* __STDARG_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdbool.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDBOOL_H_\n#define _DPUSYSCORE_STDBOOL_H_\n\n/**\n * @file stdbool.h\n * @brief Defines the boolean type.\n */\n\n/**\n * @def __bool_true_false_are_defined\n * @brief Whether the boolean type and values are defined.\n */\n#define __bool_true_false_are_defined 1\n\n/**\n * @def bool\n * @brief The boolean type.\n */\n#define bool _Bool\n\n/**\n * @def true\n * @brief The <code>true</code> constant, represented by <code>1</code>\n */\n#define true 1\n/**\n * @def false\n * @brief The <code>false</code> constant, represented by <code>0</code>\n */\n#define false 0\n\n#endif /* _DPUSYSCORE_STDBOOL_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stddef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDDEF_H_\n#define _DPUSYSCORE_STDDEF_H_\n\n/**\n * @file stddef.h\n * @brief Defines some standard types.\n */\n\n/**\n * @brief The type for the result of subtracting two pointers.\n */\ntypedef int ptrdiff_t;\n\n/**\n * @brief The type for the result of the <code>sizeof</code> operator.\n *\n * @internal No memory or object in the DPU can be more than megabytes of data.\n *           As a consequence, we can restrict the sizes to 32 bits, which is\n *           already a lot.\n */\ntypedef unsigned int size_t;\n\n/**\n * @brief Value whose alignment requirement is at least as strict (as large) as that of every scalar type.\n */\ntypedef unsigned long int max_align_t;\n\n/**\n * @brief The type for wide-character codes.\n */\ntypedef unsigned int wchar_t;\n\n/**\n * @def NULL\n * @brief The null pointer constant.\n */\n#define NULL ((void *)0)\n\n/**\n * @def offsetof\n * @hideinitializer\n * @brief Offset in bytes to the structure member, from the beginning of its structure.\n *\n * @param st the structure\n * @param m the member name\n *\n * @internal Raw version of offsetof, should be enough in our context, with all the underlying risks.\n */\n#define offsetof(st, m) ((size_t)(&((st *)0)->m))\n\n#endif /* _DPUSYSCORE_STDDEF_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdint.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDINT_H_\n#define _DPUSYSCORE_STDINT_H_\n\n/**\n * @file stdint.h\n * @brief Provides abstraction over machine types.\n */\n\n/* Exact integer types */\n\n/* Signed */\n\n/**\n * @brief A signed 8-bit value.\n */\ntypedef signed char int8_t;\n/**\n * @brief A signed 16-bit value.\n */\ntypedef short int int16_t;\n/**\n * @brief A signed 32-bit value.\n */\ntypedef int int32_t;\n/**\n * @brief A signed 64-bit value.\n */\ntypedef long long int int64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned 8-bit value.\n */\ntypedef unsigned char uint8_t;\n/**\n * @brief An unsigned 16-bit value.\n */\ntypedef unsigned short int uint16_t;\n/**\n * @brief An unsigned 32-bit value.\n */\ntypedef unsigned int uint32_t;\n\n/**\n * @brief An unsigned 64-bit value.\n */\ntypedef unsigned long int uint64_t;\n\n/* Small types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits.\n */\ntypedef signed char int_least8_t;\n/**\n * @brief A signed value on at least 16 bits.\n */\ntypedef short int int_least16_t;\n/**\n * @brief A signed value on at least 32 bits.\n */\ntypedef int int_least32_t;\n/**\n * @brief A signed value on at least 64 bits.\n */\ntypedef long int int_least64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits.\n */\ntypedef unsigned char uint_least8_t;\n/**\n * @brief An unsigned value on at least 16 bits.\n */\ntypedef unsigned short int uint_least16_t;\n/**\n * @brief An unsigned value on at least 32 bits.\n */\ntypedef unsigned int uint_least32_t;\n/**\n * @brief An unsigned value on at least 64 bits.\n */\ntypedef unsigned long int uint_least64_t;\n\n/* Fast types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits, optimized for that length.\n */\ntypedef signed char int_fast8_t;\n/**\n * @brief A signed value on at least 16 bits, optimized for that length.\n */\ntypedef int int_fast16_t;\n/**\n * @brief A signed value on at least 32 bits, optimized for that length.\n */\ntypedef int int_fast32_t;\n/**\n * @brief A signed value on at least 64 bits, optimized for that length.\n */\ntypedef long int int_fast64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits, optimized for that length.\n */\ntypedef unsigned char uint_fast8_t;\n/**\n * @brief An unsigned value on at least 16 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast16_t;\n/**\n * @brief An unsigned value on at least 32 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast32_t;\n/**\n * @brief An unsigned value on at least 64 bits, optimized for that length.\n */\ntypedef unsigned long int uint_fast64_t;\n\n/* Types for void* pointers */\n\n/**\n * @brief A signed value which can contain a pointer value.\n */\ntypedef int intptr_t;\n/**\n * @brief An unsigned value which can contain a pointer value.\n */\ntypedef unsigned int uintptr_t;\n\n/* Greatest-width integer types */\n\n/**\n * @brief A signed value which can contain all signed values.\n */\ntypedef long long int intmax_t;\n/**\n * @brief An unsigned value which can contain all unsigned values.\n */\ntypedef unsigned long long int uintmax_t;\n\n#include <limits.h>\n\n#endif /* _DPUSYSCORE_STDINT_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdio.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdarg.h>\n#include <string.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n#include <mram.h>\n#include <dpuruntime.h>\n\n#define DEFAULT_STDOUT_BUFFER_SIZE (1 << 20)\n\nunsigned char __weak __mram_noinit __stdout_buffer[DEFAULT_STDOUT_BUFFER_SIZE];\nunsigned int __weak __stdout_buffer_size = DEFAULT_STDOUT_BUFFER_SIZE;\n\n/* __lower_data: needed to make sure that the structure address will be less that a signed12\n *               (sd endian:e ra off:s12 imm:s16 used in bootstrap).\n *\n * __dma_aligned: needed to make sure that the structure address will be aligned on 8 bytes (for sd in bootstrap as well).\n *\n * This structure is initialize at zero in the bootsrap\n */\n__lower_data(__STR(__STDOUT_BUFFER_STATE)) __dma_aligned struct {\n    uint32_t wp;\n    uint32_t has_wrapped;\n} __STDOUT_BUFFER_STATE;\n\nstatic uint32_t __stdout_buffer_write_pointer_initial;\nstatic uint32_t __stdout_nr_of_wrapping;\n\n#define STDOUT_CACHE_BUFFER_SIZE 8\n_Static_assert((STDOUT_CACHE_BUFFER_SIZE >= 8) && (STDOUT_CACHE_BUFFER_SIZE <= 2048) && (STDOUT_CACHE_BUFFER_SIZE % 8 == 0),\n    \"STDOUT_CACHE_BUFFER_SIZE needs to be a multiple of 8 in ]0; 2048]\");\n\nstatic char __stdout_cache_buffer[STDOUT_CACHE_BUFFER_SIZE] __dma_aligned;\nstatic unsigned int __stdout_cache_write_index;\n\nATOMIC_BIT_INIT(__stdout_buffer_lock);\n\n__attribute__((noinline)) static void\n__transfer_cache_to_mram()\n{\n    __mram_ptr void *offset_in_mram = (__mram_ptr void *)(__STDOUT_BUFFER_STATE.wp + (uintptr_t)__stdout_buffer);\n\n    __STDOUT_BUFFER_STATE.wp += STDOUT_CACHE_BUFFER_SIZE;\n    if (__STDOUT_BUFFER_STATE.wp >= __stdout_buffer_size) {\n        __STDOUT_BUFFER_STATE.wp = 0;\n        __STDOUT_BUFFER_STATE.has_wrapped = true;\n        __stdout_nr_of_wrapping++;\n    }\n\n    mram_write(__stdout_cache_buffer, offset_in_mram, STDOUT_CACHE_BUFFER_SIZE);\n}\n\n// Generic template that will be used everywhere: cache a byte and flush to MRAM\n// when the cache is full.\n__attribute__((noinline)) static void\n__write_byte_and_flush_if_needed(uint8_t byte)\n{\n    __stdout_cache_buffer[__stdout_cache_write_index++] = byte;\n    if (__stdout_cache_write_index == STDOUT_CACHE_BUFFER_SIZE) {\n        __transfer_cache_to_mram();\n        __stdout_cache_write_index = 0;\n    }\n}\n\n__attribute__((noinline)) static void\n__finalized_print_sequence()\n{\n    memset(__stdout_cache_buffer + __stdout_cache_write_index, 0, STDOUT_CACHE_BUFFER_SIZE - __stdout_cache_write_index);\n    __transfer_cache_to_mram();\n\n    if (__stdout_nr_of_wrapping > 1\n        || (__stdout_nr_of_wrapping == 1 && __STDOUT_BUFFER_STATE.wp > __stdout_buffer_write_pointer_initial))\n        __asm__(\"fault \" __STR(__FAULT_PRINTF_OVERFLOW__)); // need to throw fault because we will not be able to print the buffer\n}\n\n__attribute__((noinline)) static void\n__open_print_sequence()\n{\n    ATOMIC_BIT_ACQUIRE(__stdout_buffer_lock);\n    __stdout_cache_write_index = 0;\n    __stdout_nr_of_wrapping = 0;\n    __stdout_buffer_write_pointer_initial = __STDOUT_BUFFER_STATE.wp;\n}\n\n/* Nothing else that the release instruction should be in this function in order to make sure that the print routine in complete\n * at this point*/\n__attribute__((noinline)) static void\n__close_print_sequence()\n{\n    ATOMIC_BIT_RELEASE(__stdout_buffer_lock);\n}\n\nvoid\nprintf(const char *restrict format, ...)\n{\n    bool insert_string_arg = true;\n    bool insert_string_arg_end_character = false;\n    char *current_format_char_ptr = (char *)format;\n\n    __open_print_sequence();\n\n    va_list args;\n    va_start(args, format);\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_format_process;\n\n            __write_byte_and_flush_if_needed('%');\n\n            while (*current_format_char_ptr != '\\0') {\n                if (*current_format_char_ptr == 'l') {\n                    __write_byte_and_flush_if_needed(*current_format_char_ptr);\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if ((*current_format_char_ptr == 'L') || (*current_format_char_ptr == 'z')) {\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if (*current_format_char_ptr == 'i') {\n                    __write_byte_and_flush_if_needed('d');\n                    break;\n                }\n                __write_byte_and_flush_if_needed(*current_format_char_ptr);\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            insert_string_arg = true;\n\n        } else {\n        standard_character_format_process:\n            if (insert_string_arg) {\n                __write_byte_and_flush_if_needed('%');\n                __write_byte_and_flush_if_needed('s');\n                insert_string_arg = false;\n            }\n        }\n    }\n\n    __write_byte_and_flush_if_needed('\\0');\n    current_format_char_ptr = (char *)format;\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_process;\n\n            if (insert_string_arg_end_character) {\n                insert_string_arg_end_character = false;\n                __write_byte_and_flush_if_needed('\\0');\n            }\n\n            bool arg_is_64_bits = false;\n\n            while (*current_format_char_ptr != '\\0') {\n                if ((*current_format_char_ptr == 'l') || (*current_format_char_ptr == 'L')) {\n                    arg_is_64_bits = true;\n                    current_format_char_ptr++;\n                    continue;\n                } else if (*current_format_char_ptr == 'z') {\n                    current_format_char_ptr++;\n                    continue;\n                }\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            switch (*current_format_char_ptr) {\n                case 's': {\n                    char *arg = (char *)va_arg(args, int);\n                    while (*arg != '\\0') {\n                        __write_byte_and_flush_if_needed(*arg);\n                        arg++;\n                    }\n                    __write_byte_and_flush_if_needed('\\0');\n                    break;\n                }\n                case 'c': {\n                    char arg_as_char = (char)va_arg(args, int);\n                    __write_byte_and_flush_if_needed(arg_as_char);\n                    break;\n                }\n                case 'f':\n                case 'e':\n                case 'E':\n                case 'g':\n                case 'G': {\n                    __asm__ volatile(\"nop\");\n                    double val = va_arg(args, double);\n                    char *arg = (char *)&val;\n                    for (int i = 0; i < 8; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                    break;\n                }\n                default: {\n                    unsigned int arg_size_in_bytes;\n                    long val;\n\n                    if (arg_is_64_bits) {\n                        val = va_arg(args, long);\n                        arg_size_in_bytes = 8;\n                    } else {\n                        val = (long)va_arg(args, int);\n                        arg_size_in_bytes = 4;\n                    }\n\n                    char *arg = (char *)&val;\n                    for (unsigned int i = 0; i < arg_size_in_bytes; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                }\n            }\n        } else {\n        standard_character_process:\n            __write_byte_and_flush_if_needed(*current_format_char_ptr);\n            insert_string_arg_end_character = true;\n        }\n    }\n\n    if (insert_string_arg_end_character) {\n        __write_byte_and_flush_if_needed('\\0');\n    }\n\n    va_end(args);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputs(const char *str)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('s');\n    __write_byte_and_flush_if_needed('\\0');\n\n    for (char *current_char_ptr = (char *)str; *current_char_ptr != '\\0'; current_char_ptr++) {\n        __write_byte_and_flush_if_needed(*current_char_ptr);\n    }\n\n    __write_byte_and_flush_if_needed('\\n');\n    __write_byte_and_flush_if_needed('\\0');\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputchar(int c)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('c');\n    __write_byte_and_flush_if_needed('\\0');\n\n    char arg_as_char = (char)c;\n    __write_byte_and_flush_if_needed(arg_as_char);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdio.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDIO_H_\n#define _DPUSYSCORE_STDIO_H_\n\n#include <attributes.h>\n#include <stddef.h>\n\n/**\n * @file stdio.h\n * @brief Standard input/output library functions.\n */\n\n/**\n * @def STDOUT_BUFFER_INIT\n * @hideinitializer\n * @brief Declares the stdout buffer. Should be used as when declaring a global variable.\n * @param size the size of the stdout buffer. Must be a multiple of 8, and greater than 0.\n */\n#define STDOUT_BUFFER_INIT(size)                                                                                                 \\\n    _Static_assert((size >= 8) && (((size)&7) == 0), \"stdout buffer size must be a multiple of 8 and > 0\");                      \\\n    unsigned char __dma_aligned __mram_noinit __stdout_buffer[(size)];                                                           \\\n    const unsigned int __stdout_buffer_size = (size);\n\n/**\n * @fn printf\n * @brief Writes the formatted data in the stdout buffer.\n *\n * This function has a prototype close to the one of the standard printf function.\n * However, the format string comply to the java.util.Formatter format, which is\n * similar to the printf format, but not quit exactly the same. Date formatter may\n * produce interpreted results, but they will probably be incorrect. Every format\n * specifier should reference one and only one of the variadic argument (eg. \"%n\"\n * is not supported).\n *\n * There is no compile-time check to verify that the format is correct: any other\n * character in the format string will not be interpreted.\n *\n * @param format how the logged data should be formatted\n * @param ... the different data to be printed\n */\nvoid __attribute__((format(printf, 1, 2))) printf(const char *restrict format, ...);\n\n/**\n * @fn puts\n * @brief Writes the string in the stdout buffer. A newline character is appended to the output.\n * @param str the null-terminated string to be written\n */\nvoid\nputs(const char *str);\n\n/**\n * @fn putchar\n * @brief Writes the character in the stdout buffer.\n * @param c the character to be written\n */\nvoid\nputchar(int c);\n\n#endif /* _DPUSYSCORE_STDIO_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdlib.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STDLIB_H\n#define DPUSYSCORE_STDLIB_H\n\n/**\n * @file stdlib.h\n * @brief Elementary standard C functions: calls the system function halt.\n */\n\n#include <stddef.h>\n#include <attributes.h>\n\n/**\n * @def EXIT_FAILURE\n * @hideinitializer\n * @brief Unsuccessful termination for exit().\n */\n#define EXIT_FAILURE 1\n\n/**\n * @def EXIT_SUCCESS\n * @hideinitializer\n * @brief Successful termination for exit().\n */\n#define EXIT_SUCCESS 0\n\n/**\n * @brief Aborts the DPU execution triggering a processor fault.\n */\n__NO_RETURN void\nabort(void);\n\n/**\n * @brief Terminates the invoking tasklet, returning the specified status.\n */\n__NO_RETURN void\nexit(int status);\n\n/**\n * @brief Get an environment variable, or NULL. In the DPU case, always NULL.\n */\nstatic inline char *\ngetenv(__attribute__((unused)) const char *name)\n{\n    return NULL;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline int\nabs(int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long int\nlabs(long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long long int\nllabs(long long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\ntypedef struct {\n    int quot;\n    int rem;\n} div_t;\n\ntypedef struct {\n    long int quot;\n    long int rem;\n} ldiv_t;\n\ntypedef struct {\n    long long int quot;\n    long long int rem;\n} lldiv_t;\n\nstatic inline div_t\ndiv(int numer, int denom)\n{\n    div_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline ldiv_t\nldiv(long int numer, long int denom)\n{\n    ldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline lldiv_t\nlldiv(long long int numer, long long int denom)\n{\n    lldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/**\n * @brief Converts a string to an integer\n *\n * Function converts the initial part of the string in nptr to an integer value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atoi()\n * returns INT_MIN. If an overflow occurs, atoi() returns INT_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nint\natoi(const char *nptr);\n\n/**\n * @brief Converts a string to a long integer (64 bits)\n *\n * Function converts the initial part of the string in nptr to a long value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atol()\n * returns LONG_MIN. If an overflow occurs, atol() returns LONG_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nlong\natol(const char *nptr);\n\n///**\n// * @brief Converts a string to a long integer (64 bits) according to the given base\n// * between 2 and 36 inclusive, or be the special value 0\n// *\n// * TODO : If the given base is oustide of the range [2...36], then errno is set to EINVAL\n// *\n// * Function converts the initial part of the string in nptr to a long value. The string may begin\n// * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n// *\n// * If base is zero or 16, the string may then include a \"0x\" prefix, and the number will be read\n// * in base 16; otherwise, a zero base is taken as 10 (decimal) unless the next character is '0',\n// * in which case it is taken as 8 (octal).\n// *\n// * Conversion stops at the first character not representing a digit in the given base.\n// * Accepted digits are : in bases above 10, the letter 'A' in either uppercase or lowercase\n// * represents 10, 'B' represents 11, and so forth, with 'Z' representing 35.\n// *\n// * If endptr is not NULL, strtol() stores the address of the first invalid character in *endptr.\n// * If there were no digits at all, strtol() stores the original value of nptr in *endptr (and\n// * returns 0). In particular, if *nptr is not '\\0' but **endptr is '\\0' on return, the entire\n// * string is valid.\n// *\n// * If an underflow occurs, atol() returns LONG_MIN. If an overflow occurs, atol()\n// * returns LONG_MAX. TODO!!! In both cases errno is set to ERANGE.\n// *\n// * @param nptr string that contains an integer in a string format\n// * @param endptr\n// * @param base\n//\n// * @return the result of conversion unless the value would overflow or underflow.\n//*/\n// long int strtol(const char *nptr, char **endptr, int base);\n// TODO : strtol() doesn't work : has to be written in assembly\n\n#endif /* DPUSYSCORE_STDLIB_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stdnoreturn.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDNORETURN_H_\n#define _DPUSYSCORE_STDNORETURN_H_\n\n/**\n * @file stdnoreturn.h\n * @brief Defines the noreturn macro.\n */\n\n/**\n * @def noreturn\n * @brief _Noreturn attribute.\n */\n#define noreturn _Noreturn\n\n#endif /* _DPUSYSCORE_STDNORETURN_H_ */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stpcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nchar *\nstpcpy(char *destination, const char *source)\n{\n    char c = *source;\n\n    while (c != '\\0') {\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    *destination = c;\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/stpncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstpncpy(char *destination, const char *source, size_t size)\n{\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            char *null_char_ptr = destination;\n\n            for (; each_byte < size; ++each_byte) {\n                *destination = '\\0';\n                destination++;\n            }\n\n            return null_char_ptr;\n        }\n\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strcat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcat(char *destination, const char *source)\n{\n    size_t length = strlen(destination);\n    unsigned int i;\n\n    for (i = 0; source[i] != '\\0'; i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrchr(const char *string, int character)\n{\n    char *str = (char *)string;\n    unsigned char c = *str;\n\n    while (1) {\n        if (c == character) {\n            return str;\n        }\n        if (c == '\\0') {\n            return NULL;\n        }\n\n        str++;\n        c = *str;\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrcmp(const char *string1, const char *string2)\n{\n    unsigned char c1 = *string1;\n    unsigned char c2 = *string2;\n\n    while (c1 != '\\0') {\n        if (c1 - c2 != 0) {\n            return c1 - c2;\n        }\n\n        string1++;\n        string2++;\n        c1 = *string1;\n        c2 = *string2;\n    }\n\n    return c1 - c2;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcpy(char *destination, const char *source)\n{\n    char *ptr = destination;\n    char c = *source;\n\n    while (c != '\\0') {\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    *ptr = c;\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strcspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrcspn(const char *string, const char *reject)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        for (unsigned int reject_index = 0; reject[reject_index] != '\\0'; ++reject_index) {\n            if (reject[reject_index] == c) {\n                return prefix_length;\n            }\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strdup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrdup(const char *string)\n{\n    size_t length = strlen(string) + 1; // we get the length of the string for memory allocation\n\n    char *result = buddy_alloc(length); // we allocate length+1 bytes for the duplicate\n\n    if (result != NULL) {\n        memcpy(result, string, length); // we copy length bytes from string to the duplicate\n    }\n\n    return result;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strerror.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <defs.h>\n#include \"errno.h\"\n\n// http://www.delorie.com/gnu/docs/glibc/libc_17.html\n\n// static char* strerror_errors[] = { \"Success\",\n//\"E2BIG\", \"EACCES\", \"EADDRINUSE\", \"EADDRNOTAVAIL\", \"EAFNOSUPPORT\", \"EAGAIN\", \"EALREADY\", \"EBADF\",\n//\"EBADMSG\", \"EBUSY\", \"ECANCELED\", \"ECHILD\", \"ECONNABORTED\", \"ECONNREFUSED\", \"ECONNRESET\", \"EDEADLK\",\n//\"EDESTADDRREQ\", \"EDOM\", \"EDQUOT\", \"EEXIST\", \"EFAULT\", \"EFBIG\", \"EHOSTUNREACH\", \"EIDRM\",\n//\"EILSEQ\", \"EINPROGRESS\", \"EINTR\", \"EINVAL\", \"EIO\", \"EISCONN\", \"EISDIR\", \"ELOOP\",\n//\"EMFILE\", \"EMLINK\", \"EMSGSIZE\", \"EMULTIHOP\", \"ENAMETOOLONG\", \"ENETDOWN\", \"ENETRESET\", \"ENETUNREACH\",\n//\"ENFILE\", \"ENOBUFS\", \"ENODATA\", \"ENODEV\", \"ENOENT\", \"ENOEXEC\", \"ENOLCK\", \"ENOLINK\",\n//\"ENOMEM\", \"ENOMSG\", \"ENOPROTOOPT\", \"ENOSPC\", \"ENOSR\", \"ENOSTR\", \"ENOSYS\", \"ENOTCONN\",\n//\"ENOTDIR\", \"ENOTEMPTY\", \"ENOTRECOVERABLE\", \"ENOTSOCK\", \"ENOTSUP\", \"ENOTTY\", \"ENXIO\", \"EOPNOTSUPP\",\n//\"EOVERFLOW\", \"EOWNERDEAD\", \"EPERM\", \"EPIPE\", \"EPROTO\", \"EPROTONOSUPPORT\", \"EPROTOTYPE\", \"ERANGE\",\n//\"EROFS\", \"ESPIPE\", \"ESRCH\", \"ESTALE\", \"ETIME\", \"ETIMEDOUT\", \"ETXTBSY\", \"EWOULDBLOCK\",\n//\"EXDEV\"\n//};\n\n// 81 errors in total including 2 not supported ones.\n\nconst static char *strerror_errors_complete[] = { \"Success\",\n    \"Argument list too long\",\n    \"Permission denied\",\n    \"Address in use\",\n    \"Address not available\",\n    \"Address family not supported\",\n    \"Resource unavailable, try again\",\n    \"Connection already in progress\",\n    \"Bad file descriptor\",\n\n    \"Bad message\",\n    \"Device or resource busy\",\n    \"Operation canceled\",\n    \"No child processes\",\n    \"Connection aborted\",\n    \"Connection refused\",\n    \"Connection reset\",\n    \"Resource deadlock would occur\",\n\n    \"Destination address required\",\n    \"Mathematics argument out of domain of function\",\n    \"Disk quota exceeded\",\n    \"File exists\",\n    \"Bad address\",\n    \"File too big\",\n    \"Host unreachable\",\n    \"Identifier removed\",\n\n    \"Illegal byte sequence\",\n    \"Operation in progress\",\n    \"Interrupted function\",\n    \"Invalid argument\",\n    \"I/O error\",\n    \"Socket is connected\",\n    \"File is a directory\",\n    \"Too many levels of symbolic links\",\n\n    \"File descriptor value too large\",\n    \"Too many links\",\n    \"Message too large\",\n    \"EMULTIHOP\",\n    \"Filename too long\",\n    \"Network is down\",\n    \"Connection aborted by network\",\n    \"Network unreachable\",\n\n    \"Too many files open in system\",\n    \"No buffer space available\",\n    \"No message is available on the STREAM head read queue\",\n    \"No such device\",\n    \"No such file or directory\",\n    \"Executable file format error\",\n    \"No locks available\",\n    \"ENOLINK\",\n\n    \"Not enough space\",\n    \"No message of the desired type\",\n    \"Protocol unavailable\",\n    \"No space left on device\",\n    \"No STREAM resources\",\n    \"Not a STREAM\",\n    \"Function not supported\",\n    \"The socket is not connected\",\n\n    \"Not a directory or a symbolic link to a directory\",\n    \"Directory not empty\",\n    \"State not recoverable\",\n    \"Not a socket\",\n    \"Not supported\",\n    \"Inappropriate I/O control operation\",\n    \"No such device or address\",\n    \"Operation not supported on socket\",\n\n    \"Value too large to be stored in data type\",\n    \"Previous owner died\",\n    \"Operation not permitted\",\n    \"Broken pipe\",\n    \"Protocol error\",\n    \"Protocol not supported\",\n    \"Protocol wrong type for socket\",\n    \"Result too large\",\n\n    \"Read-only file system\",\n    \"Invalid seek\",\n    \"No such process\",\n    \"ESTALE\",\n    \"Stream ioctl() timeout\",\n    \"Connection timed out\",\n    \"Text file busy\",\n    \"Operation would block\",\n\n    \"Cross-device link\",\n    \"Unknown error\" };\n\nchar *\nstrerror(int errnum)\n{\n    unsigned int length = sizeof(strerror_errors_complete) / sizeof(strerror_errors_complete[0]) - 1; //-1 for \"Unknown error\"\n    if (((unsigned int)errnum) >= length) {\n        errno = EINVAL;\n        return (char *)strerror_errors_complete[length];\n    }\n    return (char *)strerror_errors_complete[errnum];\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/string.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STRING_H\n#define DPUSYSCORE_STRING_H\n\n/**\n * @file string.h\n * @brief Provides functions to manipulate arrays of characters.\n */\n\n#include <stddef.h>\n\n/**\n * @brief Computes the length of the given null-terminated string.\n *\n * @param string the string for which we want the length.\n * @return The length of the string, not including the null character.\n */\nsize_t\nstrlen(const char *string);\n\n/**\n * @brief Computes the length of the given null-terminated string if this length is less than <code>max_len</code>.\n * strnlen checks at most <code>max_len</code> bytes and returns <code>max_len</code> if it has read as many bytes.\n *\n * @param string the string for which we want to find the length.\n * @param max_len maximum number of bytes to check\n * @return The length of the string, not including the null character or <code>max_len</code> if null character\n * wasn't found.\n */\nsize_t\nstrnlen(const char *string, size_t max_len);\n\n/**\n * @brief Compares the first <code>size</code> bytes of <code>area1</code> and <code>area2</code>.\n *\n * @param area1 the pointer to the start of the first area of the comparison\n * @param area2 the pointer to the start of the second area of the comparison\n * @param size the number of bytes to compare between each area.\n * @return <code>0</code> if the areas are the same, a non-zero value otherwise.\n */\nint\nmemcmp(const void *area1, const void *area2, size_t size);\n\n/**\n * @brief Compares the two null-terminated strings <code>string1</code> and <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrcmp(const char *string1, const char *string2);\n\n/**\n * @brief Compares the first <code>size</code> bytes of the two null-terminated strings <code>string1</code> and\n * <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @param size the maximum number of bytes to compare between each string.\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrncmp(const char *string1, const char *string2, size_t size);\n\n/**\n * @brief Set the first <code>size</code> bytes of <code>area</code> at <code>value</code>.\n *\n * @param area the pointer to the start of the area to set\n * @param value the value at which the area is set\n * @param size the number of bytes being set\n * @return A pointer to the start of the set area.\n */\nvoid *\nmemset(void *area, int value, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the first <code>size</code> bytes of <code>area</code>.\n *\n * @param area the pointer to the start of the area to search\n * @param character the value to search for\n * @param size the number of bytes to search\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nvoid *\nmemchr(const void *area, int character, size_t size);\n\n/**\n * @brief Concatenate the string <code>source</code> after the string <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrcat(char *destination, const char *source);\n\n/**\n * @brief Concatenate the first <code>size</code> bytes of the string <code>source</code> after the string\n * <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @param size the maximum number of bytes to concatenate\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrncat(char *destination, const char *source, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrchr(const char *string, int character);\n\n/**\n * @brief Search for the last occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the last occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrrchr(const char *string, int character);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * @warning This function is not safe for overlapping memory blocks.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemcpy(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * This is a safer method than <code>memcpy</code> for overlapping memory blocks.\n *\n * @see memcpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemmove(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrncpy(char *destination, const char *source, size_t size);\n\n/**\n * @def strxfrm\n * @hideinitializer\n * @brief Transform the first <code>size</code> bytes of the string <code>source</code> into current locale and place them in the\n * string <code>destination</code>.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strncpy</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @see strncpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\n#define strxfrm strncpy\n\n/**\n * @def strcoll\n * @hideinitializer\n * @brief Compare two null-terminated strings using the current locale.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strcmp</code>.\n *\n * @see strcmp\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\n#define strcoll strcmp\n\n/**\n * @brief Copy the string <code>source</code> into the string <code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n * If <code>size</code> is less than the length of the <code>source</code>, then\n * the remaining characters in <code>destination</code> will be filled with '\\0'\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpncpy(char *destination, const char *source, size_t size);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrlwr(char *string);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrupr(char *string);\n\n/**\n * @brief Reverses the order of characters in the string\n *\n * For example, a string \"Hello\" becomes \"olleH\". The NULL character at the end\n * of the string remains at the end.\n *\n * @param string the string we want to reverse\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrrev(char *string);\n\n/**\n * @brief Returns a string corresponding to the error number\n *\n * Warning : the returned pointer should be duplicated if the user ever needs to modify it\n *\n * @param errnum number of error\n * @return the pointer to the message corresponding to the errnum or NULL if none was found\n */\nchar *\nstrerror(int errnum);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strdup(const char *string);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument (copies at most n bytes)\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @param n max number of characters to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strndup(const char *string, size_t n);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes in accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters that the longest prefix consists of\n * @return the index of the first character in string that is not in accept\n */\nsize_t\nstrspn(const char *string, const char *accept);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes not in reject.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param reject key characters that must not be in the longest prefix\n * @return the index of the first character in string that is the same as any of the ones in reject\n */\nsize_t\nstrcspn(const char *string, const char *reject);\n\n/**\n * @brief Locates the first occurrence in the target string of any of the bytes in the string accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters\n * @return a pointer to the byte in string that matches one of the bytes in accept, or NULL if no such byte is found.\n */\nchar *\nstrpbrk(const char *string, const char *accept);\n\n/**\n * @brief Finds the first occurrence of the substring needle in the string haystack.\n *\n * If needle is an empty string, the result will be the same pointer as the one passed to haystack\n * This function uses KMP algorithm, and thereby uses more memory space\n *\n * @param haystack the target string where we look for a pattern\n * @param needle pattern to look for\n * @return a pointer to the beginning of the located substring, or NULL if the substring is not found\n */\nchar *\nstrstr(const char *haystack, const char *needle);\n\n/**\n * @brief Extracts a token from a string\n *\n * The strtok_r() function breaks a string into a sequence of zero or more nonempty tokens.\n *\n * On the first call to strtok_r(), str should point to the string to be parsed, and the value of saveptr is ignored (modified\n * internally). In each subsequent call that should parse the same string, str must be NULL and saveptr should be unchanged since\n * the previous call.\n *\n * The caller may specify different strings in delim in successive calls that parse the same string. For instance, if string is\n * \"a,b,c d e f,g\", by calling strtok_r() only with \",\" delimiter will create 4 tokens, but if the user calls it 2 times with \",\"\n * delimiter and then the rest with \" \" delimiter, 6 tokens wil be created : \"a\",\"b\",\"c\",\"d\",\"e\",\"f,g\" (\"f,g\" is indeed one token\n * as strtok_r() was called with \" \" delimiter).\n *\n * Each call to strtok_r() returns a pointer to a null-terminated string containing the next token. This string does not include\n * the delimiting byte. If no more tokens are found, strtok_r() returns NULL.\n *\n * A sequence of calls to strtok_r() that operate on the same string maintains a pointer that determines the point from which to\n * start searching for the next token. The first call to strtok_r() sets this pointer to point to the first byte of the string.\n * The start of the next token is determined by scanning forward for the next nondelimiter byte in str. If such a byte is found,\n * it is taken as the start of the next token. If no such byte is found, then there are no more tokens, and strtok_r() returns\n * NULL. (A string that is empty or that contains only delimiters will thus cause strtok() to return NULL on the first call.)\n *\n * The end of each token is found by scanning forward until either the next delimiter byte is found or until the terminating null\n * byte ('\\0') is encountered. If a delimiter byte is found, it is OVERWRITTEN with a null byte to terminate the current token,\n * and strtok_r() saves a pointer to the following byte; that pointer will be used as the starting point when searching for the\n * next token. In this case, strtok_r() returns a pointer to the start of the found token.\n *\n * From the above description, it follows that a sequence of two or more contiguous delimiter bytes in the parsed string is\n * considered to be a single delimiter, and that delimiter bytes at the start or end of the string are ignored. Put another way:\n * the tokens returned by strtok() are always nonempty strings.\n *\n * Different strings may be parsed concurrently using sequences of calls to strtok_r() that specify different saveptr arguments.\n *\n * Warning :\n *      strtok_r modifies str\n *      identity of delimiter bytes is lost (i.e. most of them will be replaced by '\\0' in str)\n *      if NULL is passed as the first argument for the FIRST call, *saveptr (not saveptr) should also be NULL\n *\n * @param str string to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @param saveptr pointer used internally by strtok_r in order to maintain context between successive calls that parse the same\n * string\n * @return a pointer to the beginning of the next token terminated by '\\0' or NULL if there are no more tokens\n */\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr);\n\n/**\n * @brief Extracts a token from a string\n *\n * If *stringp is NULL, the strsep() function returns NULL and does nothing else. Otherwise, this function finds the first token\n * in the string *stringp, that is delimited by one of the bytes in the string delim. This token is terminated by overwriting the\n * delimiter with a null byte ('\\0'), and *stringp is updated to point past the token. In case no delimiter was found, the token\n * is taken to be the entire string *stringp, and *stringp is made NULL.\n *\n * Warning:\n *      strsep() modifies its first parameter\n *      identity of delimiter bytes is lost (they will be replaced by '\\0' in *stringp)\n *\n * @param stringp pointer to a string (because string will be modified) to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @return a pointer to the found null-terminated token, that is, it returns the original value of *stringp\n */\nchar *\nstrsep(char **stringp, const char *delim);\n\n#endif /* DPUSYSCORE_STRING_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrlen(const char *string)\n{\n    const char *ptr = string;\n\n    while (*ptr != '\\0') {\n        ptr++;\n    }\n\n    return ptr - string;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strlwr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrlwr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = tolower(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strncat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrncat(char *destination, const char *source, size_t size)\n{\n    size_t length = strlen(destination);\n    size_t i;\n\n    for (i = 0; (i < size) && (source[i] != '\\0'); i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strncmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrncmp(const char *string1, const char *string2, size_t size)\n{\n    for (size_t len = 0; len < size; ++len) {\n        unsigned char c1 = string1[len];\n        unsigned char c2 = string2[len];\n\n        if (((c1 - c2) != 0) || (c1 == '\\0')) {\n            return c1 - c2;\n        }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrncpy(char *destination, const char *source, size_t size)\n{\n    char *ptr = destination;\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            for (; each_byte < size; ++each_byte) {\n                *ptr = '\\0';\n                ptr++;\n            }\n\n            return destination;\n        }\n\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strndup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrndup(const char *string, size_t n)\n{\n    size_t length = strnlen(string, n);\n    char *result = buddy_alloc(length + 1);\n\n    if (result != NULL) {\n        memcpy(result, string, length);\n        ((char *)result)[length + 1] = '\\0';\n    }\n\n    return result;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strnlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrnlen(const char *string, size_t max_len)\n{\n    size_t len = 0;\n\n    while ((string[len] != '\\0') && len < max_len) {\n        len++;\n    }\n\n    return len;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strpbrk.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\nchar *\nstrpbrk(const char *string, const char *accept)\n{\n    string += strcspn(string, accept);\n    return *string ? (char *)string : NULL;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strrchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrrchr(char *string, int character)\n{\n    char *pos = NULL;\n    char *ptr = string;\n    unsigned char c;\n\n    do {\n        c = *ptr;\n        if (c == character) {\n            pos = ptr;\n        }\n        ptr++;\n    } while (c != '\\0');\n\n    return pos;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strrev.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrrev(char *string)\n{\n    size_t length = strlen(string);\n\n    for (size_t each_char = 0; each_char < length / 2; ++each_char) {\n        char c = string[each_char];\n        string[each_char] = string[length - each_char - 1];\n        string[length - each_char - 1] = c;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strsep.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrsep(char **stringp, const char *delim)\n{\n    if (*stringp == NULL) {\n        return NULL;\n    }\n\n    char *original = *stringp;\n    char *delim_ptr = strpbrk(*stringp, delim);\n\n    if (delim_ptr == NULL) {\n        *stringp = NULL;\n    } else {\n        *delim_ptr = '\\0';\n        *stringp = delim_ptr + 1;\n    }\n\n    return original;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrspn(const char *string, const char *accept)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        unsigned int accept_index = 0;\n        while (true) {\n            char a = accept[accept_index];\n\n            if (c == a) {\n                break;\n            }\n\n            if (a == '\\0') {\n                return prefix_length;\n            }\n\n            accept_index++;\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strstr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"stdbool.h\"\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrstr(const char *haystack, const char *needle)\n{\n    char *current_needle = (char *)needle;\n    char *start_haystack = (char *)haystack;\n    char *current_haystack = start_haystack;\n\n    while (true) {\n        char needle_char = *current_needle;\n\n        if (needle_char == '\\0') {\n            return start_haystack;\n        }\n\n        char haystack_char = *current_haystack;\n\n        if (haystack_char == needle_char) {\n            current_haystack++;\n            current_needle++;\n        } else if (haystack_char == '\\0') {\n            return NULL;\n        } else {\n            current_needle = (char *)needle;\n            current_haystack = ++start_haystack;\n        }\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strtok_r.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr)\n{\n    char *end;\n\n    if (str == NULL) {\n        str = *saveptr;\n    }\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    str += strspn(str, delim);\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    end = str + strcspn(str, delim);\n    if (*end == '\\0') {\n        *saveptr = end;\n        return str;\n    }\n\n    *end = '\\0';\n    *saveptr = end + 1;\n    return str;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strtol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n////\n//////TODO : **endptr\n////\n////#include <stddef.h>\n////#include \"ctype.h\"\n////#include \"limits.h\"\n////\n////static long overflow(int sign)\n////{\n////    if(sign)\n////        return INT64_MAX;\n////    else\n////        return INT64_MIN;\n////\n////\n////}\n////\n////long strtol(const char *nptr, char **endptr, int base)\n////{\n////    if(nptr == NULL)\n////        return 0;\n////    unsigned long result = 0;\n////    int sign = 1;\n////    int i = 0;\n//////    while(isspace(nptr[i]))\n//////        i++;\n////\n//////    switch(nptr[i]){\n//////        case '-' :\n//////            sign = 0;       //we change sign only when '-' was encountered\n//////        case '+' :\n//////            i++;            //we increment i in both cases\n//////    }\n////\n//////\n//////    if((base == 16 ) && (nptr[i] == '0') && (nptr[i+1] == 'x'))\n//////        i+=2;\n//////    else if(base == 0){\n//////        if(nptr[i] == '0'){\n//////            base = 8;\n//////            i++;\n//////            if(nptr[i+1] == 'x'){\n//////                base = 16;\n//////                i++;\n//////            }\n//////        }\n//////        else\n//////            base = 10;\n//////    }\n////\n//////    switch(base) {\n//////        case 10 :\n////            while(((nptr[i]>>4) == 0x3) && ((nptr[i] & 0xf)<=9)){\n////                if((unsigned long)result>>60){\n////                    return overflow(sign);\n////                }\n////\n////                result = (unsigned long)(result<<1) + (unsigned long)(result<<3) + (unsigned long) nptr[i] - (unsigned long)\n///'0';\n//////                if((unsigned long)result>>63){\n//////                    return overflow(sign);\n//////                }\n////                i++;\n////            }\n//////            break;\n//////        case 2 :\n//////            while((nptr[i] & 0xfe) == 0x30){\n//////                result = (result<<1) + (unsigned long)(nptr[i] & 0x1);\n//////                i++;\n//////            }\n//////            break;\n//////        case 4 :\n//////            while((nptr[i] & 0xfc) == 0x30){\n//////                result = (result<<2) + (unsigned long)(nptr[i] & 0x3);\n//////                i++;\n//////            }\n//////            break;\n//////        case 8 :\n//////            while((nptr[i] & 0xf8) == 0x30){\n//////                result = (result<<3) + (unsigned long)(nptr[i] & 0x7);\n//////                i++;\n//////            }\n//////            break;\n//////        case 16 :\n//////            while(((nptr[i]>='0') && (nptr[i]<='9')) || ((nptr[i]>='a') && (nptr[i]<='f')) || ((nptr[i]>='A') &&\n///(nptr[i]<='F')) ){\n//////                unsigned long digit = ((nptr[i]>='0') && (nptr[i]<='9')) ? (unsigned long)(nptr[i] - '0') : (unsigned\n/// long)((nptr[i] & 0xf) + 10);\n//////                result = result<<4;\n//////                result = result + digit;\n//////                i++;\n//////            }\n//////            break;\n//////        default :\n//////            if(base < 2 || base > 36){ //base 0 has already been replaced by 8,10 or 16\n//////                //TODO!!!\n//////                break;\n//////            }\n//////    }\n////\n//////    if(sign == 0)\n//////        return (long)0 - (long)result;\n//////    else\n////        return (long) result;\n////\n////}\n////\n//\n//\n//\n////\n//\n//// Copyright (c) 2014-2019 - UPMEM\n//\n////\n//\n//#include <stddef.h>\n//\n//#include \"limits.h\"\n//\n//#include \"ctype.h\"\n//\n// static long overflow(int sign)\n//\n//{\n//\n//    if(sign)\n//\n//        return INT64_MAX;\n//\n//    else\n//\n//        return INT64_MIN;\n//\n//}\n//\n// long int strtol(const char *nptr, char **endptr, int base)\n//\n//{\n//\n//    if(nptr == NULL)\n//\n//        return 0;\n//\n//    int sign = 1;\n//\n//    int i=0;\n//\n//    long result = 0;\n//\n//\n//\n//    while((nptr[i]>='0') && (nptr[i]<='9')){\n//\n//        if(result>>60){\n//\n//                    return overflow(sign);\n//\n//                }\n//\n//        result = (result<<1) + (result<<3)+ nptr[i] - '0';\n//\n//        i++;\n//\n//    }\n//\n//    return result;\n//\n//}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/stdlib/strupr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrupr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = toupper(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/CMakeLists.txt",
    "content": "set(CMAKE_C_COMPILER \"/root/upmem-2023.2.0-Linux-x86_64/bin/dpu-upmem-dpurte-clang\")\nset(CMAKE_C_FLAGS \"-O3 -S -DNR_TASKLETS=${NR_TASKLETS}\")\n\ninclude_directories(\"/root/uPIMulator/sdk/misc\")\ninclude_directories(\"/root/uPIMulator/sdk/stdlib\")\ninclude_directories(\"/root/uPIMulator/sdk/syslib\")\n\nfile(GLOB_RECURSE SRCS *.c)\n\nadd_library(syslib ${SRCS})\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/absvdi2.c",
    "content": "/*===-- absvdi2.c - Implement __absvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __absvdi2 for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI di_int\n__absvdi2(di_int a)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    if (a == ((di_int)1 << (N - 1)))\n        compilerrt_abort();\n    const di_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/absvsi2.c",
    "content": "/* ===-- absvsi2.c - Implement __absvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __absvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI si_int\n__absvsi2(si_int a)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    if (a == (1 << (N - 1)))\n        compilerrt_abort();\n    const si_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/adddf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI double\n__adddf3(double a, double b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_dadd(double a, double b)\n{\n    return __adddf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/addsf3.c",
    "content": "//===-- lib/addsf3.c - Single-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI float\n__addsf3(float a, float b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_fadd(float a, float b)\n{\n    return __addsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/addvdi3.c",
    "content": "/* ===-- addvdi3.c - Implement __addvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI di_int\n__addvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a + (du_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/addvsi3.c",
    "content": "/* ===-- addvsi3.c - Implement __addvsi3 -----------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI si_int\n__addvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a + (su_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nvolatile unsigned int __sys_heap_pointer = (unsigned int)(&__sys_heap_pointer_reset);\n\nATOMIC_BIT_INIT(__heap_pointer);\n\n/* noinline, because part of grind tracked functions\n * Also used by seqread.inc\n */\nvoid *__noinline\nmem_alloc_nolock(size_t size)\n{\n    unsigned int pointer = __HEAP_POINTER;\n\n    if (size != 0) {\n        pointer = (pointer + 7) & ~7;\n\n        unsigned int new_heap_pointer, dummy;\n\n        __asm__ volatile(\"\\tadd %[nhp], %[ptr], %[sz], nc, . + 2\\n\"\n                         \"\\tfault \" __STR(__FAULT_ALLOC_HEAP_FULL__) \"\\n\"\n                                                                     \"\\tlbu %[dumb], %[nhp], -1\\n\"\n                         : [nhp] \"=r\"(new_heap_pointer), [dumb] \"=r\"(dummy)\n                         : [ptr] \"r\"(pointer), [sz] \"r\"(size));\n\n        __HEAP_POINTER = new_heap_pointer;\n    }\n    return (void *)pointer;\n}\n\nvoid *\nmem_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n    void *pointer = mem_alloc_nolock(size);\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n    return pointer;\n}\n\nvoid *\nmem_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    void *initial = &__sys_heap_pointer_reset;\n\n    __sys_heap_pointer = (unsigned int)initial;\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return (void *)initial;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ALLOC_H\n#define DPUSYSCORE_ALLOC_H\n\n/**\n * @file alloc.h\n * @brief Provides a way to manage heap allocation.\n *\n * @internal The heap is situated after the different kernel structures, local and global variables.\n *           It can grow until reaching the end of the WRAM. A reboot of the DPU reset the Heap.\n *           The current heap pointer can be accessed at the address defined by __HEAP_POINTER__.\n */\n\n#include <stddef.h>\n\n#include <fsb_allocator.h>\n#include <buddy_alloc.h>\n\n#include <attributes.h>\n\n/**\n * @fn mem_alloc\n * @brief Allocates a buffer of the given size in the heap.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * @param size the allocated buffer's size, in bytes\n * @throws a fault if there is no memory left\n * @return The allocated buffer address.\n */\nvoid *\nmem_alloc(size_t size);\n\n/**\n * @fn mem_reset\n * @brief Resets the heap.\n *\n * Every allocated buffer becomes invalid, since subsequent allocations restart from the beginning\n * of the heap.\n *\n * @return The heap initial address.\n */\nvoid *\nmem_reset(void);\n\n#endif /* DPUSYSCORE_ALLOC_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ashldi3.c",
    "content": "/* ====-- ashldi3.c - Implement __ashldi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashldi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a << b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashldi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.low = 0;\n        result.s.high = input.s.low << (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.low = input.s.low << b;\n        result.s.high = (input.s.high << b) | (input.s.low >> (bits_in_word - b));\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsl(di_int a, si_int b)\n{\n    return __ashldi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ashrdi3.c",
    "content": "/*===-- ashrdi3.c - Implement __ashrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: arithmetic a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        /* result.s.high = input.s.high < 0 ? -1 : 0 */\n        result.s.high = input.s.high >> (bits_in_word - 1);\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_lasr(di_int a, si_int b)\n{\n    return __ashrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/atomic_bit.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATOMIC_BIT_H\n#define DPUSYSCORE_ATOMIC_BIT_H\n\n/**\n * @file atomic_bit.h\n * @brief Provides direct access to the atomic bits.\n */\n\n#include <stdint.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n#define ATOMIC_BIT_GET(_name) __CONCAT(__atomic_bit_, _name)\n#define ATOMIC_BIT_INIT(_name) uint8_t __atomic_bit ATOMIC_BIT_GET(_name)\n#define ATOMIC_BIT_EXTERN(_name) extern ATOMIC_BIT_INIT(_name)\n\nextern uint8_t __atomic_start_addr;\n#define ATOMIC_BIT_INDEX(_name) (&ATOMIC_BIT_GET(_name) - &__atomic_start_addr)\n\n#define __ATOMIC_BIT_ACQUIRE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"acquire %[areg], %[abit], nz, .\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define __ATOMIC_BIT_RELEASE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"release %[areg], %[abit], nz, .+1\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define ATOMIC_BIT_ACQUIRE(_name) __asm__ volatile(\"acquire zero, %[abit], nz, .\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#define ATOMIC_BIT_RELEASE(_name) __asm__ volatile(\"release zero, %[abit], nz, .+1\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#endif /* DPUSYSCORE_ATOMIC_BIT_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/atomics.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Prototype of function can be found here: https://llvm.org/docs/Atomics.html\n */\n\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\n#define ATOMIC_BIT llvm_atomic_functions\nATOMIC_BIT_INIT(ATOMIC_BIT);\n\n#define FOR_ALL_TYPES(fct) fct(1, char) fct(2, short) fct(4, int) fct(8, long long)\n\n#define PROLOGUE(ptr, load, n_type)                                                                                              \\\n    n_type load;                                                                                                                 \\\n    ATOMIC_BIT_ACQUIRE(ATOMIC_BIT);                                                                                              \\\n    load = *ptr;\n\n#define EPILOGUE(load)                                                                                                           \\\n    ATOMIC_BIT_RELEASE(ATOMIC_BIT);                                                                                              \\\n    return load;\n\n#define __SYNC_VAL_COMPARE_AND_SWAP_N(n_val, n_type)                                                                             \\\n    n_type __dpu_sync_val_compare_and_swap_##n_val(volatile n_type *ptr, n_type expected, n_type desired)                        \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        if (load == expected)                                                                                                    \\\n            *ptr = desired;                                                                                                      \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_VAL_COMPARE_AND_SWAP_N)\n\n#define __SYNC_LOCK_TEST_AND_SET_N(n_val, n_type)                                                                                \\\n    n_type __dpu_sync_lock_test_and_set_##n_val(volatile n_type *ptr, n_type val)                                                \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = val;                                                                                                              \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_LOCK_TEST_AND_SET_N)\n\n#define __SYNC_FETCH_AND_DO_N(fct, fct_name, n_val, n_type)                                                                      \\\n    n_type __dpu_sync_fetch_and_##fct_name##_##n_val(volatile n_type *ptr, n_type val)                                           \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = fct(load, val, n_type);                                                                                           \\\n        EPILOGUE(load);                                                                                                          \\\n    }\n\n#define DO_ADD(a, b, n_type) ((a) + (b))\n#define __SYNC_FETCH_AND_ADD_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_ADD, add, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_ADD_N)\n\n#define DO_SUB(a, b, n_type) ((a) - (b))\n#define __SYNC_FETCH_AND_SUB_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_SUB, sub, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_SUB_N)\n\n#define DO_AND(a, b, n_type) ((a) & (b))\n#define __SYNC_FETCH_AND_AND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_AND, and, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_AND_N)\n\n#define DO_OR(a, b, n_type) ((a) | (b))\n#define __SYNC_FETCH_AND_OR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_OR, or, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_OR_N)\n\n#define DO_XOR(a, b, n_type) ((a) ^ (b))\n#define __SYNC_FETCH_AND_XOR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_XOR, xor, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_XOR_N)\n\n#define DO_NAND(a, b, n_type) (~((a) & (b)))\n#define __SYNC_FETCH_AND_NAND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_NAND, nand, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_NAND_N)\n\n#define DO_MAX(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MAX, max, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MAX_N)\n\n#define DO_UMAX(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMAX, umax, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMAX_N)\n\n#define DO_MIN(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MIN, min, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MIN_N)\n\n#define DO_UMIN(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMIN, umin, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMIN_N)\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/attributes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATTRIBUTES_H\n#define DPUSYSCORE_ATTRIBUTES_H\n\n/**\n * @file attributes.h\n * @brief Provides common useful compiler attributes.\n */\n\n#define DEPRECATED __attribute__((deprecated))\n\n#if __STDC_VERSION__ >= 201112L\n#define __NO_RETURN _Noreturn\n#else\n#define __NO_RETURN\n#endif /* __STDC_VERSION__ */\n\n#define __weak __attribute__((weak))\n\n#define __section(s) __attribute__((section(s)))\n\n#define __aligned(a) __attribute__((aligned(a)))\n\n#define __used __attribute__((used))\n\n#define __noinline __attribute__((noinline))\n\n#define __atomic_bit __section(\".atomic\")\n\n#define __dma_aligned __aligned(8)\n\n#define __keep __used __section(\".data.__sys_keep\")\n\n#define __host __aligned(8) __used __section(\".dpu_host\")\n\n// Use this macro at variable definition to place this variable into the section\n// .data.immediate_memory and then makes it possible to use this variable\n// directly as an immediate into load store instructions (and then avoids the need\n// to move the address into a register before): immediate values are 12 signed bits\n// large.\n#define __lower_data(name) __attribute__((used, section(\".data.immediate_memory.\" name)))\n\n/**\n * @def __mram_ptr\n * @brief An attribute declaring that a pointer is an address in MRAM.\n *\n * A typical usage is: ``unsigned int __mram_ptr * array32 = (unsigned int __mram_ptr *) 0xf000;``\n *\n * Performing a cast between a pointer in MRAM and a pointer in WRAM is not allowed by the compiler.\n *\n */\n#define __mram_ptr __attribute__((address_space(255)))\n\n#define __mram __mram_ptr __section(\".mram\") __dma_aligned __used\n\n#define __mram_noinit __mram_ptr __section(\".mram.noinit\") __dma_aligned __used\n\n#define __mram_keep __mram_ptr __section(\".mram.keep\") __dma_aligned __used\n\n#define __mram_noinit_keep __mram_ptr __section(\".mram.noinit.keep\") __dma_aligned __used\n\n#endif /* DPUSYSCORE_ATTRIBUTES_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/barrier.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <barrier.h>\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nvoid\nbarrier_wait(struct barrier_t *barrier)\n{\n    unsigned char lock = barrier->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = barrier->count;\n    unsigned char last = barrier->wait_queue;\n    unsigned char first;\n    thread_id_t tid = me();\n\n    /* Count = 1 means that I am the last to enter the barrier.\n     * Need to wake up everybody.*/\n    if (unlikely(count == 1)) {\n        if (likely(last != __EMPTY_WAIT_QUEUE)) {\n            first = __WAIT_QUEUE_TABLE[last];\n            while (first != last) {\n                __resume(first, \"0\");\n                first = __WAIT_QUEUE_TABLE[first];\n            }\n            __resume(first, \"0\");\n            barrier->wait_queue = __EMPTY_WAIT_QUEUE;\n            barrier->count = barrier->initial_count;\n        }\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    } else {\n        if (unlikely(last == __EMPTY_WAIT_QUEUE)) {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        } else {\n            first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        }\n\n        barrier->wait_queue = tid;\n        barrier->count = --count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/barrier.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BARRIER_H\n#define DPUSYSCORE_BARRIER_H\n\n/**\n * @file barrier.h\n * @brief Synchronization with barriers.\n *\n * This synchronization mechanism allows to suspend a fixed number of tasklets until the expected number of subscribers is\n * present. When the required number of tasklets reached the barrier, the counter of the barrier will be reinitialised to the\n * original value.\n *\n * @internal The barriers are represented by a static value, defining the number of expected tasklets, a counter for the\n *           current number of tasklets suspended by this barrier and a wait queue entry.\n *           Whenever a new tasklet reaches the barrier (barrier_wait), the counter is  decremented and the tasklet\n *           is put into the wait queue.\n *           If the counter is reduced to 0, all the tasklets that were suspended by this barrier will be resumed and\n *           the counter will be reinitialised to its initial value.\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef barrier_t\n * @brief A barrier object, as declared by BARRIER_INIT.\n */\ntypedef struct barrier_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} barrier_t;\n\n/**\n * @def BARRIER_INIT\n * @hideinitializer\n * @brief Declare and initialize a barrier associated to the given name.\n */\n/* clang-format off */\n#define BARRIER_INIT(_name, _counter)                                                                                            \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"barrier counter must be encoded on a byte\");                         \\\n    ATOMIC_BIT_INIT(__CONCAT(barrier_, _name));                                                                                  \\\n    extern barrier_t _name;                                                                                                      \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR( _name) \",@object\\n\"                                                                                  \\\n            \".globl \" __STR( _name) \"\\n\"                                                                                         \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(barrier_,_name))) \"\\n\"                                                        \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn barrier_wait\n * @brief Decrements the counter associated to the barrier and suspends the invoking tasklet.\n *\n * The counter of the barrier is decremented and the invoking tasklet is suspended until\n * the counter associated to the barrier is reduced to 0.\n *\n * @param barrier the barrier the tasklet will be associated to.\n */\nvoid\nbarrier_wait(barrier_t *barrier);\n\n#endif /* DPUSYSCORE_BARRIER_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/bswapdi2.c",
    "content": "/* ===-- bswapdi2.c - Implement __bswapdi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint64_t\n__bswapdi2(uint64_t u)\n{\n    return ((((u)&0xff00000000000000ULL) >> 56) | (((u)&0x00ff000000000000ULL) >> 40) | (((u)&0x0000ff0000000000ULL) >> 24)\n        | (((u)&0x000000ff00000000ULL) >> 8) | (((u)&0x00000000ff000000ULL) << 8) | (((u)&0x0000000000ff0000ULL) << 24)\n        | (((u)&0x000000000000ff00ULL) << 40) | (((u)&0x00000000000000ffULL) << 56));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/bswapsi2.c",
    "content": "/* ===-- bswapsi2.c - Implement __bswapsi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint32_t\n__bswapsi2(uint32_t u)\n{\n    return ((((u)&0xff000000) >> 24) | (((u)&0x00ff0000) >> 8) | (((u)&0x0000ff00) << 8) | (((u)&0x000000ff) << 24));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/buddy_alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <buddy_alloc.h>\n#include <alloc.h> //for mem_alloc\n#include <stddef.h> //for size_t\n#include <string.h> //for memset\n#include <dpuruntime.h>\n#include <errno.h>\n#include <defs.h>\n#include <stdbool.h>\n#include <built_ins.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nstatic unsigned char __buddy_init_done = 0;\nstatic int *__buddy_blocks = 0;\nstatic void *__buddy_heap_start = 0;\nstatic unsigned int __BUDDY_SIZE_OF_HEAP__ = 0;\nstatic unsigned char __BUDDY_MAX_POWER__ = 0;\nstatic unsigned char __BUDDY_NUMBER_OF_LEVELS__ = 0;\n\nATOMIC_BIT_INIT(__buddy_lock);\n\n#define __BUDDY_DEPTH_LEVELS__ 3\n#define __BUDDY_SHIFT_ADDRESS_TO_INDEX__ 4\n\nstatic inline unsigned int\nnext_power_of_2(int x)\n{\n    // in order to find the size of the block to allocate we\n    // count the number of leading zeros to get the correct\n    // log2(size)\n    // if size has only one \"1\" bit then we keep this power of 2\n    // otherwise, we add 1\n\n    unsigned int power_of_2 = 31 - count_leading_zeros(x);\n\n    if (count_population(x) != 1) {\n        power_of_2++;\n    }\n\n    return power_of_2;\n}\n\n/*\n * Note 1:\n *   each bit represents the state of a block. It can equal either 0 or 1 and can represent 4 different states of a block :\n *   target = 1 & buddy = 0                                      -> free                     : target block is [free] and can be\n * allocated without the need to cut the bigger block in half target = 1 & buddy = 1                                      -> not\n * in use               : neither target nor its buddy are in use and bigger blocks must be checked\n *\n *   target = 0 & both successors = 1 [not in use]               -> allocated                : this block is completely allocated\n *   target = 0 & one or both of the successors = 0 [allocated]  -> partially allocated      : block is partially allocated i.e.\n * at least one of the sub-blocks is [allocated]\n *\n * Note 2:\n *  Indexes of __buddy_blocks are indeed quite bizarre, which was a mistake during the conception stage. It doesn't change much.\n *  Indexe_in_level start from 0 from left to right, but not for the 5 least significant bits where they still start from 0 but\n * from right to left\n */\nvoid *\nsafe_buddy_alloc(size_t size)\n{\n    if ((size == 0) || (size > __BUDDY_SIZE_OF_HEAP__)) {\n        errno = EINVAL;\n        return NULL;\n    }\n\n    // we replace the size by the smallest 2 to the power of X such as it is greater than or equals the size\n    // afterwards, we take X as power_of_2 and thereby find the correct level to search for free blocks:\n    // blocks_level = __BUDDY_MAX_POWER__ - power_of_2\n    // for example if we try to allocate a block of 64 bytes (64=2^6), blocks_level = __BUDDY_MAX_POWER__ - 6\n\n    unsigned int power_of_2 = next_power_of_2(size);\n    int blocks_level = __BUDDY_MAX_POWER__ - power_of_2;\n\n    // if the size is smaller than the minimal size of\n    // block divided by 2, then we can't allocate a block\n    // so small and we have to allocate the block of the\n    // minimal allowed size\n    if (blocks_level >= __BUDDY_NUMBER_OF_LEVELS__) {\n        blocks_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n    }\n\n    // we browse all levels until we find the smallest free block that is big enough to contain \"size\" bytes\n    for (int blocks_level_current = blocks_level; blocks_level_current >= 0; --blocks_level_current) {\n        // we initialise index_in_level as the biggest index permitted in level\n        unsigned int index_in_level = 1 << blocks_level_current;\n\n        // levels 0-4 are in the same bitfield,\n        // level 5 consists of a single bitfield\n        // all other levels consist of 1<<(#level - 5)\n        // bitfields\n        unsigned int initial_number_of_current_bitfield = 0;\n        unsigned int loaded_case_mask;\n\n        switch (blocks_level_current) {\n            default:\n                initial_number_of_current_bitfield = ((1 << blocks_level_current) >> 5) - 1;\n                loaded_case_mask = 0xFFFFFFFF;\n                break;\n            case 0:\n                loaded_case_mask = 0x40000000;\n                break;\n            case 1:\n                loaded_case_mask = 0x30000000;\n                break;\n            case 2:\n                loaded_case_mask = 0x0F000000;\n                break;\n            case 3:\n                loaded_case_mask = 0x00FF0000;\n                break;\n            case 4:\n                loaded_case_mask = 0x0000FFFF;\n                break;\n        }\n\n        for (int number_of_current_bitfield = initial_number_of_current_bitfield; number_of_current_bitfield >= 0;\n             --number_of_current_bitfield, index_in_level -= 32) {\n            // sizes of levels in __buddy_blocks is a geometric\n            // series and thereby we can easily calculate the\n            // number of bitfields that precede the current level\n            unsigned int real_index = (1 << blocks_level_current) >> 5;\n            // we load the bitfield\n            unsigned int *initial_loaded_case_address\n                = (unsigned int *)(__buddy_blocks + number_of_current_bitfield + real_index);\n            // if we are in the very first bitfield\n            // that contains first 5 levels, then we\n            // need to make sure that buddy_free will\n            // ignore the bits that represent blocks\n            // that don't belong to blocks_level_current\n            unsigned int loaded_case = *initial_loaded_case_address & loaded_case_mask;\n\n            // this formula gives the number of zeros\n            // before the first pair of free/allocated blocks\n            // present in the current bitfield. If it equals\n            // 32, then no such pair is present.\n            unsigned int lz_before_first_pair_tmp = ((loaded_case << 1) ^ loaded_case) & 0xAAAAAAAA;\n\n            if (lz_before_first_pair_tmp != 0) {\n                unsigned int lz_before_first_pair = count_leading_zeros(lz_before_first_pair_tmp);\n                index_in_level = index_in_level - lz_before_first_pair - 1;\n\n                // if we are in the very first bitfield,\n                // then we need to take into account the special\n                // positioning of the 5 levels of blocks\n                // inside this bitfield\n                if (blocks_level_current < 5) {\n                    index_in_level += 1 << blocks_level_current;\n                }\n\n                unsigned int highlight_target_bit = 1 << index_in_level;\n\n                // if current level is among first 4\n                //(5th is unnecessary to consider)\n                // then we need to shift the mask\n                if (blocks_level_current < 4) {\n                    // we want to find the value of the offset to shift the mask for target and its buddy\n                    // offset = 32 - 2^(current_lvl+1)\n                    highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                }\n\n                // we have the position of a pair of\n                // free/allocated blocks, but we might\n                // need to shift this position by 1\n                // if the target's buddy is the potential\n                // block to allocate\n                loaded_case = loaded_case & highlight_target_bit;\n\n                if (loaded_case == 0) {\n                    highlight_target_bit = highlight_target_bit >> 1;\n                    index_in_level--;\n                }\n\n                // loaded_case have been modified if the first bitfield is handled\n                loaded_case = *initial_loaded_case_address;\n\n                // we mark the target bit as allocated\n                loaded_case -= highlight_target_bit;\n                *initial_loaded_case_address = loaded_case;\n\n                // if we have already had a free block of the necessary size,\n                // we return its address, otherwise we jump to\n                //__buddy_alloc_break_loop and start cutting the blocks\n                // in half until we get a block of the required size\n                if (blocks_level == blocks_level_current) {\n                    return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n                }\n\n                // we have already set the block to 0 [partially allocated]\n                // so we descend and start with the next one\n                blocks_level_current++;\n\n                while (blocks_level_current <= blocks_level) {\n                    index_in_level = index_in_level << 1;\n                    highlight_target_bit = 1 << index_in_level;\n\n                    // first 5 levels are stored in the same\n                    // bitfield. We need to handle this\n                    // special case and shift the mask\n                    int blocks_level_clamped = blocks_level_current - 4;\n\n                    if (blocks_level_clamped < 0) {\n                        highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                    }\n\n                    // we load the bitfield\n\n                    // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n                    unsigned int real_index = 0;\n                    blocks_level_clamped--;\n                    if (blocks_level_clamped >= 0) {\n                        real_index = 1 << blocks_level_clamped;\n                        blocks_level_clamped = index_in_level >> 5;\n                        real_index += blocks_level_clamped;\n                    }\n                    loaded_case = __buddy_blocks[real_index];\n\n                    // we mark the bit as allocated\n                    __buddy_blocks[real_index] = loaded_case - highlight_target_bit;\n\n                    // we continue to descend\n                    blocks_level_current++;\n                }\n\n                return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n            }\n        }\n    }\n\n    // if no level contains a big enough block, we return NULL\n    errno = ENOMEM;\n    return NULL;\n}\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nint\nbuddy_search_for_pointer(void *pointer, buddy_search_context_t context)\n{\n    // if the pointer is not aligned to 64 bits, then it is corrupted\n    // if the pointer is outside of the heap, we can do nothing\n    if (((((unsigned int)pointer) & 7) != 0) || (pointer < __buddy_heap_start)\n        || (pointer > (__buddy_heap_start + __BUDDY_SIZE_OF_HEAP__ - 1))) {\n        errno = EINVAL;\n        return -1;\n    }\n\n    // we transform the real address into an index for __buddy_blocks\n    // index_in_level = (pointer - START_OF_HEAP)>>__BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    unsigned int index_in_level = (pointer - __buddy_heap_start) >> __BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    // we start to search for the pointer from the lowest level\n    unsigned int target_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n\n    while (true) {\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        unsigned int highlight_target_bit = 1 << index_in_level;\n        unsigned int highlight_buddy_bit;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the\n        // same bitfield. We need to handle\n        // this special case and shift\n        // the masks\n        int target_level_clamped = target_level - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << target_level);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding to the index\n        // in __buddy_blocks\n        // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n        unsigned int real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index_in_level >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        unsigned int loaded_case = __buddy_blocks[real_index];\n\n        // We search for an allocated block\n        // if we are on the highest level, we quit.\n        if (((loaded_case & highlight_target_bit) == 0) || (target_level <= 0)) {\n            context->target_level = target_level;\n            context->real_index = real_index;\n            context->highlight_target_bit = highlight_target_bit;\n            context->highlight_buddy_bit = highlight_buddy_bit;\n            return index_in_level;\n        }\n\n        // Condition required to avoid unwanted release\n        if ((loaded_case & highlight_buddy_bit) == 0) {\n            errno = EINVAL;\n            return -1;\n        }\n\n        // we rise to the higher level\n        index_in_level = index_in_level >> 1;\n        target_level--;\n    }\n}\n\nstatic void\nbuddy_free_fusion_of_blocks(unsigned int index, buddy_search_context_t context)\n{\n    unsigned int real_index = context->real_index;\n    unsigned int current_level_freeing = context->target_level;\n    unsigned int highlight_target_bit = context->highlight_target_bit;\n    unsigned int highlight_buddy_bit = context->highlight_buddy_bit;\n    unsigned int loaded_case = __buddy_blocks[real_index];\n    // if we are at the highest level, there is nothing to fuse\n    while (current_level_freeing > 0) {\n        // fusion occurs only when both blocks are free\n        if (((loaded_case & highlight_target_bit) == 0) | ((loaded_case & highlight_buddy_bit) == 0)) {\n            return;\n        }\n\n        // index of predecessor = index of successor >> 1\n        index = index >> 1;\n        // we rise to the higher level\n        current_level_freeing--;\n\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        highlight_target_bit = 1 << index;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the same bitfield.\n        // We need to handle this special case and shift\n        // the masks\n        int target_level_clamped = current_level_freeing - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << current_level_freeing);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding\n        // to the index in __buddy_blocks\n        //\n        // As both sub-blocks were freed, their \"father\"\n        // must be marked as free.\n        real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        loaded_case = __buddy_blocks[real_index] | highlight_target_bit;\n        __buddy_blocks[real_index] = loaded_case;\n    }\n}\n\nvoid\nsafe_buddy_free(void *pointer)\n{\n    struct _buddy_search_context_t context;\n\n    int index = buddy_search_for_pointer(pointer, &context);\n\n    if (index != -1) {\n        __buddy_blocks[context.real_index] |= context.highlight_target_bit;\n        buddy_free_fusion_of_blocks(index, &context);\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline *\nbuddy_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = safe_buddy_alloc(size);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_free(void *pointer)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    safe_buddy_free(pointer);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n\n/*if the size of the smallest block needs to be changed, then only 2 things need to change :\n *  __BUDDY_DEPTH_LEVELS__ here in buddy_init.c\n *  __BUDDY_SHIFT_ADDRESS_TO_INDEX__ in buddy_defs.s\n *\n *  When the minimal size of a block needs to be 32 bytes, then these two constants must equal 4 and 5 correspondingly\n *  If minimal size needs to be 16 bytes, then these two constants must equal 3 and 4 correspondingly\n *  If minimal size needs to be 8 bytes, then these two constants must equal 2 and 3 correspondingly\n *\n *  Also, certain tests (Global, Reset, LevelByLevel) should also be changed.\n */\n\n// TODO: Right now the size must be of power of 2 : 2048, 4096, 8192 and it won't work with other sizes.\n// TODO: There is no point in accepting other sizes, as the whole idea of having buddy allocation is based on it.\n// TODO: Right now the possibility of failure of mem_alloc is not taken into account of.\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_init(size_t size_of_heap)\n{\n    if (__buddy_init_done == 0) {\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n\n        __BUDDY_SIZE_OF_HEAP__ = size_of_heap;\n\n        unsigned int power_of_2 = count_leading_zeros(size_of_heap);\n        __BUDDY_MAX_POWER__ = (31 - power_of_2);\n\n        __BUDDY_NUMBER_OF_LEVELS__ = __BUDDY_MAX_POWER__ - __BUDDY_DEPTH_LEVELS__;\n\n        unsigned int blocks_in_buddy_blocks = (1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2;\n        __buddy_blocks = mem_alloc(size_of_heap + blocks_in_buddy_blocks);\n\n        __buddy_heap_start = __buddy_blocks + (blocks_in_buddy_blocks >> 2);\n\n        __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n        memset(&__buddy_blocks[1], 0xff, blocks_in_buddy_blocks - 4); // in order to initialize the __buddy_blocks structure\n        __buddy_init_done = 1;\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n\n    __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n    memset(&__buddy_blocks[1],\n        0xff,\n        ((1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2) - 4); // in order to initialize the __buddy_blocks structure\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/buddy_alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BUDDY_ALLOC_H\n#define DPUSYSCORE_BUDDY_ALLOC_H\n\n/**\n * @file buddy_alloc.h\n * @brief Dynamic memory allocation and freeing.\n *\n * This library allows to create unique memory space in the heap to allocate and free\n * blocks of data.\n *\n * The memory space is initialized with <code>buddy_init</code>, which must be invoked only once during\n * the program's lifecycle.\n *\n * Functions can then dynamically get and free buffers, using <code>buddy_alloc</code> and <code>buddy_free</code>\n * respectively.\n *\n * In this implementation, the allocatable buffer size is chosen during the first call to <code>buddy_init</code>.\n * Tested sizes : 2048, 4096, 8192, 16384 and 32768 bytes\n * The allocated buffers are properly aligned on DMA transfer constraints, so that they can be\n * used as is in MRAM/WRAM transfer operations.\n */\n\n/*\n * @internal The algorithm used in this implementation is Buddy memory allocation.\n *\n * A particularity of this implementation is that no headers are created and thereby\n * the memory consumption of the heap is reduced. The drawback is a slight slow-down\n * in speed of memory freeing.\n *\n * Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free. If the pointer given in the parameter\n *   is not currently allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>, <code>buddy_free</code>\n *   will do nothing.\n *\n */\n\n#include <stddef.h>\n\n/**\n * @fn buddy_init\n * @brief Allocates size_of_heap bytes for a heap that <code>buddy_alloc</code> can access to.\n *\n * Reserves memory space in the heap used to perform dynamic allocation and release of buffers.\n *\n * @param size_of_heap the size of heap in bytes that <code>buddy_alloc</code> can access to\n */\nvoid\nbuddy_init(size_t size_of_heap);\n\n/**\n * @fn buddy_reset\n * @brief Resets the heap.\n *\n * Quickly frees all pointers allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>.\n * Warning : currently buddy_reset() doesn't reset the size of the allocated heap.\n */\nvoid\nbuddy_reset(void);\n\n/**\n * @fn buddy_alloc\n * @brief Allocates a buffer of the given size in the heap, in a runtime-safe way.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * Due to the idea of the buddy algorithm (to decrease external fragmentation),\n * the allocated blocks will be of size equal to a power of 2. In other words,\n * if the user allocates 33 bytes, 64 bytes will be allocated and when 2049 bytes\n * are requested, 4096 will be allocated. The user might want to take this into\n * account if she/he wishes to minimise the memory consumption.\n *\n * The minimal size of the allocated block is 16 bytes, but can easily be changed in\n * future implementations, so <code>buddy_alloc</code> is mostly adapted to allocating medium and\n * big structures, such as arrays containing more than 8 bytes (in order to make sure\n * that not too much memory space is wasted), binary trees or linked lists.\n *\n * If the <code>size</code> passed in parameter is less or equal to 0 or greater than the size of heap,\n * errno will be set to EINVAL and <code>buddy_alloc</code> will do nothing.\n * If <code>buddy_alloc</code> fails to find enough free memory space to allocate, errno will be\n * set to ENOMEM.\n *\n * @param size the allocated buffer's size, in bytes\n * @return A pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_alloc(size_t size);\n\n/**\n * @fn buddy_free\n * @brief Frees a specified pointer, in a runtime-safe way.\n *\n *  Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free and will see a pointer to the beginning of the\n *   block in the same way as the pointer to anywhere inside the block. For example, if we have\n *   allocated an int array[10], <code>buddy_free</code> will treat &array[0] the same way as &array[1]\n *   or as the address of any other element inside this array and will free the whole block.\n *\n * If the pointer given in the parameter is not currently allocated by <code>buddy_alloc</code> or\n * <code>buddy_realloc</code>, <code>buddy_free</code> will do nothing.\n *\n * This function frees the memory space pointed to by pointer, which\n * must have been returned by a previous call to <code>buddy_alloc</code> or <code>buddy_realloc</code>\n * If it wasn't or if <code>buddy_free</code> has already been called for this pointer before,\n * then <code>buddy_free</code> will do nothing. If pointer is NULL, no operation is performed.\n * If the pointer passed as a parameter is not aligned to 64 bits or if it is outside\n * of the allocated heap errno will be set to EINVAL.\n * If <code>buddy_free</code> detects the attempt to free a non-allocated pointer, it will equally\n * set errno to EINVAL.\n *\n * @param pointer the pointer to the block to free\n */\nvoid\nbuddy_free(void *pointer);\n\n/**\n * @fn buddy_realloc\n * @brief Changes the size of the memory block pointed to by <code>ptr</code> to <code>size</code> bytes in a runtime-safe way.\n *\n * The contents will be unchanged in the range from the start of the region up to the minimum of the old and new sizes.\n * If the new <code>size</code> is larger than the old size, the added memory will not be initialized.\n * If <code>ptr</code> is NULL, then the call is equivalent to <code>buddy_alloc(size)</code> for all values of <code>size</code>.\n * If <code>size</code> is equal to zero, and <code>ptr</code> is not NULL, then the call is equivalent to\n * <code>buddy_free(ptr)</code> and the return value will be equal to the pointer passed as the parameter. Unless <code>ptr</code>\n * is NULL, it should have been returned by an earlier call to <code>buddy_alloc()</code> or <code>buddy_realloc()</code>. If it\n * wasn't, then <code>buddy_realloc()</code> will try to find this pointer among the allocated ones, but undefined behavior might\n * occur.\n *\n * If new <code>size</code> is smaller than the old size, then the remaining memory will potentially be released (depends\n * on the size of block).\n *\n * <code>buddy_realloc()</code> internally calls <code>buddy_alloc</code> and <code>buddy_free</code> and thereby will set errno\n * to ENOMEM or EINVAL on failure.\n *\n * @param ptr original pointer\n * @param size the new allocated buffer's size, in bytes\n * @return A new (or the same) pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_realloc(void *ptr, size_t size);\n\n#endif /* DPUSYSCORE_BUDDY_ALLOC_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/buddy_realloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n// todo integrate in buddy_alloc.c, when we have reduced the buddy_alloc object file size\n\n#include <buddy_alloc.h>\n#include <stddef.h>\n#include <alloc.h>\n#include <string.h> //for memcpy\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nATOMIC_BIT_EXTERN(__buddy_lock);\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nextern void *\nsafe_buddy_alloc(size_t size);\nextern void\nsafe_buddy_free(void *ptr);\nextern int\nbuddy_search_for_pointer(void *ptr, buddy_search_context_t context);\n\nstatic int\nbuddy_sizeofblock(void *pointer)\n{\n    // We get the pointer (address) as the parameter and look for any allocated block that starts at this address.\n    // If it is allocated, it will be found and its size will be returned.\n    // If it is currently non allocated, buddy_sizeofblock will do nothing.\n    struct _buddy_search_context_t dummy;\n    int index = buddy_search_for_pointer(pointer, &dummy);\n\n    if (index == -1) {\n        return -1;\n    }\n\n    return 1 << (12 - index);\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nbuddy_realloc(void *ptr, size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = ptr;\n    if (ptr == NULL) { // if ptr == NULL, then buddy_realloc must behave as buddy_alloc\n        result = safe_buddy_alloc(size);\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n        return result; //\n    }\n\n    if (size == 0) { // if size == 0 and ptr != NULL, then buddy_realloc behaves as buddy_free\n        safe_buddy_free(ptr); //\n        ATOMIC_BIT_RELEASE(__buddy_lock); //\n        return ptr; //\n    }\n\n    size_t size_block = buddy_sizeofblock(ptr);\n\n    if (size_block == ((size_t)-1)) { // size_block is set to -1 if ptr was not found among\n        ATOMIC_BIT_RELEASE(__buddy_lock); // allocated pointers and that there is nothing to do\n        return NULL;\n    }\n\n    if (size <= (size_block >> 1)) { // if newly allocated block is smaller than the currently allocated block\n        size_block = size; // we will only copy \"size\" bytes\n    } else if (size <= size_block) { // if newly allocated block is of the same size as the currently allocated block\n        ATOMIC_BIT_RELEASE(__buddy_lock); // then there is no reason to do anything\n        return ptr;\n    }\n\n    safe_buddy_free(ptr); // newly allocated block is either bigger or smaller than the currently allocated\n    result = safe_buddy_alloc(size); // block and we need to call buddy_alloc to be sure that external fragmentation\n    memcpy(result, ptr, size_block); // is avoided.\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/built_ins.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef BUILT_INS_H\n#define BUILT_INS_H\n\n/**\n * @file built_ins.h\n * @brief Provides access to the built-in functions\n *\n * Automatically generated by the DPU assembler\n */\n\n#define __builtin_nor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rri(rc, ra, shift) __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zri(zero, ra, shift) __asm__(\"lsr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrr(zero, ra, rb) __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_boot_rici(ra, imm, boot_cc, pc) __asm__(\"boot %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_erii(endian, ra, off, imm) __asm__(\"sb \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_esii(endian, sa, off, imm) __asm__(\"sb \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsl_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rri(rc, ra, shift) __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zri(zero, ra, shift) __asm__(\"lsl %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrr(zero, ra, rb) __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sw_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_erii(endian, ra, off, imm) __asm__(\"sw \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_esii(endian, sa, off, imm) __asm__(\"sw \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_asr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rri(rc, ra, imm) __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zri(zero, rb, imm) __asm__(\"addc %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrici(rc, ra, imm, add_nz_cc, pc)                                                                         \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrici(zero, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                          \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrr(zero, ra, rb) __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_u_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_u_rr(dc, rb) __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_s_rci(dc, true_cc, pc) __asm__(\"time.s %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_s_r(dc) __asm__(\"time.s %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_call_rri(rc, ra, off) __asm__(\"call %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_zri(zero, ra, off) __asm__(\"call %[zero], %[ra_r32], \" off \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"call %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_call_zrr(zero, ra, rb) __asm__(\"call %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zri(zero, ra, shift) __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrr(zero, ra, rb) __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_stop_ci(boot_cc, pc) __asm__(\"stop \" boot_cc \", \" pc \"\" :::)\n\n#define __builtin_ldmai_rri(ra, rb, immDma)                                                                                      \\\n    __asm__(\"ldmai %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_rrci(rc, rb, true_cc, pc)                                                                             \\\n    __asm__(\"time_cfg %[rc_wr32], %[rb_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zrci(zero, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg %[zero], %[rb_wr32], \" true_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_rr(rc, rb) __asm__(\"time_cfg %[rc_wr32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zr(zero, rb) __asm__(\"time_cfg %[zero], %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rri(rc, ra, imm) __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zri(zero, rb, imm) __asm__(\"or %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrici(rc, ra, imm, log_nz_cc, pc)                                                                           \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrici(zero, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rric(rc, ra, imm, log_set_cc)                                                                               \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zric(zero, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrif(rc, ra, imm, false_cc)                                                                                 \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrif(zero, ra, imm, false_cc) __asm__(\"or %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                            \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrrc(rc, ra, rb, log_set_cc)                                                                                \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrrc(zero, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrr(rc, ra, rb)                                                                                             \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrr(zero, ra, rb) __asm__(\"or %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cao_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rr(dc, ra) __asm__(\"cao.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zri(zero, ra, shift) __asm__(\"lsrx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrr(zero, ra, rb) __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rr(dc, ra) __asm__(\"cls.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sd_erir(endian, ra, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[ra_r32], \" off \", %[db_wr64]\" ::[ra_r32] \"r\"(ra), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_erii(endian, ra, off, imm) __asm__(\"sd \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sd_esir(endian, sa, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[sa_r32], \" off \", %[db_wr64]\" ::[sa_r32] \"r\"(sa), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_esii(endian, sa, off, imm) __asm__(\"sd \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsrx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sdma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"sdma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zri(zero, ra, shift) __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_zrr(zero, ra, rb) __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_time_u_rci(dc, true_cc, pc) __asm__(\"time.u %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_u_r(dc) __asm__(\"time.u %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_subc_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rr(dc, ra) __asm__(\"clo.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_zrr(zero, ra, rb) __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrr(zero, ra, rb) __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rir(rc, imm, ra) __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zir(zero, imm, rb) __asm__(\"sub %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirc(rc, imm, ra, sub_set_cc)                                                                              \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirc(zero, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirf(rc, imm, ra, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirf(zero, imm, ra, false_cc) __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rric(rc, ra, imm, ext_sub_set_cc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zric(zero, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrif(zero, ra, imm, false_cc) __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_ssi(sc, sa, imm) __asm__(\"sub %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sub_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"sub %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_sub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                          \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_zrr(zero, ra, rb) __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsb_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrc(zero, ra, log_set_cc) __asm__(\"extsb %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rr(rc, ra) __asm__(\"extsb %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zr(zero, ra) __asm__(\"extsb %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_movd_rrci(dc, db, true_false_cc, pc)                                                                           \\\n    __asm__(\"movd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_lsl1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zri(zero, ra, shift) __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_zrr(zero, ra, rb) __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rr(dc, ra) __asm__(\"sats.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rri(rc, ra, imm) __asm__(\"and %[rc_wr32], %[ra_wr32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_wr32] \"r\"(ra) :)\n\n#define __builtin_and_zri(zero, rb, imm) __asm__(\"and %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrif(zero, ra, imm, false_cc) __asm__(\"and %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrr(zero, ra, rb) __asm__(\"and %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrc(zero, ra, log_set_cc) __asm__(\"cls %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rr(rc, ra) __asm__(\"cls %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zr(zero, ra) __asm__(\"cls %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrrc(rc, ra, rb, sub_set_cc)                                                                              \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrrc(zero, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrr(zero, ra, rb) __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_div_step_rrrici(dc, ra, db, shift, div_cc, pc)                                                                 \\\n    __asm__(\"div_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" div_cc \", \" pc \"\"                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_rol_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rri(rc, ra, shift) __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zri(zero, ra, shift) __asm__(\"rol %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrr(zero, ra, rb) __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_swapd_rrci(dc, db, true_false_cc, pc)                                                                          \\\n    __asm__(\"swapd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_add_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrr(zero, ra, rb) __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_s_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_id_erii(endian, ra, off, imm) __asm__(\"sb_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rki(dc, ra, imm) __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nop_() __asm__(\"nop \" :::)\n\n#define __builtin_sd_id_erii(endian, ra, off, imm) __asm__(\"sd_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_id_erii(endian, ra, off, imm) __asm__(\"sh_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrc(zero, ra, log_set_cc) __asm__(\"extsh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rr(rc, ra) __asm__(\"extsh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zr(zero, ra) __asm__(\"extsh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_acquire_rici(ra, imm, acquire_cc, pc)                                                                          \\\n    __asm__(\"acquire %[ra_r32], \" imm \", \" acquire_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rri(rc, ra, imm) __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zri(zero, rb, imm) __asm__(\"xor %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrif(zero, ra, imm, false_cc) __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrr(zero, ra, rb) __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zri(zero, ra, shift) __asm__(\"lslx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrr(zero, ra, rb) __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrr(zero, ra, rb) __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rr(dc, ra) __asm__(\"clo.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rr(dc, ra) __asm__(\"extsh.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rri(rc, ra, shift) __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zri(zero, ra, shift) __asm__(\"ror %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrr(zero, ra, rb) __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_fault_i(imm) __asm__(\"fault \" imm \"\" :::)\n\n#define __builtin_clz_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rr(dc, ra) __asm__(\"clz.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rri(dc, rb, imm) __asm__(\"or.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_s_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sats_rrci(rc, ra, log_nz_cc, pc)                                                                               \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrci(zero, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rrc(rc, ra, log_set_cc)                                                                                   \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrc(zero, ra, log_set_cc) __asm__(\"sats %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rr(rc, ra) __asm__(\"sats %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zr(zero, ra) __asm__(\"sats %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_erri(endian, rc, ra, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lw_ersi(endian, rc, sa, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extsb_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rr(dc, ra) __asm__(\"extsb.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rr(dc, rb) __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrc(zero, ra, log_set_cc) __asm__(\"cao %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rr(rc, ra) __asm__(\"cao %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zr(zero, ra) __asm__(\"cao %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrc(zero, ra, log_set_cc) __asm__(\"extuh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rr(rc, ra) __asm__(\"extuh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zr(zero, ra) __asm__(\"extuh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_u_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rki(dc, ra, imm) __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrif(zero, ra, imm, false_cc) __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrr(zero, ra, rb) __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrc(zero, ra, log_set_cc) __asm__(\"clo %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rr(rc, ra) __asm__(\"clo %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zr(zero, ra) __asm__(\"clo %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extub_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrc(zero, ra, log_set_cc) __asm__(\"extub %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rr(rc, ra) __asm__(\"extub %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zr(zero, ra) __asm__(\"extub %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_id_erii(endian, ra, off, imm) __asm__(\"sw_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_rci(rc, true_cc, pc) __asm__(\"time %[rc_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_zci(zero, true_cc, pc) __asm__(\"time %[zero], \" true_cc \", \" pc \"\" :::)\n\n#define __builtin_time_r(rc) __asm__(\"time %[rc_wr32]\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_z(zero) __asm__(\"time %[zero]\" :::)\n\n#define __builtin_asr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rri(rc, ra, shift) __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zri(zero, ra, shift) __asm__(\"asr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrr(zero, ra, rb) __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ldma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"ldma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ld_erri(endian, dc, ra, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ld_ersi(endian, dc, sa, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[sa_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cls_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rr(dc, ra) __asm__(\"cls.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rr(dc, ra) __asm__(\"extuh.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rr(dc, ra) __asm__(\"sats.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_resume_rici(ra, imm, boot_cc, pc) __asm__(\"resume %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cao_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rr(dc, ra) __asm__(\"cao.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rr(dc, ra) __asm__(\"clz.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zri(zero, ra, shift) __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrr(zero, ra, rb) __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrc(rc, ra, rb, sub_set_cc)                                                                             \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrc(zero, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_zrr(zero, ra, rb) __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rri(rc, ra, imm) __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zri(zero, rb, imm) __asm__(\"add %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrici(rc, ra, imm, add_nz_cc, pc)                                                                          \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrici(zero, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrif(zero, ra, imm, false_cc) __asm__(\"add %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_ssi(sc, sa, imm) __asm__(\"add %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_add_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                           \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrr(zero, ra, rb) __asm__(\"add %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"add %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_nor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrif(zero, ra, imm, false_cc) __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrr(zero, ra, rb) __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rri(dc, rb, imm) __asm__(\"or.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_u_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rir(rc, imm, ra) __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zir(zero, imm, rb) __asm__(\"subc %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirc(rc, imm, ra, sub_set_cc)                                                                             \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirc(zero, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirf(rc, imm, ra, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirf(zero, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rric(rc, ra, imm, ext_sub_set_cc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zric(zero, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                         \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_zrr(zero, ra, rb) __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extub_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rr(dc, ra) __asm__(\"extub.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrr(zero, ra, rb) __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_release_rici(ra, imm, release_cc, pc)                                                                          \\\n    __asm__(\"release %[ra_r32], \" imm \", \" release_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clz_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrc(zero, ra, log_set_cc) __asm__(\"clz %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rr(rc, ra) __asm__(\"clz %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zr(zero, ra) __asm__(\"clz %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_step_rrrici(dc, ra, db, shift, boot_cc, pc)                                                                \\\n    __asm__(\"mul_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" boot_cc \", \" pc \"\"                                         \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_sh_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_erii(endian, ra, off, imm) __asm__(\"sh \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_esii(endian, sa, off, imm) __asm__(\"sh \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lbu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#endif /* BUILT_INS_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/clzdi2.c",
    "content": "/* ===-- clzdi2.c - Implement __clzdi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.high == 0);\n    return __builtin_clz((x.s.high & ~f) | (x.s.low & f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/clzsi2.c",
    "content": "/* ===-- clzsi2.c - Implement __clzsi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0xFFFF0000) == 0) << 4; /* if (x is small) t = 16 else 0 */\n    x >>= 16 - t; /* x = [0 - 0xFFFF] */\n    su_int r = t; /* r = [0, 16] */\n    /* return r + clz(x) */\n    t = ((x & 0xFF00) == 0) << 3;\n    x >>= 8 - t; /* x = [0 - 0xFF] */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + clz(x) */\n    t = ((x & 0xF0) == 0) << 2;\n    x >>= 4 - t; /* x = [0 - 0xF] */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + clz(x) */\n    t = ((x & 0xC) == 0) << 1;\n    x >>= 2 - t; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + clz(x) */\n    /*     switch (x)\n     *     {\n     *     case 0:\n     *         return r + 2;\n     *     case 1:\n     *         return r + 1;\n     *     case 2:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - x) & -((x & 2) == 0));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/cmpdi2.c",
    "content": "/* ===-- cmpdi2.c - Implement __cmpdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __cmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__cmpdi2(di_int a, di_int b)\n{\n    dwords x;\n    x.all = a;\n    dwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_lcmp(di_int a, di_int b)\n{\n    return __cmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/comparedf2.c",
    "content": "//===-- lib/comparedf2.c - Double-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// // This file implements the following soft-float comparison routines:\n//\n//   __eqdf2   __gedf2   __unorddf2\n//   __ledf2   __gtdf2\n//   __ltdf2\n//   __nedf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __ledf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gedf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unorddf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __ledf2( ) and __gedf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ledf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a floating-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpdf2, __ledf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gedf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unorddf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nedf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtdf2(fp_t a, fp_t b)\n{\n    return __gedf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_dcmpun(fp_t a, fp_t b)\n{\n    return __unorddf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/comparesf2.c",
    "content": "//===-- lib/comparesf2.c - Single-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements the following soft-fp_t comparison routines:\n//\n//   __eqsf2   __gesf2   __unordsf2\n//   __lesf2   __gtsf2\n//   __ltsf2\n//   __nesf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __lesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unordsf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__lesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a fp_ting-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpsf2, __lesf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unordsf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nesf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtsf2(fp_t a, fp_t b)\n{\n    return __gesf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_fcmpun(fp_t a, fp_t b)\n{\n    return __unordsf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ctzdi2.c",
    "content": "/* ===-- ctzdi2.c - Implement __ctzdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits  */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.low == 0);\n    return __builtin_ctz((x.s.high & f) | (x.s.low & ~f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ctzsi2.c",
    "content": "/* ===-- ctzsi2.c - Implement __ctzsi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0x0000FFFF) == 0) << 4; /* if (x has no small bits) t = 16 else 0 */\n    x >>= t; /* x = [0 - 0xFFFF] + higher garbage bits */\n    su_int r = t; /* r = [0, 16]  */\n    /* return r + ctz(x) */\n    t = ((x & 0x00FF) == 0) << 3;\n    x >>= t; /* x = [0 - 0xFF] + higher garbage bits */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + ctz(x) */\n    t = ((x & 0x0F) == 0) << 2;\n    x >>= t; /* x = [0 - 0xF] + higher garbage bits */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + ctz(x) */\n    t = ((x & 0x3) == 0) << 1;\n    x >>= t;\n    x &= 3; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + ctz(x) */\n\n    /*  The branch-less return statement below is equivalent\n     *  to the following switch statement:\n     *     switch (x)\n     *    {\n     *     case 0:\n     *         return r + 2;\n     *     case 2:\n     *         return r + 1;\n     *     case 1:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - (x >> 1)) & -((x & 1) == 0));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/defs.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nint\ncheck_stack()\n{\n    unsigned int stack_base, stack_size;\n    int stack_limit, remaining;\n    thread_id_t tid = me();\n\n    stack_base = __SP_TABLE__[tid].stack_ptr;\n    stack_size = __SP_TABLE__[tid].stack_size;\n    stack_limit = (int)(stack_base + stack_size);\n    __asm__ volatile(\"sub %[r], %[l], r22\" : [r] \"=r\"(remaining) : [l] \"r\"(stack_limit));\n\n    return remaining;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/defs.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEFS_H\n#define DPUSYSCORE_DEFS_H\n\n#include <sysdef.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n/**\n * @file defs.h\n * @brief Miscellaneous system functions.\n *\n * General purpose definitions.\n */\n\n#if __STDC_VERSION__ >= 201112L\n#define __ATTRIBUTE_NO_RETURN__ _Noreturn\n#else\n#define __ATTRIBUTE_NO_RETURN__\n#endif /* __STDC_VERSION__ */\n\n/**\n * @fn me\n * @internal This just returns the value of the special register id.\n * @return The current tasklet's sysname.\n */\nstatic inline sysname_t\nme()\n{\n    return __builtin_dpu_tid();\n}\n\n/**\n * @fn halt\n * @brief Halts the DPU.\n * @throws FAULT_HALT always\n */\n__ATTRIBUTE_NO_RETURN__ static inline void\nhalt()\n{\n    __builtin_trap();\n    __builtin_unreachable();\n}\n\n/**\n * @fn check_stack\n * @return the number of unused 32-bits words in the current runtime's stack.\n *         If the number is negative, it indicates by how much 32-bits words the stack overflowed.\n *\n * @internal This fetches the position of the next stack in memory from the Stack Pointer Table (cf. tasklet.h)\n *           and compute the remaining bytes.\n */\nint\ncheck_stack();\n\n#endif /* DPUSYSCORE_DEFS_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/devprivate.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEVPRIVATE_H\n#define DPUSYSCORE_DEVPRIVATE_H\n\n/**\n * @file devprivate.h\n * @brief Reserved for internal use ... please do not use those functions unless you know exactly what you do.\n */\n\n/**\n * @def tell\n * @brief On a simulator, injects a tell instruction to print out developer debug info.\n * @nolink\n *\n * @warning This function will not work on a target different from simulator.\n *\n * @param reg a register\n * @param val a constant value\n */\n#define tell(reg, val) __asm__(\"tell %[r], \" val : : [r] \"r\"(reg) :)\n\n#endif /* DPUSYSCORE_DEVPRIVATE_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/div32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __udiv32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"  clz r3, r1, max, __udiv32_division_by_zero\\n\" // r3 = by how many the divider can be shifted on 32-bit\n                     \"  clz r4, r0\\n\" // r4 = number of useless bits of the dividend\n                     \"  sub r3, r4, r3, gtu, __udiv32_result_0\\n\" // r3 = the maximal shift to be done\n                     \"  move r4, r1\\n\"\n                     \"  move.u d0, r0\\n\"\n                     \"  jump r3, __udiv32_base\\n\" // As we will jump backward relatively to __udiv32_base\n                     \"  div_step d0, r4, d0, 31\\n\"\n                     \"  div_step d0, r4, d0, 30\\n\"\n                     \"  div_step d0, r4, d0, 29\\n\"\n                     \"  div_step d0, r4, d0, 28\\n\"\n                     \"  div_step d0, r4, d0, 27\\n\"\n                     \"  div_step d0, r4, d0, 26\\n\"\n                     \"  div_step d0, r4, d0, 25\\n\"\n                     \"  div_step d0, r4, d0, 24\\n\"\n                     \"  div_step d0, r4, d0, 23\\n\"\n                     \"  div_step d0, r4, d0, 22\\n\"\n                     \"  div_step d0, r4, d0, 21\\n\"\n                     \"  div_step d0, r4, d0, 20\\n\"\n                     \"  div_step d0, r4, d0, 19\\n\"\n                     \"  div_step d0, r4, d0, 18\\n\"\n                     \"  div_step d0, r4, d0, 17\\n\"\n                     \"  div_step d0, r4, d0, 16\\n\"\n                     \"  div_step d0, r4, d0, 15\\n\"\n                     \"  div_step d0, r4, d0, 14\\n\"\n                     \"  div_step d0, r4, d0, 13\\n\"\n                     \"  div_step d0, r4, d0, 12\\n\"\n                     \"  div_step d0, r4, d0, 11\\n\"\n                     \"  div_step d0, r4, d0, 10\\n\"\n                     \"  div_step d0, r4, d0, 9\\n\"\n                     \"  div_step d0, r4, d0, 8\\n\"\n                     \"  div_step d0, r4, d0, 7\\n\"\n                     \"  div_step d0, r4, d0, 6\\n\"\n                     \"  div_step d0, r4, d0, 5\\n\"\n                     \"  div_step d0, r4, d0, 4\\n\"\n                     \"  div_step d0, r4, d0, 3\\n\"\n                     \"  div_step d0, r4, d0, 2\\n\"\n                     \"  div_step d0, r4, d0, 1\\n\"\n                     \"__udiv32_base:\\n\"\n                     \"  div_step d0, r4, d0, 0\\n\"\n                     \"__udiv32_exit:\\n\"\n                     \"  jump r23\\n\"\n                     \"__udiv32_result_0:\\n\"\n                     \"  move.u d0, r0, true, __udiv32_exit\\n\"\n                     \"__udiv32_division_by_zero:\\n\"\n                     \"  fault \"__STR(__FAULT_DIVISION_BY_ZERO__));\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __div32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"sd r22, 0, d22\\n\"\n                     \"add r22, r22, 8\\n\"\n                     // The quotient's sign depends on the sign of the dividend and divider... After few tries it sounds\n                     // like the quickest way to select the operators is to branch according to the cases.\n                     \"  clo r3, r0, z, __div32_pos_dividend\\n\"\n                     \"  clo r3, r1, z, __div32_neg_dividend_pos_divider\\n\"\n                     \"__div32_neg_dividend_neg_divider:\\n\" // As a result, the quotient is positive and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1, true, __div32_exit\\n\"\n                     \"__div32_neg_dividend_pos_divider:\\n\" // As a result, the quotient is negative and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend:\\n\"\n                     \"  clo r3, r1, z, __div32_pos_dividend_pos_divider\\n\"\n                     \"  neg r1, r1\\n\" // As a result, the quotient is negative and the remainder positive\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend_pos_divider:\\n\" // The dividend and divider are both positive\n                     \"  call r23, __udiv32\\n\"\n                     \"__div32_exit:\\n\"\n                     \"  ld d22, r22, -8\\n\"\n                     \"  jump r23\\n\");\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/divdf3.c",
    "content": "//===-- lib/divdf3.c - Double-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divdf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    const uint32_t q31b = bSignificand >> 21;\n    uint32_t recip32 = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction32;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n\n    // recip32 might have overflowed to exactly zero in the preceding\n    // computation if the high word of b is exactly 1.0.  This would sabotage\n    // the full-width final stage of the computation that follows, so we adjust\n    // recip32 downward by one bit.\n    recip32--;\n\n    // We need to perform one more iteration to get us to 56 binary digits;\n    // The last iteration needs to happen with extra precision.\n    const uint32_t q63blo = bSignificand << 11;\n    uint64_t correction, reciprocal;\n    correction = -((uint64_t)recip32 * q31b + ((uint64_t)recip32 * q63blo >> 32));\n    uint32_t cHi = correction >> 32;\n    uint32_t cLo = correction;\n    reciprocal = (uint64_t)recip32 * cHi + ((uint64_t)recip32 * cLo >> 32);\n\n    // We already adjusted the 32-bit estimate, now we need to adjust the final\n    // 64-bit reciprocal estimate downward to ensure that it is strictly smaller\n    // than the infinitely precise exact reciprocal.  Because the computation\n    // of the Newton-Raphson step is truncating at every step, this adjustment\n    // is small; most of the work is already done.\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-56, lies in the\n    // interval [0.5, 1.0), and is strictly smaller than the true reciprocal\n    // of b.  Multiplying a by this reciprocal thus gives a numerical q = a/b\n    // in Q53 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0.5, 2.0)\n    //    3. the error in q is bounded away from 2^-53 (actually, we have a\n    //       couple of bits to spare, but this is all we need).\n\n    // We need a 64 x 64 multiply high to compute q, which isn't a basic\n    // operation in C, so we need to be a little bit fussy.\n    rep_t quotient, quotientLo;\n    wideMultiply(aSignificand << 2, reciprocal, &quotient, &quotientLo);\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 53) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 52) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        const double result = fromRep(absResult | quotientSign);\n        return result;\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ddiv(fp_t a, fp_t b)\n{\n    return __divdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/divdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__divdi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 0);\n        } else {\n            return -__udiv64(dividend, -divider, 0);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 0);\n    } else {\n        // Negative dividend, negative divider\n        return __udiv64(-dividend, -divider, 0);\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/divmodsi4.c",
    "content": "/*===-- divmodsi4.c - Implement __divmodsi4 --------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__divmodsi4(si_int a, si_int b, si_int *rem)\n{\n    long res = __div32(a, b);\n    *rem = (int)res;\n    return (int)(res >> 32);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/divsf3.c",
    "content": "//===-- lib/divsf3.c - Single-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divsf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    uint32_t q31b = bSignificand << 8;\n    uint32_t reciprocal = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n\n    // Exhaustive testing shows that the error in reciprocal after three steps\n    // is in the interval [-0x1.f58108p-31, 0x1.d0e48cp-29], in line with our\n    // expectations.  We bump the reciprocal by a tiny value to force the error\n    // to be strictly positive (in the range [0x1.4fdfp-37,0x1.287246p-29], to\n    // be specific).  This also causes 1/1 to give a sensible approximation\n    // instead of zero (due to overflow).\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-28, lies in the\n    // interval [0x1.000000eep-1, 0x1.fffffffcp-1], and is strictly smaller\n    // than the true reciprocal of b.  Multiplying a by this reciprocal thus\n    // gives a numerical q = a/b in Q24 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0x1.000000eep-1, 0x1.fffffffcp0)\n    //    3. the error in q is at most 2^-24 + 2^-27 -- the 2^24 term comes\n    //       from the fact that we truncate the product, and the 2^27 term\n    //       is the error in the reciprocal of b scaled by the maximum\n    //       possible value of a.  As a consequence of this error bound,\n    //       either q or nextafter(q) is the correctly rounded\n    rep_t quotient = (uint64_t)reciprocal * (aSignificand << 1) >> 32;\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 24) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 23) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        return fromRep(absResult | quotientSign);\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fdiv(fp_t a, fp_t b)\n{\n    return __divsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/divsi3.c",
    "content": "/* ===-- divsi3.c - Implement __divsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b)\n{\n    const int bits_in_word_m1 = (int)(sizeof(si_int) * CHAR_BIT) - 1;\n    si_int s_a = a >> bits_in_word_m1; /* s_a = a < 0 ? -1 : 0 */\n    si_int s_b = b >> bits_in_word_m1; /* s_b = b < 0 ? -1 : 0 */\n    a = (a ^ s_a) - s_a; /* negate if s_a == -1 */\n    b = (b ^ s_b) - s_b; /* negate if s_b == -1 */\n    s_a ^= s_b; /* sign of quotient */\n    /*\n     * On CPUs without unsigned hardware division support,\n     *  this calls __udivsi3 (notice the cast to su_int).\n     * On CPUs with unsigned hardware division support,\n     *  this uses the unsigned division instruction.\n     */\n    return ((su_int)a / (su_int)b ^ s_a) - s_a; /* negate if s_a == -1 */\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_idiv(si_int a, si_int b)\n{\n    return __divsi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/dpuconst.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUCONST_H\n#define DPUSYSCORE_DPUCONST_H\n\n#define __DPU_NUMBER_OF_THREADS 24\n#define __DPU_MRAM_SIZE_LOG2 26\n\n#endif /* DPUSYSCORE_DPUCONST_H */"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/dpufault.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUFAULT_H\n#define DPUSYSCORE_DPUFAULT_H\n\n// A list of \"fault codes\"\n#define __FAULT_ALLOC_HEAP_FULL__ 1\n#define __FAULT_DIVISION_BY_ZERO__ 2\n#define __FAULT_ASSERT_FAILED__ 3\n// Used in the compiler to implement a trap\n#define __FAULT_HALT__ 4\n#define __FAULT_PRINTF_OVERFLOW__ 5\n#define __FAULT_ALREADY_PROFILING__ 6\n#define __FAULT_NOT_PROFILING__ 7\n\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/dpuruntime.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPURUNTIME_H\n#define DPUSYSCORE_DPURUNTIME_H\n\n#include <built_ins.h>\n#include <dpuconst.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <stdint.h>\n\n// todo fix: This file should not be included by another syslib header file, only by source files (conflicting definitions).\n\n#define __INITIAL_HEAP_POINTER __sys_heap_pointer_reset\n#define __HEAP_POINTER __sys_heap_pointer\n#define __WAIT_QUEUE_TABLE __sys_wq_table\n#define __SP_TABLE__ __sys_thread_stack_table_ptr\n#define __STDOUT_BUFFER_STATE __stdout_buffer_state\n\n/* The order needs to match the __bootstrap function expectation */\ntypedef struct {\n    uint32_t stack_size;\n    uint32_t stack_ptr;\n} thread_stack_t;\n\nextern unsigned int __INITIAL_HEAP_POINTER;\nextern volatile unsigned int __HEAP_POINTER;\nextern unsigned char __WAIT_QUEUE_TABLE[];\nextern thread_stack_t __SP_TABLE__[];\n\n#define __acquire(base, off) __builtin_acquire_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __release(base, off, at) __builtin_release_rici(base, off, \"nz\", at)\n\n#define __resume(base, off) __builtin_resume_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __stop() __builtin_stop_ci(\"false\", \"0\")\n#define __stop_at(label) __builtin_stop_ci(\"true\", label)\n\n#define likely(x) __builtin_expect((x), 1)\n#define unlikely(x) __builtin_expect((x), 0)\n#define unreachable() __builtin_unreachable()\n\n#define count_leading_zeros(x) __builtin_clz(x)\n#define count_population(x) __builtin_popcount(x)\n\n#define __EMPTY_WAIT_QUEUE 0xFF\n\n#define __AT_THIS_INSTRUCTION \".+0\"\n#define __AT_NEXT_INSTRUCTION \".+1\"\n\n// Use this macro at the beginning of an assembly function in order to get profiled.\n#ifdef DPU_PROFILING\n#define __ADD_PROFILING_ENTRY__ \"call r23, mcount\\n\"\n#else\n#define __ADD_PROFILING_ENTRY__ \"\\n\"\n#endif\n\n#ifdef DPU_PROFILING\n/* Reset counter + count cycles */\n#define __CONFIG_PERFCOUNTER_ENTRY__                                                                                             \\\n    \"  move r23, 3\\n\"                                                                                                            \\\n    \"  time_cfg zero, r23\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__                                                                                               \\\n    \"  time r23\\n\"                                                                                                               \\\n    \"  sw zero, perfcounter_end_value, r23\\n\"\n#else\n#define __CONFIG_PERFCOUNTER_ENTRY__ \"\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__ \"\\n\"\n#endif\n\n#endif /* DPUSYSCORE_DPURUNTIME_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/extendhfsf2.c",
    "content": "//===-- lib/extendhfsf2.c - half -> single conversion -------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_HALF\n#define DST_SINGLE\n#include \"fp_extend_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE float\n__extendhfsf2(uint16_t a)\n{\n    return __extendXfYf2__(a);\n}\n\nCOMPILER_RT_ABI float\n__gnu_h2f_ieee(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_h2f(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/extendsfdf2.c",
    "content": "//===-- lib/extendsfdf2.c - single -> double conversion -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_SINGLE\n#define DST_DOUBLE\n#include \"fp_extend_impl.inc\"\n\nCOMPILER_RT_ABI double\n__extendsfdf2(float a)\n{\n    return __extendXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_f2d(float a)\n{\n    return __extendsfdf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ffsdi2.c",
    "content": "/* ===-- ffsdi2.c - Implement __ffsdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctz(x.s.high) + (1 + sizeof(si_int) * CHAR_BIT);\n    }\n    return __builtin_ctz(x.s.low) + 1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ffssi2.c",
    "content": "/* ===-- ffssi2.c - Implement __ffssi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffssi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffssi2(si_int a)\n{\n    if (a == 0) {\n        return 0;\n    }\n    return __builtin_ctz(a) + 1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ffsti2.c",
    "content": "/* ===-- ffsti2.c - Implement __ffsti2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsti2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n#ifdef CRT_HAS_128BIT\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsti2(ti_int a)\n{\n    twords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctzll(x.s.high) + (1 + sizeof(di_int) * CHAR_BIT);\n    }\n    return __builtin_ctzll(x.s.low) + 1;\n}\n\n#endif /* CRT_HAS_128BIT */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixdfdi.c",
    "content": "/* ===-- fixdfdi.c - Implement __fixdfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a);\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(double a)\n{\n    if (a < 0.0) {\n        return -__fixunsdfdi(-a);\n    }\n    return __fixunsdfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_d2lz(fp_t a)\n{\n#else\n__aeabi_d2lz(double a)\n{\n#endif\n    return __fixdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixdfsi.c",
    "content": "/* ===-- fixdfsi.c - Implement __fixdfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixdfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_d2iz(fp_t a)\n{\n    return __fixdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixsfdi.c",
    "content": "/* ===-- fixsfdi.c - Implement __fixsfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a);\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(float a)\n{\n    if (a < 0.0f) {\n        return -__fixunssfdi(-a);\n    }\n    return __fixunssfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_f2lz(fp_t a)\n{\n#else\n__aeabi_f2lz(float a)\n{\n#endif\n    return __fixsfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixsfsi.c",
    "content": "/* ===-- fixsfsi.c - Implement __fixsfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixsfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_f2iz(fp_t a)\n{\n    return __fixsfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixunsdfdi.c",
    "content": "/* ===-- fixunsdfdi.c - Implement __fixunsdfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a)\n{\n    if (a <= 0.0)\n        return 0;\n    su_int high = a / 4294967296.f; /* a / 0x1p32f; */\n    su_int low = a - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_d2ulz(fp_t a)\n{\n#else\n__aeabi_d2ulz(double a)\n{\n#endif\n    return __fixunsdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixunsdfsi.c",
    "content": "/* ===-- fixunsdfsi.c - Implement __fixunsdfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunsdfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_d2uiz(fp_t a)\n{\n    return __fixunsdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixunssfdi.c",
    "content": "/* ===-- fixunssfdi.c - Implement __fixunssfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a)\n{\n    if (a <= 0.0f)\n        return 0;\n    double da = a;\n    su_int high = da / 4294967296.f; /* da / 0x1p32f; */\n    su_int low = da - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_f2ulz(fp_t a)\n{\n#else\n__aeabi_f2ulz(float a)\n{\n#endif\n    return __fixunssfdi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fixunssfsi.c",
    "content": "/* ===-- fixunssfsi.c - Implement __fixunssfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __fixunssfsi for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunssfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_f2uiz(fp_t a)\n{\n    return __fixunssfsi(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/float.h",
    "content": "/*===---- float.h - Characteristics of floating point types ----------------===\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __FLOAT_H\n#define __FLOAT_H\n\n/**\n * @file float.h\n */\n\n/* Characteristics of floating point types, C99 5.2.4.2.2 */\n\n#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__\n#define FLT_ROUNDS (__builtin_flt_rounds())\n#define FLT_RADIX __FLT_RADIX__\n\n#define FLT_MANT_DIG __FLT_MANT_DIG__\n#define DBL_MANT_DIG __DBL_MANT_DIG__\n#define LDBL_MANT_DIG __LDBL_MANT_DIG__\n\n#if __STDC_VERSION__ >= 199901L || !defined(__STRICT_ANSI__)\n#define DECIMAL_DIG __DECIMAL_DIG__\n#endif\n\n#define FLT_DIG __FLT_DIG__\n#define DBL_DIG __DBL_DIG__\n#define LDBL_DIG __LDBL_DIG__\n\n#define FLT_MIN_EXP __FLT_MIN_EXP__\n#define DBL_MIN_EXP __DBL_MIN_EXP__\n#define LDBL_MIN_EXP __LDBL_MIN_EXP__\n\n#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__\n#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__\n#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__\n\n#define FLT_MAX_EXP __FLT_MAX_EXP__\n#define DBL_MAX_EXP __DBL_MAX_EXP__\n#define LDBL_MAX_EXP __LDBL_MAX_EXP__\n\n#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__\n#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__\n#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__\n\n#define FLT_MAX __FLT_MAX__\n#define DBL_MAX __DBL_MAX__\n#define LDBL_MAX __LDBL_MAX__\n\n#define FLT_EPSILON __FLT_EPSILON__\n#define DBL_EPSILON __DBL_EPSILON__\n#define LDBL_EPSILON __LDBL_EPSILON__\n\n#define FLT_MIN __FLT_MIN__\n#define DBL_MIN __DBL_MIN__\n#define LDBL_MIN __LDBL_MIN__\n\n#define FLT_HAS_SUBNORM (-1)\n#define DBL_HAS_SUBNORM (-1)\n#define LDBL_HAS_SUBNORM (-1)\n#define DBL_FLT_HAS_SUBNORM (-1)\n#define LDBL_FLT_HAS_SUBNORM (-1)\n\n#if __STDC_VERSION__ >= 201112L || !defined(__STRICT_ANSI__)\n#define FLT_TRUE_MIN __FLT_DENORM_MIN__\n#define DBL_TRUE_MIN __DBL_DENORM_MIN__\n#define LDBL_TRUE_MIN __LDBL_DENORM_MIN__\n#define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__\n#define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__\n#define LDBL_DECIMAL_DIG __LDBL_DECIMAL_DIG__\n#endif\n\n#endif /* __FLOAT_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatdidf.c",
    "content": "/*===-- floatdidf.c - Implement __floatdidf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdidf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop32 = 4294967296.0; // 0x1.0p32\n\n    union {\n        int64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    const double high = (int32_t)(a >> 32) * twop32;\n    low.x |= a & INT64_C(0x00000000ffffffff);\n\n    const double result = (high - twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         * Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_l2d(di_int a)\n{\n    return __floatdidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatdisf.c",
    "content": "/*===-- floatdisf.c - Implement __floatdisf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even.*/\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatdisf(di_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_l2f(di_int a)\n{\n    return __floatdisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatsidf.c",
    "content": "//===-- lib/floatsidf.c - integer -> double-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsidf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.  Extra\n    // cast to unsigned int is necessary to get the correct behavior for\n    // the input INT_MIN.\n    const int shift = significandBits - exponent;\n    result = (rep_t)(unsigned int)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2d(int a)\n{\n    return __floatsidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatsisf.c",
    "content": "//===-- lib/floatsisf.c - integer -> single-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsisf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2f(int a)\n{\n    return __floatsisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatundidf.c",
    "content": "/* ===-- floatundidf.c - Implement __floatundidf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundidf for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             du_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop84 = 19342813113834066795298816.0; // 0x1.0p84\n    static const double twop84_plus_twop52 = 19342813118337666422669312.0; // 0x1.00000001p84\n\n    union {\n        uint64_t x;\n        double d;\n    } high = { .d = twop84 };\n    union {\n        uint64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    high.x |= a >> 32;\n    low.x |= a & UINT64_C(0x00000000ffffffff);\n\n    const double result = (high.d - twop84_plus_twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         *  Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low  */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_ul2d(du_int a)\n{\n    return __floatundidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatundisf.c",
    "content": "/*===-- floatundisf.c - Implement __floatundisf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even. */\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *            du_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatundisf(du_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* 8 exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_ul2f(du_int a)\n{\n    return __floatundisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatunsidf.c",
    "content": "//===-- lib/floatunsidf.c - uint -> double-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsidf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.\n    const int shift = significandBits - exponent;\n    result = (rep_t)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2d(unsigned int a)\n{\n    return __floatunsidf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/floatunsisf.c",
    "content": "//===-- lib/floatunsisf.c - uint -> single-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsisf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2f(unsigned int a)\n{\n    return __floatunsisf(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_add_impl.inc",
    "content": "//===----- lib/fp_add_impl.inc - floaing point addition -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float addition with the IEEE-754 default rounding\n// (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __addXf3__(fp_t a, fp_t b) {\n    rep_t aRep = toRep(a);\n    rep_t bRep = toRep(b);\n    const rep_t aAbs = aRep & absMask;\n    const rep_t bAbs = bRep & absMask;\n\n    // Detect if a or b is zero, infinity, or NaN.\n    if (aAbs - REP_C(1) >= infRep - REP_C(1) ||\n        bAbs - REP_C(1) >= infRep - REP_C(1)) {\n        // NaN + anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything + NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // +/-infinity + -/+infinity = qNaN\n            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);\n            // +/-infinity + anything remaining = +/- infinity\n            else return a;\n        }\n\n        // anything remaining + +/-infinity = +/-infinity\n        if (bAbs == infRep) return b;\n\n        // zero + anything = anything\n        if (!aAbs) {\n            // but we need to get the sign right for zero + zero\n            if (!bAbs) return fromRep(toRep(a) & toRep(b));\n            else return b;\n        }\n\n        // anything + zero = anything\n        if (!bAbs) return a;\n    }\n\n    // Swap a and b if necessary so that a has the larger absolute value.\n    if (bAbs > aAbs) {\n        const rep_t temp = aRep;\n        aRep = bRep;\n        bRep = temp;\n    }\n\n    // Extract the exponent and significand from the (possibly swapped) a and b.\n    int aExponent = aRep >> significandBits & maxExponent;\n    int bExponent = bRep >> significandBits & maxExponent;\n    rep_t aSignificand = aRep & significandMask;\n    rep_t bSignificand = bRep & significandMask;\n\n    // Normalize any denormals, and adjust the exponent accordingly.\n    if (aExponent == 0) aExponent = normalize(&aSignificand);\n    if (bExponent == 0) bExponent = normalize(&bSignificand);\n\n    // The sign of the result is the sign of the larger operand, a.  If they\n    // have opposite signs, we are performing a subtraction; otherwise addition.\n    const rep_t resultSign = aRep & signBit;\n    const bool subtraction = (aRep ^ bRep) & signBit;\n\n    // Shift the significands to give us round, guard and sticky, and or in the\n    // implicit significand bit.  (If we fell through from the denormal path it\n    // was already set by normalize( ), but setting it twice won't hurt\n    // anything.)\n    aSignificand = (aSignificand | implicitBit) << 3;\n    bSignificand = (bSignificand | implicitBit) << 3;\n\n    // Shift the significand of b by the difference in exponents, with a sticky\n    // bottom bit to get rounding correct.\n    const unsigned int align = aExponent - bExponent;\n    if (align) {\n        if (align < typeWidth) {\n            const bool sticky = bSignificand << (typeWidth - align);\n            bSignificand = bSignificand >> align | sticky;\n        } else {\n            bSignificand = 1; // sticky; b is known to be non-zero.\n        }\n    }\n    if (subtraction) {\n        aSignificand -= bSignificand;\n        // If a == -b, return +zero.\n        if (aSignificand == 0) return fromRep(0);\n\n        // If partial cancellation occured, we need to left-shift the result\n        // and adjust the exponent:\n        if (aSignificand < implicitBit << 3) {\n            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);\n            aSignificand <<= shift;\n            aExponent -= shift;\n        }\n    }\n    else /* addition */ {\n        aSignificand += bSignificand;\n\n        // If the addition carried up, we need to right-shift the result and\n        // adjust the exponent:\n        if (aSignificand & implicitBit << 4) {\n            const bool sticky = aSignificand & 1;\n            aSignificand = aSignificand >> 1 | sticky;\n            aExponent += 1;\n        }\n    }\n\n    // If we have overflowed the type, return +/- infinity:\n    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);\n\n    if (aExponent <= 0) {\n        // Result is denormal before rounding; the exponent is zero and we\n        // need to shift the significand.\n        const int shift = 1 - aExponent;\n        const bool sticky = aSignificand << (typeWidth - shift);\n        aSignificand = aSignificand >> shift | sticky;\n        aExponent = 0;\n    }\n\n    // Low three bits are round, guard, and sticky.\n    const int roundGuardSticky = aSignificand & 0x7;\n\n    // Shift the significand into place, and mask off the implicit bit.\n    rep_t result = aSignificand >> 3 & significandMask;\n\n    // Insert the exponent and sign.\n    result |= (rep_t)aExponent << significandBits;\n    result |= resultSign;\n\n    // Final rounding.  The result may overflow to infinity, but that is the\n    // correct result in that case.\n    if (roundGuardSticky > 0x4) result++;\n    if (roundGuardSticky == 0x4) result += result & 1;\n    return fromRep(result);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_extend.h",
    "content": "//===-lib/fp_extend.h - low precision -> high precision conversion -*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_EXTEND_HEADER\n#define FP_EXTEND_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n#define src_rep_t_clz __builtin_clz\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\nstatic __inline int\nsrc_rep_t_clz(src_rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#elif defined SRC_HALF\ntypedef uint16_t src_t;\ntypedef uint16_t src_rep_t;\n#define SRC_REP_C UINT16_C\nstatic const int srcSigBits = 10;\n#define src_rep_t_clz __builtin_clz\n\n#else\n#error Source should be half, single, or double precision!\n#endif // end source precision\n\n#if defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_QUAD\ntypedef long double dst_t;\ntypedef __uint128_t dst_rep_t;\n#define DST_REP_C (__uint128_t)\nstatic const int dstSigBits = 112;\n\n#else\n#error Destination should be single, double, or quad precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n// End helper routines.  Conversion implementation follows.\n\n#endif // FP_EXTEND_HEADER\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_extend_impl.inc",
    "content": "//=-lib/fp_extend_impl.inc - low precision -> high precision conversion -*-- -//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a narrower to a wider\n// IEEE-754 floating-point type.  The constants and types defined following the\n// includes below parameterize the conversion.\n//\n// It does not support types that don't use the usual IEEE-754 interchange\n// formats; specifically, some work would be needed to adapt it to\n// (for example) the Intel 80-bit format or PowerPC double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *widening* operations; if you need to convert to a *narrower* floating-point\n// type (e.g. double -> float), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.  You also may\n// run into trouble finding an appropriate CLZ function for wide source types;\n// you will likely need to roll your own on some platforms.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_extend.h\"\n\nstatic __inline dst_t __extendXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const dst_rep_t dstMinNormal = DST_REP_C(1) << dstSigBits;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    // If sizeof(src_rep_t) < sizeof(int), the subtraction result is promoted\n    // to (signed) int.  To avoid that, explicitly cast to src_rep_t.\n    if ((src_rep_t)(aAbs - srcMinNormal) < srcInfinity - srcMinNormal) {\n        // a is a normal number.\n        // Extend to the destination type by shifting the significand and\n        // exponent into the proper position and rebiasing the exponent.\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits);\n        absResult += (dst_rep_t)(dstExpBias - srcExpBias) << dstSigBits;\n    }\n\n    else if (aAbs >= srcInfinity) {\n        // a is NaN or infinity.\n        // Conjure the result by beginning with infinity, then setting the qNaN\n        // bit (if needed) and right-aligning the rest of the trailing NaN\n        // payload field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= (dst_rep_t)(aAbs & srcQNaN) << (dstSigBits - srcSigBits);\n        absResult |= (dst_rep_t)(aAbs & srcNaNCode) << (dstSigBits - srcSigBits);\n    }\n\n    else if (aAbs) {\n        // a is denormal.\n        // renormalize the significand and clear the leading bit, then insert\n        // the correct adjusted exponent in the destination type.\n        const int scale = src_rep_t_clz(aAbs) - src_rep_t_clz(srcMinNormal);\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits + scale);\n        absResult ^= dstMinNormal;\n        const int resultExponent = dstExpBias - srcExpBias - scale + 1;\n        absResult |= (dst_rep_t)resultExponent << dstSigBits;\n    }\n\n    else {\n        // a is zero.\n        absResult = 0;\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_fixint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixint_t __fixint(fp_t a) {\n    const fixint_t fixint_max = (fixint_t)((~(fixuint_t)0) / 2);\n    const fixint_t fixint_min = -fixint_max - 1;\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const fixint_t sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If exponent is negative, the result is zero.\n    if (exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixint_t) * CHAR_BIT)\n        return sign == 1 ? fixint_max : fixint_min;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return sign * (significand >> (significandBits - exponent));\n    else\n        return sign * ((fixint_t)significand << (exponent - significandBits));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_fixuint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to unsigned integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixuint_t __fixuint(fp_t a) {\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const int sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If either the value or the exponent is negative, the result is zero.\n    if (sign == -1 || exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixuint_t) * CHAR_BIT)\n        return ~(fixuint_t)0;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return significand >> (significandBits - exponent);\n    else\n        return (fixuint_t)significand << (exponent - significandBits);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_lib.h",
    "content": "//===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file is a configuration header for soft-float routines in compiler-rt.\n// This file does not provide any part of the compiler-rt interface, but defines\n// many useful constants and utility routines that are used in the\n// implementation of the soft-float routines in compiler-rt.\n//\n// Assumes that float, double and long double correspond to the IEEE-754\n// binary32, binary64 and binary 128 types, respectively, and that integer\n// endianness matches floating point endianness on the target platform.\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_LIB_HEADER\n#define FP_LIB_HEADER\n\n#include <stdint.h>\n#include <stdbool.h>\n#include <limits.h>\n#include \"int_lib.h\"\n\n// x86_64 FreeBSD prior v9.3 define fixed-width types incorrectly in\n// 32-bit mode.\n#if defined(__FreeBSD__) && defined(__i386__)\n#include <sys/param.h>\n#if __FreeBSD_version < 903000 // v9.3\n#define uint64_t unsigned long long\n#define int64_t long long\n#undef UINT64_C\n#define UINT64_C(c) (c##ULL)\n#endif\n#endif\n\n#if defined SINGLE_PRECISION\n\ntypedef uint32_t rep_t;\ntypedef int32_t srep_t;\ntypedef float fp_t;\n#define REP_C UINT32_C\n#define significandBits 23\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    return __builtin_clz(a);\n}\n\n// 32x32 --> 64 bit multiply\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    const uint64_t product = (uint64_t)a * b;\n    *hi = product >> 32;\n    *lo = product;\n}\nCOMPILER_RT_ABI fp_t\n__addsf3(fp_t a, fp_t b);\n\n#elif defined DOUBLE_PRECISION\n\ntypedef uint64_t rep_t;\ntypedef int64_t srep_t;\ntypedef double fp_t;\n#define REP_C UINT64_C\n#define significandBits 52\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#define loWord(a) (a & 0xffffffffU)\n#define hiWord(a) (a >> 32)\n\n// 64x64 -> 128 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    // Each of the component 32x32 -> 64 products\n    const uint64_t plolo = loWord(a) * loWord(b);\n    const uint64_t plohi = loWord(a) * hiWord(b);\n    const uint64_t philo = hiWord(a) * loWord(b);\n    const uint64_t phihi = hiWord(a) * hiWord(b);\n    // Sum terms that contribute to lo in a way that allows us to get the carry\n    const uint64_t r0 = loWord(plolo);\n    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);\n    *lo = r0 + (r1 << 32);\n    // Sum terms contributing to hi with the carry from lo\n    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;\n}\n#undef loWord\n#undef hiWord\n\nCOMPILER_RT_ABI fp_t\n__adddf3(fp_t a, fp_t b);\n\n#elif defined QUAD_PRECISION\n#if __LDBL_MANT_DIG__ == 113\n#define CRT_LDBL_128BIT\ntypedef __uint128_t rep_t;\ntypedef __int128_t srep_t;\ntypedef long double fp_t;\n#define REP_C (__uint128_t)\n// Note: Since there is no explicit way to tell compiler the constant is a\n// 128-bit integer, we let the constant be casted to 128-bit integer\n#define significandBits 112\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    const union {\n        __uint128_t ll;\n#if _YUGA_BIG_ENDIAN\n        struct {\n            uint64_t high, low;\n        } s;\n#else\n        struct {\n            uint64_t low, high;\n        } s;\n#endif\n    } uu = { .ll = a };\n\n    uint64_t word;\n    uint64_t add;\n\n    if (uu.s.high) {\n        word = uu.s.high;\n        add = 0;\n    } else {\n        word = uu.s.low;\n        add = 64;\n    }\n    return __builtin_clzll(word) + add;\n}\n\n#define Word_LoMask UINT64_C(0x00000000ffffffff)\n#define Word_HiMask UINT64_C(0xffffffff00000000)\n#define Word_FullMask UINT64_C(0xffffffffffffffff)\n#define Word_1(a) (uint64_t)((a >> 96) & Word_LoMask)\n#define Word_2(a) (uint64_t)((a >> 64) & Word_LoMask)\n#define Word_3(a) (uint64_t)((a >> 32) & Word_LoMask)\n#define Word_4(a) (uint64_t)(a & Word_LoMask)\n\n// 128x128 -> 256 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n\n    const uint64_t product11 = Word_1(a) * Word_1(b);\n    const uint64_t product12 = Word_1(a) * Word_2(b);\n    const uint64_t product13 = Word_1(a) * Word_3(b);\n    const uint64_t product14 = Word_1(a) * Word_4(b);\n    const uint64_t product21 = Word_2(a) * Word_1(b);\n    const uint64_t product22 = Word_2(a) * Word_2(b);\n    const uint64_t product23 = Word_2(a) * Word_3(b);\n    const uint64_t product24 = Word_2(a) * Word_4(b);\n    const uint64_t product31 = Word_3(a) * Word_1(b);\n    const uint64_t product32 = Word_3(a) * Word_2(b);\n    const uint64_t product33 = Word_3(a) * Word_3(b);\n    const uint64_t product34 = Word_3(a) * Word_4(b);\n    const uint64_t product41 = Word_4(a) * Word_1(b);\n    const uint64_t product42 = Word_4(a) * Word_2(b);\n    const uint64_t product43 = Word_4(a) * Word_3(b);\n    const uint64_t product44 = Word_4(a) * Word_4(b);\n\n    const __uint128_t sum0 = (__uint128_t)product44;\n    const __uint128_t sum1 = (__uint128_t)product34 + (__uint128_t)product43;\n    const __uint128_t sum2 = (__uint128_t)product24 + (__uint128_t)product33 + (__uint128_t)product42;\n    const __uint128_t sum3 = (__uint128_t)product14 + (__uint128_t)product23 + (__uint128_t)product32 + (__uint128_t)product41;\n    const __uint128_t sum4 = (__uint128_t)product13 + (__uint128_t)product22 + (__uint128_t)product31;\n    const __uint128_t sum5 = (__uint128_t)product12 + (__uint128_t)product21;\n    const __uint128_t sum6 = (__uint128_t)product11;\n\n    const __uint128_t r0 = (sum0 & Word_FullMask) + ((sum1 & Word_LoMask) << 32);\n    const __uint128_t r1 = (sum0 >> 64) + ((sum1 >> 32) & Word_FullMask) + (sum2 & Word_FullMask) + ((sum3 << 32) & Word_HiMask);\n\n    *lo = r0 + (r1 << 64);\n    *hi = (r1 >> 64) + (sum1 >> 96) + (sum2 >> 64) + (sum3 >> 32) + sum4 + (sum5 << 32) + (sum6 << 64);\n}\n#undef Word_1\n#undef Word_2\n#undef Word_3\n#undef Word_4\n#undef Word_HiMask\n#undef Word_LoMask\n#undef Word_FullMask\n#endif // __LDBL_MANT_DIG__ == 113\n#else\n#error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.\n#endif\n\n#if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) || defined(CRT_LDBL_128BIT)\n#define typeWidth (sizeof(rep_t) * CHAR_BIT)\n#define exponentBits (typeWidth - significandBits - 1)\n#define maxExponent ((1 << exponentBits) - 1)\n#define exponentBias (maxExponent >> 1)\n\n#define implicitBit (REP_C(1) << significandBits)\n#define significandMask (implicitBit - 1U)\n#define signBit (REP_C(1) << (significandBits + exponentBits))\n#define absMask (signBit - 1U)\n#define exponentMask (absMask ^ significandMask)\n#define oneRep ((rep_t)exponentBias << significandBits)\n#define infRep exponentMask\n#define quietBit (implicitBit >> 1)\n#define qnanRep (exponentMask | quietBit)\n\nstatic __inline rep_t\ntoRep(fp_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline fp_t\nfromRep(rep_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\nstatic __inline int\nnormalize(rep_t *significand)\n{\n    const int shift = rep_clz(*significand) - rep_clz(implicitBit);\n    *significand <<= shift;\n    return 1 - shift;\n}\n\nstatic __inline void\nwideLeftShift(rep_t *hi, rep_t *lo, int count)\n{\n    *hi = *hi << count | *lo >> (typeWidth - count);\n    *lo = *lo << count;\n}\n\nstatic __inline void\nwideRightShiftWithSticky(rep_t *hi, rep_t *lo, unsigned int count)\n{\n    if (count < typeWidth) {\n        const bool sticky = *lo << (typeWidth - count);\n        *lo = *hi << (typeWidth - count) | *lo >> count | sticky;\n        *hi = *hi >> count;\n    } else if (count < 2 * typeWidth) {\n        const bool sticky = *hi << (2 * typeWidth - count) | *lo;\n        *lo = *hi >> (count - typeWidth) | sticky;\n        *hi = 0;\n    } else {\n        const bool sticky = *hi | *lo;\n        *lo = sticky;\n        *hi = 0;\n    }\n}\n#endif\n\n#endif // FP_LIB_HEADER\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_mul_impl.inc",
    "content": "//===---- lib/fp_mul_impl.inc - floating point multiplication -----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float multiplication with the IEEE-754 default\n// rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __mulXf3__(fp_t a, fp_t b) {\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN * anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything * NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity * non-zero = +/- infinity\n            if (bAbs) return fromRep(aAbs | productSign);\n            // infinity * zero = NaN\n            else return fromRep(qnanRep);\n        }\n\n        if (bAbs == infRep) {\n            //? non-zero * infinity = +/- infinity\n            if (aAbs) return fromRep(bAbs | productSign);\n            // zero * infinity = NaN\n            else return fromRep(qnanRep);\n        }\n\n        // zero * anything = +/- zero\n        if (!aAbs) return fromRep(productSign);\n        // anything * zero = +/- zero\n        if (!bAbs) return fromRep(productSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale += normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n\n    // Get the significand of a*b.  Before multiplying the significands, shift\n    // one of them left to left-align it in the field.  Thus, the product will\n    // have (exponentBits + 2) integral digits, all but two of which must be\n    // zero.  Normalizing this result is just a conditional left-shift by one\n    // and bumping the exponent accordingly.\n    rep_t productHi, productLo;\n    wideMultiply(aSignificand, bSignificand << exponentBits,\n                 &productHi, &productLo);\n\n    int productExponent = aExponent + bExponent - exponentBias + scale;\n\n    // Normalize the significand, adjust exponent if needed.\n    if (productHi & implicitBit) productExponent++;\n    else wideLeftShift(&productHi, &productLo, 1);\n\n    // If we have overflowed the type, return +/- infinity.\n    if (productExponent >= maxExponent) return fromRep(infRep | productSign);\n\n    if (productExponent <= 0) {\n        // Result is denormal before rounding\n        //\n        // If the result is so small that it just underflows to zero, return\n        // a zero of the appropriate sign.  Mathematically there is no need to\n        // handle this case separately, but we make it a special case to\n        // simplify the shift logic.\n        const unsigned int shift = REP_C(1) - (unsigned int)productExponent;\n        if (shift >= typeWidth) return fromRep(productSign);\n\n        // Otherwise, shift the significand of the result so that the round\n        // bit is the high bit of productLo.\n        wideRightShiftWithSticky(&productHi, &productLo, shift);\n    }\n    else {\n        // Result is normal before rounding; insert the exponent.\n        productHi &= significandMask;\n        productHi |= (rep_t)productExponent << significandBits;\n    }\n\n    // Insert the sign of the result:\n    productHi |= productSign;\n\n    // Final rounding.  The final result may overflow to infinity, or underflow\n    // to zero, but those are the correct results in those cases.  We use the\n    // default IEEE-754 round-to-nearest, ties-to-even rounding mode.\n    if (productLo > signBit) productHi++;\n    if (productLo == signBit) productHi += productHi & 1;\n    return fromRep(productHi);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_trunc.h",
    "content": "//=== lib/fp_trunc.h - high precision -> low precision conversion *- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination precision setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_TRUNC_HEADER\n#define FP_TRUNC_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\n\n#elif defined SRC_QUAD\ntypedef long double src_t;\ntypedef __uint128_t src_rep_t;\n#define SRC_REP_C (__uint128_t)\nstatic const int srcSigBits = 112;\n\n#else\n#error Source should be double precision or quad precision!\n#endif // end source precision\n\n#if defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_HALF\ntypedef uint16_t dst_t;\ntypedef uint16_t dst_rep_t;\n#define DST_REP_C UINT16_C\nstatic const int dstSigBits = 10;\n\n#else\n#error Destination should be single precision or double precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\n#endif // FP_TRUNC_HEADER\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fp_trunc_impl.inc",
    "content": "//= lib/fp_trunc_impl.inc - high precision -> low precision conversion *-*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a wider to a narrower\n// IEEE-754 floating-point type in the default (round to nearest, ties to even)\n// rounding mode.  The constants and types defined following the includes below\n// parameterize the conversion.\n//\n// This routine can be trivially adapted to support conversions to\n// half-precision or from quad-precision. It does not support types that don't\n// use the usual IEEE-754 interchange formats; specifically, some work would be\n// needed to adapt it to (for example) the Intel 80-bit format or PowerPC\n// double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *narrowing* operations; if you need to convert to a *wider* floating-point\n// type (e.g. float -> double), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_trunc.h\"\n\nstatic __inline dst_t __truncXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcSignificandMask = srcMinNormal - 1;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t roundMask = (SRC_REP_C(1) << (srcSigBits - dstSigBits)) - 1;\n    const src_rep_t halfway = SRC_REP_C(1) << (srcSigBits - dstSigBits - 1);\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const int underflowExponent = srcExpBias + 1 - dstExpBias;\n    const int overflowExponent = srcExpBias + dstInfExp - dstExpBias;\n    const src_rep_t underflow = (src_rep_t)underflowExponent << srcSigBits;\n    const src_rep_t overflow = (src_rep_t)overflowExponent << srcSigBits;\n\n    const dst_rep_t dstQNaN = DST_REP_C(1) << (dstSigBits - 1);\n    const dst_rep_t dstNaNCode = dstQNaN - 1;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    if (aAbs - underflow < aAbs - overflow) {\n        // The exponent of a is within the range of normal numbers in the\n        // destination format.  We can convert by simply right-shifting with\n        // rounding and adjusting the exponent.\n        absResult = aAbs >> (srcSigBits - dstSigBits);\n        absResult -= (dst_rep_t)(srcExpBias - dstExpBias) << dstSigBits;\n\n        const src_rep_t roundBits = aAbs & roundMask;\n        // Round to nearest\n        if (roundBits > halfway)\n            absResult++;\n        // Ties to even\n        else if (roundBits == halfway)\n            absResult += absResult & 1;\n    }\n    else if (aAbs > srcInfinity) {\n        // a is NaN.\n        // Conjure the result by beginning with infinity, setting the qNaN\n        // bit and inserting the (truncated) trailing NaN field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= dstQNaN;\n        absResult |= ((aAbs & srcNaNCode) >> (srcSigBits - dstSigBits)) & dstNaNCode;\n    }\n    else if (aAbs >= overflow) {\n        // a overflows to infinity.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n    }\n    else {\n        // a underflows on conversion to the destination type or is an exact\n        // zero.  The result may be a denormal or zero.  Extract the exponent\n        // to get the shift amount for the denormalization.\n        const int aExp = aAbs >> srcSigBits;\n        const int shift = srcExpBias - dstExpBias - aExp + 1;\n\n        const src_rep_t significand = (aRep & srcSignificandMask) | srcMinNormal;\n\n        // Right shift by the denormalization amount with sticky.\n        if (shift > srcSigBits) {\n            absResult = 0;\n        } else {\n            const bool sticky = significand << (srcBits - shift);\n            src_rep_t denormalizedSignificand = significand >> shift | sticky;\n            absResult = denormalizedSignificand >> (srcSigBits - dstSigBits);\n            const src_rep_t roundBits = denormalizedSignificand & roundMask;\n            // Round to nearest\n            if (roundBits > halfway)\n                absResult++;\n            // Ties to even\n            else if (roundBits == halfway)\n                absResult += absResult & 1;\n        }\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | sign >> (srcBits - dstBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fsb_allocator.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <fsb_allocator.h>\n#include <alloc.h>\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <attributes.h>\n#include <atomic_bit.h>\n\nATOMIC_BIT_INIT(__fsb_lock);\n\n// noinline, because part of grind tracked functions\nfsb_allocator_t __noinline\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks)\n{\n    if (block_size > 0xFFFFFFF8) {\n        __asm__ volatile(\"fault \" __STR(__FAULT_ALLOC_HEAP_FULL__));\n        unreachable();\n    }\n\n    block_size = (block_size == 0) ? 8 : (block_size + 7) & ~7;\n\n    unsigned int memory_space_to_allocate = block_size * nb_of_blocks + 4;\n    void *memory = mem_alloc(memory_space_to_allocate);\n\n    unsigned int first_block = (unsigned int)memory;\n\n    for (unsigned int each_block = 0; each_block < nb_of_blocks - 1; ++each_block) {\n        unsigned int next_block_address = (unsigned int)(memory + block_size);\n        *((unsigned int *)memory) = next_block_address;\n        memory = (void *)next_block_address;\n    }\n\n    *((unsigned int *)memory) = 0;\n    memory += block_size;\n\n    void *free_ptr = memory;\n    *((unsigned int *)free_ptr) = first_block;\n\n    return (fsb_allocator_t)free_ptr;\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nfsb_get(fsb_allocator_t allocator)\n{\n    void **result;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(result) : [alloc] \"r\"(allocator));\n\n    if (result == NULL) {\n        ATOMIC_BIT_RELEASE(__fsb_lock);\n        return NULL;\n    }\n\n    void *next = *result;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(next), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n\n    return (void *)result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nfsb_free(fsb_allocator_t allocator, void *ptr)\n{\n    void *next_free;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(next_free) : [alloc] \"r\"(allocator));\n\n    *((void **)ptr) = next_free;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(ptr), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/fsb_allocator.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_FBS_ALLOC_H\n#define DPUSYSCORE_FBS_ALLOC_H\n\n/**\n * @file fsb_allocator.h\n * @brief Provides a fixed-size block memory allocator.\n *\n * @internal When defining an allocator, the total memory needed will be allocated, using mem_alloc.\n *           The allocator structure is a pointer to the next available block. In each free block, the first four bytes\n *           store a pointer to the following free block, creating a linked list. To allocate a block, we just check\n *           the free pointer, check the next free pointer and update the free pointer accordingly. To free a block, we\n *           just check the free pointer, update it with the newly free block, and update the next pointer of this block\n *           with the previous free pointer.\n *           There is no protection to prevent invalid block to be added to the list. Moreover, the list being in the free\n *           blocks, if there is some memory overflow from a block, the list might be corrupted and totally invalid.\n */\n\n/**\n * @fn fsb_allocator_t\n * @brief A fixed-size block allocator.\n */\ntypedef void **fsb_allocator_t;\n\n/**\n * @fn fsb_alloc\n * @brief Allocate and initialize a fixed-size block allocator.\n *\n * @param block_size the size of the blocks allocated (will be realigned on 8 bytes, with a minimum of 8 bytes)\n * @param nb_of_blocks the number of blocks allocated\n * @throws a fault if there is no memory left\n * @return The newly allocated and ready-to-use fixed-size block allocator.\n */\nfsb_allocator_t\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks);\n\n/**\n * @fn fsb_get\n * @brief Own a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator from which we take the block\n * @return A pointer to the owned block if one was available, NULL otherwise.\n */\nvoid *\nfsb_get(fsb_allocator_t allocator);\n\n/**\n * @fn fsb_free\n * @brief Free a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator in which we put the block back in\n * @param ptr the pointer to the block to free\n */\nvoid\nfsb_free(fsb_allocator_t allocator, void *ptr);\n\n#endif /* DPUSYSCORE_FBS_ALLOC_H */"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/handshake.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <errno.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\nunsigned char __handshake_array[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };\n\nATOMIC_BIT_INIT(__handshake)[NR_THREADS];\n\n#define __acquire_handshake(off) __ATOMIC_BIT_ACQUIRE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n#define __release_handshake(off) __ATOMIC_BIT_RELEASE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n\nvoid\nhandshake_notify(void)\n{\n    thread_id_t tid = me();\n    unsigned char info;\n    __acquire_handshake(tid);\n    info = __handshake_array[tid];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[tid] = tid;\n        __release_handshake(tid);\n        __stop();\n    } else {\n        __resume(info, \"0\");\n        __handshake_array[tid] = __EMPTY_WAIT_QUEUE;\n        __release_handshake(tid);\n    }\n}\n\nint\nhandshake_wait_for(unsigned int notifier)\n{\n    thread_id_t tid = me();\n\n    unsigned char thread = (unsigned char)notifier;\n\n    __acquire_handshake(thread);\n    unsigned char info = __handshake_array[thread];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[thread] = tid;\n        __release_handshake(thread);\n        __stop();\n    } else {\n        if (unlikely(info != thread)) {\n            errno = EALREADY;\n            __release_handshake(thread);\n            return EALREADY;\n        } else {\n            __resume(info, \"0\");\n            __handshake_array[thread] = __EMPTY_WAIT_QUEUE;\n        }\n\n        __release_handshake(thread);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/handshake.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_HANDSHAKE_H\n#define DPUSYSCORE_HANDSHAKE_H\n\n/**\n * @file handshake.h\n * @brief Synchronization with handshakes.\n *\n * This synchronization mechanism allows to synchronize 2 tasklets. One tasklet will serve as a notifier\n * and will call handshake_notify() and the other as a customer and will call handshake_wait_for(notifier).\n *\n * @internal    If the notifier called handshake_notify() before the customer, it will stop until some tasklet\n *              calls handshake_wait_for(notifier).\n *              If a tasklet called handshake_wait_for(notifier) before the notifier, it will stop until\n *              the notifier calls handshake_notify(). If afterwards (still before the notifier calls\n *              handshake_notify()) another tasklet attempts to call handshake_wait_for(notifier) with\n *              the same tasklet in the parameter, the function will do nothing and will return the number\n *              of error and set the errno to the corresponding error number.\n */\n\n#include <sysdef.h>\n\n/**\n * @fn handshake_notify\n * @brief Notifies a tasklet waiting for the notifier.\n *\n * The invoking tasklet is suspended until another tasklet calls handshake_wait_for(notifier).\n * When this condition is reached, the function resumes the waiting tasklet.\n */\nvoid\nhandshake_notify(void);\n\n/**\n * @fn handshake_wait_for\n * @brief Waits for the notifier tasklet\n *\n * The invoking tasklet is suspended until the notifier tasklet (indicated in the parameter) sends a\n * notification to tell the invoking tasklet that it can go ahead.\n *\n * Beware that if the notifier tasklet and the invoking tasklet are the same, the tasklet will be suspended with no\n * easy way to wake it up. The user should check this case itself if it is something that their program allows.\n *\n * If the number of the notifier is not a defined tasklet, the function behavior is undefined. If some other tasklet has\n * already called handshake_wait_for() with the same notifier in the parameter and that the notifier has not yet called\n * handshake_notify(), the function will do nothing and simply return EALREADY.\n *\n * In both cases the errno will be set to the corresponding error number.\n *\n * @param notifier a number to wait the notification from. It must be a defined tasklet.\n * @return 0 if no error was detected, EALREADY if a corresponding error was detected.\n */\nint\nhandshake_wait_for(sysname_t notifier);\n\n#endif /* DPUSYSCORE_HANDSHAKE_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_endianness.h",
    "content": "/* ===-- int_endianness.h - configuration header for compiler-rt ------------===\n *\n *\t\t       The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_ENDIANNESS_H\n#define INT_ENDIANNESS_H\n\n#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && defined(__ORDER_LITTLE_ENDIAN__)\n\n/* Clang and GCC provide built-in endianness definitions. */\n#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* __BYTE_ORDER__ */\n\n#else /* Compilers other than Clang or GCC. */\n\n#if defined(__SVR4) && defined(__sun)\n#include <sys/byteorder.h>\n\n#if defined(_BIG_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif defined(_LITTLE_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#else /* !_LITTLE_ENDIAN */\n#error \"unknown endianness\"\n#endif /* !_LITTLE_ENDIAN */\n\n#endif /* Solaris and AuroraUX. */\n\n/* .. */\n\n#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__minix)\n#include <sys/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* *BSD */\n\n#if defined(__OpenBSD__) || defined(__Bitrig__)\n#include <machine/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* OpenBSD and Bitrig. */\n\n/* .. */\n\n/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the\n * compiler (at least with GCC) */\n#if defined(__APPLE__) || defined(__ellcc__)\n\n#ifdef __BIG_ENDIAN__\n#if __BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#endif\n#endif /* __BIG_ENDIAN__ */\n\n#ifdef __LITTLE_ENDIAN__\n#if __LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif\n#endif /* __LITTLE_ENDIAN__ */\n\n#endif /* Mac OSX */\n\n/* .. */\n\n#if defined(_WIN32)\n\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n\n#endif /* Windows */\n\n#endif /* Clang or GCC. */\n\n/* . */\n\n#if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN)\n#error Unable to determine endian\n#endif /* Check we found an endianness correctly. */\n\n#endif /* INT_ENDIANNESS_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_lib.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_LIB_H\n#define INT_LIB_H\n\n/* Assumption: Signed integral is 2's complement. */\n/* Assumption: Right shift of signed negative is arithmetic shift. */\n/* Assumption: Endianness is little or big (not mixed). */\n\n#if defined(__ELF__)\n#define FNALIAS(alias_name, original_name) void alias_name() __attribute__((alias(#original_name)))\n#else\n#define FNALIAS(alias, name) _Pragma(\"GCC error(\\\"alias unsupported on this file format\\\")\")\n#endif\n\n/* ABI macro definitions */\n\n#if __ARM_EABI__\n#ifdef COMPILER_RT_ARMHF_TARGET\n#define COMPILER_RT_ABI\n#else\n#define COMPILER_RT_ABI __attribute__((__pcs__(\"aapcs\")))\n#endif\n#else\n#define COMPILER_RT_ABI\n#endif\n\n#define AEABI_RTABI __attribute__((__pcs__(\"aapcs\")))\n\n#ifdef _MSC_VER\n#define ALWAYS_INLINE __forceinline\n#define NOINLINE __declspec(noinline)\n#define NORETURN __declspec(noreturn)\n#define UNUSED\n#else\n#define ALWAYS_INLINE __attribute__((always_inline))\n#define NOINLINE __attribute__((noinline))\n#define NORETURN __attribute__((noreturn))\n#define UNUSED __attribute__((unused))\n#endif\n\n#if defined(__NetBSD__) && (defined(_KERNEL) || defined(_STANDALONE))\n/*\n * Kernel and boot environment can't use normal headers,\n * so use the equivalent system headers.\n */\n#include <machine/limits.h>\n#include <sys/stdint.h>\n#include <sys/types.h>\n#else\n/* Include the standard compiler builtin headers we use functionality from. */\n#include <limits.h>\n#include <stdint.h>\n#include <stdbool.h>\n#include <float.h>\n#endif\n\n/* Include the commonly used internal type definitions. */\n#include \"int_types.h\"\n\n/* Include internal utility function declarations. */\n#include \"int_util.h\"\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a);\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a);\n\nCOMPILER_RT_ABI di_int\n__divdi3(di_int a, di_int b);\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b);\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem);\nCOMPILER_RT_ABI du_int\n__udivmoddi4(du_int a, du_int b, du_int *rem);\n#ifdef CRT_HAS_128BIT\nCOMPILER_RT_ABI si_int\n__clzti2(ti_int a);\nCOMPILER_RT_ABI tu_int\n__udivmodti4(tu_int a, tu_int b, tu_int *rem);\n#endif\n\n/* Definitions for builtins unavailable on MSVC */\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <intrin.h>\n\nuint32_t __inline __builtin_ctz(uint32_t value)\n{\n    unsigned long trailing_zero = 0;\n    if (_BitScanForward(&trailing_zero, value))\n        return trailing_zero;\n    return 32;\n}\n\nuint32_t __inline __builtin_clz(uint32_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse(&leading_zero, value))\n        return 31 - leading_zero;\n    return 32;\n}\n\n#if defined(_M_ARM) || defined(_M_X64)\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse64(&leading_zero, value))\n        return 63 - leading_zero;\n    return 64;\n}\n#else\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    if (value == 0)\n        return 64;\n    uint32_t msh = (uint32_t)(value >> 32);\n    uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF);\n    if (msh != 0)\n        return __builtin_clz(msh);\n    return 32 + __builtin_clz(lsh);\n}\n#endif\n\n#define __builtin_clzl __builtin_clzll\n#endif /* defined(_MSC_VER) && !defined(__clang__) */\n\n#endif /* INT_LIB_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_math.h",
    "content": "/* ===-- int_math.h - internal math inlines ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines substitutes for the libm functions used in some of the\n * compiler-rt implementations, defined in such a way that there is not a direct\n * dependency on libm or math.h. Instead, we use the compiler builtin versions\n * where available. This reduces our dependencies on the system SDK by foisting\n * the responsibility onto the compiler.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_MATH_H\n#define INT_MATH_H\n\n#ifndef __has_builtin\n#define __has_builtin(x) 0\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <math.h>\n#include <stdlib.h>\n#include <ymath.h>\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define CRT_INFINITY INFINITY\n#else\n#define CRT_INFINITY __builtin_huge_valf()\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_isfinite(x) _finite((x))\n#define crt_isinf(x) !_finite((x))\n#define crt_isnan(x) _isnan((x))\n#else\n/* Define crt_isfinite in terms of the builtin if available, otherwise provide\n * an alternate version in terms of our other functions. This supports some\n * versions of GCC which didn't have __builtin_isfinite.\n */\n#if __has_builtin(__builtin_isfinite)\n#define crt_isfinite(x) __builtin_isfinite((x))\n#elif defined(__GNUC__)\n#define crt_isfinite(x)                                                                                                          \\\n    __extension__(({                                                                                                             \\\n        __typeof((x)) x_ = (x);                                                                                                  \\\n        crt_isinf(x_) && crt_isnan(x_);                                                                                          \\\n    }))\n#else\n#error \"Do not know how to check for infinity\"\n#endif /* __has_builtin(__builtin_isfinite) */\n#define crt_isinf(x) __builtin_isinf((x))\n#define crt_isnan(x) __builtin_isnan((x))\n#endif /* _MSC_VER */\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_copysign(x, y) copysign((x), (y))\n#define crt_copysignf(x, y) copysignf((x), (y))\n#define crt_copysignl(x, y) copysignl((x), (y))\n#else\n#define crt_copysign(x, y) __builtin_copysign((x), (y))\n#define crt_copysignf(x, y) __builtin_copysignf((x), (y))\n#define crt_copysignl(x, y) __builtin_copysignl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fabs(x) fabs((x))\n#define crt_fabsf(x) fabsf((x))\n#define crt_fabsl(x) fabs((x))\n#else\n#define crt_fabs(x) __builtin_fabs((x))\n#define crt_fabsf(x) __builtin_fabsf((x))\n#define crt_fabsl(x) __builtin_fabsl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fmax(x, y) __max((x), (y))\n#define crt_fmaxf(x, y) __max((x), (y))\n#define crt_fmaxl(x, y) __max((x), (y))\n#else\n#define crt_fmax(x, y) __builtin_fmax((x), (y))\n#define crt_fmaxf(x, y) __builtin_fmaxf((x), (y))\n#define crt_fmaxl(x, y) __builtin_fmaxl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_logb(x) logb((x))\n#define crt_logbf(x) logbf((x))\n#define crt_logbl(x) logbl((x))\n#else\n#define crt_logb(x) __builtin_logb((x))\n#define crt_logbf(x) __builtin_logbf((x))\n#define crt_logbl(x) __builtin_logbl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_scalbn(x, y) scalbn((x), (y))\n#define crt_scalbnf(x, y) scalbnf((x), (y))\n#define crt_scalbnl(x, y) scalbnl((x), (y))\n#else\n#define crt_scalbn(x, y) __builtin_scalbn((x), (y))\n#define crt_scalbnf(x, y) __builtin_scalbnf((x), (y))\n#define crt_scalbnl(x, y) __builtin_scalbnl((x), (y))\n#endif\n\n#endif /* INT_MATH_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_types.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines various standard types, most importantly a number of unions\n * used to access parts of larger types.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_TYPES_H\n#define INT_TYPES_H\n\n#include \"int_endianness.h\"\n\n/* si_int is defined in Linux sysroot's asm-generic/siginfo.h */\n#ifdef si_int\n#undef si_int\n#endif\ntypedef int si_int;\ntypedef unsigned su_int;\n\ntypedef long long di_int;\ntypedef unsigned long long du_int;\n\ntypedef union {\n    di_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        si_int high;\n#else\n        si_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} dwords;\n\ntypedef union {\n    du_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        su_int high;\n#else\n        su_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} udwords;\n\n#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64))\n#define CRT_HAS_128BIT\n#endif\n\n#ifdef CRT_HAS_128BIT\ntypedef int ti_int __attribute__((mode(TI)));\ntypedef unsigned tu_int __attribute__((mode(TI)));\n\ntypedef union {\n    ti_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        di_int high;\n#else\n        di_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} twords;\n\ntypedef union {\n    tu_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        du_int high;\n#else\n        du_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} utwords;\n\nstatic __inline ti_int\nmake_ti(di_int h, di_int l)\n{\n    twords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\nstatic __inline tu_int\nmake_tu(du_int h, du_int l)\n{\n    utwords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\n#endif /* CRT_HAS_128BIT */\n\ntypedef union {\n    su_int u;\n    float f;\n} float_bits;\n\ntypedef union {\n    udwords u;\n    double f;\n} double_bits;\n\ntypedef struct {\n#if _YUGA_LITTLE_ENDIAN\n    udwords low;\n    udwords high;\n#else\n    udwords high;\n    udwords low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n} uqwords;\n\ntypedef union {\n    uqwords u;\n    long double f;\n} long_double_bits;\n\n#if __STDC_VERSION__ >= 199901L\ntypedef float _Complex Fcomplex;\ntypedef double _Complex Dcomplex;\ntypedef long double _Complex Lcomplex;\n\n#define COMPLEX_REAL(x) __real__(x)\n#define COMPLEX_IMAGINARY(x) __imag__(x)\n#else\ntypedef struct {\n    float real, imaginary;\n} Fcomplex;\n\ntypedef struct {\n    double real, imaginary;\n} Dcomplex;\n\ntypedef struct {\n    long double real, imaginary;\n} Lcomplex;\n\n#define COMPLEX_REAL(x) (x).real\n#define COMPLEX_IMAGINARY(x) (x).imaginary\n#endif\n#endif /* INT_TYPES_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_util.c",
    "content": "/* ===-- int_util.c - Implement internal utilities --------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_util.h\"\n\n/* NOTE: The definitions in this file are declared weak because we clients to be\n * able to arbitrarily package individual functions into separate .a files. If\n * we did not declare these weak, some link situations might end up seeing\n * duplicate strong definitions of the same symbol.\n *\n * We can't use this solution for kernel use (which may not support weak), but\n * currently expect that when built for kernel use all the functionality is\n * packaged into a single library.\n */\n\n#ifdef KERNEL_USE\n\nNORETURN extern void\npanic(const char *, ...);\n#ifndef _WIN32\n__attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    panic(\"%s:%d: abort in %s\", file, line, function);\n}\n\n#elif __APPLE__\n\n/* from libSystem.dylib */\nNORETURN extern void\n__assert_rtn(const char *func, const char *file, int line, const char *message);\n\n#ifndef _WIN32\n__attribute__((weak)) __attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    __assert_rtn(function, file, line, \"libcompiler_rt abort\");\n}\n\n#else\n\n/* Get the system definition of abort() */\n#include <stdlib.h>\n\n#ifndef _WIN32\n// JFR dirty patch\n// DPUCC doesn't like it either __attribute__((weak))\n// DPUCC doesn't like it either __attribute__((visibility(\"hidden\")))\n// End of patch\n#endif\nvoid\ncompilerrt_abort_impl(const char *file __attribute__((unused)),\n    int line __attribute__((unused)),\n    const char *function __attribute__((unused)))\n{\n    abort();\n}\n\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/int_util.h",
    "content": "/* ===-- int_util.h - internal utility functions ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines non-inline utilities which are available for use in the\n * library. The function definitions themselves are all contained in int_util.c\n * which will always be compiled into any compiler-rt library.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_UTIL_H\n#define INT_UTIL_H\n\n/** \\brief Trigger a program abort (or panic for kernel code). */\n#define compilerrt_abort() compilerrt_abort_impl(__FILE__, __LINE__, __func__)\n\nNORETURN void\ncompilerrt_abort_impl(const char *file, int line, const char *function);\n\n#define COMPILE_TIME_ASSERT(expr) COMPILE_TIME_ASSERT1(expr, __COUNTER__)\n#define COMPILE_TIME_ASSERT1(expr, cnt) COMPILE_TIME_ASSERT2(expr, cnt)\n#define COMPILE_TIME_ASSERT2(expr, cnt) typedef char ct_assert_##cnt[(expr) ? 1 : -1] UNUSED\n\n#endif /* INT_UTIL_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/listener.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#include <sysdef.h>\n#include <defs.h>\n\nextern bool\nfetch_request(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\nextern bool\nfifo_is_full(uint32_t fifo_info, uint32_t request_size);\nextern void\nfifo_produce(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\n\nstatic inline uint32_t\nfifo_sys_fetch_info(uint32_t fid)\n{\n    extern uint32_t __sys_fifo_sys_table;\n    return (&__sys_fifo_sys_table)[fid];\n}\n\nstatic inline uint32_t\nfifo_fetch_info(sysname_t recipient)\n{\n    extern uint32_t __sys_fifo_table_ptr;\n    return *((uint32_t *)((&__sys_fifo_table_ptr)[recipient] & 0xFFFF));\n}\n\nstatic inline sysname_t\nfetch_recipient(uint32_t id)\n{\n    return id >> 24;\n}\n\nstatic inline sysname_t\nfetch_request_id(uint32_t id)\n{\n    return id & 0x00FFFFFF;\n}\n\nvoid\n__sys_internal_listener_loop(uint32_t *request, uint32_t request_size)\n{\n    sysname_t id = me();\n    uint32_t self_fifo_info;\n    uint32_t from_host_fifo_info;\n    uint32_t to_host_fifo_info;\n\n    self_fifo_info = fifo_fetch_info(id);\n    from_host_fifo_info = fifo_sys_fetch_info(0);\n    to_host_fifo_info = fifo_sys_fetch_info(1);\n\n    while (true) {\n        if (fetch_request(self_fifo_info, request, request_size)) {\n            while (fifo_is_full(to_host_fifo_info, request_size)) {\n                // Waiting for the recipient to read some of its pending requests...\n                // Do we want to add some \"sleep\" here?\n            }\n\n            fifo_produce(to_host_fifo_info, request, request_size);\n        }\n        if (fetch_request(from_host_fifo_info, request, request_size)) {\n            sysname_t recipient = fetch_recipient(request[0]);\n\n            /* If a message is sent to the listener from the host, we interpret it as a shutdown order. */\n            if (recipient == id)\n                break;\n\n            request[0] = fetch_request_id(request[0]);\n\n            extern void internal_actor_send(uint32_t recipient, uint32_t * request, uint32_t request_size);\n            internal_actor_send(recipient, request, request_size);\n        }\n\n        // Waiting for some request...\n        // Do we want to add some \"sleep\" here?\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/lshrdi3.c",
    "content": "/* ===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __lshrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: logical a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__lshrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    udwords input;\n    udwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.high = 0;\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsr(di_int a, si_int b)\n{\n    return __lshrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/macro_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MACRO_UTILS_H\n#define DPUSYSCORE_MACRO_UTILS_H\n\n/**\n * @file macro_utils.h\n * @brief Provide utility macros.\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\n#define __CONCAT(x, y) __CONCAT_AGAIN(x, y)\n#define __CONCAT_AGAIN(x, y) x##y\n\n#define __REPEAT_0(x)\n#define __REPEAT_1(x) x(0) __REPEAT_0(x)\n#define __REPEAT_2(x) x(1) __REPEAT_1(x)\n#define __REPEAT_3(x) x(2) __REPEAT_2(x)\n#define __REPEAT_4(x) x(3) __REPEAT_3(x)\n#define __REPEAT_5(x) x(4) __REPEAT_4(x)\n#define __REPEAT_6(x) x(5) __REPEAT_5(x)\n#define __REPEAT_7(x) x(6) __REPEAT_6(x)\n#define __REPEAT_8(x) x(7) __REPEAT_7(x)\n#define __REPEAT_9(x) x(8) __REPEAT_8(x)\n#define __REPEAT_10(x) x(9) __REPEAT_9(x)\n#define __REPEAT_11(x) x(10) __REPEAT_10(x)\n#define __REPEAT_12(x) x(11) __REPEAT_11(x)\n#define __REPEAT_13(x) x(12) __REPEAT_12(x)\n#define __REPEAT_14(x) x(13) __REPEAT_13(x)\n#define __REPEAT_15(x) x(14) __REPEAT_14(x)\n#define __REPEAT_16(x) x(15) __REPEAT_15(x)\n#define __REPEAT_17(x) x(16) __REPEAT_16(x)\n#define __REPEAT_18(x) x(17) __REPEAT_17(x)\n#define __REPEAT_19(x) x(18) __REPEAT_18(x)\n#define __REPEAT_20(x) x(19) __REPEAT_19(x)\n#define __REPEAT_21(x) x(20) __REPEAT_20(x)\n#define __REPEAT_22(x) x(21) __REPEAT_21(x)\n#define __REPEAT_23(x) x(22) __REPEAT_22(x)\n#define __REPEAT_24(x) x(23) __REPEAT_23(x)\n#define __FOR_EACH_THREAD(x) __CONCAT(__REPEAT_, NR_THREADS)(x)\n\n#endif /* DPUSYSCORE_MACRO_UTILS_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mcount.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, noinline, no_instrument_function)) mcount(void)\n{\n    // Please see ret_mcount comment regarding why mcount references ret_mcount.\n    __asm__ volatile(\"jump ret_mcount\");\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) ret_mcount(void)\n{\n    // ret_mcount is used in statistics mode, mcount *must* reference ret_mcount\n    // so that ret_mcount symbol is not gc (remember that we patch the binary\n    // when copying it to iram).\n    __asm__ volatile(\"sh id4, thread_profiling, r23\\n\"\n                     \"jump r23\");\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/moddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__moddi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 1);\n        } else {\n            return __udiv64(dividend, -divider, 1);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 1);\n    } else {\n        // Negative dividend, negative divider\n        return -__udiv64(-dividend, -divider, 1);\n    }\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/modsi3.c",
    "content": "/* ===-- modsi3.c - Implement __modsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __modsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__modsi3(si_int a, si_int b)\n{\n    long res = __div32(a, b);\n    return (int)res;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mram.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MRAM_H\n#define DPUSYSCORE_MRAM_H\n\n#include <stdint.h>\n#include <attributes.h>\n\n/**\n * @file mram.h\n * @brief MRAM Transfer Management.\n */\n\n#define DPU_MRAM_HEAP_POINTER ((__mram_ptr void *)(&__sys_used_mram_end))\nextern __mram_ptr __dma_aligned uint8_t __sys_used_mram_end[0];\n\n/**\n * @fn mram_read\n * @brief Stores the specified number of bytes from MRAM to WRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in MRAM\n * @param to destination address in WRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_read(const __mram_ptr void *from, void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_ldma(to, from, nb_of_bytes);\n}\n\n/**\n * @fn mram_write\n * @brief Stores the specified number of bytes from WRAM to MRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in WRAM\n * @param to destination address in MRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_write(const void *from, __mram_ptr void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_sdma(from, to, nb_of_bytes);\n}\n\n#endif /* DPUSYSCORE_MRAM_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mul32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nint __attribute__((noinline)) __mulsi3(int a, int b)\n{\n    int dest;\n    __asm__ volatile(\"  jgtu %2, %1, __mulsi3_swap\\n\"\n                     \"  move r2, %1\\n\"\n                     \"  move r0, %2, true, __mulsi3_start\\n\"\n                     \"__mulsi3_swap:\\n\"\n                     \"  move r2, %2\\n\"\n                     \"  move r0, %1\\n\"\n                     \"__mulsi3_start:\\n\"\n                     \"  move r1, zero\\n\"\n                     \"  mul_step d0, r2, d0, 0 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 1 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 2 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 3 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 4 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 5 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 6 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 7 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 8 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 9 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 10, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 11, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 12, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 13, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 14, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 15, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 16, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 17, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 18, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 19, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 20, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 21, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 22, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 23, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 24, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 25, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 26, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 27, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 28, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 29, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 30, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 31, z, __mulsi3_exit\\n\"\n                     \"__mulsi3_exit:\\n\"\n                     \"  move %0, r1\\n\"\n                     : \"=r\"(dest)\n                     : \"r\"(a), \"r\"(b));\n    return dest;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mul64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication emulation.\n *\n * A relatively fast emulation of 64x64 multiplication using byte multipliers.\n * Basically, the two operands X and Y are seen as byte polynomials:\n *  - X = X0.2^0 + X1.2^8 + X2.2^16 + X3.2^24 + X4.2^32 + X5.2^40 + X6.2^48 + X7.2^56\n *  - Y = Y0.2^0 + Y1.2^8 + Y2.2^16 + Y3.2^24 + Y4.2^32 + Y5.2^40 + Y6.2^48 + Y7.2^56\n *\n * The product Z is expressed as a similar polynomial. Since the result is 64 bits,\n * the function drops any coefficient for a power greater than 56, hence the following\n * formula:\n *  Z = (X0.Y0).2^0\n *      + (X0.Y1 + X1.Y0).2^8\n *      + (X0.Y2 + X2.Y0 + X1.Y1).2^16\n *      + (X0.Y3 + X1.Y2 + X2.Y1 + X3.Y0).2^24\n *      + (X0.Y4 + X1.Y3 + X2.Y2 + X3.Y1 + X4.Y0).2^32\n *      etc.\n *\n * Each individual produce is computed with the native built-in 8x8 instructions.\n * Resulting processing time is in the magnitude of 150 instructions.\n *\n * The two operands are found in __D0 and the first kernel nano-stack entry.\n * The result goes into __R0 (lsbits) and __R1 (msbits).\n * Also, __R2 contains the return address register, instead of __RET__.\n */\n#include <stdint.h>\n\nstatic uint16_t\n_mul00(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * (b & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul01(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\n#define _mul02(a, b) _mul00(a, (b >> 16))\n#define _mul03(a, b) _mul01(a, (b >> 16))\n\nstatic uint16_t\n_mul11(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul12(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 16) & 0xff);\n#else\n    uint32_t r = (b >> 16);\n    __asm__ volatile(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(r) :);\n    return r;\n#endif\n}\n\n#define _mul13(a, b) _mul11(a, (b >> 16))\n#define _mul22(a, b) _mul00((a >> 16), (b >> 16))\n#define _mul23(a, b) _mul01((a >> 16), (b >> 16))\n#define _mul33(a, b) _mul11((a >> 16), (b >> 16))\n\n#define mulx0y0(xl, yl) _mul00(xl, yl)\n#define mulx0y1(xl, yl) _mul01(xl, yl)\n#define mulx0y2(xl, yl) _mul02(xl, yl)\n#define mulx0y3(xl, yl) _mul03(xl, yl)\n#define mulx0y4(xl, yh) _mul00(xl, yh)\n#define mulx0y5(xl, yh) _mul01(xl, yh)\n#define mulx0y6(xl, yh) _mul02(xl, yh)\n#define mulx0y7(xl, yh) _mul03(xl, yh)\n\n#define mulx1y1(xl, yl) _mul11(xl, yl)\n#define mulx1y2(xl, yl) _mul12(xl, yl)\n#define mulx1y3(xl, yl) _mul13(xl, yl)\n#define mulx1y4(xl, yh) _mul01(yh, xl)\n#define mulx1y5(xl, yh) _mul11(xl, yh)\n#define mulx1y6(xl, yh) _mul12(xl, yh)\n\n#define mulx2y2(xl, yl) _mul22(xl, yl)\n#define mulx2y3(xl, yl) _mul23(xl, yl)\n#define mulx2y4(xl, yh) _mul02(yh, xl)\n#define mulx2y5(xl, yh) _mul12(yh, xl)\n\n#define mulx3y3(xl, yl) _mul33(xl, yl)\n#define mulx3y4(xl, yh) _mul03(yh, xl)\n\n// Symmetry...\n#define mulx1y0(xl, yl) mulx0y1(yl, xl)\n#define mulx2y0(xl, yl) mulx0y2(yl, xl)\n#define mulx2y1(xl, yl) mulx1y2(yl, xl)\n#define mulx3y0(xl, yl) mulx0y3(yl, xl)\n#define mulx3y1(xl, yl) mulx1y3(yl, xl)\n#define mulx3y2(xl, yl) mulx2y3(yl, xl)\n#define mulx4y0(xh, yl) mulx0y4(yl, xh)\n#define mulx4y1(xh, yl) mulx1y4(yl, xh)\n#define mulx4y2(xh, yl) mulx2y4(yl, xh)\n#define mulx4y3(xh, yl) mulx3y4(yl, xh)\n#define mulx5y0(xh, yl) mulx0y5(yl, xh)\n#define mulx5y1(xh, yl) mulx1y5(yl, xh)\n#define mulx5y2(xh, yl) mulx2y5(yl, xh)\n#define mulx6y0(xh, yl) mulx0y6(yl, xh)\n#define mulx6y1(xh, yl) mulx1y6(yl, xh)\n#define mulx7y0(xh, yl) mulx0y7(yl, xh)\n\nuint64_t\n__muldi3(uint64_t x, uint64_t y)\n{\n    uint32_t xl = x;\n    uint32_t xh = ((uint64_t)x >> 32);\n    uint32_t yl = y;\n    uint32_t yh = ((uint64_t)y >> 32);\n\n    // Each fragment of the product.\n    uint32_t p0, p1, p2, p3, p4, p5, p6, p7, rh;\n    uint64_t rl;\n\n    p0 = mulx0y0(xl, yl);\n    rl = (uint64_t)p0;\n    p1 = mulx0y1(xl, yl) + mulx1y0(xl, yl);\n    rl += ((uint64_t)p1 << 8);\n    p2 = mulx0y2(xl, yl) + mulx2y0(xl, yl) + mulx1y1(xl, yl);\n    rl += ((uint64_t)p2 << 16);\n    p3 = mulx0y3(xl, yl) + mulx3y0(xl, yl) + mulx1y2(xl, yl) + mulx2y1(xl, yl);\n    rl += ((uint64_t)p3 << 24);\n    p4 = mulx0y4(xl, yh) + mulx4y0(xh, yl) + mulx1y3(xl, yl) + mulx3y1(xl, yl) + mulx2y2(xl, yl);\n    rh = p4;\n    p5 = mulx0y5(xl, yh) + mulx5y0(xh, yl) + mulx1y4(xl, yh) + mulx4y1(xh, yl) + mulx2y3(xl, yl) + mulx3y2(xl, yl);\n    rh += p5 << 8;\n    p6 = mulx0y6(xl, yh) + mulx6y0(xh, yl) + mulx1y5(xl, yh) + mulx5y1(xh, yl) + mulx2y4(xl, yh) + mulx4y2(xh, yl)\n        + mulx3y3(xl, yl);\n    rh += p6 << 16;\n    p7 = mulx0y7(xl, yh) + mulx7y0(xh, yl) + mulx1y6(xl, yh) + mulx6y1(xh, yl) + mulx2y5(xl, yh) + mulx5y2(xh, yl)\n        + mulx3y4(xl, yh) + mulx4y3(xh, yl);\n    rh += p7 << 24;\n\n    return rl + (((uint64_t)rh) << 32);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/muldc3.c",
    "content": "/* ===-- muldc3.c - Implement __muldc3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __muldc3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_math.h\"\n\n/* Returns: the product of a + ib and c + id */\n\nCOMPILER_RT_ABI Dcomplex\n__muldc3(double __a, double __b, double __c, double __d)\n{\n    double __ac = __a * __c;\n    double __bd = __b * __d;\n    double __ad = __a * __d;\n    double __bc = __b * __c;\n    Dcomplex z;\n    COMPLEX_REAL(z) = __ac - __bd;\n    COMPLEX_IMAGINARY(z) = __ad + __bc;\n    if (crt_isnan(COMPLEX_REAL(z)) && crt_isnan(COMPLEX_IMAGINARY(z))) {\n        int __recalc = 0;\n        if (crt_isinf(__a) || crt_isinf(__b)) {\n            __a = crt_copysign(crt_isinf(__a) ? 1 : 0, __a);\n            __b = crt_copysign(crt_isinf(__b) ? 1 : 0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (crt_isinf(__c) || crt_isinf(__d)) {\n            __c = crt_copysign(crt_isinf(__c) ? 1 : 0, __c);\n            __d = crt_copysign(crt_isinf(__d) ? 1 : 0, __d);\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            __recalc = 1;\n        }\n        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) || crt_isinf(__ad) || crt_isinf(__bc))) {\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (__recalc) {\n            COMPLEX_REAL(z) = CRT_INFINITY * (__a * __c - __b * __d);\n            COMPLEX_IMAGINARY(z) = CRT_INFINITY * (__a * __d + __b * __c);\n        }\n    }\n    return z;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/muldf3.c",
    "content": "//===-- lib/muldf3.c - Double-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__muldf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dmul(fp_t a, fp_t b)\n{\n    return __muldf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mulodi4.c",
    "content": "/*===-- mulodi4.c - Implement __mulodi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulodi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulodi4(di_int a, di_int b, int *overflow)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    *overflow = 0;\n    di_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mulosi4.c",
    "content": "/*===-- mulosi4.c - Implement __mulosi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulosi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulosi4(si_int a, si_int b, int *overflow)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    *overflow = 0;\n    si_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mulsf3.c",
    "content": "//===-- lib/mulsf3.c - Single-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__mulsf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fmul(fp_t a, fp_t b)\n{\n    return __mulsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mulvdi3.c",
    "content": "/*===-- mulvdi3.c - Implement __mulvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulvdi3(di_int a, di_int b)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mulvsi3.c",
    "content": "/* ===-- mulvsi3.c - Implement __mulvsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulvsi3(si_int a, si_int b)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/mutex.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MUTEX_H\n#define DPUSYSCORE_MUTEX_H\n\n/**\n * @file mutex.h\n * @brief Mutual exclusions.\n *\n * A mutex ensures mutual exclusion between threads: only one runtime can have the mutex at a time, blocking all the\n * other threads trying to take the mutex.\n *\n * @internal All the mutexes are stored in a table in WRAM. In this table, each byte represents a mutex,\n *           and can be accessed directly by taking the base address of the table and adding it the sysname of the mutex\n *           we want (thus, the sysname should be an integer in the range [0; NB_MUTEX -1]). The result of\n *           this addition is what a mutex_get will return.\n *           A lock is made by using an lb_a instruction on the address of the mutex given as a parameter.\n *           An unlock is made by using an sb_r instruction on the address of the mutex given as a parameter.\n *           The id of the runtime doing the unlock is what is currently stored at the address of the mutex.\n *           The base address of this table is associated with the pointer defined by __MUTEX_TABLE__.\n */\n\n#include <stdint.h>\n#include <sysdef.h>\n#include <stdbool.h>\n#include <atomic_bit.h>\n\n/**\n * @typedef mutex_id_t\n * @brief A mutex object reference, as declared by MUTEX_INIT.\n */\ntypedef uint8_t *mutex_id_t;\n\n/**\n * @def MUTEX_GET\n * @hideinitializer\n * @brief Return the symbol to use when using the mutex associated to the given name.\n */\n#define MUTEX_GET(_name) _name\n\n/**\n * @def MUTEX_INIT\n * @hideinitializer\n * @brief Declare and initialize a mutex associated to the given name.\n */\n#define MUTEX_INIT(_name)                                                                                                        \\\n    ATOMIC_BIT_INIT(__CONCAT(mutex_, _name));                                                                                    \\\n    const mutex_id_t MUTEX_GET(_name) = &ATOMIC_BIT_GET(__CONCAT(mutex_, _name))\n\n/**\n * @fn mutex_lock\n * @brief Takes the lock on the given mutex.\n * @param mutex the mutex we want to lock\n */\nstatic inline void\nmutex_lock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"acquire %[mtx], 0, nz, .\" : : [mtx] \"r\"(mutex) :);\n}\n\n/**\n * @fn mutex_trylock\n * @brief Tries to take the lock on the given mutex. If the lock is already taken, returns immediately.\n * @param mutex the mutex we want to lock\n * @return Whether the mutex has been successfully locked.\n */\nstatic inline bool\nmutex_trylock(mutex_id_t mutex)\n{\n    bool result = true;\n    __asm__ volatile(\"acquire %[mtx], 0, z, .+2; move %[res], 0\" : [res] \"+r\"(result) : [mtx] \"r\"(mutex) :);\n    return result;\n}\n\n/**\n * @fn mutex_unlock\n * @brief Releases the lock on the given mutex.\n * @param mutex the mutex we want to unlock\n */\nstatic inline void\nmutex_unlock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"release %[mtx], 0, nz, .+1\" : : [mtx] \"r\"(mutex) :);\n}\n\n#endif /* DPUSYSCORE_MUTEX_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/negdf2.c",
    "content": "//===-- lib/negdf2.c - double-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negdf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dneg(fp_t a)\n{\n    return __negdf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/negdi2.c",
    "content": "/* ===-- negdi2.c - Implement __negdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\nCOMPILER_RT_ABI di_int\n__negdi2(di_int a)\n{\n    /* Note: this routine is here for API compatibility; any sane compiler\n     * should expand it inline.\n     */\n    return -a;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/negsf2.c",
    "content": "//===-- lib/negsf2.c - single-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negsf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fneg(fp_t a)\n{\n    return __negsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/negvdi2.c",
    "content": "/* ===-- negvdi2.c - Implement __negvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI di_int\n__negvdi2(di_int a)\n{\n    const di_int MIN = (di_int)1 << ((int)(sizeof(di_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/negvsi2.c",
    "content": "/* ===-- negvsi2.c - Implement __negvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI si_int\n__negvsi2(si_int a)\n{\n    const si_int MIN = (si_int)1 << ((int)(sizeof(si_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/paritydi2.c",
    "content": "/* ===-- paritydi2.c - Implement __paritydi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritydi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    return __paritysi2(x.s.high ^ x.s.low);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/paritysi2.c",
    "content": "/* ===-- paritysi2.c - Implement __paritysi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritysi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x ^= x >> 16;\n    x ^= x >> 8;\n    x ^= x >> 4;\n    return (0x6996 >> (x & 0xF)) & 1;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/perfcounter.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <perfcounter.h>\n#include <attributes.h>\n\n#define BIT_IMPRECISION 4\n\nperfcounter_t\nperfcounter_get(void)\n{\n    uint32_t reg_value;\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(reg_value));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n\n#ifndef DPU_PROFILING\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value)\n{\n    uint32_t reg_value;\n    uint32_t reg_config = (reset_value ? 1 : 0) | (config << 1);\n    __asm__ volatile(\"time_cfg %[r], %[c]\" : [r] \"=r\"(reg_value) : [c] \"r\"(reg_config));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n#endif /* !DPU_PROFILING */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/perfcounter.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PERFCOUNTER_H\n#define DPUSYSCORE_PERFCOUNTER_H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n/**\n * @file perfcounter.h\n * @brief Utilities concerning the performance counter register.\n *\n */\n\n/**\n * @typedef perfcounter_t\n * @brief A value which can be stored by the performance counter.\n */\ntypedef uint64_t perfcounter_t;\n\n/**\n * @enum perfcounter_config_t\n * @brief A configuration for the performance counter, defining what should be counted.\n *\n * @var COUNT_SAME          keep the previous configuration\n * @var COUNT_CYCLES        switch to counting clock cycles\n * @var COUNT_INSTRUCTIONS  switch to counting executed instructions\n * @var COUNT_NOTHING       does not count anything\n */\ntypedef enum _perfcounter_config_t {\n    COUNT_SAME = 0,\n    COUNT_CYCLES = 1,\n    COUNT_INSTRUCTIONS = 2,\n    COUNT_NOTHING = 3,\n} perfcounter_config_t;\n\n/**\n * @def CLOCKS_PER_SEC\n * @hideinitializer\n * @brief A number used to convert the value returned by the perfcounter_get and perfcounter_config functions into seconds,\n *        when counting clock cycles.\n */\nextern const volatile uint32_t CLOCKS_PER_SEC;\n\n/**\n * @fn perfcounter_get\n * @brief Fetch the value of the performance counter register.\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_get(void);\n\n#ifndef DPU_PROFILING\n/**\n * @fn perfcounter_config\n * @brief Configure the performance counter behavior.\n *\n * This function cannot be used when profiling an application.\n *\n * @param config        The new behavior for the performance counter register\n * @param reset_value   Whether the performance counter register should be set to 0\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value);\n#else\n#define perfcounter_config(config, reset_value)                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* !DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PERFCOUNTER_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/popcountdi2.c",
    "content": "/* ===-- popcountdi2.c - Implement __popcountdi2 ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountdi2(di_int a)\n{\n    du_int x2 = (du_int)a;\n    x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL);\n    /* Every 2 bits holds the sum of every pair of bits (32) */\n    x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) */\n    x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) */\n    su_int x = (su_int)(x2 + (x2 >> 32));\n    /* The lower 32 bits hold four 16 bit sums (5 significant bits). */\n    /*   Upper 32 bits are garbage */\n    x = x + (x >> 16);\n    /* The lower 16 bits hold two 32 bit sums (6 significant bits). */\n    /*   Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000007F; /* (7 significant bits) */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/popcountsi2.c",
    "content": "/* ===-- popcountsi2.c - Implement __popcountsi2 ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x = x - ((x >> 1) & 0x55555555);\n    /* Every 2 bits holds the sum of every pair of bits */\n    x = ((x >> 2) & 0x33333333) + (x & 0x33333333);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) */\n    x = (x + (x >> 4)) & 0x0F0F0F0F;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) */\n    x = (x + (x >> 16));\n    /* The lower 16 bits hold two 8 bit sums (5 significant bits).*/\n    /*    Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/powidf2.c",
    "content": "/* ===-- powidf2.cpp - Implement __powidf2 ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powidf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI double\n__powidf2(double a, si_int b)\n{\n    const int recip = b < 0;\n    double r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/powisf2.c",
    "content": "/*===-- powisf2.cpp - Implement __powisf2 ---------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powisf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI float\n__powisf2(float a, si_int b)\n{\n    const int recip = b < 0;\n    float r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/profiling.c",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include <profiling.h>\n#include <defs.h>\n#include <dpufault.h>\n#include <dpuruntime.h>\n#include <macro_utils.h>\n#include <stdint.h>\n#include <sysdef.h>\n\n#ifdef DPU_PROFILING\nvoid __attribute__((no_instrument_function)) profiling_start(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] != PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_ALREADY_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->start[tid] = perfcounter_value;\n}\n\nvoid __attribute__((no_instrument_function)) profiling_stop(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] == PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_NOT_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->count[tid] += perfcounter_value - context->start[tid];\n    context->start[tid] = PROFILING_RESET_VALUE;\n}\n#endif /* DPU_PROFILING */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/profiling.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PROFILING_H\n#define DPUSYSCORE_PROFILING_H\n\n/**\n * @file profiling.h\n * @brief Code section profiling management.\n */\n\n#include <attributes.h>\n#include <limits.h>\n#include <profiling_internals.h>\n\n#define PROFILING_RESET_VALUE (UINT32_MAX)\n\n/**\n * @def PROFILING_INIT\n * @hideinitializer\n * @brief Declare and initialize a profiling context associated to the given name.\n */\n#define PROFILING_INIT(_name)                                                                                                    \\\n    __section(\".dpu_profiling\") dpu_profiling_t _name = {                                                                        \\\n        .start = { [0 ...(NR_THREADS - 1)] = PROFILING_RESET_VALUE },                                                            \\\n        .count = { [0 ...(NR_THREADS - 1)] = 0 },                                                                                \\\n    }\n\n#ifdef DPU_PROFILING\n/**\n * @fn profiling_start\n * @brief Start profiling a code section.\n *\n * This function saves the perfcounter current value in the profiling context.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_start(dpu_profiling_t *context);\n\n/**\n * @fn profiling_stop\n * @brief Stop profiling a code section.\n *\n * This function gets the perfcounter current value and computes the number of cyles spent in the code section.\n * The profiling_start function must be called beforehand.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_stop(dpu_profiling_t *context);\n#else\n#define profiling_start(context)                                                                                                 \\\n    do {                                                                                                                         \\\n    } while (0)\n#define profiling_stop(context)                                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PROFILING_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/profiling_internals.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/* Shared with backends */\n\n#ifndef DPUSYSCORE_PROFILING_INTERNALS_H\n#define DPUSYSCORE_PROFILING_INTERNALS_H\n\n/**\n * @file profiling_internals.h\n * @brief Code section profiling internals.\n */\n\n#include <stdint.h>\n\n#ifndef NR_THREADS\n#ifdef DPU_NR_THREADS\n#define NR_THREADS DPU_NR_THREADS\n#else\n#error \"DPU_NR_THREADS and NR_THREADS are undefined\"\n#endif /* DPU_NR_THREADS */\n#endif /* !NR_THREADS */\n\n/**\n * @typedef dpu_profiling_t\n * @brief A profiling context.\n */\ntypedef struct {\n    uint32_t start[NR_THREADS];\n    uint32_t count[NR_THREADS];\n} dpu_profiling_t;\n\n#endif /* DPUSYSCORE_PROFILING_INTERNALS_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/sem.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <sem.h>\n\n#include <defs.h>\n#include <dpuruntime.h>\n\nvoid\nsem_take(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    char count = sem->count - 1;\n    thread_id_t tid = me();\n\n    if (count < 0) {\n        unsigned char last = sem->wait_queue;\n\n        if (last != __EMPTY_WAIT_QUEUE) {\n            unsigned char first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        } else {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        }\n\n        sem->wait_queue = tid;\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    } else {\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    }\n}\n\nvoid\nsem_give(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = sem->count + 1;\n    unsigned char last = sem->wait_queue;\n\n    if (last != __EMPTY_WAIT_QUEUE) {\n        unsigned char first = __WAIT_QUEUE_TABLE[last];\n\n        if (first == last) {\n            sem->wait_queue = __EMPTY_WAIT_QUEUE;\n        } else {\n            __WAIT_QUEUE_TABLE[last] = __WAIT_QUEUE_TABLE[first];\n        }\n\n        __resume(first, \"0\");\n    }\n\n    sem->count = count;\n    __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/sem.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEM_H\n#define DPUSYSCORE_SEM_H\n\n/**\n * @file sem.h\n * @brief Synchronization with semaphores.\n *\n * A semaphore is characterized by a counter and a wait queue. It provides two functions:\n *\n *   - Take: the counter is decremented by 1. If the counter is negative, the runtime is blocked (stop) and placed in the\n *     semaphore's wait queue, waiting to be resume by another runtime.\n *   - Give: the counter is incremented by 1. If the counter was negative before the increment, the runtime resumes the execution\n *     of the first runtime waiting in the waiting queue. In all the cases, the runtime continues its own execution.\n *\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef sem_t\n * @brief A semaphore object, as declared by SEMAPHORE_INIT.\n */\ntypedef struct sem_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} sem_t;\n\n/**\n * @def SEMAPHORE_INIT\n * @hideinitializer\n * @brief Declare and initialize a semaphore associated to the given name.\n */\n/* clang-format off */\n#define SEMAPHORE_INIT(_name, _counter)                                                                                          \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"semaphore counter must be encoded on a byte\");                       \\\n    ATOMIC_BIT_INIT(__CONCAT(semaphore_, _name));                                                                                \\\n    extern sem_t (_name);                                                                                                        \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR(_name) \",@object\\n\"                                                                                   \\\n            \".globl \" __STR(_name) \"\\n\"                                                                                          \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(semaphore_, _name))) \"\\n\"                                                     \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn sem_take\n * @brief Takes one unit in the given semaphore (cf Take definition).\n * @param sem the semaphore we want to take\n */\nvoid\nsem_take(sem_t *sem);\n\n/**\n * @fn sem_give\n * @brief Gives on unit in the given semaphore (cf Give definition).\n * @param sem the semaphore we want to give\n */\nvoid\nsem_give(sem_t *sem);\n\n#endif /* DPUSYSCORE_SEM_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEQREAD_H\n#define DPUSYSCORE_SEQREAD_H\n\n/**\n * @file seqread.h\n * @brief Sequential reading of items in MRAM.\n *\n * A sequential reader allows to parse a contiguous area in MRAM in sequence.\n * For example, if the MRAM contains an array of N structures, a sequential\n * reader on this array will automatically fetch the data into WRAM, thus\n * simplify the iterative loop on the elements.\n *\n * The size of cached area is defined by default but can be overriden by\n * defining this value in SEQREAD_CACHE_SIZE.\n *\n * The use of a sequential reader implies:\n *\n *  - first, to allocate some storage in WRAM to cache the items, using seqread_alloc.\n *  - then to initialize a reader on the MRAM area, via seqread_init\n *  - finally to iterate on the elements, invoking seqread_get whenever a new item is accessed.\n *\n */\n\n#include <stdint.h>\n#include <mram.h>\n#include <macro_utils.h>\n\n#ifndef SEQREAD_CACHE_SIZE\n/**\n * @def SEQREAD_CACHE_SIZE\n * @hideinitializer\n * @brief Size of caches used by seqread.\n */\n#define SEQREAD_CACHE_SIZE 256\n#endif\n\n_Static_assert(SEQREAD_CACHE_SIZE == 32 || SEQREAD_CACHE_SIZE == 64 || SEQREAD_CACHE_SIZE == 128 || SEQREAD_CACHE_SIZE == 256\n        || SEQREAD_CACHE_SIZE == 512 || SEQREAD_CACHE_SIZE == 1024,\n    \"seqread error: invalid cache size defined\");\n\n#define __SEQREAD_FCT(suffix) __CONCAT(__CONCAT(seqread, SEQREAD_CACHE_SIZE), suffix)\n#define __SEQREAD_ALLOC __SEQREAD_FCT(_alloc)\n#define __SEQREAD_INIT __SEQREAD_FCT(_init)\n#define __SEQREAD_GET __SEQREAD_FCT(_get)\n#define __SEQREAD_TELL __SEQREAD_FCT(_tell)\n#define __SEQREAD_SEEK __SEQREAD_FCT(_seek)\n\n/**\n * @typedef seqreader_buffer_t\n * @brief An buffer to use to initial a sequential reader.\n */\ntypedef uintptr_t seqreader_buffer_t;\n\n/**\n * @typedef seqreader_t\n * @brief An object used to perform sequential reading of MRAM.\n */\ntypedef struct {\n    seqreader_buffer_t wram_cache;\n    uintptr_t mram_addr;\n} seqreader_t;\n\nseqreader_buffer_t\n__SEQREAD_ALLOC();\n\n/**\n * @fn seqread_alloc\n * @brief Initializes an area in WRAM to cache the read buffers.\n *\n * Notice that this buffer can be re-used for different sequential reads,\n * as long as it is initialized each time to a new buffer in MRAM.\n *\n * @return A pointer to the allocated cache base address.\n */\n#define seqread_alloc __SEQREAD_ALLOC\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_init\n * @brief Creates a sequential reader.\n *\n * The reader is associated to an existing cache in WRAM, created with\n * seqread_alloc and a contiguous area of data in MRAM. The function\n * loads the first pages of data into the cache and provides a pointer\n * to the first byte in cache actually mapping the expected data.\n *\n * Notice that the provided MRAM address does not need to be aligned on\n * any constraint: the routine does the alignment automatically.\n *\n * @param cache the reader's cache in WRAM\n * @param mram_addr the buffer address in MRAM\n * @param reader the sequential reader to init to the supplied MRAM address\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_init __SEQREAD_INIT\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader);\n\n/**\n * @fn seqread_get\n * @brief Fetches the next item in a sequence.\n *\n * This operation basically consists in incrementing the pointer that goes\n * through the mapped area of memory. The function automatically reloads\n * data from cache if necessary.\n *\n * As a result, the provided pointer to the cache area is set to its new value.\n *\n * The provided increment must be less than SEQREAD_CACHE_SIZE. The reader's\n * behavior is undefined if the increment exceeds this value.\n *\n * @param ptr the incremented pointer\n * @param inc the number of bytes added to this pointer\n * @param reader a pointer to the sequential reader\n * @return The updated pointer value.\n */\n#define seqread_get __SEQREAD_GET\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_seek\n * @brief Set the position of the cache to the supplied MRAM address\n *\n * Update automatically the cache if necessary.\n *\n * @param mram_addr the new buffer address in MRAM\n * @param reader a pointer to the sequential reader\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_seek __SEQREAD_SEEK\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader);\n\n/**\n * @fn seqread_tell\n * @brief Get the MRAM address corresponding to the supplied ptr in the cache\n *\n * @param ptr a pointer in the cache\n * @param reader a pointer to the sequential reader\n * @return A ptr to the MRAM address corresponding to the supplied pointer in the cache\n */\n#define seqread_tell __SEQREAD_TELL\n\n#endif /* DPUSYSCORE_SEQREAD_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread.inc",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <seqread.h>\n#include <mram.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <stddef.h>\n\n#define PAGE_SIZE (SEQREAD_CACHE_SIZE)\n#define PAGE_ALLOC_SIZE (2 * PAGE_SIZE)\n#define PAGE_OFF_MASK (PAGE_SIZE - 1)\n#define PAGE_IDX_MASK (~PAGE_OFF_MASK)\n\n#define MRAM_READ_PAGE(from, to) mram_read((__mram_ptr void *)(from), (void *)(to), PAGE_ALLOC_SIZE)\n\nextern void *\nmem_alloc_nolock(size_t size);\nATOMIC_BIT_EXTERN(__heap_pointer);\n\nseqreader_buffer_t\n__SEQREAD_ALLOC(void)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    unsigned int heap_pointer = __HEAP_POINTER;\n    seqreader_buffer_t pointer = (seqreader_buffer_t)((heap_pointer + PAGE_OFF_MASK) & PAGE_IDX_MASK);\n    size_t size = pointer + PAGE_ALLOC_SIZE - heap_pointer;\n    /* We already compute the return pointer\n     * mem_alloc_nolock is only used to really reserve the memory area in the heap */\n    mem_alloc_nolock(size);\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return pointer;\n}\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    reader->wram_cache = cache;\n    reader->mram_addr = (uintptr_t)(1 << __DPU_MRAM_SIZE_LOG2);\n\n    return __SEQREAD_SEEK(mram_addr, reader);\n}\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader)\n{\n    return (void *)__builtin_dpu_seqread_get((uintptr_t)ptr, inc, reader, PAGE_SIZE);\n}\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    uintptr_t target_addr = (uintptr_t)mram_addr;\n    uintptr_t current_addr = (uintptr_t)reader->mram_addr;\n    uintptr_t wram_cache = (uintptr_t)reader->wram_cache;\n    uintptr_t mram_offset = target_addr - current_addr;\n    if ((mram_offset & PAGE_IDX_MASK) != 0) {\n        uintptr_t target_addr_idx_page = target_addr & PAGE_IDX_MASK;\n        MRAM_READ_PAGE(target_addr_idx_page, wram_cache);\n        mram_offset = target_addr & PAGE_OFF_MASK;\n        reader->mram_addr = target_addr_idx_page;\n    }\n    return (void *)(mram_offset + wram_cache);\n}\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader)\n{\n    return (__mram_ptr void *)((uintptr_t)reader->mram_addr + ((uintptr_t)ptr & PAGE_OFF_MASK));\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread1024.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 1024\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread128.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 128\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread256.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 256\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 32\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread512.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 512\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/seqread64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 64\n#include <seqread.inc>\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/soft_cache.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <attributes.h>\n\nunsigned long __sw_cache_buffer[NR_THREADS] __dma_aligned __used;\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/soft_cache.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SOFT_CACHE_H\n#define DPUSYSCORE_SOFT_CACHE_H\n\n/**\n * @file soft_cache.h\n * @brief Software cache\n *\n * The software cache mechanism emulates a hardware cache to transparently load and store data from and to the\n * MRAM.\n *\n * This mechanism is quite slow, thus would only be used during the development process, to simplify the code.\n *\n * This module defines:\n *\n *  - A procedure to start the software cache, by creating a \"virtual TLB\" in the system, along with an area in WRAM to contain\n *    the cached MRAM pages\n *  - A procedure to flush the cache at the end of an execution, ensuring that the data in MRAM are consistent with the cached\n *    data\n *  - The special C directive \"__mram\", used to declare a pointer directly representing a buffer in MRAM.\n *\n * An MRAM pointer is mapped by the caching system. As a consequence, any access to data within this buffer is trapped\n * by a cache load or store procedure, transparently performing the required memory transactions to fetch and write back\n * the data.\n *\n */\n\n#include <attributes.h>\n\n#endif /* DPUSYSCORE_SOFT_CACHE_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/subdf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subdf3(fp_t a, fp_t b)\n{\n    return __adddf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dsub(fp_t a, fp_t b)\n{\n    return __subdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/subsf3.c",
    "content": "//===-- lib/subsf3.c - Single-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subsf3(fp_t a, fp_t b)\n{\n    return __addsf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fsub(fp_t a, fp_t b)\n{\n    return __subsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/subvdi3.c",
    "content": "/* ===-- subvdi3.c - Implement __subvdi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI di_int\n__subvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a - (du_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/subvsi3.c",
    "content": "/* ===-- subvsi3.c - Implement __subvsi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI si_int\n__subvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a - (su_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/sysdef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SYSDEF_H\n#define DPUSYSCORE_SYSDEF_H\n\n/**\n * @file sysdef.h\n * @brief Provides useful system abstractions.\n */\n\n/**\n * @typedef thread_id_t\n * @brief A unique runtime number.\n */\ntypedef unsigned int thread_id_t;\n\n/**\n * @typedef sysname_t\n * @brief A system name.\n *\n * Used to name system structures, like mutexes, semaphores, meetpoints, etc... In practice, system names\n * are integers, representing a unique identifier for the given type of structure.\n */\ntypedef unsigned int sysname_t;\n\n#endif /* DPUSYSCORE_SYSDEF_H */\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/truncdfhf2.c",
    "content": "//===-- lib/truncdfhf2.c - double -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI uint16_t\n__truncdfhf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_d2h(double a)\n{\n    return __truncdfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/truncdfsf2.c",
    "content": "//===-- lib/truncdfsf2.c - double -> single conversion ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_SINGLE\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI float\n__truncdfsf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_d2f(double a)\n{\n    return __truncdfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/truncsfhf2.c",
    "content": "//===-- lib/truncsfhf2.c - single -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_SINGLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE uint16_t\n__truncsfhf2(float a)\n{\n    return __truncXfYf2__(a);\n}\n\nCOMPILER_RT_ABI uint16_t\n__gnu_f2h_ieee(float a)\n{\n    return __truncsfhf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_f2h(float a)\n{\n    return __truncsfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/ucmpdi2.c",
    "content": "/* ===-- ucmpdi2.c - Implement __ucmpdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ucmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns:  if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__ucmpdi2(du_int a, du_int b)\n{\n    udwords x;\n    x.all = a;\n    udwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_ulcmp(di_int a, di_int b)\n{\n    return __ucmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/udiv64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication unsigned division.\n */\n#include <stdint.h>\n#include <dpuruntime.h>\n\nstatic unsigned int\n__clz__(uint64_t x)\n{\n    return __builtin_clzl(x);\n}\n\nuint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder)\n{\n    uint64_t dxo = dividend, dxe = 0;\n\n    if (divider == 0)\n        goto division_by_zero;\n    if (divider > dividend) {\n        if (ask_remainder == 0)\n            return 0;\n        else\n            return dividend;\n    }\n\n    // Mimic the div_step.\n    /// div_step functionality:\n    //   if (Dxo >= (Ra<< #u5)) {\n    //     Dxo = Dxo - (Ra<< #u5);\n    //     Dxe = (Dxe << 1) | 1;\n    //   } else {\n    //     Dxe =  Dxe << 1;\n    //   }\n    int dividerl0 = __clz__(divider), dividendl0 = __clz__(dividend);\n\n    int i = dividerl0 - dividendl0;\n\n    for (; i >= 0; i--) {\n        uint64_t pivot = ((uint64_t)divider << i);\n        if (dxo >= pivot) {\n            dxo = dxo - pivot;\n            dxe = ((uint64_t)dxe << 1) | 1L;\n        } else {\n            dxe = (uint64_t)dxe << 1;\n        }\n    }\n    if (ask_remainder == 1)\n        return dxo;\n    else\n        return dxe;\n\ndivision_by_zero:\n    __asm__ volatile(\"fault \" __STR(__FAULT_DIVISION_BY_ZERO__));\n    unreachable();\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/udivdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__udivdi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 0);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/udivmodsi4.c",
    "content": "/*===-- udivmodsi4.c - Implement __udivmodsi4 ------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem)\n{\n    unsigned long res = __udiv32(a, b);\n    *rem = (unsigned int)res;\n    return (unsigned int)(res >> 32);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/udivsi3.c",
    "content": "/* ===-- udivsi3.c - Implement __udivsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\n/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */\n\n/* This function should not call __divsi3! */\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d)\n{\n    const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT;\n    su_int q;\n    su_int r;\n    unsigned sr;\n    /* special cases */\n    if (d == 0)\n        return 0; /* ?! */\n    if (n == 0)\n        return 0;\n    sr = __builtin_clz(d) - __builtin_clz(n);\n    /* 0 <= sr <= n_uword_bits - 1 or sr large */\n    if (sr > n_uword_bits - 1) /* d > r */\n        return 0;\n    if (sr == n_uword_bits - 1) /* d == 1 */\n        return n;\n    ++sr;\n    /* 1 <= sr <= n_uword_bits - 1 */\n    /* Not a special case */\n    q = n << (n_uword_bits - sr);\n    r = n >> sr;\n    su_int carry = 0;\n    for (; sr > 0; --sr) {\n        /* r:q = ((r:q)  << 1) | carry */\n        r = (r << 1) | (q >> (n_uword_bits - 1));\n        q = (q << 1) | carry;\n        /* carry = 0;\n         * if (r.all >= d.all)\n         * {\n         *      r.all -= d.all;\n         *      carry = 1;\n         * }\n         */\n        const si_int s = (si_int)(d - r - 1) >> (n_uword_bits - 1);\n        carry = s & 1;\n        r -= d & s;\n    }\n    q = (q << 1) | carry;\n    return q;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_uidiv(su_int n, su_int d)\n{\n    return __udivsi3(n, d);\n}\n#endif\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/umoddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned remainder.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__umoddi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 1);\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/umodsi3.c",
    "content": "/* ===-- umodsi3.c - Implement __umodsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __umodsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__umodsi3(su_int a, su_int b)\n{\n    unsigned long res = __udiv32(a, b);\n    return (unsigned int)res;\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/sdk/syslib/waitqueue.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nunsigned char __attribute__((used)) __sys_wq_table[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/abi/intermediate.go",
    "content": "package abi\n\nimport (\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Immediate struct {\n\trepresentation Representation\n\tvalue          int64\n\tword           *Word\n}\n\nfunc (this *Immediate) Init(representation Representation, width int, value int64) {\n\tthis.representation = representation\n\tthis.value = value\n\n\tthis.word = new(Word)\n\tthis.word.Init(width)\n\tthis.word.SetValue(value)\n}\n\nfunc (this *Immediate) Representation() Representation {\n\treturn this.representation\n}\n\nfunc (this *Immediate) Width() int {\n\treturn this.word.Width()\n}\n\nfunc (this *Immediate) Bit(pos int) bool {\n\treturn this.word.Bit(pos)\n}\n\nfunc (this *Immediate) BitSlice(begin int, end int) int64 {\n\treturn this.word.BitSlice(this.representation, begin, end)\n}\n\nfunc (this *Immediate) Value() int64 {\n\treturn this.value\n}\n\nfunc (this *Immediate) ToByteStream() *encoding.ByteStream {\n\treturn this.word.ToByteStream()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/abi/word.go",
    "content": "package abi\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Representation int\n\nconst (\n\tUNSIGNED Representation = iota\n\tSIGNED\n)\n\ntype Word struct {\n\tbits []bool\n}\n\nfunc (this *Word) Init(width int) {\n\tif width <= 0 {\n\t\terr := errors.New(\"width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.bits = make([]bool, width)\n}\n\nfunc (this *Word) Width() int {\n\treturn len(this.bits)\n}\n\nfunc (this *Word) Size() int {\n\tif this.Width()%8 != 0 {\n\t\terr := errors.New(\"width is not a multiple of 8\")\n\t\tpanic(err)\n\t}\n\n\treturn this.Width() / 8\n}\n\nfunc (this *Word) SignBit() bool {\n\treturn this.bits[this.Width()-1]\n}\n\nfunc (this *Word) Bit(pos int) bool {\n\treturn this.bits[pos]\n}\n\nfunc (this *Word) SetBit(pos int) {\n\tthis.bits[pos] = true\n}\n\nfunc (this *Word) ClearBit(pos int) {\n\tthis.bits[pos] = false\n}\n\nfunc (this *Word) BitSlice(representation Representation, begin int, end int) int64 {\n\tthis.VerifySlice(begin, end)\n\n\tslice_width := end - begin\n\tvalue := int64(0)\n\tfor i := 0; i < slice_width; i++ {\n\t\tif this.Bit(begin + i) {\n\t\t\tif representation == SIGNED && i == slice_width-1 {\n\t\t\t\tvalue -= this.Pow2(i)\n\t\t\t} else {\n\t\t\t\tvalue += this.Pow2(i)\n\t\t\t}\n\t\t}\n\t}\n\treturn value\n}\n\nfunc (this *Word) SetBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value >= 0 {\n\t\tthis.SetPositiveBitSlice(begin, end, value)\n\t} else {\n\t\tthis.SetNegativeBitSlice(begin, end, value)\n\t}\n}\n\nfunc (this *Word) Value(representation Representation) int64 {\n\treturn this.BitSlice(representation, 0, this.Width())\n}\n\nfunc (this *Word) SetValue(value int64) {\n\tthis.SetBitSlice(0, this.Width(), value)\n}\n\nfunc (this *Word) ToByteStream() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := 0; i < this.Size(); i++ {\n\t\tbegin := 8 * i\n\t\tend := begin + 8\n\n\t\tvalue := uint8(this.BitSlice(UNSIGNED, begin, end))\n\t\tbyte_stream.Append(value)\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Word) FromByteStream(byte_stream *encoding.ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tbegin := int(8 * i)\n\t\tend := int(begin + 8)\n\n\t\tvalue := int64(byte_stream.Get(int(i)))\n\t\tthis.SetBitSlice(begin, end, value)\n\t}\n}\n\nfunc (this *Word) VerifySlice(begin int, end int) {\n\tif begin < 0 {\n\t\terr := errors.New(\"begin < 0\")\n\t\tpanic(err)\n\t}\n\n\tif begin >= end {\n\t\terr := errors.New(\"begin >= end\")\n\t\tpanic(err)\n\t}\n\n\tif end > this.Width() {\n\t\terr := errors.New(\"end > width\")\n\t\tpanic(err)\n\t}\n\n\tif end-begin > 64 {\n\t\terr := errors.New(\"end - begin >= 64\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Word) Pow2(exponent int) int64 {\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n\nfunc (this *Word) SetPositiveBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value < 0 {\n\t\terr := errors.New(\"value < 0\")\n\t\tpanic(err)\n\t}\n\n\tslice_width := end - begin\n\tfor i := 0; i < slice_width; i++ {\n\t\tif value%2 == 1 {\n\t\t\tthis.SetBit(begin + i)\n\t\t} else {\n\t\t\tthis.ClearBit(begin + i)\n\t\t}\n\n\t\tvalue /= 2\n\t}\n\n\tif value != 0 {\n\t\terr := errors.New(\"value != 0\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Word) SetNegativeBitSlice(begin int, end int, value int64) {\n\tthis.VerifySlice(begin, end)\n\n\tif value >= 0 {\n\t\terr := errors.New(\"value >= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.SetBit(end - 1)\n\n\tif begin+1 < end {\n\t\tslice_width := end - begin\n\t\tvalue += this.Pow2(slice_width - 1)\n\t\tthis.SetPositiveBitSlice(begin, end-1, value)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/compiler/compiler.go",
    "content": "package compiler\n\nimport (\n\t\"os/exec\"\n\t\"path/filepath\"\n\t\"strconv\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Compiler struct {\n\troot_dirpath string\n\tbenchmark    string\n\n\tnum_dpus     int\n\tnum_tasklets int\n}\n\nfunc (this *Compiler) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.root_dirpath = command_line_parser.StringParameter(\"root_dirpath\")\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.Build()\n}\n\nfunc (this *Compiler) Build() {\n\tdocker_dirpath := filepath.Join(this.root_dirpath, \"docker\")\n\n\tcommand := exec.Command(\"docker\", \"build\", \"-t\", \"bongjoonhyun/upimulator\", docker_dirpath)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Compiler) Compile() {\n\tthis.CompileBenchmark()\n\tthis.CompileSdk()\n}\n\nfunc (this *Compiler) CompileBenchmark() {\n\tcommand := exec.Command(\n\t\t\"docker\",\n\t\t\"run\",\n\t\t\"--privileged\",\n\t\t\"--rm\",\n\t\t\"-v\",\n\t\tthis.root_dirpath+\":/root/uPIMulator\",\n\t\t\"bongjoonhyun/upimulator\",\n\t\t\"python3\",\n\t\t\"/root/uPIMulator/benchmark/build.py\",\n\t\t\"--num_dpus\",\n\t\tstrconv.Itoa(this.num_dpus),\n\t\t\"--num_tasklets\",\n\t\tstrconv.Itoa(this.num_tasklets),\n\t)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Compiler) CompileSdk() {\n\tcommand := exec.Command(\n\t\t\"docker\",\n\t\t\"run\",\n\t\t\"--privileged\",\n\t\t\"--rm\",\n\t\t\"-v\",\n\t\tthis.root_dirpath+\":/root/uPIMulator\",\n\t\t\"bongjoonhyun/upimulator\",\n\t\t\"python3\",\n\t\t\"/root/uPIMulator/sdk/build.py\",\n\t\t\"--num_tasklets\",\n\t\tstrconv.Itoa(this.num_tasklets),\n\t)\n\n\terr := command.Run()\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/core/job.go",
    "content": "package core\n\ntype Job interface {\n\tExecute()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/core/thread_pool.go",
    "content": "package core\n\nimport (\n\t\"sync\"\n)\n\ntype ThreadPool struct {\n\tjobs []Job\n\n\twg sync.WaitGroup\n}\n\nfunc (this *ThreadPool) Init() {\n\tthis.jobs = make([]Job, 0)\n}\n\nfunc (this *ThreadPool) Enque(job Job) {\n\tthis.wg.Add(1)\n\tthis.jobs = append(this.jobs, job)\n}\n\nfunc (this *ThreadPool) Start() {\n\tfor _, job := range this.jobs {\n\t\tgo this.Dispatch(job)\n\t}\n\tthis.wg.Wait()\n}\n\nfunc (this *ThreadPool) Dispatch(job Job) {\n\tdefer this.wg.Done()\n\tjob.Execute()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/analyze_liveness_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/logic\"\n)\n\ntype AnalyzeLivenessJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *AnalyzeLivenessJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *AnalyzeLivenessJob) Execute() {\n\tfmt.Printf(\"Analyzing the liveness of %s...\\n\", this.relocatable.Path())\n\n\tliveness_analyzer := new(logic.LivenessAnalyzer)\n\tliveness_analyzer.Init()\n\n\tliveness := liveness_analyzer.Analyze(this.relocatable)\n\tthis.relocatable.SetLiveness(liveness)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/ascii_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/encoding\"\n)\n\ntype AsciiDirective struct {\n\tcharacters string\n}\n\nfunc (this *AsciiDirective) Init(characters string) {\n\tthis.characters = characters\n}\n\nfunc (this *AsciiDirective) Characters() string {\n\treturn this.characters\n}\n\nfunc (this *AsciiDirective) Size() int64 {\n\treturn int64(len(this.characters))\n}\n\nfunc (this *AsciiDirective) Encode() *encoding.ByteStream {\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\treturn ascii_encoder.Encode(this.characters)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/asciz_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/encoding\"\n)\n\ntype AscizDirective struct {\n\tcharacters string\n}\n\nfunc (this *AscizDirective) Init(characters string) {\n\tthis.characters = characters\n}\n\nfunc (this *AscizDirective) Characters() string {\n\treturn this.characters\n}\n\nfunc (this *AscizDirective) Size() int64 {\n\treturn int64(len(this.characters)) + 1\n}\n\nfunc (this *AscizDirective) Encode() *encoding.ByteStream {\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\treturn ascii_encoder.Encode(this.characters + ascii_encoder.Unknown())\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/byte_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype ByteDirective struct {\n\timmediate *abi.Immediate\n}\n\nfunc (this *ByteDirective) Init(value int64) {\n\tthis.immediate = new(abi.Immediate)\n\tthis.immediate.Init(abi.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *ByteDirective) Size() int64 {\n\treturn 1\n}\n\nfunc (this *ByteDirective) Immediate() *abi.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ByteDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/long_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype LongDirective struct {\n\timmediate *abi.Immediate\n}\n\nfunc (this *LongDirective) Init(value int64) {\n\tthis.immediate = new(abi.Immediate)\n\tthis.immediate.Init(abi.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *LongDirective) Size() int64 {\n\treturn 4\n}\n\nfunc (this *LongDirective) Immediate() *abi.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *LongDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/quad_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype QuadDirective struct {\n\timmediate *abi.Immediate\n}\n\nfunc (this *QuadDirective) Init(value int64) {\n\tthis.immediate = new(abi.Immediate)\n\tthis.immediate.Init(abi.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *QuadDirective) Size() int64 {\n\treturn 8\n}\n\nfunc (this *QuadDirective) Immediate() *abi.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *QuadDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/short_directive.go",
    "content": "package directive\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype ShortDirective struct {\n\timmediate *abi.Immediate\n}\n\nfunc (this *ShortDirective) Init(value int64) {\n\tthis.immediate = new(abi.Immediate)\n\tthis.immediate.Init(abi.UNSIGNED, 8*int(this.Size()), value)\n}\n\nfunc (this *ShortDirective) Size() int64 {\n\treturn 2\n}\n\nfunc (this *ShortDirective) Immediate() *abi.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ShortDirective) Encode() *encoding.ByteStream {\n\treturn this.immediate.ToByteStream()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/directive/zero_directive.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype ZeroDirective struct {\n\tsize      int64\n\timmediate *abi.Immediate\n}\n\nfunc (this *ZeroDirective) Init(size int64, value int64) {\n\tif size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\n\tthis.immediate = new(abi.Immediate)\n\tthis.immediate.Init(abi.UNSIGNED, 8, value)\n}\n\nfunc (this *ZeroDirective) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *ZeroDirective) Immediate() *abi.Immediate {\n\treturn this.immediate\n}\n\nfunc (this *ZeroDirective) Encode() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < this.size; i++ {\n\t\tbyte_stream.Merge(this.immediate.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/encodable.go",
    "content": "package kernel\n\nimport (\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Encodable interface {\n\tEncode() *encoding.ByteStream\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/executable.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"sort\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Executable struct {\n\tname string\n\tpath string\n\n\tbenchmark_relocatable *Relocatable\n\tsdk_relocatables      map[*Relocatable]bool\n\n\ttoken_stream *lexer.TokenStream\n\tast          *parser.Ast\n\tliveness     *Liveness\n\n\tsections    map[*Section]bool\n\tcur_section *Section\n}\n\nfunc (this *Executable) Init(name string) {\n\tthis.name = name\n\n\tthis.sdk_relocatables = make(map[*Relocatable]bool)\n\n\tthis.liveness = new(Liveness)\n\tthis.liveness.Init()\n\n\tthis.sections = make(map[*Section]bool)\n}\n\nfunc (this *Executable) Name() string {\n\treturn this.name\n}\n\nfunc (this *Executable) Path() string {\n\treturn this.path\n}\n\nfunc (this *Executable) SetPath(path string) {\n\tthis.path = path\n}\n\nfunc (this *Executable) SetBenchmarkRelocatable(relocatable *Relocatable) {\n\tthis.benchmark_relocatable = relocatable\n\n\tthis.UpdateUnresolvedSymbols(relocatable)\n}\n\nfunc (this *Executable) AddSdkRelocatable(relocatable *Relocatable) {\n\tthis.sdk_relocatables[relocatable] = true\n\n\tthis.UpdateLocalSymbols(relocatable)\n\tthis.UpdateUnresolvedSymbols(relocatable)\n}\n\nfunc (this *Executable) TokenStream() *lexer.TokenStream {\n\treturn this.token_stream\n}\n\nfunc (this *Executable) SetTokenStream(token_stream *lexer.TokenStream) {\n\tthis.token_stream = token_stream\n}\n\nfunc (this *Executable) Ast() *parser.Ast {\n\treturn this.ast\n}\n\nfunc (this *Executable) SetAst(ast *parser.Ast) {\n\tthis.ast = ast\n}\n\nfunc (this *Executable) Liveness() *Liveness {\n\treturn this.liveness\n}\n\nfunc (this *Executable) DumpAssembly() {\n\tlines := this.benchmark_relocatable.Lines()\n\n\tfor sdk_relocatable, _ := range this.sdk_relocatables {\n\t\tlines = append(lines, sdk_relocatable.Lines()...)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(this.path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpAddresses(path string) {\n\tlines := make([]string, 0)\n\n\tfor label_name, label_address := range this.Addresses() {\n\t\tline := fmt.Sprintf(\"%s: %d\", label_name, label_address)\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpAtomic(path string) {\n\tatomic_byte_stream := this.AtomicByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < atomic_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", atomic_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpIram(path string) {\n\tiram_byte_stream := this.IramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < iram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", iram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpWram(path string) {\n\twram_byte_stream := this.WramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < wram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", wram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) DumpMram(path string) {\n\tmram_byte_stream := this.MramByteStream()\n\n\tlines := make([]string, 0)\n\tfor i := int64(0); i < mram_byte_stream.Size(); i++ {\n\t\tline := fmt.Sprintf(\"%d\", mram_byte_stream.Get(int(i)))\n\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *Executable) Section(section_name SectionName, name string) *Section {\n\tfor section, _ := range this.sections {\n\t\tif section.SectionName() == section_name && section.Name() == name {\n\t\t\treturn section\n\t\t}\n\t}\n\treturn nil\n}\n\nfunc (this *Executable) Sections(section_name SectionName) map[*Section]bool {\n\tsections := make(map[*Section]bool)\n\tfor section, _ := range this.sections {\n\t\tif section.SectionName() == section_name {\n\t\t\tsections[section] = true\n\t\t}\n\t}\n\treturn sections\n}\n\nfunc (this *Executable) AddSection(\n\tsection_name SectionName,\n\tname string,\n\tsection_flags map[SectionFlag]bool,\n\tsection_type SectionType,\n) {\n\tif this.Section(section_name, name) == nil {\n\t\tsection := new(Section)\n\t\tsection.Init(section_name, name, section_flags, section_type)\n\t\tthis.sections[section] = true\n\t}\n}\n\nfunc (this *Executable) CurSection() *Section {\n\treturn this.cur_section\n}\n\nfunc (this *Executable) CheckoutSection(section_name SectionName, name string) {\n\tif section := this.Section(section_name, name); section != nil {\n\t\tthis.cur_section = section\n\t} else {\n\t\terr := errors.New(\"section is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Executable) Label(label_name string) *Label {\n\tvar label *Label = nil\n\tfor section, _ := range this.sections {\n\t\tsection_label := section.Label(label_name)\n\n\t\tif section_label != nil {\n\t\t\tif label != nil {\n\t\t\t\terr := errors.New(\"labels are duplicated\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tlabel = section_label\n\t\t}\n\t}\n\treturn label\n}\n\nfunc (this *Executable) Addresses() map[string]int64 {\n\taddresses := make(map[string]int64)\n\tfor section, _ := range this.sections {\n\t\tfor _, label := range section.Labels() {\n\t\t\taddresses[label.Name()] = label.Address()\n\t\t}\n\t}\n\treturn addresses\n}\n\nfunc (this *Executable) AtomicByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tatomic_sections := this.Sort(\n\t\tconfig_loader.AtomicOffset(),\n\t\tconfig_loader.AtomicOffset()+config_loader.AtomicSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, atomic_section := range atomic_sections {\n\t\tbyte_stream.Merge(atomic_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) IramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_sections := this.Sort(\n\t\tconfig_loader.IramOffset(),\n\t\tconfig_loader.IramOffset()+config_loader.IramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, iram_section := range iram_sections {\n\t\tbyte_stream.Merge(iram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) WramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_sections := this.Sort(\n\t\tconfig_loader.WramOffset(),\n\t\tconfig_loader.WramOffset()+config_loader.WramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, wram_section := range wram_sections {\n\t\tbyte_stream.Merge(wram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) MramByteStream() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_sections := this.Sort(\n\t\tconfig_loader.MramOffset(),\n\t\tconfig_loader.MramOffset()+config_loader.MramSize(),\n\t)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, mram_section := range mram_sections {\n\t\tbyte_stream.Merge(mram_section.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Executable) UpdateLocalSymbols(relocatable *Relocatable) {\n\tfor old_name, _ := range relocatable.Liveness().LocalSymbols() {\n\t\tnew_name := relocatable.Name() + \".\" + old_name\n\n\t\trelocatable.RenameLocalSymbol(old_name, new_name)\n\t}\n}\n\nfunc (this *Executable) UpdateUnresolvedSymbols(relocatable *Relocatable) {\n\tfor def, _ := range relocatable.Liveness().Defs() {\n\t\tthis.liveness.AddDef(def)\n\t}\n\n\tfor use, _ := range relocatable.Liveness().Uses() {\n\t\tthis.liveness.AddUse(use)\n\t}\n\n\tfor global_symbol, _ := range relocatable.Liveness().GlobalSymbols() {\n\t\tthis.liveness.AddGlobalSymbol(global_symbol)\n\t}\n}\n\nfunc (this *Executable) Sort(begin_address int64, end_address int64) []*Section {\n\tsections := make([]*Section, 0)\n\n\tfor section, _ := range this.sections {\n\t\taddress := section.Address()\n\n\t\tif begin_address <= address && address < end_address {\n\t\t\tsections = append(sections, section)\n\t\t}\n\t}\n\n\tsort_fn := func(i int, j int) bool {\n\t\treturn sections[i].Address() < sections[j].Address()\n\t}\n\n\tsort.Slice(sections, sort_fn)\n\n\treturn sections\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/acquire_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype AcquireCc struct {\n\tcondition Condition\n}\n\nfunc (this *AcquireCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *AcquireCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/add_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype AddNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *AddNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tNC5:  true,\n\t\tNC6:  true,\n\t\tNC7:  true,\n\t\tNC8:  true,\n\t\tNC9:  true,\n\t\tNC10: true,\n\t\tNC11: true,\n\t\tNC12: true,\n\t\tNC13: true,\n\t\tNC14: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *AddNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/boot_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype BootCc struct {\n\tcondition Condition\n}\n\nfunc (this *BootCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *BootCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/cc.go",
    "content": "package cc\n\ntype Condition int\n\nconst (\n\tTRUE Condition = iota\n\tFALSE\n\n\tZ\n\tNZ\n\n\tE\n\tO\n\n\tPL\n\tMI\n\n\tOV\n\tNOV\n\n\tC\n\tNC\n\n\tSZ\n\tSNZ\n\n\tSPL\n\tSMI\n\n\tSO\n\tSE\n\n\tNC5\n\tNC6\n\tNC7\n\tNC8\n\tNC9\n\tNC10\n\tNC11\n\tNC12\n\tNC13\n\tNC14\n\n\tMAX\n\tNMAX\n\n\tSH32\n\tNSH32\n\n\tEQ\n\tNEQ\n\n\tLTU\n\tLEU\n\tGTU\n\tGEU\n\n\tLTS\n\tLES\n\tGTS\n\tGES\n\n\tXZ\n\tXNZ\n\n\tXLEU\n\tXGTU\n\n\tXLES\n\tXGTS\n\n\tSMALL\n\tLARGE\n)\n\ntype Cc interface {\n\tCondition() Condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/const_cc_ge0.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcGe0 struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcGe0) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tPL: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcGe0) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/const_cc_geu.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcGeu struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcGeu) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tGEU: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcGeu) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/const_cc_zero.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ConstCcZero struct {\n\tcondition Condition\n}\n\nfunc (this *ConstCcZero) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ConstCcZero) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/count_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype CountNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *CountNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tMAX:  true,\n\t\tNMAX: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *CountNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/div_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype DivCc struct {\n\tcondition Condition\n}\n\nfunc (this *DivCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *DivCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/div_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype DivNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *DivNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *DivNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/ext_sub_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ExtSubSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *ExtSubSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tEQ:   true,\n\t\tNEQ:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tGES:  true,\n\t\tGEU:  true,\n\t\tGTS:  true,\n\t\tGTU:  true,\n\t\tLES:  true,\n\t\tLEU:  true,\n\t\tLTS:  true,\n\t\tLTU:  true,\n\t\tXGTS: true,\n\t\tXGTU: true,\n\t\tXLES: true,\n\t\tXLEU: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ExtSubSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/false_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype FalseCc struct {\n\tcondition Condition\n}\n\nfunc (this *FalseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *FalseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/imm_shift_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ImmShiftNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *ImmShiftNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tE:    true,\n\t\tO:    true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tSE:   true,\n\t\tSO:   true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ImmShiftNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/log_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype LogNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *LogNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tPL:   true,\n\t\tMI:   true,\n\t\tSZ:   true,\n\t\tSNZ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *LogNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/log_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype LogSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *LogSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:   true,\n\t\tNZ:  true,\n\t\tXZ:  true,\n\t\tXNZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *LogSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/mul_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype MulNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *MulNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tLARGE: true,\n\t\tSMALL: true,\n\t\tTRUE:  true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *MulNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/no_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype NoCc struct {\n\tcondition Condition\n}\n\nfunc (this *NoCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *NoCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/release_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ReleaseCc struct {\n\tcondition Condition\n}\n\nfunc (this *ReleaseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tNZ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ReleaseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/shift_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype ShiftNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *ShiftNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:     true,\n\t\tNZ:    true,\n\t\tXZ:    true,\n\t\tXNZ:   true,\n\t\tE:     true,\n\t\tO:     true,\n\t\tPL:    true,\n\t\tMI:    true,\n\t\tSZ:    true,\n\t\tSNZ:   true,\n\t\tSE:    true,\n\t\tSO:    true,\n\t\tSPL:   true,\n\t\tSMI:   true,\n\t\tSH32:  true,\n\t\tNSH32: true,\n\t\tTRUE:  true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *ShiftNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/sub_nz_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype SubNzCc struct {\n\tcondition Condition\n}\n\nfunc (this *SubNzCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tC:    true,\n\t\tNC:   true,\n\t\tZ:    true,\n\t\tNZ:   true,\n\t\tXZ:   true,\n\t\tXNZ:  true,\n\t\tOV:   true,\n\t\tNOV:  true,\n\t\tMI:   true,\n\t\tPL:   true,\n\t\tEQ:   true,\n\t\tNEQ:  true,\n\t\tSPL:  true,\n\t\tSMI:  true,\n\t\tGES:  true,\n\t\tGEU:  true,\n\t\tGTS:  true,\n\t\tGTU:  true,\n\t\tLES:  true,\n\t\tLEU:  true,\n\t\tLTS:  true,\n\t\tLTU:  true,\n\t\tXGTS: true,\n\t\tXGTU: true,\n\t\tXLES: true,\n\t\tXLEU: true,\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *SubNzCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/sub_set_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype SubSetCc struct {\n\tcondition Condition\n}\n\nfunc (this *SubSetCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tZ:   true,\n\t\tNZ:  true,\n\t\tXZ:  true,\n\t\tXNZ: true,\n\t\tEQ:  true,\n\t\tNEQ: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *SubSetCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/true_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype TrueCc struct {\n\tcondition Condition\n}\n\nfunc (this *TrueCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tTRUE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *TrueCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/cc/true_false_cc.go",
    "content": "package cc\n\nimport (\n\t\"errors\"\n)\n\ntype TrueFalseCc struct {\n\tcondition Condition\n}\n\nfunc (this *TrueFalseCc) Init(condition Condition) {\n\tconditions := map[Condition]bool{\n\t\tTRUE:  true,\n\t\tFALSE: true,\n\t}\n\n\tif _, found := conditions[condition]; !found {\n\t\terr := errors.New(\"condition is not allowed\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n}\n\nfunc (this *TrueFalseCc) Condition() Condition {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/endian.go",
    "content": "package instruction\n\ntype Endian int\n\nconst (\n\tLITTLE Endian = iota\n\tBIG\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/exception.go",
    "content": "package instruction\n\ntype Exception int\n\nconst (\n\tMEMORY_FAULT Exception = iota\n\tDMA_FAULT\n\tHEAP_FULL\n\tDIVISION_BY_ZERO\n\tASSERT\n\tHALT\n\tPRINT_OVERFLOW\n\tALREADY_PROFILING\n\tNOT_PROFILING\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/flag.go",
    "content": "package instruction\n\ntype Flag int\n\nconst (\n\tZERO Flag = iota\n\tCARRY\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/instruction.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"math\"\n\t\"strconv\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Instruction struct {\n\top_code OpCode\n\tsuffix  Suffix\n\n\trc *reg_descriptor.GpRegDescriptor\n\tra *reg_descriptor.SrcRegDescriptor\n\trb *reg_descriptor.SrcRegDescriptor\n\n\tdc *reg_descriptor.PairRegDescriptor\n\tdb *reg_descriptor.PairRegDescriptor\n\n\tcondition *cc.Condition\n\n\timm *abi.Immediate\n\toff *abi.Immediate\n\tpc  *abi.Immediate\n\n\tendian *Endian\n}\n\nfunc (this *Instruction) InitRici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RiciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RICI\n\tthis.ra = ra\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 16, imm)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = condition\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRri(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRric(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRIC\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\t\text_sub_setcc := new(cc.ExtSubSetCc)\n\t\text_sub_setcc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_setcc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRrici(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRICI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRrif(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRIF\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tfalse_cc := new(cc.FalseCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitRrr(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRR\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitRrrc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRC\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitRrrci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRCI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZri(op_code OpCode, ra *reg_descriptor.SrcRegDescriptor, imm int64) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRI\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 28, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZric(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRIC\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 27, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 27, imm)\n\n\t\text_sub_setcc := new(cc.ExtSubSetCc)\n\t\text_sub_setcc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_setcc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZrici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRICI\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZrif(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRIF\n\tthis.ra = ra\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 27, imm)\n\n\tfalse_cc := new(cc.LogSetCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitZrr(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRR\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitZrrc(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRC\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitZrrci(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRCI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRI && suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid S_RRI nor U_RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRric(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RricOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRIC && suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[op_code]; is_asr_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid S_RRI nor U_RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRrici(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRICI && suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\t\timm_shift_nz_cc := new(cc.ImmShiftNzCc)\n\t\timm_shift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = imm_shift_nz_cc.Condition()\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRrif(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrifOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRIF && suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tfalse_cc := new(cc.FalseCc)\n\tfalse_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = false_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRrr(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRR && suffix != U_RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitSRrrc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRC && suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrc_op_code := this.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tlog_set_cc := new(cc.LogSetCc)\n\t\tlog_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_set_cc.Condition()\n\t} else if _, is_rsub_rrrc_op_code := this.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tsub_set_cc := new(cc.SubSetCc)\n\t\tsub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_set_cc.Condition()\n\t} else if _, is_sub_rrrc_op_code := this.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\text_sub_set_cc := new(cc.ExtSubSetCc)\n\t\text_sub_set_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = ext_sub_set_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) InitSRrrci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRCI && suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tif _, is_add_rrrci_op_code := this.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tadd_nz_cc := new(cc.AddNzCc)\n\t\tadd_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = add_nz_cc.Condition()\n\t} else if _, is_and_rrrci_op_code := this.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_asr_rrrci_op_code := this.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tshift_nz_cc := new(cc.ShiftNzCc)\n\t\tshift_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = shift_nz_cc.Condition()\n\t} else if _, is_mul_rrrci_op_code := this.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tmul_nz_cc := new(cc.MulNzCc)\n\t\tmul_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = mul_nz_cc.Condition()\n\t} else if _, is_rsub_rrrci_op_code := this.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tsub_nz_cc := new(cc.SubNzCc)\n\t\tsub_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = sub_nz_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRr(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RR\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitRrc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRC\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitRrci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRCI\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZr(op_code OpCode, ra *reg_descriptor.SrcRegDescriptor) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZR\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitZrc(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRC\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitZrci(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRCI\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRr(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RrOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RR && suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitSRrc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RrcOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRC && suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tlog_set_cc := new(cc.LogSetCc)\n\tlog_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = log_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRrci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRCI && suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tif _, is_cao_rrci_op_code := this.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tcount_nz_cc := new(cc.CountNzCc)\n\t\tcount_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = count_nz_cc.Condition()\n\t} else if _, is_extsb_rrci_op_code := this.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tlog_nz_cc := new(cc.LogNzCc)\n\t\tlog_nz_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = log_nz_cc.Condition()\n\t} else if _, is_time_cfg_rrci_op_code := this.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\ttrue_cc := new(cc.TrueCc)\n\t\ttrue_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = true_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitDrdici(\n\top_code OpCode,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tdb *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.DrdiciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DRDICI\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tif _, is_div_step_drdici_op_code := this.DivStepDrdiciOpCodes()[op_code]; is_div_step_drdici_op_code {\n\t\tdiv_cc := new(cc.DivCc)\n\t\tdiv_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = div_cc.Condition()\n\t} else if _, is_mul_step_drdici_op_code := this.MulStepDrdiciOpCodes()[op_code]; is_mul_step_drdici_op_code {\n\t\tboot_cc := new(cc.BootCc)\n\t\tboot_cc.Init(condition)\n\n\t\tthis.condition = new(cc.Condition)\n\t\t*this.condition = boot_cc.Condition()\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRrri(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitRrrici(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RRRICI\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZrri(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitZrrici(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZRRICI\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRrri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.RrriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRI && suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) InitSRrrici(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RrriciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RRRICI && suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tdiv_nz_cc := new(cc.DivNzCc)\n\tdiv_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = div_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitRir(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.RirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIR\n\tthis.rc = rc\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitRirc(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIRC\n\tthis.rc = rc\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitRirci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RIRCI\n\tthis.rc = rc\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZir(op_code OpCode, imm int64, ra *reg_descriptor.SrcRegDescriptor) {\n\tif _, found := this.RirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIR\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\n\tthis.ra = ra\n}\n\nfunc (this *Instruction) InitZirc(\n\top_code OpCode,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIRC\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 27, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitZirci(\n\top_code OpCode,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZIRCI\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 11, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSRirc(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n) {\n\tif _, found := this.RircOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RIRC && suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tthis.ra = ra\n\n\tsub_set_cc := new(cc.SubSetCc)\n\tsub_set_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_set_cc.Condition()\n}\n\nfunc (this *Instruction) InitSRirci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\timm int64,\n\tra *reg_descriptor.SrcRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RirciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RIRCI && suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\tthis.ra = ra\n\n\tsub_nz_cc := new(cc.SubNzCc)\n\tsub_nz_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = sub_nz_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitR(op_code OpCode, rc *reg_descriptor.GpRegDescriptor) {\n\tif _, found := this.ROpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = R\n\tthis.rc = rc\n}\n\nfunc (this *Instruction) InitRci(\n\top_code OpCode,\n\trc *reg_descriptor.GpRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = RCI\n\tthis.rc = rc\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitZ(op_code OpCode) {\n\tif _, found := this.ROpCodes()[op_code]; !found && op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = Z\n}\n\nfunc (this *Instruction) InitZci(\n\top_code OpCode,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ZCI\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitSR(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n) {\n\tif _, found := this.ROpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_R && suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n}\n\nfunc (this *Instruction) InitSRci(\n\top_code OpCode,\n\tsuffix Suffix,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.RciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_RCI && suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\n\ttrue_cc := new(cc.TrueCc)\n\ttrue_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitCi(op_code OpCode, condition cc.Condition, pc int64) {\n\tif _, found := this.CiOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = CI\n\n\tboot_cc := new(cc.BootCc)\n\tboot_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = boot_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitI(op_code OpCode, imm int64) {\n\tif _, found := this.IOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = I\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n}\n\nfunc (this *Instruction) InitDdci(\n\top_code OpCode,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tdb *reg_descriptor.PairRegDescriptor,\n\tcondition cc.Condition,\n\tpc int64,\n) {\n\tif _, found := this.DdciOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DDCI\n\n\tthis.dc = dc\n\tthis.db = db\n\n\ttrue_false_cc := new(cc.TrueFalseCc)\n\ttrue_false_cc.Init(condition)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = true_false_cc.Condition()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, config_loader.AddressWidth(), pc)\n}\n\nfunc (this *Instruction) InitErri(\n\top_code OpCode,\n\tendian Endian,\n\trc *reg_descriptor.GpRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.ErriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERRI\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.rc = rc\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitSErri(\n\top_code OpCode,\n\tsuffix Suffix,\n\tendian Endian,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.ErriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix != S_ERRI && suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitEdri(\n\top_code OpCode,\n\tendian Endian,\n\tdc *reg_descriptor.PairRegDescriptor,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n) {\n\tif _, found := this.EdriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = EDRI\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.dc = dc\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) InitErii(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\timm int64,\n) {\n\tif _, found := this.EriiOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERII\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 16, imm)\n}\n\nfunc (this *Instruction) InitErir(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\trb *reg_descriptor.SrcRegDescriptor,\n) {\n\tif _, found := this.ErirOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERIR\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\tthis.rb = rb\n}\n\nfunc (this *Instruction) InitErid(\n\top_code OpCode,\n\tendian Endian,\n\tra *reg_descriptor.SrcRegDescriptor,\n\toff int64,\n\tdb *reg_descriptor.PairRegDescriptor,\n) {\n\tif _, found := this.EridOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = ERID\n\n\tthis.endian = new(Endian)\n\t*this.endian = endian\n\n\tthis.ra = ra\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\tthis.db = db\n}\n\nfunc (this *Instruction) InitDmaRri(\n\top_code OpCode,\n\tra *reg_descriptor.SrcRegDescriptor,\n\trb *reg_descriptor.SrcRegDescriptor,\n\timm int64,\n) {\n\tif _, found := this.DmaRriOpCodes()[op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = DMA_RRI\n\n\tthis.ra = ra\n\tthis.rb = rb\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 8, imm)\n}\n\nfunc (this *Instruction) OpCode() OpCode {\n\treturn this.op_code\n}\n\nfunc (this *Instruction) Suffix() Suffix {\n\treturn this.suffix\n}\n\nfunc (this *Instruction) Rc() *reg_descriptor.GpRegDescriptor {\n\treturn this.rc\n}\n\nfunc (this *Instruction) Ra() *reg_descriptor.SrcRegDescriptor {\n\treturn this.ra\n}\n\nfunc (this *Instruction) Rb() *reg_descriptor.SrcRegDescriptor {\n\treturn this.rb\n}\n\nfunc (this *Instruction) Dc() *reg_descriptor.PairRegDescriptor {\n\treturn this.dc\n}\n\nfunc (this *Instruction) Db() *reg_descriptor.PairRegDescriptor {\n\treturn this.db\n}\n\nfunc (this *Instruction) Condition() cc.Condition {\n\tif this.condition == nil {\n\t\terr := errors.New(\"condition == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.condition\n}\n\nfunc (this *Instruction) Imm() *abi.Immediate {\n\treturn this.imm\n}\n\nfunc (this *Instruction) Off() *abi.Immediate {\n\treturn this.off\n}\n\nfunc (this *Instruction) Pc() *abi.Immediate {\n\treturn this.pc\n}\n\nfunc (this *Instruction) Endian() Endian {\n\tif this.endian == nil {\n\t\terr := errors.New(\"endian == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.endian\n}\n\nfunc (this *Instruction) Encode() *encoding.ByteStream {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tword_ := new(abi.Word)\n\tword_.Init(config_loader.IramDataWidth())\n\n\tthis.EncodeOpCode(word_)\n\tthis.EncodeSuffix(word_)\n\n\tif this.suffix == RICI {\n\t\tthis.EncodeRici(word_)\n\t} else if this.suffix == RRI {\n\t\tthis.EncodeRri(word_)\n\t} else if this.suffix == RRIC {\n\t\tthis.EncodeRric(word_)\n\t} else if this.suffix == RRICI {\n\t\tthis.EncodeRrici(word_)\n\t} else if this.suffix == RRIF {\n\t\tthis.EncodeRrif(word_)\n\t} else if this.suffix == RRR {\n\t\tthis.EncodeRrr(word_)\n\t} else if this.suffix == RRRC {\n\t\tthis.EncodeRrrc(word_)\n\t} else if this.suffix == RRRCI {\n\t\tthis.EncodeRrrci(word_)\n\t} else if this.suffix == ZRI {\n\t\tthis.EncodeZri(word_)\n\t} else if this.suffix == ZRIC {\n\t\tthis.EncodeZric(word_)\n\t} else if this.suffix == ZRICI {\n\t\tthis.EncodeZrici(word_)\n\t} else if this.suffix == ZRIF {\n\t\tthis.EncodeZrif(word_)\n\t} else if this.suffix == ZRR {\n\t\tthis.EncodeZrr(word_)\n\t} else if this.suffix == ZRRC {\n\t\tthis.EncodeZrrc(word_)\n\t} else if this.suffix == ZRRCI {\n\t\tthis.EncodeZrrci(word_)\n\t} else if this.suffix == S_RRI || this.suffix == U_RRI {\n\t\tthis.EncodeSRri(word_)\n\t} else if this.suffix == S_RRIC || this.suffix == U_RRIC {\n\t\tthis.EncodeSRric(word_)\n\t} else if this.suffix == S_RRICI || this.suffix == U_RRICI {\n\t\tthis.EncodeSRrici(word_)\n\t} else if this.suffix == S_RRIF || this.suffix == U_RRIF {\n\t\tthis.EncodeSRrif(word_)\n\t} else if this.suffix == S_RRR || this.suffix == U_RRR {\n\t\tthis.EncodeSRrr(word_)\n\t} else if this.suffix == S_RRRC || this.suffix == U_RRRC {\n\t\tthis.EncodeSRrrc(word_)\n\t} else if this.suffix == S_RRRCI || this.suffix == U_RRRCI {\n\t\tthis.EncodeSRrrci(word_)\n\t} else if this.suffix == RR {\n\t\tthis.EncodeRr(word_)\n\t} else if this.suffix == RRC {\n\t\tthis.EncodeRrc(word_)\n\t} else if this.suffix == RRCI {\n\t\tthis.EncodeRrci(word_)\n\t} else if this.suffix == ZR {\n\t\tthis.EncodeZr(word_)\n\t} else if this.suffix == ZRC {\n\t\tthis.EncodeZrc(word_)\n\t} else if this.suffix == ZRCI {\n\t\tthis.EncodeZrci(word_)\n\t} else if this.suffix == S_RR || this.suffix == U_RR {\n\t\tthis.EncodeSRr(word_)\n\t} else if this.suffix == S_RRC || this.suffix == U_RRC {\n\t\tthis.EncodeSRrc(word_)\n\t} else if this.suffix == S_RRCI || this.suffix == U_RRCI {\n\t\tthis.EncodeSRrci(word_)\n\t} else if this.suffix == DRDICI {\n\t\tthis.EncodeDrdici(word_)\n\t} else if this.suffix == RRRI {\n\t\tthis.EncodeRrri(word_)\n\t} else if this.suffix == RRRICI {\n\t\tthis.EncodeRrrici(word_)\n\t} else if this.suffix == ZRRI {\n\t\tthis.EncodeZrri(word_)\n\t} else if this.suffix == ZRRICI {\n\t\tthis.EncodeZrrici(word_)\n\t} else if this.suffix == S_RRRI || this.suffix == U_RRRI {\n\t\tthis.EncodeSRrri(word_)\n\t} else if this.suffix == S_RRRICI || this.suffix == U_RRRICI {\n\t\tthis.EncodeSRrrici(word_)\n\t} else if this.suffix == RIR {\n\t\tthis.EncodeRir(word_)\n\t} else if this.suffix == RIRC {\n\t\tthis.EncodeRirc(word_)\n\t} else if this.suffix == RIRCI {\n\t\tthis.EncodeRirci(word_)\n\t} else if this.suffix == ZIR {\n\t\tthis.EncodeZir(word_)\n\t} else if this.suffix == ZIRC {\n\t\tthis.EncodeZirc(word_)\n\t} else if this.suffix == ZIRCI {\n\t\tthis.EncodeZirci(word_)\n\t} else if this.suffix == S_RIRC || this.suffix == U_RIRC {\n\t\tthis.EncodeSRirc(word_)\n\t} else if this.suffix == S_RIRCI || this.suffix == U_RIRCI {\n\t\tthis.EncodeSRirci(word_)\n\t} else if this.suffix == R {\n\t\tthis.EncodeR(word_)\n\t} else if this.suffix == RCI {\n\t\tthis.EncodeRci(word_)\n\t} else if this.suffix == Z {\n\t\tthis.EncodeZ(word_)\n\t} else if this.suffix == ZCI {\n\t\tthis.EncodeZci(word_)\n\t} else if this.suffix == S_R || this.suffix == U_R {\n\t\tthis.EncodeSR(word_)\n\t} else if this.suffix == S_RCI || this.suffix == U_RCI {\n\t\tthis.EncodeSRci(word_)\n\t} else if this.suffix == CI {\n\t\tthis.EncodeCi(word_)\n\t} else if this.suffix == I {\n\t\tthis.EncodeI(word_)\n\t} else if this.suffix == DDCI {\n\t\tthis.EncodeDdci(word_)\n\t} else if this.suffix == ERRI {\n\t\tthis.EncodeErri(word_)\n\t} else if this.suffix == S_ERRI || this.suffix == U_ERRI {\n\t\tthis.EncodeSErri(word_)\n\t} else if this.suffix == EDRI {\n\t\tthis.EncodeEdri(word_)\n\t} else if this.suffix == ERII {\n\t\tthis.EncodeErii(word_)\n\t} else if this.suffix == ERIR {\n\t\tthis.EncodeErir(word_)\n\t} else if this.suffix == ERID {\n\t\tthis.EncodeErid(word_)\n\t} else if this.suffix == DMA_RRI {\n\t\tthis.EncodeDmaRri(word_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn word_.ToByteStream()\n}\n\nfunc (this *Instruction) EncodeRici(word_ *abi.Word) {\n\tif _, found := this.RiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.pc.Width()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeRric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeRrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeZric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeZrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRI && this.suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeSRric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIC && this.suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRICI && this.suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIF && this.suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeSRrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRC && this.suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRCI && this.suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeRrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeZrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RR && this.suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeSRrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRC && this.suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRCI && this.suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeDrdici(word_ *abi.Word) {\n\tif _, found := this.DrdiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tdb_begin := ra_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n\n\timm_begin := db_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeRrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeZrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRI && this.suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeSRrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRICI && this.suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeRir(word_ *abi.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeRirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeRirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZir(word_ *abi.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n}\n\nfunc (this *Instruction) EncodeZirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeZirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSRirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRC && this.suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n}\n\nfunc (this *Instruction) EncodeSRirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRCI && this.suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeR(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != R {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n}\n\nfunc (this *Instruction) EncodeRci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RCI {\n\t\terr := errors.New(\"suffix is not RCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tcondition_begin := rc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeZ(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found && this.op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != Z {\n\t\terr := errors.New(\"suffix is not Z\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) EncodeZci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZCI {\n\t\terr := errors.New(\"suffix is not ZCI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeSR(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_R && this.suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n}\n\nfunc (this *Instruction) EncodeSRci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RCI && this.suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tcondition_begin := dc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeCi(word_ *abi.Word) {\n\tif _, found := this.CiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeI(word_ *abi.Word) {\n\tif _, found := this.IOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != I {\n\t\terr := errors.New(\"suffix is not I\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeDdci(word_ *abi.Word) {\n\tif _, found := this.DdciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tdb_begin := dc_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n\n\tcondition_begin := db_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tthis.EncodeCondition(word_, condition_begin, condition_end, *this.condition)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tthis.EncodePc(word_, pc_begin, pc_end, this.pc.Value())\n}\n\nfunc (this *Instruction) EncodeErri(word_ *abi.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\trc_begin := endian_end\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.EncodeGpRegDescriptor(word_, rc_begin, rc_end, this.rc)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeSErri(word_ *abi.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_ERRI && this.suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeEdri(word_ *abi.Word) {\n\tif _, found := this.EdriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, dc_begin, dc_end, this.dc)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n}\n\nfunc (this *Instruction) EncodeErii(word_ *abi.Word) {\n\tif _, found := this.EriiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\timm_begin := off_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeErir(word_ *abi.Word) {\n\tif _, found := this.ErirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\trb_begin := off_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n}\n\nfunc (this *Instruction) EncodeErid(word_ *abi.Word) {\n\tif _, found := this.EridOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\tthis.EncodeEndian(word_, endian_begin, endian_end, *this.endian)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\toff_begin := ra_end\n\toff_end := off_begin + this.off.Width()\n\tthis.EncodeOff(word_, off_begin, off_end, this.off.Value())\n\n\tdb_begin := off_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.EncodePairRegDescriptor(word_, db_begin, db_end, this.db)\n}\n\nfunc (this *Instruction) EncodeDmaRri(word_ *abi.Word) {\n\tif _, found := this.DmaRriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, ra_begin, ra_end, this.ra)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.EncodeSrcRegDescriptor(word_, rb_begin, rb_end, this.rb)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + this.imm.Width()\n\tthis.EncodeImm(word_, imm_begin, imm_end, this.imm.Value())\n}\n\nfunc (this *Instruction) EncodeOpCode(word_ *abi.Word) {\n\tword_.SetBitSlice(this.OpCodeBegin(), this.OpCodeEnd(), int64(this.op_code))\n}\n\nfunc (this *Instruction) EncodeSuffix(word_ *abi.Word) {\n\tword_.SetBitSlice(this.SuffixBegin(), this.SuffixEnd(), int64(this.suffix))\n}\n\nfunc (this *Instruction) EncodeGpRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n) {\n\tword_.SetBitSlice(begin, end, int64(gp_reg_descriptor.Index()))\n}\n\nfunc (this *Instruction) EncodeSrcRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n) {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\tword_.SetBitSlice(begin, end, int64(src_reg_descriptor.GpRegDescriptor().Index()))\n\t} else if src_reg_descriptor.IsSpRegDescriptor() {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tindex := config_loader.NumGpRegisters() + int(*src_reg_descriptor.SpRegDescriptor())\n\t\tword_.SetBitSlice(begin, end, int64(index))\n\t} else {\n\t\terr := errors.New(\"sp reg descriptor is corrupted\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) EncodePairRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n) {\n\tword_.SetBitSlice(begin, end, int64(pair_reg_descriptor.Index()))\n}\n\nfunc (this *Instruction) EncodeImm(word_ *abi.Word, begin int, end int, value int64) {\n\tword_.SetBitSlice(begin, end, value)\n}\n\nfunc (this *Instruction) EncodeCondition(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\tcondition cc.Condition,\n) {\n\tword_.SetBitSlice(begin, end, int64(condition))\n}\n\nfunc (this *Instruction) EncodePc(word_ *abi.Word, begin int, end int, pc int64) {\n\tthis.EncodeImm(word_, begin, end, pc)\n}\n\nfunc (this *Instruction) EncodeEndian(word_ *abi.Word, begin int, end int, endian Endian) {\n\tword_.SetBitSlice(begin, end, int64(endian))\n}\n\nfunc (this *Instruction) EncodeOff(word_ *abi.Word, begin int, end int, value int64) {\n\tthis.EncodeImm(word_, begin, end, value)\n}\n\nfunc (this *Instruction) Decode(byte_stream *encoding.ByteStream) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tword_ := new(abi.Word)\n\tword_.Init(config_loader.IramDataWidth())\n\tword_.FromByteStream(byte_stream)\n\n\tthis.op_code = this.DecodeOpCode(word_)\n\tthis.suffix = this.DecodeSuffix(word_)\n\n\tif this.suffix == RICI {\n\t\tthis.DecodeRici(word_)\n\t} else if this.suffix == RRI {\n\t\tthis.DecodeRri(word_)\n\t} else if this.suffix == RRIC {\n\t\tthis.DecodeRric(word_)\n\t} else if this.suffix == RRICI {\n\t\tthis.DecodeRrici(word_)\n\t} else if this.suffix == RRIF {\n\t\tthis.DecodeRrif(word_)\n\t} else if this.suffix == RRR {\n\t\tthis.DecodeRrr(word_)\n\t} else if this.suffix == RRRC {\n\t\tthis.DecodeRrrc(word_)\n\t} else if this.suffix == RRRCI {\n\t\tthis.DecodeRrrci(word_)\n\t} else if this.suffix == ZRI {\n\t\tthis.DecodeZri(word_)\n\t} else if this.suffix == ZRIC {\n\t\tthis.DecodeZric(word_)\n\t} else if this.suffix == ZRICI {\n\t\tthis.DecodeZrici(word_)\n\t} else if this.suffix == ZRIF {\n\t\tthis.DecodeZrif(word_)\n\t} else if this.suffix == ZRR {\n\t\tthis.DecodeZrr(word_)\n\t} else if this.suffix == ZRRC {\n\t\tthis.DecodeZrrc(word_)\n\t} else if this.suffix == ZRRCI {\n\t\tthis.DecodeZrrci(word_)\n\t} else if this.suffix == S_RRI || this.suffix == U_RRI {\n\t\tthis.DecodeSRri(word_)\n\t} else if this.suffix == S_RRIC || this.suffix == U_RRIC {\n\t\tthis.DecodeSRric(word_)\n\t} else if this.suffix == S_RRICI || this.suffix == U_RRICI {\n\t\tthis.DecodeSRrici(word_)\n\t} else if this.suffix == S_RRIF || this.suffix == U_RRIF {\n\t\tthis.DecodeSRrif(word_)\n\t} else if this.suffix == S_RRR || this.suffix == U_RRR {\n\t\tthis.DecodeSRrr(word_)\n\t} else if this.suffix == S_RRRC || this.suffix == U_RRRC {\n\t\tthis.DecodeSRrrc(word_)\n\t} else if this.suffix == S_RRRCI || this.suffix == U_RRRCI {\n\t\tthis.DecodeSRrrci(word_)\n\t} else if this.suffix == RR {\n\t\tthis.DecodeRr(word_)\n\t} else if this.suffix == RRC {\n\t\tthis.DecodeRrc(word_)\n\t} else if this.suffix == RRCI {\n\t\tthis.DecodeRrci(word_)\n\t} else if this.suffix == ZR {\n\t\tthis.DecodeZr(word_)\n\t} else if this.suffix == ZRC {\n\t\tthis.DecodeZrc(word_)\n\t} else if this.suffix == ZRCI {\n\t\tthis.DecodeZrci(word_)\n\t} else if this.suffix == S_RR || this.suffix == U_RR {\n\t\tthis.DecodeSRr(word_)\n\t} else if this.suffix == S_RRC || this.suffix == U_RRC {\n\t\tthis.DecodeSRrc(word_)\n\t} else if this.suffix == S_RRCI || this.suffix == U_RRCI {\n\t\tthis.DecodeSRrci(word_)\n\t} else if this.suffix == DRDICI {\n\t\tthis.DecodeDrdici(word_)\n\t} else if this.suffix == RRRI {\n\t\tthis.DecodeRrri(word_)\n\t} else if this.suffix == RRRICI {\n\t\tthis.DecodeRrrici(word_)\n\t} else if this.suffix == ZRRI {\n\t\tthis.DecodeZrri(word_)\n\t} else if this.suffix == ZRRICI {\n\t\tthis.DecodeZrrici(word_)\n\t} else if this.suffix == S_RRRI || this.suffix == U_RRRI {\n\t\tthis.DecodeSRrri(word_)\n\t} else if this.suffix == S_RRRICI || this.suffix == U_RRRICI {\n\t\tthis.DecodeSRrrici(word_)\n\t} else if this.suffix == RIR {\n\t\tthis.DecodeRir(word_)\n\t} else if this.suffix == RIRC {\n\t\tthis.DecodeRirc(word_)\n\t} else if this.suffix == RIRCI {\n\t\tthis.DecodeRirci(word_)\n\t} else if this.suffix == ZIR {\n\t\tthis.DecodeZir(word_)\n\t} else if this.suffix == ZIRC {\n\t\tthis.DecodeZirc(word_)\n\t} else if this.suffix == ZIRCI {\n\t\tthis.DecodeZirci(word_)\n\t} else if this.suffix == S_RIRC || this.suffix == U_RIRC {\n\t\tthis.DecodeSRirc(word_)\n\t} else if this.suffix == S_RIRCI || this.suffix == U_RIRCI {\n\t\tthis.DecodeSRirci(word_)\n\t} else if this.suffix == R {\n\t\tthis.DecodeR(word_)\n\t} else if this.suffix == RCI {\n\t\tthis.DecodeRci(word_)\n\t} else if this.suffix == Z {\n\t\tthis.DecodeZ(word_)\n\t} else if this.suffix == ZCI {\n\t\tthis.DecodeZci(word_)\n\t} else if this.suffix == S_R || this.suffix == U_R {\n\t\tthis.DecodeSR(word_)\n\t} else if this.suffix == S_RCI || this.suffix == U_RCI {\n\t\tthis.DecodeSRci(word_)\n\t} else if this.suffix == CI {\n\t\tthis.DecodeCi(word_)\n\t} else if this.suffix == I {\n\t\tthis.DecodeI(word_)\n\t} else if this.suffix == DDCI {\n\t\tthis.DecodeDdci(word_)\n\t} else if this.suffix == ERRI {\n\t\tthis.DecodeErri(word_)\n\t} else if this.suffix == S_ERRI || this.suffix == U_ERRI {\n\t\tthis.DecodeSErri(word_)\n\t} else if this.suffix == EDRI {\n\t\tthis.DecodeEdri(word_)\n\t} else if this.suffix == ERII {\n\t\tthis.DecodeErii(word_)\n\t} else if this.suffix == ERIR {\n\t\tthis.DecodeErir(word_)\n\t} else if this.suffix == ERID {\n\t\tthis.DecodeErid(word_)\n\t} else if this.suffix == DMA_RRI {\n\t\tthis.DecodeDmaRri(word_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeRici(word_ *abi.Word) {\n\tif _, found := this.RiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 16\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 16, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\tcondition := this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = condition\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.SIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeRric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeRrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 28\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 28, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeZric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 27\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 27, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 27\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 27, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 11\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 11, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRIF {\n\t\terr := errors.New(\"suffix is not ZRIF\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 27\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 27, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRR {\n\t\terr := errors.New(\"suffix is not ZRR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeZrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRri(word_ *abi.Word) {\n\tif _, found := this.RriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRI && this.suffix != U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tif _, is_add_rri_op_code := this.AddRriOpCodes()[this.op_code]; is_add_rri_op_code {\n\t\timm_end := imm_begin + 32\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\t} else if _, is_asr_rri_op_code := this.AsrRriOpCodes()[this.op_code]; is_asr_rri_op_code {\n\t\timm_end := imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_call_rri_op_code := this.CallRriOpCodes()[this.op_code]; is_call_rri_op_code {\n\t\timm_end := imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeSRric(word_ *abi.Word) {\n\tif _, found := this.RricOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIC && this.suffix != U_RRIC {\n\t\terr := errors.New(\"suffix is not S_RRIC nor U_RRIC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rric_op_code := this.AddRricOpCodes()[this.op_code]; is_add_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else if _, is_asr_rric_op_code := this.AsrRricOpCodes()[this.op_code]; is_asr_rric_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_sub_rric_op_code := this.SubRricOpCodes()[this.op_code]; is_sub_rric_op_code {\n\t\timm_end = imm_begin + 24\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 24, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrici(word_ *abi.Word) {\n\tif _, found := this.RriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRICI && this.suffix != U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\tvar imm_end int\n\tif _, is_add_rrici_op_code := this.AddRriciOpCodes()[this.op_code]; is_add_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else if _, is_asr_rrici_op_code := this.AsrRriciOpCodes()[this.op_code]; is_asr_rrici_op_code {\n\t\timm_end = imm_begin + 5\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\t} else if _, is_and_rrici_op_code := this.AndRriciOpCodes()[this.op_code]; is_and_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else if _, is_sub_rrici_op_code := this.SubRriciOpCodes()[this.op_code]; is_sub_rrici_op_code {\n\t\timm_end = imm_begin + 8\n\t\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\t\tthis.imm = new(abi.Immediate)\n\t\tthis.imm.Init(abi.SIGNED, 8, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := imm_end\n\tcondition_end := imm_end + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRrif(word_ *abi.Word) {\n\tif _, found := this.RrifOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRIF && this.suffix != U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\timm_begin := ra_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrr(word_ *abi.Word) {\n\tif _, found := this.RrrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRR {\n\t\terr := errors.New(\"suffix is not S_RRR nor U_RRR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeSRrrc(word_ *abi.Word) {\n\tif _, found := this.RrrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRC && this.suffix != U_RRRC {\n\t\terr := errors.New(\"suffix is not S_RRRC nor U_RRRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrrci(word_ *abi.Word) {\n\tif _, found := this.RrrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRCI && this.suffix != U_RRRCI {\n\t\terr := errors.New(\"suffix is not S_RRRCI nor U_RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\tcondition_begin := rb_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeRrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeZrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRC {\n\t\terr := errors.New(\"suffix is not ZRC\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRr(word_ *abi.Word) {\n\tif _, found := this.RrOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RR && this.suffix != U_RR {\n\t\terr := errors.New(\"suffix is not S_RR nor U_RR\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeSRrc(word_ *abi.Word) {\n\tif _, found := this.RrcOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRC && this.suffix != U_RRC {\n\t\terr := errors.New(\"suffix is not S_RRC nor U_RRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRrci(word_ *abi.Word) {\n\tif _, found := this.RrciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRCI && this.suffix != U_RRCI {\n\t\terr := errors.New(\"suffix is not S_RRCI nor U_RRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodePc(word_, pc_begin, pc_end)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeDrdici(word_ *abi.Word) {\n\tif _, found := this.DrdiciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tdb_begin := ra_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n\n\timm_begin := db_end\n\timm_end := imm_begin + 5\n\timm := this.DecodePc(word_, imm_begin, imm_end)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeRrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeZrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRrri(word_ *abi.Word) {\n\tif _, found := this.RrriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRI && this.suffix != U_RRRI {\n\t\terr := errors.New(\"suffix is not S_RRRI nor U_RRRI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n}\n\nfunc (this *Instruction) DecodeSRrrici(word_ *abi.Word) {\n\tif _, found := this.RrriciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RRRICI && this.suffix != U_RRRICI {\n\t\terr := errors.New(\"suffix is not S_RRRICI nor U_RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 5\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 5, imm)\n\n\tcondition_begin := imm_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeRir(word_ *abi.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 32\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeRirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeRirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\timm_begin := rc_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZir(word_ *abi.Word) {\n\tif _, found := this.RirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 32\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 32, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n}\n\nfunc (this *Instruction) DecodeZirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeZirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSRirc(word_ *abi.Word) {\n\tif _, found := this.RircOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRC && this.suffix != U_RIRC {\n\t\terr := errors.New(\"suffix is not S_RIRC nor U_RIRC\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n}\n\nfunc (this *Instruction) DecodeSRirci(word_ *abi.Word) {\n\tif _, found := this.RirciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RIRCI && this.suffix != U_RIRCI {\n\t\terr := errors.New(\"suffix is not S_RIRCI nor U_RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\timm_begin := dc_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 8, imm)\n\n\tra_begin := imm_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\tcondition_begin := ra_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeR(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != R {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n}\n\nfunc (this *Instruction) DecodeRci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != RCI {\n\t\terr := errors.New(\"suffix is not RCI\")\n\t\tpanic(err)\n\t}\n\n\trc_begin := this.SuffixEnd()\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tcondition_begin := rc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeZ(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found && this.op_code != NOP {\n\t\terr := errors.New(\"op code is not a valid R op code nor NOP\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != Z {\n\t\terr := errors.New(\"suffix is not R\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) DecodeZci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ZCI {\n\t\terr := errors.New(\"suffix is not ZCI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeSR(word_ *abi.Word) {\n\tif _, found := this.ROpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_R && this.suffix != U_R {\n\t\terr := errors.New(\"suffix is not S_R nor U_R\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n}\n\nfunc (this *Instruction) DecodeSRci(word_ *abi.Word) {\n\tif _, found := this.RciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid RCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_RCI && this.suffix != U_RCI {\n\t\terr := errors.New(\"suffix is not S_RCI nor U_RCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tcondition_begin := dc_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeCi(word_ *abi.Word) {\n\tif _, found := this.CiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tcondition_begin := this.SuffixEnd()\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeI(word_ *abi.Word) {\n\tif _, found := this.IOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid I op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != I {\n\t\terr := errors.New(\"suffix is not I\")\n\t\tpanic(err)\n\t}\n\n\timm_begin := this.SuffixEnd()\n\timm_end := imm_begin + 24\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 24, imm)\n}\n\nfunc (this *Instruction) DecodeDdci(word_ *abi.Word) {\n\tif _, found := this.DdciOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tdc_begin := this.SuffixEnd()\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tdb_begin := dc_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n\n\tcondition_begin := db_end\n\tcondition_end := condition_begin + this.ConditionWidth()\n\n\tthis.condition = new(cc.Condition)\n\t*this.condition = this.DecodeCondition(word_, condition_begin, condition_end)\n\n\tpc_begin := condition_end\n\tpc_end := pc_begin + this.PcWidth()\n\tpc := this.DecodeImm(word_, pc_begin, pc_end, abi.UNSIGNED)\n\n\tthis.pc = new(abi.Immediate)\n\tthis.pc.Init(abi.UNSIGNED, this.PcWidth(), pc)\n}\n\nfunc (this *Instruction) DecodeErri(word_ *abi.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\trc_begin := endian_end\n\trc_end := rc_begin + this.RegisterWidth()\n\tthis.rc = this.DecodeGpRegDescriptor(word_, rc_begin, rc_end)\n\n\tra_begin := rc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeSErri(word_ *abi.Word) {\n\tif _, found := this.ErriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != S_ERRI && this.suffix != U_ERRI {\n\t\terr := errors.New(\"suffix is not S_ERRI nor U_ERRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeEdri(word_ *abi.Word) {\n\tif _, found := this.EdriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tdc_begin := endian_end\n\tdc_end := dc_begin + this.RegisterWidth()\n\tthis.dc = this.DecodePairRegDescriptor(word_, dc_begin, dc_end)\n\n\tra_begin := dc_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n}\n\nfunc (this *Instruction) DecodeErii(word_ *abi.Word) {\n\tif _, found := this.EriiOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\timm_begin := off_end\n\timm_end := imm_begin + 16\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.SIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.SIGNED, 16, imm)\n}\n\nfunc (this *Instruction) DecodeErir(word_ *abi.Word) {\n\tif _, found := this.ErirOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\trb_begin := off_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n}\n\nfunc (this *Instruction) DecodeErid(word_ *abi.Word) {\n\tif _, found := this.EridOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tendian_begin := this.SuffixEnd()\n\tendian_end := endian_begin + this.EndianWidth()\n\n\tthis.endian = new(Endian)\n\t*this.endian = this.DecodeEndian(word_, endian_begin, endian_end)\n\n\tra_begin := endian_end\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\toff_begin := ra_end\n\toff_end := off_begin + 24\n\toff := this.DecodeOff(word_, off_begin, off_end, abi.SIGNED)\n\n\tthis.off = new(abi.Immediate)\n\tthis.off.Init(abi.SIGNED, 24, off)\n\n\tdb_begin := off_end\n\tdb_end := db_begin + this.RegisterWidth()\n\tthis.db = this.DecodePairRegDescriptor(word_, db_begin, db_end)\n}\n\nfunc (this *Instruction) DecodeDmaRri(word_ *abi.Word) {\n\tif _, found := this.DmaRriOpCodes()[this.op_code]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif this.suffix != DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tra_begin := this.SuffixEnd()\n\tra_end := ra_begin + this.RegisterWidth()\n\tthis.ra = this.DecodeSrcRegDescriptor(word_, ra_begin, ra_end)\n\n\trb_begin := ra_end\n\trb_end := rb_begin + this.RegisterWidth()\n\tthis.rb = this.DecodeSrcRegDescriptor(word_, rb_begin, rb_end)\n\n\timm_begin := rb_end\n\timm_end := imm_begin + 8\n\timm := this.DecodeImm(word_, imm_begin, imm_end, abi.UNSIGNED)\n\n\tthis.imm = new(abi.Immediate)\n\tthis.imm.Init(abi.UNSIGNED, 8, imm)\n}\n\nfunc (this *Instruction) DecodeOpCode(word_ *abi.Word) OpCode {\n\treturn OpCode(word_.BitSlice(abi.UNSIGNED, this.OpCodeBegin(), this.OpCodeEnd()))\n}\n\nfunc (this *Instruction) DecodeSuffix(word_ *abi.Word) Suffix {\n\treturn Suffix(word_.BitSlice(abi.UNSIGNED, this.SuffixBegin(), this.SuffixEnd()))\n}\n\nfunc (this *Instruction) DecodeGpRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.GpRegDescriptor {\n\tindex := int(word_.BitSlice(abi.UNSIGNED, begin, end))\n\n\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\tgp_reg_descriptor.Init(index)\n\n\treturn gp_reg_descriptor\n}\n\nfunc (this *Instruction) DecodeSrcRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.SrcRegDescriptor {\n\tindex := int(word_.BitSlice(abi.UNSIGNED, begin, end))\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif index < config_loader.NumGpRegisters() {\n\t\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\t\tgp_reg_descriptor.Init(index)\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitGpRegDescriptor(gp_reg_descriptor)\n\n\t\treturn src_reg_descriptor\n\t} else {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.SpRegDescriptor(index - config_loader.NumGpRegisters())\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\n\t\treturn src_reg_descriptor\n\t}\n}\n\nfunc (this *Instruction) DecodePairRegDescriptor(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n) *reg_descriptor.PairRegDescriptor {\n\tindex := int(word_.BitSlice(abi.UNSIGNED, begin, end))\n\n\tpair_reg_descriptor := new(reg_descriptor.PairRegDescriptor)\n\tpair_reg_descriptor.Init(index)\n\n\treturn pair_reg_descriptor\n}\n\nfunc (this *Instruction) DecodeImm(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\trepresentation abi.Representation,\n) int64 {\n\treturn word_.BitSlice(representation, begin, end)\n}\n\nfunc (this *Instruction) DecodeCondition(word_ *abi.Word, begin int, end int) cc.Condition {\n\treturn cc.Condition(word_.BitSlice(abi.UNSIGNED, begin, end))\n}\n\nfunc (this *Instruction) DecodePc(word_ *abi.Word, begin int, end int) int64 {\n\treturn this.DecodeImm(word_, begin, end, abi.UNSIGNED)\n}\n\nfunc (this *Instruction) DecodeEndian(word_ *abi.Word, begin int, end int) Endian {\n\treturn Endian(word_.BitSlice(abi.UNSIGNED, begin, end))\n}\n\nfunc (this *Instruction) DecodeOff(\n\tword_ *abi.Word,\n\tbegin int,\n\tend int,\n\trepresentation abi.Representation,\n) int64 {\n\treturn this.DecodeImm(word_, begin, end, representation)\n}\n\nfunc (this *Instruction) OpCodeBegin() int {\n\treturn 0\n}\n\nfunc (this *Instruction) OpCodeEnd() int {\n\treturn this.OpCodeBegin() + this.OpCodeWidth()\n}\n\nfunc (this *Instruction) OpCodeWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(SDMA))))\n}\n\nfunc (this *Instruction) SuffixBegin() int {\n\treturn this.OpCodeEnd()\n}\n\nfunc (this *Instruction) SuffixEnd() int {\n\treturn this.SuffixBegin() + this.SuffixWidth()\n}\n\nfunc (this *Instruction) SuffixWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(DMA_RRI))))\n}\n\nfunc (this *Instruction) RegisterWidth() int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\treturn int(\n\t\tmath.Ceil(\n\t\t\tmath.Log2(float64(config_loader.NumGpRegisters()) + 1.0 + float64(reg_descriptor.ID8)),\n\t\t),\n\t)\n}\n\nfunc (this *Instruction) ConditionWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(cc.LARGE))))\n}\n\nfunc (this *Instruction) PcWidth() int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\treturn config_loader.AddressWidth()\n}\n\nfunc (this *Instruction) EndianWidth() int {\n\treturn int(math.Ceil(math.Log2(1.0 + float64(BIG))))\n}\n\nfunc (this *Instruction) AcquireRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tACQUIRE: true,\n\t}\n}\n\nfunc (this *Instruction) ReleaseRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRELEASE: true,\n\t}\n}\n\nfunc (this *Instruction) BootRiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tBOOT:   true,\n\t\tRESUME: true,\n\t}\n}\n\nfunc (this *Instruction) RiciOpCodes() map[OpCode]bool {\n\tacquire_rici_op_codes := this.AcquireRiciOpCodes()\n\trelease_rici_op_codes := this.ReleaseRiciOpCodes()\n\tboot_rici_op_codes := this.BootRiciOpCodes()\n\n\trici_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range acquire_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\tfor k, v := range release_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\tfor k, v := range boot_rici_op_codes {\n\t\trici_op_codes[k] = v\n\t}\n\n\treturn rici_op_codes\n}\n\nfunc (this *Instruction) AddRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tOR:   true,\n\t\tXOR:  true,\n\t}\n}\n\nfunc (this *Instruction) AsrRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) CallRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCALL: true,\n\t}\n}\n\nfunc (this *Instruction) RriOpCodes() map[OpCode]bool {\n\tadd_rri_op_codes := this.AddRriOpCodes()\n\tasr_rri_op_codes := this.AsrRriOpCodes()\n\tcall_rri_op_codes := this.CallRriOpCodes()\n\n\trri_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range add_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\tfor k, v := range call_rri_op_codes {\n\t\trri_op_codes[k] = v\n\t}\n\n\treturn rri_op_codes\n}\n\nfunc (this *Instruction) AddRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) SubRricOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RricOpCodes() map[OpCode]bool {\n\tadd_rric_op_codes := this.AddRricOpCodes()\n\tasr_rric_op_codes := this.AsrRricOpCodes()\n\tsub_rric_op_codes := this.SubRricOpCodes()\n\n\trric_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range add_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rric_op_codes {\n\t\trric_op_codes[k] = v\n\t}\n\n\treturn rric_op_codes\n}\n\nfunc (this *Instruction) AddRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t}\n}\n\nfunc (this *Instruction) AndRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) SubRriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RriciOpCodes() map[OpCode]bool {\n\tadd_rrici_op_codes := this.AddRriciOpCodes()\n\tand_rrici_op_codes := this.AndRriciOpCodes()\n\tasr_rrici_op_codes := this.AsrRriciOpCodes()\n\tsub_rrici_op_codes := this.SubRriciOpCodes()\n\n\trrici_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range add_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range and_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rrici_op_codes {\n\t\trrici_op_codes[k] = v\n\t}\n\n\treturn rrici_op_codes\n}\n\nfunc (this *Instruction) RrifOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) RrrOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:       true,\n\t\tADDC:      true,\n\t\tAND:       true,\n\t\tANDN:      true,\n\t\tASR:       true,\n\t\tCMPB4:     true,\n\t\tLSL:       true,\n\t\tLSL1:      true,\n\t\tLSL1X:     true,\n\t\tLSLX:      true,\n\t\tLSR:       true,\n\t\tLSR1:      true,\n\t\tLSR1X:     true,\n\t\tLSRX:      true,\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t\tNAND:      true,\n\t\tNOR:       true,\n\t\tNXOR:      true,\n\t\tOR:        true,\n\t\tORN:       true,\n\t\tROL:       true,\n\t\tROR:       true,\n\t\tRSUB:      true,\n\t\tRSUBC:     true,\n\t\tSUB:       true,\n\t\tSUBC:      true,\n\t\tXOR:       true,\n\t\tHASH:      true,\n\t\tCALL:      true,\n\t}\n}\n\nfunc (this *Instruction) AddRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:       true,\n\t\tADDC:      true,\n\t\tAND:       true,\n\t\tANDN:      true,\n\t\tASR:       true,\n\t\tCMPB4:     true,\n\t\tLSL:       true,\n\t\tLSL1:      true,\n\t\tLSL1X:     true,\n\t\tLSLX:      true,\n\t\tLSR:       true,\n\t\tLSR1:      true,\n\t\tLSR1X:     true,\n\t\tLSRX:      true,\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t\tNAND:      true,\n\t\tNOR:       true,\n\t\tNXOR:      true,\n\t\tROL:       true,\n\t\tROR:       true,\n\t\tOR:        true,\n\t\tORN:       true,\n\t\tXOR:       true,\n\t\tHASH:      true,\n\t\tCALL:      true,\n\t}\n}\n\nfunc (this *Instruction) RsubRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRSUB:  true,\n\t\tRSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) SubRrrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RrrcOpCodes() map[OpCode]bool {\n\tadd_rrrc_op_codes := this.AddRrrcOpCodes()\n\trsub_rrrc_op_codes := this.RsubRrrcOpCodes()\n\tsub_rrrc_op_codes := this.SubRrrcOpCodes()\n\n\trrrc_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range add_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\tfor k, v := range rsub_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\tfor k, v := range sub_rrrc_op_codes {\n\t\trrrc_op_codes[k] = v\n\t}\n\n\treturn rrrc_op_codes\n}\n\nfunc (this *Instruction) AddRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tADD:  true,\n\t\tADDC: true,\n\t}\n}\n\nfunc (this *Instruction) AndRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tAND:  true,\n\t\tANDN: true,\n\t\tNAND: true,\n\t\tNOR:  true,\n\t\tNXOR: true,\n\t\tOR:   true,\n\t\tORN:  true,\n\t\tXOR:  true,\n\t\tHASH: true,\n\t}\n}\n\nfunc (this *Instruction) AsrRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tASR:   true,\n\t\tCMPB4: true,\n\t\tLSL:   true,\n\t\tLSL1:  true,\n\t\tLSL1X: true,\n\t\tLSLX:  true,\n\t\tLSR:   true,\n\t\tLSR1:  true,\n\t\tLSR1X: true,\n\t\tLSRX:  true,\n\t\tROL:   true,\n\t\tROR:   true,\n\t}\n}\n\nfunc (this *Instruction) MulRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMUL_SH_SH: true,\n\t\tMUL_SH_SL: true,\n\t\tMUL_SH_UH: true,\n\t\tMUL_SH_UL: true,\n\t\tMUL_SL_SH: true,\n\t\tMUL_SL_SL: true,\n\t\tMUL_SL_UH: true,\n\t\tMUL_SL_UL: true,\n\t\tMUL_UH_UH: true,\n\t\tMUL_UH_UL: true,\n\t\tMUL_UL_UH: true,\n\t\tMUL_UL_UL: true,\n\t}\n}\n\nfunc (this *Instruction) RsubRrrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tRSUB:  true,\n\t\tRSUBC: true,\n\t\tSUB:   true,\n\t\tSUBC:  true,\n\t}\n}\n\nfunc (this *Instruction) RrrciOpCodes() map[OpCode]bool {\n\tadd_rrrci_op_codes := this.AddRrrciOpCodes()\n\tand_rrrci_op_codes := this.AndRrrciOpCodes()\n\tasr_rrrci_op_codes := this.AsrRrrciOpCodes()\n\tmul_rrrci_op_codes := this.MulRrrciOpCodes()\n\trsub_rrrci_op_codes := this.RsubRrrciOpCodes()\n\n\trrrci_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range add_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range and_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range asr_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range mul_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range rsub_rrrci_op_codes {\n\t\trrrci_op_codes[k] = v\n\t}\n\n\treturn rrrci_op_codes\n}\n\nfunc (this *Instruction) RrOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO:      true,\n\t\tCLO:      true,\n\t\tCLS:      true,\n\t\tCLZ:      true,\n\t\tEXTSB:    true,\n\t\tEXTSH:    true,\n\t\tEXTUB:    true,\n\t\tEXTUH:    true,\n\t\tSATS:     true,\n\t\tTIME_CFG: true,\n\t}\n}\n\nfunc (this *Instruction) RrcOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO:   true,\n\t\tCLO:   true,\n\t\tCLS:   true,\n\t\tCLZ:   true,\n\t\tEXTSB: true,\n\t\tEXTSH: true,\n\t\tEXTUB: true,\n\t\tEXTUH: true,\n\t\tSATS:  true,\n\t}\n}\n\nfunc (this *Instruction) CaoRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tCAO: true,\n\t\tCLO: true,\n\t\tCLS: true,\n\t\tCLZ: true,\n\t}\n}\n\nfunc (this *Instruction) ExtsbRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tEXTSB: true,\n\t\tEXTSH: true,\n\t\tEXTUB: true,\n\t\tEXTUH: true,\n\t\tSATS:  true,\n\t}\n}\n\nfunc (this *Instruction) TimeCfgRrciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME_CFG: true,\n\t}\n}\n\nfunc (this *Instruction) RrciOpCodes() map[OpCode]bool {\n\tcao_rrci_op_codes := this.CaoRrciOpCodes()\n\textsb_rrci_op_codes := this.ExtsbRrciOpCodes()\n\ttime_cfg_rrci_op_codes := this.TimeCfgRrciOpCodes()\n\n\trrci_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range cao_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range extsb_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\tfor k, v := range time_cfg_rrci_op_codes {\n\t\trrci_op_codes[k] = v\n\t}\n\n\treturn rrci_op_codes\n}\n\nfunc (this *Instruction) DivStepDrdiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tDIV_STEP: true,\n\t}\n}\n\nfunc (this *Instruction) MulStepDrdiciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMUL_STEP: true,\n\t}\n}\n\nfunc (this *Instruction) DrdiciOpCodes() map[OpCode]bool {\n\tdiv_step_drdici_op_codes := this.DivStepDrdiciOpCodes()\n\tmul_step_drdici_op_codes := this.MulStepDrdiciOpCodes()\n\n\tdrdici_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range div_step_drdici_op_codes {\n\t\tdrdici_op_codes[k] = v\n\t}\n\n\tfor k, v := range mul_step_drdici_op_codes {\n\t\tdrdici_op_codes[k] = v\n\t}\n\n\treturn drdici_op_codes\n}\n\nfunc (this *Instruction) RrriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLSL_ADD: true,\n\t\tLSL_SUB: true,\n\t\tLSR_ADD: true,\n\t\tROL_ADD: true,\n\t}\n}\n\nfunc (this *Instruction) RrriciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLSL_ADD: true,\n\t\tLSL_SUB: true,\n\t\tLSR_ADD: true,\n\t\tROL_ADD: true,\n\t}\n}\n\nfunc (this *Instruction) RirOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RircOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) RirciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSUB:  true,\n\t\tSUBC: true,\n\t}\n}\n\nfunc (this *Instruction) ROpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME: true,\n\t}\n}\n\nfunc (this *Instruction) RciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tTIME: true,\n\t}\n}\n\nfunc (this *Instruction) CiOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSTOP: true,\n\t}\n}\n\nfunc (this *Instruction) IOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tFAULT: true,\n\t}\n}\n\nfunc (this *Instruction) MovdDdciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tMOVD: true,\n\t}\n}\n\nfunc (this *Instruction) SwapdDdciOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSWAPD: true,\n\t}\n}\n\nfunc (this *Instruction) DdciOpCodes() map[OpCode]bool {\n\tmovd_ddci_op_codes := this.MovdDdciOpCodes()\n\tswapd_ddci_op_codes := this.SwapdDdciOpCodes()\n\n\tddci_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range movd_ddci_op_codes {\n\t\tddci_op_codes[k] = v\n\t}\n\n\tfor k, v := range swapd_ddci_op_codes {\n\t\tddci_op_codes[k] = v\n\t}\n\n\treturn ddci_op_codes\n}\n\nfunc (this *Instruction) ErriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLBS: true,\n\t\tLBU: true,\n\t\tLHS: true,\n\t\tLHU: true,\n\t\tLW:  true,\n\t}\n}\n\nfunc (this *Instruction) EdriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLD: true,\n\t}\n}\n\nfunc (this *Instruction) EriiOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSB:    true,\n\t\tSB_ID: true,\n\t\tSD:    true,\n\t\tSD_ID: true,\n\t\tSH:    true,\n\t\tSH_ID: true,\n\t\tSW:    true,\n\t\tSW_ID: true,\n\t}\n}\n\nfunc (this *Instruction) ErirOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSB: true,\n\t\tSH: true,\n\t\tSW: true,\n\t}\n}\n\nfunc (this *Instruction) EridOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSD: true,\n\t}\n}\n\nfunc (this *Instruction) LdmaDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLDMA: true,\n\t}\n}\n\nfunc (this *Instruction) LdmaiDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tLDMAI: true,\n\t}\n}\n\nfunc (this *Instruction) SdmaDmaRriOpCodes() map[OpCode]bool {\n\treturn map[OpCode]bool{\n\t\tSDMA: true,\n\t}\n}\n\nfunc (this *Instruction) DmaRriOpCodes() map[OpCode]bool {\n\tldma_dma_rri_op_codes := this.LdmaDmaRriOpCodes()\n\tldmai_dma_rri_op_codes := this.LdmaiDmaRriOpCodes()\n\tsdma_dma_rri_op_codes := this.SdmaDmaRriOpCodes()\n\n\tdma_rri_op_codes := make(map[OpCode]bool)\n\n\tfor k, v := range ldma_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\tfor k, v := range ldmai_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\tfor k, v := range sdma_dma_rri_op_codes {\n\t\tdma_rri_op_codes[k] = v\n\t}\n\n\treturn dma_rri_op_codes\n}\n\nfunc (this *Instruction) Stringify() string {\n\tstr := this.StringifyOpCode() + \", \"\n\tstr += this.StringifySuffix() + \", \"\n\n\tif this.suffix == RICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == RRIC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRICI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRIF {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == RRRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ZRIC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRIF {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRR {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == ZRRC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRRCI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == S_RRIC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRIF {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == S_RRRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == U_RRIC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRIF {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == U_RRRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == RRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZR {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == ZRC {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZRCI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == S_RRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RR {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == U_RRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == DRDICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RRRI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == RRRICI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZRRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ZRRICI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RRRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == S_RRRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RRRI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == U_RRRICI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == RIR {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == RIRC {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == RIRCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ZIR {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra)\n\t} else if this.suffix == ZIRC {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == ZIRCI {\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_RIRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == S_RIRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_RIRC {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition)\n\t} else if this.suffix == U_RIRCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyImm(this.imm) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == R {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc)\n\t} else if this.suffix == RCI {\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == Z {\n\t\tstr = str[:len(str)-2]\n\t} else if this.suffix == ZCI {\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == S_R {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc)\n\t} else if this.suffix == S_RCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == U_R {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc)\n\t} else if this.suffix == U_RCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == CI {\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == I {\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == DDCI {\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db) + \", \"\n\t\tstr += this.StringifyCondition(*this.condition) + \", \"\n\t\tstr += this.StringifyPc(this.pc)\n\t} else if this.suffix == ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyGpRegDescriptor(this.rc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == S_ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == U_ERRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == EDRI {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.dc) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off)\n\t} else if this.suffix == ERII {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else if this.suffix == ERIR {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb)\n\t} else if this.suffix == ERID {\n\t\tstr += this.StringifyEndian(*this.endian) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifyOff(this.off) + \", \"\n\t\tstr += this.StringifyPairRegDescriptor(this.db)\n\t} else if this.suffix == DMA_RRI {\n\t\tstr += this.StringifySrcRegDescriptor(this.ra) + \", \"\n\t\tstr += this.StringifySrcRegDescriptor(this.rb) + \", \"\n\t\tstr += this.StringifyImm(this.imm)\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn str\n}\n\nfunc (this *Instruction) StringifyOpCode() string {\n\tif this.op_code == ACQUIRE {\n\t\treturn \"acquire\"\n\t} else if this.op_code == RELEASE {\n\t\treturn \"release\"\n\t} else if this.op_code == RELEASE {\n\t\treturn \"release\"\n\t} else if this.op_code == ADD {\n\t\treturn \"add\"\n\t} else if this.op_code == ADDC {\n\t\treturn \"addc\"\n\t} else if this.op_code == AND {\n\t\treturn \"and\"\n\t} else if this.op_code == ANDN {\n\t\treturn \"andn\"\n\t} else if this.op_code == ASR {\n\t\treturn \"asr\"\n\t} else if this.op_code == CAO {\n\t\treturn \"cao\"\n\t} else if this.op_code == CLO {\n\t\treturn \"clo\"\n\t} else if this.op_code == CLS {\n\t\treturn \"cls\"\n\t} else if this.op_code == CLZ {\n\t\treturn \"clz\"\n\t} else if this.op_code == CMPB4 {\n\t\treturn \"cmpb4\"\n\t} else if this.op_code == DIV_STEP {\n\t\treturn \"div_step\"\n\t} else if this.op_code == EXTSB {\n\t\treturn \"extsb\"\n\t} else if this.op_code == EXTSH {\n\t\treturn \"extsh\"\n\t} else if this.op_code == EXTUB {\n\t\treturn \"extub\"\n\t} else if this.op_code == EXTUH {\n\t\treturn \"extuh\"\n\t} else if this.op_code == LSL {\n\t\treturn \"lsl\"\n\t} else if this.op_code == LSL_ADD {\n\t\treturn \"lsl_add\"\n\t} else if this.op_code == LSL_SUB {\n\t\treturn \"lsl_sub\"\n\t} else if this.op_code == LSL1 {\n\t\treturn \"lsl1\"\n\t} else if this.op_code == LSL1X {\n\t\treturn \"lsl1x\"\n\t} else if this.op_code == LSLX {\n\t\treturn \"lslx\"\n\t} else if this.op_code == LSR {\n\t\treturn \"lsr\"\n\t} else if this.op_code == LSR_ADD {\n\t\treturn \"lsr_add\"\n\t} else if this.op_code == LSR1 {\n\t\treturn \"lsr1\"\n\t} else if this.op_code == LSR1X {\n\t\treturn \"lsr1x\"\n\t} else if this.op_code == LSRX {\n\t\treturn \"lsrx\"\n\t} else if this.op_code == MUL_SH_SH {\n\t\treturn \"mul_sh_sh\"\n\t} else if this.op_code == MUL_SH_SL {\n\t\treturn \"mul_sh_sl\"\n\t} else if this.op_code == MUL_SH_UH {\n\t\treturn \"mul_sh_uh\"\n\t} else if this.op_code == MUL_SH_UL {\n\t\treturn \"mul_sh_ul\"\n\t} else if this.op_code == MUL_SL_SH {\n\t\treturn \"mul_sl_sh\"\n\t} else if this.op_code == MUL_SL_SL {\n\t\treturn \"mul_sl_sl\"\n\t} else if this.op_code == MUL_SL_UH {\n\t\treturn \"mul_sl_uh\"\n\t} else if this.op_code == MUL_SL_UL {\n\t\treturn \"mul_sl_ul\"\n\t} else if this.op_code == MUL_STEP {\n\t\treturn \"mul_step\"\n\t} else if this.op_code == MUL_UH_UH {\n\t\treturn \"mul_uh_uh\"\n\t} else if this.op_code == MUL_UH_UL {\n\t\treturn \"mul_uh_ul\"\n\t} else if this.op_code == MUL_UL_UH {\n\t\treturn \"mul_ul_uh\"\n\t} else if this.op_code == MUL_UL_UL {\n\t\treturn \"mul_ul_ul\"\n\t} else if this.op_code == NAND {\n\t\treturn \"nand\"\n\t} else if this.op_code == NOR {\n\t\treturn \"nor\"\n\t} else if this.op_code == NXOR {\n\t\treturn \"nxor\"\n\t} else if this.op_code == OR {\n\t\treturn \"or\"\n\t} else if this.op_code == ORN {\n\t\treturn \"orn\"\n\t} else if this.op_code == ROL {\n\t\treturn \"rol\"\n\t} else if this.op_code == ROL_ADD {\n\t\treturn \"rol_add\"\n\t} else if this.op_code == ROR {\n\t\treturn \"ror\"\n\t} else if this.op_code == RSUB {\n\t\treturn \"rsub\"\n\t} else if this.op_code == RSUBC {\n\t\treturn \"rsubc\"\n\t} else if this.op_code == SUB {\n\t\treturn \"sub\"\n\t} else if this.op_code == SUBC {\n\t\treturn \"subc\"\n\t} else if this.op_code == XOR {\n\t\treturn \"xor\"\n\t} else if this.op_code == BOOT {\n\t\treturn \"boot\"\n\t} else if this.op_code == RESUME {\n\t\treturn \"resume\"\n\t} else if this.op_code == STOP {\n\t\treturn \"stop\"\n\t} else if this.op_code == CALL {\n\t\treturn \"call\"\n\t} else if this.op_code == FAULT {\n\t\treturn \"fault\"\n\t} else if this.op_code == NOP {\n\t\treturn \"nop\"\n\t} else if this.op_code == SATS {\n\t\treturn \"sats\"\n\t} else if this.op_code == MOVD {\n\t\treturn \"movd\"\n\t} else if this.op_code == SWAPD {\n\t\treturn \"swapd\"\n\t} else if this.op_code == HASH {\n\t\treturn \"hash\"\n\t} else if this.op_code == TIME {\n\t\treturn \"time\"\n\t} else if this.op_code == TIME_CFG {\n\t\treturn \"time_cfg\"\n\t} else if this.op_code == LBS {\n\t\treturn \"lbs\"\n\t} else if this.op_code == LBU {\n\t\treturn \"lbu\"\n\t} else if this.op_code == LD {\n\t\treturn \"ld\"\n\t} else if this.op_code == LHS {\n\t\treturn \"lhs\"\n\t} else if this.op_code == LHU {\n\t\treturn \"lhu\"\n\t} else if this.op_code == LW {\n\t\treturn \"lw\"\n\t} else if this.op_code == SB {\n\t\treturn \"sb\"\n\t} else if this.op_code == SB_ID {\n\t\treturn \"sb_id\"\n\t} else if this.op_code == SD {\n\t\treturn \"sd\"\n\t} else if this.op_code == SD_ID {\n\t\treturn \"sd_id\"\n\t} else if this.op_code == SH {\n\t\treturn \"sh\"\n\t} else if this.op_code == SH_ID {\n\t\treturn \"sh_id\"\n\t} else if this.op_code == SW {\n\t\treturn \"sw\"\n\t} else if this.op_code == SW_ID {\n\t\treturn \"sw_id\"\n\t} else if this.op_code == LDMA {\n\t\treturn \"ldma\"\n\t} else if this.op_code == LDMAI {\n\t\treturn \"ldmai\"\n\t} else if this.op_code == SDMA {\n\t\treturn \"sdma\"\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifySuffix() string {\n\tif this.suffix == RICI {\n\t\treturn \"rici\"\n\t} else if this.suffix == RRI {\n\t\treturn \"rri\"\n\t} else if this.suffix == RRIC {\n\t\treturn \"rric\"\n\t} else if this.suffix == RRICI {\n\t\treturn \"rrici\"\n\t} else if this.suffix == RRIF {\n\t\treturn \"rrif\"\n\t} else if this.suffix == RRR {\n\t\treturn \"rrr\"\n\t} else if this.suffix == RRRC {\n\t\treturn \"rrrc\"\n\t} else if this.suffix == RRRCI {\n\t\treturn \"rrrci\"\n\t} else if this.suffix == ZRI {\n\t\treturn \"zri\"\n\t} else if this.suffix == ZRIC {\n\t\treturn \"zric\"\n\t} else if this.suffix == ZRICI {\n\t\treturn \"zrici\"\n\t} else if this.suffix == ZRIF {\n\t\treturn \"zrif\"\n\t} else if this.suffix == ZRR {\n\t\treturn \"zrr\"\n\t} else if this.suffix == ZRRC {\n\t\treturn \"zrrc\"\n\t} else if this.suffix == ZRRCI {\n\t\treturn \"zrrci\"\n\t} else if this.suffix == S_RRI {\n\t\treturn \"s_rri\"\n\t} else if this.suffix == S_RRIC {\n\t\treturn \"s_rric\"\n\t} else if this.suffix == S_RRICI {\n\t\treturn \"s_rrici\"\n\t} else if this.suffix == S_RRIF {\n\t\treturn \"s_rrif\"\n\t} else if this.suffix == S_RRR {\n\t\treturn \"s_rrr\"\n\t} else if this.suffix == S_RRRC {\n\t\treturn \"s_rrrc\"\n\t} else if this.suffix == S_RRRCI {\n\t\treturn \"s_rrrci\"\n\t} else if this.suffix == U_RRI {\n\t\treturn \"u_rri\"\n\t} else if this.suffix == U_RRIC {\n\t\treturn \"u_rric\"\n\t} else if this.suffix == U_RRICI {\n\t\treturn \"u_rrici\"\n\t} else if this.suffix == U_RRIF {\n\t\treturn \"u_rrif\"\n\t} else if this.suffix == U_RRR {\n\t\treturn \"u_rrr\"\n\t} else if this.suffix == U_RRRC {\n\t\treturn \"u_rrrc\"\n\t} else if this.suffix == U_RRRCI {\n\t\treturn \"u_rrrci\"\n\t} else if this.suffix == RR {\n\t\treturn \"rr\"\n\t} else if this.suffix == RRC {\n\t\treturn \"rrc\"\n\t} else if this.suffix == RRCI {\n\t\treturn \"rrci\"\n\t} else if this.suffix == ZR {\n\t\treturn \"zr\"\n\t} else if this.suffix == ZRC {\n\t\treturn \"zrc\"\n\t} else if this.suffix == ZRCI {\n\t\treturn \"zrci\"\n\t} else if this.suffix == S_RR {\n\t\treturn \"s_rr\"\n\t} else if this.suffix == S_RRC {\n\t\treturn \"s_rrc\"\n\t} else if this.suffix == S_RRCI {\n\t\treturn \"s_rrci\"\n\t} else if this.suffix == U_RR {\n\t\treturn \"u_rr\"\n\t} else if this.suffix == U_RRC {\n\t\treturn \"u_rrc\"\n\t} else if this.suffix == U_RRCI {\n\t\treturn \"u_rrci\"\n\t} else if this.suffix == DRDICI {\n\t\treturn \"drdici\"\n\t} else if this.suffix == RRRI {\n\t\treturn \"rrri\"\n\t} else if this.suffix == RRRICI {\n\t\treturn \"rrrici\"\n\t} else if this.suffix == ZRRI {\n\t\treturn \"zrri\"\n\t} else if this.suffix == ZRRICI {\n\t\treturn \"zrrici\"\n\t} else if this.suffix == S_RRRI {\n\t\treturn \"s_rrri\"\n\t} else if this.suffix == S_RRRICI {\n\t\treturn \"s_rrrici\"\n\t} else if this.suffix == U_RRRI {\n\t\treturn \"u_rrri\"\n\t} else if this.suffix == U_RRRICI {\n\t\treturn \"u_rrrici\"\n\t} else if this.suffix == RIR {\n\t\treturn \"rir\"\n\t} else if this.suffix == RIRC {\n\t\treturn \"rirc\"\n\t} else if this.suffix == RIRCI {\n\t\treturn \"rirci\"\n\t} else if this.suffix == ZIR {\n\t\treturn \"zir\"\n\t} else if this.suffix == ZIRC {\n\t\treturn \"zirc\"\n\t} else if this.suffix == ZIRCI {\n\t\treturn \"zirci\"\n\t} else if this.suffix == S_RIRC {\n\t\treturn \"s_zirc\"\n\t} else if this.suffix == S_RIRCI {\n\t\treturn \"s_zirci\"\n\t} else if this.suffix == U_RIRC {\n\t\treturn \"u_zirc\"\n\t} else if this.suffix == U_RIRCI {\n\t\treturn \"u_zirci\"\n\t} else if this.suffix == R {\n\t\treturn \"r\"\n\t} else if this.suffix == RCI {\n\t\treturn \"rci\"\n\t} else if this.suffix == Z {\n\t\treturn \"z\"\n\t} else if this.suffix == ZCI {\n\t\treturn \"zci\"\n\t} else if this.suffix == S_R {\n\t\treturn \"s_r\"\n\t} else if this.suffix == S_RCI {\n\t\treturn \"s_rci\"\n\t} else if this.suffix == U_R {\n\t\treturn \"u_r\"\n\t} else if this.suffix == U_RCI {\n\t\treturn \"u_rci\"\n\t} else if this.suffix == CI {\n\t\treturn \"ci\"\n\t} else if this.suffix == I {\n\t\treturn \"i\"\n\t} else if this.suffix == DDCI {\n\t\treturn \"ddci\"\n\t} else if this.suffix == ERRI {\n\t\treturn \"erri\"\n\t} else if this.suffix == S_ERRI {\n\t\treturn \"s_erri\"\n\t} else if this.suffix == U_ERRI {\n\t\treturn \"u_erri\"\n\t} else if this.suffix == EDRI {\n\t\treturn \"edri\"\n\t} else if this.suffix == ERII {\n\t\treturn \"erii\"\n\t} else if this.suffix == ERIR {\n\t\treturn \"erir\"\n\t} else if this.suffix == ERID {\n\t\treturn \"erid\"\n\t} else if this.suffix == DMA_RRI {\n\t\treturn \"dma_rri\"\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyGpRegDescriptor(\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n) string {\n\treturn \"r\" + strconv.Itoa(gp_reg_descriptor.Index())\n}\n\nfunc (this *Instruction) StringifySrcRegDescriptor(\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n) string {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\treturn this.StringifyGpRegDescriptor(src_reg_descriptor.GpRegDescriptor())\n\t} else {\n\t\tsp_reg_descriptor := src_reg_descriptor.SpRegDescriptor()\n\n\t\tif *sp_reg_descriptor == reg_descriptor.ZERO {\n\t\t\treturn \"zero\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ONE {\n\t\t\treturn \"one\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.LNEG {\n\t\t\treturn \"lneg\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.MNEG {\n\t\t\treturn \"mneg\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID {\n\t\t\treturn \"id\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID2 {\n\t\t\treturn \"id2\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID4 {\n\t\t\treturn \"id4\"\n\t\t} else if *sp_reg_descriptor == reg_descriptor.ID8 {\n\t\t\treturn \"id8\"\n\t\t} else {\n\t\t\terr := errors.New(\"sp reg descriptor is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Instruction) StringifyPairRegDescriptor(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n) string {\n\treturn \"d\" + strconv.Itoa(pair_reg_descriptor.Index())\n}\n\nfunc (this *Instruction) StringifyImm(imm *abi.Immediate) string {\n\treturn strconv.FormatInt(imm.Value(), 10)\n}\n\nfunc (this *Instruction) StringifyCondition(condition cc.Condition) string {\n\tif condition == cc.TRUE {\n\t\treturn \"true\"\n\t} else if condition == cc.FALSE {\n\t\treturn \"false\"\n\t} else if condition == cc.Z {\n\t\treturn \"z\"\n\t} else if condition == cc.NZ {\n\t\treturn \"nz\"\n\t} else if condition == cc.E {\n\t\treturn \"e\"\n\t} else if condition == cc.O {\n\t\treturn \"o\"\n\t} else if condition == cc.PL {\n\t\treturn \"pl\"\n\t} else if condition == cc.MI {\n\t\treturn \"mi\"\n\t} else if condition == cc.OV {\n\t\treturn \"ov\"\n\t} else if condition == cc.NOV {\n\t\treturn \"nov\"\n\t} else if condition == cc.C {\n\t\treturn \"c\"\n\t} else if condition == cc.NC {\n\t\treturn \"nc\"\n\t} else if condition == cc.SZ {\n\t\treturn \"sz\"\n\t} else if condition == cc.SNZ {\n\t\treturn \"snz\"\n\t} else if condition == cc.SPL {\n\t\treturn \"spl\"\n\t} else if condition == cc.SMI {\n\t\treturn \"smi\"\n\t} else if condition == cc.SO {\n\t\treturn \"so\"\n\t} else if condition == cc.SE {\n\t\treturn \"se\"\n\t} else if condition == cc.NC5 {\n\t\treturn \"nc5\"\n\t} else if condition == cc.NC6 {\n\t\treturn \"nc6\"\n\t} else if condition == cc.NC7 {\n\t\treturn \"nc7\"\n\t} else if condition == cc.NC8 {\n\t\treturn \"nc8\"\n\t} else if condition == cc.NC9 {\n\t\treturn \"nc9\"\n\t} else if condition == cc.NC10 {\n\t\treturn \"nc10\"\n\t} else if condition == cc.NC11 {\n\t\treturn \"nc11\"\n\t} else if condition == cc.NC12 {\n\t\treturn \"nc12\"\n\t} else if condition == cc.NC13 {\n\t\treturn \"nc13\"\n\t} else if condition == cc.NC14 {\n\t\treturn \"nc14\"\n\t} else if condition == cc.MAX {\n\t\treturn \"max\"\n\t} else if condition == cc.NMAX {\n\t\treturn \"nmax\"\n\t} else if condition == cc.SH32 {\n\t\treturn \"sh32\"\n\t} else if condition == cc.NSH32 {\n\t\treturn \"nsh32\"\n\t} else if condition == cc.EQ {\n\t\treturn \"eq\"\n\t} else if condition == cc.NEQ {\n\t\treturn \"neq\"\n\t} else if condition == cc.LTU {\n\t\treturn \"ltu\"\n\t} else if condition == cc.LEU {\n\t\treturn \"leu\"\n\t} else if condition == cc.GTU {\n\t\treturn \"gtu\"\n\t} else if condition == cc.GEU {\n\t\treturn \"geu\"\n\t} else if condition == cc.LTS {\n\t\treturn \"lts\"\n\t} else if condition == cc.LES {\n\t\treturn \"les\"\n\t} else if condition == cc.GTS {\n\t\treturn \"gts\"\n\t} else if condition == cc.GES {\n\t\treturn \"ges\"\n\t} else if condition == cc.XZ {\n\t\treturn \"xz\"\n\t} else if condition == cc.XNZ {\n\t\treturn \"xnz\"\n\t} else if condition == cc.XLEU {\n\t\treturn \"xleu\"\n\t} else if condition == cc.XGTU {\n\t\treturn \"xgtu\"\n\t} else if condition == cc.XLES {\n\t\treturn \"xles\"\n\t} else if condition == cc.XGTS {\n\t\treturn \"xgts\"\n\t} else if condition == cc.SMALL {\n\t\treturn \"small\"\n\t} else if condition == cc.LARGE {\n\t\treturn \"large\"\n\t} else {\n\t\terr := errors.New(\"condition is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyEndian(endian Endian) string {\n\tif endian == LITTLE {\n\t\treturn \"!little\"\n\t} else if endian == BIG {\n\t\treturn \"!big\"\n\t} else {\n\t\terr := errors.New(\"endian is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Instruction) StringifyOff(off *abi.Immediate) string {\n\treturn strconv.FormatInt(off.Value(), 10)\n}\n\nfunc (this *Instruction) StringifyPc(pc *abi.Immediate) string {\n\treturn strconv.FormatInt(pc.Value(), 10)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/op_code.go",
    "content": "package instruction\n\ntype OpCode int\n\nconst (\n\tACQUIRE OpCode = iota\n\tRELEASE\n\n\tADD\n\tADDC\n\tAND\n\tANDN\n\tASR\n\tCAO\n\tCLO\n\tCLS\n\tCLZ\n\tCMPB4\n\tDIV_STEP\n\tEXTSB\n\tEXTSH\n\tEXTUB\n\tEXTUH\n\tLSL\n\tLSL_ADD\n\tLSL_SUB\n\tLSL1\n\tLSL1X\n\tLSLX\n\tLSR\n\tLSR_ADD\n\tLSR1\n\tLSR1X\n\tLSRX\n\tMUL_SH_SH\n\tMUL_SH_SL\n\tMUL_SH_UH\n\tMUL_SH_UL\n\tMUL_SL_SH\n\tMUL_SL_SL\n\tMUL_SL_UH\n\tMUL_SL_UL\n\tMUL_STEP\n\tMUL_UH_UH\n\tMUL_UH_UL\n\tMUL_UL_UH\n\tMUL_UL_UL\n\tNAND\n\tNOR\n\tNXOR\n\tOR\n\tORN\n\tROL\n\tROL_ADD\n\tROR\n\tRSUB\n\tRSUBC\n\tSUB\n\tSUBC\n\tXOR\n\n\tBOOT\n\tRESUME\n\tSTOP\n\n\tCALL\n\n\tFAULT\n\tNOP\n\tSATS\n\tMOVD\n\tSWAPD\n\n\tHASH\n\tTIME\n\tTIME_CFG\n\n\tLBS\n\tLBU\n\tLD\n\tLHS\n\tLHU\n\tLW\n\n\tSB\n\tSB_ID\n\tSD\n\tSD_ID\n\tSH\n\tSH_ID\n\tSW\n\tSW_ID\n\n\tLDMA\n\tLDMAI\n\tSDMA\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/reg_descriptor/gp_reg_descriptor.go",
    "content": "package reg_descriptor\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype GpRegDescriptor struct {\n\tindex int\n}\n\nfunc (this *GpRegDescriptor) Init(index int) {\n\tif index < 0 {\n\t\terr := errors.New(\"index < 0\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif index >= config_loader.NumGpRegisters() {\n\t\terr := errors.New(\"index >= num gp registers\")\n\t\tpanic(err)\n\t}\n\n\tthis.index = index\n}\n\nfunc (this *GpRegDescriptor) Index() int {\n\treturn this.index\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/reg_descriptor/pair_reg_descriptor.go",
    "content": "package reg_descriptor\n\nimport (\n\t\"errors\"\n)\n\ntype PairRegDescriptor struct {\n\teven_reg_descriptor *GpRegDescriptor\n\todd_reg_descriptor  *GpRegDescriptor\n}\n\nfunc (this *PairRegDescriptor) Init(index int) {\n\tif index%2 != 0 {\n\t\terr := errors.New(\"index %2 != 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.even_reg_descriptor = new(GpRegDescriptor)\n\tthis.even_reg_descriptor.Init(index)\n\n\tthis.odd_reg_descriptor = new(GpRegDescriptor)\n\tthis.odd_reg_descriptor.Init(index + 1)\n}\n\nfunc (this *PairRegDescriptor) Index() int {\n\treturn this.even_reg_descriptor.Index()\n}\n\nfunc (this *PairRegDescriptor) EvenRegDescriptor() *GpRegDescriptor {\n\treturn this.even_reg_descriptor\n}\n\nfunc (this *PairRegDescriptor) OddRegDescriptor() *GpRegDescriptor {\n\treturn this.odd_reg_descriptor\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/reg_descriptor/sp_reg_descriptor.go",
    "content": "package reg_descriptor\n\ntype SpRegDescriptor int\n\nconst (\n\tZERO SpRegDescriptor = iota\n\tONE\n\tLNEG\n\tMNEG\n\tID\n\tID2\n\tID4\n\tID8\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/reg_descriptor/src_reg_descriptor.go",
    "content": "package reg_descriptor\n\ntype SrcRegDescriptor struct {\n\tgp_reg_descriptor *GpRegDescriptor\n\tsp_reg_descriptor *SpRegDescriptor\n}\n\nfunc (this *SrcRegDescriptor) InitGpRegDescriptor(gp_reg_descriptor *GpRegDescriptor) {\n\tthis.gp_reg_descriptor = gp_reg_descriptor\n\tthis.sp_reg_descriptor = nil\n}\n\nfunc (this *SrcRegDescriptor) InitSpRegDescriptor(sp_reg_descriptor *SpRegDescriptor) {\n\tthis.gp_reg_descriptor = nil\n\tthis.sp_reg_descriptor = sp_reg_descriptor\n}\n\nfunc (this *SrcRegDescriptor) IsGpRegDescriptor() bool {\n\treturn this.gp_reg_descriptor != nil\n}\n\nfunc (this *SrcRegDescriptor) IsSpRegDescriptor() bool {\n\treturn this.sp_reg_descriptor != nil\n}\n\nfunc (this *SrcRegDescriptor) GpRegDescriptor() *GpRegDescriptor {\n\treturn this.gp_reg_descriptor\n}\n\nfunc (this *SrcRegDescriptor) SpRegDescriptor() *SpRegDescriptor {\n\treturn this.sp_reg_descriptor\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/instruction/suffix.go",
    "content": "package instruction\n\ntype Suffix int\n\nconst (\n\tRICI Suffix = iota\n\n\tRRI\n\tRRIC\n\tRRICI\n\tRRIF\n\tRRR\n\tRRRC\n\tRRRCI\n\n\tZRI\n\tZRIC\n\tZRICI\n\tZRIF\n\tZRR\n\tZRRC\n\tZRRCI\n\n\tS_RRI\n\tS_RRIC\n\tS_RRICI\n\tS_RRIF\n\tS_RRR\n\tS_RRRC\n\tS_RRRCI\n\n\tU_RRI\n\tU_RRIC\n\tU_RRICI\n\tU_RRIF\n\tU_RRR\n\tU_RRRC\n\tU_RRRCI\n\n\tRR\n\tRRC\n\tRRCI\n\n\tZR\n\tZRC\n\tZRCI\n\n\tS_RR\n\tS_RRC\n\tS_RRCI\n\n\tU_RR\n\tU_RRC\n\tU_RRCI\n\n\tDRDICI\n\n\tRRRI\n\tRRRICI\n\n\tZRRI\n\tZRRICI\n\n\tS_RRRI\n\tS_RRRICI\n\n\tU_RRRI\n\tU_RRRICI\n\n\tRIR\n\tRIRC\n\tRIRCI\n\n\tZIR\n\tZIRC\n\tZIRCI\n\n\tS_RIRC\n\tS_RIRCI\n\n\tU_RIRC\n\tU_RIRCI\n\n\tR\n\tRCI\n\n\tZ\n\tZCI\n\n\tS_R\n\tS_RCI\n\n\tU_R\n\tU_RCI\n\n\tCI\n\tI\n\n\tDDCI\n\n\tERRI\n\n\tS_ERRI\n\tU_ERRI\n\n\tEDRI\n\n\tERII\n\tERIR\n\tERID\n\n\tDMA_RRI\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/kernel.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Kernel struct {\n\taddresses map[string]int64\n\n\tatomic *encoding.ByteStream\n\tiram   *encoding.ByteStream\n\twram   *encoding.ByteStream\n\tmram   *encoding.ByteStream\n}\n\nfunc (this *Kernel) Init() {\n\tthis.addresses = make(map[string]int64)\n}\n\nfunc (this *Kernel) Address(label_name string) int64 {\n\tif address, found := this.addresses[label_name]; found {\n\t\treturn address\n\t} else {\n\t\terr := errors.New(\"address is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Kernel) Atomic() *encoding.ByteStream {\n\treturn this.atomic\n}\n\nfunc (this *Kernel) SetAtomic(atomic *encoding.ByteStream) {\n\tthis.atomic = atomic\n}\n\nfunc (this *Kernel) Iram() *encoding.ByteStream {\n\treturn this.iram\n}\n\nfunc (this *Kernel) SetIram(iram *encoding.ByteStream) {\n\tthis.iram = iram\n}\n\nfunc (this *Kernel) Wram() *encoding.ByteStream {\n\treturn this.wram\n}\n\nfunc (this *Kernel) SetWram(wram *encoding.ByteStream) {\n\tthis.wram = wram\n}\n\nfunc (this *Kernel) Mram() *encoding.ByteStream {\n\treturn this.mram\n}\n\nfunc (this *Kernel) SetMram(mram *encoding.ByteStream) {\n\tthis.mram = mram\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/label.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Label struct {\n\tname        string\n\taddress     *int64\n\tsize        int64\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Label) Init(name string) {\n\tthis.name = name\n\tthis.address = nil\n\tthis.size = 0\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n}\n\nfunc (this *Label) Name() string {\n\treturn this.name\n}\n\nfunc (this *Label) Address() int64 {\n\tif this.address == nil {\n\t\terr := errors.New(\"address is not yet set\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.address\n}\n\nfunc (this *Label) BeginAddress() int64 {\n\treturn this.Address()\n}\n\nfunc (this *Label) EndAddress() int64 {\n\treturn this.Address() + this.Size()\n}\n\nfunc (this *Label) SetAddress(address int64) {\n\tif this.address != nil {\n\t\terr := errors.New(\"address is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.address = new(int64)\n\t*this.address = address\n}\n\nfunc (this *Label) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Label) SetSize(size int64) {\n\tthis.size = size\n}\n\nfunc (this *Label) ToByteStream() *encoding.ByteStream {\n\tif this.size != this.byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\treturn this.byte_stream\n}\n\nfunc (this *Label) Append(encodable Encodable) {\n\tthis.byte_stream.Merge(encodable.Encode())\n\n\tif this.byte_stream.Size() > this.size {\n\t\terr := errors.New(\"byte stream's size > size\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/liveness.go",
    "content": "package kernel\n\ntype Liveness struct {\n\tdefs           map[string]bool\n\tuses           map[string]bool\n\tglobal_symbols map[string]bool\n}\n\nfunc (this *Liveness) Init() {\n\tthis.defs = make(map[string]bool)\n\tthis.uses = make(map[string]bool)\n\tthis.global_symbols = make(map[string]bool)\n}\n\nfunc (this *Liveness) Defs() map[string]bool {\n\treturn this.defs\n}\n\nfunc (this *Liveness) AddDef(def string) {\n\tthis.defs[def] = true\n}\n\nfunc (this *Liveness) Uses() map[string]bool {\n\treturn this.uses\n}\n\nfunc (this *Liveness) AddUse(use string) {\n\tthis.uses[use] = true\n}\n\nfunc (this *Liveness) GlobalSymbols() map[string]bool {\n\treturn this.global_symbols\n}\n\nfunc (this *Liveness) AddGlobalSymbol(global_symbol string) {\n\tthis.global_symbols[global_symbol] = true\n}\n\nfunc (this *Liveness) LocalSymbols() map[string]bool {\n\tlocal_symbols := make(map[string]bool)\n\tfor def, _ := range this.defs {\n\t\tif _, found := this.global_symbols[def]; !found {\n\t\t\tlocal_symbols[def] = true\n\t\t}\n\t}\n\treturn local_symbols\n}\n\nfunc (this *Liveness) UnresolvedSymbols() map[string]bool {\n\tunresolved_symbols := make(map[string]bool)\n\tfor use, _ := range this.uses {\n\t\tif _, found := this.defs[use]; !found {\n\t\t\tunresolved_symbols[use] = true\n\t\t}\n\t}\n\treturn unresolved_symbols\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/relocatable.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"strings\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Relocatable struct {\n\tname string\n\tpath string\n\n\ttoken_stream *lexer.TokenStream\n\tast          *parser.Ast\n\tliveness     *Liveness\n\n\trenames map[string]string\n}\n\nfunc (this *Relocatable) Init(name string) {\n\tthis.name = name\n\n\tthis.renames = make(map[string]string)\n}\n\nfunc (this *Relocatable) Name() string {\n\treturn this.name\n}\n\nfunc (this *Relocatable) Path() string {\n\treturn this.path\n}\n\nfunc (this *Relocatable) SetPath(path string) {\n\tthis.path = path\n}\n\nfunc (this *Relocatable) TokenStream() *lexer.TokenStream {\n\treturn this.token_stream\n}\n\nfunc (this *Relocatable) SetTokenStream(token_stream *lexer.TokenStream) {\n\tthis.token_stream = token_stream\n}\n\nfunc (this *Relocatable) Ast() *parser.Ast {\n\treturn this.ast\n}\n\nfunc (this *Relocatable) SetAst(ast *parser.Ast) {\n\tthis.ast = ast\n}\n\nfunc (this *Relocatable) Liveness() *Liveness {\n\treturn this.liveness\n}\n\nfunc (this *Relocatable) SetLiveness(liveness *Liveness) {\n\tthis.liveness = liveness\n}\n\nfunc (this *Relocatable) Lines() []string {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(this.path)\n\n\tlines := file_scanner.ReadLines()\n\tfor i, line := range lines {\n\t\tlines[i] = this.RenameLine(line)\n\t}\n\treturn lines\n}\n\nfunc (this *Relocatable) RenameLocalSymbol(old_name string, new_name string) {\n\tif _, found := this.liveness.LocalSymbols()[old_name]; !found {\n\t\terr := errors.New(\"local symbol is not found\")\n\t\tpanic(err)\n\t}\n\n\tif rename, found := this.renames[old_name]; found {\n\t\tif rename != new_name {\n\t\t\terr := errors.New(\"rename is already set\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.renames[old_name] = new_name\n}\n\nfunc (this *Relocatable) RenameLine(line string) string {\n\tfor old_name, new_name := range this.renames {\n\t\tline = strings.ReplaceAll(line, old_name+\",\", new_name+\",\")\n\t\tline = strings.ReplaceAll(line, old_name+\" \", new_name+\" \")\n\t\tline = strings.ReplaceAll(line, old_name+\"\\t\", new_name+\"\\t\")\n\t\tline = strings.ReplaceAll(line, old_name+\":\", new_name+\":\")\n\t\tline = strings.ReplaceAll(line, old_name+\"+\", new_name+\"+\")\n\t\tline = strings.ReplaceAll(line, old_name+\"-\", new_name+\"-\")\n\n\t\tif len(line) > len(old_name) {\n\t\t\tpos := len(line) - len(old_name)\n\n\t\t\tif line[pos:] == old_name {\n\t\t\t\tline = line[:pos] + new_name\n\t\t\t}\n\t\t}\n\t}\n\treturn line\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/kernel/section.go",
    "content": "package kernel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype SectionName int\n\nconst (\n\tATOMIC SectionName = iota\n\tBSS\n\tDATA\n\tDEBUG_ABBREV\n\tDEBUG_FRAME\n\tDEBUG_INFO\n\tDEBUG_LINE\n\tDEBUG_LOC\n\tDEBUG_RANGES\n\tDEBUG_STR\n\tDPU_HOST\n\tMRAM\n\tRODATA\n\tSTACK_SIZES\n\tTEXT\n)\n\ntype SectionFlag int\n\nconst (\n\tALLOC SectionFlag = iota\n\tWRITE\n\tEXECINSTR\n\tLINK_ORDER\n\tMERGE\n\tSTRINGS\n)\n\ntype SectionType int\n\nconst (\n\tPROGBITS SectionType = iota\n\tNOBITS\n)\n\ntype Section struct {\n\tsection_name  SectionName\n\tname          string\n\tsection_flags map[SectionFlag]bool\n\tsection_type  SectionType\n\n\tlabels    []*Label\n\tcur_label *Label\n}\n\nfunc (this *Section) Init(\n\tsection_name SectionName,\n\tname string,\n\tsection_flags map[SectionFlag]bool,\n\tsection_type SectionType,\n) {\n\tthis.section_name = section_name\n\tthis.name = name\n\tthis.section_flags = section_flags\n\tthis.section_type = section_type\n\n\tdefault_label := new(Label)\n\tdefault_label.Init(this.HiddenLabelName())\n\n\tthis.labels = make([]*Label, 0)\n\tthis.labels = append(this.labels, default_label)\n\n\tthis.cur_label = default_label\n}\n\nfunc (this *Section) SectionName() SectionName {\n\treturn this.section_name\n}\n\nfunc (this *Section) Name() string {\n\treturn this.name\n}\n\nfunc (this *Section) SectionFlags() map[SectionFlag]bool {\n\treturn this.section_flags\n}\n\nfunc (this *Section) SectionType() SectionType {\n\treturn this.section_type\n}\n\nfunc (this *Section) Address() int64 {\n\treturn this.labels[0].Address()\n}\n\nfunc (this *Section) SetAddress(address int64) {\n\tcur_address := address\n\tfor _, label := range this.labels {\n\t\tlabel.SetAddress(cur_address)\n\t\tcur_address += label.Size()\n\t}\n}\n\nfunc (this *Section) Size() int64 {\n\tsize := int64(0)\n\tfor _, label := range this.labels {\n\t\tsize += label.Size()\n\t}\n\treturn size\n}\n\nfunc (this *Section) Label(label_name string) *Label {\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn label\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *Section) Labels() []*Label {\n\treturn this.labels\n}\n\nfunc (this *Section) AppendLabel(label_name string) {\n\tlabel := new(Label)\n\tlabel.Init(label_name)\n\n\tthis.labels = append(this.labels, label)\n}\n\nfunc (this *Section) CheckoutLabel(label_name string) {\n\tif this.Label(label_name) == nil {\n\t\terr := errors.New(\"label is not found\")\n\t\tpanic(err)\n\t}\n\n\tthis.cur_label = this.Label(label_name)\n}\n\nfunc (this *Section) CurLabel() *Label {\n\treturn this.cur_label\n}\n\nfunc (this *Section) ToByteStream() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, label := range this.labels {\n\t\tbyte_stream.Merge(label.ToByteStream())\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Section) HiddenLabelName() string {\n\tif this.section_name == ATOMIC {\n\t\treturn \"atomic.\" + this.name\n\t} else if this.section_name == BSS {\n\t\treturn \"bss.\" + this.name\n\t} else if this.section_name == DATA {\n\t\treturn \"data.\" + this.name\n\t} else if this.section_name == DEBUG_ABBREV {\n\t\treturn \"debug_abbrev.\" + this.name\n\t} else if this.section_name == DEBUG_FRAME {\n\t\treturn \"debug_frame.\" + this.name\n\t} else if this.section_name == DEBUG_INFO {\n\t\treturn \"debug_info.\" + this.name\n\t} else if this.section_name == DEBUG_LINE {\n\t\treturn \"debug_line.\" + this.name\n\t} else if this.section_name == DEBUG_LOC {\n\t\treturn \"debug_loc.\" + this.name\n\t} else if this.section_name == DEBUG_RANGES {\n\t\treturn \"debug_ranges.\" + this.name\n\t} else if this.section_name == DEBUG_STR {\n\t\treturn \"debug_str.\" + this.name\n\t} else if this.section_name == DPU_HOST {\n\t\treturn \"dpu_host.\" + this.name\n\t} else if this.section_name == MRAM {\n\t\treturn \"mram.\" + this.name\n\t} else if this.section_name == RODATA {\n\t\treturn \"rodata.\" + this.name\n\t} else if this.section_name == STACK_SIZES {\n\t\treturn \"stack_sizes.\" + this.name\n\t} else if this.section_name == TEXT {\n\t\treturn \"text.\" + this.name\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lex_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype LexJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *LexJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *LexJob) Execute() {\n\tfmt.Printf(\"Lexing %s...\\n\", this.relocatable.Path())\n\n\tlexer_ := new(lexer.Lexer)\n\tlexer_.Init()\n\n\ttoken_stream := lexer_.Lex(this.relocatable.Path())\n\tthis.relocatable.SetTokenStream(token_stream)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/keyword_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype KeywordFactory struct {\n\tkeywords map[string]TokenType\n}\n\nfunc (this *KeywordFactory) Init() {\n\tthis.keywords = make(map[string]TokenType)\n}\n\nfunc (this *KeywordFactory) AddKeyword(keyword string, token_type TokenType) {\n\tthis.keywords[keyword] = token_type\n}\n\nfunc (this *KeywordFactory) IsTokenizable(word string) bool {\n\t_, found := this.keywords[word]\n\treturn found\n}\n\nfunc (this *KeywordFactory) Tokenize(word string) *Token {\n\tif _, found := this.keywords[word]; !found {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\ttoken_type := this.keywords[word]\n\n\ttoken := new(Token)\n\ttoken.Init(token_type, \"\")\n\treturn token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/lexer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Lexer struct {\n\ttokenizer *Tokenizer\n}\n\nfunc (this *Lexer) Init() {\n\tthis.tokenizer = new(Tokenizer)\n\tthis.tokenizer.Init()\n}\n\nfunc (this *Lexer) Lex(path string) *TokenStream {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tfor _, line := range file_scanner.ReadLines() {\n\t\ttoken_stream.Merge(this.Tokenize(line))\n\n\t\tnew_line := new(Token)\n\t\tnew_line.Init(NEW_LINE, \"\")\n\n\t\ttoken_stream.Append(new_line)\n\t}\n\n\tend_of_file := new(Token)\n\tend_of_file.Init(END_OF_FILE, \"\")\n\n\ttoken_stream.Append(end_of_file)\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) Tokenize(line string) *TokenStream {\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tprev_pos := 0\n\tfor prev_pos < len(line) {\n\t\ttoken, length := this.FindTokenWithMaxLength(line, prev_pos)\n\n\t\tif token != nil {\n\t\t\ttoken_stream.Append(token)\n\t\t}\n\n\t\tprev_pos += length\n\t}\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) FindTokenWithMaxLength(line string, prev_pos int) (*Token, int) {\n\tif prev_pos < 0 {\n\t\terr := errors.New(\"prev pos < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.IsWhiteSpace(string(line[prev_pos])) {\n\t\treturn nil, 1\n\t}\n\n\tif prev_pos+2 < len(line) && this.IsComment(line[prev_pos:prev_pos+2]) {\n\t\treturn nil, len(line) - prev_pos\n\t}\n\n\tif this.IsQuote(string(line[prev_pos])) {\n\t\tnext_quote_pos := this.FindNextQuote(line, prev_pos+1)\n\n\t\tword := line[prev_pos : next_quote_pos+1]\n\n\t\ttoken := this.tokenizer.Tokenize(word)\n\n\t\treturn token, next_quote_pos - prev_pos + 1\n\t}\n\n\tfor i := prev_pos + 1; i <= len(line); i++ {\n\t\tword := line[prev_pos:i]\n\n\t\tif i+1 <= len(line) {\n\t\t\tnext_word := line[prev_pos : i+1]\n\n\t\t\tif this.tokenizer.IsTokenizable(word) && !this.tokenizer.IsTokenizable(next_word) {\n\t\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\t\treturn token, i - prev_pos\n\t\t\t}\n\t\t} else {\n\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\treturn token, i - prev_pos\n\t\t}\n\t}\n\n\terr := errors.New(\"line is not further tokenizable\")\n\tpanic(err)\n}\n\nfunc (this *Lexer) IsWhiteSpace(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \" \" || word == \"\\t\" || word == \"\\n\"\n}\n\nfunc (this *Lexer) IsComment(word string) bool {\n\tif len(word) != 2 {\n\t\terr := errors.New(\"word size != 2\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \"//\"\n}\n\nfunc (this *Lexer) IsQuote(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \"\\\"\"\n}\n\nfunc (this *Lexer) FindNextQuote(line string, pos int) int {\n\tfor i := pos; i < len(line); i++ {\n\t\tif this.IsQuote(string(line[i])) {\n\t\t\treturn i\n\t\t}\n\t}\n\n\terr := errors.New(\"line does not have the next quote\")\n\tpanic(err)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/regex.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"regexp\"\n)\n\ntype Regex struct {\n\texpr  string\n\tregex *regexp.Regexp\n\n\ttoken_type TokenType\n}\n\nfunc (this *Regex) Init(expr string, token_type TokenType) {\n\tthis.expr = expr\n\n\tregex, err := regexp.Compile(expr)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.regex = regex\n\n\tthis.token_type = token_type\n}\n\nfunc (this *Regex) Expr() string {\n\treturn this.expr\n}\n\nfunc (this *Regex) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Regex) IsTokenizable(word string) bool {\n\treturn this.regex.MatchString(word)\n}\n\nfunc (this *Regex) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not matched\")\n\t\tpanic(err)\n\t}\n\n\ttoken := new(Token)\n\ttoken.Init(this.token_type, word)\n\treturn token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/regex_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype RegexFactory struct {\n\tregexes []*Regex\n}\n\nfunc (this *RegexFactory) Init() {\n\tthis.regexes = make([]*Regex, 0)\n}\n\nfunc (this *RegexFactory) HasRegex(expr string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.Expr() == expr {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) AddRegex(expr string, token_type TokenType) {\n\tif this.HasRegex(expr) {\n\t\terr := errors.New(\"regex already exists\")\n\t\tpanic(err)\n\t}\n\n\tregex := new(Regex)\n\tregex.Init(expr, token_type)\n\n\tthis.regexes = append(this.regexes, regex)\n}\n\nfunc (this *RegexFactory) IsTokenizable(word string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\ttoken := new(Token)\n\t\t\ttoken.Init(regex.TokenType(), word)\n\t\t\treturn token\n\t\t}\n\t}\n\n\treturn nil\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/token.go",
    "content": "package lexer\n\ntype TokenType int\n\nconst (\n\tEND_OF_FILE TokenType = iota\n\n\tNEW_LINE\n\n\tIDENTIFIER\n\tPOSITIVIE_NUMBER\n\tHEX_NUMBER\n\tSTRING\n\tGP_REG\n\tPAIR_REG\n\n\tACQUIRE\n\tRELEASE\n\tBOOT\n\tRESUME\n\n\tADD\n\tADDC\n\tAND\n\tANDN\n\tASR\n\tCMPB4\n\tLSL\n\tLSL1\n\tLSL1X\n\tLSLX\n\tLSR\n\tLSR1\n\tLSR1X\n\tLSRX\n\tMUL_SH_SH\n\tMUL_SH_SL\n\tMUL_SH_UH\n\tMUL_SH_UL\n\tMUL_SL_SH\n\tMUL_SL_SL\n\tMUL_SL_UH\n\tMUL_SL_UL\n\tMUL_UH_UH\n\tMUL_UH_UL\n\tMUL_UL_UH\n\tMUL_UL_UL\n\tNAND\n\tNOR\n\tNXOR\n\tOR\n\tORN\n\tROL\n\tROR\n\tRSUB\n\tRSUBC\n\tSUB\n\tSUBC\n\tXOR\n\tCALL\n\tHASH\n\n\tCAO\n\tCLO\n\tCLS\n\tCLZ\n\tEXTSB\n\tEXTSH\n\tEXTUB\n\tEXTUH\n\tSATS\n\tTIME_CFG\n\n\tDIV_STEP\n\tMUL_STEP\n\n\tLSL_ADD\n\tLSL_SUB\n\tLSR_ADD\n\tROL_ADD\n\n\tTIME\n\tNOP\n\n\tSTOP\n\n\tFAULT\n\n\tMOVD\n\tSWAPD\n\n\tLBS\n\tLBU\n\tLD\n\tLHS\n\tLHU\n\tLW\n\n\tSB\n\tSB_ID\n\tSD\n\tSD_ID\n\tSH\n\tSH_ID\n\tSW\n\tSW_ID\n\n\tLDMA\n\tLDMAI\n\tSDMA\n\n\tMOVE\n\tNEG\n\tNOT\n\tBKP\n\n\tJEQ\n\tJNEQ\n\tJZ\n\tJNZ\n\tJLTU\n\tJGTU\n\tJLEU\n\tJGEU\n\tJLTS\n\tJGTS\n\tJLES\n\tJGES\n\tJUMP\n\n\tS\n\tU\n\n\tATOMIC\n\tBSS\n\tDATA\n\tDEBUG_ABBREV\n\tDEBUG_FRAME\n\tDEBUG_INFO\n\tDEBUG_LINE\n\tDEBUG_LOC\n\tDEBUG_RANGES\n\tDEBUG_STR\n\tDPU_HOST\n\tMRAM\n\tRODATA\n\tSTACK_SIZES\n\tTEXT\n\n\tPROGBITS\n\tNOBITS\n\n\tFUNCTION\n\tOBJECT\n\n\tTRUE\n\tFALSE\n\tZ\n\tNZ\n\tE\n\tO\n\tPL\n\tMI\n\tOV\n\tNOV\n\tC\n\tNC\n\tSZ\n\tSNZ\n\tSPL\n\tSMI\n\tSO\n\tSE\n\tNC5\n\tNC6\n\tNC7\n\tNC8\n\tNC9\n\tNC10\n\tNC11\n\tNC12\n\tNC13\n\tNC14\n\tMAX\n\tNMAX\n\tSH32\n\tNSH32\n\tEQ\n\tNEQ\n\tLTU\n\tLEU\n\tGTU\n\tGEU\n\tLTS\n\tLES\n\tGTS\n\tGES\n\tXZ\n\tXNZ\n\tXLEU\n\tXGTU\n\tXLES\n\tXGTS\n\tSMALL\n\tLARGE\n\n\tLITTLE\n\tBIG\n\n\tZERO_REG\n\tONE\n\tID\n\tID2\n\tID4\n\tID8\n\tLNEG\n\tMNEG\n\n\tADDRSIG\n\tADDRSIG_SYM\n\tASCII\n\tASCIZ\n\tBYTE\n\tCFI_DEF_CFA_OFFSET\n\tCFI_ENDPROC\n\tCFI_OFFSET\n\tCFI_SECTIONS\n\tCFI_STARTPROC\n\tFILE\n\tGLOBL\n\tLOC\n\tLONG\n\tP2ALIGN\n\tQUAD\n\tSECTION\n\tSET\n\tSHORT\n\tSIZE\n\tTYPE\n\tWEAK\n\tZERO_DIRECTIVE\n\n\tIS_STMT\n\tPROLOGUE_END\n\n\tCOLON\n\tCOMMA\n\tPLUS\n\tMINUS\n)\n\ntype Token struct {\n\ttoken_type TokenType\n\tattribute  string\n}\n\nfunc (this *Token) Init(token_type TokenType, attribute string) {\n\tthis.token_type = token_type\n\tthis.attribute = attribute\n}\n\nfunc (this *Token) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Token) Attribute() string {\n\treturn this.attribute\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/token_stream.go",
    "content": "package lexer\n\ntype TokenStream struct {\n\ttokens []*Token\n}\n\nfunc (this *TokenStream) Init() {\n\tthis.tokens = make([]*Token, 0)\n}\n\nfunc (this *TokenStream) Length() int {\n\treturn len(this.tokens)\n}\n\nfunc (this *TokenStream) Get(pos int) *Token {\n\treturn this.tokens[pos]\n}\n\nfunc (this *TokenStream) Append(token *Token) {\n\tthis.tokens = append(this.tokens, token)\n}\n\nfunc (this *TokenStream) Merge(token_stream *TokenStream) {\n\tfor i := 0; i < token_stream.Length(); i++ {\n\t\tthis.Append(token_stream.Get(i))\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/lexer/tokenizer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype Tokenizer struct {\n\tkeyword_factory *KeywordFactory\n\tregex_factory   *RegexFactory\n}\n\nfunc (this *Tokenizer) Init() {\n\tthis.InitKeywordFactory()\n\tthis.InitRegexFactory()\n}\n\nfunc (this *Tokenizer) InitKeywordFactory() {\n\tthis.keyword_factory = new(KeywordFactory)\n\tthis.keyword_factory.Init()\n\n\tthis.keyword_factory.AddKeyword(\"acquire\", ACQUIRE)\n\tthis.keyword_factory.AddKeyword(\"release\", RELEASE)\n\tthis.keyword_factory.AddKeyword(\"boot\", BOOT)\n\tthis.keyword_factory.AddKeyword(\"resume\", RESUME)\n\n\tthis.keyword_factory.AddKeyword(\"add\", ADD)\n\tthis.keyword_factory.AddKeyword(\"addc\", ADDC)\n\tthis.keyword_factory.AddKeyword(\"and\", AND)\n\tthis.keyword_factory.AddKeyword(\"andn\", ANDN)\n\tthis.keyword_factory.AddKeyword(\"asr\", ASR)\n\tthis.keyword_factory.AddKeyword(\"cmpb4\", CMPB4)\n\tthis.keyword_factory.AddKeyword(\"lsl\", LSL)\n\tthis.keyword_factory.AddKeyword(\"lsl1\", LSL1)\n\tthis.keyword_factory.AddKeyword(\"lsl1x\", LSL1X)\n\tthis.keyword_factory.AddKeyword(\"lslx\", LSLX)\n\tthis.keyword_factory.AddKeyword(\"lsr\", LSR)\n\tthis.keyword_factory.AddKeyword(\"lsr1\", LSR1)\n\tthis.keyword_factory.AddKeyword(\"lsr1x\", LSR1X)\n\tthis.keyword_factory.AddKeyword(\"lsrx\", LSRX)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_sh\", MUL_SH_SH)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_sl\", MUL_SH_SL)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_uh\", MUL_SH_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_sh_ul\", MUL_SH_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_sh\", MUL_SL_SH)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_sl\", MUL_SL_SL)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_uh\", MUL_SL_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_sl_ul\", MUL_SL_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_uh_uh\", MUL_UH_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_uh_ul\", MUL_UH_UL)\n\tthis.keyword_factory.AddKeyword(\"mul_ul_uh\", MUL_UL_UH)\n\tthis.keyword_factory.AddKeyword(\"mul_ul_ul\", MUL_UL_UL)\n\tthis.keyword_factory.AddKeyword(\"nand\", NAND)\n\tthis.keyword_factory.AddKeyword(\"nor\", NOR)\n\tthis.keyword_factory.AddKeyword(\"nxor\", NXOR)\n\tthis.keyword_factory.AddKeyword(\"or\", OR)\n\tthis.keyword_factory.AddKeyword(\"orn\", ORN)\n\tthis.keyword_factory.AddKeyword(\"rol\", ROL)\n\tthis.keyword_factory.AddKeyword(\"ror\", ROR)\n\tthis.keyword_factory.AddKeyword(\"rsub\", RSUB)\n\tthis.keyword_factory.AddKeyword(\"rsubc\", RSUBC)\n\tthis.keyword_factory.AddKeyword(\"sub\", SUB)\n\tthis.keyword_factory.AddKeyword(\"subc\", SUBC)\n\tthis.keyword_factory.AddKeyword(\"xor\", XOR)\n\tthis.keyword_factory.AddKeyword(\"call\", CALL)\n\tthis.keyword_factory.AddKeyword(\"hash\", HASH)\n\tthis.keyword_factory.AddKeyword(\"cao\", CAO)\n\tthis.keyword_factory.AddKeyword(\"clo\", CLO)\n\tthis.keyword_factory.AddKeyword(\"cls\", CLS)\n\tthis.keyword_factory.AddKeyword(\"clz\", CLZ)\n\tthis.keyword_factory.AddKeyword(\"extsb\", EXTSB)\n\tthis.keyword_factory.AddKeyword(\"extsh\", EXTSH)\n\tthis.keyword_factory.AddKeyword(\"extub\", EXTUB)\n\tthis.keyword_factory.AddKeyword(\"extuh\", EXTUH)\n\tthis.keyword_factory.AddKeyword(\"sats\", SATS)\n\tthis.keyword_factory.AddKeyword(\"time_cfg\", TIME_CFG)\n\n\tthis.keyword_factory.AddKeyword(\"div_step\", DIV_STEP)\n\tthis.keyword_factory.AddKeyword(\"mul_step\", MUL_STEP)\n\n\tthis.keyword_factory.AddKeyword(\"lsl_add\", LSL_ADD)\n\tthis.keyword_factory.AddKeyword(\"lsl_sub\", LSL_SUB)\n\tthis.keyword_factory.AddKeyword(\"lsr_add\", LSR_ADD)\n\tthis.keyword_factory.AddKeyword(\"rol_add\", ROL_ADD)\n\n\tthis.keyword_factory.AddKeyword(\"time\", TIME)\n\tthis.keyword_factory.AddKeyword(\"nop\", NOP)\n\n\tthis.keyword_factory.AddKeyword(\"stop\", STOP)\n\tthis.keyword_factory.AddKeyword(\"fault\", FAULT)\n\n\tthis.keyword_factory.AddKeyword(\"movd\", MOVD)\n\tthis.keyword_factory.AddKeyword(\"swapd\", SWAPD)\n\n\tthis.keyword_factory.AddKeyword(\"lbs\", LBS)\n\tthis.keyword_factory.AddKeyword(\"lbu\", LBU)\n\tthis.keyword_factory.AddKeyword(\"ld\", LD)\n\tthis.keyword_factory.AddKeyword(\"lhs\", LHS)\n\tthis.keyword_factory.AddKeyword(\"lhu\", LHU)\n\tthis.keyword_factory.AddKeyword(\"lw\", LW)\n\n\tthis.keyword_factory.AddKeyword(\"sb\", SB)\n\tthis.keyword_factory.AddKeyword(\"sb_id\", SB_ID)\n\tthis.keyword_factory.AddKeyword(\"sd\", SD)\n\tthis.keyword_factory.AddKeyword(\"sd_id\", SD_ID)\n\tthis.keyword_factory.AddKeyword(\"sh\", SH)\n\tthis.keyword_factory.AddKeyword(\"sh_id\", SH_ID)\n\tthis.keyword_factory.AddKeyword(\"sw\", SW)\n\tthis.keyword_factory.AddKeyword(\"sw_id\", SW_ID)\n\n\tthis.keyword_factory.AddKeyword(\"ldma\", LDMA)\n\tthis.keyword_factory.AddKeyword(\"ldmai\", LDMAI)\n\tthis.keyword_factory.AddKeyword(\"sdma\", SDMA)\n\n\tthis.keyword_factory.AddKeyword(\"move\", MOVE)\n\tthis.keyword_factory.AddKeyword(\"neg\", NEG)\n\tthis.keyword_factory.AddKeyword(\"not\", NOT)\n\tthis.keyword_factory.AddKeyword(\"bkp\", BKP)\n\n\tthis.keyword_factory.AddKeyword(\"jeq\", JEQ)\n\tthis.keyword_factory.AddKeyword(\"jneq\", JNEQ)\n\tthis.keyword_factory.AddKeyword(\"jz\", JZ)\n\tthis.keyword_factory.AddKeyword(\"jnz\", JNZ)\n\tthis.keyword_factory.AddKeyword(\"jltu\", JLTU)\n\tthis.keyword_factory.AddKeyword(\"jgtu\", JGTU)\n\tthis.keyword_factory.AddKeyword(\"jleu\", JLEU)\n\tthis.keyword_factory.AddKeyword(\"jgeu\", JGEU)\n\tthis.keyword_factory.AddKeyword(\"jlts\", JLTS)\n\tthis.keyword_factory.AddKeyword(\"jgts\", JGTS)\n\tthis.keyword_factory.AddKeyword(\"jles\", JLES)\n\tthis.keyword_factory.AddKeyword(\"jges\", JGES)\n\tthis.keyword_factory.AddKeyword(\"jump\", JUMP)\n\n\tthis.keyword_factory.AddKeyword(\".s\", S)\n\tthis.keyword_factory.AddKeyword(\".u\", U)\n\n\tthis.keyword_factory.AddKeyword(\".atomic\", ATOMIC)\n\tthis.keyword_factory.AddKeyword(\".bss\", BSS)\n\tthis.keyword_factory.AddKeyword(\".data\", DATA)\n\tthis.keyword_factory.AddKeyword(\".debug_abbrev\", DEBUG_ABBREV)\n\tthis.keyword_factory.AddKeyword(\".debug_frame\", DEBUG_FRAME)\n\tthis.keyword_factory.AddKeyword(\".debug_info\", DEBUG_INFO)\n\tthis.keyword_factory.AddKeyword(\".debug_line\", DEBUG_LINE)\n\tthis.keyword_factory.AddKeyword(\".debug_loc\", DEBUG_LOC)\n\tthis.keyword_factory.AddKeyword(\".debug_ranges\", DEBUG_RANGES)\n\tthis.keyword_factory.AddKeyword(\".debug_str\", DEBUG_STR)\n\tthis.keyword_factory.AddKeyword(\".dpu_host\", DPU_HOST)\n\tthis.keyword_factory.AddKeyword(\".mram\", MRAM)\n\tthis.keyword_factory.AddKeyword(\".rodata\", RODATA)\n\tthis.keyword_factory.AddKeyword(\".stack_sizes\", STACK_SIZES)\n\tthis.keyword_factory.AddKeyword(\".text\", TEXT)\n\tthis.keyword_factory.AddKeyword(\".file\", FILE)\n\tthis.keyword_factory.AddKeyword(\".section\", SECTION)\n\n\tthis.keyword_factory.AddKeyword(\"@progbits\", PROGBITS)\n\tthis.keyword_factory.AddKeyword(\"@nobits\", NOBITS)\n\tthis.keyword_factory.AddKeyword(\"@function\", FUNCTION)\n\tthis.keyword_factory.AddKeyword(\"@object\", OBJECT)\n\n\tthis.keyword_factory.AddKeyword(\"true\", TRUE)\n\tthis.keyword_factory.AddKeyword(\"false\", FALSE)\n\tthis.keyword_factory.AddKeyword(\"z\", Z)\n\tthis.keyword_factory.AddKeyword(\"nz\", NZ)\n\tthis.keyword_factory.AddKeyword(\"e\", E)\n\tthis.keyword_factory.AddKeyword(\"o\", O)\n\tthis.keyword_factory.AddKeyword(\"pl\", PL)\n\tthis.keyword_factory.AddKeyword(\"mi\", MI)\n\tthis.keyword_factory.AddKeyword(\"ov\", OV)\n\tthis.keyword_factory.AddKeyword(\"nov\", NOV)\n\tthis.keyword_factory.AddKeyword(\"c\", C)\n\tthis.keyword_factory.AddKeyword(\"nc\", NC)\n\tthis.keyword_factory.AddKeyword(\"sz\", SZ)\n\tthis.keyword_factory.AddKeyword(\"snz\", SNZ)\n\tthis.keyword_factory.AddKeyword(\"spl\", SPL)\n\tthis.keyword_factory.AddKeyword(\"smi\", SMI)\n\tthis.keyword_factory.AddKeyword(\"so\", SO)\n\tthis.keyword_factory.AddKeyword(\"se\", SE)\n\tthis.keyword_factory.AddKeyword(\"nc5\", NC5)\n\tthis.keyword_factory.AddKeyword(\"nc6\", NC6)\n\tthis.keyword_factory.AddKeyword(\"nc7\", NC7)\n\tthis.keyword_factory.AddKeyword(\"nc8\", NC8)\n\tthis.keyword_factory.AddKeyword(\"nc9\", NC9)\n\tthis.keyword_factory.AddKeyword(\"nc10\", NC10)\n\tthis.keyword_factory.AddKeyword(\"nc11\", NC11)\n\tthis.keyword_factory.AddKeyword(\"nc12\", NC12)\n\tthis.keyword_factory.AddKeyword(\"nc13\", NC13)\n\tthis.keyword_factory.AddKeyword(\"nc14\", NC14)\n\tthis.keyword_factory.AddKeyword(\"max\", MAX)\n\tthis.keyword_factory.AddKeyword(\"nmax\", NMAX)\n\tthis.keyword_factory.AddKeyword(\"sh32\", SH32)\n\tthis.keyword_factory.AddKeyword(\"nsh32\", NSH32)\n\tthis.keyword_factory.AddKeyword(\"eq\", EQ)\n\tthis.keyword_factory.AddKeyword(\"neq\", NEQ)\n\tthis.keyword_factory.AddKeyword(\"ltu\", LTU)\n\tthis.keyword_factory.AddKeyword(\"leu\", LEU)\n\tthis.keyword_factory.AddKeyword(\"gtu\", GTU)\n\tthis.keyword_factory.AddKeyword(\"geu\", GEU)\n\tthis.keyword_factory.AddKeyword(\"lts\", LTS)\n\tthis.keyword_factory.AddKeyword(\"les\", LES)\n\tthis.keyword_factory.AddKeyword(\"gts\", GTS)\n\tthis.keyword_factory.AddKeyword(\"ges\", GES)\n\tthis.keyword_factory.AddKeyword(\"xz\", XZ)\n\tthis.keyword_factory.AddKeyword(\"xnz\", XNZ)\n\tthis.keyword_factory.AddKeyword(\"xleu\", XLEU)\n\tthis.keyword_factory.AddKeyword(\"xgtu\", XGTU)\n\tthis.keyword_factory.AddKeyword(\"xles\", XLES)\n\tthis.keyword_factory.AddKeyword(\"xgts\", XGTS)\n\tthis.keyword_factory.AddKeyword(\"small\", SMALL)\n\tthis.keyword_factory.AddKeyword(\"large\", LARGE)\n\n\tthis.keyword_factory.AddKeyword(\"!little\", LITTLE)\n\tthis.keyword_factory.AddKeyword(\"!big\", BIG)\n\n\tthis.keyword_factory.AddKeyword(\"zero\", ZERO_REG)\n\tthis.keyword_factory.AddKeyword(\"one\", ONE)\n\tthis.keyword_factory.AddKeyword(\"id\", ID)\n\tthis.keyword_factory.AddKeyword(\"id2\", ID2)\n\tthis.keyword_factory.AddKeyword(\"id4\", ID4)\n\tthis.keyword_factory.AddKeyword(\"id8\", ID8)\n\tthis.keyword_factory.AddKeyword(\"lneg\", LNEG)\n\tthis.keyword_factory.AddKeyword(\"mneg\", MNEG)\n\n\tthis.keyword_factory.AddKeyword(\".addrsig\", ADDRSIG)\n\tthis.keyword_factory.AddKeyword(\".addrsig_sym\", ADDRSIG_SYM)\n\tthis.keyword_factory.AddKeyword(\".ascii\", ASCII)\n\tthis.keyword_factory.AddKeyword(\".asciz\", ASCIZ)\n\tthis.keyword_factory.AddKeyword(\".byte\", BYTE)\n\tthis.keyword_factory.AddKeyword(\".cfi_def_cfa_offset\", CFI_DEF_CFA_OFFSET)\n\tthis.keyword_factory.AddKeyword(\".cfi_endproc\", CFI_ENDPROC)\n\tthis.keyword_factory.AddKeyword(\".cfi_offset\", CFI_OFFSET)\n\tthis.keyword_factory.AddKeyword(\".cfi_sections\", CFI_SECTIONS)\n\tthis.keyword_factory.AddKeyword(\".cfi_startproc\", CFI_STARTPROC)\n\tthis.keyword_factory.AddKeyword(\".globl\", GLOBL)\n\tthis.keyword_factory.AddKeyword(\".loc\", LOC)\n\tthis.keyword_factory.AddKeyword(\".long\", LONG)\n\tthis.keyword_factory.AddKeyword(\".p2align\", P2ALIGN)\n\tthis.keyword_factory.AddKeyword(\".quad\", QUAD)\n\tthis.keyword_factory.AddKeyword(\".set\", SET)\n\tthis.keyword_factory.AddKeyword(\".short\", SHORT)\n\tthis.keyword_factory.AddKeyword(\".size\", SIZE)\n\tthis.keyword_factory.AddKeyword(\".type\", TYPE)\n\tthis.keyword_factory.AddKeyword(\".weak\", WEAK)\n\tthis.keyword_factory.AddKeyword(\".zero\", ZERO_DIRECTIVE)\n\n\tthis.keyword_factory.AddKeyword(\"is_stmt\", IS_STMT)\n\tthis.keyword_factory.AddKeyword(\"prologue_end\", PROLOGUE_END)\n\n\tthis.keyword_factory.AddKeyword(\":\", COLON)\n\tthis.keyword_factory.AddKeyword(\",\", COMMA)\n\tthis.keyword_factory.AddKeyword(\"+\", PLUS)\n\tthis.keyword_factory.AddKeyword(\"-\", MINUS)\n}\n\nfunc (this *Tokenizer) InitRegexFactory() {\n\tthis.regex_factory = new(RegexFactory)\n\tthis.regex_factory.Init()\n\n\tthis.regex_factory.AddRegex(\"^(r)([0-9]*)$\", GP_REG)\n\tthis.regex_factory.AddRegex(\"^(d)([0-9]*)$\", PAIR_REG)\n\n\tthis.regex_factory.AddRegex(\"^([A-Za-z_.])([A-Za-z0-9_]*)$\", IDENTIFIER)\n\n\tthis.regex_factory.AddRegex(\"^([0-9]*)$\", POSITIVIE_NUMBER)\n\tthis.regex_factory.AddRegex(\"^(0x)([0-9]*)$\", HEX_NUMBER)\n\n\tthis.regex_factory.AddRegex(\"^(\\\")(.*)(\\\")$\", STRING)\n}\n\nfunc (this *Tokenizer) IsTokenizable(word string) bool {\n\treturn this.keyword_factory.IsTokenizable(word) || this.regex_factory.IsTokenizable(word)\n}\n\nfunc (this *Tokenizer) Tokenize(word string) *Token {\n\tif this.keyword_factory.IsTokenizable(word) {\n\t\treturn this.keyword_factory.Tokenize(word)\n\t} else if this.regex_factory.IsTokenizable(word) {\n\t\treturn this.regex_factory.Tokenize(word)\n\t} else {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/linker.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"os\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/device/core\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/logic\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Linker struct {\n\troot_dirpath string\n\tbin_dirpath  string\n\tbenchmark    string\n\n\tbenchmark_relocatable *kernel.Relocatable\n\tsdk_relocatables      map[string]*kernel.Relocatable\n\n\texecutable *kernel.Executable\n\n\tlinker_script *logic.LinkerScript\n}\n\nfunc (this *Linker) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.root_dirpath = command_line_parser.StringParameter(\"root_dirpath\")\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tthis.InitBenchmarkRelocatable()\n\tthis.InitSdkRelocatables()\n\n\tthis.executable = new(kernel.Executable)\n\tthis.executable.Init(this.benchmark)\n\n\tthis.linker_script = new(logic.LinkerScript)\n\tthis.linker_script.Init(command_line_parser)\n}\n\nfunc (this *Linker) InitBenchmarkRelocatable() {\n\tbenchmark_build_dirpath := filepath.Join(this.root_dirpath, \"benchmark\", \"build\")\n\n\tassembly_path := filepath.Join(\n\t\tbenchmark_build_dirpath,\n\t\tthis.benchmark,\n\t\t\"dpu\",\n\t\t\"CMakeFiles\",\n\t\tfmt.Sprintf(\"%s_device.dir\", this.benchmark),\n\t\t\"task.c.o\",\n\t)\n\n\tthis.benchmark_relocatable = new(kernel.Relocatable)\n\tthis.benchmark_relocatable.Init(this.benchmark)\n\tthis.benchmark_relocatable.SetPath(assembly_path)\n}\n\nfunc (this *Linker) InitSdkRelocatables() {\n\tthis.sdk_relocatables = make(map[string]*kernel.Relocatable)\n\n\tsdk_build_dirpath := filepath.Join(this.root_dirpath, \"sdk\", \"build\")\n\n\tsdk_build_dir_entries, sdk_build_dir_read_err := os.ReadDir(sdk_build_dirpath)\n\n\tif sdk_build_dir_read_err != nil {\n\t\tpanic(sdk_build_dir_read_err)\n\t}\n\n\tfor _, sdk_build_dir_entry := range sdk_build_dir_entries {\n\t\tif sdk_build_dir_entry.IsDir() && sdk_build_dir_entry.Name() != \"CMakeFiles\" {\n\t\t\tsdk_lib_dirpath := filepath.Join(\n\t\t\t\tsdk_build_dirpath,\n\t\t\t\tsdk_build_dir_entry.Name(),\n\t\t\t\t\"CMakeFiles\",\n\t\t\t\tsdk_build_dir_entry.Name()+\".dir\",\n\t\t\t)\n\n\t\t\tsdk_lib_dir_entries, sdk_lib_dir_read_err := os.ReadDir(sdk_lib_dirpath)\n\n\t\t\tif sdk_lib_dir_read_err != nil {\n\t\t\t\tpanic(sdk_lib_dir_read_err)\n\t\t\t}\n\n\t\t\tfor _, sdk_lib_dir_entry := range sdk_lib_dir_entries {\n\t\t\t\tassembly_path := filepath.Join(sdk_lib_dirpath, sdk_lib_dir_entry.Name())\n\n\t\t\t\tlib_dir_name := filepath.Base(sdk_lib_dirpath)\n\t\t\t\tsdk_relocatable_name := lib_dir_name[:len(lib_dir_name)-4] + \".\" + sdk_lib_dir_entry.Name()[:len(sdk_lib_dir_entry.Name())-4]\n\n\t\t\t\tsdk_relocatable := new(kernel.Relocatable)\n\t\t\t\tsdk_relocatable.Init(sdk_relocatable_name)\n\t\t\t\tsdk_relocatable.SetPath(assembly_path)\n\n\t\t\t\tthis.sdk_relocatables[sdk_relocatable_name] = sdk_relocatable\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Linker) Link() {\n\tthis.Lex()\n\tthis.Parse()\n\tthis.AnalyzeLiveness()\n\tthis.MakeExecutable()\n\tthis.LoadExecutable()\n\tthis.DumpExecutable()\n}\n\nfunc (this *Linker) Lex() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init()\n\n\tbenchmark_lex_job := new(LexJob)\n\tbenchmark_lex_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_lex_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_lex_job := new(LexJob)\n\t\tsdk_lex_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_lex_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) Parse() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init()\n\n\tbenchmark_parse_job := new(ParseJob)\n\tbenchmark_parse_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_parse_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_parse_job := new(ParseJob)\n\t\tsdk_parse_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_parse_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) AnalyzeLiveness() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init()\n\n\tbenchmark_analyze_liveness_job := new(AnalyzeLivenessJob)\n\tbenchmark_analyze_liveness_job.Init(this.benchmark_relocatable)\n\n\tthread_pool.Enque(benchmark_analyze_liveness_job)\n\n\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\tsdk_analyze_liveness_job := new(AnalyzeLivenessJob)\n\t\tsdk_analyze_liveness_job.Init(sdk_relocatable)\n\n\t\tthread_pool.Enque(sdk_analyze_liveness_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *Linker) MakeExecutable() {\n\tfmt.Printf(\"Resolving symbols of %s...\\n\", this.executable.Name())\n\n\tthis.executable.SetBenchmarkRelocatable(this.benchmark_relocatable)\n\tthis.ResolveSymbols()\n\n\texecutable_path := filepath.Join(this.bin_dirpath, \"main.S\")\n\n\tfmt.Printf(\"Dumping the executable to %s...\\n\", this.executable.Path())\n\n\tthis.executable.SetPath(executable_path)\n\tthis.executable.DumpAssembly()\n}\n\nfunc (this *Linker) HasResolved() bool {\n\tfor unresolved_symbol, _ := range this.executable.Liveness().UnresolvedSymbols() {\n\t\tif !this.linker_script.HasLinkerConstant(unresolved_symbol) {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *Linker) ResolveSymbols() {\n\tthis.executable.AddSdkRelocatable(this.sdk_relocatables[\"misc.crt0\"])\n\n\tfor !this.HasResolved() {\n\t\tfor unresolved_symbol, _ := range this.executable.Liveness().UnresolvedSymbols() {\n\t\t\tif !this.linker_script.HasLinkerConstant(unresolved_symbol) {\n\t\t\t\tfor _, sdk_relocatable := range this.sdk_relocatables {\n\t\t\t\t\tif _, found := sdk_relocatable.Liveness().GlobalSymbols()[unresolved_symbol]; found {\n\t\t\t\t\t\tthis.executable.AddSdkRelocatable(sdk_relocatable)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *Linker) LoadExecutable() {\n\tfmt.Println(\"Re-lexing executable\")\n\tlexer_ := new(lexer.Lexer)\n\tlexer_.Init()\n\ttoken_stream := lexer_.Lex(this.executable.Path())\n\tthis.executable.SetTokenStream(token_stream)\n\n\tfmt.Println(\"Re-parsing executable...\")\n\tparser_ := new(parser.Parser)\n\tparser_.Init()\n\tast := parser_.Parse(token_stream)\n\tthis.executable.SetAst(ast)\n\n\tfmt.Println(\"Assigning labels...\")\n\tlabel_assigner := new(logic.LabelAssigner)\n\tlabel_assigner.Init()\n\tlabel_assigner.Assign(this.executable)\n\n\tfmt.Println(\"Assigning addresses..\")\n\tthis.linker_script.Assign(this.executable)\n\n\tfmt.Println(\"Setting alias labels...\")\n\tset_assigner := new(logic.SetAssigner)\n\tset_assigner.Init()\n\tset_assigner.Assign(this.executable)\n\n\tfmt.Println(\"Assigning instructions...\")\n\tinstruction_assigner := new(logic.InstructionAssigner)\n\tinstruction_assigner.Init(this.linker_script)\n\tinstruction_assigner.Assign(this.executable)\n}\n\nfunc (this *Linker) DumpExecutable() {\n\tthis.linker_script.DumpValues(filepath.Join(this.bin_dirpath, \"values.txt\"))\n\tthis.executable.DumpAddresses(filepath.Join(this.bin_dirpath, \"addresses.txt\"))\n\tthis.executable.DumpAtomic(filepath.Join(this.bin_dirpath, \"atomic.bin\"))\n\tthis.executable.DumpIram(filepath.Join(this.bin_dirpath, \"iram.bin\"))\n\tthis.executable.DumpWram(filepath.Join(this.bin_dirpath, \"wram.bin\"))\n\tthis.executable.DumpMram(filepath.Join(this.bin_dirpath, \"mram.bin\"))\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/instruction_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/kernel/directive\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype InstructionAssigner struct {\n\texecutable    *kernel.Executable\n\twalker        *parser.Walker\n\tlinker_script *LinkerScript\n}\n\nfunc (this *InstructionAssigner) Init(linker_script *LinkerScript) {\n\tthis.linker_script = linker_script\n\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(stmt.ASCII, this.WalkAsciiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ASCIZ, this.WalkAscizStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BYTE, this.WalkByteStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_PROGRAM_COUNTER, this.WalkLongProgramCounterStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_SECTION_NAME, this.WalkLongSectionNameStmt)\n\tthis.walker.RegisterStmtCallback(stmt.QUAD, this.WalkQuadStmt)\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SHORT, this.WalkShortStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_DOUBLE_NUMBER, this.WalkZeroDoubleNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_SINGLE_NUMBER, this.WalkZeroSingleNumberStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.CI, this.WalkCiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DMA_RRI, this.WalkDmaRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DRDICI, this.WalkDrdiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.EDRI, this.WalkEdriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERID, this.WalkEridStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERII, this.WalkEriiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERIR, this.WalkErirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERRI, this.WalkErriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.I, this.WalkIStmt)\n\tthis.walker.RegisterStmtCallback(stmt.NOP, this.WalkNopStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RCI, this.WalkRciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RICI, this.WalkRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRCI, this.WalkRirciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRC, this.WalkRircStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIR, this.WalkRirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRCI, this.WalkRrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRC, this.WalkRrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRICI, this.WalkRriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRIC, this.WalkRricStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRI, this.WalkRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRCI, this.WalkRrrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRC, this.WalkRrrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRICI, this.WalkRrriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRI, this.WalkRrriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRR, this.WalkRrrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RR, this.WalkRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.R, this.WalkRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.S_ERRI, this.WalkSErriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RCI, this.WalkSRciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRCI, this.WalkSRirciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRC, this.WalkSRircStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRCI, this.WalkSRrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRC, this.WalkSRrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRICI, this.WalkSRriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRIC, this.WalkSRricStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRI, this.WalkSRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRCI, this.WalkSRrrciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRC, this.WalkSRrrcStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRICI, this.WalkSRrriciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRI, this.WalkSRrriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRR, this.WalkSRrrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RR, this.WalkSRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_R, this.WalkSRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.BKP, this.WalkBkpStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BOOT_RI, this.WalkBootRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RI, this.WalkCallRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RR, this.WalkCallRrStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DIV_STEP_DRDI, this.WalkDivStepDrdiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RII, this.WalkJeqRiiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RRI, this.WalkJeqRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JNZ_RI, this.WalkJnzRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_I, this.WalkJumpIStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_R, this.WalkJumpRStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_RRI, this.WalkLbsRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_S_RRI, this.WalkLbsSRriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LD_DRI, this.WalkLdDriStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVD_DD, this.WalkMovdDdStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RICI, this.WalkMoveRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RI, this.WalkMoveRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RICI, this.WalkMoveSRiciStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RI, this.WalkMoveSRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RII, this.WalkSbIdRiiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RI, this.WalkSbIdRiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_RIR, this.WalkSbRirStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SD_RID, this.WalkSdRidStmt)\n\tthis.walker.RegisterStmtCallback(stmt.STOP, this.WalkStopStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TIME_CFG_R, this.WalkTimeCfgRStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *InstructionAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *InstructionAssigner) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tascii_stmt := stmt_.AsciiStmt()\n\ttoken := ascii_stmt.Token()\n\tattribute := token.Attribute()\n\tcharacters := attribute[1 : len(attribute)-1]\n\n\t// TODO(bongjoon.hyun@gmail.com): decode octal code\n\n\tascii_directive := new(directive.AsciiDirective)\n\tascii_directive.Init(characters)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(ascii_directive)\n}\n\nfunc (this *InstructionAssigner) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tasciz_stmt := stmt_.AscizStmt()\n\ttoken := asciz_stmt.Token()\n\tattribute := token.Attribute()\n\tcharacters := attribute[1 : len(attribute)-1]\n\n\tasciz_directive := new(directive.AscizDirective)\n\tasciz_directive.Init(characters)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(asciz_directive)\n}\n\nfunc (this *InstructionAssigner) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tbyte_stmt := stmt_.ByteStmt()\n\n\tvalue := this.EvaluateProgramCounter(byte_stmt.Expr())\n\n\tbyte_directive := new(directive.ByteDirective)\n\tbyte_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(byte_directive)\n}\n\nfunc (this *InstructionAssigner) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tlong_program_counter_stmt := stmt_.LongProgramCounterStmt()\n\n\tvalue := this.EvaluateProgramCounter(long_program_counter_stmt.Expr())\n\n\tlong_directive := new(directive.LongDirective)\n\tlong_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(long_directive)\n}\n\nfunc (this *InstructionAssigner) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tlong_section_name_stmt := stmt_.LongSectionNameStmt()\n\n\tvalue := this.EvaluateSectionName(long_section_name_stmt.Expr())\n\n\tlong_directive := new(directive.LongDirective)\n\tlong_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(long_directive)\n}\n\nfunc (this *InstructionAssigner) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tquad_stmt := stmt_.QuadStmt()\n\n\tvalue := this.EvaluateProgramCounter(quad_stmt.Expr())\n\n\tquad_directive := new(directive.QuadDirective)\n\tquad_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(quad_directive)\n}\n\nfunc (this *InstructionAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tshort_stmt := stmt_.ShortStmt()\n\n\tvalue := this.EvaluateProgramCounter(short_stmt.Expr())\n\n\tshort_directive := new(directive.ShortDirective)\n\tshort_directive.Init(value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(short_directive)\n}\n\nfunc (this *InstructionAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *InstructionAssigner) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\tsize := this.EvaluateProgramCounter(zero_double_number_stmt.Expr1())\n\tvalue := this.EvaluateProgramCounter(zero_double_number_stmt.Expr2())\n\n\tzero_directive := new(directive.ZeroDirective)\n\tzero_directive.Init(size, value)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(zero_directive)\n}\n\nfunc (this *InstructionAssigner) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\tsize := this.EvaluateProgramCounter(zero_single_number_stmt.Expr())\n\n\tzero_directive := new(directive.ZeroDirective)\n\tzero_directive.Init(size, 0)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(zero_directive)\n}\n\nfunc (this *InstructionAssigner) WalkCiStmt(stmt_ *stmt.Stmt) {\n\tci_stmt := stmt_.CiStmt()\n\n\top_code := this.ConvertCiOpCode(ci_stmt.OpCode())\n\tcondition := this.ConvertCondition(ci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(ci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitCi(op_code, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDdciStmt(stmt_ *stmt.Stmt) {\n\tddci_stmt := stmt_.DdciStmt()\n\n\top_code := this.ConvertDdciOpCode(ddci_stmt.OpCode())\n\tdc := this.ConvertPairReg(ddci_stmt.Dc())\n\tdb := this.ConvertPairReg(ddci_stmt.Db())\n\tcondition := this.ConvertCondition(ddci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(ddci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDdci(op_code, dc, db, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDmaRriStmt(stmt_ *stmt.Stmt) {\n\tdma_rri_stmt := stmt_.DmaRriStmt()\n\n\top_code := this.ConvertDmaRriOpCode(dma_rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(dma_rri_stmt.Ra())\n\trb := this.ConvertSrcReg(dma_rri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(dma_rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDmaRri(op_code, ra, rb, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDrdiciStmt(stmt_ *stmt.Stmt) {\n\tdrdici_stmt := stmt_.DrdiciStmt()\n\n\top_code := this.ConvertDrdiciOpCode(drdici_stmt.OpCode())\n\tdc := this.ConvertPairReg(drdici_stmt.Dc())\n\tra := this.ConvertSrcReg(drdici_stmt.Ra())\n\tdb := this.ConvertPairReg(drdici_stmt.Db())\n\timm := this.EvaluateProgramCounter(drdici_stmt.Imm())\n\tcondition := this.ConvertCondition(drdici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(drdici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDrdici(op_code, dc, ra, db, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEdriStmt(stmt_ *stmt.Stmt) {\n\tedri_stmt := stmt_.EdriStmt()\n\n\top_code := this.ConvertLoadOpCode(edri_stmt.OpCode())\n\tendian := this.ConvertEndian(edri_stmt.Endian())\n\tdc := this.ConvertPairReg(edri_stmt.Dc())\n\tra := this.ConvertSrcReg(edri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(edri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitEdri(op_code, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEridStmt(stmt_ *stmt.Stmt) {\n\terid_stmt := stmt_.EridStmt()\n\n\top_code := this.ConvertStoreOpCode(erid_stmt.OpCode())\n\tendian := this.ConvertEndian(erid_stmt.Endian())\n\tra := this.ConvertSrcReg(erid_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erid_stmt.Off())\n\tdb := this.ConvertPairReg(erid_stmt.Db())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErid(op_code, endian, ra, off, db)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkEriiStmt(stmt_ *stmt.Stmt) {\n\terii_stmt := stmt_.EriiStmt()\n\n\top_code := this.ConvertStoreOpCode(erii_stmt.OpCode())\n\tendian := this.ConvertEndian(erii_stmt.Endian())\n\tra := this.ConvertSrcReg(erii_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erii_stmt.Off())\n\timm := this.EvaluateProgramCounter(erii_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkErirStmt(stmt_ *stmt.Stmt) {\n\terir_stmt := stmt_.ErirStmt()\n\n\top_code := this.ConvertStoreOpCode(erir_stmt.OpCode())\n\tendian := this.ConvertEndian(erir_stmt.Endian())\n\tra := this.ConvertSrcReg(erir_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erir_stmt.Off())\n\trb := this.ConvertSrcReg(erir_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErir(op_code, endian, ra, off, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkErriStmt(stmt_ *stmt.Stmt) {\n\terri_stmt := stmt_.ErriStmt()\n\n\top_code := this.ConvertLoadOpCode(erri_stmt.OpCode())\n\tendian := this.ConvertEndian(erri_stmt.Endian())\n\trc := this.ConvertGpReg(erri_stmt.Rc())\n\tra := this.ConvertSrcReg(erri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(erri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErri(op_code, endian, rc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkIStmt(stmt_ *stmt.Stmt) {\n\ti_stmt := stmt_.IStmt()\n\n\top_code := this.ConvertIOpCode(i_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(i_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitI(op_code, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkNopStmt(stmt_ *stmt.Stmt) {\n\tnop_stmt := stmt_.NopStmt()\n\n\top_code := this.ConvertROpCode(nop_stmt.OpCode())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZ(op_code)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRciStmt(stmt_ *stmt.Stmt) {\n\trci_stmt := stmt_.RciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rci_stmt.Rc())\n\n\top_code := this.ConvertROpCode(rci_stmt.OpCode())\n\tcondition := this.ConvertCondition(rci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rci_stmt.Rc())\n\n\t\tinstruction_.InitRci(op_code, rc, condition, pc)\n\t} else {\n\t\tinstruction_.InitZci(op_code, condition, pc)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRiciStmt(stmt_ *stmt.Stmt) {\n\trici_stmt := stmt_.RiciStmt()\n\n\top_code := this.ConvertRiciOpCode(rici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rici_stmt.Imm())\n\tcondition := this.ConvertCondition(rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRirciStmt(stmt_ *stmt.Stmt) {\n\trirci_stmt := stmt_.RirciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rirci_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rirci_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rirci_stmt.Imm())\n\tra := this.ConvertSrcReg(rirci_stmt.Ra())\n\tcondition := this.ConvertCondition(rirci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rirci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rirci_stmt.Rc())\n\n\t\tinstruction_.InitRirci(op_code, rc, imm, ra, condition, pc)\n\t} else {\n\t\tinstruction_.InitZirci(op_code, imm, ra, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRircStmt(stmt_ *stmt.Stmt) {\n\trirc_stmt := stmt_.RircStmt()\n\n\tis_zero_reg := this.IsZeroReg(rirc_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rirc_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rirc_stmt.Imm())\n\tra := this.ConvertSrcReg(rirc_stmt.Ra())\n\tcondition := this.ConvertCondition(rirc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rirc_stmt.Rc())\n\n\t\tinstruction_.InitRirc(op_code, rc, imm, ra, condition)\n\t} else {\n\t\tinstruction_.InitZirc(op_code, imm, ra, condition)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRirStmt(stmt_ *stmt.Stmt) {\n\trir_stmt := stmt_.RirStmt()\n\n\tis_zero_reg := this.IsZeroReg(rir_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rir_stmt.OpCode())\n\timm := this.EvaluateProgramCounter(rir_stmt.Imm())\n\tra := this.ConvertSrcReg(rir_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rir_stmt.Rc())\n\n\t\tinstruction_.InitRir(op_code, rc, imm, ra)\n\t} else {\n\t\tinstruction_.InitZir(op_code, imm, ra)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrciStmt(stmt_ *stmt.Stmt) {\n\trrci_stmt := stmt_.RrciStmt()\n\n\top_code := this.ConvertRrOpCode(rrci_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrci_stmt.Ra())\n\tcondition := this.ConvertCondition(rrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t} else if op_code == instruction.SUB {\n\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRirci(op_code, rc, imm, ra, condition, pc)\n\t} else if op_code == instruction.XOR {\n\t\tis_zero_reg := this.IsZeroReg(rrci_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t\t} else {\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t\t}\n\t} else {\n\t\tis_zero_reg := this.IsZeroReg(rrci_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rrci_stmt.Rc())\n\n\t\t\tinstruction_.InitRrci(op_code, rc, ra, condition, pc)\n\t\t} else {\n\t\t\tinstruction_.InitZrci(op_code, ra, condition, pc)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrcStmt(stmt_ *stmt.Stmt) {\n\trrc_stmt := stmt_.RrcStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrc_stmt.Rc())\n\n\top_code := this.ConvertRrOpCode(rrc_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrc_stmt.Ra())\n\tcondition := this.ConvertCondition(rrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrc_stmt.Rc())\n\n\t\tinstruction_.InitRrc(op_code, rc, ra, condition)\n\t} else {\n\t\tinstruction_.InitZrc(op_code, ra, condition)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRriciStmt(stmt_ *stmt.Stmt) {\n\trrici_stmt := stmt_.RriciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrici_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rrici_stmt.Imm())\n\tcondition := this.ConvertCondition(rrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrici_stmt.Rc())\n\n\t\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRricStmt(stmt_ *stmt.Stmt) {\n\trric_stmt := stmt_.RricStmt()\n\n\tis_zero_reg := this.IsZeroReg(rric_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rric_stmt.OpCode())\n\tra := this.ConvertSrcReg(rric_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rric_stmt.Imm())\n\tcondition := this.ConvertCondition(rric_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rric_stmt.Rc())\n\n\t\tif condition != cc.FALSE {\n\t\t\tinstruction_.InitRric(op_code, rc, ra, imm, condition)\n\t\t} else {\n\t\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t\t}\n\t} else {\n\t\tif condition != cc.FALSE {\n\t\t\tinstruction_.InitZric(op_code, ra, imm, condition)\n\t\t} else {\n\t\t\tinstruction_.InitZrif(op_code, ra, imm, condition)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRriStmt(stmt_ *stmt.Stmt) {\n\trri_stmt := stmt_.RriStmt()\n\n\tis_zero_reg := this.IsZeroReg(rri_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(rri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.ANDN || op_code == instruction.NAND || op_code == instruction.NOR ||\n\t\top_code == instruction.NXOR ||\n\t\top_code == instruction.ORN {\n\t\trc := this.ConvertGpReg(rri_stmt.Rc())\n\t\tcondition := cc.FALSE\n\n\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t} else if !is_zero_reg {\n\t\trc := this.ConvertGpReg(rri_stmt.Rc())\n\n\t\tinstruction_.InitRri(op_code, rc, ra, imm)\n\t} else {\n\t\tinstruction_.InitZri(op_code, ra, imm)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrciStmt(stmt_ *stmt.Stmt) {\n\trrrci_stmt := stmt_.RrrciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrci_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrrci_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrci_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrci_stmt.Rb())\n\tcondition := this.ConvertCondition(rrrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrci_stmt.Rc())\n\n\t\tinstruction_.InitRrrci(op_code, rc, ra, rb, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrrci(op_code, ra, rb, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrcStmt(stmt_ *stmt.Stmt) {\n\trrrc_stmt := stmt_.RrrcStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrc_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrrc_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrc_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrc_stmt.Rb())\n\tcondition := this.ConvertCondition(rrrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrc_stmt.Rc())\n\n\t\tinstruction_.InitRrrc(op_code, rc, ra, rb, condition)\n\t} else {\n\t\tinstruction_.InitZrrc(op_code, ra, rb, condition)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrriciStmt(stmt_ *stmt.Stmt) {\n\trrrici_stmt := stmt_.RrriciStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrrici_stmt.Rc())\n\n\top_code := this.ConvertRrriOpCode(rrrici_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrrici_stmt.Ra())\n\trb := this.ConvertSrcReg(rrrici_stmt.Rb())\n\timm := this.EvaluateProgramCounter(rrrici_stmt.Imm())\n\tcondition := this.ConvertCondition(rrrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(rrrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrrici_stmt.Rc())\n\n\t\tinstruction_.InitRrrici(op_code, rc, ra, rb, imm, condition, pc)\n\t} else {\n\t\tinstruction_.InitZrrici(op_code, ra, rb, imm, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrriStmt(stmt_ *stmt.Stmt) {\n\trrri_stmt := stmt_.RrriStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrri_stmt.Rc())\n\n\top_code := this.ConvertRrriOpCode(rrri_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrri_stmt.Ra())\n\trb := this.ConvertSrcReg(rrri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(rrri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrri_stmt.Rc())\n\n\t\tinstruction_.InitRrri(op_code, rc, ra, rb, imm)\n\t} else {\n\t\tinstruction_.InitZrri(op_code, ra, rb, imm)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrrStmt(stmt_ *stmt.Stmt) {\n\trrr_stmt := stmt_.RrrStmt()\n\n\tis_zero_reg := this.IsZeroReg(rrr_stmt.Rc())\n\n\top_code := this.ConvertRriOpCode(rrr_stmt.OpCode())\n\tra := this.ConvertSrcReg(rrr_stmt.Ra())\n\trb := this.ConvertSrcReg(rrr_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(rrr_stmt.Rc())\n\n\t\tinstruction_.InitRrr(op_code, rc, ra, rb)\n\t} else {\n\t\tinstruction_.InitZrr(op_code, ra, rb)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRrStmt(stmt_ *stmt.Stmt) {\n\trr_stmt := stmt_.RrStmt()\n\n\top_code := this.ConvertRrOpCode(rr_stmt.OpCode())\n\tra := this.ConvertSrcReg(rr_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\timm := int64(0)\n\t\tcondition := cc.FALSE\n\n\t\tinstruction_.InitRrif(op_code, rc, ra, imm, condition)\n\t} else if op_code == instruction.SUB {\n\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\timm := int64(0)\n\n\t\tinstruction_.InitRir(op_code, rc, imm, ra)\n\t} else if op_code == instruction.XOR {\n\t\tis_zero_reg := this.IsZeroReg(rr_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitRri(op_code, rc, ra, imm)\n\t\t} else {\n\t\t\timm := int64(-1)\n\n\t\t\tinstruction_.InitZri(op_code, ra, imm)\n\t\t}\n\t} else {\n\t\tis_zero_reg := this.IsZeroReg(rr_stmt.Rc())\n\n\t\tif !is_zero_reg {\n\t\t\trc := this.ConvertGpReg(rr_stmt.Rc())\n\n\t\t\tinstruction_.InitRr(op_code, rc, ra)\n\t\t} else {\n\t\t\tinstruction_.InitZr(op_code, ra)\n\t\t}\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkRStmt(stmt_ *stmt.Stmt) {\n\tr_stmt := stmt_.RStmt()\n\n\tis_zero_reg := this.IsZeroReg(r_stmt.Rc())\n\n\top_code := this.ConvertROpCode(r_stmt.OpCode())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif !is_zero_reg {\n\t\trc := this.ConvertGpReg(r_stmt.Rc())\n\n\t\tinstruction_.InitR(op_code, rc)\n\t} else {\n\t\tinstruction_.InitZ(op_code)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSErriStmt(stmt_ *stmt.Stmt) {\n\ts_erri_stmt := stmt_.SErriStmt()\n\n\top_code := this.ConvertLoadOpCode(s_erri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_erri_stmt.Suffix(), instruction.ERRI)\n\tendian := this.ConvertEndian(s_erri_stmt.Endian())\n\tdc := this.ConvertPairReg(s_erri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_erri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(s_erri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSErri(op_code, suffix, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRciStmt(stmt_ *stmt.Stmt) {\n\ts_rci_stmt := stmt_.SRciStmt()\n\n\top_code := this.ConvertROpCode(s_rci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rci_stmt.Suffix(), instruction.RCI)\n\tdc := this.ConvertPairReg(s_rci_stmt.Dc())\n\tcondition := this.ConvertCondition(s_rci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRci(op_code, suffix, dc, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRirciStmt(stmt_ *stmt.Stmt) {\n\ts_rirci_stmt := stmt_.SRirciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rirci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rirci_stmt.Suffix(), instruction.RIRCI)\n\tdc := this.ConvertPairReg(s_rirci_stmt.Dc())\n\timm := this.EvaluateProgramCounter(s_rirci_stmt.Imm())\n\tra := this.ConvertSrcReg(s_rirci_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rirci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rirci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRirci(op_code, suffix, dc, imm, ra, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRircStmt(stmt_ *stmt.Stmt) {\n\ts_rirc_stmt := stmt_.SRircStmt()\n\n\top_code := this.ConvertRriOpCode(s_rirc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rirc_stmt.Suffix(), instruction.RIRC)\n\tdc := this.ConvertPairReg(s_rirc_stmt.Dc())\n\timm := this.EvaluateProgramCounter(s_rirc_stmt.Imm())\n\tra := this.ConvertSrcReg(s_rirc_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rirc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRirc(op_code, suffix, dc, imm, ra, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrciStmt(stmt_ *stmt.Stmt) {\n\ts_rrci_stmt := stmt_.SRrciStmt()\n\n\top_code := this.ConvertRrOpCode(s_rrci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrci_stmt.Suffix(), instruction.RRCI)\n\tdc := this.ConvertPairReg(s_rrci_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrci_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\tif suffix == instruction.S_RRCI {\n\t\t\tsuffix = instruction.S_RRICI\n\t\t\timm := int64(0)\n\n\t\t\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\t\t} else {\n\t\t\tsuffix = instruction.U_RRICI\n\t\t\timm := int64(0)\n\n\t\t\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\t\t}\n\t} else {\n\t\tinstruction_.InitSRrci(op_code, suffix, dc, ra, condition, pc)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrcStmt(stmt_ *stmt.Stmt) {\n\ts_rrc_stmt := stmt_.SRrcStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrc_stmt.Suffix(), instruction.RRC)\n\tdc := this.ConvertPairReg(s_rrc_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrc_stmt.Ra())\n\tcondition := this.ConvertCondition(s_rrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrc(op_code, suffix, dc, ra, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRriciStmt(stmt_ *stmt.Stmt) {\n\ts_rrici_stmt := stmt_.SRriciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrici_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrici_stmt.Suffix(), instruction.RRICI)\n\tdc := this.ConvertPairReg(s_rrici_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrici_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rrici_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRricStmt(stmt_ *stmt.Stmt) {\n\ts_rric_stmt := stmt_.SRricStmt()\n\n\top_code := this.ConvertRriOpCode(s_rric_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rric_stmt.Suffix(), instruction.RRIC)\n\tdc := this.ConvertPairReg(s_rric_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rric_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rric_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rric_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif condition != cc.FALSE {\n\t\tinstruction_.InitSRric(op_code, suffix, dc, ra, imm, condition)\n\t} else {\n\t\tinstruction_.InitSRrif(op_code, suffix, dc, ra, imm, condition)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRriStmt(stmt_ *stmt.Stmt) {\n\ts_rri_stmt := stmt_.SRriStmt()\n\n\top_code := this.ConvertRriOpCode(s_rri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rri_stmt.Suffix(), instruction.RRI)\n\tdc := this.ConvertPairReg(s_rri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(s_rri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRri(op_code, suffix, dc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrciStmt(stmt_ *stmt.Stmt) {\n\ts_rrrci_stmt := stmt_.SRrrciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrci_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrci_stmt.Suffix(), instruction.RRRCI)\n\tdc := this.ConvertPairReg(s_rrrci_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrci_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrci_stmt.Rb())\n\tcondition := this.ConvertCondition(s_rrrci_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrrci_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrci(op_code, suffix, dc, ra, rb, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrcStmt(stmt_ *stmt.Stmt) {\n\ts_rrrc_stmt := stmt_.SRrrcStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrc_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrc_stmt.Suffix(), instruction.RRRC)\n\tdc := this.ConvertPairReg(s_rrrc_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrc_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrc_stmt.Rb())\n\tcondition := this.ConvertCondition(s_rrrc_stmt.Condition())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrc(op_code, suffix, dc, ra, rb, condition)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrriciStmt(stmt_ *stmt.Stmt) {\n\ts_rrrici_stmt := stmt_.SRrriciStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrrici_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrrici_stmt.Suffix(), instruction.RRRICI)\n\tdc := this.ConvertPairReg(s_rrrici_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrrici_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrrici_stmt.Rb())\n\timm := this.EvaluateProgramCounter(s_rrrici_stmt.Imm())\n\tcondition := this.ConvertCondition(s_rrrici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(s_rrrici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrrici(op_code, suffix, dc, ra, rb, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrriStmt(stmt_ *stmt.Stmt) {\n\ts_rrri_stmt := stmt_.SRrriStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrri_stmt.Suffix(), instruction.RRRI)\n\tdc := this.ConvertPairReg(s_rrri_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrri_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrri_stmt.Rb())\n\timm := this.EvaluateProgramCounter(s_rrri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrri(op_code, suffix, dc, ra, rb, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrrStmt(stmt_ *stmt.Stmt) {\n\ts_rrr_stmt := stmt_.SRrrStmt()\n\n\top_code := this.ConvertRriOpCode(s_rrr_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rrr_stmt.Suffix(), instruction.RRR)\n\tdc := this.ConvertPairReg(s_rrr_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rrr_stmt.Ra())\n\trb := this.ConvertSrcReg(s_rrr_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrr(op_code, suffix, dc, ra, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRrStmt(stmt_ *stmt.Stmt) {\n\ts_rr_stmt := stmt_.SRrStmt()\n\n\top_code := this.ConvertRrOpCode(s_rr_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_rr_stmt.Suffix(), instruction.RR)\n\tdc := this.ConvertPairReg(s_rr_stmt.Dc())\n\tra := this.ConvertSrcReg(s_rr_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.OR {\n\t\tif suffix == instruction.S_RR {\n\t\t\timm := int64(0)\n\t\t\tcondition := cc.FALSE\n\n\t\t\tinstruction_.InitSRrif(op_code, instruction.S_RRIF, dc, ra, imm, condition)\n\t\t} else if suffix == instruction.U_RR {\n\t\t\timm := int64(0)\n\t\t\tcondition := cc.FALSE\n\n\t\t\tinstruction_.InitSRrif(op_code, instruction.U_RRIF, dc, ra, imm, condition)\n\t\t} else {\n\t\t\terr := errors.New(\"suffix is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\tinstruction_.InitSRr(op_code, suffix, dc, ra)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSRStmt(stmt_ *stmt.Stmt) {\n\ts_r_stmt := stmt_.SRStmt()\n\n\top_code := this.ConvertRriOpCode(s_r_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(s_r_stmt.Suffix(), instruction.R)\n\tdc := this.ConvertPairReg(s_r_stmt.Dc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSR(op_code, suffix, dc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkBkpStmt(stmt_ *stmt.Stmt) {\n\top_code := instruction.FAULT\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitI(op_code, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkBootRiStmt(stmt_ *stmt.Stmt) {\n\tboot_ri_stmt := stmt_.BootRiStmt()\n\n\top_code := this.ConvertRiciOpCode(boot_ri_stmt.OpCode())\n\tra := this.ConvertSrcReg(boot_ri_stmt.Ra())\n\timm := this.EvaluateProgramCounter(boot_ri_stmt.Imm())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkCallRiStmt(stmt_ *stmt.Stmt) {\n\tcall_ri_stmt := stmt_.CallRiStmt()\n\n\top_code := instruction.CALL\n\trc := this.ConvertGpReg(call_ri_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(call_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkCallRrStmt(stmt_ *stmt.Stmt) {\n\tcall_rr_stmt := stmt_.CallRrStmt()\n\n\top_code := instruction.CALL\n\trc := this.ConvertGpReg(call_rr_stmt.Rc())\n\tra := this.ConvertSrcReg(call_rr_stmt.Ra())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkDivStepDrdiStmt(stmt_ *stmt.Stmt) {\n\tdiv_step_drdi_stmt := stmt_.DivStepDrdiStmt()\n\n\top_code := this.ConvertDrdiciOpCode(div_step_drdi_stmt.OpCode())\n\tdc := this.ConvertPairReg(div_step_drdi_stmt.Dc())\n\tra := this.ConvertSrcReg(div_step_drdi_stmt.Ra())\n\tdb := this.ConvertPairReg(div_step_drdi_stmt.Db())\n\timm := this.EvaluateProgramCounter(div_step_drdi_stmt.Imm())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDrdici(op_code, dc, ra, db, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJeqRiiStmt(stmt_ *stmt.Stmt) {\n\tjeq_rii_stmt := stmt_.JeqRiiStmt()\n\n\top_code := this.ConvertJumpOpCode(jeq_rii_stmt.OpCode())\n\tra := this.ConvertSrcReg(jeq_rii_stmt.Ra())\n\timm := this.EvaluateProgramCounter(jeq_rii_stmt.Imm())\n\tcondition := this.ConvertJumpCondition(jeq_rii_stmt.OpCode())\n\tpc := this.EvaluateProgramCounter(jeq_rii_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJeqRriStmt(stmt_ *stmt.Stmt) {\n\tjeq_rri_stmt := stmt_.JeqRriStmt()\n\n\top_code := this.ConvertJumpOpCode(jeq_rri_stmt.OpCode())\n\tra := this.ConvertSrcReg(jeq_rri_stmt.Ra())\n\trb := this.ConvertSrcReg(jeq_rri_stmt.Rb())\n\tcondition := this.ConvertJumpCondition(jeq_rri_stmt.OpCode())\n\tpc := this.EvaluateProgramCounter(jeq_rri_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZrrci(op_code, ra, rb, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJnzRiStmt(stmt_ *stmt.Stmt) {\n\tjnz_ri_stmt := stmt_.JnzRiStmt()\n\n\top_code := this.ConvertJumpOpCode(jnz_ri_stmt.OpCode())\n\tra := this.ConvertSrcReg(jnz_ri_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tif op_code == instruction.SUB {\n\t\timm := int64(0)\n\t\tcondition := this.ConvertJumpCondition(jnz_ri_stmt.OpCode())\n\t\tpc := this.EvaluateProgramCounter(jnz_ri_stmt.Pc())\n\n\t\tinstruction_.InitZrici(op_code, ra, imm, condition, pc)\n\t} else if op_code == instruction.CALL {\n\t\timm := this.EvaluateProgramCounter(jnz_ri_stmt.Pc())\n\n\t\tinstruction_.InitZri(op_code, ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJumpIStmt(stmt_ *stmt.Stmt) {\n\tjump_i_stmt := stmt_.JumpIStmt()\n\n\top_code := instruction.CALL\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(jump_i_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZri(op_code, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkJumpRStmt(stmt_ *stmt.Stmt) {\n\tjump_r_stmt := stmt_.JumpRStmt()\n\n\top_code := instruction.CALL\n\tra := this.ConvertSrcReg(jump_r_stmt.Ra())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZri(op_code, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLbsRriStmt(stmt_ *stmt.Stmt) {\n\tlbs_rri_stmt := stmt_.LbsRriStmt()\n\n\top_code := this.ConvertLoadOpCode(lbs_rri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\trc := this.ConvertGpReg(lbs_rri_stmt.Rc())\n\tra := this.ConvertSrcReg(lbs_rri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(lbs_rri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErri(op_code, endian, rc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLbsSRriStmt(stmt_ *stmt.Stmt) {\n\tlbs_s_rri_stmt := stmt_.LbsSRriStmt()\n\n\top_code := this.ConvertLoadOpCode(lbs_s_rri_stmt.OpCode())\n\tsuffix := this.ConvertSuffix(lbs_s_rri_stmt.Suffix(), instruction.ERRI)\n\tendian := instruction.LITTLE\n\tdc := this.ConvertPairReg(lbs_s_rri_stmt.Dc())\n\tra := this.ConvertSrcReg(lbs_s_rri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(lbs_s_rri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSErri(op_code, suffix, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLdDriStmt(stmt_ *stmt.Stmt) {\n\tld_dri_stmt := stmt_.LdDriStmt()\n\n\top_code := this.ConvertLoadOpCode(ld_dri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tdc := this.ConvertPairReg(ld_dri_stmt.Dc())\n\tra := this.ConvertSrcReg(ld_dri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(ld_dri_stmt.Off())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitEdri(op_code, endian, dc, ra, off)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMovdDdStmt(stmt_ *stmt.Stmt) {\n\tmovd_dd_stmt := stmt_.MovdDdStmt()\n\n\top_code := this.ConvertDdciOpCode(movd_dd_stmt.OpCode())\n\tdc := this.ConvertPairReg(movd_dd_stmt.Dc())\n\tdb := this.ConvertPairReg(movd_dd_stmt.Db())\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitDdci(op_code, dc, db, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveRiciStmt(stmt_ *stmt.Stmt) {\n\tmove_rici_stmt := stmt_.MoveRiciStmt()\n\n\top_code := instruction.OR\n\trc := this.ConvertGpReg(move_rici_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_rici_stmt.Imm())\n\tcondition := this.ConvertCondition(move_rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(move_rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRrici(op_code, rc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveRiStmt(stmt_ *stmt.Stmt) {\n\tmove_ri_stmt := stmt_.MoveRiStmt()\n\n\top_code := instruction.OR\n\trc := this.ConvertGpReg(move_ri_stmt.Rc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitRri(op_code, rc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveSRiciStmt(stmt_ *stmt.Stmt) {\n\tmove_s_rici_stmt := stmt_.MoveSRiciStmt()\n\n\top_code := instruction.OR\n\tsuffix := this.ConvertSuffix(move_s_rici_stmt.Suffix(), instruction.RRICI)\n\tdc := this.ConvertPairReg(move_s_rici_stmt.Dc())\n\n\tzero_reg := new(reg_descriptor.SpRegDescriptor)\n\t*zero_reg = reg_descriptor.ZERO\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(zero_reg)\n\n\timm := this.EvaluateProgramCounter(move_s_rici_stmt.Imm())\n\tcondition := this.ConvertCondition(move_s_rici_stmt.Condition())\n\tpc := this.EvaluateProgramCounter(move_s_rici_stmt.Pc())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRrici(op_code, suffix, dc, ra, imm, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkMoveSRiStmt(stmt_ *stmt.Stmt) {\n\tmove_s_ri_stmt := stmt_.MoveSRiStmt()\n\n\t// NOTE(bongjoon.hyun@gmail.com): move.s is implemented by using and.s:rki\n\top_code := instruction.AND\n\tsuffix := this.ConvertSuffix(move_s_ri_stmt.Suffix(), instruction.RRI)\n\tdc := this.ConvertPairReg(move_s_ri_stmt.Dc())\n\n\tlneg_reg := new(reg_descriptor.SpRegDescriptor)\n\t*lneg_reg = reg_descriptor.LNEG\n\tra := new(reg_descriptor.SrcRegDescriptor)\n\tra.InitSpRegDescriptor(lneg_reg)\n\n\timm := this.EvaluateProgramCounter(move_s_ri_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitSRri(op_code, suffix, dc, ra, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbIdRiiStmt(stmt_ *stmt.Stmt) {\n\tsb_id_rii_stmt := stmt_.SbIdRiiStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_id_rii_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_id_rii_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_id_rii_stmt.Off())\n\timm := this.EvaluateProgramCounter(sb_id_rii_stmt.Imm())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbIdRiStmt(stmt_ *stmt.Stmt) {\n\tsb_id_ri_stmt := stmt_.SbIdRiStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_id_ri_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_id_ri_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_id_ri_stmt.Off())\n\timm := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErii(op_code, endian, ra, off, imm)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSbRirStmt(stmt_ *stmt.Stmt) {\n\tsb_rir_stmt := stmt_.SbRirStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_rir_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_rir_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_rir_stmt.Off())\n\trb := this.ConvertSrcReg(sb_rir_stmt.Rb())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErir(op_code, endian, ra, off, rb)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkSdRidStmt(stmt_ *stmt.Stmt) {\n\tsb_rid_stmt := stmt_.SdRidStmt()\n\n\top_code := this.ConvertStoreOpCode(sb_rid_stmt.OpCode())\n\tendian := instruction.LITTLE\n\tra := this.ConvertSrcReg(sb_rid_stmt.Ra())\n\toff := this.EvaluateProgramCounter(sb_rid_stmt.Off())\n\tdb := this.ConvertPairReg(sb_rid_stmt.Db())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitErid(op_code, endian, ra, off, db)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkStopStmt(stmt_ *stmt.Stmt) {\n\top_code := instruction.STOP\n\tcondition := cc.FALSE\n\tpc := int64(0)\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitCi(op_code, condition, pc)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkTimeCfgRStmt(stmt_ *stmt.Stmt) {\n\ttime_cfg_r_stmt := stmt_.TimeCfgRStmt()\n\n\top_code := instruction.TIME_CFG\n\tra := this.ConvertSrcReg(time_cfg_r_stmt.Ra())\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.InitZr(op_code, ra)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.Append(instruction_)\n}\n\nfunc (this *InstructionAssigner) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tlabel_name := token.Attribute()\n\n\tif label_name != \"__sys_used_mram_end\" {\n\t\tthis.executable.CurSection().CheckoutLabel(label_name)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n\nfunc (this *InstructionAssigner) ConvertCiOpCode(op_code *expr.Expr) instruction.OpCode {\n\tci_op_code_expr := op_code.CiOpCodeExpr()\n\n\ttoken_type := ci_op_code_expr.Token().TokenType()\n\tif token_type == lexer.STOP {\n\t\treturn instruction.STOP\n\t} else {\n\t\terr := errors.New(\"CI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDdciOpCode(op_code *expr.Expr) instruction.OpCode {\n\tddci_op_code_expr := op_code.DdciOpCodeExpr()\n\n\ttoken_type := ddci_op_code_expr.Token().TokenType()\n\tif token_type == lexer.MOVD {\n\t\treturn instruction.MOVD\n\t} else if token_type == lexer.SWAPD {\n\t\treturn instruction.SWAPD\n\t} else {\n\t\terr := errors.New(\"DDCI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDmaRriOpCode(op_code *expr.Expr) instruction.OpCode {\n\tdma_rri_op_code_expr := op_code.DmaRriOpCodeExpr()\n\n\ttoken_type := dma_rri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LDMA {\n\t\treturn instruction.LDMA\n\t} else if token_type == lexer.LDMAI {\n\t\treturn instruction.LDMAI\n\t} else if token_type == lexer.SDMA {\n\t\treturn instruction.SDMA\n\t} else {\n\t\terr := errors.New(\"DMA_RRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertDrdiciOpCode(op_code *expr.Expr) instruction.OpCode {\n\tdrdici_op_code_expr := op_code.DrdiciOpCodeExpr()\n\n\ttoken_type := drdici_op_code_expr.Token().TokenType()\n\tif token_type == lexer.DIV_STEP {\n\t\treturn instruction.DIV_STEP\n\t} else if token_type == lexer.MUL_STEP {\n\t\treturn instruction.MUL_STEP\n\t} else {\n\t\terr := errors.New(\"DRDICI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertIOpCode(op_code *expr.Expr) instruction.OpCode {\n\ti_op_code_expr := op_code.IOpCodeExpr()\n\n\ttoken_type := i_op_code_expr.Token().TokenType()\n\tif token_type == lexer.FAULT {\n\t\treturn instruction.FAULT\n\t} else {\n\t\terr := errors.New(\"I op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRiciOpCode(op_code *expr.Expr) instruction.OpCode {\n\trici_op_code_expr := op_code.RiciOpCodeExpr()\n\n\ttoken_type := rici_op_code_expr.Token().TokenType()\n\tif token_type == lexer.ACQUIRE {\n\t\treturn instruction.ACQUIRE\n\t} else if token_type == lexer.RELEASE {\n\t\treturn instruction.RELEASE\n\t} else if token_type == lexer.BOOT {\n\t\treturn instruction.BOOT\n\t} else if token_type == lexer.RESUME {\n\t\treturn instruction.RESUME\n\t} else {\n\t\terr := errors.New(\"I op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertROpCode(op_code *expr.Expr) instruction.OpCode {\n\tr_op_code_expr := op_code.ROpCodeExpr()\n\n\ttoken_type := r_op_code_expr.Token().TokenType()\n\tif token_type == lexer.TIME {\n\t\treturn instruction.TIME\n\t} else if token_type == lexer.NOP {\n\t\treturn instruction.NOP\n\t} else {\n\t\terr := errors.New(\"R op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRrOpCode(op_code *expr.Expr) instruction.OpCode {\n\trr_op_code_expr := op_code.RrOpCodeExpr()\n\n\ttoken_type := rr_op_code_expr.Token().TokenType()\n\tif token_type == lexer.CAO {\n\t\treturn instruction.CAO\n\t} else if token_type == lexer.CLO {\n\t\treturn instruction.CLO\n\t} else if token_type == lexer.CLS {\n\t\treturn instruction.CLS\n\t} else if token_type == lexer.CLZ {\n\t\treturn instruction.CLZ\n\t} else if token_type == lexer.EXTSB {\n\t\treturn instruction.EXTSB\n\t} else if token_type == lexer.EXTSH {\n\t\treturn instruction.EXTSH\n\t} else if token_type == lexer.EXTUB {\n\t\treturn instruction.EXTUB\n\t} else if token_type == lexer.EXTUH {\n\t\treturn instruction.EXTUH\n\t} else if token_type == lexer.SATS {\n\t\treturn instruction.SATS\n\t} else if token_type == lexer.TIME_CFG {\n\t\treturn instruction.TIME_CFG\n\t} else if token_type == lexer.MOVE {\n\t\treturn instruction.OR\n\t} else if token_type == lexer.NEG {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.NOT {\n\t\treturn instruction.XOR\n\t} else {\n\t\terr := errors.New(\"RR op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRriOpCode(op_code *expr.Expr) instruction.OpCode {\n\trri_op_code_expr := op_code.RriOpCodeExpr()\n\n\ttoken_type := rri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.ADD {\n\t\treturn instruction.ADD\n\t} else if token_type == lexer.ADDC {\n\t\treturn instruction.ADDC\n\t} else if token_type == lexer.AND {\n\t\treturn instruction.AND\n\t} else if token_type == lexer.ANDN {\n\t\treturn instruction.ANDN\n\t} else if token_type == lexer.ASR {\n\t\treturn instruction.ASR\n\t} else if token_type == lexer.CMPB4 {\n\t\treturn instruction.CMPB4\n\t} else if token_type == lexer.LSL {\n\t\treturn instruction.LSL\n\t} else if token_type == lexer.LSL1 {\n\t\treturn instruction.LSL1\n\t} else if token_type == lexer.LSL1X {\n\t\treturn instruction.LSL1X\n\t} else if token_type == lexer.LSLX {\n\t\treturn instruction.LSLX\n\t} else if token_type == lexer.LSR {\n\t\treturn instruction.LSR\n\t} else if token_type == lexer.LSR1 {\n\t\treturn instruction.LSR1\n\t} else if token_type == lexer.LSR1X {\n\t\treturn instruction.LSR1X\n\t} else if token_type == lexer.LSRX {\n\t\treturn instruction.LSRX\n\t} else if token_type == lexer.MUL_SH_SH {\n\t\treturn instruction.MUL_SH_SH\n\t} else if token_type == lexer.MUL_SH_SL {\n\t\treturn instruction.MUL_SH_SL\n\t} else if token_type == lexer.MUL_SH_UH {\n\t\treturn instruction.MUL_SH_UH\n\t} else if token_type == lexer.MUL_SH_UL {\n\t\treturn instruction.MUL_SH_UL\n\t} else if token_type == lexer.MUL_SL_SH {\n\t\treturn instruction.MUL_SL_SH\n\t} else if token_type == lexer.MUL_SL_SL {\n\t\treturn instruction.MUL_SL_SL\n\t} else if token_type == lexer.MUL_SL_UH {\n\t\treturn instruction.MUL_SL_UH\n\t} else if token_type == lexer.MUL_SL_UL {\n\t\treturn instruction.MUL_SL_UL\n\t} else if token_type == lexer.MUL_UH_UH {\n\t\treturn instruction.MUL_UH_UH\n\t} else if token_type == lexer.MUL_UH_UL {\n\t\treturn instruction.MUL_UH_UL\n\t} else if token_type == lexer.MUL_UL_UH {\n\t\treturn instruction.MUL_UL_UH\n\t} else if token_type == lexer.MUL_UL_UL {\n\t\treturn instruction.MUL_UL_UL\n\t} else if token_type == lexer.NAND {\n\t\treturn instruction.NAND\n\t} else if token_type == lexer.NOR {\n\t\treturn instruction.NOR\n\t} else if token_type == lexer.NXOR {\n\t\treturn instruction.NXOR\n\t} else if token_type == lexer.OR {\n\t\treturn instruction.OR\n\t} else if token_type == lexer.ORN {\n\t\treturn instruction.ORN\n\t} else if token_type == lexer.ROL {\n\t\treturn instruction.ROL\n\t} else if token_type == lexer.ROR {\n\t\treturn instruction.ROR\n\t} else if token_type == lexer.RSUB {\n\t\treturn instruction.RSUB\n\t} else if token_type == lexer.RSUBC {\n\t\treturn instruction.RSUBC\n\t} else if token_type == lexer.SUB {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.SUBC {\n\t\treturn instruction.SUBC\n\t} else if token_type == lexer.XOR {\n\t\treturn instruction.XOR\n\t} else if token_type == lexer.CALL {\n\t\treturn instruction.CALL\n\t} else if token_type == lexer.HASH {\n\t\treturn instruction.HASH\n\t} else {\n\t\terr := errors.New(\"RRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertRrriOpCode(op_code *expr.Expr) instruction.OpCode {\n\trrri_op_code_expr := op_code.RrriOpCodeExpr()\n\n\ttoken_type := rrri_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LSL_ADD {\n\t\treturn instruction.LSL_ADD\n\t} else if token_type == lexer.LSL_SUB {\n\t\treturn instruction.LSL_SUB\n\t} else if token_type == lexer.LSR_ADD {\n\t\treturn instruction.LSR_ADD\n\t} else if token_type == lexer.ROL_ADD {\n\t\treturn instruction.ROL_ADD\n\t} else {\n\t\terr := errors.New(\"RRRI op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertLoadOpCode(op_code *expr.Expr) instruction.OpCode {\n\tload_op_code_expr := op_code.LoadOpCodeExpr()\n\n\ttoken_type := load_op_code_expr.Token().TokenType()\n\tif token_type == lexer.LBS {\n\t\treturn instruction.LBS\n\t} else if token_type == lexer.LBU {\n\t\treturn instruction.LBU\n\t} else if token_type == lexer.LD {\n\t\treturn instruction.LD\n\t} else if token_type == lexer.LHS {\n\t\treturn instruction.LHS\n\t} else if token_type == lexer.LHU {\n\t\treturn instruction.LHU\n\t} else if token_type == lexer.LW {\n\t\treturn instruction.LW\n\t} else {\n\t\terr := errors.New(\"load op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertStoreOpCode(op_code *expr.Expr) instruction.OpCode {\n\tstore_op_code_expr := op_code.StoreOpCodeExpr()\n\n\ttoken_type := store_op_code_expr.Token().TokenType()\n\tif token_type == lexer.SB {\n\t\treturn instruction.SB\n\t} else if token_type == lexer.SB_ID {\n\t\treturn instruction.SB_ID\n\t} else if token_type == lexer.SD {\n\t\treturn instruction.SD\n\t} else if token_type == lexer.SD_ID {\n\t\treturn instruction.SD_ID\n\t} else if token_type == lexer.SH {\n\t\treturn instruction.SH\n\t} else if token_type == lexer.SH_ID {\n\t\treturn instruction.SH_ID\n\t} else if token_type == lexer.SW {\n\t\treturn instruction.SW\n\t} else if token_type == lexer.SW_ID {\n\t\treturn instruction.SW_ID\n\t} else {\n\t\terr := errors.New(\"store op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertJumpOpCode(op_code *expr.Expr) instruction.OpCode {\n\tjump_op_code_expr := op_code.JumpOpCodeExpr()\n\n\ttoken_type := jump_op_code_expr.Token().TokenType()\n\tif token_type == lexer.JEQ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGES {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGEU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGTS {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JGTU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLES {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLEU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLTS {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JLTU {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JNEQ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JNZ {\n\t\treturn instruction.SUB\n\t} else if token_type == lexer.JUMP {\n\t\treturn instruction.CALL\n\t} else if token_type == lexer.JZ {\n\t\treturn instruction.SUB\n\t} else {\n\t\terr := errors.New(\"jump op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertSuffix(\n\tsuffix *expr.Expr,\n\tbase instruction.Suffix,\n) instruction.Suffix {\n\tsuffix_expr := suffix.SuffixExpr()\n\n\ttoken_type := suffix_expr.Token().TokenType()\n\tif token_type == lexer.S {\n\t\tif base == instruction.ERRI {\n\t\t\treturn instruction.S_ERRI\n\t\t} else if base == instruction.RCI {\n\t\t\treturn instruction.S_RCI\n\t\t} else if base == instruction.RIRCI {\n\t\t\treturn instruction.S_RIRCI\n\t\t} else if base == instruction.RIRC {\n\t\t\treturn instruction.S_RIRC\n\t\t} else if base == instruction.RRCI {\n\t\t\treturn instruction.S_RRCI\n\t\t} else if base == instruction.RRC {\n\t\t\treturn instruction.S_RRC\n\t\t} else if base == instruction.RRICI {\n\t\t\treturn instruction.S_RRICI\n\t\t} else if base == instruction.RRIC {\n\t\t\treturn instruction.S_RRIC\n\t\t} else if base == instruction.RRI {\n\t\t\treturn instruction.S_RRI\n\t\t} else if base == instruction.RRRCI {\n\t\t\treturn instruction.S_RRRCI\n\t\t} else if base == instruction.RRRC {\n\t\t\treturn instruction.S_RRRC\n\t\t} else if base == instruction.RRRICI {\n\t\t\treturn instruction.S_RRRICI\n\t\t} else if base == instruction.RRRI {\n\t\t\treturn instruction.S_RRRI\n\t\t} else if base == instruction.RRR {\n\t\t\treturn instruction.S_RRR\n\t\t} else if base == instruction.RR {\n\t\t\treturn instruction.S_RR\n\t\t} else if base == instruction.R {\n\t\t\treturn instruction.S_R\n\t\t} else {\n\t\t\terr := errors.New(\"base is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if token_type == lexer.U {\n\t\tif base == instruction.ERRI {\n\t\t\treturn instruction.U_ERRI\n\t\t} else if base == instruction.RCI {\n\t\t\treturn instruction.U_RCI\n\t\t} else if base == instruction.RIRCI {\n\t\t\treturn instruction.U_RIRCI\n\t\t} else if base == instruction.RIRC {\n\t\t\treturn instruction.U_RIRC\n\t\t} else if base == instruction.RRCI {\n\t\t\treturn instruction.U_RRCI\n\t\t} else if base == instruction.RRC {\n\t\t\treturn instruction.U_RRC\n\t\t} else if base == instruction.RRICI {\n\t\t\treturn instruction.U_RRICI\n\t\t} else if base == instruction.RRIC {\n\t\t\treturn instruction.U_RRIC\n\t\t} else if base == instruction.RRI {\n\t\t\treturn instruction.U_RRI\n\t\t} else if base == instruction.RRRCI {\n\t\t\treturn instruction.U_RRRCI\n\t\t} else if base == instruction.RRRC {\n\t\t\treturn instruction.U_RRRC\n\t\t} else if base == instruction.RRRICI {\n\t\t\treturn instruction.U_RRRICI\n\t\t} else if base == instruction.RRRI {\n\t\t\treturn instruction.U_RRRI\n\t\t} else if base == instruction.RRR {\n\t\t\treturn instruction.U_RRR\n\t\t} else if base == instruction.RR {\n\t\t\treturn instruction.U_RR\n\t\t} else if base == instruction.R {\n\t\t\treturn instruction.U_R\n\t\t} else {\n\t\t\terr := errors.New(\"base is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertGpReg(expr_ *expr.Expr) *reg_descriptor.GpRegDescriptor {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\tindex, err := strconv.Atoi(src_reg_expr.Token().Attribute()[1:])\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\tgp_reg_descriptor.Init(index)\n\treturn gp_reg_descriptor\n}\n\nfunc (this *InstructionAssigner) ConvertSrcReg(expr_ *expr.Expr) *reg_descriptor.SrcRegDescriptor {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\ttoken := src_reg_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.GP_REG {\n\t\tgp_reg_descriptor := this.ConvertGpReg(expr_)\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitGpRegDescriptor(gp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ZERO_REG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ZERO\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ONE {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ONE\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID2 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID2\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID4 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID4\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.ID8 {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.ID8\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.LNEG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.LNEG\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else if token_type == lexer.MNEG {\n\t\tsp_reg_descriptor := new(reg_descriptor.SpRegDescriptor)\n\t\t*sp_reg_descriptor = reg_descriptor.MNEG\n\n\t\tsrc_reg_descriptor := new(reg_descriptor.SrcRegDescriptor)\n\t\tsrc_reg_descriptor.InitSpRegDescriptor(sp_reg_descriptor)\n\t\treturn src_reg_descriptor\n\t} else {\n\t\terr := errors.New(\"src reg is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertPairReg(\n\ttoken *lexer.Token,\n) *reg_descriptor.PairRegDescriptor {\n\tindex, err := strconv.Atoi(token.Attribute()[1:])\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tpair_reg_descriptor := new(reg_descriptor.PairRegDescriptor)\n\tpair_reg_descriptor.Init(index)\n\treturn pair_reg_descriptor\n}\n\nfunc (this *InstructionAssigner) ConvertCondition(expr_ *expr.Expr) cc.Condition {\n\tcondition_expr := expr_.ConditionExpr()\n\n\ttoken := condition_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.TRUE {\n\t\treturn cc.TRUE\n\t} else if token_type == lexer.FALSE {\n\t\treturn cc.FALSE\n\t} else if token_type == lexer.Z {\n\t\treturn cc.Z\n\t} else if token_type == lexer.NZ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.E {\n\t\treturn cc.E\n\t} else if token_type == lexer.O {\n\t\treturn cc.O\n\t} else if token_type == lexer.PL {\n\t\treturn cc.PL\n\t} else if token_type == lexer.MI {\n\t\treturn cc.MI\n\t} else if token_type == lexer.OV {\n\t\treturn cc.OV\n\t} else if token_type == lexer.NOV {\n\t\treturn cc.NOV\n\t} else if token_type == lexer.C {\n\t\treturn cc.C\n\t} else if token_type == lexer.NC {\n\t\treturn cc.NC\n\t} else if token_type == lexer.SZ {\n\t\treturn cc.SZ\n\t} else if token_type == lexer.SNZ {\n\t\treturn cc.SNZ\n\t} else if token_type == lexer.SPL {\n\t\treturn cc.SPL\n\t} else if token_type == lexer.SMI {\n\t\treturn cc.SMI\n\t} else if token_type == lexer.SO {\n\t\treturn cc.SO\n\t} else if token_type == lexer.SE {\n\t\treturn cc.SE\n\t} else if token_type == lexer.NC5 {\n\t\treturn cc.NC5\n\t} else if token_type == lexer.NC6 {\n\t\treturn cc.NC6\n\t} else if token_type == lexer.NC7 {\n\t\treturn cc.NC7\n\t} else if token_type == lexer.NC8 {\n\t\treturn cc.NC8\n\t} else if token_type == lexer.NC9 {\n\t\treturn cc.NC9\n\t} else if token_type == lexer.NC10 {\n\t\treturn cc.NC10\n\t} else if token_type == lexer.NC11 {\n\t\treturn cc.NC11\n\t} else if token_type == lexer.NC12 {\n\t\treturn cc.NC12\n\t} else if token_type == lexer.NC13 {\n\t\treturn cc.NC13\n\t} else if token_type == lexer.NC14 {\n\t\treturn cc.NC14\n\t} else if token_type == lexer.MAX {\n\t\treturn cc.MAX\n\t} else if token_type == lexer.NMAX {\n\t\treturn cc.NMAX\n\t} else if token_type == lexer.SH32 {\n\t\treturn cc.SH32\n\t} else if token_type == lexer.NSH32 {\n\t\treturn cc.NSH32\n\t} else if token_type == lexer.EQ {\n\t\treturn cc.EQ\n\t} else if token_type == lexer.NEQ {\n\t\treturn cc.NEQ\n\t} else if token_type == lexer.LTU {\n\t\treturn cc.LTU\n\t} else if token_type == lexer.LEU {\n\t\treturn cc.LEU\n\t} else if token_type == lexer.GTU {\n\t\treturn cc.GTU\n\t} else if token_type == lexer.GEU {\n\t\treturn cc.GEU\n\t} else if token_type == lexer.LTS {\n\t\treturn cc.LTS\n\t} else if token_type == lexer.LES {\n\t\treturn cc.LES\n\t} else if token_type == lexer.GTS {\n\t\treturn cc.GTS\n\t} else if token_type == lexer.GES {\n\t\treturn cc.GES\n\t} else if token_type == lexer.XZ {\n\t\treturn cc.XZ\n\t} else if token_type == lexer.XNZ {\n\t\treturn cc.XNZ\n\t} else if token_type == lexer.XLEU {\n\t\treturn cc.XLEU\n\t} else if token_type == lexer.XGTU {\n\t\treturn cc.XGTU\n\t} else if token_type == lexer.XLES {\n\t\treturn cc.XLES\n\t} else if token_type == lexer.XGTS {\n\t\treturn cc.XGTS\n\t} else if token_type == lexer.SMALL {\n\t\treturn cc.SMALL\n\t} else if token_type == lexer.LARGE {\n\t\treturn cc.LARGE\n\t} else {\n\t\terr := errors.New(\"condition is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertEndian(expr_ *expr.Expr) instruction.Endian {\n\tendian_expr := expr_.EndianExpr()\n\n\ttoken := endian_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.LITTLE {\n\t\treturn instruction.LITTLE\n\t} else if token_type == lexer.BIG {\n\t\treturn instruction.BIG\n\t} else {\n\t\terr := errors.New(\"endian is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) ConvertJumpCondition(op_code *expr.Expr) cc.Condition {\n\tjump_op_code_expr := op_code.JumpOpCodeExpr()\n\n\ttoken_type := jump_op_code_expr.Token().TokenType()\n\tif token_type == lexer.JEQ {\n\t\treturn cc.Z\n\t} else if token_type == lexer.JGES {\n\t\treturn cc.GES\n\t} else if token_type == lexer.JGEU {\n\t\treturn cc.GEU\n\t} else if token_type == lexer.JGTS {\n\t\treturn cc.GTS\n\t} else if token_type == lexer.JGTU {\n\t\treturn cc.GTU\n\t} else if token_type == lexer.JLES {\n\t\treturn cc.LES\n\t} else if token_type == lexer.JLEU {\n\t\treturn cc.LEU\n\t} else if token_type == lexer.JLTS {\n\t\treturn cc.LTS\n\t} else if token_type == lexer.JLTU {\n\t\treturn cc.LTU\n\t} else if token_type == lexer.JNEQ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.JNZ {\n\t\treturn cc.NZ\n\t} else if token_type == lexer.JZ {\n\t\treturn cc.Z\n\t} else {\n\t\terr := errors.New(\"jump op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateProgramCounter(expr_ *expr.Expr) int64 {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\n\tchild_expr := program_counter_expr.Expr()\n\tchild_expr_type := child_expr.ExprType()\n\tif child_expr_type == expr.PRIMARY {\n\t\treturn this.EvaluatePrimary(child_expr)\n\t} else if child_expr_type == expr.NEGATIVE_NUMBER {\n\t\treturn this.EvaluateNegativeNumber(child_expr)\n\t} else if child_expr_type == expr.BINARY_ADD {\n\t\treturn this.EvaluateBinaryAdd(child_expr)\n\t} else if child_expr_type == expr.BINARY_SUB {\n\t\treturn this.EvaluateBinarySub(child_expr)\n\t} else {\n\t\terr := errors.New(\"program counter expr is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluatePrimary(expr_ *expr.Expr) int64 {\n\tprimary_expr := expr_.PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\ttoken_type := token.TokenType()\n\tif token_type == lexer.POSITIVIE_NUMBER {\n\t\treturn this.EvaluatePositiveNumber(token)\n\t} else if token_type == lexer.HEX_NUMBER {\n\t\treturn this.EvaluateHexNumber(token)\n\t} else if token_type == lexer.IDENTIFIER {\n\t\treturn this.EvaluateIdentifier(token)\n\t} else {\n\t\terr := errors.New(\"primary expr is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluatePositiveNumber(token *lexer.Token) int64 {\n\tvalue, err := strconv.ParseInt(token.Attribute(), 10, 64)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn value\n}\n\nfunc (this *InstructionAssigner) EvaluateHexNumber(token *lexer.Token) int64 {\n\tattribute := token.Attribute()\n\tvar value int64\n\tvar err error\n\tif attribute[:2] == \"0x\" {\n\t\tvalue, err = strconv.ParseInt(attribute[2:], 16, 64)\n\t} else {\n\t\tvalue, err = strconv.ParseInt(attribute, 16, 64)\n\t}\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn value\n}\n\nfunc (this *InstructionAssigner) EvaluateIdentifier(token *lexer.Token) int64 {\n\tname := token.Attribute()\n\n\tlabel := this.executable.Label(name)\n\tlinker_constant := this.linker_script.LinkerConstant(name)\n\n\tif label != nil {\n\t\tif linker_constant != nil {\n\t\t\terr := errors.New(\"label and linker constant both exist\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\treturn label.Address()\n\t} else if linker_constant != nil {\n\t\treturn linker_constant.Value()\n\t} else {\n\t\terr := errors.New(\"label and linker constant do not exist\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateNegativeNumber(expr_ *expr.Expr) int64 {\n\tnegative_number_expr := expr_.NegativeNumberExpr()\n\n\treturn -this.EvaluatePositiveNumber(negative_number_expr.Token())\n}\n\nfunc (this *InstructionAssigner) EvaluateBinaryAdd(expr_ *expr.Expr) int64 {\n\tbinary_add_expr := expr_.BinaryAddExpr()\n\n\tis_operand1_nr_tasklets := binary_add_expr.Operand1().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tAttribute() ==\n\t\t\"NR_TASKLETS\"\n\tis_operand2_number := binary_add_expr.Operand2().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tTokenType() !=\n\t\tlexer.IDENTIFIER\n\tif !is_operand1_nr_tasklets && is_operand2_number {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand1(),\n\t\t) + iram_data_size*this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand2(),\n\t\t)\n\t} else {\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand1(),\n\t\t) + this.EvaluatePrimary(\n\t\t\tbinary_add_expr.Operand2(),\n\t\t)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateBinarySub(expr_ *expr.Expr) int64 {\n\tbinary_sub_expr := expr_.BinarySubExpr()\n\n\tis_operand1_nr_tasklets := binary_sub_expr.Operand1().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tAttribute() ==\n\t\t\"NR_TASKLETS\"\n\tis_operand2_number := binary_sub_expr.Operand2().\n\t\tPrimaryExpr().\n\t\tToken().\n\t\tTokenType() !=\n\t\tlexer.IDENTIFIER\n\tif !is_operand1_nr_tasklets && is_operand2_number {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand1(),\n\t\t) - iram_data_size*this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand2(),\n\t\t)\n\t} else {\n\t\treturn this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand1(),\n\t\t) - this.EvaluatePrimary(\n\t\t\tbinary_sub_expr.Operand2(),\n\t\t)\n\t}\n}\n\nfunc (this *InstructionAssigner) EvaluateSectionName(expr_ *expr.Expr) int64 {\n\tsection_name := this.ConvertSectionName(expr_)\n\tname := \"\"\n\n\treturn this.executable.Section(section_name, name).Address()\n}\n\nfunc (this *InstructionAssigner) IsZeroReg(expr_ *expr.Expr) bool {\n\tsrc_reg_expr := expr_.SrcRegExpr()\n\n\treturn src_reg_expr.Token().TokenType() == lexer.ZERO_REG\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/label_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype LabelAssigner struct {\n\texecutable *kernel.Executable\n\twalker     *parser.Walker\n}\n\nfunc (this *LabelAssigner) Init() {\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(stmt.ASCII, this.WalkAsciiStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ASCIZ, this.WalkAscizStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BYTE, this.WalkByteStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_PROGRAM_COUNTER, this.WalkLongProgramCounterStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LONG_SECTION_NAME, this.WalkLongSectionNameStmt)\n\tthis.walker.RegisterStmtCallback(stmt.QUAD, this.WalkQuadStmt)\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SHORT, this.WalkShortStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_DOUBLE_NUMBER, this.WalkZeroDoubleNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ZERO_SINGLE_NUMBER, this.WalkZeroSingleNumberStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.CI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DDCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DMA_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DRDICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.EDRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERID, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.ERRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.I, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.NOP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRIC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RRR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.S_ERRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RIRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRIC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRCI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRC, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RRR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.S_R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.BKP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.BOOT_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.CALL_RR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.DIV_STEP_DRDI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JEQ_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JNZ_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_I, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.JUMP_R, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LBS_S_RRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LD_DRI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVD_DD, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RICI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.MOVE_S_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RII, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_ID_RI, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SB_RIR, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SD_RID, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.STOP, this.WalkInstructionStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TIME_CFG_R, this.WalkInstructionStmt)\n\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *LabelAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *LabelAssigner) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tascii_stmt := stmt_.AsciiStmt()\n\ttoken := ascii_stmt.Token()\n\tattribute := token.Attribute()\n\n\t// TODO(bongjoon.hyun@gmail.com): decode octal code\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + int64(len(attribute)) - 2)\n}\n\nfunc (this *LabelAssigner) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tasciz_stmt := stmt_.AscizStmt()\n\ttoken := asciz_stmt.Token()\n\tattribute := token.Attribute()\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + int64(len(attribute)) - 1)\n}\n\nfunc (this *LabelAssigner) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 1)\n}\n\nfunc (this *LabelAssigner) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 4)\n}\n\nfunc (this *LabelAssigner) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 4)\n}\n\nfunc (this *LabelAssigner) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 8)\n}\n\nfunc (this *LabelAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\tsection_flags := this.ConvertSectionFlags(section_identifier_number_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_identifier_number_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\tsection_flags := this.ConvertSectionFlags(section_identifier_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_identifier_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\tsection_flags := this.ConvertSectionFlags(section_stack_sizes_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_stack_sizes_stmt.Expr1())\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\tsection_flags := this.ConvertSectionFlags(section_string_number_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_string_number_stmt.Expr2())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\tsection_flags := this.ConvertSectionFlags(section_string_stmt.Token())\n\tsection_type := this.ConvertSectionType(section_string_stmt.Expr2())\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + 2)\n}\n\nfunc (this *LabelAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\tsection_flags := make(map[kernel.SectionFlag]bool)\n\tsection_type := kernel.PROGBITS\n\n\tif this.executable.Section(section_name, name) == nil {\n\t\tthis.executable.AddSection(section_name, name, section_flags, section_type)\n\t}\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *LabelAssigner) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\tprogram_counter_expr := zero_double_number_stmt.Expr1().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tattribute := token.Attribute()\n\n\tsize, err := strconv.ParseInt(attribute, 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + size)\n}\n\nfunc (this *LabelAssigner) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\tprogram_counter_expr := zero_single_number_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tattribute := token.Attribute()\n\n\tsize, err := strconv.ParseInt(attribute, 10, 64)\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + size)\n}\n\nfunc (this *LabelAssigner) WalkInstructionStmt(stmt_ *stmt.Stmt) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_width := config_loader.IramDataWidth()\n\tinstruction_size := int64(iram_data_width / 8)\n\n\tcur_label := this.executable.CurSection().CurLabel()\n\tcur_label.SetSize(cur_label.Size() + instruction_size)\n}\n\nfunc (this *LabelAssigner) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\tlabel_name := token.Attribute()\n\n\tif label_name != \"__sys_used_mram_end\" {\n\t\tif this.executable.CurSection().Label(label_name) == nil {\n\t\t\tthis.executable.CurSection().AppendLabel(label_name)\n\t\t}\n\n\t\tthis.executable.CurSection().CheckoutLabel(label_name)\n\t}\n}\n\nfunc (this *LabelAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LabelAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n\nfunc (this *LabelAssigner) ConvertSectionFlags(token *lexer.Token) map[kernel.SectionFlag]bool {\n\tattribute := token.Attribute()\n\n\tsection_flags := make(map[kernel.SectionFlag]bool)\n\tfor i := 1; i < len(attribute)-1; i++ {\n\t\tif attribute[i] == 'a' {\n\t\t\tsection_flags[kernel.ALLOC] = true\n\t\t} else if attribute[i] == 'w' {\n\t\t\tsection_flags[kernel.WRITE] = true\n\t\t} else if attribute[i] == 'x' {\n\t\t\tsection_flags[kernel.EXECINSTR] = true\n\t\t} else if attribute[i] == 'o' {\n\t\t\tsection_flags[kernel.LINK_ORDER] = true\n\t\t} else if attribute[i] == 'M' {\n\t\t\tsection_flags[kernel.MERGE] = true\n\t\t} else if attribute[i] == 'S' {\n\t\t\tsection_flags[kernel.STRINGS] = true\n\t\t} else {\n\t\t\terr := errors.New(\"section flag is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\treturn section_flags\n}\n\nfunc (this *LabelAssigner) ConvertSectionType(expr_ *expr.Expr) kernel.SectionType {\n\tsection_type_expr := expr_.SectionTypeExpr()\n\ttoken := section_type_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tif token_type == lexer.PROGBITS {\n\t\treturn kernel.PROGBITS\n\t} else if token_type == lexer.NOBITS {\n\t\treturn kernel.NOBITS\n\t} else {\n\t\terr := errors.New(\"section type is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/linker_constant.go",
    "content": "package logic\n\ntype LinkerConstant struct {\n\tname  string\n\tvalue int64\n}\n\nfunc (this *LinkerConstant) Init(name string) {\n\tthis.name = name\n\tthis.value = 0\n}\n\nfunc (this *LinkerConstant) Name() string {\n\treturn this.name\n}\n\nfunc (this *LinkerConstant) Value() int64 {\n\treturn this.value\n}\n\nfunc (this *LinkerConstant) SetValue(value int64) {\n\tthis.value = value\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/linker_script.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"math\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype LinkerScript struct {\n\tcommand_line_parser *misc.CommandLineParser\n\n\tnum_tasklets           int\n\tmin_access_granularity int64\n\n\tlinker_constants map[string]*LinkerConstant\n}\n\nfunc (this *LinkerScript) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\n\tthis.linker_constants = make(map[string]*LinkerConstant)\n\n\tthis.InitLinkerConstants()\n}\n\nfunc (this *LinkerScript) Assign(executable *kernel.Executable) {\n\tthis.AssignAtomic(executable)\n\tthis.AssignIram(executable)\n\tthis.AssignWram(executable)\n\tthis.AssignMram(executable)\n}\n\nfunc (this *LinkerScript) HasLinkerConstant(name string) bool {\n\t_, found := this.linker_constants[name]\n\treturn found\n}\n\nfunc (this *LinkerScript) LinkerConstant(name string) *LinkerConstant {\n\treturn this.linker_constants[name]\n}\n\nfunc (this *LinkerScript) InitLinkerConstants() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmax_num_tasklets := config_loader.MaxNumTasklets()\n\tstack_size := config_loader.StackSize()\n\n\tthis.linker_constants[\"NR_TASKLETS\"] = new(LinkerConstant)\n\tthis.linker_constants[\"NR_TASKLETS\"].Init(\"NR_TASKLETS\")\n\tthis.linker_constants[\"NR_TASKLETS\"].SetValue(int64(this.num_tasklets))\n\n\tfor i := 0; i < max_num_tasklets; i++ {\n\t\tstack_size_tasklet := \"STACK_SIZE_TASKLET_\" + strconv.Itoa(i)\n\n\t\tthis.linker_constants[stack_size_tasklet] = new(LinkerConstant)\n\t\tthis.linker_constants[stack_size_tasklet].Init(stack_size_tasklet)\n\t\tthis.linker_constants[stack_size_tasklet].SetValue(stack_size)\n\t}\n\n\tthis.linker_constants[\"__atomic_start_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_start_addr\"].Init(\"__atomic_start_addr\")\n\n\tthis.linker_constants[\"__atomic_used_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_used_addr\"].Init(\"__atomic_used_addr\")\n\n\tthis.linker_constants[\"__atomic_end_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__atomic_end_addr\"].Init(\"__atomic_end_addr\")\n\n\tthis.linker_constants[\"__rodata_start_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__rodata_start_addr\"].Init(\"__rodata_start_addr\")\n\n\tthis.linker_constants[\"__rodata_end_addr\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__rodata_end_addr\"].Init(\"__rodata_end_addr\")\n\n\tfor i := 0; i < max_num_tasklets; i++ {\n\t\tsys_stack_thread := \"__sys_stack_thread_\" + strconv.Itoa(i)\n\n\t\tthis.linker_constants[sys_stack_thread] = new(LinkerConstant)\n\t\tthis.linker_constants[sys_stack_thread].Init(sys_stack_thread)\n\t}\n\n\tthis.linker_constants[\"__sw_cache_buffer\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sw_cache_buffer\"].Init(\"__sw_cache_buffer\")\n\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"].Init(\"__sys_heap_pointer_reset\")\n\n\tthis.linker_constants[\"__sys_used_mram_end\"] = new(LinkerConstant)\n\tthis.linker_constants[\"__sys_used_mram_end\"].Init(\"__sys_used_mram_end\")\n}\n\nfunc (this *LinkerScript) AssignAtomic(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.AtomicOffset()\n\n\tthis.linker_constants[\"__atomic_start_addr\"].SetValue(cur_address)\n\n\tthis.linker_constants[\"__atomic_used_addr\"].SetValue(cur_address)\n\n\tfor section, _ := range executable.Sections(kernel.ATOMIC) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tthis.linker_constants[\"__atomic_end_addr\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.AtomicOffset()+config_loader.AtomicSize() {\n\t\terr := errors.New(\"address is larger than the atomic end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignIram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.IramOffset()\n\n\tbootstrap := executable.Section(kernel.TEXT, \"__bootstrap\")\n\tif bootstrap == nil {\n\t\terr := errors.New(\"bootstrap is not found\")\n\t\tpanic(err)\n\t}\n\n\tbootstrap.SetAddress(cur_address)\n\tcur_address += bootstrap.Size()\n\n\ttext_default := executable.Section(kernel.TEXT, \"\")\n\tif text_default != nil {\n\t\ttext_default.SetAddress(cur_address)\n\t\tcur_address += text_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.TEXT) {\n\t\tif section.Name() != \"__bootstrap\" && section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tif cur_address >= config_loader.IramOffset()+config_loader.IramSize() {\n\t\terr := errors.New(\"address is larger than the IRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignWram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.WramOffset()\n\n\tsys_zero := executable.Section(kernel.DATA, \"__sys_zero\")\n\tif sys_zero != nil {\n\t\tsys_zero.SetAddress(cur_address)\n\t\tcur_address += sys_zero.Size()\n\t}\n\n\timmediate_memory := executable.Section(kernel.DATA, \"immediate_memory\")\n\tif immediate_memory != nil {\n\t\timmediate_memory.SetAddress(cur_address)\n\t\tcur_address += immediate_memory.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DATA) {\n\t\tif strings.Contains(section.Name(), \"immediate_memory.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tthis.linker_constants[\"__rodata_start_addr\"].SetValue(cur_address)\n\n\trodata_default := executable.Section(kernel.RODATA, \"\")\n\tif rodata_default != nil {\n\t\trodata_default.SetAddress(cur_address)\n\t\tcur_address += rodata_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.RODATA) {\n\t\tif section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tthis.linker_constants[\"__rodata_end_addr\"].SetValue(cur_address)\n\n\tbss_default := executable.Section(kernel.BSS, \"\")\n\tif bss_default != nil {\n\t\tbss_default.SetAddress(cur_address)\n\t\tcur_address += bss_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.BSS) {\n\t\tif section.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tsys_keep := executable.Section(kernel.DATA, \"__sys_keep\")\n\tif sys_keep != nil {\n\t\tsys_keep.SetAddress(cur_address)\n\t\tcur_address += sys_keep.Size()\n\t}\n\n\tdata_default := executable.Section(kernel.DATA, \"\")\n\tif data_default != nil {\n\t\tdata_default.SetAddress(cur_address)\n\t\tcur_address += data_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DATA) {\n\t\tif section.Name() != \"__sys_zero\" &&\n\t\t\tsection.Name() != \"__sys_keep\" &&\n\t\t\t!strings.Contains(section.Name(), \"immediate_memory\") &&\n\t\t\tsection.Name() != \"\" {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.__sys_host\" section\n\n\tdpu_host := executable.Section(kernel.DPU_HOST, \"\")\n\tif dpu_host != nil {\n\t\tdpu_host.SetAddress(cur_address)\n\t\tcur_address += dpu_host.Size()\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.__sys_profilng\" section\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.stacks\" section\n\n\tfor i := 0; i < config_loader.MaxNumTasklets(); i++ {\n\t\tsys_stack_thread := \"__sys_stack_thread_\" + strconv.Itoa(i)\n\t\tthis.linker_constants[sys_stack_thread].SetValue(cur_address)\n\n\t\tstack_size_tasklet := \"STACK_SIZE_TASKLET_\" + strconv.Itoa(i)\n\t\tcur_address += this.linker_constants[stack_size_tasklet].Value()\n\t}\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.sw_cache\" section\n\n\tthis.linker_constants[\"__sw_cache_buffer\"].SetValue(cur_address)\n\tcur_address += int64(8 * config_loader.MaxNumTasklets())\n\n\t// TODO(bongjoon.hyun@gmail.com): figure out \".data.heap_pointer_reset\" section\n\n\tcur_address = int64(\n\t\tmath.Ceil(float64(cur_address)/float64(this.min_access_granularity)),\n\t) * int64(\n\t\tthis.min_access_granularity,\n\t)\n\tthis.linker_constants[\"__sys_heap_pointer_reset\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.WramOffset()+config_loader.WramSize() {\n\t\terr := errors.New(\"address is larger than the WRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) AssignMram(executable *kernel.Executable) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tcur_address := config_loader.MramOffset()\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_ABBREV) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_FRAME) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_INFO) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_LINE) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_LOC) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_RANGES) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.DEBUG_STR) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.STACK_SIZES) {\n\t\tsection.SetAddress(cur_address)\n\t\tcur_address += section.Size()\n\t}\n\n\tnoinit := executable.Section(kernel.MRAM, \"noinit\")\n\tif noinit != nil {\n\t\tnoinit.SetAddress(cur_address)\n\t\tcur_address += noinit.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.\") &&\n\t\t\t!strings.Contains(section.Name(), \"noinit.keep\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tnoinit_keep := executable.Section(kernel.MRAM, \"noinit.keep\")\n\tif noinit_keep != nil {\n\t\tnoinit_keep.SetAddress(cur_address)\n\t\tcur_address += noinit_keep.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.keep\") &&\n\t\t\t!strings.Contains(section.Name(), \"noinit.keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"noinit.keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tmram_default := executable.Section(kernel.MRAM, \"\")\n\tif mram_default != nil {\n\t\tmram_default.SetAddress(cur_address)\n\t\tcur_address += mram_default.Size()\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif section.Name() != \"\" &&\n\t\t\t!strings.Contains(section.Name(), \"noinit\") &&\n\t\t\t!strings.Contains(section.Name(), \"keep\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"keep\") &&\n\t\t\t!strings.Contains(section.Name(), \"keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tfor section, _ := range executable.Sections(kernel.MRAM) {\n\t\tif strings.Contains(section.Name(), \"keep.\") {\n\t\t\tsection.SetAddress(cur_address)\n\t\t\tcur_address += section.Size()\n\t\t}\n\t}\n\n\tcur_address = int64(\n\t\tmath.Ceil(float64(cur_address)/float64(this.min_access_granularity)),\n\t) * this.min_access_granularity\n\n\tthis.linker_constants[\"__sys_used_mram_end\"].SetValue(cur_address)\n\n\tif cur_address >= config_loader.MramOffset()+config_loader.MramSize() {\n\t\terr := errors.New(\"address is larger than the MRAM end address\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *LinkerScript) DumpValues(path string) {\n\tlines := make([]string, 0)\n\n\tfor _, linker_constant := range this.linker_constants {\n\t\tline := fmt.Sprintf(\"%s: %d\", linker_constant.Name(), linker_constant.Value())\n\t\tlines = append(lines, line)\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/liveness_analyzer.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype LivenessAnalyzer struct {\n\tliveness *kernel.Liveness\n\twalker   *parser.Walker\n}\n\nfunc (this *LivenessAnalyzer) Init() {\n\tthis.liveness = new(kernel.Liveness)\n\tthis.liveness.Init()\n\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterExprCallback(expr.PRIMARY, this.WalkPrimaryExpr)\n\tthis.walker.RegisterStmtCallback(stmt.GLOBAL, this.WalkGlobalStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SET, this.WalkSetStmt)\n\tthis.walker.RegisterStmtCallback(stmt.LABEL, this.WalkLabelStmt)\n}\n\nfunc (this *LivenessAnalyzer) Analyze(relocatable *kernel.Relocatable) *kernel.Liveness {\n\tthis.walker.Walk(relocatable.Ast())\n\treturn this.liveness\n}\n\nfunc (this *LivenessAnalyzer) WalkPrimaryExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"expr type is not primary\")\n\t\tpanic(err)\n\t}\n\n\tprimary_expr := expr_.PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\tif token.TokenType() == lexer.IDENTIFIER {\n\t\tthis.liveness.AddUse(token.Attribute())\n\t}\n}\n\nfunc (this *LivenessAnalyzer) WalkGlobalStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.GLOBAL {\n\t\terr := errors.New(\"stmt type is not global\")\n\t\tpanic(err)\n\t}\n\n\tglobal_stmt := stmt_.GlobalStmt()\n\n\tprogram_counter_expr := global_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\tif attribute != \"__sys_used_mram_end\" {\n\t\tthis.liveness.AddGlobalSymbol(attribute)\n\t}\n}\n\nfunc (this *LivenessAnalyzer) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SET {\n\t\terr := errors.New(\"stmt type is not set\")\n\t\tpanic(err)\n\t}\n\n\tset_stmt := stmt_.SetStmt()\n\n\tprogram_counter_expr1 := set_stmt.Expr1().ProgramCounterExpr()\n\tprogram_counter_expr2 := set_stmt.Expr2().ProgramCounterExpr()\n\n\tprimary_expr1 := program_counter_expr1.Expr().PrimaryExpr()\n\tprimary_expr2 := program_counter_expr2.Expr().PrimaryExpr()\n\n\ttoken1 := primary_expr1.Token()\n\ttoken2 := primary_expr2.Token()\n\n\tif token1.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token1 type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tif token2.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token2 type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.liveness.AddDef(token1.Attribute())\n\tthis.liveness.AddUse(token2.Attribute())\n}\n\nfunc (this *LivenessAnalyzer) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LABEL {\n\t\terr := errors.New(\"stmt type is not label\")\n\t\tpanic(err)\n\t}\n\n\tlabel_stmt := stmt_.LabelStmt()\n\n\tprogram_counter_expr := label_stmt.Expr().ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\tif attribute != \"__sys_used_mram_end\" {\n\t\tthis.liveness.AddDef(attribute)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/logic/set_assigner.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype SetAssigner struct {\n\texecutable *kernel.Executable\n\twalker     *parser.Walker\n}\n\nfunc (this *SetAssigner) Init() {\n\tthis.walker = new(parser.Walker)\n\tthis.walker.Init()\n\n\tthis.walker.RegisterStmtCallback(\n\t\tstmt.SECTION_IDENTIFIER_NUMBER,\n\t\tthis.WalkSectionIdentifierNumberStmt,\n\t)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_IDENTIFIER, this.WalkSectionIdentifierStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STACK_SIZES, this.WalkSectionStackSizes)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING_NUMBER, this.WalkSectionStringNumberStmt)\n\tthis.walker.RegisterStmtCallback(stmt.SECTION_STRING, this.WalkSectionStringStmt)\n\tthis.walker.RegisterStmtCallback(stmt.TEXT, this.WalkTextStmt)\n}\n\nfunc (this *SetAssigner) Assign(executable *kernel.Executable) {\n\tthis.executable = executable\n\tthis.walker.Walk(executable.Ast())\n}\n\nfunc (this *SetAssigner) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_number_stmt := stmt_.SectionIdentifierNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_number_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_number_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tsection_identifier_stmt := stmt_.SectionIdentifierStmt()\n\n\tsection_name := this.ConvertSectionName(section_identifier_stmt.Expr1())\n\tname := this.ConvertName(section_identifier_stmt.Expr2())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStackSizes(stmt_ *stmt.Stmt) {\n\tsection_stack_sizes_stmt := stmt_.SectionStackSizesStmt()\n\n\tsection_name := kernel.STACK_SIZES\n\n\tsection_name_expr := section_stack_sizes_stmt.Expr2().SectionNameExpr()\n\ttoken := section_name_expr.Token()\n\ttoken_type := token.TokenType()\n\n\tname := \"\"\n\tif token_type == lexer.ATOMIC {\n\t\tname += \".atomic.\"\n\t} else if token_type == lexer.BSS {\n\t\tname += \".bss.\"\n\t} else if token_type == lexer.DATA {\n\t\tname += \".data.\"\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\tname += \".debug_abbrev.\"\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\tname += \".debug_frame.\"\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\tname += \".debug_info.\"\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\tname += \".debug_line.\"\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\tname += \".debug_loc.\"\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\tname += \".debug_ranges.\"\n\t} else if token_type == lexer.DEBUG_STR {\n\t\tname += \".debug_str.\"\n\t} else if token_type == lexer.DPU_HOST {\n\t\tname += \".dpu_host.\"\n\t} else if token_type == lexer.MRAM {\n\t\tname += \".mram.\"\n\t} else if token_type == lexer.RODATA {\n\t\tname += \".rodata.\"\n\t} else if token_type == lexer.STACK_SIZES {\n\t\tname += \".stack_sizes.\"\n\t} else if token_type == lexer.TEXT {\n\t\tname += \".text.\"\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n\n\tname += this.ConvertName(section_stack_sizes_stmt.Expr3())\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tsection_string_number_stmt := stmt_.SectionStringNumberStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_number_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tsection_string_stmt := stmt_.SectionStringStmt()\n\n\tsection_name := this.ConvertSectionName(section_string_stmt.Expr1())\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tset_stmt := stmt_.SetStmt()\n\n\tprogram_counter_expr1 := set_stmt.Expr1().ProgramCounterExpr()\n\tprogram_counter_expr2 := set_stmt.Expr2().ProgramCounterExpr()\n\n\tprimary_expr1 := program_counter_expr1.Expr().PrimaryExpr()\n\tprimary_expr2 := program_counter_expr2.Expr().PrimaryExpr()\n\n\ttoken1 := primary_expr1.Token()\n\ttoken2 := primary_expr2.Token()\n\n\tattribute1 := token1.Attribute()\n\tattribute2 := token2.Attribute()\n\n\tsrc_label := this.executable.CurSection().Label(attribute1)\n\n\tif this.executable.CurSection().Label(attribute2) == nil {\n\t\tthis.executable.CurSection().AppendLabel(attribute2)\n\t}\n\n\tdst_label := this.executable.CurSection().Label(attribute2)\n\n\tdst_label.SetAddress(src_label.Address())\n}\n\nfunc (this *SetAssigner) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tsection_name := kernel.TEXT\n\tname := \"\"\n\n\tthis.executable.CheckoutSection(section_name, name)\n}\n\nfunc (this *SetAssigner) ConvertSectionName(expr_ *expr.Expr) kernel.SectionName {\n\tsection_name_expr := expr_.SectionNameExpr()\n\ttoken_type := section_name_expr.Token().TokenType()\n\n\tif token_type == lexer.ATOMIC {\n\t\treturn kernel.ATOMIC\n\t} else if token_type == lexer.BSS {\n\t\treturn kernel.BSS\n\t} else if token_type == lexer.DATA {\n\t\treturn kernel.DATA\n\t} else if token_type == lexer.DEBUG_ABBREV {\n\t\treturn kernel.DEBUG_ABBREV\n\t} else if token_type == lexer.DEBUG_FRAME {\n\t\treturn kernel.DEBUG_FRAME\n\t} else if token_type == lexer.DEBUG_INFO {\n\t\treturn kernel.DEBUG_INFO\n\t} else if token_type == lexer.DEBUG_LINE {\n\t\treturn kernel.DEBUG_LINE\n\t} else if token_type == lexer.DEBUG_LOC {\n\t\treturn kernel.DEBUG_LOC\n\t} else if token_type == lexer.DEBUG_RANGES {\n\t\treturn kernel.DEBUG_RANGES\n\t} else if token_type == lexer.DEBUG_STR {\n\t\treturn kernel.DEBUG_STR\n\t} else if token_type == lexer.DPU_HOST {\n\t\treturn kernel.DPU_HOST\n\t} else if token_type == lexer.MRAM {\n\t\treturn kernel.MRAM\n\t} else if token_type == lexer.RODATA {\n\t\treturn kernel.RODATA\n\t} else if token_type == lexer.STACK_SIZES {\n\t\treturn kernel.STACK_SIZES\n\t} else if token_type == lexer.TEXT {\n\t\treturn kernel.TEXT\n\t} else {\n\t\terr := errors.New(\"section name is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *SetAssigner) ConvertName(expr_ *expr.Expr) string {\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\tprimary_expr := program_counter_expr.Expr().PrimaryExpr()\n\ttoken := primary_expr.Token()\n\n\tif token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tattribute := token.Attribute()\n\n\tif attribute[0] != '.' {\n\t\terr := errors.New(\"attribute does not start with .\")\n\t\tpanic(err)\n\t}\n\n\treturn attribute[1:]\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parse_job.go",
    "content": "package linker\n\nimport (\n\t\"fmt\"\n\t\"uPIMulator/src/device/linker/kernel\"\n\t\"uPIMulator/src/device/linker/parser\"\n)\n\ntype ParseJob struct {\n\trelocatable *kernel.Relocatable\n}\n\nfunc (this *ParseJob) Init(relocatable *kernel.Relocatable) {\n\tthis.relocatable = relocatable\n}\n\nfunc (this *ParseJob) Execute() {\n\tfmt.Printf(\"Parsing %s...\\n\", this.relocatable.Path())\n\n\tparser_ := new(parser.Parser)\n\tparser_.Init()\n\n\tast := parser_.Parse(this.relocatable.TokenStream())\n\tthis.relocatable.SetAst(ast)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/ast.go",
    "content": "package parser\n\nimport (\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype Ast struct {\n\tstmts []*stmt.Stmt\n}\n\nfunc (this *Ast) Init(stmts []*stmt.Stmt) {\n\tthis.stmts = stmts\n}\n\nfunc (this *Ast) Length() int {\n\treturn len(this.stmts)\n}\n\nfunc (this *Ast) Get(pos int) *stmt.Stmt {\n\treturn this.stmts[pos]\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/binary_add_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BinaryAddExpr struct {\n\toperand1 *Expr\n\toperand2 *Expr\n}\n\nfunc (this *BinaryAddExpr) Init(operand1 *Expr, operand2 *Expr) {\n\tif operand1.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand1 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tif operand2.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand2 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand1 = operand1\n\tthis.operand2 = operand2\n}\n\nfunc (this *BinaryAddExpr) Operand1() *Expr {\n\treturn this.operand1\n}\n\nfunc (this *BinaryAddExpr) Operand2() *Expr {\n\treturn this.operand2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/binary_sub_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BinarySubExpr struct {\n\toperand1 *Expr\n\toperand2 *Expr\n}\n\nfunc (this *BinarySubExpr) Init(operand1 *Expr, operand2 *Expr) {\n\tif operand1.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand1 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tif operand2.ExprType() != PRIMARY {\n\t\terr := errors.New(\"operand2 is not a primary expr\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand1 = operand1\n\tthis.operand2 = operand2\n}\n\nfunc (this *BinarySubExpr) Operand1() *Expr {\n\treturn this.operand1\n}\n\nfunc (this *BinarySubExpr) Operand2() *Expr {\n\treturn this.operand2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/ci_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype CiOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *CiOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.STOP {\n\t\terr := errors.New(\"token type is not a CI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *CiOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/condition_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype ConditionExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *ConditionExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.TRUE &&\n\t\ttoken_type != lexer.FALSE &&\n\t\ttoken_type != lexer.Z &&\n\t\ttoken_type != lexer.NZ &&\n\t\ttoken_type != lexer.E &&\n\t\ttoken_type != lexer.O &&\n\t\ttoken_type != lexer.PL &&\n\t\ttoken_type != lexer.MI &&\n\t\ttoken_type != lexer.OV &&\n\t\ttoken_type != lexer.NOV &&\n\t\ttoken_type != lexer.C &&\n\t\ttoken_type != lexer.NC &&\n\t\ttoken_type != lexer.SZ &&\n\t\ttoken_type != lexer.SNZ &&\n\t\ttoken_type != lexer.SPL &&\n\t\ttoken_type != lexer.SMI &&\n\t\ttoken_type != lexer.SO &&\n\t\ttoken_type != lexer.SE &&\n\t\ttoken_type != lexer.NC5 &&\n\t\ttoken_type != lexer.NC6 &&\n\t\ttoken_type != lexer.NC7 &&\n\t\ttoken_type != lexer.NC8 &&\n\t\ttoken_type != lexer.NC9 &&\n\t\ttoken_type != lexer.NC10 &&\n\t\ttoken_type != lexer.NC11 &&\n\t\ttoken_type != lexer.NC12 &&\n\t\ttoken_type != lexer.NC13 &&\n\t\ttoken_type != lexer.NC14 &&\n\t\ttoken_type != lexer.MAX &&\n\t\ttoken_type != lexer.NMAX &&\n\t\ttoken_type != lexer.SH32 &&\n\t\ttoken_type != lexer.NSH32 &&\n\t\ttoken_type != lexer.EQ &&\n\t\ttoken_type != lexer.NEQ &&\n\t\ttoken_type != lexer.LTU &&\n\t\ttoken_type != lexer.LEU &&\n\t\ttoken_type != lexer.GTU &&\n\t\ttoken_type != lexer.GEU &&\n\t\ttoken_type != lexer.LTS &&\n\t\ttoken_type != lexer.LES &&\n\t\ttoken_type != lexer.GTS &&\n\t\ttoken_type != lexer.GES &&\n\t\ttoken_type != lexer.XZ &&\n\t\ttoken_type != lexer.XNZ &&\n\t\ttoken_type != lexer.XLEU &&\n\t\ttoken_type != lexer.XGTU &&\n\t\ttoken_type != lexer.XLES &&\n\t\ttoken_type != lexer.XGTS &&\n\t\ttoken_type != lexer.SMALL &&\n\t\ttoken_type != lexer.LARGE {\n\t\terr := errors.New(\"token type is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *ConditionExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/ddci_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype DdciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DdciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.MOVD && token_type != lexer.SWAPD {\n\t\terr := errors.New(\"token type is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DdciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/dma_rri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype DmaRriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DmaRriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LDMA && token_type != lexer.LDMAI && token_type != lexer.SDMA {\n\t\terr := errors.New(\"token type is not a DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DmaRriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/drdici_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype DrdiciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *DrdiciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.DIV_STEP && token_type != lexer.MUL_STEP {\n\t\terr := errors.New(\"token type is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *DrdiciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/endian_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype EndianExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *EndianExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LITTLE &&\n\t\ttoken_type != lexer.BIG {\n\t\terr := errors.New(\"token type is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *EndianExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/expr.go",
    "content": "package expr\n\nimport (\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype ExprType int\n\nconst (\n\tCI_OP_CODE ExprType = iota\n\tDDCI_OP_CODE\n\tDMA_RRI_OP_CODE\n\tDRDICI_OP_CODE\n\tI_OP_CODE\n\tJUMP_OP_CODE\n\tLOAD_OP_CODE\n\tR_OP_CODE\n\tRICI_OP_CODE\n\tRR_OP_CODE\n\tRRI_OP_CODE\n\tRRRI_OP_CODE\n\tSTORE_OP_CODE\n\n\tSUFFIX\n\tCONDITION\n\tENDIAN\n\n\tSECTION_NAME\n\tSECTION_TYPE\n\n\tSYMBOL_TYPE\n\n\tNEGATIVE_NUMBER\n\tPRIMARY\n\tBINARY_ADD\n\tBINARY_SUB\n\tPROGRAM_COUNTER\n\n\tSRC_REG\n)\n\ntype Expr struct {\n\texpr_type ExprType\n\n\tci_op_code_expr      *CiOpCodeExpr\n\tddci_op_code_expr    *DdciOpCodeExpr\n\tdma_rri_op_code_expr *DmaRriOpCodeExpr\n\tdrdici_op_code_expr  *DrdiciOpCodeExpr\n\ti_op_code_expr       *IOpCodeExpr\n\tjump_op_code_expr    *JumpOpCodeExpr\n\tload_op_code_expr    *LoadOpCodeExpr\n\tr_op_code_expr       *ROpCodeExpr\n\trici_op_code_expr    *RiciOpCodeExpr\n\trr_op_code_expr      *RrOpCodeExpr\n\trri_op_code_expr     *RriOpCodeExpr\n\trrri_op_code_expr    *RrriOpCodeExpr\n\tstore_op_code_expr   *StoreOpCodeExpr\n\n\tsuffix_expr    *SuffixExpr\n\tcondition_expr *ConditionExpr\n\tendian_expr    *EndianExpr\n\n\tsection_name_expr *SectionNameExpr\n\tsection_type_expr *SectionTypeExpr\n\n\tsymbol_type_expr *SymbolTypeExpr\n\n\tnegative_number_expr *NegativeNumberExpr\n\tprimary_expr         *PrimaryExpr\n\tbinary_add_expr      *BinaryAddExpr\n\tbinary_sub_expr      *BinarySubExpr\n\tprogram_counter_expr *ProgramCounterExpr\n\n\tsrc_reg_expr *SrcRegExpr\n}\n\nfunc (this *Expr) InitCiOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = CI_OP_CODE\n\n\tthis.ci_op_code_expr = new(CiOpCodeExpr)\n\tthis.ci_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDdciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DDCI_OP_CODE\n\n\tthis.ddci_op_code_expr = new(DdciOpCodeExpr)\n\tthis.ddci_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDmaRriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DMA_RRI_OP_CODE\n\n\tthis.dma_rri_op_code_expr = new(DmaRriOpCodeExpr)\n\tthis.dma_rri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitDrdiciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = DRDICI_OP_CODE\n\n\tthis.drdici_op_code_expr = new(DrdiciOpCodeExpr)\n\tthis.drdici_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitIOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = I_OP_CODE\n\n\tthis.i_op_code_expr = new(IOpCodeExpr)\n\tthis.i_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitJumpOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = JUMP_OP_CODE\n\n\tthis.jump_op_code_expr = new(JumpOpCodeExpr)\n\tthis.jump_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitLoadOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = LOAD_OP_CODE\n\n\tthis.load_op_code_expr = new(LoadOpCodeExpr)\n\tthis.load_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitROpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = R_OP_CODE\n\n\tthis.r_op_code_expr = new(ROpCodeExpr)\n\tthis.r_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRiciOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RICI_OP_CODE\n\n\tthis.rici_op_code_expr = new(RiciOpCodeExpr)\n\tthis.rici_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRrOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RR_OP_CODE\n\n\tthis.rr_op_code_expr = new(RrOpCodeExpr)\n\tthis.rr_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RRI_OP_CODE\n\n\tthis.rri_op_code_expr = new(RriOpCodeExpr)\n\tthis.rri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitRrriOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = RRRI_OP_CODE\n\n\tthis.rrri_op_code_expr = new(RrriOpCodeExpr)\n\tthis.rrri_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitStoreOpCodeExpr(token *lexer.Token) {\n\tthis.expr_type = STORE_OP_CODE\n\n\tthis.store_op_code_expr = new(StoreOpCodeExpr)\n\tthis.store_op_code_expr.Init(token)\n}\n\nfunc (this *Expr) InitSuffixExpr(token *lexer.Token) {\n\tthis.expr_type = SUFFIX\n\n\tthis.suffix_expr = new(SuffixExpr)\n\tthis.suffix_expr.Init(token)\n}\n\nfunc (this *Expr) InitConditionExpr(token *lexer.Token) {\n\tthis.expr_type = CONDITION\n\n\tthis.condition_expr = new(ConditionExpr)\n\tthis.condition_expr.Init(token)\n}\n\nfunc (this *Expr) InitEndianExpr(token *lexer.Token) {\n\tthis.expr_type = ENDIAN\n\n\tthis.endian_expr = new(EndianExpr)\n\tthis.endian_expr.Init(token)\n}\n\nfunc (this *Expr) InitSectionNameExpr(token *lexer.Token) {\n\tthis.expr_type = SECTION_NAME\n\n\tthis.section_name_expr = new(SectionNameExpr)\n\tthis.section_name_expr.Init(token)\n}\n\nfunc (this *Expr) InitSectionTypeExpr(token *lexer.Token) {\n\tthis.expr_type = SECTION_TYPE\n\n\tthis.section_type_expr = new(SectionTypeExpr)\n\tthis.section_type_expr.Init(token)\n}\n\nfunc (this *Expr) InitSymbolTypeExpr(token *lexer.Token) {\n\tthis.expr_type = SYMBOL_TYPE\n\n\tthis.symbol_type_expr = new(SymbolTypeExpr)\n\tthis.symbol_type_expr.Init(token)\n}\n\nfunc (this *Expr) InitNegativeNumberExpr(token *lexer.Token) {\n\tthis.expr_type = NEGATIVE_NUMBER\n\n\tthis.negative_number_expr = new(NegativeNumberExpr)\n\tthis.negative_number_expr.Init(token)\n}\n\nfunc (this *Expr) InitPrimaryExpr(token *lexer.Token) {\n\tthis.expr_type = PRIMARY\n\n\tthis.primary_expr = new(PrimaryExpr)\n\tthis.primary_expr.Init(token)\n}\n\nfunc (this *Expr) InitBinaryAddExpr(operand1 *Expr, operand2 *Expr) {\n\tthis.expr_type = BINARY_ADD\n\n\tthis.binary_add_expr = new(BinaryAddExpr)\n\tthis.binary_add_expr.Init(operand1, operand2)\n}\n\nfunc (this *Expr) InitBinarySubExpr(operand1 *Expr, operand2 *Expr) {\n\tthis.expr_type = BINARY_SUB\n\n\tthis.binary_sub_expr = new(BinarySubExpr)\n\tthis.binary_sub_expr.Init(operand1, operand2)\n}\n\nfunc (this *Expr) InitProgramCounterExpr(expr *Expr) {\n\tthis.expr_type = PROGRAM_COUNTER\n\n\tthis.program_counter_expr = new(ProgramCounterExpr)\n\tthis.program_counter_expr.Init(expr)\n}\n\nfunc (this *Expr) InitSrcRegExpr(token *lexer.Token) {\n\tthis.expr_type = SRC_REG\n\n\tthis.src_reg_expr = new(SrcRegExpr)\n\tthis.src_reg_expr.Init(token)\n}\n\nfunc (this *Expr) ExprType() ExprType {\n\treturn this.expr_type\n}\n\nfunc (this *Expr) CiOpCodeExpr() *CiOpCodeExpr {\n\treturn this.ci_op_code_expr\n}\n\nfunc (this *Expr) DdciOpCodeExpr() *DdciOpCodeExpr {\n\treturn this.ddci_op_code_expr\n}\n\nfunc (this *Expr) DmaRriOpCodeExpr() *DmaRriOpCodeExpr {\n\treturn this.dma_rri_op_code_expr\n}\n\nfunc (this *Expr) DrdiciOpCodeExpr() *DrdiciOpCodeExpr {\n\treturn this.drdici_op_code_expr\n}\n\nfunc (this *Expr) IOpCodeExpr() *IOpCodeExpr {\n\treturn this.i_op_code_expr\n}\n\nfunc (this *Expr) JumpOpCodeExpr() *JumpOpCodeExpr {\n\treturn this.jump_op_code_expr\n}\n\nfunc (this *Expr) LoadOpCodeExpr() *LoadOpCodeExpr {\n\treturn this.load_op_code_expr\n}\n\nfunc (this *Expr) ROpCodeExpr() *ROpCodeExpr {\n\treturn this.r_op_code_expr\n}\n\nfunc (this *Expr) RiciOpCodeExpr() *RiciOpCodeExpr {\n\treturn this.rici_op_code_expr\n}\n\nfunc (this *Expr) RrOpCodeExpr() *RrOpCodeExpr {\n\treturn this.rr_op_code_expr\n}\n\nfunc (this *Expr) RriOpCodeExpr() *RriOpCodeExpr {\n\treturn this.rri_op_code_expr\n}\n\nfunc (this *Expr) RrriOpCodeExpr() *RrriOpCodeExpr {\n\treturn this.rrri_op_code_expr\n}\n\nfunc (this *Expr) StoreOpCodeExpr() *StoreOpCodeExpr {\n\treturn this.store_op_code_expr\n}\n\nfunc (this *Expr) SuffixExpr() *SuffixExpr {\n\treturn this.suffix_expr\n}\n\nfunc (this *Expr) ConditionExpr() *ConditionExpr {\n\treturn this.condition_expr\n}\n\nfunc (this *Expr) EndianExpr() *EndianExpr {\n\treturn this.endian_expr\n}\n\nfunc (this *Expr) SectionNameExpr() *SectionNameExpr {\n\treturn this.section_name_expr\n}\n\nfunc (this *Expr) SectionTypeExpr() *SectionTypeExpr {\n\treturn this.section_type_expr\n}\n\nfunc (this *Expr) SymbolTypeExpr() *SymbolTypeExpr {\n\treturn this.symbol_type_expr\n}\n\nfunc (this *Expr) NegativeNumberExpr() *NegativeNumberExpr {\n\treturn this.negative_number_expr\n}\n\nfunc (this *Expr) PrimaryExpr() *PrimaryExpr {\n\treturn this.primary_expr\n}\n\nfunc (this *Expr) BinaryAddExpr() *BinaryAddExpr {\n\treturn this.binary_add_expr\n}\n\nfunc (this *Expr) BinarySubExpr() *BinarySubExpr {\n\treturn this.binary_sub_expr\n}\n\nfunc (this *Expr) ProgramCounterExpr() *ProgramCounterExpr {\n\treturn this.program_counter_expr\n}\n\nfunc (this *Expr) SrcRegExpr() *SrcRegExpr {\n\treturn this.src_reg_expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/i_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype IOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *IOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.FAULT && token_type != lexer.BKP {\n\t\terr := errors.New(\"token type is not an I op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *IOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/jump_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype JumpOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *JumpOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.JEQ &&\n\t\ttoken_type != lexer.JNEQ &&\n\t\ttoken_type != lexer.JZ &&\n\t\ttoken_type != lexer.JNZ &&\n\t\ttoken_type != lexer.JLTU &&\n\t\ttoken_type != lexer.JGTU &&\n\t\ttoken_type != lexer.JLEU &&\n\t\ttoken_type != lexer.JGEU &&\n\t\ttoken_type != lexer.JLTS &&\n\t\ttoken_type != lexer.JGTS &&\n\t\ttoken_type != lexer.JLES &&\n\t\ttoken_type != lexer.JGES &&\n\t\ttoken_type != lexer.JUMP {\n\t\terr := errors.New(\"token type is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *JumpOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/load_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype LoadOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *LoadOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LBS &&\n\t\ttoken_type != lexer.LBU &&\n\t\ttoken_type != lexer.LD &&\n\t\ttoken_type != lexer.LHS &&\n\t\ttoken_type != lexer.LHU &&\n\t\ttoken_type != lexer.LW {\n\t\terr := errors.New(\"token type is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *LoadOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/negative_number_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype NegativeNumberExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *NegativeNumberExpr) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.POSITIVIE_NUMBER {\n\t\terr := errors.New(\"token type is not positive number\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *NegativeNumberExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/primary_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype PrimaryExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *PrimaryExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.POSITIVIE_NUMBER && token_type != lexer.HEX_NUMBER &&\n\t\ttoken_type != lexer.IDENTIFIER {\n\t\terr := errors.New(\"token type is not positive number, hex number, nor identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *PrimaryExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/program_counter_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype ProgramCounterExpr struct {\n\texpr *Expr\n}\n\nfunc (this *ProgramCounterExpr) Init(expr *Expr) {\n\texpr_type := expr.ExprType()\n\n\tif expr_type != PRIMARY && expr_type != NEGATIVE_NUMBER && expr_type != BINARY_ADD &&\n\t\texpr_type != BINARY_SUB {\n\t\terr := errors.New(\"expr type is not primary, negative number, binary add, nor binary sub\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr\n}\n\nfunc (this *ProgramCounterExpr) Expr() *Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/r_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype ROpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *ROpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.TIME && token_type != lexer.NOP {\n\t\terr := errors.New(\"token type is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *ROpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/rici_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype RiciOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RiciOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ACQUIRE &&\n\t\ttoken_type != lexer.RELEASE &&\n\t\ttoken_type != lexer.BOOT &&\n\t\ttoken_type != lexer.RESUME {\n\t\terr := errors.New(\"token type is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RiciOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/rr_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype RrOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RrOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.CAO &&\n\t\ttoken_type != lexer.CLO &&\n\t\ttoken_type != lexer.CLS &&\n\t\ttoken_type != lexer.CLZ &&\n\t\ttoken_type != lexer.EXTSB &&\n\t\ttoken_type != lexer.EXTSH &&\n\t\ttoken_type != lexer.EXTUB &&\n\t\ttoken_type != lexer.EXTUH &&\n\t\ttoken_type != lexer.SATS &&\n\t\ttoken_type != lexer.TIME_CFG &&\n\t\ttoken_type != lexer.MOVE &&\n\t\ttoken_type != lexer.NEG &&\n\t\ttoken_type != lexer.NOT {\n\t\terr := errors.New(\"token type is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RrOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/rri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype RriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ADD &&\n\t\ttoken_type != lexer.ADDC &&\n\t\ttoken_type != lexer.AND &&\n\t\ttoken_type != lexer.ANDN &&\n\t\ttoken_type != lexer.ASR &&\n\t\ttoken_type != lexer.CMPB4 &&\n\t\ttoken_type != lexer.LSL &&\n\t\ttoken_type != lexer.LSL1 &&\n\t\ttoken_type != lexer.LSL1X &&\n\t\ttoken_type != lexer.LSLX &&\n\t\ttoken_type != lexer.LSR &&\n\t\ttoken_type != lexer.LSR1 &&\n\t\ttoken_type != lexer.LSR1X &&\n\t\ttoken_type != lexer.LSRX &&\n\t\ttoken_type != lexer.MUL_SH_SH &&\n\t\ttoken_type != lexer.MUL_SH_SL &&\n\t\ttoken_type != lexer.MUL_SH_UH &&\n\t\ttoken_type != lexer.MUL_SH_UL &&\n\t\ttoken_type != lexer.MUL_SL_SH &&\n\t\ttoken_type != lexer.MUL_SL_SL &&\n\t\ttoken_type != lexer.MUL_SL_UH &&\n\t\ttoken_type != lexer.MUL_SL_UL &&\n\t\ttoken_type != lexer.MUL_UH_UH &&\n\t\ttoken_type != lexer.MUL_UH_UL &&\n\t\ttoken_type != lexer.MUL_UL_UH &&\n\t\ttoken_type != lexer.MUL_UL_UL &&\n\t\ttoken_type != lexer.NAND &&\n\t\ttoken_type != lexer.NOR &&\n\t\ttoken_type != lexer.NXOR &&\n\t\ttoken_type != lexer.OR &&\n\t\ttoken_type != lexer.ORN &&\n\t\ttoken_type != lexer.ROL &&\n\t\ttoken_type != lexer.ROR &&\n\t\ttoken_type != lexer.RSUB &&\n\t\ttoken_type != lexer.RSUBC &&\n\t\ttoken_type != lexer.SUB &&\n\t\ttoken_type != lexer.SUBC &&\n\t\ttoken_type != lexer.XOR &&\n\t\ttoken_type != lexer.CALL {\n\t\terr := errors.New(\"token type is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/rrri_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype RrriOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *RrriOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.LSL_ADD &&\n\t\ttoken_type != lexer.LSL_SUB &&\n\t\ttoken_type != lexer.LSR_ADD &&\n\t\ttoken_type != lexer.ROL_ADD {\n\t\terr := errors.New(\"token type is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *RrriOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/section_name_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype SectionNameExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SectionNameExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.ATOMIC &&\n\t\ttoken_type != lexer.BSS &&\n\t\ttoken_type != lexer.DATA &&\n\t\ttoken_type != lexer.DEBUG_ABBREV &&\n\t\ttoken_type != lexer.DEBUG_FRAME &&\n\t\ttoken_type != lexer.DEBUG_INFO &&\n\t\ttoken_type != lexer.DEBUG_LINE &&\n\t\ttoken_type != lexer.DEBUG_LOC &&\n\t\ttoken_type != lexer.DEBUG_RANGES &&\n\t\ttoken_type != lexer.DEBUG_STR &&\n\t\ttoken_type != lexer.DPU_HOST &&\n\t\ttoken_type != lexer.MRAM &&\n\t\ttoken_type != lexer.RODATA &&\n\t\ttoken_type != lexer.STACK_SIZES &&\n\t\ttoken_type != lexer.TEXT {\n\t\terr := errors.New(\"token type is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SectionNameExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/section_type_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype SectionTypeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SectionTypeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.PROGBITS && token_type != lexer.NOBITS {\n\t\terr := errors.New(\"token type is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SectionTypeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/src_reg_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype SrcRegExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SrcRegExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.GP_REG &&\n\t\ttoken_type != lexer.ZERO_REG &&\n\t\ttoken_type != lexer.ONE &&\n\t\ttoken_type != lexer.ID &&\n\t\ttoken_type != lexer.ID2 &&\n\t\ttoken_type != lexer.ID4 &&\n\t\ttoken_type != lexer.ID8 &&\n\t\ttoken_type != lexer.LNEG &&\n\t\ttoken_type != lexer.MNEG {\n\t\terr := errors.New(\"token type is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SrcRegExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/store_op_code_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype StoreOpCodeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *StoreOpCodeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.SB &&\n\t\ttoken_type != lexer.SB_ID &&\n\t\ttoken_type != lexer.SD &&\n\t\ttoken_type != lexer.SD_ID &&\n\t\ttoken_type != lexer.SH &&\n\t\ttoken_type != lexer.SH_ID &&\n\t\ttoken_type != lexer.SW &&\n\t\ttoken_type != lexer.SW_ID {\n\t\terr := errors.New(\"token type is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *StoreOpCodeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/suffix_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype SuffixExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SuffixExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.S && token_type != lexer.U {\n\t\terr := errors.New(\"token type is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SuffixExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/expr/symbol_type.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype SymbolTypeExpr struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *SymbolTypeExpr) Init(token *lexer.Token) {\n\ttoken_type := token.TokenType()\n\n\tif token_type != lexer.FUNCTION && token_type != lexer.OBJECT {\n\t\terr := errors.New(\"token type is not a symbol type\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *SymbolTypeExpr) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/parser.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype Parser struct {\n\tstack *Stack\n\ttable *Table\n}\n\nfunc (this *Parser) Init() {\n\tthis.stack = new(Stack)\n\tthis.stack.Init()\n\n\tthis.table = new(Table)\n\tthis.table.Init(this.stack)\n\n\tthis.RegisterAccessExpr()\n\tthis.RegisterConcatExpr()\n\tthis.RegisterBinaryAddExpr()\n\tthis.RegisterBinarySubExpr()\n\tthis.RegisterCiOpCodeExpr()\n\tthis.RegisterConditionExpr()\n\tthis.RegisterDdciOpCodeExpr()\n\tthis.RegisterDmaRriOpCodeExpr()\n\tthis.RegisterDrdiciOpCodeExpr()\n\tthis.RegisterEndianExpr()\n\tthis.RegisterIOpCodeExpr()\n\tthis.RegisterJumpOpCodeExpr()\n\tthis.RegisterLoadOpCodeExpr()\n\tthis.RegisterNegativeNumberExpr()\n\tthis.RegisterPrimaryExpr()\n\tthis.RegisterProgramCounterExpr()\n\tthis.RegisterROpCodeExpr()\n\tthis.RegisterRiciOpCodeExpr()\n\tthis.RegisterRrOpCodeExpr()\n\tthis.RegisterRriOpCodeExpr()\n\tthis.RegisterRrriOpCodeExpr()\n\tthis.RegisterSectionNameExpr()\n\tthis.RegisterSectionTypeExpr()\n\tthis.RegisterSrcRegExpr()\n\tthis.RegisterStoreOpCodeExpr()\n\tthis.RegisterSuffixExpr()\n\tthis.RegisterSymbolTypeExpr()\n\n\tthis.RegisterAddrsigStmt()\n\tthis.RegisterAddrsigSymStmt()\n\tthis.RegisterAsciiStmt()\n\tthis.RegisterAscizStmt()\n\tthis.RegisterByteStmt()\n\tthis.RegisterCfiDefCfaOffsetStmt()\n\tthis.RegisterCfiEndprocStmt()\n\tthis.RegisterCfiOffsetStmt()\n\tthis.RegisterCfiSectionsStmt()\n\tthis.RegisterCfiStartprocStmt()\n\tthis.RegisterFileNumberStmt()\n\tthis.RegisterFileStringStmt()\n\tthis.RegisterGlobalStmt()\n\tthis.RegisterLocIsStmtStmt()\n\tthis.RegisterLocNumberStmt()\n\tthis.RegisterLocPrologueEndStmt()\n\tthis.RegisterLongProgramCounterStmt()\n\tthis.RegisterLongSectionNameStmt()\n\tthis.RegisterP2AlignStmt()\n\tthis.RegisterQuadStmt()\n\tthis.RegisterSectionIdentifierNumberStmt()\n\tthis.RegisterSectionIdentifierStmt()\n\tthis.RegisterSectionStackSizesStmt()\n\tthis.RegisterSectionStringNumberStmt()\n\tthis.RegisterSectionStringStmt()\n\tthis.RegisterSetStmt()\n\tthis.RegisterShortStmt()\n\tthis.RegisterSizeStmt()\n\tthis.RegisterTextStmt()\n\tthis.RegisterTypeStmt()\n\tthis.RegisterWeakStmt()\n\tthis.RegisterZeroDoubleNumberStmt()\n\tthis.RegisterZeroSingleNumberStmt()\n\n\tthis.RegisterCiStmt()\n\tthis.RegisterDdciStmt()\n\tthis.RegisterDmaRriStmt()\n\tthis.RegisterDrdiciStmt()\n\tthis.RegisterEdriStmt()\n\tthis.RegisterEriiStmt()\n\tthis.RegisterErirStmt()\n\tthis.RegisterErriStmt()\n\tthis.RegisterIStmt()\n\tthis.RegisterRciStmt()\n\tthis.RegisterRiciStmt()\n\tthis.RegisterRirciStmt()\n\tthis.RegisterRircStmt()\n\tthis.RegisterRirStmt()\n\tthis.RegisterRrciStmt()\n\tthis.RegisterRrcStmt()\n\tthis.RegisterRriciStmt()\n\tthis.RegisterRricStmt()\n\tthis.RegisterRriStmt()\n\tthis.RegisterRrrciStmt()\n\tthis.RegisterRrrcStmt()\n\tthis.RegisterRrriciStmt()\n\tthis.RegisterRrriStmt()\n\tthis.RegisterRrrStmt()\n\tthis.RegisterRrStmt()\n\tthis.RegisterRStmt()\n\n\tthis.RegisterSErriStmt()\n\tthis.RegisterSRciStmt()\n\tthis.RegisterSRirciStmt()\n\tthis.RegisterSRrciStmt()\n\tthis.RegisterSRrcStmt()\n\tthis.RegisterSRriciStmt()\n\tthis.RegisterSRricStmt()\n\tthis.RegisterSRriStmt()\n\tthis.RegisterSRrrciStmt()\n\tthis.RegisterSRrrcStmt()\n\tthis.RegisterSRrriciStmt()\n\tthis.RegisterSRrriStmt()\n\tthis.RegisterSRrrStmt()\n\tthis.RegisterSRrStmt()\n\tthis.RegisterSRStmt()\n\n\tthis.RegisterNopStmt()\n\tthis.RegisterBkpStmt()\n\tthis.RegisterBootRiStmt()\n\tthis.RegisterCallRiStmt()\n\tthis.RegisterCallRrStmt()\n\tthis.RegisterDivStepDrdiStmt()\n\tthis.RegisterJeqRiiStmt()\n\tthis.RegisterJeqRriStmt()\n\tthis.RegisterJnzRiStmt()\n\tthis.RegisterJumpIStmt()\n\tthis.RegisterJumpRStmt()\n\tthis.RegisterLbsRriStmt()\n\tthis.RegisterLbsSRriStmt()\n\tthis.RegisterLdDriStmt()\n\tthis.RegisterMovdDdStmt()\n\tthis.RegisterMoveRiciStmt()\n\tthis.RegisterMoveRiStmt()\n\tthis.RegisterMoveSRiciStmt()\n\tthis.RegisterMoveSRiStmt()\n\tthis.RegisterSbIdRiiStmt()\n\tthis.RegisterSbIdRiStmt()\n\tthis.RegisterSbRirStmt()\n\tthis.RegisterSdRidStmt()\n\tthis.RegisterStopStmt()\n\tthis.RegisterTimeCfgRStmt()\n\n\tthis.RegisterLabelStmt()\n}\n\nfunc (this *Parser) Parse(token_stream *lexer.TokenStream) *Ast {\n\tfor pos := 0; pos < token_stream.Length(); pos++ {\n\t\ttoken := token_stream.Get(pos)\n\n\t\tthis.ReduceExpr(token)\n\n\t\tif token.TokenType() != lexer.NEW_LINE {\n\t\t\tstack_item := new(StackItem)\n\t\t\tstack_item.InitToken(token)\n\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tthis.ReduceStmt(token)\n\n\t\t\tif !this.stack.AreStmts() {\n\t\t\t\terr := errors.New(\"stack are not stmts\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n\n\tif !this.stack.CanAccept() {\n\t\terr := errors.New(\"stack cannot be accepted\")\n\t\tpanic(err)\n\t}\n\n\treturn this.stack.Accept()\n}\n\nfunc (this *Parser) ReduceExpr(token *lexer.Token) {\n\tfor {\n\t\treducible_expr_rule, stack_items := this.table.FindReducibleExprRule(token)\n\n\t\tif reducible_expr_rule != nil {\n\t\t\tstack_item := reducible_expr_rule.Reduce(stack_items, token)\n\n\t\t\tthis.stack.Pop(len(stack_items))\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nfunc (this *Parser) ReduceStmt(token *lexer.Token) {\n\tfor {\n\t\treducible_stmt_rule, stack_items := this.table.FindReducibleStmtRule(token)\n\n\t\tif reducible_stmt_rule != nil {\n\t\t\tstack_item := reducible_stmt_rule.Reduce(stack_items, token)\n\n\t\t\tthis.stack.Pop(len(stack_items))\n\t\t\tthis.stack.Push(stack_item)\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nfunc (this *Parser) RegisterAccessExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.IDENTIFIER &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken1 := stack_items[0].Token()\n\t\ttoken2 := stack_items[1].Token()\n\n\t\tattribute := token1.Attribute() + token2.Attribute()\n\n\t\ttoken := new(lexer.Token)\n\t\ttoken.Init(lexer.IDENTIFIER, attribute)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitToken(token)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterConcatExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.NEGATIVE_NUMBER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[1].Expr()\n\n\t\tnegative_number_expr := operand2.NegativeNumberExpr()\n\t\ttoken := negative_number_expr.Token()\n\n\t\tprimary_expr := new(expr.Expr)\n\t\tprimary_expr.InitPrimaryExpr(token)\n\n\t\tbinary_sub_expr := new(expr.Expr)\n\t\tbinary_sub_expr.InitBinarySubExpr(operand1, primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_sub_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterBinaryAddExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PLUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PRIMARY {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[2].Expr()\n\n\t\tbinary_add_expr := new(expr.Expr)\n\t\tbinary_add_expr.InitBinaryAddExpr(operand1, operand2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_add_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterBinarySubExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PRIMARY {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\toperand1 := stack_items[0].Expr()\n\t\toperand2 := stack_items[2].Expr()\n\n\t\tbinary_sub_expr := new(expr.Expr)\n\t\tbinary_sub_expr.InitBinarySubExpr(operand1, operand2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(binary_sub_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterCiOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.STOP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tci_op_code_expr := new(expr.Expr)\n\t\tci_op_code_expr.InitCiOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(ci_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDdciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.MOVD || token_type == lexer.SWAPD {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tddci_op_code_expr := new(expr.Expr)\n\t\tddci_op_code_expr.InitDdciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(ddci_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDmaRriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LDMA || token_type == lexer.LDMAI || token_type == lexer.SDMA {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tdma_rri_op_code_expr := new(expr.Expr)\n\t\tdma_rri_op_code_expr.InitDmaRriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(dma_rri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterDrdiciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.DIV_STEP || token_type == lexer.MUL_STEP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tdrdici_op_code_expr := new(expr.Expr)\n\t\tdrdici_op_code_expr.InitDrdiciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(drdici_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterConditionExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.TRUE ||\n\t\t\t\t\ttoken_type == lexer.FALSE ||\n\t\t\t\t\ttoken_type == lexer.Z ||\n\t\t\t\t\ttoken_type == lexer.NZ ||\n\t\t\t\t\ttoken_type == lexer.E ||\n\t\t\t\t\ttoken_type == lexer.O ||\n\t\t\t\t\ttoken_type == lexer.PL ||\n\t\t\t\t\ttoken_type == lexer.MI ||\n\t\t\t\t\ttoken_type == lexer.OV ||\n\t\t\t\t\ttoken_type == lexer.NOV ||\n\t\t\t\t\ttoken_type == lexer.C ||\n\t\t\t\t\ttoken_type == lexer.NC ||\n\t\t\t\t\ttoken_type == lexer.SZ ||\n\t\t\t\t\ttoken_type == lexer.SNZ ||\n\t\t\t\t\ttoken_type == lexer.SPL ||\n\t\t\t\t\ttoken_type == lexer.SMI ||\n\t\t\t\t\ttoken_type == lexer.SO ||\n\t\t\t\t\ttoken_type == lexer.SE ||\n\t\t\t\t\ttoken_type == lexer.NC5 ||\n\t\t\t\t\ttoken_type == lexer.NC5 ||\n\t\t\t\t\ttoken_type == lexer.NC6 ||\n\t\t\t\t\ttoken_type == lexer.NC7 ||\n\t\t\t\t\ttoken_type == lexer.NC8 ||\n\t\t\t\t\ttoken_type == lexer.NC9 ||\n\t\t\t\t\ttoken_type == lexer.NC10 ||\n\t\t\t\t\ttoken_type == lexer.NC11 ||\n\t\t\t\t\ttoken_type == lexer.NC12 ||\n\t\t\t\t\ttoken_type == lexer.NC13 ||\n\t\t\t\t\ttoken_type == lexer.NC14 ||\n\t\t\t\t\ttoken_type == lexer.MAX ||\n\t\t\t\t\ttoken_type == lexer.NMAX ||\n\t\t\t\t\ttoken_type == lexer.SH32 ||\n\t\t\t\t\ttoken_type == lexer.NSH32 ||\n\t\t\t\t\ttoken_type == lexer.EQ ||\n\t\t\t\t\ttoken_type == lexer.NEQ ||\n\t\t\t\t\ttoken_type == lexer.LTU ||\n\t\t\t\t\ttoken_type == lexer.LEU ||\n\t\t\t\t\ttoken_type == lexer.GTU ||\n\t\t\t\t\ttoken_type == lexer.GEU ||\n\t\t\t\t\ttoken_type == lexer.LTS ||\n\t\t\t\t\ttoken_type == lexer.LES ||\n\t\t\t\t\ttoken_type == lexer.GTS ||\n\t\t\t\t\ttoken_type == lexer.GES ||\n\t\t\t\t\ttoken_type == lexer.XZ ||\n\t\t\t\t\ttoken_type == lexer.XNZ ||\n\t\t\t\t\ttoken_type == lexer.XLEU ||\n\t\t\t\t\ttoken_type == lexer.XGTU ||\n\t\t\t\t\ttoken_type == lexer.XLES ||\n\t\t\t\t\ttoken_type == lexer.XGTS ||\n\t\t\t\t\ttoken_type == lexer.SMALL ||\n\t\t\t\t\ttoken_type == lexer.LARGE {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tcondition_expr := new(expr.Expr)\n\t\tcondition_expr.InitConditionExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(condition_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterEndianExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LITTLE || token_type == lexer.BIG {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tendian_expr := new(expr.Expr)\n\t\tendian_expr.InitEndianExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(endian_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterIOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.FAULT || token_type == lexer.BKP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\ti_op_code_expr := new(expr.Expr)\n\t\ti_op_code_expr.InitIOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(i_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.JEQ ||\n\t\t\t\t\ttoken_type == lexer.JNEQ ||\n\t\t\t\t\ttoken_type == lexer.JZ ||\n\t\t\t\t\ttoken_type == lexer.JNZ ||\n\t\t\t\t\ttoken_type == lexer.JLTU ||\n\t\t\t\t\ttoken_type == lexer.JGTU ||\n\t\t\t\t\ttoken_type == lexer.JLEU ||\n\t\t\t\t\ttoken_type == lexer.JGEU ||\n\t\t\t\t\ttoken_type == lexer.JLTS ||\n\t\t\t\t\ttoken_type == lexer.JGTS ||\n\t\t\t\t\ttoken_type == lexer.JLES ||\n\t\t\t\t\ttoken_type == lexer.JGES ||\n\t\t\t\t\ttoken_type == lexer.JUMP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tjump_op_code_expr := new(expr.Expr)\n\t\tjump_op_code_expr.InitJumpOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(jump_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterLoadOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LBS ||\n\t\t\t\t\ttoken_type == lexer.LBU ||\n\t\t\t\t\ttoken_type == lexer.LD ||\n\t\t\t\t\ttoken_type == lexer.LHS ||\n\t\t\t\t\ttoken_type == lexer.LHU ||\n\t\t\t\t\ttoken_type == lexer.LW {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tload_op_code_expr := new(expr.Expr)\n\t\tload_op_code_expr.InitLoadOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(load_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterNegativeNumberExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.POSITIVIE_NUMBER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tnegativer_number_expr := new(expr.Expr)\n\t\tnegativer_number_expr.InitNegativeNumberExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(negativer_number_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExpr() {\n\tprecedence := map[lexer.TokenType]bool{lexer.IDENTIFIER: true}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.POSITIVIE_NUMBER || token_type == lexer.HEX_NUMBER || token_type == lexer.IDENTIFIER {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.Expr)\n\t\tprimary_expr.InitPrimaryExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(primary_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterProgramCounterExpr() {\n\tprecedence := map[lexer.TokenType]bool{lexer.PLUS: true, lexer.MINUS: true}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR {\n\t\t\t\texpr_type := stack_items[0].Expr().ExprType()\n\n\t\t\t\tif expr_type == expr.PRIMARY ||\n\t\t\t\t\texpr_type == expr.NEGATIVE_NUMBER ||\n\t\t\t\t\texpr_type == expr.BINARY_ADD ||\n\t\t\t\t\texpr_type == expr.BINARY_SUB {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[0].Expr()\n\n\t\tprogram_counter_expr := new(expr.Expr)\n\t\tprogram_counter_expr.InitProgramCounterExpr(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(program_counter_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterROpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.TIME || token_type == lexer.NOP {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tr_op_code_expr := new(expr.Expr)\n\t\tr_op_code_expr.InitROpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(r_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRiciOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ACQUIRE ||\n\t\t\t\t\ttoken_type == lexer.RELEASE ||\n\t\t\t\t\ttoken_type == lexer.BOOT ||\n\t\t\t\t\ttoken_type == lexer.RESUME {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trici_op_code_expr := new(expr.Expr)\n\t\trici_op_code_expr.InitRiciOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rici_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRrOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.CAO ||\n\t\t\t\t\ttoken_type == lexer.CLO ||\n\t\t\t\t\ttoken_type == lexer.CLS ||\n\t\t\t\t\ttoken_type == lexer.CLZ ||\n\t\t\t\t\ttoken_type == lexer.EXTSB ||\n\t\t\t\t\ttoken_type == lexer.EXTSH ||\n\t\t\t\t\ttoken_type == lexer.EXTUB ||\n\t\t\t\t\ttoken_type == lexer.EXTUH ||\n\t\t\t\t\ttoken_type == lexer.SATS ||\n\t\t\t\t\ttoken_type == lexer.TIME_CFG ||\n\t\t\t\t\ttoken_type == lexer.MOVE ||\n\t\t\t\t\ttoken_type == lexer.NEG ||\n\t\t\t\t\ttoken_type == lexer.NOT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trr_op_code_expr := new(expr.Expr)\n\t\trr_op_code_expr.InitRrOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rr_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ADD ||\n\t\t\t\t\ttoken_type == lexer.ADDC ||\n\t\t\t\t\ttoken_type == lexer.AND ||\n\t\t\t\t\ttoken_type == lexer.ANDN ||\n\t\t\t\t\ttoken_type == lexer.ASR ||\n\t\t\t\t\ttoken_type == lexer.CMPB4 ||\n\t\t\t\t\ttoken_type == lexer.LSL ||\n\t\t\t\t\ttoken_type == lexer.LSL1 ||\n\t\t\t\t\ttoken_type == lexer.LSL1X ||\n\t\t\t\t\ttoken_type == lexer.LSLX ||\n\t\t\t\t\ttoken_type == lexer.LSR ||\n\t\t\t\t\ttoken_type == lexer.LSR1 ||\n\t\t\t\t\ttoken_type == lexer.LSR1X ||\n\t\t\t\t\ttoken_type == lexer.LSRX ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_SH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_SL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SH_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_SH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_SL ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_SL_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_UH_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_UH_UL ||\n\t\t\t\t\ttoken_type == lexer.MUL_UL_UH ||\n\t\t\t\t\ttoken_type == lexer.MUL_UL_UL ||\n\t\t\t\t\ttoken_type == lexer.NAND ||\n\t\t\t\t\ttoken_type == lexer.NOR ||\n\t\t\t\t\ttoken_type == lexer.NXOR ||\n\t\t\t\t\ttoken_type == lexer.OR ||\n\t\t\t\t\ttoken_type == lexer.ORN ||\n\t\t\t\t\ttoken_type == lexer.ROL ||\n\t\t\t\t\ttoken_type == lexer.ROR ||\n\t\t\t\t\ttoken_type == lexer.RSUB ||\n\t\t\t\t\ttoken_type == lexer.RSUBC ||\n\t\t\t\t\ttoken_type == lexer.SUB ||\n\t\t\t\t\ttoken_type == lexer.SUBC ||\n\t\t\t\t\ttoken_type == lexer.XOR ||\n\t\t\t\t\ttoken_type == lexer.CALL {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trri_op_code_expr := new(expr.Expr)\n\t\trri_op_code_expr.InitRriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.LSL_ADD ||\n\t\t\t\t\ttoken_type == lexer.LSL_SUB ||\n\t\t\t\t\ttoken_type == lexer.LSR_ADD ||\n\t\t\t\t\ttoken_type == lexer.ROL_ADD {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\trrri_op_code_expr := new(expr.Expr)\n\t\trrri_op_code_expr.InitRrriOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(rrri_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterStoreOpCodeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.SB ||\n\t\t\t\t\ttoken_type == lexer.SB_ID ||\n\t\t\t\t\ttoken_type == lexer.SD ||\n\t\t\t\t\ttoken_type == lexer.SD_ID ||\n\t\t\t\t\ttoken_type == lexer.SH ||\n\t\t\t\t\ttoken_type == lexer.SH_ID ||\n\t\t\t\t\ttoken_type == lexer.SW ||\n\t\t\t\t\ttoken_type == lexer.SW_ID {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tstore_op_code_expr := new(expr.Expr)\n\t\tstore_op_code_expr.InitStoreOpCodeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(store_op_code_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSuffixExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.S || token_type == lexer.U {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsuffix_expr := new(expr.Expr)\n\t\tsuffix_expr.InitSuffixExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(suffix_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionNameExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.ATOMIC ||\n\t\t\t\t\ttoken_type == lexer.BSS ||\n\t\t\t\t\ttoken_type == lexer.DATA ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_ABBREV ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_FRAME ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_INFO ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_LINE ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_LOC ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_RANGES ||\n\t\t\t\t\ttoken_type == lexer.DEBUG_STR ||\n\t\t\t\t\ttoken_type == lexer.DPU_HOST ||\n\t\t\t\t\ttoken_type == lexer.MRAM ||\n\t\t\t\t\ttoken_type == lexer.RODATA ||\n\t\t\t\t\ttoken_type == lexer.STACK_SIZES ||\n\t\t\t\t\ttoken_type == lexer.TEXT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsection_name_expr := new(expr.Expr)\n\t\tsection_name_expr.InitSectionNameExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(section_name_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionTypeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.PROGBITS || token_type == lexer.NOBITS {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsection_type_expr := new(expr.Expr)\n\t\tsection_type_expr.InitSectionTypeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(section_type_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSrcRegExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.GP_REG ||\n\t\t\t\t\ttoken_type == lexer.ZERO_REG ||\n\t\t\t\t\ttoken_type == lexer.ONE ||\n\t\t\t\t\ttoken_type == lexer.ID ||\n\t\t\t\t\ttoken_type == lexer.ID2 ||\n\t\t\t\t\ttoken_type == lexer.ID4 ||\n\t\t\t\t\ttoken_type == lexer.ID8 ||\n\t\t\t\t\ttoken_type == lexer.LNEG ||\n\t\t\t\t\ttoken_type == lexer.MNEG {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsrc_reg_expr := new(expr.Expr)\n\t\tsrc_reg_expr.InitSrcRegExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(src_reg_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterSymbolTypeExpr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN {\n\t\t\t\ttoken_type := stack_items[0].Token().TokenType()\n\n\t\t\t\tif token_type == lexer.FUNCTION || token_type == lexer.OBJECT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tsymbol_type_expr := new(expr.Expr)\n\t\tsymbol_type_expr.InitSymbolTypeExpr(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(symbol_type_expr)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddExprRule(rule)\n}\n\nfunc (this *Parser) RegisterAddrsigStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ADDRSIG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\taddrsig_stmt := new(stmt.Stmt)\n\t\taddrsig_stmt.InitAddrsigStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(addrsig_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAddrsigSymStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ADDRSIG_SYM &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\taddrsig_sym_stmt := new(stmt.Stmt)\n\t\taddrsig_sym_stmt.InitAddrsigSymStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(addrsig_sym_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAsciiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ASCII &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tascii_stmt := new(stmt.Stmt)\n\t\tascii_stmt.InitAsciiStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ascii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterAscizStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ASCIZ &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tasciz_stmt := new(stmt.Stmt)\n\t\tasciz_stmt.InitAscizStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(asciz_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterByteStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.BYTE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tbyte_stmt := new(stmt.Stmt)\n\t\tbyte_stmt.InitByteStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(byte_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiDefCfaOffsetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_DEF_CFA_OFFSET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tcfi_def_cfa_offset_stmt := new(stmt.Stmt)\n\t\tcfi_def_cfa_offset_stmt.InitCfiDefCfaOffsetStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_def_cfa_offset_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiEndprocStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_ENDPROC {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcfi_endproc_stmt := new(stmt.Stmt)\n\t\tcfi_endproc_stmt.InitCfiEndprocStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_endproc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiOffsetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_OFFSET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tcfi_offset_stmt := new(stmt.Stmt)\n\t\tcfi_offset_stmt.InitCfiOffsetStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_offset_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiSectionsStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_SECTIONS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tcfi_sections_stmt := new(stmt.Stmt)\n\t\tcfi_sections_stmt.InitCfiSectionsStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_sections_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCfiStartprocStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CFI_STARTPROC {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcfi_startproc_stmt := new(stmt.Stmt)\n\t\tcfi_startproc_stmt.InitCfiStartprocStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(cfi_startproc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterFileNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.FILE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\t\ttoken1 := stack_items[2].Token()\n\t\ttoken2 := stack_items[3].Token()\n\n\t\tfile_number_stmt := new(stmt.Stmt)\n\t\tfile_number_stmt.InitFileNumberStmt(expr_, token1, token2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(file_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterFileStringStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.FILE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[1].Token()\n\n\t\tfile_string_stmt := new(stmt.Stmt)\n\t\tfile_string_stmt.InitFileStringStmt(token)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(file_string_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterGlobalStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.GLOBL &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tglobal_stmt := new(stmt.Stmt)\n\t\tglobal_stmt.InitGlobalStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(global_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocIsStmtStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.IS_STMT &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\t\texpr4 := stack_items[5].Expr()\n\n\t\tloc_is_stmt_stmt := new(stmt.Stmt)\n\t\tloc_is_stmt_stmt.InitLocIsStmtStmt(expr1, expr2, expr3, expr4)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_is_stmt_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\n\t\tloc_number_stmt := new(stmt.Stmt)\n\t\tloc_number_stmt.InitLocNumberStmt(expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLocPrologueEndStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LOC &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.PROLOGUE_END {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\texpr3 := stack_items[3].Expr()\n\n\t\tloc_prologue_end_stmt := new(stmt.Stmt)\n\t\tloc_prologue_end_stmt.InitLocPrologueEndStmt(expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(loc_prologue_end_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLongProgramCounterStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LONG &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tlong_program_counter_stmt := new(stmt.Stmt)\n\t\tlong_program_counter_stmt.InitLongProgramCounterStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(long_program_counter_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLongSectionNameStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LONG &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tlong_section_name_stmt := new(stmt.Stmt)\n\t\tlong_section_name_stmt.InitLongSectionNameStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(long_section_name_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterP2AlignStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.P2ALIGN &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tp2align_stmt := new(stmt.Stmt)\n\t\tp2align_stmt.InitP2AlignStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(p2align_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterQuadStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.QUAD &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tquad_stmt := new(stmt.Stmt)\n\t\tquad_stmt.InitQuadStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(quad_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionIdentifierNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\ttoken := stack_items[4].Token()\n\t\texpr3 := stack_items[6].Expr()\n\t\texpr4 := stack_items[8].Expr()\n\n\t\tsection_identifier_number_stmt := new(stmt.Stmt)\n\t\tsection_identifier_number_stmt.InitSectionIdentifierNumberStmt(\n\t\t\texpr1,\n\t\t\texpr2,\n\t\t\ttoken,\n\t\t\texpr3,\n\t\t\texpr4,\n\t\t)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_identifier_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionIdentifierStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SECTION_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[2].Expr()\n\t\ttoken := stack_items[4].Token()\n\t\texpr3 := stack_items[6].Expr()\n\n\t\tsection_identifier_stmt := new(stmt.Stmt)\n\t\tsection_identifier_stmt.InitSectionIdentifierStmt(expr1, expr2, token, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_identifier_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStackSizesStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[3].Token()\n\t\texpr1 := stack_items[5].Expr()\n\t\texpr2 := stack_items[7].Expr()\n\t\texpr3 := stack_items[8].Expr()\n\n\t\tsection_stack_sizes_stmt := new(stmt.Stmt)\n\t\tsection_stack_sizes_stmt.InitSectionStackSizesStmt(token, expr1, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_stack_sizes_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStringNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\ttoken := stack_items[3].Token()\n\t\texpr2 := stack_items[5].Expr()\n\t\texpr3 := stack_items[7].Expr()\n\n\t\tsection_string_number_stmt := new(stmt.Stmt)\n\t\tsection_string_number_stmt.InitSectionStringNumberStmt(expr1, token, expr2, expr3)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_string_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSectionStringStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SECTION &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SECTION_NAME &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.STRING &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SECTION_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\ttoken := stack_items[3].Token()\n\t\texpr2 := stack_items[5].Expr()\n\n\t\tsection_string_stmt := new(stmt.Stmt)\n\t\tsection_string_stmt.InitSectionStringStmt(expr1, token, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(section_string_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSetStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SET &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tset_stmt := new(stmt.Stmt)\n\t\tset_stmt.InitSetStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(set_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterShortStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SHORT &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tshort_stmt := new(stmt.Stmt)\n\t\tshort_stmt.InitShortStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(short_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSizeStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SIZE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tsize_stmt := new(stmt.Stmt)\n\t\tsize_stmt.InitSizeStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(size_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTextStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.SECTION_NAME {\n\t\t\t\texpr_ := stack_items[0].Expr()\n\t\t\t\tif expr_.SectionNameExpr().Token().TokenType() == lexer.TEXT {\n\t\t\t\t\treturn true\n\t\t\t\t} else {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttext_stmt := new(stmt.Stmt)\n\t\ttext_stmt.InitTextStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(text_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.TYPE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SYMBOL_TYPE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\ttype_stmt := new(stmt.Stmt)\n\t\ttype_stmt.InitTypeStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(type_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterWeakStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.WEAK &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tweak_stmt := new(stmt.Stmt)\n\t\tweak_stmt.InitWeakStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(weak_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterZeroDoubleNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ZERO_DIRECTIVE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr1 := stack_items[1].Expr()\n\t\texpr2 := stack_items[3].Expr()\n\n\t\tzero_double_number_stmt := new(stmt.Stmt)\n\t\tzero_double_number_stmt.InitZeroDoubleNumberStmt(expr1, expr2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(zero_double_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterZeroSingleNumberStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.ZERO_DIRECTIVE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[1].Expr()\n\n\t\tzero_single_number_stmt := new(stmt.Stmt)\n\t\tzero_single_number_stmt.InitZeroSingleNumberStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(zero_single_number_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.CI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tcondition := stack_items[1].Expr()\n\t\tpc := stack_items[3].Expr()\n\n\t\tci_stmt := new(stmt.Stmt)\n\t\tci_stmt.InitCiStmt(op_code, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDdciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DDCI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tdb := stack_items[3].Token()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\tddci_stmt := new(stmt.Stmt)\n\t\tddci_stmt.InitDdciStmt(op_code, dc, db, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ddci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDmaRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DMA_RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\trb := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tdma_rri_stmt := new(stmt.Stmt)\n\t\tdma_rri_stmt.InitDmaRriStmt(op_code, ra, rb, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(dma_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDrdiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 12 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DRDICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[10].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[10].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[11].StackItemType() == EXPR &&\n\t\t\t\tstack_items[11].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\t\timm := stack_items[7].Expr()\n\t\tcondition := stack_items[9].Expr()\n\t\tpc := stack_items[11].Expr()\n\n\t\tdrdici_stmt := new(stmt.Stmt)\n\t\tdrdici_stmt.InitDrdiciStmt(op_code, dc, ra, db, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(drdici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEdriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tdc := stack_items[3].Token()\n\t\tra := stack_items[5].Expr()\n\t\toff := stack_items[7].Expr()\n\n\t\tedri_stmt := new(stmt.Stmt)\n\t\tedri_stmt.InitEdriStmt(op_code, endian, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(edri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEridStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\tdb := stack_items[7].Token()\n\n\t\tedri_stmt := new(stmt.Stmt)\n\t\tedri_stmt.InitEridStmt(op_code, endian, ra, off, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(edri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterEriiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\n\t\terii_stmt := new(stmt.Stmt)\n\t\terii_stmt.InitEriiStmt(op_code, endian, ra, off, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterErirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\t\trb := stack_items[7].Expr()\n\n\t\terir_stmt := new(stmt.Stmt)\n\t\terir_stmt.InitErirStmt(op_code, endian, ra, off, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterErriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tendian := stack_items[1].Expr()\n\t\trc := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\toff := stack_items[7].Expr()\n\n\t\terri_stmt := new(stmt.Stmt)\n\t\terri_stmt.InitErriStmt(op_code, endian, rc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(erri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterIStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.I_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\timm := stack_items[1].Expr()\n\n\t\ti_stmt := new(stmt.Stmt)\n\t\ti_stmt.InitIStmt(op_code, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(i_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tcondition := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\trci_stmt := new(stmt.Stmt)\n\t\trci_stmt.InitRciStmt(op_code, rc, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\trici_stmt := new(stmt.Stmt)\n\t\trici_stmt.InitRiciStmt(op_code, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRirciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trirci_stmt := new(stmt.Stmt)\n\t\trirci_stmt.InitRirciStmt(op_code, rc, imm, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rirci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRircStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trirc_stmt := new(stmt.Stmt)\n\t\trirc_stmt.InitRircStmt(op_code, rc, imm, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rirc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tra := stack_items[5].Expr()\n\n\t\trir_stmt := new(stmt.Stmt)\n\t\trir_stmt.InitRirStmt(op_code, rc, imm, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\trrci_stmt := new(stmt.Stmt)\n\t\trrci_stmt.InitRrciStmt(op_code, rc, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\n\t\trrc_stmt := new(stmt.Stmt)\n\t\trrc_stmt.InitRrcStmt(op_code, rc, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trrici_stmt := new(stmt.Stmt)\n\t\trrici_stmt.InitRriciStmt(op_code, rc, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRricStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trric_stmt := new(stmt.Stmt)\n\t\trric_stmt.InitRricStmt(op_code, rc, ra, imm, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rric_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\n\t\trri_stmt := new(stmt.Stmt)\n\t\trri_stmt.InitRriStmt(op_code, rc, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 10 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[9].Expr()\n\n\t\trrrci_stmt := new(stmt.Stmt)\n\t\trrrci_stmt.InitRrrciStmt(op_code, rc, ra, rb, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\trrrc_stmt := new(stmt.Stmt)\n\t\trrrc_stmt.InitRrrcStmt(op_code, rc, ra, rb, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 12 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[8].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[8].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[9].StackItemType() == EXPR &&\n\t\t\t\tstack_items[9].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[10].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[10].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[11].StackItemType() == EXPR &&\n\t\t\t\tstack_items[11].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\t\tcondition := stack_items[9].Expr()\n\t\tpc := stack_items[11].Expr()\n\n\t\trrrici_stmt := new(stmt.Stmt)\n\t\trrrici_stmt.InitRrriciStmt(op_code, rc, ra, rb, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\t\timm := stack_items[7].Expr()\n\n\t\trrri_stmt := new(stmt.Stmt)\n\t\trrri_stmt.InitRrriStmt(op_code, rc, ra, rb, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\n\t\trrr_stmt := new(stmt.Stmt)\n\t\trrr_stmt.InitRrrStmt(op_code, rc, ra, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rrr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\n\t\trr_stmt := new(stmt.Stmt)\n\t\trr_stmt.InitRrStmt(op_code, rc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\n\t\tr_stmt := new(stmt.Stmt)\n\t\tr_stmt.InitRStmt(op_code, rc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSErriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].Expr().ExprType() == expr.ENDIAN &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tendian := stack_items[2].Expr()\n\t\tdc := stack_items[4].Token()\n\t\tra := stack_items[6].Expr()\n\t\toff := stack_items[8].Expr()\n\n\t\ts_erri_stmt := new(stmt.Stmt)\n\t\ts_erri_stmt.InitSErriStmt(op_code, suffix, endian, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_erri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tcondition := stack_items[4].Expr()\n\t\tpc := stack_items[6].Expr()\n\n\t\ts_rci_stmt := new(stmt.Stmt)\n\t\ts_rci_stmt.InitSRciStmt(op_code, suffix, dc, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRirciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tra := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rirci_stmt := new(stmt.Stmt)\n\t\ts_rirci_stmt.InitSRirciStmt(op_code, suffix, dc, imm, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rirci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRircStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tra := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\n\t\ts_rirc_stmt := new(stmt.Stmt)\n\t\ts_rirc_stmt.InitSRircStmt(op_code, suffix, dc, imm, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rirc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\t\tpc := stack_items[8].Expr()\n\n\t\ts_rrci_stmt := new(stmt.Stmt)\n\t\ts_rrci_stmt.InitSRrciStmt(op_code, suffix, dc, ra, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\n\t\ts_rrc_stmt := new(stmt.Stmt)\n\t\ts_rrc_stmt.InitSRrcStmt(op_code, suffix, dc, ra, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rrici_stmt := new(stmt.Stmt)\n\t\ts_rrici_stmt.InitSRriciStmt(op_code, suffix, dc, ra, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRricStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\t\tcondition := stack_items[8].Expr()\n\n\t\ts_rric_stmt := new(stmt.Stmt)\n\t\ts_rric_stmt.InitSRricStmt(op_code, suffix, dc, ra, imm, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rric_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\timm := stack_items[6].Expr()\n\n\t\ts_rri_stmt := new(stmt.Stmt)\n\t\ts_rri_stmt.InitSRriStmt(op_code, suffix, dc, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 11 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\tcondition := stack_items[7].Expr()\n\t\tpc := stack_items[10].Expr()\n\n\t\ts_rrrci_stmt := new(stmt.Stmt)\n\t\ts_rrrci_stmt.InitSRrrciStmt(op_code, suffix, dc, ra, rb, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrci_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrcStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.CONDITION {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\tcondition := stack_items[7].Expr()\n\n\t\ts_rrrc_stmt := new(stmt.Stmt)\n\t\ts_rrrc_stmt.InitSRrrcStmt(op_code, suffix, dc, ra, rb, condition)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrc_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrriciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 13 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[9].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[9].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[10].StackItemType() == EXPR &&\n\t\t\t\tstack_items[10].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[11].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[11].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[12].StackItemType() == EXPR &&\n\t\t\t\tstack_items[12].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\timm := stack_items[8].Expr()\n\t\tcondition := stack_items[10].Expr()\n\t\tpc := stack_items[12].Expr()\n\n\t\ts_rrrici_stmt := new(stmt.Stmt)\n\t\ts_rrrici_stmt.InitSRrriciStmt(op_code, suffix, dc, ra, rb, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrrici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\t\timm := stack_items[8].Expr()\n\n\t\ts_rrri_stmt := new(stmt.Stmt)\n\t\ts_rrri_stmt.InitSRrriStmt(op_code, suffix, dc, ra, rb, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\trb := stack_items[6].Expr()\n\n\t\ts_rrr_stmt := new(stmt.Stmt)\n\t\ts_rrr_stmt.InitSRrrStmt(op_code, suffix, dc, ra, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rrr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\n\t\ts_rr_stmt := new(stmt.Stmt)\n\t\ts_rr_stmt.InitSRrStmt(op_code, suffix, dc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\n\t\ts_r_stmt := new(stmt.Stmt)\n\t\ts_r_stmt.InitSRStmt(op_code, suffix, dc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(s_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterNopStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.R_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\tif op_code.ROpCodeExpr().Token().TokenType() != lexer.NOP {\n\t\t\terr := errors.New(\"op code is not NOP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tnop_stmt := new(stmt.Stmt)\n\t\tnop_stmt.InitNopStmt(op_code)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(nop_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterBkpStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.I_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\tif op_code.IOpCodeExpr().Token().TokenType() != lexer.BKP {\n\t\t\terr := errors.New(\"op code is not BKP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbkp_stmt := new(stmt.Stmt)\n\t\tbkp_stmt.InitBkpStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(bkp_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterBootRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RiciOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.BOOT && token_type != lexer.RESUME {\n\t\t\terr := errors.New(\"op code is not BOOT nor RESUME\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tboot_ri_stmt := new(stmt.Stmt)\n\t\tboot_ri_stmt.InitBootRiStmt(op_code, ra, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(boot_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCallRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RriOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.CALL {\n\t\t\terr := errors.New(\"op code is not CALL\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tcall_ri_stmt := new(stmt.Stmt)\n\t\tcall_ri_stmt.InitCallRiStmt(rc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(call_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterCallRrStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RRI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RriOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.CALL {\n\t\t\terr := errors.New(\"op code is not CALL\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tcall_rr_stmt := new(stmt.Stmt)\n\t\tcall_rr_stmt.InitCallRrStmt(rc, ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(call_rr_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterDivStepDrdiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DRDICI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\t\tpc := stack_items[7].Expr()\n\n\t\tdiv_step_drdi_stmt := new(stmt.Stmt)\n\t\tdiv_step_drdi_stmt.InitDivStepDrdiStmt(op_code, dc, ra, db, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(div_step_drdi_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJeqRiiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tjeq_rii_stmt := new(stmt.Stmt)\n\t\tjeq_rii_stmt.InitJeqRiiStmt(op_code, ra, imm, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jeq_rii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJeqRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\trb := stack_items[3].Expr()\n\t\tpc := stack_items[5].Expr()\n\n\t\tjeq_rri_stmt := new(stmt.Stmt)\n\t\tjeq_rri_stmt.InitJeqRriStmt(op_code, ra, rb, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jeq_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJnzRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\tpc := stack_items[3].Expr()\n\n\t\tjnz_ri_stmt := new(stmt.Stmt)\n\t\tjnz_ri_stmt.InitJnzRiStmt(op_code, ra, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jnz_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpIStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tpc := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.JumpOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.JUMP {\n\t\t\terr := errors.New(\"op code is not JUMP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tjump_i_stmt := new(stmt.Stmt)\n\t\tjump_i_stmt.InitJumpIStmt(pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jump_i_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterJumpRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.JUMP_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.JumpOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.JUMP {\n\t\t\terr := errors.New(\"op code is not JUMP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tjump_r_stmt := new(stmt.Stmt)\n\t\tjump_r_stmt.InitJumpRStmt(ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(jump_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLbsRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\n\t\tlbs_rri_stmt := new(stmt.Stmt)\n\t\tlbs_rri_stmt.InitLbsRriStmt(op_code, rc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(lbs_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLbsSRriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\tra := stack_items[4].Expr()\n\t\toff := stack_items[6].Expr()\n\n\t\tlbs_s_rri_stmt := new(stmt.Stmt)\n\t\tlbs_s_rri_stmt.InitLbsSRriStmt(op_code, suffix, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(lbs_s_rri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLdDriStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.LOAD_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tra := stack_items[3].Expr()\n\t\toff := stack_items[5].Expr()\n\n\t\tld_dri_stmt := new(stmt.Stmt)\n\t\tld_dri_stmt.InitLdDriStmt(op_code, dc, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(ld_dri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMovdDdStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.DDCI_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tdc := stack_items[1].Token()\n\t\tdb := stack_items[3].Token()\n\n\t\tmovd_dd_stmt := new(stmt.Stmt)\n\t\tmovd_dd_stmt.InitMovdDdStmt(op_code, dc, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(movd_dd_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 8 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[6].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[6].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[7].StackItemType() == EXPR &&\n\t\t\t\tstack_items[7].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\t\tcondition := stack_items[5].Expr()\n\t\tpc := stack_items[7].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_rici_stmt := new(stmt.Stmt)\n\t\tmove_rici_stmt.InitMoveRiciStmt(rc, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\trc := stack_items[1].Expr()\n\t\timm := stack_items[3].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_ri_stmt := new(stmt.Stmt)\n\t\tmove_ri_stmt.InitMoveRiStmt(rc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveSRiciStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 9 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[6].StackItemType() == EXPR &&\n\t\t\t\tstack_items[6].Expr().ExprType() == expr.CONDITION &&\n\t\t\t\tstack_items[7].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[7].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[8].StackItemType() == EXPR &&\n\t\t\t\tstack_items[8].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\t\tcondition := stack_items[6].Expr()\n\t\tpc := stack_items[8].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_s_rici_stmt := new(stmt.Stmt)\n\t\tmove_s_rici_stmt.InitMoveSRiciStmt(suffix, dc, imm, condition, pc)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_s_rici_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterMoveSRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SUFFIX &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.PAIR_REG &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[4].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tsuffix := stack_items[1].Expr()\n\t\tdc := stack_items[2].Token()\n\t\timm := stack_items[4].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.MOVE {\n\t\t\terr := errors.New(\"op code is not MOVE\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tmove_s_ri_stmt := new(stmt.Stmt)\n\t\tmove_s_ri_stmt.InitMoveSRiStmt(suffix, dc, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(move_s_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbIdRiiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\timm := stack_items[5].Expr()\n\n\t\tsb_id_rii_stmt := new(stmt.Stmt)\n\t\tsb_id_rii_stmt.InitSbIdRiiStmt(op_code, ra, off, imm)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_id_rii_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbIdRiStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\n\t\tsb_id_ri_stmt := new(stmt.Stmt)\n\t\tsb_id_ri_stmt.InitSbIdRiStmt(op_code, ra, off)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_id_ri_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSbRirStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\trb := stack_items[5].Expr()\n\n\t\tsb_rir_stmt := new(stmt.Stmt)\n\t\tsb_rir_stmt.InitSbRirStmt(op_code, ra, off, rb)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sb_rir_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterSdRidStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 6 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.STORE_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.PAIR_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\t\toff := stack_items[3].Expr()\n\t\tdb := stack_items[5].Token()\n\n\t\tsd_rid_stmt := new(stmt.Stmt)\n\t\tsd_rid_stmt.InitSdRidStmt(op_code, ra, off, db)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(sd_rid_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterStopStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.CI_OP_CODE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\n\t\ttoken_type := op_code.CiOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.STOP {\n\t\t\terr := errors.New(\"op code is not STOP\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tstop_stmt := new(stmt.Stmt)\n\t\tstop_stmt.InitStopStmt()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stop_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterTimeCfgRStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.RR_OP_CODE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.SRC_REG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\top_code := stack_items[0].Expr()\n\t\tra := stack_items[1].Expr()\n\n\t\ttoken_type := op_code.RrOpCodeExpr().Token().TokenType()\n\t\tif token_type != lexer.TIME_CFG {\n\t\t\terr := errors.New(\"op code is not TIME_CFG\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\ttime_cfg_r_stmt := new(stmt.Stmt)\n\t\ttime_cfg_r_stmt.InitTimeCfgRStmt(ra)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(time_cfg_r_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n\nfunc (this *Parser) RegisterLabelStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.PROGRAM_COUNTER &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.COLON {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[0].Expr()\n\n\t\tlabel_stmt := new(stmt.Stmt)\n\t\tlabel_stmt.InitLabelStmt(expr_)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(label_stmt)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddStmtRule(rule)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/rule.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype Reducible func([]*StackItem) bool\ntype Reduce func([]*StackItem) *StackItem\n\ntype Rule struct {\n\tprecedence map[lexer.TokenType]bool\n\n\treducible Reducible\n\treduce    Reduce\n}\n\nfunc (this *Rule) Init(precedence map[lexer.TokenType]bool, reducible Reducible, reduce Reduce) {\n\tthis.precedence = precedence\n\tthis.reducible = reducible\n\tthis.reduce = reduce\n}\n\nfunc (this *Rule) IsReducible(stack_items []*StackItem, token *lexer.Token) bool {\n\tif _, found := this.precedence[token.TokenType()]; found {\n\t\treturn false\n\t} else {\n\t\treturn this.reducible(stack_items)\n\t}\n}\n\nfunc (this *Rule) Reduce(stack_items []*StackItem, token *lexer.Token) *StackItem {\n\tif !this.IsReducible(stack_items, token) {\n\t\terr := errors.New(\"stack items are not reducible\")\n\t\tpanic(err)\n\t}\n\n\treturn this.reduce(stack_items)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stack.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype Stack struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *Stack) Init() {\n\tthis.stack_items = make([]*StackItem, 0)\n}\n\nfunc (this *Stack) Push(stack_item *StackItem) {\n\tthis.stack_items = append(this.stack_items, stack_item)\n}\n\nfunc (this *Stack) Pop(num int) {\n\tthis.stack_items = this.stack_items[:len(this.stack_items)-num]\n}\n\nfunc (this *Stack) Front(num int) []*StackItem {\n\tstack_items := make([]*StackItem, 0)\n\tfor i := 0; i < num; i++ {\n\t\tstack_item := this.stack_items[len(this.stack_items)-num+i]\n\t\tstack_items = append(stack_items, stack_item)\n\t}\n\treturn stack_items\n}\n\nfunc (this *Stack) NonStmtLength() int {\n\tnon_stmt_length := 0\n\tfor i := len(this.stack_items) - 1; i >= 0; i-- {\n\t\tstack_item := this.stack_items[i]\n\n\t\tif stack_item.StackItemType() != STMT {\n\t\t\tnon_stmt_length++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn non_stmt_length\n}\n\nfunc (this *Stack) AreStmts() bool {\n\tfor _, stack_item := range this.stack_items {\n\t\tif stack_item.StackItemType() == STMT {\n\t\t\tcontinue\n\t\t} else {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *Stack) CanAccept() bool {\n\tfor i, stack_item := range this.stack_items {\n\t\tif i < len(this.stack_items)-1 {\n\t\t\tif stack_item.StackItemType() == STMT {\n\t\t\t\tcontinue\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t} else {\n\t\t\tif stack_item.StackItemType() == TOKEN && stack_item.Token().TokenType() == lexer.END_OF_FILE {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Stack) Accept() *Ast {\n\tif !this.CanAccept() {\n\t\terr := errors.New(\"stack cannot be accepted\")\n\t\tpanic(err)\n\t}\n\n\tstmts := make([]*stmt.Stmt, 0)\n\tfor i := 0; i < len(this.stack_items)-1; i++ {\n\t\tstmts = append(stmts, this.stack_items[i].Stmt())\n\t}\n\n\tast := new(Ast)\n\tast.Init(stmts)\n\n\treturn ast\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stack_item.go",
    "content": "package parser\n\nimport (\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype StackItemType int\n\nconst (\n\tTOKEN StackItemType = iota\n\tEXPR\n\tSTMT\n)\n\ntype StackItem struct {\n\tstack_item_type StackItemType\n\n\ttoken *lexer.Token\n\texpr  *expr.Expr\n\tstmt  *stmt.Stmt\n}\n\nfunc (this *StackItem) InitToken(token *lexer.Token) {\n\tthis.stack_item_type = TOKEN\n\n\tthis.token = token\n}\n\nfunc (this *StackItem) InitExpr(expr *expr.Expr) {\n\tthis.stack_item_type = EXPR\n\n\tthis.expr = expr\n}\n\nfunc (this *StackItem) InitStmt(stmt *stmt.Stmt) {\n\tthis.stack_item_type = STMT\n\n\tthis.stmt = stmt\n}\n\nfunc (this *StackItem) StackItemType() StackItemType {\n\treturn this.stack_item_type\n}\n\nfunc (this *StackItem) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *StackItem) Expr() *expr.Expr {\n\treturn this.expr\n}\n\nfunc (this *StackItem) Stmt() *stmt.Stmt {\n\treturn this.stmt\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/addrsig_stmt.go",
    "content": "package directive\n\ntype AddrsigStmt struct {\n}\n\nfunc (this *AddrsigStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/addrsig_sym_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype AddrsigSymStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *AddrsigSymStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *AddrsigSymStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/ascii_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype AsciiStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *AsciiStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *AsciiStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/asciz_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype AscizStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *AscizStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *AscizStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/byte_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ByteStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ByteStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ByteStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/cfi_def_cfa_offset_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CfiDefCfaOffsetStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *CfiDefCfaOffsetStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *CfiDefCfaOffsetStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/cfi_endproc.go",
    "content": "package directive\n\ntype CfiEndprocStmt struct {\n}\n\nfunc (this *CfiEndprocStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/cfi_offset_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CfiOffsetStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *CfiOffsetStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *CfiOffsetStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *CfiOffsetStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/cfi_sections_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CfiSectionsStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *CfiSectionsStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *CfiSectionsStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/cfi_startproc_stmt.go",
    "content": "package directive\n\ntype CfiStartprocStmt struct {\n}\n\nfunc (this *CfiStartprocStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/file_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype FileNumberStmt struct {\n\texpr   *expr.Expr\n\ttoken1 *lexer.Token\n\ttoken2 *lexer.Token\n}\n\nfunc (this *FileNumberStmt) Init(expr_ *expr.Expr, token1 *lexer.Token, token2 *lexer.Token) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token1.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token1 is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif token2.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token2 is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n\tthis.token1 = token1\n\tthis.token2 = token2\n}\n\nfunc (this *FileNumberStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n\nfunc (this *FileNumberStmt) Token1() *lexer.Token {\n\treturn this.token1\n}\n\nfunc (this *FileNumberStmt) Token2() *lexer.Token {\n\treturn this.token2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/file_string_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype FileStringStmt struct {\n\ttoken *lexer.Token\n}\n\nfunc (this *FileStringStmt) Init(token *lexer.Token) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n}\n\nfunc (this *FileStringStmt) Token() *lexer.Token {\n\treturn this.token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/global_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype GlobalStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *GlobalStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *GlobalStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/loc_is_stmt_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LocIsStmtStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n\texpr4 *expr.Expr\n}\n\nfunc (this *LocIsStmtStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr4.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr4 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n\tthis.expr4 = expr4\n}\n\nfunc (this *LocIsStmtStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocIsStmtStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocIsStmtStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n\nfunc (this *LocIsStmtStmt) Expr4() *expr.Expr {\n\treturn this.expr4\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/loc_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LocNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *LocNumberStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *LocNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/loc_prologue_end_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LocPrologueEndStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *LocPrologueEndStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *LocPrologueEndStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *LocPrologueEndStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *LocPrologueEndStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/long_program_counter.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LongProgramCounterStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LongProgramCounterStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LongProgramCounterStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/long_section_name_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LongSectionNameStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LongSectionNameStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LongSectionNameStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/p2_align_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype P2AlignStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *P2AlignStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *P2AlignStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/quad_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype QuadStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *QuadStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *QuadStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/section_identifier_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SectionIdentifierNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\ttoken *lexer.Token\n\texpr3 *expr.Expr\n\texpr4 *expr.Expr\n}\n\nfunc (this *SectionIdentifierNumberStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr3 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr4.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr4 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.token = token\n\tthis.expr3 = expr3\n\tthis.expr4 = expr4\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionIdentifierNumberStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n\nfunc (this *SectionIdentifierNumberStmt) Expr4() *expr.Expr {\n\treturn this.expr4\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/section_identifier_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SectionIdentifierStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\ttoken *lexer.Token\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionIdentifierStmt) Init(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr3 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.token = token\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionIdentifierStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionIdentifierStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionIdentifierStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionIdentifierStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/section_stack_sizes_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SectionStackSizesStmt struct {\n\ttoken *lexer.Token\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionStackSizesStmt) Init(\n\ttoken *lexer.Token,\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr1.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr1 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr2 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.token = token\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionStackSizesStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStackSizesStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStackSizesStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionStackSizesStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/section_string_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SectionStringNumberStmt struct {\n\texpr1 *expr.Expr\n\ttoken *lexer.Token\n\texpr2 *expr.Expr\n\texpr3 *expr.Expr\n}\n\nfunc (this *SectionStringNumberStmt) Init(\n\texpr1 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr2 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tif expr3.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr3 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.token = token\n\tthis.expr2 = expr2\n\tthis.expr3 = expr3\n}\n\nfunc (this *SectionStringNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStringNumberStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStringNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n\nfunc (this *SectionStringNumberStmt) Expr3() *expr.Expr {\n\treturn this.expr3\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/section_string_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SectionStringStmt struct {\n\texpr1 *expr.Expr\n\ttoken *lexer.Token\n\texpr2 *expr.Expr\n}\n\nfunc (this *SectionStringStmt) Init(expr1 *expr.Expr, token *lexer.Token, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.SECTION_NAME {\n\t\terr := errors.New(\"expr1 is not a section name\")\n\t\tpanic(err)\n\t}\n\n\tif token.TokenType() != lexer.STRING {\n\t\terr := errors.New(\"token is not a string\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SECTION_TYPE {\n\t\terr := errors.New(\"expr2 is not a section type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.token = token\n\tthis.expr2 = expr2\n}\n\nfunc (this *SectionStringStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SectionStringStmt) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *SectionStringStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/set_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SetStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *SetStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr1 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr2 is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *SetStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SetStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/short_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ShortStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ShortStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ShortStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/size_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SizeStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *SizeStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *SizeStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *SizeStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/text_stmt.go",
    "content": "package directive\n\ntype TextStmt struct {\n}\n\nfunc (this *TextStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/type_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype TypeStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *TypeStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.SYMBOL_TYPE {\n\t\terr := errors.New(\"expr is not a symbol type\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr2\n}\n\nfunc (this *TypeStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *TypeStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/weak_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype WeakStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *WeakStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *WeakStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/zero_double_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ZeroDoubleNumberStmt struct {\n\texpr1 *expr.Expr\n\texpr2 *expr.Expr\n}\n\nfunc (this *ZeroDoubleNumberStmt) Init(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tif expr1.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif expr2.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr1 = expr1\n\tthis.expr2 = expr2\n}\n\nfunc (this *ZeroDoubleNumberStmt) Expr1() *expr.Expr {\n\treturn this.expr1\n}\n\nfunc (this *ZeroDoubleNumberStmt) Expr2() *expr.Expr {\n\treturn this.expr2\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/directive/zero_single_number_stmt.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ZeroSingleNumberStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ZeroSingleNumberStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *ZeroSingleNumberStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/ci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CiStmt struct {\n\top_code   *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *CiStmt) Init(op_code *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.CI_OP_CODE {\n\t\terr := errors.New(\"op code is not a CI op code\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *CiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *CiStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *CiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/ddci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype DdciStmt struct {\n\top_code   *expr.Expr\n\tdc        *lexer.Token\n\tdb        *lexer.Token\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *DdciStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tdb *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DDCI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.db = db\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *DdciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DdciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DdciStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DdciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *DdciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/dma_rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype DmaRriStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *DmaRriStmt) Init(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.DMA_RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DMA_RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *DmaRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DmaRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DmaRriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *DmaRriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/drdici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype DrdiciStmt struct {\n\top_code   *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tdb        *lexer.Token\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *DrdiciStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DRDICI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *DrdiciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DrdiciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DrdiciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DrdiciStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DrdiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *DrdiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *DrdiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/edri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype EdriStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *EdriStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *EdriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EdriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EdriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *EdriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EdriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/erid_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype EridStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\tdb      *lexer.Token\n}\n\nfunc (this *EridStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.db = db\n}\n\nfunc (this *EridStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EridStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EridStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EridStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *EridStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/erii_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype EriiStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *EriiStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.imm = imm\n}\n\nfunc (this *EriiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *EriiStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *EriiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *EriiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *EriiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/erir_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ErirStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *ErirStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\trb *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.ra = ra\n\tthis.off = off\n\tthis.rb = rb\n}\n\nfunc (this *ErirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *ErirStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *ErirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *ErirStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *ErirStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/erri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype ErriStmt struct {\n\top_code *expr.Expr\n\tendian  *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *ErriStmt) Init(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.endian = endian\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *ErriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *ErriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *ErriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *ErriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *ErriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/i_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype IStmt struct {\n\top_code *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *IStmt) Init(op_code *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.I_OP_CODE {\n\t\terr := errors.New(\"op code is not an I op code\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.imm = imm\n}\n\nfunc (this *IStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *IStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/nop_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype NopStmt struct {\n\top_code *expr.Expr\n}\n\nfunc (this *NopStmt) Init(op_code *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n}\n\nfunc (this *NopStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/r_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n}\n\nfunc (this *RStmt) Init(op_code *expr.Expr, rc *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n}\n\nfunc (this *RStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RciStmt) Init(op_code *expr.Expr, rc *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RiciStmt struct {\n\top_code   *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RiciStmt) Init(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RICI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RiciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RiciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rir_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RirStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\timm     *expr.Expr\n\tra      *expr.Expr\n}\n\nfunc (this *RirStmt) Init(op_code *expr.Expr, rc *expr.Expr, imm *expr.Expr, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n}\n\nfunc (this *RirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RirStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RirStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rirc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RircStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RircStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *RircStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RircStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RircStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RircStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RircStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rirci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RirciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RirciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RirciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RirciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RirciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RirciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RirciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RirciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n}\n\nfunc (this *RrStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *RrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrcStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RrcStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, condition *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *RrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrcStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *RriStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *RriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rric_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RricStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RricStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n}\n\nfunc (this *RricStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RricStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RricStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RricStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RricStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RriciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RriciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RriciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrrStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *RrrStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, rb *expr.Expr) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *RrrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrrcStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *RrrcStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n}\n\nfunc (this *RrrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrcStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrcStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrrciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrrciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrrciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrrciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *RrriStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *RrriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/rrrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype RrriciStmt struct {\n\top_code   *expr.Expr\n\trc        *expr.Expr\n\tra        *expr.Expr\n\trb        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *RrriciStmt) Init(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a progrcm counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *RrriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *RrriciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *RrriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *RrriciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *RrriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *RrriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *RrriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_erri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SErriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tendian  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *SErriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif endian.ExprType() != expr.ENDIAN {\n\t\terr := errors.New(\"endian is not an endian\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.endian = endian\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *SErriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SErriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SErriStmt) Endian() *expr.Expr {\n\treturn this.endian\n}\n\nfunc (this *SErriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SErriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SErriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_r_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n}\n\nfunc (this *SRStmt) Init(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n}\n\nfunc (this *SRStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.R_OP_CODE {\n\t\terr := errors.New(\"op code is not an R op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rirc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRircStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRircStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *SRircStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRircStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRircStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRircStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRircStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRircStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rirci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRirciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRirciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRirciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRirciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRirciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRirciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRirciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRirciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRirciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n}\n\nfunc (this *SRrStmt) Init(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token, ra *expr.Expr) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n}\n\nfunc (this *SRrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrcStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRrcStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.condition = condition\n}\n\nfunc (this *SRrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrcStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrcStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RR_OP_CODE {\n\t\terr := errors.New(\"op code is not an RR op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SRriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *SRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rric_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRricStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRricStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n}\n\nfunc (this *SRricStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRricStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRricStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRricStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRricStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRricStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRriciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRriciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRriciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRriciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrr_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrrStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *SRrrStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n}\n\nfunc (this *SRrrStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrrc_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrrcStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n}\n\nfunc (this *SRrrcStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n}\n\nfunc (this *SRrrcStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrcStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrcStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrcStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrcStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrrcStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrrci_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrrciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrrciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrrciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrrciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrrciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrrciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrrciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrrciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrrciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrri_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\trb      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SRrriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n}\n\nfunc (this *SRrriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrriStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/instruction/s_rrrici_stmt.go",
    "content": "package instruction\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SRrriciStmt struct {\n\top_code   *expr.Expr\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\tra        *expr.Expr\n\trb        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *SRrriciStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.RRRI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RRRI op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *SRrriciStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SRrriciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *SRrriciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *SRrriciStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SRrriciStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *SRrriciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *SRrriciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *SRrriciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/label_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LabelStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *LabelStmt) Init(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr = expr_\n}\n\nfunc (this *LabelStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/stmt.go",
    "content": "package stmt\n\nimport (\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt/directive\"\n\t\"uPIMulator/src/device/linker/parser/stmt/instruction\"\n\t\"uPIMulator/src/device/linker/parser/stmt/sugar\"\n)\n\ntype StmtType int\n\nconst (\n\tADDRSIG StmtType = iota\n\tADDRSIG_SYM\n\tASCII\n\tASCIZ\n\tBYTE\n\tCFI_DEF_CFA_OFFSET\n\tCFI_ENDPROC\n\tCFI_OFFSET\n\tCFI_SECTIONS\n\tCFI_STARTPROC\n\tFILE_NUMBER\n\tFILE_STRING\n\tGLOBAL\n\tLOC_IS_STMT\n\tLOC_NUMBER\n\tLOC_PROLOGUE_END\n\tLONG_PROGRAM_COUNTER\n\tLONG_SECTION_NAME\n\tP2_ALIGN\n\tQUAD\n\tSECTION_IDENTIFIER_NUMBER\n\tSECTION_IDENTIFIER\n\tSECTION_STACK_SIZES\n\tSECTION_STRING_NUMBER\n\tSECTION_STRING\n\tSET\n\tSHORT\n\tSIZE\n\tTEXT\n\tTYPE\n\tWEAK\n\tZERO_SINGLE_NUMBER\n\tZERO_DOUBLE_NUMBER\n\n\tRICI\n\tRRI\n\tRRIC\n\tRRICI\n\tRRR\n\tRRRC\n\tRRRCI\n\n\tS_RRI\n\tS_RRIC\n\tS_RRICI\n\tS_RRR\n\tS_RRRC\n\tS_RRRCI\n\n\tRR\n\tRRC\n\tRRCI\n\n\tS_RR\n\tS_RRC\n\tS_RRCI\n\n\tDRDICI\n\n\tRRRI\n\tRRRICI\n\n\tS_RRRI\n\tS_RRRICI\n\n\tRIR\n\tRIRC\n\tRIRCI\n\n\tS_RIRC\n\tS_RIRCI\n\n\tR\n\tRCI\n\n\tS_R\n\tS_RCI\n\n\tCI\n\tI\n\n\tDDCI\n\n\tERRI\n\tEDRI\n\tS_ERRI\n\n\tERII\n\tERIR\n\tERID\n\n\tDMA_RRI\n\n\tNOP\n\n\tMOVE_RI\n\tMOVE_RICI\n\tMOVE_S_RI\n\tMOVE_S_RICI\n\n\tJEQ_RII\n\tJEQ_RRI\n\tJNZ_RI\n\tJUMP_I\n\tJUMP_R\n\n\tDIV_STEP_DRDI\n\tBOOT_RI\n\tSTOP\n\tCALL_RI\n\tCALL_RR\n\tBKP\n\tMOVD_DD\n\tTIME_CFG_R\n\tLBS_RRI\n\tLBS_S_RRI\n\tLD_DRI\n\tSB_RIR\n\tSB_ID_RII\n\tSB_ID_RI\n\tSD_RID\n\n\tLABEL\n)\n\ntype Stmt struct {\n\tstmt_type StmtType\n\n\taddrsig_stmt                   *directive.AddrsigStmt\n\taddrsig_sym_stmt               *directive.AddrsigSymStmt\n\tascii_stmt                     *directive.AsciiStmt\n\tasciz_stmt                     *directive.AscizStmt\n\tbyte_stmt                      *directive.ByteStmt\n\tcfi_def_cfa_offset_stmt        *directive.CfiDefCfaOffsetStmt\n\tcfi_endproc_stmt               *directive.CfiEndprocStmt\n\tcfi_offset_stmt                *directive.CfiOffsetStmt\n\tcfi_sections_stmt              *directive.CfiSectionsStmt\n\tcfi_startproc_stmt             *directive.CfiStartprocStmt\n\tfile_number_stmt               *directive.FileNumberStmt\n\tfile_string_stmt               *directive.FileStringStmt\n\tglobal_stmt                    *directive.GlobalStmt\n\tloc_is_stmt_stmt               *directive.LocIsStmtStmt\n\tloc_number_stmt                *directive.LocNumberStmt\n\tloc_prologue_end_stmt          *directive.LocPrologueEndStmt\n\tlong_program_counter_stmt      *directive.LongProgramCounterStmt\n\tlong_section_name_stmt         *directive.LongSectionNameStmt\n\tp2_align_stmt                  *directive.P2AlignStmt\n\tquad_stmt                      *directive.QuadStmt\n\tsection_identifier_number_stmt *directive.SectionIdentifierNumberStmt\n\tsection_identifier_stmt        *directive.SectionIdentifierStmt\n\tsection_stack_sizes_stmt       *directive.SectionStackSizesStmt\n\tsection_string_number_stmt     *directive.SectionStringNumberStmt\n\tsection_string_stmt            *directive.SectionStringStmt\n\tset_stmt                       *directive.SetStmt\n\tshort_stmt                     *directive.ShortStmt\n\tsize_stmt                      *directive.SizeStmt\n\ttext_stmt                      *directive.TextStmt\n\ttype_stmt                      *directive.TypeStmt\n\tweak_stmt                      *directive.WeakStmt\n\tzero_single_number_stmt        *directive.ZeroSingleNumberStmt\n\tzero_double_number_stmt        *directive.ZeroDoubleNumberStmt\n\n\tci_stmt      *instruction.CiStmt\n\tddci_stmt    *instruction.DdciStmt\n\tdma_rri_stmt *instruction.DmaRriStmt\n\tdrdici_stmt  *instruction.DrdiciStmt\n\tedri_stmt    *instruction.EdriStmt\n\terid_stmt    *instruction.EridStmt\n\terii_stmt    *instruction.EriiStmt\n\terir_stmt    *instruction.ErirStmt\n\terri_stmt    *instruction.ErriStmt\n\ti_stmt       *instruction.IStmt\n\tnop_stmt     *instruction.NopStmt\n\tr_stmt       *instruction.RStmt\n\trci_stmt     *instruction.RciStmt\n\trici_stmt    *instruction.RiciStmt\n\trir_stmt     *instruction.RirStmt\n\trirc_stmt    *instruction.RircStmt\n\trirci_stmt   *instruction.RirciStmt\n\trr_stmt      *instruction.RrStmt\n\trrc_stmt     *instruction.RrcStmt\n\trrci_stmt    *instruction.RrciStmt\n\trri_stmt     *instruction.RriStmt\n\trric_stmt    *instruction.RricStmt\n\trrici_stmt   *instruction.RriciStmt\n\trrr_stmt     *instruction.RrrStmt\n\trrrc_stmt    *instruction.RrrcStmt\n\trrrci_stmt   *instruction.RrrciStmt\n\trrri_stmt    *instruction.RrriStmt\n\trrrici_stmt  *instruction.RrriciStmt\n\n\ts_erri_stmt   *instruction.SErriStmt\n\ts_r_stmt      *instruction.SRStmt\n\ts_rci_stmt    *instruction.SRciStmt\n\ts_rirc_stmt   *instruction.SRircStmt\n\ts_rirci_stmt  *instruction.SRirciStmt\n\ts_rr_stmt     *instruction.SRrStmt\n\ts_rrc_stmt    *instruction.SRrcStmt\n\ts_rrci_stmt   *instruction.SRrciStmt\n\ts_rri_stmt    *instruction.SRriStmt\n\ts_rric_stmt   *instruction.SRricStmt\n\ts_rrici_stmt  *instruction.SRriciStmt\n\ts_rrr_stmt    *instruction.SRrrStmt\n\ts_rrrc_stmt   *instruction.SRrrcStmt\n\ts_rrrci_stmt  *instruction.SRrrciStmt\n\ts_rrri_stmt   *instruction.SRrriStmt\n\ts_rrrici_stmt *instruction.SRrriciStmt\n\n\tbkp_stmt           *sugar.BkpStmt\n\tboot_ri_stmt       *sugar.BootRiStmt\n\tcall_ri_stmt       *sugar.CallRiStmt\n\tcall_rr_stmt       *sugar.CallRrStmt\n\tdiv_step_drdi_stmt *sugar.DivStepDrdiStmt\n\tjeq_rii_stmt       *sugar.JeqRiiStmt\n\tjeq_rri_stmt       *sugar.JeqRriStmt\n\tjnz_ri_stmt        *sugar.JnzRiStmt\n\tjump_i_stmt        *sugar.JumpIStmt\n\tjump_r_stmt        *sugar.JumpRStmt\n\tlbs_rri_stmt       *sugar.LbsRriStmt\n\tlbs_s_rri_stmt     *sugar.LbsSRriStmt\n\tld_dri_stmt        *sugar.LdDriStmt\n\tmovd_dd_stmt       *sugar.MovdDdStmt\n\tmove_ri_stmt       *sugar.MoveRiStmt\n\tmove_rici_stmt     *sugar.MoveRiciStmt\n\tmove_s_ri_stmt     *sugar.MoveSRiStmt\n\tmove_s_rici_stmt   *sugar.MoveSRiciStmt\n\tsb_id_ri_stmt      *sugar.SbIdRiStmt\n\tsb_id_rii_stmt     *sugar.SbIdRiiStmt\n\tsb_rir_stmt        *sugar.SbRirStmt\n\tsd_rid_stmt        *sugar.SdRidStmt\n\tstop_stmt          *sugar.StopStmt\n\ttime_cfg_r_stmt    *sugar.TimeCfgRStmt\n\n\tlabel_stmt *LabelStmt\n}\n\nfunc (this *Stmt) InitAddrsigStmt() {\n\tthis.stmt_type = ADDRSIG\n\n\tthis.addrsig_stmt = new(directive.AddrsigStmt)\n\tthis.addrsig_stmt.Init()\n}\n\nfunc (this *Stmt) InitAddrsigSymStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = ADDRSIG_SYM\n\n\tthis.addrsig_sym_stmt = new(directive.AddrsigSymStmt)\n\tthis.addrsig_sym_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitAsciiStmt(token *lexer.Token) {\n\tthis.stmt_type = ASCII\n\n\tthis.ascii_stmt = new(directive.AsciiStmt)\n\tthis.ascii_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitAscizStmt(token *lexer.Token) {\n\tthis.stmt_type = ASCIZ\n\n\tthis.asciz_stmt = new(directive.AscizStmt)\n\tthis.asciz_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitByteStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = BYTE\n\n\tthis.byte_stmt = new(directive.ByteStmt)\n\tthis.byte_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiDefCfaOffsetStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = CFI_DEF_CFA_OFFSET\n\n\tthis.cfi_def_cfa_offset_stmt = new(directive.CfiDefCfaOffsetStmt)\n\tthis.cfi_def_cfa_offset_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiEndprocStmt() {\n\tthis.stmt_type = CFI_ENDPROC\n\n\tthis.cfi_endproc_stmt = new(directive.CfiEndprocStmt)\n\tthis.cfi_endproc_stmt.Init()\n}\n\nfunc (this *Stmt) InitCfiOffsetStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = CFI_OFFSET\n\n\tthis.cfi_offset_stmt = new(directive.CfiOffsetStmt)\n\tthis.cfi_offset_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitCfiSectionsStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = CFI_SECTIONS\n\n\tthis.cfi_sections_stmt = new(directive.CfiSectionsStmt)\n\tthis.cfi_sections_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitCfiStartprocStmt() {\n\tthis.stmt_type = CFI_STARTPROC\n\n\tthis.cfi_startproc_stmt = new(directive.CfiStartprocStmt)\n\tthis.cfi_startproc_stmt.Init()\n}\n\nfunc (this *Stmt) InitFileNumberStmt(expr_ *expr.Expr, token1 *lexer.Token, token2 *lexer.Token) {\n\tthis.stmt_type = FILE_NUMBER\n\n\tthis.file_number_stmt = new(directive.FileNumberStmt)\n\tthis.file_number_stmt.Init(expr_, token1, token2)\n}\n\nfunc (this *Stmt) InitFileStringStmt(token *lexer.Token) {\n\tthis.stmt_type = FILE_STRING\n\n\tthis.file_string_stmt = new(directive.FileStringStmt)\n\tthis.file_string_stmt.Init(token)\n}\n\nfunc (this *Stmt) InitGlobalStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = GLOBAL\n\n\tthis.global_stmt = new(directive.GlobalStmt)\n\tthis.global_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitLocIsStmtStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tthis.stmt_type = LOC_IS_STMT\n\n\tthis.loc_is_stmt_stmt = new(directive.LocIsStmtStmt)\n\tthis.loc_is_stmt_stmt.Init(expr1, expr2, expr3, expr4)\n}\n\nfunc (this *Stmt) InitLocNumberStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = LOC_NUMBER\n\n\tthis.loc_number_stmt = new(directive.LocNumberStmt)\n\tthis.loc_number_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitLocPrologueEndStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = LOC_PROLOGUE_END\n\n\tthis.loc_prologue_end_stmt = new(directive.LocPrologueEndStmt)\n\tthis.loc_prologue_end_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitLongProgramCounterStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LONG_PROGRAM_COUNTER\n\n\tthis.long_program_counter_stmt = new(directive.LongProgramCounterStmt)\n\tthis.long_program_counter_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitLongSectionNameStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LONG_SECTION_NAME\n\n\tthis.long_section_name_stmt = new(directive.LongSectionNameStmt)\n\tthis.long_section_name_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitP2AlignStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = P2_ALIGN\n\n\tthis.p2_align_stmt = new(directive.P2AlignStmt)\n\tthis.p2_align_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitQuadStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = QUAD\n\n\tthis.quad_stmt = new(directive.QuadStmt)\n\tthis.quad_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitSectionIdentifierNumberStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n\texpr4 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_IDENTIFIER_NUMBER\n\n\tthis.section_identifier_number_stmt = new(directive.SectionIdentifierNumberStmt)\n\tthis.section_identifier_number_stmt.Init(expr1, expr2, token, expr3, expr4)\n}\n\nfunc (this *Stmt) InitSectionIdentifierStmt(\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_IDENTIFIER\n\n\tthis.section_identifier_stmt = new(directive.SectionIdentifierStmt)\n\tthis.section_identifier_stmt.Init(expr1, expr2, token, expr3)\n}\n\nfunc (this *Stmt) InitSectionStackSizesStmt(\n\ttoken *lexer.Token,\n\texpr1 *expr.Expr,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_STACK_SIZES\n\n\tthis.section_stack_sizes_stmt = new(directive.SectionStackSizesStmt)\n\tthis.section_stack_sizes_stmt.Init(token, expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitSectionStringNumberStmt(\n\texpr1 *expr.Expr,\n\ttoken *lexer.Token,\n\texpr2 *expr.Expr,\n\texpr3 *expr.Expr,\n) {\n\tthis.stmt_type = SECTION_STRING_NUMBER\n\n\tthis.section_string_number_stmt = new(directive.SectionStringNumberStmt)\n\tthis.section_string_number_stmt.Init(expr1, token, expr2, expr3)\n}\n\nfunc (this *Stmt) InitSectionStringStmt(expr1 *expr.Expr, token *lexer.Token, expr2 *expr.Expr) {\n\tthis.stmt_type = SECTION_STRING\n\n\tthis.section_string_stmt = new(directive.SectionStringStmt)\n\tthis.section_string_stmt.Init(expr1, token, expr2)\n}\n\nfunc (this *Stmt) InitSetStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = SET\n\n\tthis.set_stmt = new(directive.SetStmt)\n\tthis.set_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitShortStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = SHORT\n\n\tthis.short_stmt = new(directive.ShortStmt)\n\tthis.short_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitSizeStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = SIZE\n\n\tthis.size_stmt = new(directive.SizeStmt)\n\tthis.size_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitTextStmt() {\n\tthis.stmt_type = TEXT\n\n\tthis.text_stmt = new(directive.TextStmt)\n\tthis.text_stmt.Init()\n}\n\nfunc (this *Stmt) InitTypeStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = TYPE\n\n\tthis.type_stmt = new(directive.TypeStmt)\n\tthis.type_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitWeakStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = WEAK\n\n\tthis.weak_stmt = new(directive.WeakStmt)\n\tthis.weak_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitZeroSingleNumberStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = ZERO_SINGLE_NUMBER\n\n\tthis.zero_single_number_stmt = new(directive.ZeroSingleNumberStmt)\n\tthis.zero_single_number_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) InitZeroDoubleNumberStmt(expr1 *expr.Expr, expr2 *expr.Expr) {\n\tthis.stmt_type = ZERO_DOUBLE_NUMBER\n\n\tthis.zero_double_number_stmt = new(directive.ZeroDoubleNumberStmt)\n\tthis.zero_double_number_stmt.Init(expr1, expr2)\n}\n\nfunc (this *Stmt) InitCiStmt(expr1 *expr.Expr, expr2 *expr.Expr, expr3 *expr.Expr) {\n\tthis.stmt_type = CI\n\n\tthis.ci_stmt = new(instruction.CiStmt)\n\tthis.ci_stmt.Init(expr1, expr2, expr3)\n}\n\nfunc (this *Stmt) InitDdciStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tdb *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = DDCI\n\n\tthis.ddci_stmt = new(instruction.DdciStmt)\n\tthis.ddci_stmt.Init(op_code, dc, db, condition, pc)\n}\n\nfunc (this *Stmt) InitDmaRriStmt(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = DMA_RRI\n\n\tthis.dma_rri_stmt = new(instruction.DmaRriStmt)\n\tthis.dma_rri_stmt.Init(op_code, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitDrdiciStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = DRDICI\n\n\tthis.drdici_stmt = new(instruction.DrdiciStmt)\n\tthis.drdici_stmt.Init(op_code, dc, ra, db, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitEdriStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = EDRI\n\n\tthis.edri_stmt = new(instruction.EdriStmt)\n\tthis.edri_stmt.Init(op_code, endian, dc, ra, off)\n}\n\nfunc (this *Stmt) InitEridStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tthis.stmt_type = ERID\n\n\tthis.erid_stmt = new(instruction.EridStmt)\n\tthis.erid_stmt.Init(op_code, endian, ra, off, db)\n}\n\nfunc (this *Stmt) InitEriiStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = ERII\n\n\tthis.erii_stmt = new(instruction.EriiStmt)\n\tthis.erii_stmt.Init(op_code, endian, ra, off, imm)\n}\n\nfunc (this *Stmt) InitErirStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\trb *expr.Expr,\n) {\n\tthis.stmt_type = ERIR\n\n\tthis.erir_stmt = new(instruction.ErirStmt)\n\tthis.erir_stmt.Init(op_code, endian, ra, off, rb)\n}\n\nfunc (this *Stmt) InitErriStmt(\n\top_code *expr.Expr,\n\tendian *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = ERRI\n\n\tthis.erri_stmt = new(instruction.ErriStmt)\n\tthis.erri_stmt.Init(op_code, endian, rc, ra, off)\n}\n\nfunc (this *Stmt) InitIStmt(op_code *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = I\n\n\tthis.i_stmt = new(instruction.IStmt)\n\tthis.i_stmt.Init(op_code, imm)\n}\n\nfunc (this *Stmt) InitNopStmt(op_code *expr.Expr) {\n\tthis.stmt_type = NOP\n\n\tthis.nop_stmt = new(instruction.NopStmt)\n\tthis.nop_stmt.Init(op_code)\n}\n\nfunc (this *Stmt) InitRStmt(op_code *expr.Expr, rc *expr.Expr) {\n\tthis.stmt_type = R\n\n\tthis.r_stmt = new(instruction.RStmt)\n\tthis.r_stmt.Init(op_code, rc)\n}\n\nfunc (this *Stmt) InitRciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RCI\n\n\tthis.rci_stmt = new(instruction.RciStmt)\n\tthis.rci_stmt.Init(op_code, rc, condition, pc)\n}\n\nfunc (this *Stmt) InitRiciStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RICI\n\n\tthis.rici_stmt = new(instruction.RiciStmt)\n\tthis.rici_stmt.Init(op_code, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitRirStmt(op_code *expr.Expr, rc *expr.Expr, imm *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = RIR\n\n\tthis.rir_stmt = new(instruction.RirStmt)\n\tthis.rir_stmt.Init(op_code, rc, imm, ra)\n}\n\nfunc (this *Stmt) InitRircStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RIRC\n\n\tthis.rirc_stmt = new(instruction.RircStmt)\n\tthis.rirc_stmt.Init(op_code, rc, imm, ra, condition)\n}\n\nfunc (this *Stmt) InitRirciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RIRCI\n\n\tthis.rirci_stmt = new(instruction.RirciStmt)\n\tthis.rirci_stmt.Init(op_code, rc, imm, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitRrStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = RR\n\n\tthis.rr_stmt = new(instruction.RrStmt)\n\tthis.rr_stmt.Init(op_code, rc, ra)\n}\n\nfunc (this *Stmt) InitRrcStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRC\n\n\tthis.rrc_stmt = new(instruction.RrcStmt)\n\tthis.rrc_stmt.Init(op_code, rc, ra, condition)\n}\n\nfunc (this *Stmt) InitRrciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRCI\n\n\tthis.rrci_stmt = new(instruction.RrciStmt)\n\tthis.rrci_stmt.Init(op_code, rc, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitRriStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = RRI\n\n\tthis.rri_stmt = new(instruction.RriStmt)\n\tthis.rri_stmt.Init(op_code, rc, ra, imm)\n}\n\nfunc (this *Stmt) InitRricStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRIC\n\n\tthis.rric_stmt = new(instruction.RricStmt)\n\tthis.rric_stmt.Init(op_code, rc, ra, imm, condition)\n}\n\nfunc (this *Stmt) InitRriciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRICI\n\n\tthis.rrici_stmt = new(instruction.RriciStmt)\n\tthis.rrici_stmt.Init(op_code, rc, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitRrrStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, rb *expr.Expr) {\n\tthis.stmt_type = RRR\n\n\tthis.rrr_stmt = new(instruction.RrrStmt)\n\tthis.rrr_stmt.Init(op_code, rc, ra, rb)\n}\n\nfunc (this *Stmt) InitRrrcStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = RRRC\n\n\tthis.rrrc_stmt = new(instruction.RrrcStmt)\n\tthis.rrrc_stmt.Init(op_code, rc, ra, rb, condition)\n}\n\nfunc (this *Stmt) InitRrrciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRRCI\n\n\tthis.rrrci_stmt = new(instruction.RrrciStmt)\n\tthis.rrrci_stmt.Init(op_code, rc, ra, rb, condition, pc)\n}\n\nfunc (this *Stmt) InitRrriStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = RRRI\n\n\tthis.rrri_stmt = new(instruction.RrriStmt)\n\tthis.rrri_stmt.Init(op_code, rc, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitRrriciStmt(\n\top_code *expr.Expr,\n\trc *expr.Expr,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = RRRICI\n\n\tthis.rrrici_stmt = new(instruction.RrriciStmt)\n\tthis.rrrici_stmt.Init(op_code, rc, ra, rb, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSErriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tendian *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = S_ERRI\n\n\tthis.s_erri_stmt = new(instruction.SErriStmt)\n\tthis.s_erri_stmt.Init(op_code, suffix, endian, dc, ra, off)\n}\n\nfunc (this *Stmt) InitSRStmt(op_code *expr.Expr, suffix *expr.Expr, dc *lexer.Token) {\n\tthis.stmt_type = S_R\n\n\tthis.s_r_stmt = new(instruction.SRStmt)\n\tthis.s_r_stmt.Init(op_code, suffix, dc)\n}\n\nfunc (this *Stmt) InitSRciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RCI\n\n\tthis.s_rci_stmt = new(instruction.SRciStmt)\n\tthis.s_rci_stmt.Init(op_code, suffix, dc, condition, pc)\n}\n\nfunc (this *Stmt) InitSRircStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RIRC\n\n\tthis.s_rirc_stmt = new(instruction.SRircStmt)\n\tthis.s_rirc_stmt.Init(op_code, suffix, dc, imm, ra, condition)\n}\n\nfunc (this *Stmt) InitSRirciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RIRCI\n\n\tthis.s_rirci_stmt = new(instruction.SRirciStmt)\n\tthis.s_rirci_stmt.Init(op_code, suffix, dc, imm, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n) {\n\tthis.stmt_type = S_RR\n\n\tthis.s_rr_stmt = new(instruction.SRrStmt)\n\tthis.s_rr_stmt.Init(op_code, suffix, dc, ra)\n}\n\nfunc (this *Stmt) InitSRrcStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRC\n\n\tthis.s_rrc_stmt = new(instruction.SRrcStmt)\n\tthis.s_rrc_stmt.Init(op_code, suffix, dc, ra, condition)\n}\n\nfunc (this *Stmt) InitSRrciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRCI\n\n\tthis.s_rrci_stmt = new(instruction.SRrciStmt)\n\tthis.s_rrci_stmt.Init(op_code, suffix, dc, ra, condition, pc)\n}\n\nfunc (this *Stmt) InitSRriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = S_RRI\n\n\tthis.s_rri_stmt = new(instruction.SRriStmt)\n\tthis.s_rri_stmt.Init(op_code, suffix, dc, ra, imm)\n}\n\nfunc (this *Stmt) InitSRricStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRIC\n\n\tthis.s_rric_stmt = new(instruction.SRricStmt)\n\tthis.s_rric_stmt.Init(op_code, suffix, dc, ra, imm, condition)\n}\n\nfunc (this *Stmt) InitSRriciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRICI\n\n\tthis.s_rrici_stmt = new(instruction.SRriciStmt)\n\tthis.s_rrici_stmt.Init(op_code, suffix, dc, ra, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrrStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n) {\n\tthis.stmt_type = S_RRR\n\n\tthis.s_rrr_stmt = new(instruction.SRrrStmt)\n\tthis.s_rrr_stmt.Init(op_code, suffix, dc, ra, rb)\n}\n\nfunc (this *Stmt) InitSRrrcStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRC\n\n\tthis.s_rrrc_stmt = new(instruction.SRrrcStmt)\n\tthis.s_rrrc_stmt.Init(op_code, suffix, dc, ra, rb, condition)\n}\n\nfunc (this *Stmt) InitSRrrciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRCI\n\n\tthis.s_rrrci_stmt = new(instruction.SRrrciStmt)\n\tthis.s_rrrci_stmt.Init(op_code, suffix, dc, ra, rb, condition, pc)\n}\n\nfunc (this *Stmt) InitSRrriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRI\n\n\tthis.s_rrri_stmt = new(instruction.SRrriStmt)\n\tthis.s_rrri_stmt.Init(op_code, suffix, dc, ra, rb, imm)\n}\n\nfunc (this *Stmt) InitSRrriciStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\trb *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = S_RRRICI\n\n\tthis.s_rrrici_stmt = new(instruction.SRrriciStmt)\n\tthis.s_rrrici_stmt.Init(op_code, suffix, dc, ra, rb, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitBkpStmt() {\n\tthis.stmt_type = BKP\n\n\tthis.bkp_stmt = new(sugar.BkpStmt)\n\tthis.bkp_stmt.Init()\n}\n\nfunc (this *Stmt) InitBootRiStmt(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = BOOT_RI\n\n\tthis.boot_ri_stmt = new(sugar.BootRiStmt)\n\tthis.boot_ri_stmt.Init(op_code, ra, imm)\n}\n\nfunc (this *Stmt) InitCallRiStmt(rc *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = CALL_RI\n\n\tthis.call_ri_stmt = new(sugar.CallRiStmt)\n\tthis.call_ri_stmt.Init(rc, imm)\n}\n\nfunc (this *Stmt) InitCallRrStmt(rc *expr.Expr, ra *expr.Expr) {\n\tthis.stmt_type = CALL_RR\n\n\tthis.call_rr_stmt = new(sugar.CallRrStmt)\n\tthis.call_rr_stmt.Init(rc, ra)\n}\n\nfunc (this *Stmt) InitDivStepDrdiStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = DIV_STEP_DRDI\n\n\tthis.div_step_drdi_stmt = new(sugar.DivStepDrdiStmt)\n\tthis.div_step_drdi_stmt.Init(op_code, dc, ra, db, imm)\n}\n\nfunc (this *Stmt) InitJeqRiiStmt(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JEQ_RII\n\n\tthis.jeq_rii_stmt = new(sugar.JeqRiiStmt)\n\tthis.jeq_rii_stmt.Init(op_code, ra, imm, pc)\n}\n\nfunc (this *Stmt) InitJeqRriStmt(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JEQ_RRI\n\n\tthis.jeq_rri_stmt = new(sugar.JeqRriStmt)\n\tthis.jeq_rri_stmt.Init(op_code, ra, rb, pc)\n}\n\nfunc (this *Stmt) InitJnzRiStmt(op_code *expr.Expr, ra *expr.Expr, pc *expr.Expr) {\n\tthis.stmt_type = JNZ_RI\n\n\tthis.jnz_ri_stmt = new(sugar.JnzRiStmt)\n\tthis.jnz_ri_stmt.Init(op_code, ra, pc)\n}\n\nfunc (this *Stmt) InitJumpIStmt(pc *expr.Expr) {\n\tthis.stmt_type = JUMP_I\n\n\tthis.jump_i_stmt = new(sugar.JumpIStmt)\n\tthis.jump_i_stmt.Init(pc)\n}\n\nfunc (this *Stmt) InitJumpRStmt(ra *expr.Expr) {\n\tthis.stmt_type = JUMP_R\n\n\tthis.jump_r_stmt = new(sugar.JumpRStmt)\n\tthis.jump_r_stmt.Init(ra)\n}\n\nfunc (this *Stmt) InitLbsRriStmt(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tthis.stmt_type = LBS_RRI\n\n\tthis.lbs_rri_stmt = new(sugar.LbsRriStmt)\n\tthis.lbs_rri_stmt.Init(op_code, rc, ra, off)\n}\n\nfunc (this *Stmt) InitLbsSRriStmt(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = LBS_S_RRI\n\n\tthis.lbs_s_rri_stmt = new(sugar.LbsSRriStmt)\n\tthis.lbs_s_rri_stmt.Init(op_code, suffix, dc, ra, off)\n}\n\nfunc (this *Stmt) InitLdDriStmt(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tthis.stmt_type = LD_DRI\n\n\tthis.ld_dri_stmt = new(sugar.LdDriStmt)\n\tthis.ld_dri_stmt.Init(op_code, dc, ra, off)\n}\n\nfunc (this *Stmt) InitMovdDdStmt(op_code *expr.Expr, dc *lexer.Token, db *lexer.Token) {\n\tthis.stmt_type = MOVD_DD\n\n\tthis.movd_dd_stmt = new(sugar.MovdDdStmt)\n\tthis.movd_dd_stmt.Init(op_code, dc, db)\n}\n\nfunc (this *Stmt) InitMoveRiStmt(rc *expr.Expr, imm *expr.Expr) {\n\tthis.stmt_type = MOVE_RI\n\n\tthis.move_ri_stmt = new(sugar.MoveRiStmt)\n\tthis.move_ri_stmt.Init(rc, imm)\n}\n\nfunc (this *Stmt) InitMoveRiciStmt(\n\trc *expr.Expr,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = MOVE_RICI\n\n\tthis.move_rici_stmt = new(sugar.MoveRiciStmt)\n\tthis.move_rici_stmt.Init(rc, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitMoveSRiStmt(suffix *expr.Expr, dc *lexer.Token, imm *expr.Expr) {\n\tthis.stmt_type = MOVE_S_RI\n\n\tthis.move_s_ri_stmt = new(sugar.MoveSRiStmt)\n\tthis.move_s_ri_stmt.Init(suffix, dc, imm)\n}\n\nfunc (this *Stmt) InitMoveSRiciStmt(\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tthis.stmt_type = MOVE_S_RICI\n\n\tthis.move_s_rici_stmt = new(sugar.MoveSRiciStmt)\n\tthis.move_s_rici_stmt.Init(suffix, dc, imm, condition, pc)\n}\n\nfunc (this *Stmt) InitSbIdRiStmt(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tthis.stmt_type = SB_ID_RI\n\n\tthis.sb_id_ri_stmt = new(sugar.SbIdRiStmt)\n\tthis.sb_id_ri_stmt.Init(op_code, ra, off)\n}\n\nfunc (this *Stmt) InitSbIdRiiStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\timm *expr.Expr,\n) {\n\tthis.stmt_type = SB_ID_RII\n\n\tthis.sb_id_rii_stmt = new(sugar.SbIdRiiStmt)\n\tthis.sb_id_rii_stmt.Init(op_code, ra, off, imm)\n}\n\nfunc (this *Stmt) InitSbRirStmt(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, rb *expr.Expr) {\n\tthis.stmt_type = SB_RIR\n\n\tthis.sb_rir_stmt = new(sugar.SbRirStmt)\n\tthis.sb_rir_stmt.Init(op_code, ra, off, rb)\n}\n\nfunc (this *Stmt) InitSdRidStmt(\n\top_code *expr.Expr,\n\tra *expr.Expr,\n\toff *expr.Expr,\n\tdb *lexer.Token,\n) {\n\tthis.stmt_type = SD_RID\n\n\tthis.sd_rid_stmt = new(sugar.SdRidStmt)\n\tthis.sd_rid_stmt.Init(op_code, ra, off, db)\n}\n\nfunc (this *Stmt) InitStopStmt() {\n\tthis.stmt_type = STOP\n\n\tthis.stop_stmt = new(sugar.StopStmt)\n\tthis.stop_stmt.Init()\n}\n\nfunc (this *Stmt) InitTimeCfgRStmt(ra *expr.Expr) {\n\tthis.stmt_type = TIME_CFG_R\n\n\tthis.time_cfg_r_stmt = new(sugar.TimeCfgRStmt)\n\tthis.time_cfg_r_stmt.Init(ra)\n}\n\nfunc (this *Stmt) InitLabelStmt(expr_ *expr.Expr) {\n\tthis.stmt_type = LABEL\n\n\tthis.label_stmt = new(LabelStmt)\n\tthis.label_stmt.Init(expr_)\n}\n\nfunc (this *Stmt) StmtType() StmtType {\n\treturn this.stmt_type\n}\n\nfunc (this *Stmt) AddrsigStmt() *directive.AddrsigStmt {\n\treturn this.addrsig_stmt\n}\n\nfunc (this *Stmt) AddrsigSymStmt() *directive.AddrsigSymStmt {\n\treturn this.addrsig_sym_stmt\n}\n\nfunc (this *Stmt) AsciiStmt() *directive.AsciiStmt {\n\treturn this.ascii_stmt\n}\n\nfunc (this *Stmt) AscizStmt() *directive.AscizStmt {\n\treturn this.asciz_stmt\n}\n\nfunc (this *Stmt) ByteStmt() *directive.ByteStmt {\n\treturn this.byte_stmt\n}\n\nfunc (this *Stmt) CfiDefCfaOffsetStmt() *directive.CfiDefCfaOffsetStmt {\n\treturn this.cfi_def_cfa_offset_stmt\n}\n\nfunc (this *Stmt) CfiEndprocStmt() *directive.CfiEndprocStmt {\n\treturn this.cfi_endproc_stmt\n}\n\nfunc (this *Stmt) CfiOffsetStmt() *directive.CfiOffsetStmt {\n\treturn this.cfi_offset_stmt\n}\n\nfunc (this *Stmt) CfiSectionsStmt() *directive.CfiSectionsStmt {\n\treturn this.cfi_sections_stmt\n}\n\nfunc (this *Stmt) CfiStartprocStmt() *directive.CfiStartprocStmt {\n\treturn this.cfi_startproc_stmt\n}\n\nfunc (this *Stmt) FileNumberStmt() *directive.FileNumberStmt {\n\treturn this.file_number_stmt\n}\n\nfunc (this *Stmt) FileStringStmt() *directive.FileStringStmt {\n\treturn this.file_string_stmt\n}\n\nfunc (this *Stmt) GlobalStmt() *directive.GlobalStmt {\n\treturn this.global_stmt\n}\n\nfunc (this *Stmt) LocIsStmtStmt() *directive.LocIsStmtStmt {\n\treturn this.loc_is_stmt_stmt\n}\n\nfunc (this *Stmt) LocNumberStmt() *directive.LocNumberStmt {\n\treturn this.loc_number_stmt\n}\n\nfunc (this *Stmt) LocPrologueEndStmt() *directive.LocPrologueEndStmt {\n\treturn this.loc_prologue_end_stmt\n}\n\nfunc (this *Stmt) LongProgramCounterStmt() *directive.LongProgramCounterStmt {\n\treturn this.long_program_counter_stmt\n}\n\nfunc (this *Stmt) LongSectionNameStmt() *directive.LongSectionNameStmt {\n\treturn this.long_section_name_stmt\n}\n\nfunc (this *Stmt) P2AlignStmt() *directive.P2AlignStmt {\n\treturn this.p2_align_stmt\n}\n\nfunc (this *Stmt) QuadStmt() *directive.QuadStmt {\n\treturn this.quad_stmt\n}\n\nfunc (this *Stmt) SectionIdentifierNumberStmt() *directive.SectionIdentifierNumberStmt {\n\treturn this.section_identifier_number_stmt\n}\n\nfunc (this *Stmt) SectionIdentifierStmt() *directive.SectionIdentifierStmt {\n\treturn this.section_identifier_stmt\n}\n\nfunc (this *Stmt) SectionStackSizesStmt() *directive.SectionStackSizesStmt {\n\treturn this.section_stack_sizes_stmt\n}\n\nfunc (this *Stmt) SectionStringNumberStmt() *directive.SectionStringNumberStmt {\n\treturn this.section_string_number_stmt\n}\n\nfunc (this *Stmt) SectionStringStmt() *directive.SectionStringStmt {\n\treturn this.section_string_stmt\n}\n\nfunc (this *Stmt) SetStmt() *directive.SetStmt {\n\treturn this.set_stmt\n}\n\nfunc (this *Stmt) ShortStmt() *directive.ShortStmt {\n\treturn this.short_stmt\n}\n\nfunc (this *Stmt) SizeStmt() *directive.SizeStmt {\n\treturn this.size_stmt\n}\n\nfunc (this *Stmt) TextStmt() *directive.TextStmt {\n\treturn this.text_stmt\n}\n\nfunc (this *Stmt) TypeStmt() *directive.TypeStmt {\n\treturn this.type_stmt\n}\n\nfunc (this *Stmt) WeakStmt() *directive.WeakStmt {\n\treturn this.weak_stmt\n}\n\nfunc (this *Stmt) ZeroSingleNumberStmt() *directive.ZeroSingleNumberStmt {\n\treturn this.zero_single_number_stmt\n}\n\nfunc (this *Stmt) ZeroDoubleNumberStmt() *directive.ZeroDoubleNumberStmt {\n\treturn this.zero_double_number_stmt\n}\n\nfunc (this *Stmt) CiStmt() *instruction.CiStmt {\n\treturn this.ci_stmt\n}\n\nfunc (this *Stmt) DdciStmt() *instruction.DdciStmt {\n\treturn this.ddci_stmt\n}\n\nfunc (this *Stmt) DmaRriStmt() *instruction.DmaRriStmt {\n\treturn this.dma_rri_stmt\n}\n\nfunc (this *Stmt) DrdiciStmt() *instruction.DrdiciStmt {\n\treturn this.drdici_stmt\n}\n\nfunc (this *Stmt) EdriStmt() *instruction.EdriStmt {\n\treturn this.edri_stmt\n}\n\nfunc (this *Stmt) EridStmt() *instruction.EridStmt {\n\treturn this.erid_stmt\n}\n\nfunc (this *Stmt) EriiStmt() *instruction.EriiStmt {\n\treturn this.erii_stmt\n}\n\nfunc (this *Stmt) ErirStmt() *instruction.ErirStmt {\n\treturn this.erir_stmt\n}\n\nfunc (this *Stmt) ErriStmt() *instruction.ErriStmt {\n\treturn this.erri_stmt\n}\n\nfunc (this *Stmt) IStmt() *instruction.IStmt {\n\treturn this.i_stmt\n}\n\nfunc (this *Stmt) NopStmt() *instruction.NopStmt {\n\treturn this.nop_stmt\n}\n\nfunc (this *Stmt) RStmt() *instruction.RStmt {\n\treturn this.r_stmt\n}\n\nfunc (this *Stmt) RciStmt() *instruction.RciStmt {\n\treturn this.rci_stmt\n}\n\nfunc (this *Stmt) RiciStmt() *instruction.RiciStmt {\n\treturn this.rici_stmt\n}\n\nfunc (this *Stmt) RirStmt() *instruction.RirStmt {\n\treturn this.rir_stmt\n}\n\nfunc (this *Stmt) RircStmt() *instruction.RircStmt {\n\treturn this.rirc_stmt\n}\n\nfunc (this *Stmt) RirciStmt() *instruction.RirciStmt {\n\treturn this.rirci_stmt\n}\n\nfunc (this *Stmt) RrStmt() *instruction.RrStmt {\n\treturn this.rr_stmt\n}\n\nfunc (this *Stmt) RrcStmt() *instruction.RrcStmt {\n\treturn this.rrc_stmt\n}\n\nfunc (this *Stmt) RrciStmt() *instruction.RrciStmt {\n\treturn this.rrci_stmt\n}\n\nfunc (this *Stmt) RriStmt() *instruction.RriStmt {\n\treturn this.rri_stmt\n}\n\nfunc (this *Stmt) RricStmt() *instruction.RricStmt {\n\treturn this.rric_stmt\n}\n\nfunc (this *Stmt) RriciStmt() *instruction.RriciStmt {\n\treturn this.rrici_stmt\n}\n\nfunc (this *Stmt) RrrStmt() *instruction.RrrStmt {\n\treturn this.rrr_stmt\n}\n\nfunc (this *Stmt) RrrcStmt() *instruction.RrrcStmt {\n\treturn this.rrrc_stmt\n}\n\nfunc (this *Stmt) RrrciStmt() *instruction.RrrciStmt {\n\treturn this.rrrci_stmt\n}\n\nfunc (this *Stmt) RrriStmt() *instruction.RrriStmt {\n\treturn this.rrri_stmt\n}\n\nfunc (this *Stmt) RrriciStmt() *instruction.RrriciStmt {\n\treturn this.rrrici_stmt\n}\n\nfunc (this *Stmt) SErriStmt() *instruction.SErriStmt {\n\treturn this.s_erri_stmt\n}\n\nfunc (this *Stmt) SRStmt() *instruction.SRStmt {\n\treturn this.s_r_stmt\n}\n\nfunc (this *Stmt) SRciStmt() *instruction.SRciStmt {\n\treturn this.s_rci_stmt\n}\n\nfunc (this *Stmt) SRircStmt() *instruction.SRircStmt {\n\treturn this.s_rirc_stmt\n}\n\nfunc (this *Stmt) SRirciStmt() *instruction.SRirciStmt {\n\treturn this.s_rirci_stmt\n}\n\nfunc (this *Stmt) SRrStmt() *instruction.SRrStmt {\n\treturn this.s_rr_stmt\n}\n\nfunc (this *Stmt) SRrcStmt() *instruction.SRrcStmt {\n\treturn this.s_rrc_stmt\n}\n\nfunc (this *Stmt) SRrciStmt() *instruction.SRrciStmt {\n\treturn this.s_rrci_stmt\n}\n\nfunc (this *Stmt) SRriStmt() *instruction.SRriStmt {\n\treturn this.s_rri_stmt\n}\n\nfunc (this *Stmt) SRricStmt() *instruction.SRricStmt {\n\treturn this.s_rric_stmt\n}\n\nfunc (this *Stmt) SRriciStmt() *instruction.SRriciStmt {\n\treturn this.s_rrici_stmt\n}\n\nfunc (this *Stmt) SRrrStmt() *instruction.SRrrStmt {\n\treturn this.s_rrr_stmt\n}\n\nfunc (this *Stmt) SRrrcStmt() *instruction.SRrrcStmt {\n\treturn this.s_rrrc_stmt\n}\n\nfunc (this *Stmt) SRrrciStmt() *instruction.SRrrciStmt {\n\treturn this.s_rrrci_stmt\n}\n\nfunc (this *Stmt) SRrriStmt() *instruction.SRrriStmt {\n\treturn this.s_rrri_stmt\n}\n\nfunc (this *Stmt) SRrriciStmt() *instruction.SRrriciStmt {\n\treturn this.s_rrrici_stmt\n}\n\nfunc (this *Stmt) BkpStmt() *sugar.BkpStmt {\n\treturn this.bkp_stmt\n}\n\nfunc (this *Stmt) BootRiStmt() *sugar.BootRiStmt {\n\treturn this.boot_ri_stmt\n}\n\nfunc (this *Stmt) CallRiStmt() *sugar.CallRiStmt {\n\treturn this.call_ri_stmt\n}\n\nfunc (this *Stmt) CallRrStmt() *sugar.CallRrStmt {\n\treturn this.call_rr_stmt\n}\n\nfunc (this *Stmt) DivStepDrdiStmt() *sugar.DivStepDrdiStmt {\n\treturn this.div_step_drdi_stmt\n}\n\nfunc (this *Stmt) JeqRiiStmt() *sugar.JeqRiiStmt {\n\treturn this.jeq_rii_stmt\n}\n\nfunc (this *Stmt) JeqRriStmt() *sugar.JeqRriStmt {\n\treturn this.jeq_rri_stmt\n}\n\nfunc (this *Stmt) JnzRiStmt() *sugar.JnzRiStmt {\n\treturn this.jnz_ri_stmt\n}\n\nfunc (this *Stmt) JumpIStmt() *sugar.JumpIStmt {\n\treturn this.jump_i_stmt\n}\n\nfunc (this *Stmt) JumpRStmt() *sugar.JumpRStmt {\n\treturn this.jump_r_stmt\n}\n\nfunc (this *Stmt) LbsRriStmt() *sugar.LbsRriStmt {\n\treturn this.lbs_rri_stmt\n}\n\nfunc (this *Stmt) LbsSRriStmt() *sugar.LbsSRriStmt {\n\treturn this.lbs_s_rri_stmt\n}\n\nfunc (this *Stmt) LdDriStmt() *sugar.LdDriStmt {\n\treturn this.ld_dri_stmt\n}\n\nfunc (this *Stmt) MovdDdStmt() *sugar.MovdDdStmt {\n\treturn this.movd_dd_stmt\n}\n\nfunc (this *Stmt) MoveRiStmt() *sugar.MoveRiStmt {\n\treturn this.move_ri_stmt\n}\n\nfunc (this *Stmt) MoveRiciStmt() *sugar.MoveRiciStmt {\n\treturn this.move_rici_stmt\n}\n\nfunc (this *Stmt) MoveSRiStmt() *sugar.MoveSRiStmt {\n\treturn this.move_s_ri_stmt\n}\n\nfunc (this *Stmt) MoveSRiciStmt() *sugar.MoveSRiciStmt {\n\treturn this.move_s_rici_stmt\n}\n\nfunc (this *Stmt) SbIdRiStmt() *sugar.SbIdRiStmt {\n\treturn this.sb_id_ri_stmt\n}\n\nfunc (this *Stmt) SbIdRiiStmt() *sugar.SbIdRiiStmt {\n\treturn this.sb_id_rii_stmt\n}\n\nfunc (this *Stmt) SbRirStmt() *sugar.SbRirStmt {\n\treturn this.sb_rir_stmt\n}\n\nfunc (this *Stmt) SdRidStmt() *sugar.SdRidStmt {\n\treturn this.sd_rid_stmt\n}\n\nfunc (this *Stmt) StopStmt() *sugar.StopStmt {\n\treturn this.stop_stmt\n}\n\nfunc (this *Stmt) TimeCfgRStmt() *sugar.TimeCfgRStmt {\n\treturn this.time_cfg_r_stmt\n}\n\nfunc (this *Stmt) LabelStmt() *LabelStmt {\n\treturn this.label_stmt\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/bkp_stmt.go",
    "content": "package sugar\n\ntype BkpStmt struct {\n}\n\nfunc (this *BkpStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/boot_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype BootRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *BootRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.RICI_OP_CODE {\n\t\terr := errors.New(\"op code is not an RICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n}\n\nfunc (this *BootRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *BootRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *BootRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/call_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CallRiStmt struct {\n\trc  *expr.Expr\n\timm *expr.Expr\n}\n\nfunc (this *CallRiStmt) Init(rc *expr.Expr, imm *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n}\n\nfunc (this *CallRiStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *CallRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/call_rr_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype CallRrStmt struct {\n\trc *expr.Expr\n\tra *expr.Expr\n}\n\nfunc (this *CallRrStmt) Init(rc *expr.Expr, ra *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.ra = ra\n}\n\nfunc (this *CallRrStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *CallRrStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/div_step_drdi_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype DivStepDrdiStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\tdb      *lexer.Token\n\timm     *expr.Expr\n}\n\nfunc (this *DivStepDrdiStmt) Init(\n\top_code *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\tdb *lexer.Token,\n\timm *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.DRDICI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DRDICI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.db = db\n\tthis.imm = imm\n}\n\nfunc (this *DivStepDrdiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *DivStepDrdiStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *DivStepDrdiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *DivStepDrdiStmt) Db() *lexer.Token {\n\treturn this.db\n}\n\nfunc (this *DivStepDrdiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/jeq_rii_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype JeqRiiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\timm     *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JeqRiiStmt) Init(op_code *expr.Expr, ra *expr.Expr, imm *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.imm = imm\n\tthis.pc = pc\n}\n\nfunc (this *JeqRiiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JeqRiiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JeqRiiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *JeqRiiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/jeq_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype JeqRriStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\trb      *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JeqRriStmt) Init(op_code *expr.Expr, ra *expr.Expr, rb *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.rb = rb\n\tthis.pc = pc\n}\n\nfunc (this *JeqRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JeqRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JeqRriStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n\nfunc (this *JeqRriStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/jnz_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype JnzRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\tpc      *expr.Expr\n}\n\nfunc (this *JnzRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, pc *expr.Expr) {\n\tif op_code.ExprType() != expr.JUMP_OP_CODE {\n\t\terr := errors.New(\"op code is not a jump op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.pc = pc\n}\n\nfunc (this *JnzRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *JnzRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *JnzRiStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/jump_i_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype JumpIStmt struct {\n\tpc *expr.Expr\n}\n\nfunc (this *JumpIStmt) Init(pc *expr.Expr) {\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.pc = pc\n}\n\nfunc (this *JumpIStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/jump_r_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype JumpRStmt struct {\n\tra *expr.Expr\n}\n\nfunc (this *JumpRStmt) Init(ra *expr.Expr) {\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.ra = ra\n}\n\nfunc (this *JumpRStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/lbs_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LbsRriStmt struct {\n\top_code *expr.Expr\n\trc      *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LbsRriStmt) Init(op_code *expr.Expr, rc *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.rc = rc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LbsRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LbsRriStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *LbsRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LbsRriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/lbs_s_rri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LbsSRriStmt struct {\n\top_code *expr.Expr\n\tsuffix  *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LbsSRriStmt) Init(\n\top_code *expr.Expr,\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\tra *expr.Expr,\n\toff *expr.Expr,\n) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LbsSRriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LbsSRriStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *LbsSRriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *LbsSRriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LbsSRriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/ld_dri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype LdDriStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *LdDriStmt) Init(op_code *expr.Expr, dc *lexer.Token, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.LOAD_OP_CODE {\n\t\terr := errors.New(\"op code is not a load op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *LdDriStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *LdDriStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *LdDriStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *LdDriStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/movd_dd_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype MovdDdStmt struct {\n\top_code *expr.Expr\n\tdc      *lexer.Token\n\tdb      *lexer.Token\n}\n\nfunc (this *MovdDdStmt) Init(op_code *expr.Expr, dc *lexer.Token, db *lexer.Token) {\n\tif op_code.ExprType() != expr.DDCI_OP_CODE {\n\t\terr := errors.New(\"op code is not a DDCI op code\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"db is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.dc = dc\n\tthis.db = db\n}\n\nfunc (this *MovdDdStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *MovdDdStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MovdDdStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/move_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype MoveRiStmt struct {\n\trc  *expr.Expr\n\timm *expr.Expr\n}\n\nfunc (this *MoveRiStmt) Init(rc *expr.Expr, imm *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n}\n\nfunc (this *MoveRiStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *MoveRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/move_rici_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype MoveRiciStmt struct {\n\trc        *expr.Expr\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *MoveRiciStmt) Init(rc *expr.Expr, imm *expr.Expr, condition *expr.Expr, pc *expr.Expr) {\n\tif rc.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rc is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.rc = rc\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *MoveRiciStmt) Rc() *expr.Expr {\n\treturn this.rc\n}\n\nfunc (this *MoveRiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *MoveRiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *MoveRiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/move_s_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype MoveSRiStmt struct {\n\tsuffix *expr.Expr\n\tdc     *lexer.Token\n\timm    *expr.Expr\n}\n\nfunc (this *MoveSRiStmt) Init(suffix *expr.Expr, dc *lexer.Token, imm *expr.Expr) {\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n}\n\nfunc (this *MoveSRiStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *MoveSRiStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MoveSRiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/move_s_rici_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype MoveSRiciStmt struct {\n\tsuffix    *expr.Expr\n\tdc        *lexer.Token\n\timm       *expr.Expr\n\tcondition *expr.Expr\n\tpc        *expr.Expr\n}\n\nfunc (this *MoveSRiciStmt) Init(\n\tsuffix *expr.Expr,\n\tdc *lexer.Token,\n\timm *expr.Expr,\n\tcondition *expr.Expr,\n\tpc *expr.Expr,\n) {\n\tif suffix.ExprType() != expr.SUFFIX {\n\t\terr := errors.New(\"suffix is not a suffix\")\n\t\tpanic(err)\n\t}\n\n\tif dc.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif condition.ExprType() != expr.CONDITION {\n\t\terr := errors.New(\"condition is not a condition\")\n\t\tpanic(err)\n\t}\n\n\tif pc.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"pc is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.suffix = suffix\n\tthis.dc = dc\n\tthis.imm = imm\n\tthis.condition = condition\n\tthis.pc = pc\n}\n\nfunc (this *MoveSRiciStmt) Suffix() *expr.Expr {\n\treturn this.suffix\n}\n\nfunc (this *MoveSRiciStmt) Dc() *lexer.Token {\n\treturn this.dc\n}\n\nfunc (this *MoveSRiciStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n\nfunc (this *MoveSRiciStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *MoveSRiciStmt) Pc() *expr.Expr {\n\treturn this.pc\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/sb_id_ri_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SbIdRiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n}\n\nfunc (this *SbIdRiStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n}\n\nfunc (this *SbIdRiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbIdRiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbIdRiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/sb_id_rii_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SbIdRiiStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\timm     *expr.Expr\n}\n\nfunc (this *SbIdRiiStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, imm *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif imm.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"imm is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.imm = imm\n}\n\nfunc (this *SbIdRiiStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbIdRiiStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbIdRiiStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SbIdRiiStmt) Imm() *expr.Expr {\n\treturn this.imm\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/sb_rir_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SbRirStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\trb      *expr.Expr\n}\n\nfunc (this *SbRirStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, rb *expr.Expr) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif rb.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"rb is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.rb = rb\n}\n\nfunc (this *SbRirStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SbRirStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SbRirStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SbRirStmt) Rb() *expr.Expr {\n\treturn this.rb\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/sd_rid_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype SdRidStmt struct {\n\top_code *expr.Expr\n\tra      *expr.Expr\n\toff     *expr.Expr\n\tdb      *lexer.Token\n}\n\nfunc (this *SdRidStmt) Init(op_code *expr.Expr, ra *expr.Expr, off *expr.Expr, db *lexer.Token) {\n\tif op_code.ExprType() != expr.STORE_OP_CODE {\n\t\terr := errors.New(\"op code is not a store op code\")\n\t\tpanic(err)\n\t}\n\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tif off.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"off is not a program counter\")\n\t\tpanic(err)\n\t}\n\n\tif db.TokenType() != lexer.PAIR_REG {\n\t\terr := errors.New(\"dc is not a pair reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.op_code = op_code\n\tthis.ra = ra\n\tthis.off = off\n\tthis.db = db\n}\n\nfunc (this *SdRidStmt) OpCode() *expr.Expr {\n\treturn this.op_code\n}\n\nfunc (this *SdRidStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n\nfunc (this *SdRidStmt) Off() *expr.Expr {\n\treturn this.off\n}\n\nfunc (this *SdRidStmt) Db() *lexer.Token {\n\treturn this.db\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/stop_stmt.go",
    "content": "package sugar\n\ntype StopStmt struct {\n}\n\nfunc (this *StopStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/stmt/sugar/time_cfg_r_stmt.go",
    "content": "package sugar\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n)\n\ntype TimeCfgRStmt struct {\n\tra *expr.Expr\n}\n\nfunc (this *TimeCfgRStmt) Init(ra *expr.Expr) {\n\tif ra.ExprType() != expr.SRC_REG {\n\t\terr := errors.New(\"ra is not a src reg\")\n\t\tpanic(err)\n\t}\n\n\tthis.ra = ra\n}\n\nfunc (this *TimeCfgRStmt) Ra() *expr.Expr {\n\treturn this.ra\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/table.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/lexer\"\n)\n\ntype Table struct {\n\texpr_rules []*Rule\n\tstmt_rules []*Rule\n\n\tstack *Stack\n}\n\nfunc (this *Table) Init(stack *Stack) {\n\tthis.expr_rules = make([]*Rule, 0)\n\tthis.stmt_rules = make([]*Rule, 0)\n\n\tthis.stack = stack\n}\n\nfunc (this *Table) AddExprRule(rule *Rule) {\n\tthis.expr_rules = append(this.expr_rules, rule)\n}\n\nfunc (this *Table) AddStmtRule(rule *Rule) {\n\tthis.stmt_rules = append(this.stmt_rules, rule)\n}\n\nfunc (this *Table) FindReducibleExprRule(token *lexer.Token) (*Rule, []*StackItem) {\n\tfor num := this.stack.NonStmtLength(); num > 0; num-- {\n\t\tstack_items := this.stack.Front(num)\n\n\t\tfor _, expr_rule := range this.expr_rules {\n\t\t\tif expr_rule.IsReducible(stack_items, token) {\n\t\t\t\treturn expr_rule, stack_items\n\t\t\t}\n\t\t}\n\t}\n\treturn nil, []*StackItem{}\n}\n\nfunc (this *Table) FindReducibleStmtRule(token *lexer.Token) (*Rule, []*StackItem) {\n\tif token.TokenType() != lexer.NEW_LINE {\n\t\terr := errors.New(\"token is not a new line\")\n\t\tpanic(err)\n\t}\n\n\tnum := this.stack.NonStmtLength()\n\tstack_items := this.stack.Front(num)\n\n\tfor _, stmt_rule := range this.stmt_rules {\n\t\tif stmt_rule.IsReducible(stack_items, token) {\n\t\t\treturn stmt_rule, stack_items\n\t\t}\n\t}\n\treturn nil, []*StackItem{}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/linker/parser/walker.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/parser/expr\"\n\t\"uPIMulator/src/device/linker/parser/stmt\"\n)\n\ntype ExprCallback func(*expr.Expr)\ntype StmtCallback func(*stmt.Stmt)\n\ntype Walker struct {\n\texpr_callbacks map[expr.ExprType]ExprCallback\n\tstmt_callbacks map[stmt.StmtType]StmtCallback\n}\n\nfunc (this *Walker) Init() {\n\tthis.expr_callbacks = make(map[expr.ExprType]ExprCallback)\n\tthis.stmt_callbacks = make(map[stmt.StmtType]StmtCallback)\n}\n\nfunc (this *Walker) RegisterExprCallback(expr_type expr.ExprType, expr_callback ExprCallback) {\n\tif _, found := this.expr_callbacks[expr_type]; found {\n\t\terr := errors.New(\"expr callbak is already registered\")\n\t\tpanic(err)\n\t}\n\n\tthis.expr_callbacks[expr_type] = expr_callback\n}\n\nfunc (this *Walker) RegisterStmtCallback(stmt_type stmt.StmtType, stmt_callback StmtCallback) {\n\tif _, found := this.stmt_callbacks[stmt_type]; found {\n\t\terr := errors.New(\"stmt callbak is already registered\")\n\t\tpanic(err)\n\t}\n\n\tthis.stmt_callbacks[stmt_type] = stmt_callback\n}\n\nfunc (this *Walker) Walk(ast *Ast) {\n\tfor i := 0; i < ast.Length(); i++ {\n\t\tstmt_ := ast.Get(i)\n\n\t\tstmt_type := stmt_.StmtType()\n\t\tif stmt_type == stmt.ASCII {\n\t\t\tthis.WalkAsciiStmt(stmt_)\n\t\t} else if stmt_type == stmt.ASCIZ {\n\t\t\tthis.WalkAscizStmt(stmt_)\n\t\t} else if stmt_type == stmt.BYTE {\n\t\t\tthis.WalkByteStmt(stmt_)\n\t\t} else if stmt_type == stmt.GLOBAL {\n\t\t\tthis.WalkGlobalStmt(stmt_)\n\t\t} else if stmt_type == stmt.LONG_PROGRAM_COUNTER {\n\t\t\tthis.WalkLongProgramCounterStmt(stmt_)\n\t\t} else if stmt_type == stmt.LONG_SECTION_NAME {\n\t\t\tthis.WalkLongSectionNameStmt(stmt_)\n\t\t} else if stmt_type == stmt.P2_ALIGN {\n\t\t\tthis.WalkP2AlignStmt(stmt_)\n\t\t} else if stmt_type == stmt.QUAD {\n\t\t\tthis.WalkQuadStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_IDENTIFIER_NUMBER {\n\t\t\tthis.WalkSectionIdentifierNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_IDENTIFIER {\n\t\t\tthis.WalkSectionIdentifierStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STACK_SIZES {\n\t\t\tthis.WalkSectionStackSizesStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STRING_NUMBER {\n\t\t\tthis.WalkSectionStringNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.SECTION_STRING {\n\t\t\tthis.WalkSectionStringStmt(stmt_)\n\t\t} else if stmt_type == stmt.SET {\n\t\t\tthis.WalkSetStmt(stmt_)\n\t\t} else if stmt_type == stmt.SHORT {\n\t\t\tthis.WalkShortStmt(stmt_)\n\t\t} else if stmt_type == stmt.SIZE {\n\t\t\tthis.WalkSizeStmt(stmt_)\n\t\t} else if stmt_type == stmt.TEXT {\n\t\t\tthis.WalkTextStmt(stmt_)\n\t\t} else if stmt_type == stmt.ZERO_DOUBLE_NUMBER {\n\t\t\tthis.WalkZeroDoubleNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.ZERO_SINGLE_NUMBER {\n\t\t\tthis.WalkZeroSingleNumberStmt(stmt_)\n\t\t} else if stmt_type == stmt.CI {\n\t\t\tthis.WalkCiStmt(stmt_)\n\t\t} else if stmt_type == stmt.DDCI {\n\t\t\tthis.WalkDdciStmt(stmt_)\n\t\t} else if stmt_type == stmt.DMA_RRI {\n\t\t\tthis.WalkDmaRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.DRDICI {\n\t\t\tthis.WalkDrdiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.EDRI {\n\t\t\tthis.WalkEdriStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERID {\n\t\t\tthis.WalkEridStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERII {\n\t\t\tthis.WalkEriiStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERIR {\n\t\t\tthis.WalkErirStmt(stmt_)\n\t\t} else if stmt_type == stmt.ERRI {\n\t\t\tthis.WalkErriStmt(stmt_)\n\t\t} else if stmt_type == stmt.I {\n\t\t\tthis.WalkIStmt(stmt_)\n\t\t} else if stmt_type == stmt.NOP {\n\t\t\tthis.WalkNopStmt(stmt_)\n\t\t} else if stmt_type == stmt.RCI {\n\t\t\tthis.WalkRciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RICI {\n\t\t\tthis.WalkRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIRCI {\n\t\t\tthis.WalkRirciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIRC {\n\t\t\tthis.WalkRircStmt(stmt_)\n\t\t} else if stmt_type == stmt.RIR {\n\t\t\tthis.WalkRirStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRCI {\n\t\t\tthis.WalkRrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRC {\n\t\t\tthis.WalkRrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRICI {\n\t\t\tthis.WalkRriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRIC {\n\t\t\tthis.WalkRricStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRI {\n\t\t\tthis.WalkRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRCI {\n\t\t\tthis.WalkRrrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRC {\n\t\t\tthis.WalkRrrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRICI {\n\t\t\tthis.WalkRrriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRRI {\n\t\t\tthis.WalkRrriStmt(stmt_)\n\t\t} else if stmt_type == stmt.RRR {\n\t\t\tthis.WalkRrrStmt(stmt_)\n\t\t} else if stmt_type == stmt.RR {\n\t\t\tthis.WalkRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.R {\n\t\t\tthis.WalkRStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_ERRI {\n\t\t\tthis.WalkSErriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RCI {\n\t\t\tthis.WalkSRciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RIRCI {\n\t\t\tthis.WalkSRirciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RIRC {\n\t\t\tthis.WalkSRircStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRCI {\n\t\t\tthis.WalkSRrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRC {\n\t\t\tthis.WalkSRrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRICI {\n\t\t\tthis.WalkSRriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRIC {\n\t\t\tthis.WalkSRricStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRI {\n\t\t\tthis.WalkSRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRCI {\n\t\t\tthis.WalkSRrrciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRC {\n\t\t\tthis.WalkSRrrcStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRICI {\n\t\t\tthis.WalkSRrriciStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRRI {\n\t\t\tthis.WalkSRrriStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RRR {\n\t\t\tthis.WalkSRrrStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_RR {\n\t\t\tthis.WalkSRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.S_R {\n\t\t\tthis.WalkSRStmt(stmt_)\n\t\t} else if stmt_type == stmt.BKP {\n\t\t\tthis.WalkBkpStmt(stmt_)\n\t\t} else if stmt_type == stmt.BOOT_RI {\n\t\t\tthis.WalkBootRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.CALL_RI {\n\t\t\tthis.WalkCallRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.CALL_RR {\n\t\t\tthis.WalkCallRrStmt(stmt_)\n\t\t} else if stmt_type == stmt.DIV_STEP_DRDI {\n\t\t\tthis.WalkDivStepDrdiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JEQ_RII {\n\t\t\tthis.WalkJeqRiiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JEQ_RRI {\n\t\t\tthis.WalkJeqRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.JNZ_RI {\n\t\t\tthis.WalkJnzRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.JUMP_I {\n\t\t\tthis.WalkJumpIStmt(stmt_)\n\t\t} else if stmt_type == stmt.JUMP_R {\n\t\t\tthis.WalkJumpRStmt(stmt_)\n\t\t} else if stmt_type == stmt.LBS_RRI {\n\t\t\tthis.WalkLbsRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.LBS_S_RRI {\n\t\t\tthis.WalkLbsSRriStmt(stmt_)\n\t\t} else if stmt_type == stmt.LD_DRI {\n\t\t\tthis.WalkLdDriStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVD_DD {\n\t\t\tthis.WalkMovdDdStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_RICI {\n\t\t\tthis.WalkMoveRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_RI {\n\t\t\tthis.WalkMoveRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_S_RICI {\n\t\t\tthis.WalkMoveSRiciStmt(stmt_)\n\t\t} else if stmt_type == stmt.MOVE_S_RI {\n\t\t\tthis.WalkMoveSRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_ID_RII {\n\t\t\tthis.WalkSbIdRiiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_ID_RI {\n\t\t\tthis.WalkSbIdRiStmt(stmt_)\n\t\t} else if stmt_type == stmt.SB_RIR {\n\t\t\tthis.WalkSbRirStmt(stmt_)\n\t\t} else if stmt_type == stmt.SD_RID {\n\t\t\tthis.WalkSdRidStmt(stmt_)\n\t\t} else if stmt_type == stmt.STOP {\n\t\t\tthis.WalkStopStmt(stmt_)\n\t\t} else if stmt_type == stmt.TIME_CFG_R {\n\t\t\tthis.WalkTimeCfgRStmt(stmt_)\n\t\t} else if stmt_type == stmt.LABEL {\n\t\t\tthis.WalkLabelStmt(stmt_)\n\t\t} else {\n\t\t\tcontinue\n\t\t}\n\t}\n}\n\nfunc (this *Walker) WalkBinaryAddExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.BINARY_ADD {\n\t\terr := errors.New(\"expr type is not binary add expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.BINARY_ADD]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tbinary_add_expr := expr_.BinaryAddExpr()\n\n\toperand1 := binary_add_expr.Operand1()\n\toperand2 := binary_add_expr.Operand2()\n\n\tthis.WalkPrimaryExpr(operand1)\n\tthis.WalkPrimaryExpr(operand2)\n}\n\nfunc (this *Walker) WalkBinarySubExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.BINARY_SUB {\n\t\terr := errors.New(\"expr type is not binary sub expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.BINARY_SUB]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tbinary_sub_expr := expr_.BinarySubExpr()\n\n\toperand1 := binary_sub_expr.Operand1()\n\toperand2 := binary_sub_expr.Operand2()\n\n\tthis.WalkPrimaryExpr(operand1)\n\tthis.WalkPrimaryExpr(operand2)\n}\n\nfunc (this *Walker) WalkNegativeNumberExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.NEGATIVE_NUMBER {\n\t\terr := errors.New(\"expr type is not negative number expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.NEGATIVE_NUMBER]; found {\n\t\texpr_callback(expr_)\n\t}\n}\n\nfunc (this *Walker) WalkPrimaryExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"expr type is not primary\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.PRIMARY]; found {\n\t\texpr_callback(expr_)\n\t}\n}\n\nfunc (this *Walker) WalkProgramCounterExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() != expr.PROGRAM_COUNTER {\n\t\terr := errors.New(\"expr type is not program counter expr\")\n\t\tpanic(err)\n\t}\n\n\tif expr_callback, found := this.expr_callbacks[expr.PROGRAM_COUNTER]; found {\n\t\texpr_callback(expr_)\n\t}\n\n\tprogram_counter_expr := expr_.ProgramCounterExpr()\n\n\tchild_expr := program_counter_expr.Expr()\n\tchild_expr_type := child_expr.ExprType()\n\n\tif child_expr_type == expr.PRIMARY {\n\t\tthis.WalkPrimaryExpr(child_expr)\n\t} else if child_expr_type == expr.NEGATIVE_NUMBER {\n\t\tthis.WalkNegativeNumberExpr(child_expr)\n\t} else if child_expr_type == expr.BINARY_ADD {\n\t\tthis.WalkBinaryAddExpr(child_expr)\n\t} else if child_expr_type == expr.BINARY_SUB {\n\t\tthis.WalkBinarySubExpr(child_expr)\n\t} else {\n\t\terr := errors.New(\"child expr is not valid for a program counter expr\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Walker) WalkAsciiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ASCII {\n\t\terr := errors.New(\"stmt type is not an ASCII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ASCII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkAscizStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ASCIZ {\n\t\terr := errors.New(\"stmt type is not an ASCIZ stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ASCIZ]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkByteStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BYTE {\n\t\terr := errors.New(\"stmt type is not a byte stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BYTE]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tbyte_stmt := stmt_.ByteStmt()\n\n\texpr_ := byte_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkGlobalStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.GLOBAL {\n\t\terr := errors.New(\"stmt type is not a global stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.GLOBAL]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tglobal_stmt := stmt_.GlobalStmt()\n\n\texpr_ := global_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkLongProgramCounterStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LONG_PROGRAM_COUNTER {\n\t\terr := errors.New(\"stmt type is not a long program counter stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LONG_PROGRAM_COUNTER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlong_program_counter_stmt := stmt_.LongProgramCounterStmt()\n\n\texpr_ := long_program_counter_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkLongSectionNameStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LONG_SECTION_NAME {\n\t\terr := errors.New(\"stmt type is not a long section name stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LONG_SECTION_NAME]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkP2AlignStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.P2_ALIGN {\n\t\terr := errors.New(\"stmt type is not a p2align stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.P2_ALIGN]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkQuadStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.QUAD {\n\t\terr := errors.New(\"stmt type is not a quad stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.QUAD]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tquad_stmt := stmt_.QuadStmt()\n\n\texpr_ := quad_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkSectionIdentifierNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_IDENTIFIER_NUMBER {\n\t\terr := errors.New(\"stmt type is not a section identifier number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_IDENTIFIER_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionIdentifierStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_IDENTIFIER {\n\t\terr := errors.New(\"stmt type is not a section identifier stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_IDENTIFIER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionStackSizesStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STACK_SIZES {\n\t\terr := errors.New(\"stmt type is not a section stack sizes stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STACK_SIZES]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\nfunc (this *Walker) WalkSectionStringNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STRING_NUMBER {\n\t\terr := errors.New(\"stmt type is not a section string number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STRING_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSectionStringStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SECTION_STRING {\n\t\terr := errors.New(\"stmt type is not a section string stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SECTION_STRING]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSetStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SET {\n\t\terr := errors.New(\"stmt type is not a set stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SET]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tset_stmt := stmt_.SetStmt()\n\n\texpr1 := set_stmt.Expr1()\n\texpr2 := set_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkShortStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SHORT {\n\t\terr := errors.New(\"stmt type is not a short stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SHORT]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tshort_stmt := stmt_.ShortStmt()\n\n\texpr_ := short_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkSizeStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SIZE {\n\t\terr := errors.New(\"stmt type is not a size stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SIZE]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsize_stmt := stmt_.SizeStmt()\n\n\texpr1 := size_stmt.Expr1()\n\texpr2 := size_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkTextStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.TEXT {\n\t\terr := errors.New(\"stmt type is not a text stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.TEXT]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkZeroDoubleNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ZERO_DOUBLE_NUMBER {\n\t\terr := errors.New(\"stmt type is not a zero double number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ZERO_DOUBLE_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tzero_double_number_stmt := stmt_.ZeroDoubleNumberStmt()\n\n\texpr1 := zero_double_number_stmt.Expr1()\n\texpr2 := zero_double_number_stmt.Expr2()\n\n\tthis.WalkProgramCounterExpr(expr1)\n\tthis.WalkProgramCounterExpr(expr2)\n}\n\nfunc (this *Walker) WalkZeroSingleNumberStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ZERO_SINGLE_NUMBER {\n\t\terr := errors.New(\"stmt type is not a zero single number stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ZERO_SINGLE_NUMBER]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tzero_single_number_stmt := stmt_.ZeroSingleNumberStmt()\n\n\texpr_ := zero_single_number_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n\nfunc (this *Walker) WalkCiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CI {\n\t\terr := errors.New(\"stmt type is not a CI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tci_stmt := stmt_.CiStmt()\n\n\tpc := ci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkDdciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DDCI {\n\t\terr := errors.New(\"stmt type is not a DDCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DDCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tddci_stmt := stmt_.DdciStmt()\n\n\tpc := ddci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkDmaRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DMA_RRI {\n\t\terr := errors.New(\"stmt type is not a DMA_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DMA_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdma_rri_stmt := stmt_.DmaRriStmt()\n\n\timm := dma_rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkDrdiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DRDICI {\n\t\terr := errors.New(\"stmt type is not a DRDICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DRDICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdrdici_stmt := stmt_.DrdiciStmt()\n\n\timm := drdici_stmt.Imm()\n\tpc := drdici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkEdriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.EDRI {\n\t\terr := errors.New(\"stmt type is not an EDRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.EDRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tedri_stmt := stmt_.EdriStmt()\n\n\toff := edri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkEridStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERID {\n\t\terr := errors.New(\"stmt type is not an ERID stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERID]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terid_stmt := stmt_.EridStmt()\n\n\toff := erid_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkEriiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERII {\n\t\terr := errors.New(\"stmt type is not an ERII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terii_stmt := stmt_.EriiStmt()\n\n\toff := erii_stmt.Off()\n\timm := erii_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(off)\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkErirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERIR {\n\t\terr := errors.New(\"stmt type is not an ERIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terir_stmt := stmt_.ErirStmt()\n\n\toff := erir_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkErriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.ERRI {\n\t\terr := errors.New(\"stmt type is not an ERRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.ERRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\terri_stmt := stmt_.ErriStmt()\n\n\toff := erri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkIStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.I {\n\t\terr := errors.New(\"stmt type is not an I stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.I]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ti_stmt := stmt_.IStmt()\n\n\timm := i_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkNopStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.NOP {\n\t\terr := errors.New(\"stmt type is not a NOP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.NOP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RCI {\n\t\terr := errors.New(\"stmt type is not an RCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trci_stmt := stmt_.RciStmt()\n\n\tpc := rci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RICI {\n\t\terr := errors.New(\"stmt type is not an RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trici_stmt := stmt_.RiciStmt()\n\n\timm := rici_stmt.Imm()\n\tpc := rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRirciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIRCI {\n\t\terr := errors.New(\"stmt type is not an RIRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trirci_stmt := stmt_.RirciStmt()\n\n\timm := rirci_stmt.Imm()\n\tpc := rirci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRircStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIRC {\n\t\terr := errors.New(\"stmt type is not an RIRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trirc_stmt := stmt_.RircStmt()\n\n\timm := rirc_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RIR {\n\t\terr := errors.New(\"stmt type is not an RIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trir_stmt := stmt_.RirStmt()\n\n\timm := rir_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRCI {\n\t\terr := errors.New(\"stmt type is not an RRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrci_stmt := stmt_.RrciStmt()\n\n\tpc := rrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRC {\n\t\terr := errors.New(\"stmt type is not an RRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRICI {\n\t\terr := errors.New(\"stmt type is not an RRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrici_stmt := stmt_.RriciStmt()\n\n\timm := rrici_stmt.Imm()\n\tpc := rrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRricStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRIC {\n\t\terr := errors.New(\"stmt type is not an RRIC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRIC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trric_stmt := stmt_.RricStmt()\n\n\timm := rric_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRI {\n\t\terr := errors.New(\"stmt type is not an RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trri_stmt := stmt_.RriStmt()\n\n\timm := rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRCI {\n\t\terr := errors.New(\"stmt type is not an RRRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrrci_stmt := stmt_.RrrciStmt()\n\n\tpc := rrrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRC {\n\t\terr := errors.New(\"stmt type is not an RRRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRrriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRICI {\n\t\terr := errors.New(\"stmt type is not an RRRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrrici_stmt := stmt_.RrriciStmt()\n\n\timm := rrrici_stmt.Imm()\n\tpc := rrrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkRrriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRRI {\n\t\terr := errors.New(\"stmt type is not an RRRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\trrri_stmt := stmt_.RrriStmt()\n\n\timm := rrri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkRrrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RRR {\n\t\terr := errors.New(\"stmt type is not an RRR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.RR {\n\t\terr := errors.New(\"stmt type is not an RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.R {\n\t\terr := errors.New(\"stmt type is not an R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSErriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_ERRI {\n\t\terr := errors.New(\"stmt type is not a S_ERRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_ERRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_erri_stmt := stmt_.SErriStmt()\n\n\toff := s_erri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSRciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RCI {\n\t\terr := errors.New(\"stmt type is not a S_RCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rci_stmt := stmt_.SRciStmt()\n\n\tpc := s_rci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRirciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RIRCI {\n\t\terr := errors.New(\"stmt type is not a S_RIRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RIRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rirci_stmt := stmt_.SRirciStmt()\n\n\timm := s_rirci_stmt.Imm()\n\tpc := s_rirci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRircStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RIRC {\n\t\terr := errors.New(\"stmt type is not a S_RIRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RIRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rirc_stmt := stmt_.SRircStmt()\n\n\timm := s_rirc_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRCI {\n\t\terr := errors.New(\"stmt type is not a S_RRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrci_stmt := stmt_.SRrciStmt()\n\n\tpc := s_rrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRC {\n\t\terr := errors.New(\"stmt type is not a S_RRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRICI {\n\t\terr := errors.New(\"stmt type is not a S_RRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrici_stmt := stmt_.SRriciStmt()\n\n\timm := s_rrici_stmt.Imm()\n\tpc := s_rrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRricStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRIC {\n\t\terr := errors.New(\"stmt type is not a S_RRIC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRIC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rric_stmt := stmt_.SRricStmt()\n\n\timm := s_rric_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRI {\n\t\terr := errors.New(\"stmt type is not a S_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rri_stmt := stmt_.SRriStmt()\n\n\timm := s_rri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrrciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRCI {\n\t\terr := errors.New(\"stmt type is not an S_RRRCI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRCI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrrci_stmt := stmt_.SRrrciStmt()\n\n\tpc := s_rrrci_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrrcStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRC {\n\t\terr := errors.New(\"stmt type is not an S_RRRC stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.RRRC]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRrriciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRICI {\n\t\terr := errors.New(\"stmt type is not a S_RRRICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrrici_stmt := stmt_.SRrriciStmt()\n\n\timm := s_rrrici_stmt.Imm()\n\tpc := s_rrrici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkSRrriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRRI {\n\t\terr := errors.New(\"stmt type is not a S_RRRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\ts_rrri_stmt := stmt_.SRrriStmt()\n\n\timm := s_rrri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSRrrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RRR {\n\t\terr := errors.New(\"stmt type is not a RRR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RRR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_RR {\n\t\terr := errors.New(\"stmt type is not a S_RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkSRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.S_R {\n\t\terr := errors.New(\"stmt type is not a S_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.S_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkBkpStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BKP {\n\t\terr := errors.New(\"stmt type is not a BKP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BKP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkBootRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.BOOT_RI {\n\t\terr := errors.New(\"stmt type is not a BOOT_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.BOOT_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tboot_ri_stmt := stmt_.BootRiStmt()\n\n\timm := boot_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkCallRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CALL_RI {\n\t\terr := errors.New(\"stmt type is not a CALL_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CALL_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tcall_ri_stmt := stmt_.CallRiStmt()\n\n\timm := call_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkCallRrStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.CALL_RR {\n\t\terr := errors.New(\"stmt type is not a CALL_RR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.CALL_RR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkDivStepDrdiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.DIV_STEP_DRDI {\n\t\terr := errors.New(\"stmt type is not a DIV_STEP_DRDI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.DIV_STEP_DRDI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tdiv_step_drdi_stmt := stmt_.DivStepDrdiStmt()\n\n\timm := div_step_drdi_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkJeqRiiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JEQ_RII {\n\t\terr := errors.New(\"stmt type is not a JEQ_RII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JEQ_RII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjeq_rii_stmt := stmt_.JeqRiiStmt()\n\n\timm := jeq_rii_stmt.Imm()\n\tpc := jeq_rii_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJeqRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JEQ_RRI {\n\t\terr := errors.New(\"stmt type is not a JEQ_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JEQ_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjeq_rri_stmt := stmt_.JeqRriStmt()\n\n\tpc := jeq_rri_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJnzRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JNZ_RI {\n\t\terr := errors.New(\"stmt type is not a JNZ_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JNZ_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjnz_ri_stmt := stmt_.JnzRiStmt()\n\n\tpc := jnz_ri_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJumpIStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JUMP_I {\n\t\terr := errors.New(\"stmt type is not a JUMP_I stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JUMP_I]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tjump_i_stmt := stmt_.JumpIStmt()\n\n\tpc := jump_i_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkJumpRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.JUMP_R {\n\t\terr := errors.New(\"stmt type is not a JUMP_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.JUMP_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkLbsRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LBS_RRI {\n\t\terr := errors.New(\"stmt type is not a LBS_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LBS_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlbs_rri_stmt := stmt_.LbsRriStmt()\n\n\toff := lbs_rri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkLbsSRriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LBS_S_RRI {\n\t\terr := errors.New(\"stmt type is not a LBS_S_RRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LBS_S_RRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlbs_s_rri_stmt := stmt_.LbsSRriStmt()\n\n\toff := lbs_s_rri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkLdDriStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LD_DRI {\n\t\terr := errors.New(\"stmt type is not a LD_DRI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LD_DRI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tld_dri_stmt := stmt_.LdDriStmt()\n\n\toff := ld_dri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkMovdDdStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVD_DD {\n\t\terr := errors.New(\"stmt type is not a MOVD_DD stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVD_DD]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkMoveRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_RICI {\n\t\terr := errors.New(\"stmt type is not a MOVE_RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_rici_stmt := stmt_.MoveRiciStmt()\n\n\timm := move_rici_stmt.Imm()\n\tpc := move_rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkMoveRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_RI {\n\t\terr := errors.New(\"stmt type is not a MOVE_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_ri_stmt := stmt_.MoveRiStmt()\n\n\timm := move_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkMoveSRiciStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_S_RICI {\n\t\terr := errors.New(\"stmt type is not a MOVE_S_RICI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_S_RICI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_s_rici_stmt := stmt_.MoveSRiciStmt()\n\n\timm := move_s_rici_stmt.Imm()\n\tpc := move_s_rici_stmt.Pc()\n\n\tthis.WalkProgramCounterExpr(imm)\n\tthis.WalkProgramCounterExpr(pc)\n}\n\nfunc (this *Walker) WalkMoveSRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.MOVE_S_RI {\n\t\terr := errors.New(\"stmt type is not a MOVE_S_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.MOVE_S_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tmove_s_ri_stmt := stmt_.MoveSRiStmt()\n\n\timm := move_s_ri_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSbIdRiiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_ID_RII {\n\t\terr := errors.New(\"stmt type is not a SB_ID_RII stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_ID_RII]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_id_rii_stmt := stmt_.SbIdRiiStmt()\n\n\toff := sb_id_rii_stmt.Off()\n\timm := sb_id_rii_stmt.Imm()\n\n\tthis.WalkProgramCounterExpr(off)\n\tthis.WalkProgramCounterExpr(imm)\n}\n\nfunc (this *Walker) WalkSbIdRiStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_ID_RI {\n\t\terr := errors.New(\"stmt type is not a SB_ID_RI stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_ID_RI]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_id_ri_stmt := stmt_.SbIdRiStmt()\n\n\toff := sb_id_ri_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSbRirStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SB_RIR {\n\t\terr := errors.New(\"stmt type is not a SB_RIR stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SB_RIR]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsb_rir_stmt := stmt_.SbRirStmt()\n\n\toff := sb_rir_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkSdRidStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.SD_RID {\n\t\terr := errors.New(\"stmt type is not a SD_RID stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.SD_RID]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tsd_rid_stmt := stmt_.SdRidStmt()\n\n\toff := sd_rid_stmt.Off()\n\n\tthis.WalkProgramCounterExpr(off)\n}\n\nfunc (this *Walker) WalkStopStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.STOP {\n\t\terr := errors.New(\"stmt type is not a STOP stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.STOP]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkTimeCfgRStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.TIME_CFG_R {\n\t\terr := errors.New(\"stmt type is not a TIME_CFG_R stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.TIME_CFG_R]; found {\n\t\tstmt_callback(stmt_)\n\t}\n}\n\nfunc (this *Walker) WalkLabelStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() != stmt.LABEL {\n\t\terr := errors.New(\"stmt type is not a LABEL stmt\")\n\t\tpanic(err)\n\t}\n\n\tif stmt_callback, found := this.stmt_callbacks[stmt.LABEL]; found {\n\t\tstmt_callback(stmt_)\n\t}\n\n\tlabel_stmt := stmt_.LabelStmt()\n\n\texpr_ := label_stmt.Expr()\n\n\tthis.WalkProgramCounterExpr(expr_)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/channel/channel.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu\"\n\t\"uPIMulator/src/device/simulator/rank\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Channel struct {\n\tchannel_id int\n\tranks      []*rank.Rank\n\n\tinput_q    *ChannelCommandQ\n\tready_q    *ChannelCommandQ\n\tscoreboard map[*rank.RankCommand]*ChannelCommand\n}\n\nfunc (this *Channel) Init(channel_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\n\tthis.ranks = make([]*rank.Rank, 0)\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tfor i := 0; i < num_ranks_per_channel; i++ {\n\t\trank_ := new(rank.Rank)\n\t\trank_.Init(channel_id, i, command_line_parser)\n\t\tthis.ranks = append(this.ranks, rank_)\n\t}\n\n\tthis.input_q = new(ChannelCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.ready_q = new(ChannelCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.scoreboard = make(map[*rank.RankCommand]*ChannelCommand)\n}\n\nfunc (this *Channel) Fini() {\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Fini()\n\t}\n\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Channel) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Channel) NumRanks() int {\n\treturn len(this.ranks)\n}\n\nfunc (this *Channel) Ranks() []*rank.Rank {\n\treturn this.ranks\n}\n\nfunc (this *Channel) Dpus() []*dpu.Dpu {\n\tdpus := make([]*dpu.Dpu, 0)\n\n\tfor _, rank_ := range this.ranks {\n\t\tdpus = append(dpus, rank_.Dpus()...)\n\t}\n\n\treturn dpus\n}\n\nfunc (this *Channel) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Channel) Push(channel_command *ChannelCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"channel cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(channel_command)\n}\n\nfunc (this *Channel) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Channel) Pop() *ChannelCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"channel cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Channel) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Cycle()\n\t}\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Channel) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tchannel_command, _ := this.input_q.Front(0)\n\n\t\trank_id := channel_command.RankId()\n\t\tif this.ranks[rank_id].CanPush() {\n\t\t\tthis.input_q.Pop()\n\n\t\t\trank_command := channel_command.RankCommand()\n\n\t\t\tthis.ranks[rank_id].Push(rank_command)\n\t\t\tthis.scoreboard[rank_command] = channel_command\n\t\t}\n\t}\n}\n\nfunc (this *Channel) ServiceReadyQ() {\n\tfor _, rank_ := range this.ranks {\n\t\tif rank_.CanPop() && this.ready_q.CanPush(1) {\n\t\t\trank_command := rank_.Pop()\n\t\t\tchannel_command := this.scoreboard[rank_command]\n\n\t\t\tthis.ready_q.Push(channel_command)\n\t\t\tdelete(this.scoreboard, rank_command)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/channel/channel_command.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/device/simulator/rank\"\n)\n\ntype ChannelCommand struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\trank_command *rank.RankCommand\n\tdma_command  *dram.DmaCommand\n}\n\nfunc (this *ChannelCommand) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tdma_command *dram.DmaCommand,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.rank_command = new(rank.RankCommand)\n\tthis.rank_command.Init(channel_id, rank_id, dpu_id, dma_command)\n\n\tthis.dma_command = dma_command\n}\n\nfunc (this *ChannelCommand) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *ChannelCommand) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *ChannelCommand) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *ChannelCommand) RankCommand() *rank.RankCommand {\n\treturn this.rank_command\n}\n\nfunc (this *ChannelCommand) DmaCommand() *dram.DmaCommand {\n\treturn this.dma_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/channel/channel_command_q.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n)\n\ntype ChannelCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tchannel_commands []*ChannelCommand\n\tcycles           []int64\n}\n\nfunc (this *ChannelCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.channel_commands = make([]*ChannelCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *ChannelCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"channel command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ChannelCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *ChannelCommandQ) Length() int {\n\treturn len(this.channel_commands)\n}\n\nfunc (this *ChannelCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *ChannelCommandQ) IsEmpty() bool {\n\treturn len(this.channel_commands) == 0\n}\n\nfunc (this *ChannelCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.channel_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelCommandQ) Push(channel_command *ChannelCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_commands = append(this.channel_commands, channel_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *ChannelCommandQ) PushWithTimer(channel_command *ChannelCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_commands = append(this.channel_commands, channel_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *ChannelCommandQ) CanPop(num_items int) bool {\n\tif len(this.channel_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelCommandQ) Pop() *ChannelCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"channel command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tchannel_command := this.channel_commands[0]\n\n\tthis.channel_commands = this.channel_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn channel_command\n}\n\nfunc (this *ChannelCommandQ) Front(pos int) (*ChannelCommand, int64) {\n\treturn this.channel_commands[pos], this.cycles[pos]\n}\n\nfunc (this *ChannelCommandQ) Remove(pos int) {\n\tthis.channel_commands = append(this.channel_commands[:pos], this.channel_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *ChannelCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/control_interface.go",
    "content": "package dpu\n\nimport (\n\t\"errors\"\n)\n\ntype ControlInterface struct {\n\tboot bool\n}\n\nfunc (this *ControlInterface) Init() {\n\tthis.boot = false\n}\n\nfunc (this *ControlInterface) Boot() bool {\n\treturn this.boot\n}\n\nfunc (this *ControlInterface) SetBoot() {\n\tif this.boot {\n\t\terr := errors.New(\"control interface is already booted\")\n\t\tpanic(err)\n\t}\n\n\tthis.boot = true\n}\n\nfunc (this *ControlInterface) UnsetBoot() {\n\tif !this.boot {\n\t\terr := errors.New(\"control interface is not booted\")\n\t\tpanic(err)\n\t}\n\n\tthis.boot = false\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dpu.go",
    "content": "package dpu\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/device/simulator/dpu/logic\"\n\t\"uPIMulator/src/device/simulator/dpu/sram\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Dpu struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tlogic_frequency  int64\n\tmemory_frequency int64\n\tfrequency_ratio  float64\n\tcycles           int64\n\n\tcontrol_interface *ControlInterface\n\tthreads           []*logic.Thread\n\tthread_scheduler  *logic.ThreadScheduler\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\twram              *sram.Wram\n\tmram              *dram.Mram\n\toperand_collector *logic.OperandCollector\n\tmemory_controller *dram.MemoryController\n\tdma               *logic.Dma\n\tlogic             *logic.Logic\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *Dpu) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.logic_frequency = command_line_parser.IntParameter(\"logic_frequency\")\n\tthis.memory_frequency = command_line_parser.IntParameter(\"memory_frequency\")\n\tthis.frequency_ratio = float64(this.memory_frequency) / float64(this.logic_frequency)\n\tthis.cycles = 0\n\n\tthis.control_interface = new(ControlInterface)\n\tthis.control_interface.Init()\n\n\tthis.threads = make([]*logic.Thread, 0)\n\tnum_threads := int(command_line_parser.IntParameter(\"num_tasklets\"))\n\tfor i := 0; i < num_threads; i++ {\n\t\tthread := new(logic.Thread)\n\t\tthread.Init(i)\n\t\tthis.threads = append(this.threads, thread)\n\t}\n\n\tthis.thread_scheduler = new(logic.ThreadScheduler)\n\tthis.thread_scheduler.Init(channel_id, rank_id, dpu_id, this.threads, command_line_parser)\n\n\tthis.atomic = new(sram.Atomic)\n\tthis.atomic.Init()\n\n\tthis.iram = new(sram.Iram)\n\tthis.iram.Init()\n\n\tthis.wram = new(sram.Wram)\n\tthis.wram.Init()\n\n\tthis.mram = new(dram.Mram)\n\tthis.mram.Init(command_line_parser)\n\n\tthis.operand_collector = new(logic.OperandCollector)\n\tthis.operand_collector.Init()\n\tthis.operand_collector.ConnectWram(this.wram)\n\n\tthis.memory_controller = new(dram.MemoryController)\n\tthis.memory_controller.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\tthis.memory_controller.ConnectMram(this.mram)\n\n\tthis.dma = new(logic.Dma)\n\tthis.dma.Init()\n\tthis.dma.ConnectAtomic(this.atomic)\n\tthis.dma.ConnectIram(this.iram)\n\tthis.dma.ConnectOperandCollector(this.operand_collector)\n\tthis.dma.ConnectMemoryController(this.memory_controller)\n\n\tthis.logic = new(logic.Logic)\n\tthis.logic.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\tthis.logic.ConnectThreadScheduler(this.thread_scheduler)\n\tthis.logic.ConnectAtomic(this.atomic)\n\tthis.logic.ConnectIram(this.iram)\n\tthis.logic.ConnectOperandCollector(this.operand_collector)\n\tthis.logic.ConnectDma(this.dma)\n\n\tname := fmt.Sprintf(\"DPU%d-%d-%d\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *Dpu) Fini() {\n\tfor _, thread := range this.threads {\n\t\tthread.Fini()\n\t}\n\n\tthis.atomic.Fini()\n\tthis.iram.Fini()\n\tthis.wram.Fini()\n\tthis.mram.Fini()\n\n\tthis.operand_collector.Fini()\n\tthis.memory_controller.Fini()\n\n\tthis.logic.Fini()\n\tthis.dma.Fini()\n}\n\nfunc (this *Dpu) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Dpu) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Dpu) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *Dpu) ThreadScheduler() *logic.ThreadScheduler {\n\treturn this.thread_scheduler\n}\n\nfunc (this *Dpu) Logic() *logic.Logic {\n\treturn this.logic\n}\n\nfunc (this *Dpu) MemoryController() *dram.MemoryController {\n\treturn this.memory_controller\n}\n\nfunc (this *Dpu) Dma() *logic.Dma {\n\treturn this.dma\n}\n\nfunc (this *Dpu) Threads() []*logic.Thread {\n\treturn this.threads\n}\n\nfunc (this *Dpu) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *Dpu) Boot() {\n\tthis.control_interface.SetBoot()\n\tthis.thread_scheduler.Boot(0)\n}\n\nfunc (this *Dpu) Unboot() {\n\tthis.control_interface.UnsetBoot()\n\tthis.thread_scheduler.Unboot()\n}\n\nfunc (this *Dpu) IsZombie() bool {\n\tfor _, thread := range this.threads {\n\t\tif thread.ThreadState() != logic.ZOMBIE {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn this.logic.IsEmpty() && this.memory_controller.IsEmpty()\n}\n\nfunc (this *Dpu) Cycle() {\n\tthis.dma.Cycle()\n\n\tnum_memory_cycles := int(\n\t\tthis.frequency_ratio*float64(this.cycles) - this.frequency_ratio*float64(this.cycles-1),\n\t)\n\tfor i := 0; i < num_memory_cycles; i++ {\n\t\tthis.memory_controller.Cycle()\n\t}\n\n\tif this.control_interface.Boot() {\n\t\tfor _, thread := range this.threads {\n\t\t\tthread.IncrementIssueCycle()\n\t\t}\n\n\t\tthis.thread_scheduler.Cycle()\n\t\tthis.logic.Cycle()\n\t}\n\n\tthis.cycles++\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/dma_command.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype DmaCommand struct {\n\tmemory_operation MemoryOperation\n\twram_address     *int64\n\tmram_address     *int64\n\tsize             int64\n\n\tbyte_stream *encoding.ByteStream\n\tacks        []bool\n\n\tinstruction *instruction.Instruction\n}\n\nfunc (this *DmaCommand) InitReadFromMram(mram_address int64, size int64) {\n\tthis.memory_operation = READ\n\tthis.wram_address = nil\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = nil\n}\n\nfunc (this *DmaCommand) InitWriteToMram(\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tthis.memory_operation = WRITE\n\tthis.wram_address = nil\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = nil\n}\n\nfunc (this *DmaCommand) InitReadFromMramToWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif instruction_.OpCode() != instruction.LDMA {\n\t\terr := errors.New(\"instruction's op code != LDMA\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = READ\n\n\tthis.wram_address = new(int64)\n\t*this.wram_address = wram_address\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = instruction_\n}\n\nfunc (this *DmaCommand) InitWriteToMramFromWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif instruction_.OpCode() != instruction.SDMA {\n\t\terr := errors.New(\"instruction's op code != SDMA\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = WRITE\n\n\tthis.wram_address = new(int64)\n\t*this.wram_address = wram_address\n\n\tthis.mram_address = new(int64)\n\t*this.mram_address = mram_address\n\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.instruction = instruction_\n}\n\nfunc (this *DmaCommand) Fini() {\n\tif !this.IsReady() {\n\t\terr := errors.New(\"DMA command is not ready\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *DmaCommand) WramAddress() int64 {\n\tif this.wram_address == nil {\n\t\terr := errors.New(\"DMA command does not have a WRAM address\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.wram_address\n}\n\nfunc (this *DmaCommand) MramAddress() int64 {\n\tif this.mram_address == nil {\n\t\terr := errors.New(\"DMA command does not have an MRAM address\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.mram_address\n}\n\nfunc (this *DmaCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *DmaCommand) HasInstruction() bool {\n\treturn this.instruction != nil\n}\n\nfunc (this *DmaCommand) Instruction() *instruction.Instruction {\n\treturn this.instruction\n}\n\nfunc (this *DmaCommand) ByteStream(mram_address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *DmaCommand) SetByteStream(\n\tmram_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *DmaCommand) SetAck(mram_address int64, size int64) {\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(mram_address) + int(i)\n\n\t\tif this.acks[index] {\n\t\t\terr := errors.New(\"ACK is already set\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.acks[index] = true\n\t}\n}\n\nfunc (this *DmaCommand) IsReady() bool {\n\tfor _, ack := range this.acks {\n\t\tif !ack {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *DmaCommand) Index(mram_address int64) int {\n\tif mram_address < this.MramAddress() {\n\t\terr := errors.New(\"MRAM address < DMA command's MRAM address\")\n\t\tpanic(err)\n\t} else if mram_address >= this.MramAddress()+this.Size() {\n\t\terr := errors.New(\"MRAM address >= DMA command's MRAM address + DMA command's size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(mram_address - this.MramAddress())\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/dma_command_q.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n)\n\ntype DmaCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tdma_commands []*DmaCommand\n\tcycles       []int64\n}\n\nfunc (this *DmaCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.dma_commands = make([]*DmaCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *DmaCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"DMA command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *DmaCommandQ) Length() int {\n\treturn len(this.dma_commands)\n}\n\nfunc (this *DmaCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *DmaCommandQ) IsEmpty() bool {\n\treturn len(this.dma_commands) == 0\n}\n\nfunc (this *DmaCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.dma_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Push(dma_command *DmaCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *DmaCommandQ) PushWithTimer(dma_command *DmaCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *DmaCommandQ) CanPop(num_items int) bool {\n\tif len(this.dma_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Pop() *DmaCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"DMA command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tdma_command := this.dma_commands[0]\n\n\tthis.dma_commands = this.dma_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn dma_command\n}\n\nfunc (this *DmaCommandQ) Front(pos int) (*DmaCommand, int64) {\n\treturn this.dma_commands[pos], this.cycles[pos]\n}\n\nfunc (this *DmaCommandQ) Remove(pos int) {\n\tthis.dma_commands = append(this.dma_commands[:pos], this.dma_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *DmaCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/memory_command.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype MemoryOperation int\n\nconst (\n\tACTIVATION MemoryOperation = iota\n\tREAD\n\tWRITE\n\tPRECHARGE\n)\n\ntype MemoryCommand struct {\n\tmemory_operation MemoryOperation\n\taddress          int64\n\tsize             int64\n\tbyte_stream      *encoding.ByteStream\n\tdma_command      *DmaCommand\n}\n\nfunc (this *MemoryCommand) InitActivation(memory_operation MemoryOperation, address int64) {\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = 0\n\tthis.byte_stream = nil\n\tthis.dma_command = nil\n}\n\nfunc (this *MemoryCommand) InitRead(\n\tmemory_operation MemoryOperation,\n\taddress int64,\n\tsize int64,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != READ {\n\t\terr := errors.New(\"DMA operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) InitWrite(\n\tmemory_operation MemoryOperation,\n\taddress int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != WRITE {\n\t\terr := errors.New(\"memory operation != WRITE\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != WRITE {\n\t\terr := errors.New(\"DMA operation != WRITE\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.address = address\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *MemoryCommand) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *MemoryCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *MemoryCommand) ByteStream() *encoding.ByteStream {\n\tif this.byte_stream == nil {\n\t\terr := errors.New(\"byte stream == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.byte_stream\n}\n\nfunc (this *MemoryCommand) SetByteStream(byte_stream *encoding.ByteStream) {\n\tif this.memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *MemoryCommand) DmaCommand() *DmaCommand {\n\tif this.dma_command == nil {\n\t\terr := errors.New(\"DMA command == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.dma_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/memory_command_q.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n)\n\ntype MemoryCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tmemory_commands []*MemoryCommand\n\tcycles          []int64\n}\n\nfunc (this *MemoryCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.memory_commands = make([]*MemoryCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *MemoryCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *MemoryCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *MemoryCommandQ) Length() int {\n\treturn len(this.memory_commands)\n}\n\nfunc (this *MemoryCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *MemoryCommandQ) IsEmpty() bool {\n\treturn len(this.memory_commands) == 0\n}\n\nfunc (this *MemoryCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.memory_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *MemoryCommandQ) PushWithTimer(memory_command *MemoryCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *MemoryCommandQ) CanPop(num_items int) bool {\n\tif len(this.memory_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Pop() *MemoryCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"memory command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tmemory_command := this.memory_commands[0]\n\n\tthis.memory_commands = this.memory_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn memory_command\n}\n\nfunc (this *MemoryCommandQ) Front(pos int) (*MemoryCommand, int64) {\n\treturn this.memory_commands[pos], this.cycles[pos]\n}\n\nfunc (this *MemoryCommandQ) Remove(pos int) {\n\tthis.memory_commands = append(this.memory_commands[:pos], this.memory_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *MemoryCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/memory_controller.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryController struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\twordline_size int64\n\n\tmemory_scheduler *MemoryScheduler\n\trow_buffer       *RowBuffer\n\tmram             *Mram\n\n\tinput_q          *DmaCommandQ\n\twait_q           *DmaCommandQ\n\tmemory_command_q *MemoryCommandQ\n\tready_q          *DmaCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *MemoryController) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.memory_scheduler = new(MemoryScheduler)\n\tthis.memory_scheduler.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.row_buffer = new(RowBuffer)\n\tthis.row_buffer.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.mram = nil\n\n\tthis.input_q = new(DmaCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.wait_q = new(DmaCommandQ)\n\tthis.wait_q.Init(-1, 0)\n\n\tthis.memory_command_q = new(MemoryCommandQ)\n\tthis.memory_command_q.Init(-1, 0)\n\n\tthis.ready_q = new(DmaCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tname := fmt.Sprintf(\"MemoryController[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *MemoryController) Fini() {\n\tthis.memory_scheduler.Fini()\n\tthis.row_buffer.Fini()\n\n\tthis.input_q.Fini()\n\tthis.wait_q.Fini()\n\tthis.memory_command_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryController) ConnectMram(mram *Mram) {\n\tif this.mram != nil {\n\t\terr := errors.New(\"MRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram = mram\n\tthis.row_buffer.ConnectMram(mram)\n}\n\nfunc (this *MemoryController) MemoryScheduler() *MemoryScheduler {\n\treturn this.memory_scheduler\n}\n\nfunc (this *MemoryController) RowBuffer() *RowBuffer {\n\treturn this.row_buffer\n}\n\nfunc (this *MemoryController) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *MemoryController) IsEmpty() bool {\n\treturn this.memory_scheduler.IsEmpty() &&\n\t\tthis.row_buffer.IsEmpty() &&\n\t\tthis.input_q.IsEmpty() &&\n\t\tthis.wait_q.IsEmpty() &&\n\t\tthis.memory_command_q.IsEmpty() &&\n\t\tthis.ready_q.IsEmpty()\n}\n\nfunc (this *MemoryController) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryController) Push(dma_command *DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory controller cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *MemoryController) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryController) Pop() *DmaCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory controller cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryController) Read(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.mram.Read(cur_wordline_address)\n\n\t\tfor i := cur_offset; i < cur_offset+cur_size; i++ {\n\t\t\tbyte_stream.Append(mram_byte_stream.Get(int(i)))\n\t\t}\n\n\t\tcur_address += cur_size\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *MemoryController) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tcur_byte_stream_offset := int64(0)\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.mram.Read(cur_wordline_address)\n\n\t\tfor i := int64(0); i < cur_size; i++ {\n\t\t\tmram_byte_stream.Set(int(i+cur_offset), byte_stream.Get(int(i+cur_byte_stream_offset)))\n\t\t}\n\n\t\tthis.mram.Write(cur_wordline_address, mram_byte_stream.Size(), mram_byte_stream)\n\n\t\tcur_address += cur_size\n\t\tcur_byte_stream_offset += cur_size\n\t}\n}\n\nfunc (this *MemoryController) Flush() {\n\tthis.memory_scheduler.Flush()\n\tthis.row_buffer.Flush()\n}\n\nfunc (this *MemoryController) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceScheduler()\n\tthis.ServiceMemoryCommandQ()\n\tthis.ServiceRowBuffer()\n\tthis.ServiceWaitQ()\n\n\tthis.memory_scheduler.Cycle()\n\tthis.row_buffer.Cycle()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.memory_command_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.stat_factory.Increment(\"memory_cycle\", 1)\n}\n\nfunc (this *MemoryController) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) && this.memory_scheduler.CanPush() {\n\t\tdma_command := this.input_q.Pop()\n\t\tthis.memory_scheduler.Push(dma_command)\n\t\tthis.wait_q.Push(dma_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceScheduler() {\n\tif this.memory_scheduler.CanPop() && this.memory_command_q.CanPush(1) {\n\t\tmemory_command := this.memory_scheduler.Pop()\n\t\tthis.memory_command_q.Push(memory_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceMemoryCommandQ() {\n\tif this.memory_command_q.CanPop(1) && this.row_buffer.CanPush() {\n\t\tmemory_command := this.memory_command_q.Pop()\n\t\tthis.row_buffer.Push(memory_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceRowBuffer() {\n\tif this.row_buffer.CanPop() {\n\t\tmemory_command := this.row_buffer.Pop()\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\treturn\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\treturn\n\t\t} else if memory_operation == READ {\n\t\t\taddress := memory_command.Address()\n\t\t\tsize := memory_command.Size()\n\t\t\tbyte_stream := memory_command.ByteStream()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetByteStream(address, size, byte_stream)\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else if memory_operation == WRITE {\n\t\t\taddress := memory_command.Address()\n\t\t\tsize := memory_command.Size()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceWaitQ() {\n\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\tdma_command, _ := this.wait_q.Front(i)\n\n\t\tif dma_command.IsReady() && this.ready_q.CanPush(1) {\n\t\t\tthis.wait_q.Remove(i)\n\t\t\tthis.ready_q.Push(dma_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *MemoryController) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/memory_scheduler.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryScheduler struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tinput_q        *DmaCommandQ\n\treorder_buffer *MemoryCommandQ\n\tready_q        *MemoryCommandQ\n\n\trow_address            *int64\n\twordline_size          int64\n\tmin_access_granularity int64\n\treorder_window_size    int\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *MemoryScheduler) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.input_q = new(DmaCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.reorder_buffer = new(MemoryCommandQ)\n\tthis.reorder_buffer.Init(-1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.row_address = nil\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\tthis.reorder_window_size = int(command_line_parser.IntParameter(\"reorder_window_size\"))\n\n\tname := fmt.Sprintf(\"MemoryScheduler[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *MemoryScheduler) Fini() {\n\tthis.input_q.Fini()\n\tthis.reorder_buffer.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryScheduler) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *MemoryScheduler) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.reorder_buffer.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *MemoryScheduler) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryScheduler) Push(dma_command *DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory scheduler cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *MemoryScheduler) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryScheduler) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory scheduler cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryScheduler) Flush() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory scheduler cannot be flushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.row_address = nil\n}\n\nfunc (this *MemoryScheduler) Cycle() {\n\tthis.ServiceInputQ()\n\n\tif !this.ReorderFr() {\n\t\tthis.ReorderFcFs()\n\t}\n\n\tthis.input_q.Cycle()\n\tthis.reorder_buffer.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *MemoryScheduler) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tdma_command := this.input_q.Pop()\n\n\t\tthis.PopulateMemoryCommands(dma_command)\n\t}\n}\n\nfunc (this *MemoryScheduler) PopulateMemoryCommands(dma_command *DmaCommand) {\n\tbegin_address := dma_command.MramAddress()\n\tend_address := dma_command.MramAddress() + dma_command.Size()\n\n\tfor address := begin_address; address < end_address; {\n\t\twordline_address := this.WordlineAddress(address)\n\n\t\tsize := this.Min(\n\t\t\tthis.Min(\n\t\t\t\taddress+this.min_access_granularity,\n\t\t\t\twordline_address+this.wordline_size,\n\t\t\t),\n\t\t\tend_address,\n\t\t) - address\n\n\t\tmemory_operation := dma_command.MemoryOperation()\n\t\tmemory_command := new(MemoryCommand)\n\t\tif memory_operation == READ {\n\t\t\tmemory_command.InitRead(READ, address, size, dma_command)\n\t\t} else if memory_operation == WRITE {\n\t\t\tbyte_stream := dma_command.ByteStream(address, size)\n\t\t\tmemory_command.InitWrite(WRITE, address, size, byte_stream, dma_command)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.reorder_buffer.Push(memory_command)\n\n\t\taddress += size\n\t}\n}\n\nfunc (this *MemoryScheduler) ReorderFr() bool {\n\tif this.row_address != nil && this.ready_q.CanPush(1) {\n\t\tfor i := 0; this.reorder_buffer.CanPop(i+1) && i < this.reorder_window_size; i++ {\n\t\t\tmemory_command, _ := this.reorder_buffer.Front(i)\n\n\t\t\tif this.WordlineAddress(memory_command.Address()) == *this.row_address {\n\t\t\t\tif i != 0 {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fr\", 1)\n\t\t\t\t} else {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fcfs\", 1)\n\t\t\t\t}\n\n\t\t\t\tthis.reorder_buffer.Remove(i)\n\t\t\t\tthis.ready_q.Push(memory_command)\n\n\t\t\t\treturn true\n\t\t\t}\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *MemoryScheduler) ReorderFcFs() bool {\n\tif this.reorder_buffer.CanPop(1) && this.row_address != nil && this.ready_q.CanPush(3) {\n\t\tmemory_command := this.reorder_buffer.Pop()\n\t\twordline_address := this.WordlineAddress(memory_command.Address())\n\n\t\tprecharge := new(MemoryCommand)\n\t\tprecharge.InitActivation(PRECHARGE, *this.row_address)\n\n\t\tactivation := new(MemoryCommand)\n\t\tactivation.InitActivation(ACTIVATION, wordline_address)\n\n\t\tthis.ready_q.Push(precharge)\n\t\tthis.ready_q.Push(activation)\n\t\tthis.ready_q.Push(memory_command)\n\n\t\t*this.row_address = wordline_address\n\n\t\treturn true\n\t} else if this.reorder_buffer.CanPop(1) && this.row_address == nil && this.ready_q.CanPush(2) {\n\t\tmemory_command := this.reorder_buffer.Pop()\n\t\twordline_address := this.WordlineAddress(memory_command.Address())\n\n\t\tactivation := new(MemoryCommand)\n\t\tactivation.InitActivation(ACTIVATION, wordline_address)\n\n\t\tthis.ready_q.Push(activation)\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.row_address = new(int64)\n\t\t*this.row_address = wordline_address\n\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *MemoryScheduler) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *MemoryScheduler) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/mram.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Mram struct {\n\taddress int64\n\tsize    int64\n\n\twordline_size int64\n\twordlines     []*Wordline\n}\n\nfunc (this *Mram) Init(command_line_parser *misc.CommandLineParser) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.MramOffset()\n\tthis.size = config_loader.MramSize()\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tif this.wordline_size <= 0 {\n\t\terr := errors.New(\"wordline size <= 0\")\n\t\tpanic(err)\n\t} else if this.address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t} else if this.size%this.wordline_size != 0 {\n\t\terr := errors.New(\"size is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\tthis.wordlines = make([]*Wordline, 0)\n\tnum_wordlines := int(this.size / this.wordline_size)\n\tfor i := 0; i < num_wordlines; i++ {\n\t\twordline := new(Wordline)\n\t\twordline.Init(this.address+int64(i)*this.wordline_size, this.wordline_size)\n\t\tthis.wordlines = append(this.wordlines, wordline)\n\t}\n}\n\nfunc (this *Mram) Fini() {\n\tfor _, wordline := range this.wordlines {\n\t\twordline.Fini()\n\t}\n}\n\nfunc (this *Mram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Mram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Mram) Read(address int64) *encoding.ByteStream {\n\treturn this.wordlines[this.Index(address)].Read()\n}\n\nfunc (this *Mram) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tthis.wordlines[this.Index(address)].Write(byte_stream)\n}\n\nfunc (this *Mram) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < MRAM offset\")\n\t\tpanic(err)\n\t} else if address+this.wordline_size > this.address+this.size {\n\t\terr := errors.New(\"address + wordline size > MRAM offset + MRAM size\")\n\t\tpanic(err)\n\t} else if address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int((address - this.address) / this.wordline_size)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/row_buffer.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype RowBuffer struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tt_ras         int64\n\tt_rcd         int64\n\tt_cl          int64\n\tt_bl          int64\n\tt_rp          int64\n\twordline_size int64\n\n\tmram        *Mram\n\trow_address *int64\n\trow_buffer  *encoding.ByteStream\n\n\tinput_q *MemoryCommandQ\n\tready_q *MemoryCommandQ\n\n\tactivation_q *MemoryCommandQ\n\tio_q         *MemoryCommandQ\n\tbus_q        *MemoryCommandQ\n\tprecharge_q  *MemoryCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *RowBuffer) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.t_ras = command_line_parser.IntParameter(\"t_ras\")\n\tthis.t_rcd = command_line_parser.IntParameter(\"t_rcd\")\n\tthis.t_cl = command_line_parser.IntParameter(\"t_cl\")\n\tthis.t_bl = command_line_parser.IntParameter(\"t_bl\")\n\tthis.t_rp = command_line_parser.IntParameter(\"t_rp\")\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.mram = nil\n\tthis.row_address = nil\n\tthis.row_buffer = nil\n\n\tthis.input_q = new(MemoryCommandQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.activation_q = new(MemoryCommandQ)\n\tthis.activation_q.Init(1, this.t_ras)\n\n\tthis.io_q = new(MemoryCommandQ)\n\tthis.io_q.Init(1, this.t_cl)\n\n\tthis.bus_q = new(MemoryCommandQ)\n\tthis.bus_q.Init(1, this.t_bl)\n\n\tthis.precharge_q = new(MemoryCommandQ)\n\tthis.precharge_q.Init(1, this.t_rp)\n\n\tname := fmt.Sprintf(\"RowBuffer[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *RowBuffer) Fini() {\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n\tthis.activation_q.Fini()\n\tthis.io_q.Fini()\n\tthis.bus_q.Fini()\n\tthis.precharge_q.Fini()\n}\n\nfunc (this *RowBuffer) ConnectMram(mram *Mram) {\n\tif this.mram != nil {\n\t\terr := errors.New(\"MRAM is already connected\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram = mram\n}\n\nfunc (this *RowBuffer) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *RowBuffer) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.ready_q.IsEmpty() && this.activation_q.IsEmpty() &&\n\t\tthis.io_q.IsEmpty() &&\n\t\tthis.bus_q.IsEmpty() &&\n\t\tthis.precharge_q.IsEmpty()\n}\n\nfunc (this *RowBuffer) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *RowBuffer) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"row buffer cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(memory_command)\n}\n\nfunc (this *RowBuffer) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *RowBuffer) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"row buffer cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *RowBuffer) Flush() {\n\tif this.row_address != nil {\n\t\tthis.WriteToMram()\n\n\t\tthis.row_address = nil\n\t\tthis.row_buffer = nil\n\t}\n}\n\nfunc (this *RowBuffer) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceActivationQ()\n\tthis.ServiceIoQ()\n\tthis.ServiceBusQ()\n\tthis.ServicePrechargeQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.activation_q.Cycle()\n\tthis.io_q.Cycle()\n\tthis.bus_q.Cycle()\n\tthis.precharge_q.Cycle()\n}\n\nfunc (this *RowBuffer) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tmemory_command, _ := this.input_q.Front(0)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\tif this.activation_q.IsEmpty() && this.row_address == nil {\n\t\t\t\tthis.activation_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == READ {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == WRITE {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\tif this.activation_q.IsEmpty() && this.io_q.IsEmpty() && this.bus_q.IsEmpty() && this.precharge_q.IsEmpty() {\n\t\t\t\tthis.precharge_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServiceActivationQ() {\n\tif !this.activation_q.IsEmpty() {\n\t\tmemory_command, cycle := this.activation_q.Front(0)\n\n\t\tif cycle == this.t_ras-this.t_rcd {\n\t\t\tif this.row_address != nil {\n\t\t\t\terr := errors.New(\"row buffer is not precharged\")\n\t\t\t\tpanic(err)\n\t\t\t} else if memory_command.Address()%this.wordline_size != 0 {\n\t\t\t\terr := errors.New(\"memory command is not aligned with wordline size\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.row_address = new(int64)\n\t\t\t*this.row_address = memory_command.Address()\n\n\t\t\tthis.row_buffer = this.ReadFromMram()\n\t\t}\n\t}\n\n\tif this.activation_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.activation_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_activations\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceIoQ() {\n\tif this.io_q.CanPop(1) && this.bus_q.CanPush(1) {\n\t\tmemory_command := this.io_q.Pop()\n\t\tthis.bus_q.Push(memory_command)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceBusQ() {\n\tif this.bus_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.bus_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == READ {\n\t\t\tbyte_stream := this.ReadFromRowBuffer(memory_command.Address(), memory_command.Size())\n\t\t\tmemory_command.SetByteStream(byte_stream)\n\n\t\t\tthis.stat_factory.Increment(\"num_reads\", 1)\n\t\t\tthis.stat_factory.Increment(\"read_bytes\", memory_command.Size())\n\t\t} else if memory_operation == WRITE {\n\t\t\tthis.WriteToRowBuffer(memory_command.Address(), memory_command.Size(), memory_command.ByteStream())\n\n\t\t\tthis.stat_factory.Increment(\"num_writes\", 1)\n\t\t\tthis.stat_factory.Increment(\"write_bytes\", memory_command.Size())\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServicePrechargeQ() {\n\tif this.precharge_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.precharge_q.Pop()\n\n\t\taddress := memory_command.Address()\n\t\tif address%this.wordline_size != 0 {\n\t\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\t\tpanic(err)\n\t\t} else if address != *this.row_address {\n\t\t\terr := errors.New(\"address != row address\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.WriteToMram()\n\t\tthis.row_address = nil\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_precharges\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ReadFromMram() *encoding.ByteStream {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\treturn this.mram.Read(*this.row_address)\n}\n\nfunc (this *RowBuffer) ReadFromRowBuffer(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.row_buffer.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *RowBuffer) WriteToMram() {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\tthis.mram.Write(*this.row_address, this.row_buffer.Size(), this.row_buffer)\n}\n\nfunc (this *RowBuffer) WriteToRowBuffer(\n\taddress int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.row_buffer.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *RowBuffer) Index(address int64) int {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if address < *this.row_address {\n\t\terr := errors.New(\"address < row address\")\n\t\tpanic(err)\n\t} else if address >= *this.row_address+this.wordline_size {\n\t\terr := errors.New(\"address >= row address + wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - *this.row_address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/dram/wordline.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Wordline struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Wordline) Init(address int64, size int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_size := int64(config_loader.MramDataWidth() / 8)\n\n\tif address < 0 {\n\t\terr := errors.New(\"address < 0\")\n\t\tpanic(err)\n\t} else if size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t} else if size%mram_data_size != 0 {\n\t\terr := errors.New(\"size is not aligned with MRAM data size\")\n\t\tpanic(err)\n\t}\n\n\tthis.address = address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Wordline) Fini() {\n}\n\nfunc (this *Wordline) Read() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < this.byte_stream.Size(); i++ {\n\t\tbyte_stream.Append(this.byte_stream.Get(int(i)))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Wordline) Write(byte_stream *encoding.ByteStream) {\n\tif this.size != byte_stream.Size() {\n\t\terr := errors.New(\"wordline's size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/alu.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Alu struct {\n}\n\nfunc (this *Alu) Init() {\n}\n\nfunc (this *Alu) Fini() {\n}\n\nfunc (this *Alu) AtomicAddressHash(operand1 int64, operand2 int64) int64 {\n\tif operand1+operand2 >= 256 {\n\t\terr := errors.New(\"operand1 + operand2 >= 256\")\n\t\tpanic(err)\n\t}\n\n\tresult, _, _ := this.Add(operand1, operand2)\n\treturn result\n}\n\nfunc (this *Alu) Add(operand1 int64, operand2 int64) (int64, bool, bool) {\n\treturn this.Addc(operand1, operand2, false)\n}\n\nfunc (this *Alu) Addc(operand1 int64, operand2 int64, carry_flag bool) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tif carry_flag {\n\t\tresult = word1.Value(abi.UNSIGNED) + word2.Value(abi.UNSIGNED) + 1\n\t} else {\n\t\tresult = word1.Value(abi.UNSIGNED) + word2.Value(abi.UNSIGNED)\n\t}\n\n\tmax_unsigned_value := this.Pow2(mram_data_width) - 1\n\n\tvar carry bool\n\tif result > max_unsigned_value {\n\t\tresult %= this.Pow2(mram_data_width)\n\t\tcarry = true\n\t} else {\n\t\tcarry = false\n\t}\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result_word.Value(abi.SIGNED), carry, overflow\n}\n\nfunc (this *Alu) Sub(operand1 int64, operand2 int64) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tvar carry bool\n\tif word1.Value(abi.UNSIGNED) >= word2.Value(abi.UNSIGNED) {\n\t\tresult = word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED)\n\t\tcarry = false\n\t} else {\n\t\tresult = this.Pow2(mram_data_width) + word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED)\n\t\tcarry = true\n\t}\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result, carry, overflow\n}\n\nfunc (this *Alu) Subc(operand1 int64, operand2 int64, carry_flag bool) (int64, bool, bool) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tvar result int64\n\tvar carry bool\n\tif carry_flag {\n\t\tif word1.Value(abi.UNSIGNED)+1 >= word2.Value(abi.UNSIGNED) {\n\t\t\tresult = word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED) - 1\n\t\t\tcarry = false\n\t\t} else {\n\t\t\tresult = this.Pow2(mram_data_width) + word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED) - 1\n\t\t\tcarry = true\n\t\t}\n\t} else {\n\t\tif word1.Value(abi.UNSIGNED) >= word2.Value(abi.UNSIGNED) {\n\t\t\tresult = word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED)\n\t\t\tcarry = false\n\t\t} else {\n\t\t\tresult = this.Pow2(mram_data_width) + word1.Value(abi.UNSIGNED) - word2.Value(abi.UNSIGNED)\n\t\t\tcarry = true\n\t\t}\n\t}\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tresult_word.SetValue(result)\n\n\tvar overflow bool\n\tif word1.SignBit() && !word2.SignBit() && result_word.SignBit() {\n\t\toverflow = true\n\t} else if !word1.SignBit() && word2.SignBit() && !result_word.SignBit() {\n\t\toverflow = true\n\t} else {\n\t\toverflow = false\n\t}\n\n\treturn result, carry, overflow\n}\n\nfunc (this *Alu) And(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Nand(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Andn(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Or(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Nor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Orn(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) || word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Xor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else if word1.Bit(i) && !word2.Bit(i) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tresult_word.ClearBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Nxor(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else if word1.Bit(i) && word2.Bit(i) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tresult_word.SetBit(i)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Asr(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\tmsb := word_.SignBit()\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tif msb {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Lsl(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) LslAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Lsl(operand2, shift))\n}\n\nfunc (this *Alu) LslSub(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Sub(operand1, this.Lsl(operand2, shift))\n}\n\nfunc (this *Alu) Lsl1(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Lsl1x(operand int64, shift int64) int64 {\n\terr := errors.New(\"lsl1x is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Lslx(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tif shift_value == 0 {\n\t\treturn 0\n\t} else {\n\t\treturn this.Lsr(operand, int64(mram_data_width)-shift_value)\n\t}\n}\n\nfunc (this *Alu) Lsr(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tresult_word.ClearBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) LsrAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Lsr(operand2, shift))\n}\n\nfunc (this *Alu) Lsr1(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Lsr1x(operand int64, shift int64) int64 {\n\terr := errors.New(\"lsr1x is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Lsrx(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tif shift_value == 0 {\n\t\treturn 0\n\t} else {\n\t\treturn this.Lsl(operand, int64(mram_data_width)-shift_value)\n\t}\n}\n\nfunc (this *Alu) Rol(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i < int(shift_value) {\n\t\t\tif word_.Bit(i + mram_data_width - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i - int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) RolAdd(operand1 int64, operand2 int64, shift int64) (int64, bool, bool) {\n\treturn this.Add(operand1, this.Rol(operand2, shift))\n}\n\nfunc (this *Alu) Ror(operand int64, shift int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tshift_word := new(abi.Word)\n\tshift_word.Init(mram_data_width)\n\tshift_word.SetValue(shift)\n\tshift_value := shift_word.BitSlice(abi.UNSIGNED, 0, 5)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif i+int(shift_value) >= mram_data_width {\n\t\t\tif word_.Bit((i + int(shift_value)) % mram_data_width) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t\tresult_word.SetBit(i)\n\t\t} else {\n\t\t\tif word_.Bit(i + int(shift_value)) {\n\t\t\t\tresult_word.SetBit(i)\n\t\t\t} else {\n\t\t\t\tresult_word.ClearBit(i)\n\t\t\t}\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Cao(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tones := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(i) {\n\t\t\tones++\n\t\t}\n\t}\n\treturn ones\n}\n\nfunc (this *Alu) Clo(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tleading_ones := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(mram_data_width - 1 - i) {\n\t\t\tleading_ones++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_ones\n}\n\nfunc (this *Alu) Cls(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\tmsb := word_.SignBit()\n\n\tleading_sign_bits := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif word_.Bit(mram_data_width-1-i) == msb {\n\t\t\tleading_sign_bits++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_sign_bits\n}\n\nfunc (this *Alu) Clz(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\tleading_zeros := int64(0)\n\tfor i := 0; i < mram_data_width; i++ {\n\t\tif !word_.Bit(mram_data_width - 1 - i) {\n\t\t\tleading_zeros++\n\t\t} else {\n\t\t\tbreak\n\t\t}\n\t}\n\treturn leading_zeros\n}\n\nfunc (this *Alu) Cmpb4(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\tfor i := 0; i < 4; i++ {\n\t\tbegin := 8 * i\n\t\tend := 8 * (i + 1)\n\n\t\tbyte1 := word1.BitSlice(abi.UNSIGNED, begin, end)\n\t\tbyte2 := word2.BitSlice(abi.UNSIGNED, begin, end)\n\n\t\tif byte1 == byte2 {\n\t\t\tresult_word.SetBitSlice(begin, end, 1)\n\t\t} else {\n\t\t\tresult_word.SetBitSlice(begin, end, 0)\n\t\t}\n\t}\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Extsb(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(abi.SIGNED, 0, 8)\n}\n\nfunc (this *Alu) Extsh(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(abi.SIGNED, 0, 16)\n}\n\nfunc (this *Alu) Extub(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(abi.UNSIGNED, 0, 8)\n}\n\nfunc (this *Alu) Extuh(operand int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\treturn word_.BitSlice(abi.UNSIGNED, 0, 16)\n}\n\nfunc (this *Alu) MulShSh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 8, 16) * word2.BitSlice(abi.SIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulShSl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 8, 16) * word2.BitSlice(abi.SIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulShUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 8, 16) * word2.BitSlice(abi.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulShUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 8, 16) * word2.BitSlice(abi.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulSlSh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 0, 8) * word2.BitSlice(abi.SIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulSlSl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 0, 8) * word2.BitSlice(abi.SIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulSlUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 0, 8) * word2.BitSlice(abi.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulSlUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.SIGNED, 0, 8) * word2.BitSlice(abi.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.SIGNED)\n}\n\nfunc (this *Alu) MulUhUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.UNSIGNED, 8, 16) * word2.BitSlice(abi.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) MulUhUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.UNSIGNED, 8, 16) * word2.BitSlice(abi.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) MulUlUh(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.UNSIGNED, 0, 8) * word2.BitSlice(abi.UNSIGNED, 8, 16)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) MulUlUl(operand1 int64, operand2 int64) int64 {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tif mram_data_width != 4*8 {\n\t\terr := errors.New(\"MRAM data width != 4 * 8\")\n\t\tpanic(err)\n\t}\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(mram_data_width)\n\n\tresult := word1.BitSlice(abi.UNSIGNED, 0, 8) * word2.BitSlice(abi.UNSIGNED, 0, 8)\n\tresult_word.SetValue(result)\n\n\treturn result_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Sats(operand int64) int64 {\n\terr := errors.New(\"sats is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) Hash(operand1 int64, operand2 int64) int64 {\n\terr := errors.New(\"hash is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Alu) SignedExtension(operand int64) (int64, int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\teven_word := new(abi.Word)\n\teven_word.Init(mram_data_width)\n\tif word_.SignBit() {\n\t\teven_word.SetValue(-1)\n\t}\n\n\todd_word := new(abi.Word)\n\todd_word.Init(mram_data_width)\n\todd_word.SetValue(word_.Value(abi.UNSIGNED))\n\n\treturn even_word.Value(abi.UNSIGNED), odd_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) UnsignedExtension(operand int64) (int64, int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword_ := new(abi.Word)\n\tword_.Init(mram_data_width)\n\tword_.SetValue(operand)\n\n\teven_word := new(abi.Word)\n\teven_word.Init(mram_data_width)\n\teven_word.SetValue(0)\n\n\todd_word := new(abi.Word)\n\todd_word.Init(mram_data_width)\n\todd_word.SetValue(word_.Value(abi.UNSIGNED))\n\n\treturn even_word.Value(abi.UNSIGNED), odd_word.Value(abi.UNSIGNED)\n}\n\nfunc (this *Alu) Pow2(exponent int) int64 {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/cycle_rule.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype CycleRule struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tinput_q *InstructionQ\n\twait_q  *InstructionQ\n\tready_q *InstructionQ\n\n\tscoreboard map[*instruction.Instruction]*Thread\n\treg_sets   []*RegSet\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *CycleRule) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tnum_tasklets := int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.input_q = new(InstructionQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(1, 0)\n\n\tthis.ready_q = new(InstructionQ)\n\tthis.ready_q.Init(1, 0)\n\n\tthis.scoreboard = make(map[*instruction.Instruction]*Thread)\n\n\tfor i := 0; i < num_tasklets; i++ {\n\t\treg_set := new(RegSet)\n\t\treg_set.Init(i)\n\n\t\tthis.reg_sets = append(this.reg_sets, reg_set)\n\t}\n\n\tname := fmt.Sprintf(\"CycleRule[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *CycleRule) Fini() {\n\tthis.input_q.Fini()\n\tthis.wait_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *CycleRule) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *CycleRule) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.wait_q.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *CycleRule) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *CycleRule) Push(instruction_ *instruction.Instruction, thread *Thread) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"cycle rule cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(instruction_)\n\tthis.scoreboard[instruction_] = thread\n}\n\nfunc (this *CycleRule) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *CycleRule) Pop() *instruction.Instruction {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"cycle rule cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tinstruction_ := this.ready_q.Pop()\n\n\tdelete(this.scoreboard, instruction_)\n\treturn instruction_\n}\n\nfunc (this *CycleRule) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceWaitQ()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *CycleRule) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) {\n\t\tinstruction_ := this.input_q.Pop()\n\n\t\tthread_id := this.scoreboard[instruction_].ThreadId()\n\t\tthis.reg_sets[thread_id].CollectReadGpRegs(instruction_)\n\n\t\textra_cycles := this.CalculateExtraCycles(instruction_)\n\n\t\tthis.wait_q.PushWithTimer(instruction_, extra_cycles)\n\n\t\tthis.stat_factory.Increment(\"cycle_rule\", extra_cycles)\n\t}\n}\n\nfunc (this *CycleRule) ServiceWaitQ() {\n\tif this.wait_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tinstruction_ := this.wait_q.Pop()\n\t\tthis.ready_q.Push(instruction_)\n\n\t\tthread_id := this.scoreboard[instruction_].ThreadId()\n\t\tthis.reg_sets[thread_id].Clear()\n\t\tthis.reg_sets[thread_id].CollectWriteGpRegs(instruction_)\n\t}\n}\n\nfunc (this *CycleRule) CalculateExtraCycles(instruction_ *instruction.Instruction) int64 {\n\tthread_id := this.scoreboard[instruction_].ThreadId()\n\n\treg_set := this.reg_sets[thread_id]\n\n\tif reg_set.ThreadId() != thread_id {\n\t\terr := errors.New(\"reg set's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\treg_indicies := reg_set.RegIndices()\n\n\teven_counter := 0\n\todd_counter := 0\n\tfor reg_index, _ := range reg_indicies {\n\t\tif reg_index%2 == 0 {\n\t\t\teven_counter++\n\t\t} else {\n\t\t\todd_counter++\n\t\t}\n\t}\n\n\treturn int64(even_counter/2 + odd_counter/2)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/dma.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/device/simulator/dpu/sram\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Dma struct {\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\toperand_collector *OperandCollector\n\tmemory_controller *dram.MemoryController\n\n\tinput_q *dram.DmaCommandQ\n\tready_q *dram.DmaCommandQ\n}\n\nfunc (this *Dma) Init() {\n\tthis.atomic = nil\n\tthis.iram = nil\n\tthis.operand_collector = nil\n\tthis.memory_controller = nil\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmax_num_tasklets := config_loader.MaxNumTasklets()\n\n\tthis.input_q = new(dram.DmaCommandQ)\n\tthis.input_q.Init(max_num_tasklets, 0)\n\n\tthis.ready_q = new(dram.DmaCommandQ)\n\tthis.ready_q.Init(max_num_tasklets, 0)\n}\n\nfunc (this *Dma) Fini() {\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Dma) ConnectAtomic(atomic *sram.Atomic) {\n\tif this.atomic != nil {\n\t\terr := errors.New(\"atomic is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.atomic = atomic\n}\n\nfunc (this *Dma) ConnectIram(iram *sram.Iram) {\n\tif this.iram != nil {\n\t\terr := errors.New(\"IRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram = iram\n}\n\nfunc (this *Dma) ConnectOperandCollector(operand_collector *OperandCollector) {\n\tif this.operand_collector != nil {\n\t\terr := errors.New(\"operand collector is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand_collector = operand_collector\n}\n\nfunc (this *Dma) ConnectMemoryController(memory_controller *dram.MemoryController) {\n\tif this.memory_controller != nil {\n\t\terr := errors.New(\"memory controller is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_controller = memory_controller\n}\n\nfunc (this *Dma) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *Dma) TransferToAtomic(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tif byte_stream.Get(int(i)) != 0 {\n\t\t\terr := errors.New(\"atomic byte is not set to 0\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Dma) TransferToIram(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_offset := config_loader.IramOffset()\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif address != this.iram.Address() {\n\t\terr := errors.New(\"address != IRAM's address\")\n\t\tpanic(err)\n\t} else if byte_stream.Size()%iram_data_size != 0 {\n\t\terr := errors.New(\"byte stream's size is not aligned with IRAM data size\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram.Write(iram_offset, size, byte_stream)\n}\n\nfunc (this *Dma) TransferFromWram(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tvalue := this.operand_collector.Lbu(address + i)\n\t\tbyte_stream.Append(uint8(value))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Dma) TransferToWram(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tthis.operand_collector.Sb(address+i, int64(value))\n\t}\n}\n\nfunc (this *Dma) TransferFromMram(address int64, size int64) *encoding.ByteStream {\n\tthis.memory_controller.Flush()\n\treturn this.memory_controller.Read(address, size)\n}\n\nfunc (this *Dma) TransferToMram(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_controller.Write(address, size, byte_stream)\n}\n\nfunc (this *Dma) TransferFromWramToMram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tbyte_stream := this.TransferFromWram(wram_address, size)\n\n\tdma_command := new(dram.DmaCommand)\n\tdma_command.InitWriteToMramFromWram(wram_address, mram_address, size, byte_stream, instruction_)\n\n\tthis.Push(dma_command)\n}\n\nfunc (this *Dma) TransferFromMramToWram(\n\twram_address int64,\n\tmram_address int64,\n\tsize int64,\n\tinstruction_ *instruction.Instruction,\n) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tdma_command := new(dram.DmaCommand)\n\tdma_command.InitReadFromMramToWram(wram_address, mram_address, size, instruction_)\n\n\tthis.Push(dma_command)\n}\n\nfunc (this *Dma) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Dma) Push(dma_command *dram.DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"DMA cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *Dma) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Dma) Pop() *dram.DmaCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"DMA cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Dma) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Dma) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.memory_controller.CanPush() {\n\t\tdma_command := this.input_q.Pop()\n\t\tthis.memory_controller.Push(dma_command)\n\t}\n}\n\nfunc (this *Dma) ServiceReadyQ() {\n\tif this.memory_controller.CanPop() && this.ready_q.CanPush(1) {\n\t\tdma_command := this.memory_controller.Pop()\n\t\tthis.ready_q.Push(dma_command)\n\n\t\tif dma_command.HasInstruction() && dma_command.MemoryOperation() == dram.READ {\n\t\t\twram_address := dma_command.WramAddress()\n\t\t\tmram_address := dma_command.MramAddress()\n\t\t\tsize := dma_command.Size()\n\t\t\tbyte_stream := dma_command.ByteStream(mram_address, size)\n\n\t\t\tthis.TransferToWram(wram_address, byte_stream.Size(), byte_stream)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/instruction_q.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n)\n\ntype InstructionQ struct {\n\tsize  int\n\ttimer int64\n\n\tinstructions []*instruction.Instruction\n\tcycles       []int64\n}\n\nfunc (this *InstructionQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.instructions = make([]*instruction.Instruction, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *InstructionQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"instruction queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *InstructionQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *InstructionQ) Length() int {\n\treturn len(this.instructions)\n}\n\nfunc (this *InstructionQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *InstructionQ) IsEmpty() bool {\n\treturn len(this.instructions) == 0\n}\n\nfunc (this *InstructionQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.instructions) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *InstructionQ) Push(instruction_ *instruction.Instruction) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"instruction queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.instructions = append(this.instructions, instruction_)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *InstructionQ) PushWithTimer(instruction_ *instruction.Instruction, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"instruction queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.instructions = append(this.instructions, instruction_)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *InstructionQ) CanPop(num_items int) bool {\n\tif len(this.instructions) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *InstructionQ) Pop() *instruction.Instruction {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"instruction queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tinstruction_ := this.instructions[0]\n\n\tthis.instructions = this.instructions[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn instruction_\n}\n\nfunc (this *InstructionQ) Front(pos int) (*instruction.Instruction, int64) {\n\treturn this.instructions[pos], this.cycles[pos]\n}\n\nfunc (this *InstructionQ) Remove(pos int) {\n\tthis.instructions = append(this.instructions[:pos], this.instructions[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *InstructionQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/logic.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"math\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/device/simulator/dpu/sram\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Logic struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tnum_channels          int\n\tnum_ranks_per_channel int\n\tnum_dpus_per_rank     int\n\n\tverbose int\n\n\tmin_access_granularity int64\n\n\tthread_scheduler  *ThreadScheduler\n\tatomic            *sram.Atomic\n\tiram              *sram.Iram\n\toperand_collector *OperandCollector\n\tdma               *Dma\n\n\tscoreboard map[*instruction.Instruction]*Thread\n\n\tpipeline   *Pipeline\n\tcycle_rule *CycleRule\n\n\talu    *Alu\n\twait_q *InstructionQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *Logic) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.num_channels = int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.num_ranks_per_channel = int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tthis.num_dpus_per_rank = int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\n\tthis.verbose = int(command_line_parser.IntParameter(\"verbose\"))\n\n\tthis.thread_scheduler = nil\n\tthis.atomic = nil\n\tthis.iram = nil\n\tthis.operand_collector = nil\n\tthis.dma = nil\n\n\tthis.scoreboard = make(map[*instruction.Instruction]*Thread)\n\n\tthis.pipeline = new(Pipeline)\n\tthis.pipeline.Init(command_line_parser)\n\n\tthis.cycle_rule = new(CycleRule)\n\tthis.cycle_rule.Init(channel_id, rank_id, dpu_id, command_line_parser)\n\n\tthis.alu = new(Alu)\n\tthis.alu.Init()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(config_loader.MaxNumTasklets(), 0)\n\n\tname := fmt.Sprintf(\"Logic[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *Logic) Fini() {\n\tthis.pipeline.Fini()\n\tthis.cycle_rule.Fini()\n\n\tthis.alu.Fini()\n\tthis.wait_q.Fini()\n}\n\nfunc (this *Logic) ConnectThreadScheduler(thread_scheduler *ThreadScheduler) {\n\tif this.thread_scheduler != nil {\n\t\terr := errors.New(\"thread scheduler is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_scheduler = thread_scheduler\n}\n\nfunc (this *Logic) ConnectAtomic(atomic *sram.Atomic) {\n\tif this.atomic != nil {\n\t\terr := errors.New(\"atomic is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.atomic = atomic\n}\n\nfunc (this *Logic) ConnectIram(iram *sram.Iram) {\n\tif this.iram != nil {\n\t\terr := errors.New(\"IRAM is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.iram = iram\n}\n\nfunc (this *Logic) ConnectOperandCollector(operand_collector *OperandCollector) {\n\tif this.operand_collector != nil {\n\t\terr := errors.New(\"operand collector is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.operand_collector = operand_collector\n}\n\nfunc (this *Logic) ConnectDma(dma *Dma) {\n\tif this.dma != nil {\n\t\terr := errors.New(\"DMA is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma = dma\n}\n\nfunc (this *Logic) CycleRule() *CycleRule {\n\treturn this.cycle_rule\n}\n\nfunc (this *Logic) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *Logic) IsEmpty() bool {\n\treturn this.pipeline.IsEmpty() && this.cycle_rule.IsEmpty() && this.wait_q.IsEmpty()\n}\n\nfunc (this *Logic) Cycle() {\n\tthis.ServiceThreadScheduler()\n\tthis.ServicePipeline()\n\tthis.ServiceCycleRule()\n\tthis.ServiceLogic()\n\tthis.ServiceDma()\n\n\tthis.pipeline.Cycle()\n\tthis.cycle_rule.Cycle()\n\n\tthis.stat_factory.Increment(\"logic_cycle\", 1)\n}\n\nfunc (this *Logic) ServiceThreadScheduler() {\n\tif this.pipeline.CanPush() && this.cycle_rule.CanPush() && this.wait_q.CanPush(1) {\n\t\tthread := this.thread_scheduler.Schedule()\n\n\t\tif thread != nil {\n\t\t\tpc := thread.RegFile().ReadPcReg()\n\t\t\tinstruction_ := this.iram.Read(pc)\n\n\t\t\tthis.scoreboard[instruction_] = thread\n\n\t\t\tthis.pipeline.Push(instruction_)\n\n\t\t\tif instruction_.Suffix() != instruction.DMA_RRI {\n\t\t\t\tthis.ExecuteInstruction(instruction_)\n\t\t\t} else {\n\t\t\t\tthis.thread_scheduler.Block(thread.ThreadId())\n\t\t\t\tthread.RegFile().IncrementPcReg()\n\t\t\t\tthis.wait_q.Push(instruction_)\n\t\t\t}\n\n\t\t\tthis.stat_factory.Increment(\"num_instructions\", 1)\n\t\t}\n\n\t\tactive_tasklets := fmt.Sprintf(\n\t\t\t\"active_tasklets_%d\",\n\t\t\tthis.thread_scheduler.NumIssuableThreads(),\n\t\t)\n\t\tthis.stat_factory.Increment(active_tasklets, 1)\n\t} else {\n\t\tthis.stat_factory.Increment(\"backpressure\", 1)\n\t\tthis.stat_factory.Increment(\"active_tasklets_0\", 1)\n\t}\n}\n\nfunc (this *Logic) ServicePipeline() {\n\tif this.pipeline.CanPop() && this.cycle_rule.CanPush() {\n\t\tinstruction_ := this.pipeline.Pop()\n\t\tthread := this.scoreboard[instruction_]\n\n\t\tif instruction_ != nil {\n\t\t\tthis.cycle_rule.Push(instruction_, thread)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ServiceCycleRule() {\n\tif this.cycle_rule.CanPop() {\n\t\tinstruction_ := this.cycle_rule.Pop()\n\n\t\tif instruction_.Suffix() != instruction.DMA_RRI {\n\t\t\tdelete(this.scoreboard, instruction_)\n\t\t} else {\n\t\t\tthis.ExecuteInstruction(instruction_)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ServiceLogic() {\n}\n\nfunc (this *Logic) ServiceDma() {\n\tif this.dma.CanPop() {\n\t\tdma_command := this.dma.Pop()\n\n\t\thas_waked_up := false\n\t\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.wait_q.Front(i)\n\n\t\t\tif dma_command.Instruction() == instruction_ {\n\t\t\t\tthread := this.scoreboard[instruction_]\n\n\t\t\t\tthis.thread_scheduler.Awake(thread.ThreadId())\n\n\t\t\t\tthis.wait_q.Remove(i)\n\t\t\t\tdelete(this.scoreboard, instruction_)\n\n\t\t\t\thas_waked_up = true\n\t\t\t\tbreak\n\t\t\t}\n\t\t}\n\n\t\tif !has_waked_up {\n\t\t\terr := errors.New(\"DMA command has not waked up an instruction\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *Logic) ExecuteInstruction(instruction_ *instruction.Instruction) {\n\tthread := this.scoreboard[instruction_]\n\n\tunique_dpu_id := this.channel_id*this.num_ranks_per_channel*this.num_dpus_per_rank + this.rank_id*this.num_dpus_per_rank + this.dpu_id\n\n\tif this.verbose >= 1 {\n\t\tfmt.Printf(\n\t\t\t\"{%d}[%d] %s\\n\",\n\t\t\tunique_dpu_id,\n\t\t\tthread.ThreadId(),\n\t\t\tinstruction_.Stringify(),\n\t\t)\n\t}\n\n\tsuffix := instruction_.Suffix()\n\n\tif suffix == instruction.RICI {\n\t\tthis.ExecuteRici(instruction_)\n\t} else if suffix == instruction.RRI {\n\t\tthis.ExecuteRri(instruction_)\n\t} else if suffix == instruction.RRIC {\n\t\tthis.ExecuteRric(instruction_)\n\t} else if suffix == instruction.RRICI {\n\t\tthis.ExecuteRrici(instruction_)\n\t} else if suffix == instruction.RRIF {\n\t\tthis.ExecuteRrif(instruction_)\n\t} else if suffix == instruction.RRR {\n\t\tthis.ExecuteRrr(instruction_)\n\t} else if suffix == instruction.RRRC {\n\t\tthis.ExecuteRrrc(instruction_)\n\t} else if suffix == instruction.RRRCI {\n\t\tthis.ExecuteRrrci(instruction_)\n\t} else if suffix == instruction.ZRI {\n\t\tthis.ExecuteZri(instruction_)\n\t} else if suffix == instruction.ZRIC {\n\t\tthis.ExecuteZric(instruction_)\n\t} else if suffix == instruction.ZRICI {\n\t\tthis.ExecuteZrici(instruction_)\n\t} else if suffix == instruction.ZRIF {\n\t\tthis.ExecuteZrif(instruction_)\n\t} else if suffix == instruction.ZRR {\n\t\tthis.ExecuteZrr(instruction_)\n\t} else if suffix == instruction.ZRRC {\n\t\tthis.ExecuteZrrc(instruction_)\n\t} else if suffix == instruction.ZRRCI {\n\t\tthis.ExecuteZrrci(instruction_)\n\t} else if suffix == instruction.S_RRI || suffix == instruction.U_RRI {\n\t\tthis.ExecuteSRri(instruction_)\n\t} else if suffix == instruction.S_RRIC || suffix == instruction.U_RRIC {\n\t\tthis.ExecuteSRric(instruction_)\n\t} else if suffix == instruction.S_RRICI || suffix == instruction.U_RRICI {\n\t\tthis.ExecuteSRrici(instruction_)\n\t} else if suffix == instruction.S_RRIF || suffix == instruction.U_RRIF {\n\t\tthis.ExecuteSRrif(instruction_)\n\t} else if suffix == instruction.S_RRR || suffix == instruction.U_RRR {\n\t\tthis.ExecuteSRrr(instruction_)\n\t} else if suffix == instruction.S_RRRC || suffix == instruction.U_RRRC {\n\t\tthis.ExecuteSRrrc(instruction_)\n\t} else if suffix == instruction.S_RRRCI || suffix == instruction.U_RRRCI {\n\t\tthis.ExecuteSRrrci(instruction_)\n\t} else if suffix == instruction.RR {\n\t\tthis.ExecuteRr(instruction_)\n\t} else if suffix == instruction.RRC {\n\t\tthis.ExecuteRrc(instruction_)\n\t} else if suffix == instruction.RRCI {\n\t\tthis.ExecuteRrci(instruction_)\n\t} else if suffix == instruction.ZR {\n\t\tthis.ExecuteZr(instruction_)\n\t} else if suffix == instruction.ZRC {\n\t\tthis.ExecuteZrc(instruction_)\n\t} else if suffix == instruction.ZRCI {\n\t\tthis.ExecuteZrci(instruction_)\n\t} else if suffix == instruction.S_RR || suffix == instruction.U_RR {\n\t\tthis.ExecuteSRr(instruction_)\n\t} else if suffix == instruction.S_RRC || suffix == instruction.U_RRC {\n\t\tthis.ExecuteSRrc(instruction_)\n\t} else if suffix == instruction.S_RRCI || suffix == instruction.U_RRCI {\n\t\tthis.ExecuteSRrci(instruction_)\n\t} else if suffix == instruction.DRDICI {\n\t\tthis.ExecuteDrdici(instruction_)\n\t} else if suffix == instruction.RRRI {\n\t\tthis.ExecuteRrri(instruction_)\n\t} else if suffix == instruction.RRRICI {\n\t\tthis.ExecuteRrrici(instruction_)\n\t} else if suffix == instruction.ZRRI {\n\t\tthis.ExecuteZrri(instruction_)\n\t} else if suffix == instruction.ZRRICI {\n\t\tthis.ExecuteZrrici(instruction_)\n\t} else if suffix == instruction.S_RRRI || suffix == instruction.U_RRRI {\n\t\tthis.ExecuteSRrri(instruction_)\n\t} else if suffix == instruction.S_RRRICI || suffix == instruction.U_RRRICI {\n\t\tthis.ExecuteSRrrici(instruction_)\n\t} else if suffix == instruction.RIR {\n\t\tthis.ExecuteRir(instruction_)\n\t} else if suffix == instruction.RIRC {\n\t\tthis.ExecuteRirc(instruction_)\n\t} else if suffix == instruction.RIRCI {\n\t\tthis.ExecuteRirci(instruction_)\n\t} else if suffix == instruction.ZIR {\n\t\tthis.ExecuteZir(instruction_)\n\t} else if suffix == instruction.ZIRC {\n\t\tthis.ExecuteZirc(instruction_)\n\t} else if suffix == instruction.ZIRCI {\n\t\tthis.ExecuteZirci(instruction_)\n\t} else if suffix == instruction.S_RIRC || suffix == instruction.U_RIRC {\n\t\tthis.ExecuteSRirc(instruction_)\n\t} else if suffix == instruction.S_RIRCI || suffix == instruction.U_RIRCI {\n\t\tthis.ExecuteSRirci(instruction_)\n\t} else if suffix == instruction.R {\n\t\tthis.ExecuteR(instruction_)\n\t} else if suffix == instruction.RCI {\n\t\tthis.ExecuteRci(instruction_)\n\t} else if suffix == instruction.Z {\n\t\tthis.ExecuteZ(instruction_)\n\t} else if suffix == instruction.ZCI {\n\t\tthis.ExecuteZci(instruction_)\n\t} else if suffix == instruction.S_R || suffix == instruction.U_R {\n\t\tthis.ExecuteSR(instruction_)\n\t} else if suffix == instruction.S_RCI || suffix == instruction.U_RCI {\n\t\tthis.ExecuteSRci(instruction_)\n\t} else if suffix == instruction.CI {\n\t\tthis.ExecuteCi(instruction_)\n\t} else if suffix == instruction.I {\n\t\tthis.ExecuteI(instruction_)\n\t} else if suffix == instruction.DDCI {\n\t\tthis.ExecuteDdci(instruction_)\n\t} else if suffix == instruction.ERRI {\n\t\tthis.ExecuteErri(instruction_)\n\t} else if suffix == instruction.S_ERRI || suffix == instruction.U_ERRI {\n\t\tthis.ExecuteSErri(instruction_)\n\t} else if suffix == instruction.EDRI {\n\t\tthis.ExecuteEdri(instruction_)\n\t} else if suffix == instruction.ERII {\n\t\tthis.ExecuteErii(instruction_)\n\t} else if suffix == instruction.ERIR {\n\t\tthis.ExecuteErir(instruction_)\n\t} else if suffix == instruction.ERID {\n\t\tthis.ExecuteErid(instruction_)\n\t} else if suffix == instruction.DMA_RRI {\n\t\tthis.ExecuteDmaRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n\n\tif this.verbose >= 2 {\n\t\tfmt.Println(this.PrintRegFile(thread))\n\t}\n}\n\nfunc (this *Logic) ExecuteRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_acquire_rici_op_code := instruction_.AcquireRiciOpCodes()[op_code]; is_acquire_rici_op_code {\n\t\tthis.ExecuteAcquireRici(instruction_)\n\t} else if _, is_release_rici_op_code := instruction_.ReleaseRiciOpCodes()[op_code]; is_release_rici_op_code {\n\t\tthis.ExecuteReleaseRici(instruction_)\n\t} else if _, is_boot_rici_op_code := instruction_.BootRiciOpCodes()[op_code]; is_boot_rici_op_code {\n\t\tthis.ExecuteBootRici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAcquireRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AcquireRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid acquire RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tatomic_address := this.alu.AtomicAddressHash(ra, imm)\n\n\tcan_acquire := this.atomic.CanAcquire(atomic_address)\n\tif can_acquire {\n\t\tthis.atomic.Acquire(atomic_address, thread.ThreadId())\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tif can_acquire {\n\t\tthis.SetAcquireCc(instruction_, 0)\n\t} else {\n\t\tthis.SetAcquireCc(instruction_, 1)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tif can_acquire {\n\t\tthis.SetFlags(instruction_, 0, false)\n\t} else {\n\t\tthis.SetFlags(instruction_, 1, false)\n\t}\n}\n\nfunc (this *Logic) ExecuteReleaseRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ReleaseRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid release RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tatomic_address := this.alu.AtomicAddressHash(ra, imm)\n\n\tcan_release := this.atomic.CanRelease(atomic_address, thread.ThreadId())\n\tif can_release {\n\t\tthis.atomic.Release(atomic_address, thread.ThreadId())\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tif can_release {\n\t\tthis.SetAcquireCc(instruction_, 0)\n\t} else {\n\t\tthis.SetAcquireCc(instruction_, 1)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tif can_release {\n\t\tthis.SetFlags(instruction_, 0, false)\n\t} else {\n\t\tthis.SetFlags(instruction_, 1, false)\n\t}\n}\n\nfunc (this *Logic) ExecuteBootRici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.BootRiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid boot RICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RICI {\n\t\terr := errors.New(\"suffix is not RICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.UNSIGNED)\n\timm := instruction_.Imm().Value()\n\n\tthread_id := int(this.alu.AtomicAddressHash(ra, imm))\n\n\tthread.RegFile().ClearConditions()\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.BOOT {\n\t\tcan_boot := this.thread_scheduler.Boot(thread_id)\n\t\tif can_boot {\n\t\t\tthis.SetBootCc(instruction_, ra, 0)\n\t\t\tthis.SetFlags(instruction_, 0, false)\n\t\t} else {\n\t\t\tthis.SetBootCc(instruction_, ra, 1)\n\t\t\tthis.SetFlags(instruction_, 1, false)\n\t\t}\n\t} else if op_code == instruction.RESUME {\n\t\tcan_resume := this.thread_scheduler.Awake(thread_id)\n\t\tif can_resume {\n\t\t\tthis.SetBootCc(instruction_, ra, 0)\n\t\t\tthis.SetFlags(instruction_, 0, false)\n\t\t} else {\n\t\t\tthis.SetBootCc(instruction_, ra, 1)\n\t\t\tthis.SetFlags(instruction_, 1, false)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddRri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrRri(instruction_)\n\t} else if _, is_call_rri_op_code := instruction_.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.ExecuteCallRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteCallRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CallRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid call RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif imm == 0 {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else {\n\t\tresult, carry, _ = this.alu.Add(ra*iram_data_size, imm)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tpc := thread.RegFile().ReadPcReg()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), pc+iram_data_size)\n\n\tthread.RegFile().WritePcReg(result)\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rric_op_code := instruction_.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.ExecuteAddRric(instruction_)\n\t} else if _, is_asrc_rric_op_code := instruction_.AsrRricOpCodes()[op_code]; is_asrc_rric_op_code {\n\t\tthis.ExecuteAsrRric(instruction_)\n\t} else if _, is_sub_rric_op_code := instruction_.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.ExecuteSubRric(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubRric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIC {\n\t\terr := errors.New(\"suffix is not RRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, imm, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddRrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndRrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrRrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubRrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRICI {\n\t\terr := errors.New(\"suffix is not RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRIF {\n\t\terr := errors.New(\"suffix is not RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRR {\n\t\terr := errors.New(\"suffix is not RRR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, rb, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tif op_code != instruction.CALL {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\t\tthread.RegFile().IncrementPcReg()\n\t} else {\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tpc := thread.RegFile().ReadPcReg()\n\t\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), pc+iram_data_size)\n\t\tthread.RegFile().WritePcReg(result)\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrc_op_code := instruction_.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tthis.ExecuteAddRrrc(instruction_)\n\t} else if _, is_rsub_rrrc_op_code := instruction_.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tthis.ExecuteRsubRrrc(instruction_)\n\t} else if _, is_sub_rrrc_op_code := instruction_.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\tthis.ExecuteSubRrrc(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRsubRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, ra, rb, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSubRrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRC {\n\t\terr := errors.New(\"suffix is not RRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, rb, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrci_op_code := instruction_.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tthis.ExecuteAddRrrci(instruction_)\n\t} else if _, is_and_rrrci_op_code := instruction_.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tthis.ExecuteAndRrrci(instruction_)\n\t} else if _, is_asr_rrrci_op_code := instruction_.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tthis.ExecuteAsrRrrci(instruction_)\n\t} else if _, is_mul_rrrci_op_code := instruction_.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tthis.ExecuteMulRrrci(instruction_)\n\t} else if _, is_rsub_rrrci_op_code := instruction_.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tthis.ExecuteRsubRrrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetMulNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRsubRrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRCI {\n\t\terr := errors.New(\"suffix is not RRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, overflow = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, rb, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddZri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrZri(instruction_)\n\t} else if _, is_call_rri_op_code := instruction_.CallRriOpCodes()[op_code]; is_call_rri_op_code {\n\t\tthis.ExecuteCallZri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteCallZri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CallRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid call RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRI {\n\t\terr := errors.New(\"suffix is not ZRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif imm == 0 {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else {\n\t\tresult, carry, _ = this.alu.Add(ra*iram_data_size, imm)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WritePcReg(result)\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rric_op_code := instruction_.AddRricOpCodes()[op_code]; is_add_rric_op_code {\n\t\tthis.ExecuteAddZric(instruction_)\n\t} else if _, is_asrc_rric_op_code := instruction_.AsrRricOpCodes()[op_code]; is_asrc_rric_op_code {\n\t\tthis.ExecuteAsrZric(instruction_)\n\t} else if _, is_sub_rric_op_code := instruction_.SubRricOpCodes()[op_code]; is_sub_rric_op_code {\n\t\tthis.ExecuteSubZric(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubZric(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRricOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRIC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIC {\n\t\terr := errors.New(\"suffix is not ZRIC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, imm, result, carry, overflow)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddZrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndZrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrZrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubZrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubZrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRICI {\n\t\terr := errors.New(\"suffix is not ZRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRIF {\n\t\terr := errors.New(\"suffix is not ZRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRR {\n\t\terr := errors.New(\"suffix is not ZRR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, rb, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tif op_code != instruction.CALL {\n\t\tthread.RegFile().IncrementPcReg()\n\t} else {\n\t\tthread.RegFile().WritePcReg(result)\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrc_op_code := instruction_.AddRrrcOpCodes()[op_code]; is_add_rrrc_op_code {\n\t\tthis.ExecuteAddZrrc(instruction_)\n\t} else if _, is_rsub_rrrc_op_code := instruction_.RsubRrrcOpCodes()[op_code]; is_rsub_rrrc_op_code {\n\t\tthis.ExecuteRsubZrrc(instruction_)\n\t} else if _, is_sub_rrrc_op_code := instruction_.SubRrrcOpCodes()[op_code]; is_sub_rrrc_op_code {\n\t\tthis.ExecuteSubZrrc(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t\tcarry = false\n\t} else if op_code == instruction.CALL {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRsubZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, _ = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(rb, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, ra, rb, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSubZrrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRrrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRC {\n\t\terr := errors.New(\"suffix is not ZRRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetExtSubSetCc(instruction_, ra, rb, result, carry, overflow)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrrci_op_code := instruction_.AddRrrciOpCodes()[op_code]; is_add_rrrci_op_code {\n\t\tthis.ExecuteAddZrrci(instruction_)\n\t} else if _, is_and_rrrci_op_code := instruction_.AndRrrciOpCodes()[op_code]; is_and_rrrci_op_code {\n\t\tthis.ExecuteAndZrrci(instruction_)\n\t} else if _, is_asr_rrrci_op_code := instruction_.AsrRrrciOpCodes()[op_code]; is_asr_rrrci_op_code {\n\t\tthis.ExecuteAsrZrrci(instruction_)\n\t} else if _, is_mul_rrrci_op_code := instruction_.MulRrrciOpCodes()[op_code]; is_mul_rrrci_op_code {\n\t\tthis.ExecuteMulZrrci(instruction_)\n\t} else if _, is_rsub_rrrci_op_code := instruction_.RsubRrrciOpCodes()[op_code]; is_rsub_rrrci_op_code {\n\t\tthis.ExecuteRsubZrrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, rb)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, rb)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, rb)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, rb)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, rb)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, rb)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, rb)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, rb)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, rb)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, rb)\n\t} else if op_code == instruction.CMPB4 {\n\t\tresult = this.alu.Cmpb4(ra, rb)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, rb)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, rb)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, rb)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, rb)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, rb)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, rb)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, rb)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, rb)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, rb)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.MUL_SH_SH {\n\t\tresult = this.alu.MulShSh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_SL {\n\t\tresult = this.alu.MulShSl(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UH {\n\t\tresult = this.alu.MulShUh(ra, rb)\n\t} else if op_code == instruction.MUL_SH_UL {\n\t\tresult = this.alu.MulShUl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SH {\n\t\tresult = this.alu.MulSlSh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_SL {\n\t\tresult = this.alu.MulSlSl(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UH {\n\t\tresult = this.alu.MulSlUh(ra, rb)\n\t} else if op_code == instruction.MUL_SL_UL {\n\t\tresult = this.alu.MulSlUl(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UH {\n\t\tresult = this.alu.MulUhUh(ra, rb)\n\t} else if op_code == instruction.MUL_UH_UL {\n\t\tresult = this.alu.MulUhUl(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UH {\n\t\tresult = this.alu.MulUlUh(ra, rb)\n\t} else if op_code == instruction.MUL_UL_UL {\n\t\tresult = this.alu.MulUlUl(ra, rb)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetMulNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRsubZrrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RsubRrrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid rsub RRRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRCI {\n\t\terr := errors.New(\"suffix is not ZRRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.RSUB {\n\t\tresult, carry, overflow = this.alu.Sub(rb, ra)\n\t} else if op_code == instruction.RSUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(rb, ra, carry_flag)\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(ra, rb)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, rb, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, rb, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rri_op_code := instruction_.AddRriOpCodes()[op_code]; is_add_rri_op_code {\n\t\tthis.ExecuteAddSRri(instruction_)\n\t} else if _, is_asr_rri_op_code := instruction_.AsrRriOpCodes()[op_code]; is_asr_rri_op_code {\n\t\tthis.ExecuteAsrSRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAsrSRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRI && instruction_.Suffix() != instruction.U_RRI {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRric(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRric is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_add_rrici_op_code := instruction_.AddRriciOpCodes()[op_code]; is_add_rrici_op_code {\n\t\tthis.ExecuteAddSRrici(instruction_)\n\t} else if _, is_and_rrici_op_code := instruction_.AndRriciOpCodes()[op_code]; is_and_rrici_op_code {\n\t\tthis.ExecuteAndSRrici(instruction_)\n\t} else if _, is_asr_rrici_op_code := instruction_.AsrRriciOpCodes()[op_code]; is_asr_rrici_op_code {\n\t\tthis.ExecuteAsrSRrici(instruction_)\n\t} else if _, is_sub_rrici_op_code := instruction_.SubRriciOpCodes()[op_code]; is_sub_rrici_op_code {\n\t\tthis.ExecuteSubSRrici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteAddSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AddRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid add RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, overflow = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Addc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetAddNzCc(instruction_, ra, result, carry, overflow)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteAndSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AndRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid and RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteAsrSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.AsrRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid asr RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult = this.alu.Asr(ra, imm)\n\t} else if op_code == instruction.LSL {\n\t\tresult = this.alu.Lsl(ra, imm)\n\t} else if op_code == instruction.LSL1 {\n\t\tresult = this.alu.Lsl1(ra, imm)\n\t} else if op_code == instruction.LSL1X {\n\t\tresult = this.alu.Lsl1x(ra, imm)\n\t} else if op_code == instruction.LSLX {\n\t\tresult = this.alu.Lslx(ra, imm)\n\t} else if op_code == instruction.LSR {\n\t\tresult = this.alu.Lsr(ra, imm)\n\t} else if op_code == instruction.LSR1 {\n\t\tresult = this.alu.Lsr1(ra, imm)\n\t} else if op_code == instruction.LSR1X {\n\t\tresult = this.alu.Lsr1x(ra, imm)\n\t} else if op_code == instruction.LSRX {\n\t\tresult = this.alu.Lsrx(ra, imm)\n\t} else if op_code == instruction.ROL {\n\t\tresult = this.alu.Rol(ra, imm)\n\t} else if op_code == instruction.ROR {\n\t\tresult = this.alu.Ror(ra, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetImmShiftNzCc(instruction_, ra, result)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteSubSRrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SubRriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sub RRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRICI && instruction_.Suffix() != instruction.U_RRICI {\n\t\terr := errors.New(\"suffix is not S_RRICI nor U_RRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ASR {\n\t\tresult, carry, overflow = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(ra, imm, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, ra, imm, result, carry, overflow)\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRICI {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRICI {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRI nor U_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrif(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrifOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRIF op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.S_RRIF && instruction_.Suffix() != instruction.U_RRIF {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.ADD {\n\t\tresult, carry, _ = this.alu.Add(ra, imm)\n\t} else if op_code == instruction.ADDC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Addc(ra, imm, carry_flag)\n\t} else if op_code == instruction.AND {\n\t\tresult = this.alu.And(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ANDN {\n\t\tresult = this.alu.Andn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NAND {\n\t\tresult = this.alu.Nand(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NOR {\n\t\tresult = this.alu.Nor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.NXOR {\n\t\tresult = this.alu.Nxor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.OR {\n\t\tresult = this.alu.Or(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.ORN {\n\t\tresult = this.alu.Orn(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(ra, imm)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(ra, imm, carry_flag)\n\t} else if op_code == instruction.XOR {\n\t\tresult = this.alu.Xor(ra, imm)\n\t\tcarry = false\n\t} else if op_code == instruction.HASH {\n\t\tresult = this.alu.Hash(ra, imm)\n\t\tcarry = false\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\n\tvar even int64\n\tvar odd int64\n\tif instruction_.Suffix() == instruction.S_RRIF {\n\t\teven, odd = this.alu.SignedExtension(result)\n\t} else if instruction_.Suffix() == instruction.U_RRIF {\n\t\teven, odd = this.alu.UnsignedExtension(result)\n\t} else {\n\t\terr := errors.New(\"suffix is not S_RRIF nor U_RRIF\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrr(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrr is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RR {\n\t\terr := errors.New(\"suffix is not RR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_cao_rrci_op_code := instruction_.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tthis.ExecuteCaoRrci(instruction_)\n\t} else if _, is_extsb_rrci_op_code := instruction_.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tthis.ExecuteExtsbRrci(instruction_)\n\t} else if _, is_time_cfg_rrci_op_code := instruction_.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\tthis.ExecuteTimeCfgRrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteCaoRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CaoRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid cao RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetCountNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteExtsbRrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ExtsbRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid extsb RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRCI {\n\t\terr := errors.New(\"suffix is not RRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteTimeCfgRrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteTimeCfgRrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteZr(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZR {\n\t\terr := errors.New(\"suffix is not ZR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteZrc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrcOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRC {\n\t\terr := errors.New(\"suffix is not RRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else if op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else if op_code == instruction.TIME_CFG {\n\t\terr := errors.New(\"TimeCfg is not yet implemented\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogSetCc(instruction_, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_cao_rrci_op_code := instruction_.CaoRrciOpCodes()[op_code]; is_cao_rrci_op_code {\n\t\tthis.ExecuteCaoZrci(instruction_)\n\t} else if _, is_extsb_rrci_op_code := instruction_.ExtsbRrciOpCodes()[op_code]; is_extsb_rrci_op_code {\n\t\tthis.ExecuteExtsbZrci(instruction_)\n\t} else if _, is_time_cfg_rrci_op_code := instruction_.TimeCfgRrciOpCodes()[op_code]; is_time_cfg_rrci_op_code {\n\t\tthis.ExecuteTimeCfgZrci(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteCaoZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CaoRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid cao RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.CAO {\n\t\tresult = this.alu.Cao(ra)\n\t} else if op_code == instruction.CLO {\n\t\tresult = this.alu.Clo(ra)\n\t} else if op_code == instruction.CLS {\n\t\tresult = this.alu.Cls(ra)\n\t} else if op_code == instruction.CLZ {\n\t\tresult = this.alu.Clz(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetCountNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteExtsbZrci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ExtsbRrciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid extsb RRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRCI {\n\t\terr := errors.New(\"suffix is not ZRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.EXTSB {\n\t\tresult = this.alu.Extsb(ra)\n\t} else if op_code == instruction.EXTSH {\n\t\tresult = this.alu.Extsh(ra)\n\t} else if op_code == instruction.EXTUB {\n\t\tresult = this.alu.Extub(ra)\n\t} else if op_code == instruction.EXTUH {\n\t\tresult = this.alu.Extuh(ra)\n\t} else if op_code == instruction.SATS {\n\t\tresult = this.alu.Sats(ra)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetLogNzCc(instruction_, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteTimeCfgZrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteTimeCfgZrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRr(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRr is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_div_step_drdici_op_code := instruction_.DivStepDrdiciOpCodes()[op_code]; is_div_step_drdici_op_code {\n\t\tthis.ExecuteDivStepDrdici(instruction_)\n\t} else if _, is_mul_step_drdici_op_code := instruction_.MulStepDrdiciOpCodes()[op_code]; is_mul_step_drdici_op_code {\n\t\tthis.ExecuteMulStepDrdici(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteDivStepDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DivStepDrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid div_step DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), abi.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tdbo_word := new(abi.Word)\n\tdbo_word.Init(mram_data_width)\n\tdbo_word.SetValue(dbo)\n\n\tra_shift_value := this.alu.Lsl(ra, imm)\n\tra_shift_word := new(abi.Word)\n\tra_shift_word.Init(mram_data_width)\n\tra_shift_word.SetValue(ra_shift_value)\n\n\tresult, _, _ := this.alu.Sub(dbo, ra_shift_value)\n\n\tvar dce int64\n\tvar dco int64\n\tif dbo_word.Value(abi.UNSIGNED) >= ra_shift_word.Value(abi.UNSIGNED) {\n\t\tdce = this.alu.Lsl1(dbe, 1)\n\t\tdco = result\n\t} else {\n\t\tdce = this.alu.Lsl(dbe, 1)\n\t\tdco = thread.RegFile().ReadGpReg(instruction_.Dc().OddRegDescriptor(), abi.SIGNED)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivCc(instruction_, ra)\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dce)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dco)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, false)\n}\n\nfunc (this *Logic) ExecuteMulStepDrdici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MulStepDrdiciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid mul_step DRDICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DRDICI {\n\t\terr := errors.New(\"suffix is not DRDICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), abi.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tresult1 := this.alu.Lsr(dbe, 1)\n\tresult2, _, _ := this.alu.Sub(this.alu.And(dbe, 1), 1)\n\n\tvar dco int64\n\tif result2 == 0 {\n\t\tdco, _, _ = this.alu.Add(dbo, this.alu.Lsl(ra, imm))\n\t} else {\n\t\tdco = thread.RegFile().ReadGpReg(instruction_.Dc().OddRegDescriptor(), abi.SIGNED)\n\t}\n\n\tdce := this.alu.Lsr(dbe, 1)\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetBootCc(instruction_, ra, result1)\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dce)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dco)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result1, false)\n}\n\nfunc (this *Logic) ExecuteRrri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRI {\n\t\terr := errors.New(\"suffix is not RRRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRrrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RRRICI {\n\t\terr := errors.New(\"suffix is not RRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivNzCc(instruction_, ra)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRI {\n\t\terr := errors.New(\"suffix is not ZRRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZrrici(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RrriciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RRRICI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZRRICI {\n\t\terr := errors.New(\"suffix is not ZRRICI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LSL_ADD {\n\t\tresult, carry, _ = this.alu.LslAdd(ra, rb, imm)\n\t} else if op_code == instruction.LSL_SUB {\n\t\tresult, carry, _ = this.alu.LslSub(ra, rb, imm)\n\t} else if op_code == instruction.LSR_ADD {\n\t\tresult, carry, _ = this.alu.LsrAdd(ra, rb, imm)\n\t} else if op_code == instruction.ROL_ADD {\n\t\tresult, carry, _ = this.alu.RolAdd(ra, rb, imm)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetDivNzCc(instruction_, ra)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRrri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRrrici(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRrrici is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIR {\n\t\terr := errors.New(\"suffix is not RIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRirc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RircOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIRC {\n\t\terr := errors.New(\"suffix is not RIRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, imm, ra, result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 1)\n\t} else {\n\t\tthread.RegFile().WriteGpReg(instruction_.Rc(), 0)\n\t}\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteRirci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.RIRCI {\n\t\terr := errors.New(\"suffix is not RIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, imm, ra, result, carry, overflow)\n\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIR {\n\t\terr := errors.New(\"suffix is not ZIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZirc(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RircOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRC op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIRC {\n\t\terr := errors.New(\"suffix is not ZIRC\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, _ = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, _ = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubSetCc(instruction_, imm, ra, result)\n\n\tthread.RegFile().IncrementPcReg()\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteZirci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.RirciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid RIRCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ZIRCI {\n\t\terr := errors.New(\"suffix is not ZIRCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\timm := instruction_.Imm().Value()\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\n\tvar result int64\n\tvar carry bool\n\tvar overflow bool\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SUB {\n\t\tresult, carry, overflow = this.alu.Sub(imm, ra)\n\t} else if op_code == instruction.SUBC {\n\t\tcarry_flag := thread.RegFile().ReadFlagReg(instruction.CARRY)\n\t\tresult, carry, overflow = this.alu.Subc(imm, ra, carry_flag)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthis.SetSubNzCc(instruction_, imm, ra, result, carry, overflow)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n\n\tthis.SetFlags(instruction_, result, carry)\n}\n\nfunc (this *Logic) ExecuteSRirc(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRirc is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRirci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRirci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteR(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteR is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteRci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteRci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteZ(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ROpCodes()[instruction_.OpCode()]; !found &&\n\t\tinstruction_.OpCode() != instruction.NOP {\n\t\terr := errors.New(\"op code is not a valid R op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.Z {\n\t\terr := errors.New(\"suffix is not Z\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteZci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteZci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSR(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSR is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSRci(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSRci is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteCi(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.CiOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid CI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.CI {\n\t\terr := errors.New(\"suffix is not CI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tthis.thread_scheduler.Sleep(thread.ThreadId())\n\n\tthread.RegFile().ClearConditions()\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteI(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteI is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteDdci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_movd_ddci_op_code := instruction_.MovdDdciOpCodes()[op_code]; is_movd_ddci_op_code {\n\t\tthis.ExecuteMovdDdci(instruction_)\n\t} else if _, is_swapd_ddci_op_code := instruction_.SwapdDdciOpCodes()[op_code]; is_swapd_ddci_op_code {\n\t\tthis.ExecuteSwapdDdciRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteMovdDdci(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.MovdDdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid movd DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), abi.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), abi.SIGNED)\n\n\tthread.RegFile().ClearConditions()\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dbe)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dbo)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteSwapdDdciRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SwapdDdciOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid movd DDCI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DDCI {\n\t\terr := errors.New(\"suffix is not DDCI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tdbe := thread.RegFile().ReadGpReg(instruction_.Db().EvenRegDescriptor(), abi.SIGNED)\n\tdbo := thread.RegFile().ReadGpReg(instruction_.Db().OddRegDescriptor(), abi.SIGNED)\n\n\tthread.RegFile().ClearConditions()\n\n\tthread.RegFile().WriteGpReg(instruction_.Dc().EvenRegDescriptor(), dbo)\n\tthread.RegFile().WriteGpReg(instruction_.Dc().OddRegDescriptor(), dbe)\n\n\tif thread.RegFile().ReadConditionReg(instruction_.Condition()) {\n\t\tthread.RegFile().WritePcReg(instruction_.Pc().Value())\n\t} else {\n\t\tthread.RegFile().IncrementPcReg()\n\t}\n}\n\nfunc (this *Logic) ExecuteErri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ErriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERRI {\n\t\terr := errors.New(\"suffix is not ERRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\toff := instruction_.Off().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tvar result int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LBS {\n\t\tresult = this.operand_collector.Lbs(address)\n\t} else if op_code == instruction.LBU {\n\t\tresult = this.operand_collector.Lbu(address)\n\t} else if op_code == instruction.LHS {\n\t\tresult = this.operand_collector.Lhs(address)\n\t} else if op_code == instruction.LHU {\n\t\tresult = this.operand_collector.Lhu(address)\n\t} else if op_code == instruction.LW {\n\t\tresult = this.operand_collector.Lw(address)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WriteGpReg(instruction_.Rc(), result)\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteSErri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteSErri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteEdri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EdriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid EDRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.EDRI {\n\t\terr := errors.New(\"suffix is not EDRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\toff := instruction_.Off().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tvar even int64\n\tvar odd int64\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.LD {\n\t\teven, odd = this.operand_collector.Ld(address)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().WritePairReg(instruction_.Dc(), even, odd)\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErii(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EriiOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERII op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERII {\n\t\terr := errors.New(\"suffix is not ERII\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\toff := instruction_.Off().Value()\n\timm := instruction_.Imm().Value()\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SB {\n\t\tthis.operand_collector.Sb(address, imm)\n\t} else if op_code == instruction.SB_ID {\n\t\tthis.operand_collector.Sb(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SH {\n\t\tthis.operand_collector.Sh(address, imm)\n\t} else if op_code == instruction.SH_ID {\n\t\tthis.operand_collector.Sh(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SW {\n\t\tthis.operand_collector.Sw(address, imm)\n\t} else if op_code == instruction.SW_ID {\n\t\tthis.operand_collector.Sw(address, this.alu.Or(int64(thread.ThreadId()), imm))\n\t} else if op_code == instruction.SD {\n\t\teven, odd := this.alu.UnsignedExtension(imm)\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else if op_code == instruction.SD_ID {\n\t\teven, odd := this.alu.UnsignedExtension(this.alu.Or(int64(thread.ThreadId()), imm))\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErir(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.ErirOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERIR op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERIR {\n\t\terr := errors.New(\"suffix is not ERIR\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\toff := instruction_.Off().Value()\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\trb_word := new(abi.Word)\n\trb_word.Init(config_loader.MramDataWidth())\n\trb_word.SetValue(rb)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SB {\n\t\tthis.operand_collector.Sb(address, rb_word.BitSlice(abi.UNSIGNED, 0, 8))\n\t} else if op_code == instruction.SH {\n\t\tthis.operand_collector.Sh(address, rb_word.BitSlice(abi.UNSIGNED, 0, 16))\n\t} else if op_code == instruction.SW {\n\t\tthis.operand_collector.Sw(address, rb_word.BitSlice(abi.UNSIGNED, 0, 32))\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteErid(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.EridOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ERID op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.ERID {\n\t\terr := errors.New(\"suffix is not ERID\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\toff := instruction_.Off().Value()\n\teven, odd := thread.RegFile().ReadPairReg(instruction_.Db(), abi.SIGNED)\n\n\taddress, _, _ := this.alu.Add(ra, off)\n\n\top_code := instruction_.OpCode()\n\tif op_code == instruction.SD {\n\t\tthis.operand_collector.Sd(address, even, odd)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthread.RegFile().ClearConditions()\n\tthread.RegFile().IncrementPcReg()\n}\n\nfunc (this *Logic) ExecuteDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.DmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\top_code := instruction_.OpCode()\n\tif _, is_ldma_dma_rri_op_code := instruction_.LdmaDmaRriOpCodes()[op_code]; is_ldma_dma_rri_op_code {\n\t\tthis.ExecuteLdmaDmaRri(instruction_)\n\t} else if _, is_ldmai_dma_rri_op_code := instruction_.LdmaiDmaRriOpCodes()[op_code]; is_ldmai_dma_rri_op_code {\n\t\tthis.ExecuteLdmaiDmaRri(instruction_)\n\t} else if _, is_sdma_dma_rri_op_code := instruction_.SdmaDmaRriOpCodes()[op_code]; is_sdma_dma_rri_op_code {\n\t\tthis.ExecuteSdmaDmaRri(instruction_)\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Logic) ExecuteLdmaDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.LdmaDmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid ldma DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_end_address := config_loader.WramOffset() + config_loader.WramSize()\n\twram_end_address_width := int(math.Floor(math.Log2(float64(wram_end_address))) + 1)\n\twram_mask := this.Pow2(wram_end_address_width) - 1\n\twram_address := this.alu.And(ra, wram_mask)\n\n\tmram_end_address := config_loader.MramOffset() + config_loader.MramSize()\n\tmram_end_address_width := int(math.Floor(math.Log2(float64(mram_end_address))) + 1)\n\tmram_mask := this.Pow2(mram_end_address_width) - 1\n\tmram_address := this.alu.And(rb, mram_mask)\n\n\tsize := (1 + this.alu.And(imm+this.alu.And(this.alu.Lsr(ra, 24), 255), 255)) * this.min_access_granularity\n\n\tthis.dma.TransferFromMramToWram(wram_address, mram_address, size, instruction_)\n\n\tthread.RegFile().ClearConditions()\n}\n\nfunc (this *Logic) ExecuteLdmaiDmaRri(instruction_ *instruction.Instruction) {\n\terr := errors.New(\"ExecuteLdmaiDmaRri is not yet implemented\")\n\tpanic(err)\n}\n\nfunc (this *Logic) ExecuteSdmaDmaRri(instruction_ *instruction.Instruction) {\n\tif _, found := instruction_.SdmaDmaRriOpCodes()[instruction_.OpCode()]; !found {\n\t\terr := errors.New(\"op code is not a valid sdma DMA_RRI op code\")\n\t\tpanic(err)\n\t} else if instruction_.Suffix() != instruction.DMA_RRI {\n\t\terr := errors.New(\"suffix is not DMA_RRI\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.scoreboard[instruction_]\n\n\tra := thread.RegFile().ReadSrcReg(instruction_.Ra(), abi.SIGNED)\n\trb := thread.RegFile().ReadSrcReg(instruction_.Rb(), abi.SIGNED)\n\timm := instruction_.Imm().Value()\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\twram_end_address := config_loader.WramOffset() + config_loader.WramSize()\n\twram_end_address_width := int(math.Floor(math.Log2(float64(wram_end_address))) + 1)\n\twram_mask := this.Pow2(wram_end_address_width) - 1\n\twram_address := this.alu.And(ra, wram_mask)\n\n\tmram_end_address := config_loader.MramOffset() + config_loader.MramSize()\n\tmram_end_address_width := int(math.Floor(math.Log2(float64(mram_end_address))) + 1)\n\tmram_mask := this.Pow2(mram_end_address_width) - 1\n\tmram_address := this.alu.And(rb, mram_mask)\n\n\tsize := (1 + this.alu.And(imm+this.alu.And(this.alu.Lsr(ra, 24), 255), 255)) * this.min_access_granularity\n\n\tthis.dma.TransferFromWramToMram(wram_address, mram_address, size, instruction_)\n\n\tthread.RegFile().ClearConditions()\n}\n\nfunc (this *Logic) SetAcquireCc(instruction_ *instruction.Instruction, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n}\n\nfunc (this *Logic) SetAddNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tresult_word := new(abi.Word)\n\tresult_word.Init(config_loader.MramDataWidth())\n\tresult_word.SetValue(result)\n\n\tif result_word.Bit(6) {\n\t\tthread.RegFile().SetCondition(cc.NC5)\n\t}\n\n\tif result_word.Bit(7) {\n\t\tthread.RegFile().SetCondition(cc.NC6)\n\t}\n\n\tif result_word.Bit(8) {\n\t\tthread.RegFile().SetCondition(cc.NC7)\n\t}\n\n\tif result_word.Bit(9) {\n\t\tthread.RegFile().SetCondition(cc.NC8)\n\t}\n\n\tif result_word.Bit(10) {\n\t\tthread.RegFile().SetCondition(cc.NC9)\n\t}\n\n\tif result_word.Bit(11) {\n\t\tthread.RegFile().SetCondition(cc.NC10)\n\t}\n\n\tif result_word.Bit(12) {\n\t\tthread.RegFile().SetCondition(cc.NC11)\n\t}\n\n\tif result_word.Bit(13) {\n\t\tthread.RegFile().SetCondition(cc.NC12)\n\t}\n\n\tif result_word.Bit(14) {\n\t\tthread.RegFile().SetCondition(cc.NC13)\n\t}\n\n\tif result_word.Bit(15) {\n\t\tthread.RegFile().SetCondition(cc.NC14)\n\t}\n}\n\nfunc (this *Logic) SetBootCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetCountNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif result == int64(config_loader.MramDataWidth()) {\n\t\tthread.RegFile().SetCondition(cc.MAX)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NMAX)\n\t}\n}\n\nfunc (this *Logic) SetDivCc(instruction_ *instruction.Instruction, operand1 int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetDivNzCc(instruction_ *instruction.Instruction, operand1 int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetExtSubSetCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tif word1.Value(abi.UNSIGNED) < word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) <= word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LEU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) > word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) >= word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GEU)\n\t}\n\n\tif word1.Value(abi.SIGNED) < word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTS)\n\t}\n\n\tif word1.Value(abi.SIGNED) <= word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LES)\n\t}\n\n\tif word1.Value(abi.SIGNED) > word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTS)\n\t}\n\n\tif word1.Value(abi.SIGNED) >= word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GES)\n\t}\n\n\tif carry || thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XLEU)\n\t}\n\n\tif carry || !thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XGTU)\n\t}\n\n\tif thread.RegFile().ReadFlagReg(instruction.ZERO) && (result < 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XLES)\n\t}\n\n\tif !thread.RegFile().ReadFlagReg(instruction.ZERO) && (result >= 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XGTS)\n\t}\n}\n\nfunc (this *Logic) SetImmShiftNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif result%2 == 0 {\n\t\tthread.RegFile().SetCondition(cc.E)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.O)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1%2 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SE)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SO)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetLogNzCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n}\n\nfunc (this *Logic) SetLogSetCc(instruction_ *instruction.Instruction, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n}\n\nfunc (this *Logic) SetMulNzCc(instruction_ *instruction.Instruction, operand1 int64, result int64) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == 0 {\n\t\tthread.RegFile().SetCondition(cc.SZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SNZ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tif result < 256 {\n\t\tthread.RegFile().SetCondition(cc.SMALL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.LARGE)\n\t}\n}\n\nfunc (this *Logic) SetSubNzCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n\tcarry bool,\n\toverflow bool,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetCondition(cc.C)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NC)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif overflow {\n\t\tthread.RegFile().SetCondition(cc.OV)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NOV)\n\t}\n\n\tif result >= 0 {\n\t\tthread.RegFile().SetCondition(cc.PL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.MI)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n\n\tif operand1 >= 0 {\n\t\tthread.RegFile().SetCondition(cc.SPL)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.SMI)\n\t}\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_width := config_loader.MramDataWidth()\n\n\tword1 := new(abi.Word)\n\tword1.Init(mram_data_width)\n\tword1.SetValue(operand1)\n\n\tword2 := new(abi.Word)\n\tword2.Init(mram_data_width)\n\tword2.SetValue(operand2)\n\n\tif word1.Value(abi.UNSIGNED) < word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) <= word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LEU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) > word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTU)\n\t}\n\n\tif word1.Value(abi.UNSIGNED) >= word2.Value(abi.UNSIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GEU)\n\t}\n\n\tif word1.Value(abi.SIGNED) < word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LTS)\n\t}\n\n\tif word1.Value(abi.SIGNED) <= word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.LES)\n\t}\n\n\tif word1.Value(abi.SIGNED) > word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GTS)\n\t}\n\n\tif word1.Value(abi.SIGNED) >= word2.Value(abi.SIGNED) {\n\t\tthread.RegFile().SetCondition(cc.GES)\n\t}\n\n\tif carry || thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XLEU)\n\t}\n\n\tif carry || !thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XGTU)\n\t}\n\n\tif thread.RegFile().ReadFlagReg(instruction.ZERO) && (result < 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XLES)\n\t}\n\n\tif !thread.RegFile().ReadFlagReg(instruction.ZERO) && (result >= 0 || overflow) {\n\t\tthread.RegFile().SetCondition(cc.XGTS)\n\t}\n}\n\nfunc (this *Logic) SetSubSetCc(\n\tinstruction_ *instruction.Instruction,\n\toperand1 int64,\n\toperand2 int64,\n\tresult int64,\n) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetCondition(cc.Z)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NZ)\n\t}\n\n\tif result == 0 && thread.RegFile().ReadFlagReg(instruction.ZERO) {\n\t\tthread.RegFile().SetCondition(cc.XZ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.XNZ)\n\t}\n\n\tif operand1 == operand2 {\n\t\tthread.RegFile().SetCondition(cc.EQ)\n\t} else {\n\t\tthread.RegFile().SetCondition(cc.NEQ)\n\t}\n}\n\nfunc (this *Logic) SetFlags(instruction_ *instruction.Instruction, result int64, carry bool) {\n\tthread := this.scoreboard[instruction_]\n\n\tif result == 0 {\n\t\tthread.RegFile().SetFlag(instruction.ZERO)\n\t} else {\n\t\tthread.RegFile().ClearFlag(instruction.ZERO)\n\t}\n\n\tif carry {\n\t\tthread.RegFile().SetFlag(instruction.CARRY)\n\t} else {\n\t\tthread.RegFile().ClearFlag(instruction.CARRY)\n\t}\n}\n\nfunc (this *Logic) Pow2(exponent int) int64 {\n\tif exponent < 0 {\n\t\terr := errors.New(\"exponent < 0\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n\nfunc (this *Logic) PrintRegFile(thread *Thread) string {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tlines := \"\"\n\tfor i := 0; i < config_loader.NumGpRegisters(); i++ {\n\t\tgp_reg_descriptor := new(reg_descriptor.GpRegDescriptor)\n\t\tgp_reg_descriptor.Init(i)\n\n\t\tlines += fmt.Sprintf(\n\t\t\t\"r%d: %d\\n\",\n\t\t\ti,\n\t\t\tthread.RegFile().ReadGpReg(gp_reg_descriptor, abi.SIGNED),\n\t\t)\n\t}\n\treturn lines\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/operand_collector.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/simulator/dpu/sram\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype OperandCollector struct {\n\twram *sram.Wram\n}\n\nfunc (this *OperandCollector) Init() {\n\tthis.wram = nil\n}\n\nfunc (this *OperandCollector) Fini() {\n}\n\nfunc (this *OperandCollector) ConnectWram(wram *sram.Wram) {\n\tif this.wram != nil {\n\t\terr := errors.New(\"wram is already set\")\n\t\tpanic(err)\n\t}\n\n\tthis.wram = wram\n}\n\nfunc (this *OperandCollector) Lbs(address int64) int64 {\n\tbyte_stream := this.wram.Read(address, 1)\n\n\tvalue := int64(byte_stream.Get(0))\n\n\tword_ := new(abi.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\treturn word_.Value(abi.SIGNED)\n}\n\nfunc (this *OperandCollector) Lbu(address int64) int64 {\n\tbyte_stream := this.wram.Read(address, 1)\n\n\tvalue := int64(byte_stream.Get(0))\n\n\tword_ := new(abi.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\treturn word_.Value(abi.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Lhs(address int64) int64 {\n\tword_ := new(abi.Word)\n\tword_.Init(16)\n\tword_.SetBitSlice(0, 8, this.Lbs(address))\n\tword_.SetBitSlice(8, 16, this.Lbs(address+1))\n\treturn word_.Value(abi.SIGNED)\n}\n\nfunc (this *OperandCollector) Lhu(address int64) int64 {\n\tword_ := new(abi.Word)\n\tword_.Init(16)\n\tword_.SetBitSlice(0, 8, this.Lbu(address))\n\tword_.SetBitSlice(8, 16, this.Lbu(address+1))\n\treturn word_.Value(abi.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Lw(address int64) int64 {\n\tword_ := new(abi.Word)\n\tword_.Init(32)\n\tword_.SetBitSlice(0, 8, this.Lbu(address))\n\tword_.SetBitSlice(8, 16, this.Lbu(address+1))\n\tword_.SetBitSlice(16, 24, this.Lbu(address+2))\n\tword_.SetBitSlice(24, 32, this.Lbu(address+3))\n\treturn word_.Value(abi.UNSIGNED)\n}\n\nfunc (this *OperandCollector) Ld(address int64) (int64, int64) {\n\treturn this.Lw(address + 4), this.Lw(address)\n}\n\nfunc (this *OperandCollector) Sb(address int64, value int64) {\n\tword_ := new(abi.Word)\n\tword_.Init(8)\n\tword_.SetValue(value)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\tbyte_stream.Append(uint8(word_.Value(abi.UNSIGNED)))\n\n\tthis.wram.Write(address, 1, byte_stream)\n}\n\nfunc (this *OperandCollector) Sh(address int64, value int64) {\n\tword_ := new(abi.Word)\n\tword_.Init(16)\n\tword_.SetValue(value)\n\n\tthis.Sb(address, word_.BitSlice(abi.UNSIGNED, 0, 8))\n\tthis.Sb(address+1, word_.BitSlice(abi.UNSIGNED, 8, 16))\n}\n\nfunc (this *OperandCollector) Sw(address int64, value int64) {\n\tword_ := new(abi.Word)\n\tword_.Init(32)\n\tword_.SetValue(value)\n\n\tthis.Sb(address, word_.BitSlice(abi.UNSIGNED, 0, 8))\n\tthis.Sb(address+1, word_.BitSlice(abi.UNSIGNED, 8, 16))\n\tthis.Sb(address+2, word_.BitSlice(abi.UNSIGNED, 16, 24))\n\tthis.Sb(address+3, word_.BitSlice(abi.UNSIGNED, 24, 32))\n}\n\nfunc (this *OperandCollector) Sd(address int64, even int64, odd int64) {\n\tthis.Sw(address+4, even)\n\tthis.Sw(address, odd)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/pipeline.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Pipeline struct {\n\tnum_pipeline_stages int\n\n\tinput_q *InstructionQ\n\twait_q  *InstructionQ\n\tready_q *InstructionQ\n}\n\nfunc (this *Pipeline) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.num_pipeline_stages = int(command_line_parser.IntParameter(\"num_pipeline_stages\"))\n\n\tthis.input_q = new(InstructionQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.wait_q = new(InstructionQ)\n\tthis.wait_q.Init(this.num_pipeline_stages-1, 0)\n\tfor this.wait_q.CanPush(1) {\n\t\tthis.wait_q.Push(nil)\n\t}\n\n\tthis.ready_q = new(InstructionQ)\n\tthis.ready_q.Init(1, 0)\n\tfor this.ready_q.CanPush(1) {\n\t\tthis.ready_q.Push(nil)\n\t}\n}\n\nfunc (this *Pipeline) Fini() {\n\tthis.input_q.Fini()\n\n\tfor this.wait_q.CanPop(1) {\n\t\tif this.wait_q.Pop() != nil {\n\t\t\terr := errors.New(\"wait queue is not empty\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\tthis.wait_q.Fini()\n\n\tfor this.ready_q.CanPop(1) {\n\t\tif this.ready_q.Pop() != nil {\n\t\t\terr := errors.New(\"ready queue is not empty\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Pipeline) IsEmpty() bool {\n\treturn this.IsInputQEmpty() && this.IsWaitQEmpty() && this.IsReadyQEmpty()\n}\n\nfunc (this *Pipeline) IsInputQEmpty() bool {\n\treturn this.input_q.IsEmpty()\n}\n\nfunc (this *Pipeline) IsWaitQEmpty() bool {\n\tif this.wait_q.IsEmpty() {\n\t\treturn true\n\t} else {\n\t\tfor i := 0; this.wait_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.wait_q.Front(i)\n\n\t\t\tif instruction_ != nil {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\n\t\treturn true\n\t}\n}\n\nfunc (this *Pipeline) IsReadyQEmpty() bool {\n\tif this.ready_q.IsEmpty() {\n\t\treturn true\n\t} else {\n\t\tfor i := 0; this.ready_q.CanPop(i + 1); i++ {\n\t\t\tinstruction_, _ := this.ready_q.Front(i)\n\n\t\t\tif instruction_ != nil {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *Pipeline) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Pipeline) Push(instruction_ *instruction.Instruction) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"pipeline cannot be pushed\")\n\t\tpanic(err)\n\t} else if instruction_ == nil {\n\t\terr := errors.New(\"instruction == nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(instruction_)\n}\n\nfunc (this *Pipeline) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Pipeline) Pop() *instruction.Instruction {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"pipeline cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Pipeline) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceWaitQ()\n\n\tthis.input_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Pipeline) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.wait_q.CanPush(1) {\n\t\tinstruction_ := this.input_q.Pop()\n\t\tthis.wait_q.Push(instruction_)\n\t} else if this.wait_q.CanPush(1) {\n\t\tthis.wait_q.Push(nil)\n\t}\n}\n\nfunc (this *Pipeline) ServiceWaitQ() {\n\tif this.wait_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tinstruction_ := this.wait_q.Pop()\n\t\tthis.ready_q.Push(instruction_)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/reg_set.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n)\n\ntype RegSet struct {\n\tthread_id int\n\n\tprev_write_gp_reg_set map[*reg_descriptor.GpRegDescriptor]bool\n\tcur_read_gp_reg_set   map[*reg_descriptor.GpRegDescriptor]bool\n}\n\nfunc (this *RegSet) Init(thread_id int) {\n\tif thread_id < 0 {\n\t\terr := errors.New(\"thread ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = thread_id\n\n\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n}\n\nfunc (this *RegSet) ThreadId() int {\n\treturn this.thread_id\n}\n\nfunc (this *RegSet) CollectReadGpRegs(instruction_ *instruction.Instruction) {\n\tsuffix := instruction_.Suffix()\n\tif suffix == instruction.RICI ||\n\t\tsuffix == instruction.RRI ||\n\t\tsuffix == instruction.RRIC ||\n\t\tsuffix == instruction.RRICI ||\n\t\tsuffix == instruction.RRIF ||\n\t\tsuffix == instruction.ZRI ||\n\t\tsuffix == instruction.ZRIC ||\n\t\tsuffix == instruction.ZRICI ||\n\t\tsuffix == instruction.ZRIF ||\n\t\tsuffix == instruction.S_RRI ||\n\t\tsuffix == instruction.U_RRI ||\n\t\tsuffix == instruction.S_RRIC ||\n\t\tsuffix == instruction.U_RRIC ||\n\t\tsuffix == instruction.S_RRICI ||\n\t\tsuffix == instruction.U_RRICI ||\n\t\tsuffix == instruction.S_RRIF ||\n\t\tsuffix == instruction.U_RRIF ||\n\t\tsuffix == instruction.RR ||\n\t\tsuffix == instruction.RRC ||\n\t\tsuffix == instruction.RRCI ||\n\t\tsuffix == instruction.ZR ||\n\t\tsuffix == instruction.ZRC ||\n\t\tsuffix == instruction.ZRCI ||\n\t\tsuffix == instruction.S_RR ||\n\t\tsuffix == instruction.U_RR ||\n\t\tsuffix == instruction.S_RRC ||\n\t\tsuffix == instruction.U_RRC ||\n\t\tsuffix == instruction.S_RRCI ||\n\t\tsuffix == instruction.U_RRCI ||\n\t\tsuffix == instruction.RIR ||\n\t\tsuffix == instruction.RIRC ||\n\t\tsuffix == instruction.RIRCI ||\n\t\tsuffix == instruction.ZIR ||\n\t\tsuffix == instruction.ZIRC ||\n\t\tsuffix == instruction.ZIRCI ||\n\t\tsuffix == instruction.S_RIRC ||\n\t\tsuffix == instruction.U_RIRC ||\n\t\tsuffix == instruction.S_RIRCI ||\n\t\tsuffix == instruction.U_RIRCI ||\n\t\tsuffix == instruction.ERRI ||\n\t\tsuffix == instruction.S_ERRI || suffix == instruction.U_ERRI ||\n\t\tsuffix == instruction.EDRI ||\n\t\tsuffix == instruction.ERII {\n\t\tif instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\t\t}\n\t} else if suffix == instruction.RRR ||\n\t\tsuffix == instruction.RRRC ||\n\t\tsuffix == instruction.RRRCI ||\n\t\tsuffix == instruction.ZRR ||\n\t\tsuffix == instruction.ZRRC ||\n\t\tsuffix == instruction.ZRRCI ||\n\t\tsuffix == instruction.S_RRR ||\n\t\tsuffix == instruction.U_RRR ||\n\t\tsuffix == instruction.S_RRRC ||\n\t\tsuffix == instruction.U_RRRC ||\n\t\tsuffix == instruction.S_RRRCI ||\n\t\tsuffix == instruction.U_RRRCI ||\n\t\tsuffix == instruction.RRRI ||\n\t\tsuffix == instruction.RRRICI ||\n\t\tsuffix == instruction.ZRRI ||\n\t\tsuffix == instruction.ZRRICI ||\n\t\tsuffix == instruction.S_RRRI ||\n\t\tsuffix == instruction.U_RRRI ||\n\t\tsuffix == instruction.S_RRRICI ||\n\t\tsuffix == instruction.U_RRRICI ||\n\t\tsuffix == instruction.ERIR ||\n\t\tsuffix == instruction.DMA_RRI {\n\t\tif instruction_.Ra().IsGpRegDescriptor() && instruction_.Rb().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Rb().GpRegDescriptor()] = true\n\t\t} else if instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t} else if instruction_.Rb().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Rb().GpRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\t\t}\n\t} else if suffix == instruction.DRDICI || suffix == instruction.ERID {\n\t\tif instruction_.Ra().IsGpRegDescriptor() {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Ra().GpRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t\t} else {\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t\t}\n\n\t} else if suffix == instruction.R ||\n\t\tsuffix == instruction.RCI ||\n\t\tsuffix == instruction.Z ||\n\t\tsuffix == instruction.ZCI ||\n\t\tsuffix == instruction.S_R ||\n\t\tsuffix == instruction.U_R ||\n\t\tsuffix == instruction.S_RCI ||\n\t\tsuffix == instruction.U_RCI ||\n\t\tsuffix == instruction.CI ||\n\t\tsuffix == instruction.I {\n\t\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\t} else if suffix == instruction.DDCI {\n\t\tthis.cur_read_gp_reg_set[instruction_.Db().EvenRegDescriptor()] = true\n\t\tthis.cur_read_gp_reg_set[instruction_.Db().OddRegDescriptor()] = true\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RegSet) CollectWriteGpRegs(instruction_ *instruction.Instruction) {\n\tsuffix := instruction_.Suffix()\n\tif suffix == instruction.RICI ||\n\t\tsuffix == instruction.ZRI ||\n\t\tsuffix == instruction.ZRIC ||\n\t\tsuffix == instruction.ZRICI ||\n\t\tsuffix == instruction.ZRIF ||\n\t\tsuffix == instruction.ZRR ||\n\t\tsuffix == instruction.ZRRC ||\n\t\tsuffix == instruction.ZRRCI ||\n\t\tsuffix == instruction.ZR ||\n\t\tsuffix == instruction.ZRC ||\n\t\tsuffix == instruction.ZRCI ||\n\t\tsuffix == instruction.ZRRI ||\n\t\tsuffix == instruction.ZRRICI ||\n\t\tsuffix == instruction.ZIR ||\n\t\tsuffix == instruction.ZIRC ||\n\t\tsuffix == instruction.ZIRCI ||\n\t\tsuffix == instruction.Z ||\n\t\tsuffix == instruction.ZCI ||\n\t\tsuffix == instruction.CI ||\n\t\tsuffix == instruction.I ||\n\t\tsuffix == instruction.ERII ||\n\t\tsuffix == instruction.ERIR ||\n\t\tsuffix == instruction.ERID ||\n\t\tsuffix == instruction.DMA_RRI {\n\t\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\t} else if suffix == instruction.RRI ||\n\t\tsuffix == instruction.RRIC ||\n\t\tsuffix == instruction.RRICI ||\n\t\tsuffix == instruction.RRIF ||\n\t\tsuffix == instruction.RRR ||\n\t\tsuffix == instruction.RRRC ||\n\t\tsuffix == instruction.RRRCI ||\n\t\tsuffix == instruction.RR ||\n\t\tsuffix == instruction.RRC ||\n\t\tsuffix == instruction.RRCI ||\n\t\tsuffix == instruction.RRRI ||\n\t\tsuffix == instruction.RRRICI ||\n\t\tsuffix == instruction.RIR ||\n\t\tsuffix == instruction.RIRC ||\n\t\tsuffix == instruction.RIRCI ||\n\t\tsuffix == instruction.R ||\n\t\tsuffix == instruction.RCI ||\n\t\tsuffix == instruction.ERRI {\n\t\tthis.prev_write_gp_reg_set[instruction_.Rc()] = true\n\t} else if suffix == instruction.S_RRI ||\n\t\tsuffix == instruction.U_RRI ||\n\t\tsuffix == instruction.S_RRIC ||\n\t\tsuffix == instruction.U_RRIC ||\n\t\tsuffix == instruction.S_RRICI ||\n\t\tsuffix == instruction.U_RRICI ||\n\t\tsuffix == instruction.S_RRIF ||\n\t\tsuffix == instruction.U_RRIF ||\n\t\tsuffix == instruction.S_RRR ||\n\t\tsuffix == instruction.U_RRR ||\n\t\tsuffix == instruction.S_RRRC ||\n\t\tsuffix == instruction.U_RRRC ||\n\t\tsuffix == instruction.S_RRRCI ||\n\t\tsuffix == instruction.U_RRRCI ||\n\t\tsuffix == instruction.S_RR ||\n\t\tsuffix == instruction.U_RR ||\n\t\tsuffix == instruction.S_RRC ||\n\t\tsuffix == instruction.U_RRC ||\n\t\tsuffix == instruction.S_RRCI ||\n\t\tsuffix == instruction.U_RRCI ||\n\t\tsuffix == instruction.DRDICI ||\n\t\tsuffix == instruction.S_RRRI ||\n\t\tsuffix == instruction.U_RRRI ||\n\t\tsuffix == instruction.S_RRRICI ||\n\t\tsuffix == instruction.U_RRRICI ||\n\t\tsuffix == instruction.S_RIRC ||\n\t\tsuffix == instruction.U_RIRC ||\n\t\tsuffix == instruction.S_RIRCI ||\n\t\tsuffix == instruction.U_RIRCI ||\n\t\tsuffix == instruction.S_R ||\n\t\tsuffix == instruction.U_R ||\n\t\tsuffix == instruction.DDCI ||\n\t\tsuffix == instruction.S_ERRI ||\n\t\tsuffix == instruction.U_ERRI ||\n\t\tsuffix == instruction.EDRI {\n\t\tthis.prev_write_gp_reg_set[instruction_.Dc().EvenRegDescriptor()] = true\n\t\tthis.prev_write_gp_reg_set[instruction_.Dc().OddRegDescriptor()] = true\n\t} else {\n\t\terr := errors.New(\"suffix is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RegSet) Clear() {\n\tthis.prev_write_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n\tthis.cur_read_gp_reg_set = make(map[*reg_descriptor.GpRegDescriptor]bool)\n}\n\nfunc (this *RegSet) RegIndices() map[int]bool {\n\treg_indices := make(map[int]bool)\n\n\tfor gp_reg_descriptor, _ := range this.prev_write_gp_reg_set {\n\t\treg_indices[gp_reg_descriptor.Index()] = true\n\t}\n\n\tfor gp_reg_descriptor, _ := range this.cur_read_gp_reg_set {\n\t\treg_indices[gp_reg_descriptor.Index()] = true\n\t}\n\n\treturn reg_indices\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/thread.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu/reg\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype ThreadState int\n\nconst (\n\tEMBRYO ThreadState = iota\n\tRUNNABLE\n\tSLEEP\n\tBLOCK\n\tZOMBIE\n)\n\ntype Thread struct {\n\tthread_id    int\n\tthread_state ThreadState\n\treg_file     *reg.RegFile\n\tissue_cycle  int64\n}\n\nfunc (this *Thread) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tif thread_id < 0 {\n\t\terr := errors.New(\"thread ID < 0\")\n\t\tpanic(err)\n\t} else if thread_id >= config_loader.MaxNumTasklets() {\n\t\terr := errors.New(\"thread ID >= max number of tasklets\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = thread_id\n\tthis.thread_state = EMBRYO\n\n\tthis.reg_file = new(reg.RegFile)\n\tthis.reg_file.Init(thread_id)\n\n\tthis.issue_cycle = 0\n}\n\nfunc (this *Thread) Fini() {\n\tif this.thread_state != EMBRYO {\n\t\terr := errors.New(\"thread state is not zombie\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Thread) ThreadId() int {\n\treturn this.thread_id\n}\n\nfunc (this *Thread) ThreadState() ThreadState {\n\treturn this.thread_state\n}\n\nfunc (this *Thread) SetThreadState(thread_state ThreadState) {\n\tthis.thread_state = thread_state\n}\n\nfunc (this *Thread) RegFile() *reg.RegFile {\n\treturn this.reg_file\n}\n\nfunc (this *Thread) IssueCycle() int64 {\n\treturn this.issue_cycle\n}\n\nfunc (this *Thread) IncrementIssueCycle() {\n\tthis.issue_cycle++\n}\n\nfunc (this *Thread) ResetIssueCycle() {\n\tthis.issue_cycle = 0\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/thread_q.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n)\n\ntype ThreadQ struct {\n\tsize  int\n\ttimer int64\n\n\tthreads []*Thread\n\tcycles  []int64\n}\n\nfunc (this *ThreadQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.threads = make([]*Thread, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *ThreadQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"thread queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *ThreadQ) Length() int {\n\treturn len(this.threads)\n}\n\nfunc (this *ThreadQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *ThreadQ) IsEmpty() bool {\n\treturn len(this.threads) == 0\n}\n\nfunc (this *ThreadQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.threads) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *ThreadQ) Push(thread *Thread) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"thread queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.threads = append(this.threads, thread)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *ThreadQ) PushWithTimer(thread *Thread, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"thread queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.threads = append(this.threads, thread)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *ThreadQ) CanPop(num_items int) bool {\n\tif len(this.threads) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *ThreadQ) Pop() *Thread {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"thread queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tthread := this.threads[0]\n\n\tthis.threads = this.threads[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn thread\n}\n\nfunc (this *ThreadQ) Front(pos int) (*Thread, int64) {\n\treturn this.threads[pos], this.cycles[pos]\n}\n\nfunc (this *ThreadQ) Remove(pos int) {\n\tthis.threads = append(this.threads[:pos], this.threads[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *ThreadQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/logic/thread_scheduler.go",
    "content": "package logic\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype ThreadScheduler struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tnum_revolver_scheduling_cycles int64\n\n\tthreads  []*Thread\n\tthread_q *ThreadQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *ThreadScheduler) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tthreads []*Thread,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.num_revolver_scheduling_cycles = command_line_parser.IntParameter(\n\t\t\"num_revolver_scheduling_cycles\",\n\t)\n\n\tthis.threads = threads\n\n\tthis.thread_q = new(ThreadQ)\n\tthis.thread_q.Init(len(this.threads), 0)\n\tfor _, thread := range threads {\n\t\tthis.thread_q.Push(thread)\n\t}\n\n\tname := fmt.Sprintf(\"ThreadScheduler[%d_%d_%d]\", channel_id, rank_id, dpu_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *ThreadScheduler) Fini() {\n\tfor this.thread_q.CanPop(1) {\n\t\tthis.thread_q.Pop()\n\t}\n\n\tthis.thread_q.Fini()\n}\n\nfunc (this *ThreadScheduler) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *ThreadScheduler) NumIssuableThreads() int {\n\tnum_issuable_threads := 0\n\n\tfor _, thread := range this.threads {\n\t\tif thread.ThreadState() == RUNNABLE {\n\t\t\tnum_issuable_threads++\n\t\t}\n\t}\n\n\treturn num_issuable_threads\n}\n\nfunc (this *ThreadScheduler) Schedule() *Thread {\n\tvar is_blocked bool\n\tis_blocked = false\n\tfor i := 0; i < this.thread_q.Size(); i++ {\n\t\tthread := this.thread_q.Pop()\n\t\tthis.thread_q.Push(thread)\n\n\t\tif thread.IssueCycle() >= this.num_revolver_scheduling_cycles {\n\t\t\tif thread.ThreadState() == RUNNABLE {\n\t\t\t\tthread.ResetIssueCycle()\n\n\t\t\t\tthis.stat_factory.Increment(\"breakdown_run\", 1)\n\n\t\t\t\treturn thread\n\t\t\t} else if thread.ThreadState() == BLOCK {\n\t\t\t\tis_blocked = true\n\t\t\t}\n\t\t}\n\t}\n\n\tif is_blocked {\n\t\tthis.stat_factory.Increment(\"breakdown_dma\", 1)\n\t} else {\n\t\tthis.stat_factory.Increment(\"breakdown_etc\", 1)\n\t}\n\n\treturn nil\n}\n\nfunc (this *ThreadScheduler) Boot(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == EMBRYO {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == ZOMBIE {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not bootable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Unboot() bool {\n\tfor _, thread := range this.threads {\n\t\tthread_state := thread.ThreadState()\n\n\t\tif thread_state == ZOMBIE {\n\t\t\tthread.SetThreadState(EMBRYO)\n\t\t} else {\n\t\t\terr := errors.New(\"thread is not unbootable\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\treturn true\n}\n\nfunc (this *ThreadScheduler) Sleep(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == RUNNABLE {\n\t\tthread.SetThreadState(SLEEP)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not sleepable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Block(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == RUNNABLE {\n\t\tthread.SetThreadState(BLOCK)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not blockable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Awake(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == EMBRYO {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == SLEEP {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else if thread_state == BLOCK {\n\t\tthread.SetThreadState(RUNNABLE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not awakable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Shutdown(thread_id int) bool {\n\tthread := this.threads[thread_id]\n\n\tif thread.ThreadId() != thread_id {\n\t\terr := errors.New(\"thread's thread ID != thread ID\")\n\t\tpanic(err)\n\t}\n\n\tthread_state := thread.ThreadState()\n\tif thread_state == SLEEP {\n\t\tthread.SetThreadState(ZOMBIE)\n\t\treturn true\n\t} else {\n\t\terr := errors.New(\"thread is not shotdownable\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ThreadScheduler) Cycle() {\n\tthis.thread_q.Cycle()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/condition_reg.go",
    "content": "package reg\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/cc\"\n)\n\ntype ConditionReg struct {\n\tconditions map[cc.Condition]bool\n}\n\nfunc (this *ConditionReg) Init() {\n\tthis.conditions = make(map[cc.Condition]bool)\n\n\tthis.ClearConditions()\n}\n\nfunc (this *ConditionReg) Fini() {\n}\n\nfunc (this *ConditionReg) Condition(condition cc.Condition) bool {\n\tif condition == cc.TRUE {\n\t\treturn true\n\t} else if condition == cc.FALSE {\n\t\treturn false\n\t} else {\n\t\treturn this.conditions[condition]\n\t}\n}\n\nfunc (this *ConditionReg) SetCondition(condition cc.Condition) {\n\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\terr := errors.New(\"condition is true or false\")\n\t\tpanic(err)\n\t}\n\n\tthis.conditions[condition] = true\n}\n\nfunc (this *ConditionReg) ClearCondition(condition cc.Condition) {\n\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\terr := errors.New(\"condition is true or false\")\n\t\tpanic(err)\n\t}\n\n\tthis.conditions[condition] = false\n}\n\nfunc (this *ConditionReg) ClearConditions() {\n\tfor i := 0; i <= int(cc.LARGE); i++ {\n\t\tcondition := cc.Condition(i)\n\n\t\tif condition == cc.TRUE || condition == cc.FALSE {\n\t\t\tcontinue\n\t\t} else {\n\t\t\tthis.conditions[condition] = false\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/exception_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n)\n\ntype ExceptionReg struct {\n\texceptions map[instruction.Exception]bool\n}\n\nfunc (this *ExceptionReg) Init() {\n\tthis.exceptions = make(map[instruction.Exception]bool)\n\n\tthis.ClearExceptions()\n}\n\nfunc (this *ExceptionReg) Fini() {\n}\n\nfunc (this *ExceptionReg) Exception(exception instruction.Exception) bool {\n\treturn this.exceptions[exception]\n}\n\nfunc (this *ExceptionReg) SetException(exception instruction.Exception) {\n\tthis.exceptions[exception] = true\n}\n\nfunc (this *ExceptionReg) ClearException(exception instruction.Exception) {\n\tthis.exceptions[exception] = false\n}\n\nfunc (this *ExceptionReg) ClearExceptions() {\n\tfor i := 0; i <= int(instruction.NOT_PROFILING); i++ {\n\t\texception := instruction.Exception(i)\n\n\t\tthis.exceptions[exception] = false\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/flag_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n)\n\ntype FlagReg struct {\n\tflags map[instruction.Flag]bool\n}\n\nfunc (this *FlagReg) Init() {\n\tthis.flags = make(map[instruction.Flag]bool)\n\n\tthis.ClearFlags()\n}\n\nfunc (this *FlagReg) Fini() {\n}\n\nfunc (this *FlagReg) Flag(flag instruction.Flag) bool {\n\treturn this.flags[flag]\n}\n\nfunc (this *FlagReg) SetFlag(flag instruction.Flag) {\n\tthis.flags[flag] = true\n}\n\nfunc (this *FlagReg) ClearFlag(flag instruction.Flag) {\n\tthis.flags[flag] = false\n}\n\nfunc (this *FlagReg) ClearFlags() {\n\tfor i := 0; i <= int(instruction.CARRY); i++ {\n\t\tflag := instruction.Flag(i)\n\n\t\tthis.flags[flag] = false\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/gp_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype GpReg struct {\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor\n\tword              *abi.Word\n}\n\nfunc (this *GpReg) Init(index int) {\n\tthis.gp_reg_descriptor = new(reg_descriptor.GpRegDescriptor)\n\tthis.gp_reg_descriptor.Init(index)\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.word = new(abi.Word)\n\tthis.word.Init(config_loader.MramDataWidth())\n}\n\nfunc (this *GpReg) Fini() {\n}\n\nfunc (this *GpReg) Index() int {\n\treturn this.gp_reg_descriptor.Index()\n}\n\nfunc (this *GpReg) Read(representation abi.Representation) int64 {\n\treturn this.word.Value(representation)\n}\n\nfunc (this *GpReg) Write(value int64) {\n\tthis.word.SetValue(value)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/pc_reg.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype PcReg struct {\n\tword *abi.Word\n}\n\nfunc (this *PcReg) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.word = new(abi.Word)\n\tthis.word.Init(config_loader.AddressWidth())\n}\n\nfunc (this *PcReg) Fini() {\n}\n\nfunc (this *PcReg) Read() int64 {\n\treturn this.word.Value(abi.UNSIGNED)\n}\n\nfunc (this *PcReg) Write(value int64) {\n\tthis.word.SetValue(value)\n}\n\nfunc (this *PcReg) Increment() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tthis.Write(this.Read() + iram_data_size)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/reg_file.go",
    "content": "package reg\n\nimport (\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/cc\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype RegFile struct {\n\tgp_regs       []*GpReg\n\tsp_reg        *SpReg\n\tpc_reg        *PcReg\n\tcondition_reg *ConditionReg\n\tflag_reg      *FlagReg\n\texception_reg *ExceptionReg\n}\n\nfunc (this *RegFile) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.gp_regs = make([]*GpReg, 0)\n\tfor i := 0; i < config_loader.NumGpRegisters(); i++ {\n\t\tgp_reg := new(GpReg)\n\t\tgp_reg.Init(i)\n\n\t\tthis.gp_regs = append(this.gp_regs, gp_reg)\n\t}\n\n\tthis.sp_reg = new(SpReg)\n\tthis.sp_reg.Init(thread_id)\n\n\tthis.pc_reg = new(PcReg)\n\tthis.pc_reg.Init()\n\n\tthis.condition_reg = new(ConditionReg)\n\tthis.condition_reg.Init()\n\n\tthis.flag_reg = new(FlagReg)\n\tthis.flag_reg.Init()\n\n\tthis.exception_reg = new(ExceptionReg)\n\tthis.exception_reg.Init()\n}\n\nfunc (this *RegFile) Fini() {\n\tfor _, gp_reg := range this.gp_regs {\n\t\tgp_reg.Fini()\n\t}\n\n\tthis.sp_reg.Fini()\n\tthis.pc_reg.Fini()\n\tthis.condition_reg.Fini()\n\tthis.flag_reg.Fini()\n\tthis.exception_reg.Fini()\n}\n\nfunc (this *RegFile) ReadGpReg(\n\tgp_reg_descriptor *reg_descriptor.GpRegDescriptor,\n\trepresentation abi.Representation,\n) int64 {\n\treturn this.gp_regs[gp_reg_descriptor.Index()].Read(representation)\n}\n\nfunc (this *RegFile) ReadSpReg(\n\tsp_reg_descriptor *reg_descriptor.SpRegDescriptor,\n\trepresentation abi.Representation,\n) int64 {\n\treturn this.sp_reg.Read(sp_reg_descriptor, representation)\n}\n\nfunc (this *RegFile) ReadPairReg(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n\trepresentation abi.Representation,\n) (int64, int64) {\n\teven := this.ReadGpReg(pair_reg_descriptor.EvenRegDescriptor(), representation)\n\todd := this.ReadGpReg(pair_reg_descriptor.OddRegDescriptor(), abi.UNSIGNED)\n\n\treturn even, odd\n}\n\nfunc (this *RegFile) ReadSrcReg(\n\tsrc_reg_descriptor *reg_descriptor.SrcRegDescriptor,\n\trepresentation abi.Representation,\n) int64 {\n\tif src_reg_descriptor.IsGpRegDescriptor() {\n\t\treturn this.ReadGpReg(src_reg_descriptor.GpRegDescriptor(), representation)\n\t} else {\n\t\treturn this.ReadSpReg(src_reg_descriptor.SpRegDescriptor(), representation)\n\t}\n}\n\nfunc (this *RegFile) ReadPcReg() int64 {\n\treturn this.pc_reg.Read()\n}\n\nfunc (this *RegFile) ReadConditionReg(condition cc.Condition) bool {\n\treturn this.condition_reg.Condition(condition)\n}\n\nfunc (this *RegFile) ReadFlagReg(flag instruction.Flag) bool {\n\treturn this.flag_reg.Flag(flag)\n}\n\nfunc (this *RegFile) ReadExceptionReg(exception instruction.Exception) bool {\n\treturn this.exception_reg.Exception(exception)\n}\n\nfunc (this *RegFile) WriteGpReg(gp_reg_descriptor *reg_descriptor.GpRegDescriptor, value int64) {\n\tthis.gp_regs[gp_reg_descriptor.Index()].Write(value)\n}\n\nfunc (this *RegFile) WritePairReg(\n\tpair_reg_descriptor *reg_descriptor.PairRegDescriptor,\n\teven int64,\n\todd int64,\n) {\n\tthis.WriteGpReg(pair_reg_descriptor.EvenRegDescriptor(), even)\n\tthis.WriteGpReg(pair_reg_descriptor.OddRegDescriptor(), odd)\n}\n\nfunc (this *RegFile) WritePcReg(value int64) {\n\tthis.pc_reg.Write(value)\n}\n\nfunc (this *RegFile) IncrementPcReg() {\n\tthis.pc_reg.Increment()\n}\n\nfunc (this *RegFile) SetCondition(condition cc.Condition) {\n\tthis.condition_reg.SetCondition(condition)\n}\n\nfunc (this *RegFile) ClearCondition(condition cc.Condition) {\n\tthis.condition_reg.ClearCondition(condition)\n}\n\nfunc (this *RegFile) ClearConditions() {\n\tthis.condition_reg.ClearConditions()\n}\n\nfunc (this *RegFile) SetFlag(flag instruction.Flag) {\n\tthis.flag_reg.SetFlag(flag)\n}\n\nfunc (this *RegFile) ClearFlag(flag instruction.Flag) {\n\tthis.flag_reg.ClearFlag(flag)\n}\n\nfunc (this *RegFile) ClearFlags() {\n\tthis.flag_reg.ClearFlags()\n}\n\nfunc (this *RegFile) SetException(exception instruction.Exception) {\n\tthis.exception_reg.SetException(exception)\n}\n\nfunc (this *RegFile) ClearException(exception instruction.Exception) {\n\tthis.exception_reg.ClearException(exception)\n}\n\nfunc (this *RegFile) ClearExceptions() {\n\tthis.exception_reg.ClearExceptions()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/reg/sp_reg.go",
    "content": "package reg\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/abi\"\n\t\"uPIMulator/src/device/linker/kernel/instruction/reg_descriptor\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype SpReg struct {\n\tzero *abi.Word\n\tone  *abi.Word\n\tlneg *abi.Word\n\tmneg *abi.Word\n\tid   *abi.Word\n\tid2  *abi.Word\n\tid4  *abi.Word\n\tid8  *abi.Word\n}\n\nfunc (this *SpReg) Init(thread_id int) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.zero = new(abi.Word)\n\tthis.zero.Init(config_loader.MramDataWidth())\n\tthis.zero.SetValue(0)\n\n\tthis.one = new(abi.Word)\n\tthis.one.Init(config_loader.MramDataWidth())\n\tthis.one.SetValue(1)\n\n\tthis.lneg = new(abi.Word)\n\tthis.lneg.Init(config_loader.MramDataWidth())\n\tthis.lneg.SetValue(-1)\n\n\tthis.mneg = new(abi.Word)\n\tthis.mneg.Init(config_loader.MramDataWidth())\n\tthis.mneg.SetValue(int64(this.mneg.Width()) - 1)\n\n\tthis.id = new(abi.Word)\n\tthis.id.Init(config_loader.MramDataWidth())\n\tthis.id.SetValue(int64(thread_id))\n\n\tthis.id2 = new(abi.Word)\n\tthis.id2.Init(config_loader.MramDataWidth())\n\tthis.id2.SetValue(int64(2 * thread_id))\n\n\tthis.id4 = new(abi.Word)\n\tthis.id4.Init(config_loader.MramDataWidth())\n\tthis.id4.SetValue(int64(4 * thread_id))\n\n\tthis.id8 = new(abi.Word)\n\tthis.id8.Init(config_loader.MramDataWidth())\n\tthis.id8.SetValue(int64(8 * thread_id))\n}\n\nfunc (this *SpReg) Fini() {\n}\n\nfunc (this *SpReg) Read(\n\tsp_reg_descriptor *reg_descriptor.SpRegDescriptor,\n\trepresentation abi.Representation,\n) int64 {\n\tif *sp_reg_descriptor == reg_descriptor.ZERO {\n\t\treturn this.zero.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ONE {\n\t\treturn this.one.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.LNEG {\n\t\treturn this.lneg.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.MNEG {\n\t\treturn this.mneg.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID {\n\t\treturn this.id.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID2 {\n\t\treturn this.id2.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID4 {\n\t\treturn this.id4.Value(representation)\n\t} else if *sp_reg_descriptor == reg_descriptor.ID8 {\n\t\treturn this.id8.Value(representation)\n\t} else {\n\t\terr := errors.New(\"sp reg descriptor is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/sram/atomic.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Atomic struct {\n\taddress int64\n\tsize    int64\n\n\tlocks []*Lock\n}\n\nfunc (this *Atomic) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.AtomicOffset()\n\tthis.size = config_loader.AtomicSize()\n\n\tthis.locks = make([]*Lock, 0)\n\tfor i := int64(0); i < this.size; i++ {\n\t\tlock := new(Lock)\n\t\tlock.Init()\n\n\t\tthis.locks = append(this.locks, lock)\n\t}\n}\n\nfunc (this *Atomic) Fini() {\n\tfor _, lock := range this.locks {\n\t\tlock.Fini()\n\t}\n}\n\nfunc (this *Atomic) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Atomic) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Atomic) CanAcquire(address int64) bool {\n\treturn this.locks[this.Index(address)].CanAcquire()\n}\n\nfunc (this *Atomic) Acquire(address int64, thread_id int) {\n\tthis.locks[this.Index(address)].Acquire(thread_id)\n}\n\nfunc (this *Atomic) CanRelease(address int64, thread_id int) bool {\n\treturn this.locks[this.Index(address)].CanRelease(thread_id)\n}\n\nfunc (this *Atomic) Release(address int64, thread_id int) {\n\tthis.locks[this.Index(address)].Release(thread_id)\n}\n\nfunc (this *Atomic) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < atomic offset\")\n\t\tpanic(err)\n\t} else if address >= this.address+this.size {\n\t\terr := errors.New(\"address >= atomic offset + atomic size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/sram/iram.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/linker/kernel/instruction\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Iram struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Iram) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.IramOffset()\n\tthis.size = config_loader.IramSize()\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < this.size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Iram) Fini() {\n}\n\nfunc (this *Iram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Iram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Iram) Read(address int64) *instruction.Instruction {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\tfor i := int64(0); i < iram_data_size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\tinstruction_ := new(instruction.Instruction)\n\tinstruction_.Decode(byte_stream)\n\treturn instruction_\n}\n\nfunc (this *Iram) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *Iram) Index(address int64) int {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tiram_data_size := int64(config_loader.IramDataWidth() / 8)\n\n\tif address < this.address {\n\t\terr := errors.New(\"address < IRAM offset\")\n\t\tpanic(err)\n\t} else if address+iram_data_size > this.address+this.size {\n\t\terr := errors.New(\"address >= IRAM offset + IRAM size\")\n\t\tpanic(err)\n\t}\n\n\tif (address-this.address)%iram_data_size != 0 {\n\t\terr := errors.New(\"addresses are not aligned with IRAM data size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/sram/lock.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n)\n\ntype Lock struct {\n\tthread_id *int\n}\n\nfunc (this *Lock) Init() {\n\tthis.thread_id = nil\n}\n\nfunc (this *Lock) Fini() {\n\tif this.thread_id != nil {\n\t\terr := errors.New(\"thread ID != nil\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Lock) CanAcquire() bool {\n\treturn this.thread_id == nil\n}\n\nfunc (this *Lock) Acquire(thread_id int) {\n\tif !this.CanAcquire() {\n\t\terr := errors.New(\"lock cannot be acquired\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = new(int)\n\t*this.thread_id = thread_id\n}\n\nfunc (this *Lock) CanRelease(thread_id int) bool {\n\treturn this.thread_id == nil || *this.thread_id == thread_id\n}\n\nfunc (this *Lock) Release(thread_id int) {\n\tif !this.CanRelease(thread_id) {\n\t\terr := errors.New(\"lock cannot be released\")\n\t\tpanic(err)\n\t}\n\n\tthis.thread_id = nil\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/dpu/sram/wram.go",
    "content": "package sram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Wram struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Wram) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = config_loader.WramOffset()\n\tthis.size = config_loader.WramSize()\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < this.size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Wram) Fini() {\n}\n\nfunc (this *Wram) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Wram) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Wram) Read(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Wram) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *Wram) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < WRAM offset\")\n\t\tpanic(err)\n\t} else if address >= this.address+this.size {\n\t\terr := errors.New(\"address >= WRAM offset + WRAM size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - this.address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/rank/rank.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Rank struct {\n\tchannel_id int\n\trank_id    int\n\n\tdpus []*dpu.Dpu\n\n\tinput_q    *RankCommandQ\n\tready_q    *RankCommandQ\n\tscoreboard map[*dram.DmaCommand]*RankCommand\n}\n\nfunc (this *Rank) Init(channel_id int, rank_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\n\tthis.dpus = make([]*dpu.Dpu, 0)\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tfor i := 0; i < num_dpus_per_rank; i++ {\n\t\tdpu_ := new(dpu.Dpu)\n\t\tdpu_.Init(channel_id, rank_id, i, command_line_parser)\n\n\t\tthis.dpus = append(this.dpus, dpu_)\n\t}\n\n\tthis.input_q = new(RankCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.ready_q = new(RankCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.scoreboard = make(map[*dram.DmaCommand]*RankCommand)\n}\n\nfunc (this *Rank) Fini() {\n\tfor _, dpu_ := range this.dpus {\n\t\tdpu_.Fini()\n\t}\n\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Rank) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Rank) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Rank) NumDpus() int {\n\treturn len(this.dpus)\n}\n\nfunc (this *Rank) Dpus() []*dpu.Dpu {\n\treturn this.dpus\n}\n\nfunc (this *Rank) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Rank) Push(rank_command *RankCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"rank cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(rank_command)\n}\n\nfunc (this *Rank) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Rank) Pop() *RankCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"rank cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Rank) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Rank) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\trank_command, _ := this.input_q.Front(0)\n\n\t\tdpu_id := rank_command.DpuId()\n\t\tif this.dpus[dpu_id].Dma().CanPush() {\n\t\t\tthis.input_q.Pop()\n\n\t\t\tdma_command := rank_command.DmaCommand()\n\n\t\t\tthis.dpus[dpu_id].Dma().Push(dma_command)\n\t\t\tthis.scoreboard[dma_command] = rank_command\n\t\t}\n\t}\n}\n\nfunc (this *Rank) ServiceReadyQ() {\n\tfor _, dpu_ := range this.dpus {\n\t\tif dpu_.Dma().CanPop() && this.ready_q.CanPush(1) {\n\t\t\tdma_command := dpu_.Dma().Pop()\n\t\t\trank_command := this.scoreboard[dma_command]\n\n\t\t\tthis.ready_q.Push(rank_command)\n\t\t\tdelete(this.scoreboard, dma_command)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/rank/rank_command.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n)\n\ntype RankCommand struct {\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tdma_command *dram.DmaCommand\n}\n\nfunc (this *RankCommand) Init(\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tdma_command *dram.DmaCommand,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if dpu_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\n\tthis.dma_command = dma_command\n}\n\nfunc (this *RankCommand) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *RankCommand) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *RankCommand) DmaCommand() *dram.DmaCommand {\n\treturn this.dma_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/device/simulator/rank/rank_command_q.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n)\n\ntype RankCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\trank_commands []*RankCommand\n\tcycles        []int64\n}\n\nfunc (this *RankCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.rank_commands = make([]*RankCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *RankCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"rank command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RankCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *RankCommandQ) Length() int {\n\treturn len(this.rank_commands)\n}\n\nfunc (this *RankCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *RankCommandQ) IsEmpty() bool {\n\treturn len(this.rank_commands) == 0\n}\n\nfunc (this *RankCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.rank_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *RankCommandQ) Push(rank_command *RankCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"rank command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.rank_commands = append(this.rank_commands, rank_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *RankCommandQ) PushWithTimer(rank_command *RankCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"rank command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.rank_commands = append(this.rank_commands, rank_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *RankCommandQ) CanPop(num_items int) bool {\n\tif len(this.rank_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *RankCommandQ) Pop() *RankCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"rank command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\trank_command := this.rank_commands[0]\n\n\tthis.rank_commands = this.rank_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn rank_command\n}\n\nfunc (this *RankCommandQ) Front(pos int) (*RankCommand, int64) {\n\treturn this.rank_commands[pos], this.cycles[pos]\n}\n\nfunc (this *RankCommandQ) Remove(pos int) {\n\tthis.rank_commands = append(this.rank_commands[:pos], this.rank_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *RankCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/encoding/ascii_encoder.go",
    "content": "package encoding\n\ntype AsciiEncoder struct {\n\ttable          map[string]uint8\n\tinverted_table map[uint8]string\n\tunknown        string\n}\n\nfunc (this *AsciiEncoder) Init() {\n\tthis.table = make(map[string]uint8)\n\tthis.inverted_table = make(map[uint8]string)\n\n\tthis.table[\"\\t\"] = 9\n\tthis.table[\" \"] = 32\n\tthis.table[\"!\"] = 33\n\tthis.table[\"\\\"\"] = 34\n\tthis.table[\"#\"] = 35\n\tthis.table[\"$\"] = 36\n\tthis.table[\"%\"] = 37\n\tthis.table[\"&\"] = 38\n\tthis.table[\"'\"] = 39\n\tthis.table[\"(\"] = 40\n\tthis.table[\")\"] = 41\n\tthis.table[\"*\"] = 42\n\tthis.table[\"+\"] = 43\n\tthis.table[\",\"] = 44\n\tthis.table[\"-\"] = 45\n\tthis.table[\".\"] = 46\n\tthis.table[\"/\"] = 47\n\tthis.table[\"0\"] = 48\n\tthis.table[\"1\"] = 49\n\tthis.table[\"2\"] = 50\n\tthis.table[\"3\"] = 51\n\tthis.table[\"4\"] = 52\n\tthis.table[\"5\"] = 53\n\tthis.table[\"6\"] = 54\n\tthis.table[\"7\"] = 55\n\tthis.table[\"8\"] = 56\n\tthis.table[\"9\"] = 57\n\tthis.table[\":\"] = 58\n\tthis.table[\"\"] = 59\n\tthis.table[\"<\"] = 60\n\tthis.table[\"=\"] = 61\n\tthis.table[\">\"] = 62\n\tthis.table[\"?\"] = 63\n\tthis.table[\"@\"] = 64\n\tthis.table[\"A\"] = 65\n\tthis.table[\"B\"] = 66\n\tthis.table[\"C\"] = 67\n\tthis.table[\"D\"] = 68\n\tthis.table[\"E\"] = 69\n\tthis.table[\"F\"] = 70\n\tthis.table[\"G\"] = 71\n\tthis.table[\"H\"] = 72\n\tthis.table[\"I\"] = 73\n\tthis.table[\"J\"] = 74\n\tthis.table[\"K\"] = 75\n\tthis.table[\"L\"] = 76\n\tthis.table[\"M\"] = 77\n\tthis.table[\"N\"] = 78\n\tthis.table[\"O\"] = 79\n\tthis.table[\"P\"] = 80\n\tthis.table[\"Q\"] = 81\n\tthis.table[\"R\"] = 82\n\tthis.table[\"S\"] = 83\n\tthis.table[\"T\"] = 84\n\tthis.table[\"U\"] = 85\n\tthis.table[\"V\"] = 86\n\tthis.table[\"W\"] = 87\n\tthis.table[\"X\"] = 88\n\tthis.table[\"Y\"] = 89\n\tthis.table[\"Z\"] = 90\n\tthis.table[\"[\"] = 91\n\tthis.table[\"\\\\\"] = 92\n\tthis.table[\"]\"] = 93\n\tthis.table[\"^\"] = 94\n\tthis.table[\"_\"] = 95\n\tthis.table[\"`\"] = 96\n\tthis.table[\"a\"] = 97\n\tthis.table[\"b\"] = 98\n\tthis.table[\"c\"] = 99\n\tthis.table[\"d\"] = 100\n\tthis.table[\"e\"] = 101\n\tthis.table[\"f\"] = 102\n\tthis.table[\"g\"] = 103\n\tthis.table[\"h\"] = 104\n\tthis.table[\"i\"] = 105\n\tthis.table[\"j\"] = 106\n\tthis.table[\"k\"] = 107\n\tthis.table[\"l\"] = 108\n\tthis.table[\"m\"] = 109\n\tthis.table[\"n\"] = 110\n\tthis.table[\"o\"] = 111\n\tthis.table[\"p\"] = 112\n\tthis.table[\"q\"] = 113\n\tthis.table[\"r\"] = 114\n\tthis.table[\"s\"] = 115\n\tthis.table[\"t\"] = 116\n\tthis.table[\"u\"] = 117\n\tthis.table[\"v\"] = 118\n\tthis.table[\"w\"] = 119\n\tthis.table[\"x\"] = 120\n\tthis.table[\"y\"] = 121\n\tthis.table[\"z\"] = 122\n\tthis.table[\"{\"] = 123\n\tthis.table[\"|\"] = 124\n\tthis.table[\"}\"] = 125\n\tthis.table[\"~\"] = 126\n\tthis.table[\"Ç\"] = 128\n\tthis.table[\"ü\"] = 129\n\tthis.table[\"é\"] = 130\n\tthis.table[\"â\"] = 131\n\tthis.table[\"ä\"] = 132\n\tthis.table[\"à\"] = 133\n\tthis.table[\"å\"] = 134\n\tthis.table[\"ç\"] = 135\n\tthis.table[\"ê\"] = 136\n\tthis.table[\"ë\"] = 137\n\tthis.table[\"è\"] = 138\n\tthis.table[\"ï\"] = 139\n\tthis.table[\"î\"] = 140\n\tthis.table[\"ì\"] = 141\n\tthis.table[\"Ä\"] = 142\n\tthis.table[\"Å\"] = 143\n\tthis.table[\"É\"] = 144\n\tthis.table[\"æ\"] = 145\n\tthis.table[\"Æ\"] = 146\n\tthis.table[\"ô\"] = 147\n\tthis.table[\"ö\"] = 148\n\tthis.table[\"ò\"] = 149\n\tthis.table[\"û\"] = 150\n\tthis.table[\"ù\"] = 151\n\tthis.table[\"ÿ\"] = 152\n\tthis.table[\"Ö\"] = 153\n\tthis.table[\"Ü\"] = 154\n\tthis.table[\"ø\"] = 155\n\tthis.table[\"£\"] = 156\n\tthis.table[\"Ø\"] = 157\n\tthis.table[\"×\"] = 158\n\tthis.table[\"ƒ\"] = 159\n\tthis.table[\"á\"] = 160\n\tthis.table[\"í\"] = 161\n\tthis.table[\"ó\"] = 162\n\tthis.table[\"ú\"] = 163\n\tthis.table[\"ñ\"] = 164\n\tthis.table[\"Ñ\"] = 165\n\tthis.table[\"ª\"] = 166\n\tthis.table[\"º\"] = 167\n\tthis.table[\"¿\"] = 168\n\tthis.table[\"®\"] = 169\n\tthis.table[\"¬\"] = 170\n\tthis.table[\"½\"] = 171\n\tthis.table[\"¼\"] = 172\n\tthis.table[\"¡\"] = 173\n\tthis.table[\"«\"] = 174\n\tthis.table[\"»\"] = 175\n\tthis.table[\"░\"] = 176\n\tthis.table[\"▒\"] = 177\n\tthis.table[\"▓\"] = 178\n\tthis.table[\"│\"] = 179\n\tthis.table[\"┤\"] = 180\n\tthis.table[\"Á\"] = 181\n\tthis.table[\"Â\"] = 182\n\tthis.table[\"À\"] = 183\n\tthis.table[\"©\"] = 184\n\tthis.table[\"╣\"] = 185\n\tthis.table[\"║\"] = 186\n\tthis.table[\"╗\"] = 187\n\tthis.table[\"╝\"] = 188\n\tthis.table[\"¢\"] = 189\n\tthis.table[\"¥\"] = 190\n\tthis.table[\"┐\"] = 191\n\tthis.table[\"└\"] = 192\n\tthis.table[\"┴\"] = 193\n\tthis.table[\"┬\"] = 194\n\tthis.table[\"├\"] = 195\n\tthis.table[\"─\"] = 196\n\tthis.table[\"┼\"] = 197\n\tthis.table[\"ã\"] = 198\n\tthis.table[\"Ã\"] = 199\n\tthis.table[\"╚\"] = 200\n\tthis.table[\"╔\"] = 201\n\tthis.table[\"╩\"] = 202\n\tthis.table[\"╦\"] = 203\n\tthis.table[\"╠\"] = 204\n\tthis.table[\"═\"] = 205\n\tthis.table[\"╬\"] = 206\n\tthis.table[\"¤\"] = 207\n\tthis.table[\"ð\"] = 208\n\tthis.table[\"Ð\"] = 209\n\tthis.table[\"Ê\"] = 210\n\tthis.table[\"Ë\"] = 211\n\tthis.table[\"È\"] = 212\n\tthis.table[\"ı\"] = 213\n\tthis.table[\"Í\"] = 214\n\tthis.table[\"Î\"] = 215\n\tthis.table[\"Ï\"] = 216\n\tthis.table[\"┘\"] = 217\n\tthis.table[\"┌\"] = 218\n\tthis.table[\"█\"] = 219\n\tthis.table[\"▄\"] = 220\n\tthis.table[\"¦\"] = 221\n\tthis.table[\"Ì\"] = 222\n\tthis.table[\"▀\"] = 223\n\tthis.table[\"Ó\"] = 224\n\tthis.table[\"ß\"] = 225\n\tthis.table[\"Ô\"] = 226\n\tthis.table[\"Ò\"] = 227\n\tthis.table[\"õ\"] = 228\n\tthis.table[\"Õ\"] = 229\n\tthis.table[\"µ\"] = 230\n\tthis.table[\"þ\"] = 231\n\tthis.table[\"Þ\"] = 232\n\tthis.table[\"Ú\"] = 233\n\tthis.table[\"Û\"] = 234\n\tthis.table[\"Ù\"] = 235\n\tthis.table[\"ý\"] = 236\n\tthis.table[\"Ý\"] = 237\n\tthis.table[\"¯\"] = 238\n\tthis.table[\"´\"] = 239\n\tthis.table[\"≡\"] = 240\n\tthis.table[\"±\"] = 241\n\tthis.table[\"‗\"] = 242\n\tthis.table[\"¾\"] = 243\n\tthis.table[\"¶\"] = 244\n\tthis.table[\"§\"] = 245\n\tthis.table[\"÷\"] = 246\n\tthis.table[\"¸\"] = 247\n\tthis.table[\"°\"] = 248\n\tthis.table[\"¨\"] = 249\n\tthis.table[\"·\"] = 250\n\tthis.table[\"¹\"] = 251\n\tthis.table[\"³\"] = 252\n\tthis.table[\"²\"] = 253\n\tthis.table[\"■\"] = 254\n\n\tfor character, value := range this.table {\n\t\tthis.inverted_table[value] = character\n\t}\n\n\tthis.unknown = \"■\"\n}\n\nfunc (this *AsciiEncoder) Encode(characters string) *ByteStream {\n\tbyte_stream := new(ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, character := range characters {\n\t\tvalue := this.table[string(character)]\n\t\tbyte_stream.Append(value)\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *AsciiEncoder) Decode(byte_stream *ByteStream) string {\n\tcharacters := \"\"\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tcharacters += this.inverted_table[value]\n\t}\n\n\treturn characters\n}\n\nfunc (this *AsciiEncoder) Unknown() string {\n\treturn this.unknown\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/encoding/byte_stream.go",
    "content": "package encoding\n\nimport (\n\t\"errors\"\n)\n\ntype ByteStream struct {\n\tbytes []uint8\n}\n\nfunc (this *ByteStream) Init() {\n\tthis.bytes = make([]uint8, 0)\n}\n\nfunc (this *ByteStream) Size() int64 {\n\treturn int64(len(this.bytes))\n}\n\nfunc (this *ByteStream) Get(pos int) uint8 {\n\treturn this.bytes[pos]\n}\n\nfunc (this *ByteStream) Set(pos int, value uint8) {\n\tthis.bytes[pos] = value\n}\n\nfunc (this *ByteStream) Append(value uint8) {\n\tthis.bytes = append(this.bytes, value)\n}\n\nfunc (this *ByteStream) Remove(pos int) {\n\tthis.bytes = append(this.bytes[:pos], this.bytes[pos+1:]...)\n}\n\nfunc (this *ByteStream) Merge(byte_stream *ByteStream) {\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tvalue := byte_stream.Get(int(i))\n\t\tthis.Append(value)\n\t}\n}\n\nfunc (this *ByteStream) Signbit() bool {\n\tlast_byte := this.Get(int(this.Size() - 1))\n\tsign_bit := ((int(last_byte) & (1 << 7)) >> 7) == 1\n\treturn sign_bit\n}\n\nfunc (this *ByteStream) SignedValue() int64 {\n\tif this.Size() > 8 {\n\t\terr := errors.New(\"byte stream cannot convert into an integer\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(0)\n\tfor i := int64(0); i < this.Size()-1; i++ {\n\t\tvalue += int64(this.Get(int(i))) * this.Pow2(int(8*i))\n\t}\n\n\tlast_byte := this.Get(int(this.Size() - 1))\n\n\tfor i := 0; i < 7; i++ {\n\t\tbit := ((int(last_byte) & (1 << i)) >> i) == 1\n\n\t\tif bit {\n\t\t\tvalue += this.Pow2(8*(len(this.bytes)-1) + i)\n\t\t}\n\t}\n\n\tif this.Signbit() {\n\t\tvalue -= this.Pow2(8*len(this.bytes) - 1)\n\t}\n\n\treturn value\n}\n\nfunc (this *ByteStream) UnsignedValue() int64 {\n\tif this.Size() > 8 {\n\t\terr := errors.New(\"byte stream cannot convert into an integer\")\n\t\tpanic(err)\n\t}\n\n\tvalue := int64(0)\n\tfor i := int64(0); i < this.Size(); i++ {\n\t\tvalue += int64(this.Get(int(i))) * this.Pow2(int(8*i))\n\t}\n\treturn value\n}\n\nfunc (this *ByteStream) Pow2(exponent int) int64 {\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/abi/binary.go",
    "content": "package abi\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Binary struct {\n\tbenchmark    string\n\tnum_dpus     int\n\tnum_tasklets int\n\n\ttoken_stream *lexer.TokenStream\n\tast          *parser.Ast\n\trelocatable  *Relocatable\n}\n\nfunc (this *Binary) Init(benchmark string, num_dpus int, num_tasklets int) {\n\tif num_dpus <= 0 {\n\t\terr := errors.New(\"num DPUs <= 0\")\n\t\tpanic(err)\n\t} else if num_tasklets <= 0 {\n\t\terr := errors.New(\"num tasklets <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.benchmark = benchmark\n\tthis.num_dpus = num_dpus\n\tthis.num_tasklets = num_tasklets\n\n\tthis.token_stream = nil\n\tthis.ast = nil\n\tthis.relocatable = nil\n}\n\nfunc (this *Binary) Benchmark() string {\n\treturn this.benchmark\n}\n\nfunc (this *Binary) NumDpus() int {\n\treturn this.num_dpus\n}\n\nfunc (this *Binary) NumTasklets() int {\n\treturn this.num_tasklets\n}\n\nfunc (this *Binary) TokenStream() *lexer.TokenStream {\n\tif this.token_stream == nil {\n\t\terr := errors.New(\"token stream == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.token_stream\n}\n\nfunc (this *Binary) SetTokenStream(token_stream *lexer.TokenStream) {\n\tif this.token_stream != nil {\n\t\terr := errors.New(\"token stream != nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.token_stream = token_stream\n}\n\nfunc (this *Binary) Ast() *parser.Ast {\n\tif this.ast == nil {\n\t\terr := errors.New(\"AST == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ast\n}\n\nfunc (this *Binary) SetAst(ast *parser.Ast) {\n\tif this.ast != nil {\n\t\terr := errors.New(\"AST != nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.ast = ast\n}\n\nfunc (this *Binary) Relocatable() *Relocatable {\n\tif this.relocatable == nil {\n\t\terr := errors.New(\"relocatable == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.relocatable\n}\n\nfunc (this *Binary) SetRelocatable(relocatable *Relocatable) {\n\tif this.relocatable != nil {\n\t\terr := errors.New(\"relocatable != nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.relocatable = relocatable\n}\n\nfunc (this *Binary) Dump(path string) {\n\tlines := make([]string, 0)\n\n\tfor _, label := range this.relocatable.Labels() {\n\t\tlines = append(lines, label.Stringify())\n\t}\n\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(path)\n\tfile_dumper.WriteLines(lines)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/abi/bytecode.go",
    "content": "package abi\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype Bytecode struct {\n\top_code OpCode\n\targ1    *int64\n\targ2    *int64\n\tstr1    *string\n\tstr2    *string\n}\n\nfunc (this *Bytecode) Init(op_code OpCode, args []int64, strs []string) {\n\tthis.op_code = op_code\n\n\tif len(args) == 0 {\n\t\tthis.arg1 = nil\n\t\tthis.arg2 = nil\n\t} else if len(args) == 1 {\n\t\tthis.arg1 = new(int64)\n\t\t*this.arg1 = args[0]\n\n\t\tthis.arg2 = nil\n\t} else if len(args) == 2 {\n\t\tthis.arg1 = new(int64)\n\t\t*this.arg1 = args[0]\n\n\t\tthis.arg2 = new(int64)\n\t\t*this.arg2 = args[1]\n\t} else {\n\t\terr := errors.New(\"len(args) > 2\")\n\t\tpanic(err)\n\t}\n\n\tif len(strs) == 0 {\n\t\tthis.str1 = nil\n\t\tthis.str2 = nil\n\t} else if len(strs) == 1 {\n\t\tthis.str1 = new(string)\n\t\t*this.str1 = strs[0]\n\n\t\tthis.str2 = nil\n\t} else if len(strs) == 2 {\n\t\tthis.str1 = new(string)\n\t\t*this.str1 = strs[0]\n\n\t\tthis.str2 = new(string)\n\t\t*this.str2 = strs[1]\n\t} else {\n\t\terr := errors.New(\"len(strs) > 2\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Bytecode) OpCode() OpCode {\n\treturn this.op_code\n}\n\nfunc (this *Bytecode) Arg1() int64 {\n\tif this.arg1 == nil {\n\t\terr := errors.New(\"arg1 == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.arg1\n}\n\nfunc (this *Bytecode) Arg2() int64 {\n\tif this.arg2 == nil {\n\t\terr := errors.New(\"arg2 == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.arg2\n}\n\nfunc (this *Bytecode) Str1() string {\n\tif this.str1 == nil {\n\t\terr := errors.New(\"str1 == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.str1\n}\n\nfunc (this *Bytecode) Str2() string {\n\tif this.str2 == nil {\n\t\terr := errors.New(\"str2 == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.str2\n}\n\nfunc (this *Bytecode) Stringify() string {\n\tif this.op_code == NEW_SCOPE {\n\t\treturn \"NEW_SCOPE\"\n\t} else if this.op_code == DELETE_SCOPE {\n\t\treturn \"DELETE_SCOPE\"\n\t} else if this.op_code == PUSH_CHAR {\n\t\treturn fmt.Sprintf(\"PUSH_CHAR %d\", *this.arg1)\n\t} else if this.op_code == PUSH_SHORT {\n\t\treturn fmt.Sprintf(\"PUSH_SHORT %d\", *this.arg1)\n\t} else if this.op_code == PUSH_INT {\n\t\treturn fmt.Sprintf(\"PUSH_INT %d\", *this.arg1)\n\t} else if this.op_code == PUSH_LONG {\n\t\treturn fmt.Sprintf(\"PUSH_LONG %d\", *this.arg1)\n\t} else if this.op_code == PUSH_STRING {\n\t\treturn fmt.Sprintf(\"PUSH_STRING %s\", *this.str1)\n\t} else if this.op_code == POP {\n\t\treturn \"POP\"\n\t} else if this.op_code == BEGIN_STRUCT {\n\t\treturn fmt.Sprintf(\"BEGIN_STRUCT %s\", *this.str1)\n\t} else if this.op_code == APPEND_VOID {\n\t\treturn fmt.Sprintf(\"APPEND_VOID %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == APPEND_CHAR {\n\t\treturn fmt.Sprintf(\"APPEND_VOID %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == APPEND_SHORT {\n\t\treturn fmt.Sprintf(\"APPEND_SHORT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == APPEND_INT {\n\t\treturn fmt.Sprintf(\"APPEND_INT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == APPEND_LONG {\n\t\treturn fmt.Sprintf(\"APPEND_LONG %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == APPEND_STRUCT {\n\t\treturn fmt.Sprintf(\"APPEND_STRUCT %d %s %s\", *this.arg1, *this.str1, *this.str2)\n\t} else if this.op_code == END_STRUCT {\n\t\treturn \"END_STRUCT\"\n\t} else if this.op_code == NEW_GLOBAL_VOID {\n\t\treturn fmt.Sprintf(\"NEW_GLOBAL_VOID %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_GLOBAL_CHAR {\n\t\treturn fmt.Sprintf(\"NEW_GLOBAL_CHAR %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_GLOBAL_SHORT {\n\t\treturn fmt.Sprintf(\"NEW_GLOBAL_SHORT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_GLOBAL_INT {\n\t\treturn fmt.Sprintf(\"NEW_GLOBAL_INT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_GLOBAL_LONG {\n\t\treturn fmt.Sprintf(\"NEW_GLOBAL_LONG %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_VOID {\n\t\treturn fmt.Sprintf(\"NEW_FAST_VOID %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_CHAR {\n\t\treturn fmt.Sprintf(\"NEW_FAST_CHAR %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_SHORT {\n\t\treturn fmt.Sprintf(\"NEW_FAST_SHORT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_INT {\n\t\treturn fmt.Sprintf(\"NEW_FAST_INT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_LONG {\n\t\treturn fmt.Sprintf(\"NEW_FAST_LONG %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_FAST_STRUCT {\n\t\treturn fmt.Sprintf(\"NEW_FAST_STRUCT %d %s %s\", *this.arg1, *this.str1, *this.str2)\n\t} else if this.op_code == NEW_ARG_VOID {\n\t\treturn fmt.Sprintf(\"NEW_ARG_VOID %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_ARG_CHAR {\n\t\treturn fmt.Sprintf(\"NEW_ARG_CHAR %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_ARG_SHORT {\n\t\treturn fmt.Sprintf(\"NEW_ARG_SHORT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_ARG_INT {\n\t\treturn fmt.Sprintf(\"NEW_ARG_INT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_ARG_LONG {\n\t\treturn fmt.Sprintf(\"NEW_ARG_LONG %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == NEW_ARG_STRUCT {\n\t\treturn fmt.Sprintf(\"NEW_ARG_STRUCT %d %s %s\", *this.arg1, *this.str1, *this.str2)\n\t} else if this.op_code == NEW_RETURN_VOID {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_VOID %d\", *this.arg1)\n\t} else if this.op_code == NEW_RETURN_CHAR {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_CHAR %d\", *this.arg1)\n\t} else if this.op_code == NEW_RETURN_SHORT {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_SHORT %d\", *this.arg1)\n\t} else if this.op_code == NEW_RETURN_INT {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_INT %d\", *this.arg1)\n\t} else if this.op_code == NEW_RETURN_LONG {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_LONG %d\", *this.arg1)\n\t} else if this.op_code == NEW_RETURN_STRUCT {\n\t\treturn fmt.Sprintf(\"NEW_RETURN_STRUCT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == SIZEOF_VOID {\n\t\treturn fmt.Sprintf(\"SIZEOF_VOID %d\", *this.arg1)\n\t} else if this.op_code == SIZEOF_CHAR {\n\t\treturn fmt.Sprintf(\"SIZEOF_CHAR %d\", *this.arg1)\n\t} else if this.op_code == SIZEOF_SHORT {\n\t\treturn fmt.Sprintf(\"SIZEOF_SHORT %d\", *this.arg1)\n\t} else if this.op_code == SIZEOF_INT {\n\t\treturn fmt.Sprintf(\"SIZEOF_INT %d\", *this.arg1)\n\t} else if this.op_code == SIZEOF_LONG {\n\t\treturn fmt.Sprintf(\"SIZEOF_LONG %d\", *this.arg1)\n\t} else if this.op_code == SIZEOF_STRUCT {\n\t\treturn fmt.Sprintf(\"SIZEOF_STRUCT %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == GET_IDENTIFIER {\n\t\treturn fmt.Sprintf(\"GET_IDENTIFIER %s\", *this.str1)\n\t} else if this.op_code == GET_ARG_IDENTIFIER {\n\t\treturn fmt.Sprintf(\"GET_ARG_IDENTIFIER %s\", *this.str1)\n\t} else if this.op_code == GET_SUBSCRIPT {\n\t\treturn \"GET_SUBSCRIPT\"\n\t} else if this.op_code == GET_ACCESS {\n\t\treturn fmt.Sprintf(\"GET_ACCESS %s\", *this.str1)\n\t} else if this.op_code == GET_REFERENCE {\n\t\treturn fmt.Sprintf(\"GET_REFERENCE %s\", *this.str1)\n\t} else if this.op_code == GET_ADDRESS {\n\t\treturn \"GET_ADDRESS\"\n\t} else if this.op_code == GET_VALUE {\n\t\treturn \"GET_VALUE\"\n\t} else if this.op_code == ALLOC {\n\t\treturn \"ALLOC\"\n\t} else if this.op_code == FREE {\n\t\treturn \"FREE\"\n\t} else if this.op_code == ASSERT {\n\t\treturn \"ASSERT\"\n\t} else if this.op_code == ADD {\n\t\treturn \"ADD\"\n\t} else if this.op_code == SUB {\n\t\treturn \"SUB\"\n\t} else if this.op_code == MUL {\n\t\treturn \"MUL\"\n\t} else if this.op_code == DIV {\n\t\treturn \"DIV\"\n\t} else if this.op_code == MOD {\n\t\treturn \"MOD\"\n\t} else if this.op_code == LSHIFT {\n\t\treturn \"LSHIFT\"\n\t} else if this.op_code == RSHIFT {\n\t\treturn \"RSHIFT\"\n\t} else if this.op_code == NEGATE {\n\t\treturn \"NEGATE\"\n\t} else if this.op_code == TILDE {\n\t\treturn \"TILDE\"\n\t} else if this.op_code == SQRT {\n\t\treturn \"SQRT\"\n\t} else if this.op_code == BITWISE_AND {\n\t\treturn \"BITWISE_AND\"\n\t} else if this.op_code == BITWISE_XOR {\n\t\treturn \"BITWISE_XOR\"\n\t} else if this.op_code == BITWISE_OR {\n\t\treturn \"BITWISE_OR\"\n\t} else if this.op_code == LOGICAL_AND {\n\t\treturn \"LOGICAL_AND\"\n\t} else if this.op_code == LOGICAL_OR {\n\t\treturn \"LOGICAL_OR\"\n\t} else if this.op_code == LOGICAL_NOT {\n\t\treturn \"LOGICAL_NOT\"\n\t} else if this.op_code == EQ {\n\t\treturn \"EQ\"\n\t} else if this.op_code == NOT_EQ {\n\t\treturn \"NOT_EQ\"\n\t} else if this.op_code == LESS {\n\t\treturn \"LESS\"\n\t} else if this.op_code == LESS_EQ {\n\t\treturn \"LESS_EQ\"\n\t} else if this.op_code == GREATER {\n\t\treturn \"GREATER\"\n\t} else if this.op_code == GREATER_EQ {\n\t\treturn \"GREATER_EQ\"\n\t} else if this.op_code == CONDITIONAL {\n\t\treturn \"CONDITIONAL\"\n\t} else if this.op_code == ASSIGN {\n\t\treturn \"ASSIGN\"\n\t} else if this.op_code == ASSIGN_STAR {\n\t\treturn \"ASSIGN_STAR\"\n\t} else if this.op_code == ASSIGN_DIV {\n\t\treturn \"ASSIGN_DIV\"\n\t} else if this.op_code == ASSIGN_MOD {\n\t\treturn \"ASSIGN_MOD\"\n\t} else if this.op_code == ASSIGN_ADD {\n\t\treturn \"ASSIGN_ADD\"\n\t} else if this.op_code == ASSIGN_SUB {\n\t\treturn \"ASSIGN_SUB\"\n\t} else if this.op_code == ASSIGN_LSHIFT {\n\t\treturn \"ASSIGN_LSHIFT\"\n\t} else if this.op_code == ASSIGN_RSHIFT {\n\t\treturn \"ASSIGN_RSHIFT\"\n\t} else if this.op_code == ASSIGN_BITWISE_AND {\n\t\treturn \"ASSIGN_BITWISE_AND\"\n\t} else if this.op_code == ASSIGN_BITWISE_XOR {\n\t\treturn \"ASSIGN_BITWISE_XOR\"\n\t} else if this.op_code == ASSIGN_BITWISE_OR {\n\t\treturn \"ASSIGN_BITWISE_OR\"\n\t} else if this.op_code == ASSIGN_PLUS_PLUS {\n\t\treturn \"ASSIGN_PLUS_PLUS\"\n\t} else if this.op_code == ASSIGN_MINUS_MINUS {\n\t\treturn \"ASSIGN_MINUS_MINUS\"\n\t} else if this.op_code == ASSIGN_RETURN {\n\t\treturn \"ASSIGN_RETURN\"\n\t} else if this.op_code == JUMP {\n\t\treturn fmt.Sprintf(\"JUMP %s\", *this.str1)\n\t} else if this.op_code == JUMP_IF_ZERO {\n\t\treturn fmt.Sprintf(\"JUMP_IF_ZERO %s\", *this.str1)\n\t} else if this.op_code == JUMP_IF_NONZERO {\n\t\treturn fmt.Sprintf(\"JUMP_IF_NONZERO %s\", *this.str1)\n\t} else if this.op_code == CALL {\n\t\treturn fmt.Sprintf(\"CALL %s\", *this.str1)\n\t} else if this.op_code == RETURN {\n\t\treturn \"RETURN\"\n\t} else if this.op_code == NOP {\n\t\treturn \"NOP\"\n\t} else if this.op_code == DPU_ALLOC {\n\t\treturn fmt.Sprintf(\"DPU_ALLOC %d\", *this.arg1)\n\t} else if this.op_code == DPU_LOAD {\n\t\treturn fmt.Sprintf(\"DPU_LOAD %d %s\", *this.arg1, *this.str1)\n\t} else if this.op_code == DPU_PREPARE {\n\t\treturn \"DPU_PREPARE\"\n\t} else if this.op_code == DPU_TRANSFER {\n\t\treturn \"DPU_TRANSFER\"\n\t} else if this.op_code == DPU_COPY_TO {\n\t\treturn \"DPU_COPY_TO\"\n\t} else if this.op_code == DPU_COPY_FROM {\n\t\treturn \"DPU_COPY_FROM\"\n\t} else if this.op_code == DPU_LAUNCH {\n\t\treturn \"DPU_LAUNCH\"\n\t} else if this.op_code == DPU_FREE {\n\t\treturn \"DPU_FREE\"\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/abi/label.go",
    "content": "package abi\n\nimport (\n\t\"fmt\"\n)\n\ntype Label struct {\n\tname      string\n\tbytecodes []*Bytecode\n}\n\nfunc (this *Label) Init(name string) {\n\tthis.name = name\n}\n\nfunc (this *Label) Name() string {\n\treturn this.name\n}\n\nfunc (this *Label) Length() int {\n\treturn len(this.bytecodes)\n}\n\nfunc (this *Label) Get(index int) *Bytecode {\n\treturn this.bytecodes[index]\n}\n\nfunc (this *Label) Append(bytecode *Bytecode) {\n\tthis.bytecodes = append(this.bytecodes, bytecode)\n}\n\nfunc (this *Label) Stringify() string {\n\tss := fmt.Sprintf(\"%s:\\n\", this.name)\n\n\tfor i := 0; i < len(this.bytecodes); i++ {\n\t\tbytecode := this.bytecodes[i]\n\n\t\tif i != len(this.bytecodes)-1 {\n\t\t\tss += fmt.Sprintf(\"\\t%s\\n\", bytecode.Stringify())\n\t\t} else {\n\t\t\tss += fmt.Sprintf(\"\\t%s\", bytecode.Stringify())\n\t\t}\n\t}\n\n\treturn ss\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/abi/op_code.go",
    "content": "package abi\n\ntype OpCode int\n\nconst (\n\tNEW_SCOPE OpCode = iota\n\tDELETE_SCOPE\n\n\tPUSH_CHAR\n\tPUSH_SHORT\n\tPUSH_INT\n\tPUSH_LONG\n\tPUSH_STRING\n\n\tPOP\n\n\tBEGIN_STRUCT\n\tAPPEND_VOID\n\tAPPEND_CHAR\n\tAPPEND_SHORT\n\tAPPEND_INT\n\tAPPEND_LONG\n\tAPPEND_STRUCT\n\tEND_STRUCT\n\n\tNEW_GLOBAL_VOID\n\tNEW_GLOBAL_CHAR\n\tNEW_GLOBAL_SHORT\n\tNEW_GLOBAL_INT\n\tNEW_GLOBAL_LONG\n\n\tNEW_FAST_VOID\n\tNEW_FAST_CHAR\n\tNEW_FAST_SHORT\n\tNEW_FAST_INT\n\tNEW_FAST_LONG\n\tNEW_FAST_STRUCT\n\n\tNEW_ARG_VOID\n\tNEW_ARG_CHAR\n\tNEW_ARG_SHORT\n\tNEW_ARG_INT\n\tNEW_ARG_LONG\n\tNEW_ARG_STRUCT\n\n\tNEW_RETURN_VOID\n\tNEW_RETURN_CHAR\n\tNEW_RETURN_SHORT\n\tNEW_RETURN_INT\n\tNEW_RETURN_LONG\n\tNEW_RETURN_STRUCT\n\n\tSIZEOF_VOID\n\tSIZEOF_CHAR\n\tSIZEOF_SHORT\n\tSIZEOF_INT\n\tSIZEOF_LONG\n\tSIZEOF_STRUCT\n\n\tGET_IDENTIFIER\n\tGET_ARG_IDENTIFIER\n\n\tGET_SUBSCRIPT\n\tGET_ACCESS\n\tGET_REFERENCE\n\tGET_ADDRESS\n\tGET_VALUE\n\n\tALLOC\n\tFREE\n\n\tASSERT\n\n\tADD\n\tSUB\n\tMUL\n\tDIV\n\tMOD\n\n\tLSHIFT\n\tRSHIFT\n\n\tNEGATE\n\tTILDE\n\tSQRT\n\n\tBITWISE_AND\n\tBITWISE_XOR\n\tBITWISE_OR\n\n\tLOGICAL_AND\n\tLOGICAL_OR\n\tLOGICAL_NOT\n\n\tEQ\n\tNOT_EQ\n\tLESS\n\tLESS_EQ\n\tGREATER\n\tGREATER_EQ\n\n\tCONDITIONAL\n\n\tASSIGN\n\tASSIGN_STAR\n\tASSIGN_DIV\n\tASSIGN_MOD\n\tASSIGN_ADD\n\tASSIGN_SUB\n\tASSIGN_LSHIFT\n\tASSIGN_RSHIFT\n\tASSIGN_BITWISE_AND\n\tASSIGN_BITWISE_XOR\n\tASSIGN_BITWISE_OR\n\tASSIGN_PLUS_PLUS\n\tASSIGN_MINUS_MINUS\n\tASSIGN_RETURN\n\n\tJUMP\n\tJUMP_IF_ZERO\n\tJUMP_IF_NONZERO\n\n\tCALL\n\n\tRETURN\n\n\tNOP\n\n\tDPU_ALLOC\n\tDPU_LOAD\n\tDPU_PREPARE\n\tDPU_TRANSFER\n\tDPU_COPY_TO\n\tDPU_COPY_FROM\n\tDPU_LAUNCH\n\tDPU_FREE\n)\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/abi/relocatable.go",
    "content": "package abi\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype Relocatable struct {\n\tlabels []*Label\n\n\tcur_func *Label\n\n\tcur_loop_condition *Label\n\tcur_loop_body      *Label\n\tcur_loop_end       *Label\n\n\tcur_label *Label\n\n\tlabel_brk int\n}\n\nfunc (this *Relocatable) Init() {\n\tthis.labels = make([]*Label, 0)\n\n\tthis.cur_func = nil\n\n\tthis.cur_loop_condition = nil\n\tthis.cur_loop_body = nil\n\tthis.cur_loop_end = nil\n\n\tthis.cur_label = nil\n\n\tthis.label_brk = 0\n}\n\nfunc (this *Relocatable) HasFunc(func_name string) bool {\n\treturn this.HasLabel(func_name)\n}\n\nfunc (this *Relocatable) CurFunc() *Label {\n\tif this.cur_func == nil {\n\t\terr := errors.New(\"cur func == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.cur_func\n}\n\nfunc (this *Relocatable) NewFunc(func_name string) *Label {\n\tlabel := this.NewNamedLabel(func_name)\n\n\treturn label\n}\n\nfunc (this *Relocatable) SwitchFunc(func_name string) {\n\tthis.cur_func = this.Label(func_name)\n}\n\nfunc (this *Relocatable) CurLoopCondition() *Label {\n\tif this.cur_loop_condition == nil {\n\t\terr := errors.New(\"cur loop condition == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.cur_loop_condition\n}\n\nfunc (this *Relocatable) CurLoopBody() *Label {\n\tif this.cur_loop_body == nil {\n\t\terr := errors.New(\"cur loop body == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.cur_loop_body\n}\n\nfunc (this *Relocatable) CurLoopEnd() *Label {\n\tif this.cur_loop_end == nil {\n\t\terr := errors.New(\"cur loop end == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.cur_loop_end\n}\n\nfunc (this *Relocatable) NewLoop() (*Label, *Label, *Label) {\n\tthis.cur_loop_condition = this.NewUnnamedLabel()\n\tthis.cur_loop_body = this.NewUnnamedLabel()\n\tthis.cur_loop_end = this.NewUnnamedLabel()\n\n\treturn this.cur_loop_condition, this.cur_loop_body, this.cur_loop_end\n}\n\nfunc (this *Relocatable) HasLabel(label_name string) bool {\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn true\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *Relocatable) Label(label_name string) *Label {\n\tif !this.HasLabel(label_name) {\n\t\terr_msg := fmt.Sprintf(\"label (%s) is not found\", label_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn label\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *Relocatable) Labels() []*Label {\n\treturn this.labels\n}\n\nfunc (this *Relocatable) NewNamedLabel(label_name string) *Label {\n\tif this.HasLabel(label_name) {\n\t\terr_msg := fmt.Sprintf(\"label (%s) already exists\", label_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tlabel := new(Label)\n\tlabel.Init(label_name)\n\n\tthis.labels = append(this.labels, label)\n\n\treturn label\n}\n\nfunc (this *Relocatable) NewUnnamedLabel() *Label {\n\tlabel_name := fmt.Sprintf(\"L%d\", this.label_brk)\n\tthis.label_brk++\n\n\tlabel := new(Label)\n\tlabel.Init(label_name)\n\n\tthis.labels = append(this.labels, label)\n\n\treturn label\n}\n\nfunc (this *Relocatable) SwitchLabel(label_name string) {\n\tthis.cur_label = this.Label(label_name)\n}\n\nfunc (this *Relocatable) CurLabel() *Label {\n\treturn this.cur_label\n}\n\nfunc (this *Relocatable) NewBytecode(op_code OpCode, args []int64, strs []string) {\n\tbytecode := new(Bytecode)\n\tbytecode.Init(op_code, args, strs)\n\n\tthis.cur_label.Append(bytecode)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/codegen/codegen.go",
    "content": "package codegen\n\nimport (\n\t\"errors\"\n\t\"strconv\"\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/host/interpreter/codegen/type_system\"\n\t\"uPIMulator/src/host/interpreter/parser\"\n\t\"uPIMulator/src/host/interpreter/parser/decl\"\n\t\"uPIMulator/src/host/interpreter/parser/directive\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n\t\"uPIMulator/src/host/interpreter/parser/stmt\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype Codegen struct {\n\tbenchmark        string\n\tnum_dpus         int\n\tnum_tasklets     int\n\tdata_prep_params int\n\n\tdpu_mram_heap_pointer_name int64\n\n\ttype_system *type_system.TypeSystem\n\n\trelocatable *abi.Relocatable\n\n\tcur_block_depth int\n\tblock_depths    map[string]int\n}\n\nfunc (this *Codegen) Init(\n\tbenchmark string,\n\tnum_dpus int,\n\tnum_tasklets int,\n\tdata_prep_params int,\n\tdpu_mram_heap_pointer_name int64,\n) {\n\tthis.benchmark = benchmark\n\tthis.num_dpus = num_dpus\n\tthis.num_tasklets = num_tasklets\n\tthis.data_prep_params = data_prep_params\n\tthis.dpu_mram_heap_pointer_name = dpu_mram_heap_pointer_name\n\n\tthis.type_system = new(type_system.TypeSystem)\n\tthis.type_system.Init()\n\n\tthis.relocatable = new(abi.Relocatable)\n\tthis.relocatable.Init()\n\n\tthis.cur_block_depth = 0\n\tthis.block_depths = make(map[string]int)\n}\n\nfunc (this *Codegen) Codegen(ast *parser.Ast) *abi.Relocatable {\n\tthis.CodegenInitBootstrap()\n\n\tfor i := 0; i < ast.Length(); i++ {\n\t\tstack_item := ast.Get(i)\n\n\t\tif stack_item.StackItemType() == parser.DIRECTIVE {\n\t\t\tthis.CodegenDirective(stack_item.Directive())\n\t\t} else if stack_item.StackItemType() == parser.DECL {\n\t\t\tthis.CodegenDecl(stack_item.Decl())\n\t\t} else {\n\t\t\terr := errors.New(\"stack item is not directive nor decl\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.CodegenFiniBootstrap()\n\n\treturn this.relocatable\n}\n\nfunc (this *Codegen) CodegenInitBootstrap() {\n\tthis.relocatable.NewFunc(\"__bootstrap\")\n\tthis.relocatable.SwitchLabel(\"__bootstrap\")\n\n\tthis.relocatable.NewBytecode(abi.NEW_SCOPE, []int64{}, []string{})\n\n\tthis.relocatable.NewBytecode(abi.BEGIN_STRUCT, []int64{}, []string{\"dpu_set_t\"})\n\tthis.relocatable.NewBytecode(abi.APPEND_INT, []int64{0}, []string{\"foo\"})\n\tthis.relocatable.NewBytecode(abi.END_STRUCT, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenFiniBootstrap() {\n\tthis.relocatable.SwitchLabel(\"__bootstrap\")\n\n\tthis.relocatable.NewBytecode(abi.CALL, []int64{}, []string{\"main\"})\n\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenDirective(directive_ *directive.Directive) {\n\tif directive_.DirectiveType() == directive.INCLUDE {\n\t\tthis.CodegenIncludeDirective(directive_.IncludeDirective())\n\t} else if directive_.DirectiveType() == directive.DEFINE {\n\t\tthis.CodegenDefineDirective(directive_.DefineDirective())\n\t} else {\n\t\terr := errors.New(\"directive type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenIncludeDirective(include_directive *directive.IncludeDirective) {\n}\n\nfunc (this *Codegen) CodegenDefineDirective(define_directive *directive.DefineDirective) {\n\tthis.relocatable.SwitchLabel(\"__bootstrap\")\n\n\tlvalue := define_directive.Lvalue()\n\trvalue := define_directive.Rvalue()\n\n\tif rvalue.ExprType() == expr.PRIMARY {\n\t\tif rvalue.PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER {\n\t\t\terr := errors.New(\"rvalue primary expr type is identifier\")\n\t\t\tpanic(err)\n\t\t} else if rvalue.PrimaryExpr().PrimaryExprType() == expr.NUMBER {\n\t\t\tif lvalue.Attribute() == \"NUM_DPUS\" {\n\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_GLOBAL_INT, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{int64(this.num_dpus)}, []string{})\n\t\t\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t\t\t} else if lvalue.Attribute() == \"NUM_TASKLETS\" {\n\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_GLOBAL_INT, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{int64(this.num_tasklets)}, []string{})\n\t\t\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t\t\t} else if lvalue.Attribute() == \"DATA_PREP_PARAMS\" {\n\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_GLOBAL_INT, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{int64(this.data_prep_params)}, []string{})\n\t\t\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t\t\t} else {\n\t\t\t\trvalue_value, err := strconv.ParseInt(rvalue.PrimaryExpr().Token().Attribute(), 10, 64)\n\t\t\t\tif err != nil {\n\t\t\t\t\tpanic(err)\n\t\t\t\t}\n\n\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_GLOBAL_INT, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{0}, []string{lvalue.Attribute()})\n\t\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{rvalue_value}, []string{})\n\t\t\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t\t\t}\n\t\t} else if rvalue.PrimaryExpr().PrimaryExprType() == expr.STRING {\n\t\t} else if rvalue.PrimaryExpr().PrimaryExprType() == expr.NULLPTR {\n\t\t\terr := errors.New(\"rvalue primary expr type is nullptr\")\n\t\t\tpanic(err)\n\t\t} else if rvalue.PrimaryExpr().PrimaryExprType() == expr.PAREN {\n\t\t\terr := errors.New(\"rvalue primary expr type is paren\")\n\t\t\tpanic(err)\n\t\t} else {\n\t\t\terr := errors.New(\"primary expr type is valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"rvalue expr type is primary\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenDecl(decl_ *decl.Decl) {\n\tif decl_.DeclType() == decl.STRUCT_DEF {\n\t\tthis.CodegenStructDef(decl_.StructDef())\n\t} else if decl_.DeclType() == decl.FUNC_DECL {\n\t\tthis.CodegenFuncDecl(decl_.FuncDecl())\n\t} else if decl_.DeclType() == decl.FUNC_DEF {\n\t\tthis.CodegenFuncDef(decl_.FuncDef())\n\t} else {\n\t\terr := errors.New(\"decl type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenStructDef(struct_def *decl.StructDef) {\n\tthis.relocatable.SwitchLabel(\"__bootstrap\")\n\n\tstruct_name := struct_def.Identifier().Attribute()\n\n\tthis.relocatable.NewBytecode(abi.BEGIN_STRUCT, []int64{}, []string{struct_name})\n\n\tfor i := 0; i < struct_def.Body().BlockStmt().Length(); i++ {\n\t\tstmt_ := struct_def.Body().BlockStmt().Get(i)\n\n\t\ttype_specifier_ := stmt_.VarDeclStmt().TypeSpecifier()\n\t\tfield_name := stmt_.VarDeclStmt().Identifier().Attribute()\n\n\t\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\t\tif type_specifier_.NumStars() == 0 {\n\t\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(\n\t\t\t\tabi.APPEND_VOID,\n\t\t\t\t[]int64{int64(type_specifier_.NumStars())},\n\t\t\t\t[]string{field_name},\n\t\t\t)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\t\tthis.relocatable.NewBytecode(abi.APPEND_CHAR, []int64{int64(type_specifier_.NumStars())}, []string{field_name})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\t\tthis.relocatable.NewBytecode(abi.APPEND_SHORT, []int64{int64(type_specifier_.NumStars())}, []string{field_name})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\t\tthis.relocatable.NewBytecode(abi.APPEND_INT, []int64{int64(type_specifier_.NumStars())}, []string{field_name})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\t\tthis.relocatable.NewBytecode(abi.APPEND_LONG, []int64{int64(type_specifier_.NumStars())}, []string{field_name})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\t\tthis.relocatable.NewBytecode(abi.APPEND_STRUCT, []int64{int64(type_specifier_.NumStars())}, []string{type_specifier_.StructIdentifier().Attribute(), field_name})\n\t\t} else {\n\t\t\terr := errors.New(\"type specifier type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.relocatable.NewBytecode(abi.END_STRUCT, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenFuncDecl(func_decl *decl.FuncDecl) {\n\ttype_specifier_ := func_decl.TypeSpecifier()\n\n\tmethod := new(type_system.Method)\n\n\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitPrimitive(\n\t\t\ttype_system.VOID,\n\t\t\ttype_specifier_.NumStars(),\n\t\t\tfunc_decl.Identifier().Attribute(),\n\t\t)\n\n\t\tmethod.Init(symbol)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitPrimitive(type_system.CHAR, type_specifier_.NumStars(), func_decl.Identifier().Attribute())\n\n\t\tmethod.Init(symbol)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitPrimitive(type_system.SHORT, type_specifier_.NumStars(), func_decl.Identifier().Attribute())\n\n\t\tmethod.Init(symbol)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitPrimitive(type_system.INT, type_specifier_.NumStars(), func_decl.Identifier().Attribute())\n\n\t\tmethod.Init(symbol)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitPrimitive(type_system.LONG, type_specifier_.NumStars(), func_decl.Identifier().Attribute())\n\n\t\tmethod.Init(symbol)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\tsymbol := new(type_system.Symbol)\n\t\tsymbol.InitStruct(type_system.STRUCT, type_specifier_.StructIdentifier().Attribute(), type_specifier_.NumStars(), func_decl.Identifier().Attribute())\n\n\t\tmethod.Init(symbol)\n\t} else {\n\t\terr := errors.New(\"type specifier type is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_system.AddMethod(method)\n\n\tfor i := 0; i < func_decl.ParamList().Length(); i++ {\n\t\tparam := func_decl.ParamList().Get(i)\n\n\t\tif param.TypeSpecifier().TypeSpecifierType() == type_specifier.VOID {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(\n\t\t\t\ttype_system.VOID,\n\t\t\t\tparam.TypeSpecifier().NumStars(),\n\t\t\t\tparam.Identifier().Attribute(),\n\t\t\t)\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.CHAR {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.CHAR, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.SHORT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.SHORT, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.INT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.INT, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.LONG {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.LONG, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.STRUCT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitStruct(type_system.STRUCT, param.TypeSpecifier().StructIdentifier().Attribute(), param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\tmethod.AppendParam(symbol)\n\t\t} else {\n\t\t\terr := errors.New(\"type specifier type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tthis.relocatable.NewFunc(func_decl.Identifier().Attribute())\n}\n\nfunc (this *Codegen) CodegenFuncDef(func_def *decl.FuncDef) {\n\tthis.cur_block_depth = 0\n\n\ttype_specifier_ := func_def.TypeSpecifier()\n\n\tfunc_name := func_def.Identifier().Attribute()\n\n\tif !this.type_system.HasMethod(func_name) {\n\t\tmethod := new(type_system.Method)\n\n\t\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(\n\t\t\t\ttype_system.VOID,\n\t\t\t\ttype_specifier_.NumStars(),\n\t\t\t\tfunc_def.Identifier().Attribute(),\n\t\t\t)\n\n\t\t\tmethod.Init(symbol)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.CHAR, type_specifier_.NumStars(), func_def.Identifier().Attribute())\n\n\t\t\tmethod.Init(symbol)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.SHORT, type_specifier_.NumStars(), func_def.Identifier().Attribute())\n\n\t\t\tmethod.Init(symbol)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.INT, type_specifier_.NumStars(), func_def.Identifier().Attribute())\n\n\t\t\tmethod.Init(symbol)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitPrimitive(type_system.LONG, type_specifier_.NumStars(), func_def.Identifier().Attribute())\n\n\t\t\tmethod.Init(symbol)\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\t\tsymbol := new(type_system.Symbol)\n\t\t\tsymbol.InitStruct(type_system.CHAR, type_specifier_.StructIdentifier().Attribute(), type_specifier_.NumStars(), func_def.Identifier().Attribute())\n\n\t\t\tmethod.Init(symbol)\n\t\t} else {\n\t\t\terr := errors.New(\"type specifier type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.type_system.AddMethod(method)\n\n\t\tfor i := 0; i < func_def.ParamList().Length(); i++ {\n\t\t\tparam := func_def.ParamList().Get(i)\n\n\t\t\tif param.TypeSpecifier().TypeSpecifierType() == type_specifier.VOID {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitPrimitive(\n\t\t\t\t\ttype_system.VOID,\n\t\t\t\t\tparam.TypeSpecifier().NumStars(),\n\t\t\t\t\tparam.Identifier().Attribute(),\n\t\t\t\t)\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.CHAR {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitPrimitive(type_system.CHAR, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.SHORT {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitPrimitive(type_system.SHORT, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.INT {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitPrimitive(type_system.INT, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.LONG {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitPrimitive(type_system.LONG, param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else if param.TypeSpecifier().TypeSpecifierType() == type_specifier.STRUCT {\n\t\t\t\tsymbol := new(type_system.Symbol)\n\t\t\t\tsymbol.InitStruct(type_system.STRUCT, param.TypeSpecifier().StructIdentifier().Attribute(), param.TypeSpecifier().NumStars(), param.Identifier().Attribute())\n\n\t\t\t\tmethod.AppendParam(symbol)\n\t\t\t} else {\n\t\t\t\terr := errors.New(\"type specifier type is not valid\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\n\t\tthis.relocatable.NewFunc(func_def.Identifier().Attribute())\n\t}\n\n\tthis.relocatable.SwitchFunc(func_name)\n\tthis.relocatable.SwitchLabel(func_name)\n\n\tthis.CodegenStmt(func_def.Body())\n}\n\nfunc (this *Codegen) CodegenStmt(stmt_ *stmt.Stmt) {\n\tif stmt_.StmtType() == stmt.EMPTY {\n\t\tthis.CodegenEmptyStmt(stmt_.EmptyStmt())\n\t} else if stmt_.StmtType() == stmt.VAR_DECL {\n\t\tthis.CodegenVarDeclStmt(stmt_.VarDeclStmt())\n\t} else if stmt_.StmtType() == stmt.VAR_DECL_INIT {\n\t\tthis.CodegenVarDeclInitStmt(stmt_.VarDeclInitStmt())\n\t} else if stmt_.StmtType() == stmt.FOR {\n\t\tthis.CodegenForStmt(stmt_.ForStmt())\n\t} else if stmt_.StmtType() == stmt.DPU_FOREACH {\n\t\tthis.CodegenDpuForeachStmt(stmt_.DpuForeachStmt())\n\t} else if stmt_.StmtType() == stmt.WHILE {\n\t\tthis.CodegenWhileStmt(stmt_.WhileStmt())\n\t} else if stmt_.StmtType() == stmt.CONTINUE {\n\t\tthis.CodegenContinueStmt(stmt_.ContinueStmt())\n\t} else if stmt_.StmtType() == stmt.BREAK {\n\t\tthis.CodegenBreakStmt(stmt_.BreakStmt())\n\t} else if stmt_.StmtType() == stmt.IF {\n\t\tthis.CodegenIfStmt(stmt_.IfStmt())\n\t} else if stmt_.StmtType() == stmt.RETURN {\n\t\tthis.CodegenReturnStmt(stmt_.ReturnStmt())\n\t} else if stmt_.StmtType() == stmt.EXPR {\n\t\tthis.CodegenExprStmt(stmt_.ExprStmt())\n\t} else if stmt_.StmtType() == stmt.BLOCK {\n\t\tthis.CodegenBlockStmt(stmt_.BlockStmt())\n\t} else {\n\t\terr := errors.New(\"stmt type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenEmptyStmt(empty_stmt *stmt.EmptyStmt) {\n\tthis.relocatable.NewBytecode(abi.NOP, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenVarDeclStmt(var_decl_stmt *stmt.VarDeclStmt) {\n\ttype_specifier_ := var_decl_stmt.TypeSpecifier()\n\tsymbol_name := var_decl_stmt.Identifier().Attribute()\n\n\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\tif type_specifier_.NumStars() == 0 {\n\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.relocatable.NewBytecode(\n\t\t\tabi.NEW_FAST_VOID,\n\t\t\t[]int64{int64(type_specifier_.NumStars())},\n\t\t\t[]string{symbol_name},\n\t\t)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_CHAR, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_SHORT, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_INT, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_LONG, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_STRUCT, []int64{int64(type_specifier_.NumStars())}, []string{type_specifier_.StructIdentifier().Attribute(), symbol_name})\n\t} else {\n\t\terr := errors.New(\"type specifier type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenVarDeclInitStmt(var_decl_init_stmt *stmt.VarDeclInitStmt) {\n\ttype_specifier_ := var_decl_init_stmt.TypeSpecifier()\n\tsymbol_name := var_decl_init_stmt.Identifier().Attribute()\n\n\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\tif type_specifier_.NumStars() == 0 {\n\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.relocatable.NewBytecode(\n\t\t\tabi.NEW_FAST_VOID,\n\t\t\t[]int64{int64(type_specifier_.NumStars())},\n\t\t\t[]string{symbol_name},\n\t\t)\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_CHAR, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_SHORT, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_INT, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_LONG, []int64{int64(type_specifier_.NumStars())}, []string{symbol_name})\n\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\tthis.relocatable.NewBytecode(abi.NEW_FAST_STRUCT, []int64{int64(type_specifier_.NumStars())}, []string{type_specifier_.StructIdentifier().Attribute(), symbol_name})\n\t} else {\n\t\terr := errors.New(\"type specifier type is not valid\")\n\t\tpanic(err)\n\t}\n\n\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{}, []string{symbol_name})\n\tthis.CodegenExpr(var_decl_init_stmt.Expr())\n\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenForStmt(for_stmt *stmt.ForStmt) {\n\tcondition_label, body_label, end_label := this.relocatable.NewLoop()\n\n\tthis.relocatable.NewBytecode(abi.NEW_SCOPE, []int64{}, []string{})\n\tthis.block_depths[condition_label.Name()] = this.cur_block_depth\n\tthis.cur_block_depth++\n\tthis.CodegenStmt(for_stmt.Initialization())\n\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{condition_label.Name()})\n\n\tthis.relocatable.SwitchLabel(condition_label.Name())\n\tthis.CodegenExpr(for_stmt.Condition())\n\tthis.relocatable.NewBytecode(abi.JUMP_IF_NONZERO, []int64{}, []string{body_label.Name()})\n\tthis.CodegenExpr(for_stmt.Condition())\n\tthis.relocatable.NewBytecode(abi.JUMP_IF_ZERO, []int64{}, []string{end_label.Name()})\n\n\tthis.relocatable.SwitchLabel(body_label.Name())\n\tthis.CodegenStmt(for_stmt.Body())\n\tthis.CodegenStmt(for_stmt.Update())\n\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{condition_label.Name()})\n\n\tthis.relocatable.SwitchLabel(end_label.Name())\n\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n\tthis.cur_block_depth--\n}\n\nfunc (this *Codegen) CodegenDpuForeachStmt(dpu_foreach_stmt *stmt.DpuForeachStmt) {\n\tif dpu_foreach_stmt.Foreach().Get(1).ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"second argument's expr type is not primary\")\n\t\tpanic(err)\n\t} else if dpu_foreach_stmt.Foreach().Get(1).PrimaryExpr().PrimaryExprType() != expr.IDENTIFIER {\n\t\terr := errors.New(\"second argument's primary expr type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tdpu_symbol_name := dpu_foreach_stmt.Foreach().Get(1).PrimaryExpr().Token().Attribute()\n\n\tif dpu_foreach_stmt.Foreach().Get(2).ExprType() != expr.PRIMARY {\n\t\terr := errors.New(\"third argument's expr type is not primary\")\n\t\tpanic(err)\n\t} else if dpu_foreach_stmt.Foreach().Get(2).PrimaryExpr().PrimaryExprType() != expr.IDENTIFIER {\n\t\terr := errors.New(\"third argument's primary expr type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\ti_symbol_name := dpu_foreach_stmt.Foreach().Get(2).PrimaryExpr().Token().Attribute()\n\n\tthis.relocatable.NewBytecode(abi.NEW_SCOPE, []int64{}, []string{})\n\n\tthis.relocatable.NewBytecode(abi.NEW_FAST_INT, []int64{0}, []string{dpu_symbol_name})\n\tthis.relocatable.NewBytecode(abi.NEW_FAST_INT, []int64{0}, []string{i_symbol_name})\n\n\tfor i := 0; i < this.num_dpus; i++ {\n\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{}, []string{dpu_symbol_name})\n\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{int64(i)}, []string{})\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\n\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{}, []string{i_symbol_name})\n\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{int64(i)}, []string{})\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\n\t\tthis.CodegenStmt(dpu_foreach_stmt.Body())\n\t}\n\n\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenWhileStmt(while_stmt *stmt.WhileStmt) {\n\tcondition_label, body_label, end_label := this.relocatable.NewLoop()\n\n\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{condition_label.Name()})\n\n\tthis.relocatable.SwitchLabel(condition_label.Name())\n\tthis.CodegenExpr(while_stmt.Condition())\n\tthis.relocatable.NewBytecode(abi.JUMP_IF_NONZERO, []int64{}, []string{body_label.Name()})\n\tthis.CodegenExpr(while_stmt.Condition())\n\tthis.relocatable.NewBytecode(abi.JUMP_IF_ZERO, []int64{}, []string{end_label.Name()})\n\n\tthis.relocatable.SwitchLabel(body_label.Name())\n\tthis.CodegenStmt(while_stmt.Body())\n\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{condition_label.Name()})\n\n\tthis.relocatable.SwitchLabel(end_label.Name())\n}\n\nfunc (this *Codegen) CodegenContinueStmt(continue_stmt *stmt.ContinueStmt) {\n\tloop_depth := this.block_depths[this.relocatable.CurLoopCondition().Name()]\n\tfor i := 0; i < this.cur_block_depth-loop_depth-1; i++ {\n\t\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n\t}\n\tthis.cur_block_depth = loop_depth\n\n\tthis.relocatable.NewBytecode(\n\t\tabi.JUMP,\n\t\t[]int64{},\n\t\t[]string{this.relocatable.CurLoopCondition().Name()},\n\t)\n}\n\nfunc (this *Codegen) CodegenBreakStmt(break_stmt *stmt.BreakStmt) {\n\tloop_depth := this.block_depths[this.relocatable.CurLoopCondition().Name()]\n\tfor i := 0; i < this.cur_block_depth-loop_depth-1; i++ {\n\t\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n\t}\n\tthis.cur_block_depth = loop_depth\n\n\tthis.relocatable.NewBytecode(\n\t\tabi.JUMP,\n\t\t[]int64{},\n\t\t[]string{this.relocatable.CurLoopEnd().Name()},\n\t)\n}\n\nfunc (this *Codegen) CodegenIfStmt(if_stmt *stmt.IfStmt) {\n\tvar num_branches int\n\tif if_stmt.HasElseBody() {\n\t\tnum_branches = 2 + if_stmt.NumElseIfs()\n\t} else {\n\t\tnum_branches = 1 + if_stmt.NumElseIfs()\n\t}\n\n\tbranches := make([]*abi.Label, 0)\n\tfor i := 0; i < num_branches; i++ {\n\t\tbranch := this.relocatable.NewUnnamedLabel()\n\t\tbranches = append(branches, branch)\n\t}\n\n\tbranch_end := this.relocatable.NewUnnamedLabel()\n\n\tthis.CodegenExpr(if_stmt.IfCondition())\n\tthis.relocatable.NewBytecode(abi.JUMP_IF_NONZERO, []int64{}, []string{branches[0].Name()})\n\n\tfor i := 0; i < if_stmt.NumElseIfs(); i++ {\n\t\tthis.CodegenExpr(if_stmt.ElseIfCondition(i))\n\t\tthis.relocatable.NewBytecode(abi.JUMP_IF_NONZERO, []int64{}, []string{branches[i+1].Name()})\n\t}\n\n\tif if_stmt.HasElseBody() {\n\t\tthis.relocatable.NewBytecode(\n\t\t\tabi.JUMP,\n\t\t\t[]int64{},\n\t\t\t[]string{branches[len(branches)-1].Name()},\n\t\t)\n\t} else {\n\t\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{branch_end.Name()})\n\t}\n\n\tthis.relocatable.SwitchLabel(branches[0].Name())\n\tthis.CodegenStmt(if_stmt.IfBody())\n\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{branch_end.Name()})\n\n\tfor i := 0; i < if_stmt.NumElseIfs(); i++ {\n\t\tthis.relocatable.SwitchLabel(branches[i+1].Name())\n\t\tthis.CodegenStmt(if_stmt.ElseIfBody(i))\n\t\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{branch_end.Name()})\n\t}\n\n\tif if_stmt.HasElseBody() {\n\t\tthis.relocatable.SwitchLabel(branches[len(branches)-1].Name())\n\t\tthis.CodegenStmt(if_stmt.ElseBody())\n\t\tthis.relocatable.NewBytecode(abi.JUMP, []int64{}, []string{branch_end.Name()})\n\t}\n\n\tthis.relocatable.SwitchLabel(branch_end.Name())\n}\n\nfunc (this *Codegen) CodegenReturnStmt(return_stmt *stmt.ReturnStmt) {\n\tif return_stmt.HasValue() {\n\t\tfunc_name := this.relocatable.CurFunc().Name()\n\t\tmethod := this.type_system.Method(func_name)\n\n\t\tif method.Symbol().SymbolType() == type_system.VOID {\n\t\t\tif method.Symbol().NumStars() == 0 {\n\t\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(\n\t\t\t\tabi.NEW_RETURN_VOID,\n\t\t\t\t[]int64{int64(method.Symbol().NumStars())},\n\t\t\t\t[]string{},\n\t\t\t)\n\t\t} else if method.Symbol().SymbolType() == type_system.CHAR {\n\t\t\tthis.relocatable.NewBytecode(abi.NEW_RETURN_CHAR, []int64{int64(method.Symbol().NumStars())}, []string{})\n\t\t} else if method.Symbol().SymbolType() == type_system.SHORT {\n\t\t\tthis.relocatable.NewBytecode(abi.NEW_RETURN_SHORT, []int64{int64(method.Symbol().NumStars())}, []string{})\n\t\t} else if method.Symbol().SymbolType() == type_system.INT {\n\t\t\tthis.relocatable.NewBytecode(abi.NEW_RETURN_INT, []int64{int64(method.Symbol().NumStars())}, []string{})\n\t\t} else if method.Symbol().SymbolType() == type_system.LONG {\n\t\t\tthis.relocatable.NewBytecode(abi.NEW_RETURN_LONG, []int64{int64(method.Symbol().NumStars())}, []string{})\n\t\t} else if method.Symbol().SymbolType() == type_system.STRUCT {\n\t\t\tthis.relocatable.NewBytecode(abi.NEW_RETURN_STRUCT, []int64{int64(method.Symbol().NumStars())}, []string{method.Symbol().StructName()})\n\t\t} else {\n\t\t\terr := errors.New(\"symbol type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.CodegenExpr(return_stmt.Value())\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_RETURN, []int64{}, []string{})\n\t}\n\n\tthis.relocatable.NewBytecode(abi.RETURN, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenExprStmt(expr_stmt *stmt.ExprStmt) {\n\tthis.CodegenExpr(expr_stmt.Expr())\n}\n\nfunc (this *Codegen) CodegenBlockStmt(block_stmt *stmt.BlockStmt) {\n\tthis.relocatable.NewBytecode(abi.NEW_SCOPE, []int64{}, []string{})\n\tthis.block_depths[this.relocatable.CurLabel().Name()] = this.cur_block_depth\n\tthis.cur_block_depth++\n\n\tfor i := 0; i < block_stmt.Length(); i++ {\n\t\tstmt_ := block_stmt.Get(i)\n\t\tthis.CodegenStmt(stmt_)\n\t}\n\n\tthis.relocatable.NewBytecode(abi.DELETE_SCOPE, []int64{}, []string{})\n\tthis.cur_block_depth--\n}\n\nfunc (this *Codegen) CodegenExpr(expr_ *expr.Expr) {\n\tif expr_.ExprType() == expr.PRIMARY {\n\t\tthis.CodegenPrimaryExpr(expr_.PrimaryExpr())\n\t} else if expr_.ExprType() == expr.POSTFIX {\n\t\tthis.CodegenPostfixExpr(expr_.PostfixExpr())\n\t} else if expr_.ExprType() == expr.UNARY {\n\t\tthis.CodegenUnaryExpr(expr_.UnaryExpr())\n\t} else if expr_.ExprType() == expr.MULTIPLICATIVE {\n\t\tthis.CodegenMultiplicativeExpr(expr_.MultiplicativeExpr())\n\t} else if expr_.ExprType() == expr.ADDITIVE {\n\t\tthis.CodegenAdditiveExpr(expr_.AdditiveExpr())\n\t} else if expr_.ExprType() == expr.SHIFT {\n\t\tthis.CodegenShiftExpr(expr_.ShiftExpr())\n\t} else if expr_.ExprType() == expr.RELATIONAL {\n\t\tthis.CodegenRelationalExpr(expr_.RelationalExpr())\n\t} else if expr_.ExprType() == expr.EQUALITY {\n\t\tthis.CodegenEqualityExpr(expr_.EqualityExpr())\n\t} else if expr_.ExprType() == expr.BITWISE_AND {\n\t\tthis.CodegenBitwiseAndExpr(expr_.BitwiseAndExpr())\n\t} else if expr_.ExprType() == expr.BITWISE_XOR {\n\t\tthis.CodegenBitwiseXorExpr(expr_.BitwiseXorExpr())\n\t} else if expr_.ExprType() == expr.BITWISE_OR {\n\t\tthis.CodegenBitwiseOrExpr(expr_.BitwiseOrExpr())\n\t} else if expr_.ExprType() == expr.LOGICAL_AND {\n\t\tthis.CodegenLogicalAndExpr(expr_.LogicalAndExpr())\n\t} else if expr_.ExprType() == expr.LOGICAL_OR {\n\t\tthis.CodegenLogicalOrExpr(expr_.LogicalOrExpr())\n\t} else if expr_.ExprType() == expr.CONDITIONAL {\n\t\tthis.CodegenConditionalExpr(expr_.ConditionalExpr())\n\t} else if expr_.ExprType() == expr.ASSIGNMENT {\n\t\tthis.CodegenAssignmentExpr(expr_.AssignmentExpr())\n\t} else {\n\t\terr := errors.New(\"expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenPrimaryExpr(primary_expr *expr.PrimaryExpr) {\n\tif primary_expr.PrimaryExprType() == expr.IDENTIFIER {\n\t\tsymbol_name := primary_expr.Token().Attribute()\n\n\t\tif symbol_name == \"DPU_XFER_TO_DPU\" {\n\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{0}, []string{})\n\t\t} else if symbol_name == \"DPU_XFER_FROM_DPU\" {\n\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{1}, []string{})\n\t\t} else if symbol_name == \"DPU_MRAM_HEAP_POINTER_NAME\" {\n\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{this.dpu_mram_heap_pointer_name}, []string{})\n\t\t} else if symbol_name == \"DPU_XFER_DEFAULT\" {\n\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{0}, []string{})\n\t\t} else if symbol_name == \"DPU_SYNCHRONOUS\" {\n\t\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{0}, []string{})\n\t\t} else {\n\t\t\tthis.relocatable.NewBytecode(abi.GET_IDENTIFIER, []int64{}, []string{symbol_name})\n\t\t}\n\t} else if primary_expr.PrimaryExprType() == expr.NUMBER {\n\t\tnumber, err := strconv.ParseInt(primary_expr.Token().Attribute(), 10, 64)\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{number}, []string{})\n\t} else if primary_expr.PrimaryExprType() == expr.STRING {\n\t\tstr := primary_expr.Token().Attribute()\n\n\t\tthis.relocatable.NewBytecode(abi.PUSH_STRING, []int64{}, []string{str})\n\t} else if primary_expr.PrimaryExprType() == expr.NULLPTR {\n\t\tthis.relocatable.NewBytecode(abi.PUSH_INT, []int64{0}, []string{})\n\t} else if primary_expr.PrimaryExprType() == expr.PAREN {\n\t\tthis.CodegenExpr(primary_expr.Expr())\n\t} else {\n\t\terr := errors.New(\"primary expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenPostfixExpr(postfix_expr *expr.PostfixExpr) {\n\tif postfix_expr.PostfixExprType() == expr.BRACKET {\n\t\tthis.CodegenExpr(postfix_expr.Base())\n\t\tthis.CodegenExpr(postfix_expr.OffsetExpr())\n\n\t\tthis.relocatable.NewBytecode(abi.GET_SUBSCRIPT, []int64{}, []string{})\n\t} else if postfix_expr.PostfixExprType() == expr.CALL {\n\t\tif postfix_expr.Base().ExprType() != expr.PRIMARY {\n\t\t\terr := errors.New(\"base expr type is not primary\")\n\t\t\tpanic(err)\n\t\t} else if postfix_expr.Base().PrimaryExpr().PrimaryExprType() != expr.IDENTIFIER {\n\t\t\terr := errors.New(\"base primary expr type is not identifier\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tfunc_name := postfix_expr.Base().PrimaryExpr().Token().Attribute()\n\n\t\tif func_name == \"malloc\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.ALLOC, []int64{}, []string{})\n\t\t} else if func_name == \"free\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.FREE, []int64{}, []string{})\n\t\t} else if func_name == \"assert\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.ASSERT, []int64{}, []string{})\n\t\t} else if func_name == \"sqrt\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.SQRT, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_alloc\" {\n\t\t\tfor i := 0; i < this.num_dpus; i++ {\n\t\t\t\tthis.relocatable.NewBytecode(abi.DPU_ALLOC, []int64{int64(i)}, []string{})\n\t\t\t}\n\t\t} else if func_name == \"dpu_load\" {\n\t\t\tfor i := 0; i < this.num_dpus; i++ {\n\t\t\t\tthis.relocatable.NewBytecode(abi.DPU_LOAD, []int64{int64(i)}, []string{this.benchmark})\n\t\t\t}\n\t\t} else if func_name == \"dpu_prepare_xfer\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_PREPARE, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_push_xfer\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_TRANSFER, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_copy_to\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_COPY_TO, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_copy_from\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_COPY_FROM, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_launch\" {\n\t\t\tfor i := 0; i < postfix_expr.ArgList().Length(); i++ {\n\t\t\t\tthis.CodegenExpr(postfix_expr.ArgList().Get(i))\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_LAUNCH, []int64{}, []string{})\n\t\t} else if func_name == \"dpu_free\" {\n\t\t\tthis.relocatable.NewBytecode(abi.DPU_FREE, []int64{}, []string{})\n\t\t} else {\n\t\t\tmethod := this.type_system.Method(func_name)\n\t\t\tparams := method.Params()\n\n\t\t\tfor i, param := range params {\n\t\t\t\targ := postfix_expr.ArgList().Get(i)\n\n\t\t\t\tif param.SymbolType() == type_system.VOID {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_VOID, []int64{int64(param.NumStars())}, []string{param.Name()})\n\t\t\t\t} else if param.SymbolType() == type_system.CHAR {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_CHAR, []int64{int64(param.NumStars())}, []string{param.Name()})\n\t\t\t\t} else if param.SymbolType() == type_system.SHORT {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_SHORT, []int64{int64(param.NumStars())}, []string{param.Name()})\n\t\t\t\t} else if param.SymbolType() == type_system.INT {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_INT, []int64{int64(param.NumStars())}, []string{param.Name()})\n\t\t\t\t} else if param.SymbolType() == type_system.LONG {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_LONG, []int64{int64(param.NumStars())}, []string{param.Name()})\n\t\t\t\t} else if param.SymbolType() == type_system.STRUCT {\n\t\t\t\t\tthis.relocatable.NewBytecode(abi.NEW_ARG_STRUCT, []int64{int64(param.NumStars())}, []string{param.StructName(), param.Name()})\n\t\t\t\t} else {\n\t\t\t\t\terr := errors.New(\"symbol type is not valid\")\n\t\t\t\t\tpanic(err)\n\t\t\t\t}\n\n\t\t\t\tthis.relocatable.NewBytecode(abi.GET_ARG_IDENTIFIER, []int64{0}, []string{param.Name()})\n\t\t\t\tthis.CodegenExpr(arg)\n\t\t\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.CALL, []int64{}, []string{func_name})\n\t\t}\n\t} else if postfix_expr.PostfixExprType() == expr.DOT {\n\t\tfield_name := postfix_expr.OffsetToken().Attribute()\n\n\t\tthis.CodegenExpr(postfix_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.GET_ACCESS, []int64{}, []string{field_name})\n\t} else if postfix_expr.PostfixExprType() == expr.ARROW {\n\t\tfield_name := postfix_expr.OffsetToken().Attribute()\n\n\t\tthis.CodegenExpr(postfix_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.GET_REFERENCE, []int64{}, []string{field_name})\n\t} else if postfix_expr.PostfixExprType() == expr.POSTFIX_PLUS_PLUS {\n\t\tthis.CodegenExpr(postfix_expr.Base())\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_PLUS_PLUS, []int64{}, []string{})\n\t} else if postfix_expr.PostfixExprType() == expr.POSTFIX_MINUS_MINUS {\n\t\tthis.CodegenExpr(postfix_expr.Base())\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_MINUS_MINUS, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"postfix expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenUnaryExpr(unary_expr *expr.UnaryExpr) {\n\tif unary_expr.UnaryExprType() == expr.UNARY_PLUS_PLUS {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_PLUS_PLUS, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.UNARY_MINUS_MINUS {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_MINUS_MINUS, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.AND {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.GET_ADDRESS, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.STAR {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.GET_VALUE, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.PLUS {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\t} else if unary_expr.UnaryExprType() == expr.MINUS {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.NEGATE, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.TILDE {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.TILDE, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.NOT {\n\t\tthis.CodegenExpr(unary_expr.Base())\n\n\t\tthis.relocatable.NewBytecode(abi.LOGICAL_NOT, []int64{}, []string{})\n\t} else if unary_expr.UnaryExprType() == expr.SIZEOF {\n\t\ttype_specifier_ := unary_expr.TypeSpecifier()\n\n\t\tif type_specifier_.TypeSpecifierType() == type_specifier.VOID {\n\t\t\tif type_specifier_.NumStars() == 0 {\n\t\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_VOID, []int64{int64(type_specifier_.NumStars())}, []string{})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.CHAR {\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_CHAR, []int64{int64(type_specifier_.NumStars())}, []string{})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.SHORT {\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_SHORT, []int64{int64(type_specifier_.NumStars())}, []string{})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.INT {\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_INT, []int64{int64(type_specifier_.NumStars())}, []string{})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.LONG {\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_LONG, []int64{int64(type_specifier_.NumStars())}, []string{})\n\t\t} else if type_specifier_.TypeSpecifierType() == type_specifier.STRUCT {\n\t\t\tthis.relocatable.NewBytecode(abi.SIZEOF_STRUCT, []int64{int64(type_specifier_.NumStars())}, []string{type_specifier_.StructIdentifier().Attribute()})\n\t\t} else {\n\t\t\terr := errors.New(\"type specifier type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\terr := errors.New(\"unary expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenMultiplicativeExpr(multiplicative_expr *expr.MultiplicativeExpr) {\n\tthis.CodegenExpr(multiplicative_expr.Loperand())\n\tthis.CodegenExpr(multiplicative_expr.Roperand())\n\n\tif multiplicative_expr.MultiplicativeExprType() == expr.MUL {\n\t\tthis.relocatable.NewBytecode(abi.MUL, []int64{}, []string{})\n\t} else if multiplicative_expr.MultiplicativeExprType() == expr.DIV {\n\t\tthis.relocatable.NewBytecode(abi.DIV, []int64{}, []string{})\n\t} else if multiplicative_expr.MultiplicativeExprType() == expr.MOD {\n\t\tthis.relocatable.NewBytecode(abi.MOD, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"multiplicative expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenAdditiveExpr(additive_expr *expr.AdditiveExpr) {\n\tthis.CodegenExpr(additive_expr.Loperand())\n\tthis.CodegenExpr(additive_expr.Roperand())\n\n\tif additive_expr.AdditiveExprType() == expr.ADD {\n\t\tthis.relocatable.NewBytecode(abi.ADD, []int64{}, []string{})\n\t} else if additive_expr.AdditiveExprType() == expr.SUB {\n\t\tthis.relocatable.NewBytecode(abi.SUB, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"additive expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenShiftExpr(shift_expr *expr.ShiftExpr) {\n\tthis.CodegenExpr(shift_expr.Loperand())\n\tthis.CodegenExpr(shift_expr.Roperand())\n\n\tif shift_expr.ShiftExprType() == expr.LSHIFT {\n\t\tthis.relocatable.NewBytecode(abi.LSHIFT, []int64{}, []string{})\n\t} else if shift_expr.ShiftExprType() == expr.RSHIFT {\n\t\tthis.relocatable.NewBytecode(abi.RSHIFT, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"shift expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenRelationalExpr(relational_expr *expr.RelationalExpr) {\n\tthis.CodegenExpr(relational_expr.Loperand())\n\tthis.CodegenExpr(relational_expr.Roperand())\n\n\tif relational_expr.RelationalExprType() == expr.LESS {\n\t\tthis.relocatable.NewBytecode(abi.LESS, []int64{}, []string{})\n\t} else if relational_expr.RelationalExprType() == expr.LESS_EQ {\n\t\tthis.relocatable.NewBytecode(abi.LESS_EQ, []int64{}, []string{})\n\t} else if relational_expr.RelationalExprType() == expr.GREATER {\n\t\tthis.relocatable.NewBytecode(abi.GREATER, []int64{}, []string{})\n\t} else if relational_expr.RelationalExprType() == expr.GREATER_EQ {\n\t\tthis.relocatable.NewBytecode(abi.GREATER_EQ, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"relational expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenEqualityExpr(equality_expr *expr.EqualityExpr) {\n\tthis.CodegenExpr(equality_expr.Loperand())\n\tthis.CodegenExpr(equality_expr.Roperand())\n\n\tif equality_expr.EqualityExprType() == expr.EQ {\n\t\tthis.relocatable.NewBytecode(abi.EQ, []int64{}, []string{})\n\t} else if equality_expr.EqualityExprType() == expr.NOT_EQ {\n\t\tthis.relocatable.NewBytecode(abi.NOT_EQ, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"equality expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *Codegen) CodegenBitwiseAndExpr(bitwise_and_expr *expr.BitwiseAndExpr) {\n\tthis.CodegenExpr(bitwise_and_expr.Loperand())\n\tthis.CodegenExpr(bitwise_and_expr.Roperand())\n\n\tthis.relocatable.NewBytecode(abi.BITWISE_AND, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenBitwiseXorExpr(bitwise_xor_expr *expr.BitwiseXorExpr) {\n\tthis.CodegenExpr(bitwise_xor_expr.Loperand())\n\tthis.CodegenExpr(bitwise_xor_expr.Roperand())\n\n\tthis.relocatable.NewBytecode(abi.BITWISE_XOR, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenBitwiseOrExpr(bitwise_or_expr *expr.BitwiseOrExpr) {\n\tthis.CodegenExpr(bitwise_or_expr.Loperand())\n\tthis.CodegenExpr(bitwise_or_expr.Roperand())\n\n\tthis.relocatable.NewBytecode(abi.BITWISE_OR, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenLogicalAndExpr(logical_and_expr *expr.LogicalAndExpr) {\n\tthis.CodegenExpr(logical_and_expr.Loperand())\n\tthis.CodegenExpr(logical_and_expr.Roperand())\n\n\tthis.relocatable.NewBytecode(abi.LOGICAL_AND, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenLogicalOrExpr(logical_or_expr *expr.LogicalOrExpr) {\n\tthis.CodegenExpr(logical_or_expr.Loperand())\n\tthis.CodegenExpr(logical_or_expr.Roperand())\n\n\tthis.relocatable.NewBytecode(abi.LOGICAL_OR, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenConditionalExpr(conditional_expr *expr.ConditionalExpr) {\n\tthis.CodegenExpr(conditional_expr.ConditionalExpr())\n\tthis.CodegenExpr(conditional_expr.TrueExpr())\n\tthis.CodegenExpr(conditional_expr.FalseExpr())\n\n\tthis.relocatable.NewBytecode(abi.CONDITIONAL, []int64{}, []string{})\n}\n\nfunc (this *Codegen) CodegenAssignmentExpr(assignment_expr *expr.AssignmentExpr) {\n\tthis.CodegenExpr(assignment_expr.Lvalue())\n\tthis.CodegenExpr(assignment_expr.Rvalue())\n\n\tif assignment_expr.AssignmentExprType() == expr.ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.STAR_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_STAR, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.DIV_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_DIV, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.MOD_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_MOD, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.PLUS_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_ADD, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.MINUS_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_SUB, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.LSHIFT_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_LSHIFT, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.RSHIFT_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_RSHIFT, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.AND_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_BITWISE_AND, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.CARET_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_BITWISE_XOR, []int64{}, []string{})\n\t} else if assignment_expr.AssignmentExprType() == expr.OR_ASSIGN {\n\t\tthis.relocatable.NewBytecode(abi.ASSIGN_BITWISE_OR, []int64{}, []string{})\n\t} else {\n\t\terr := errors.New(\"assignment expr type is not valid\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/codegen/type_system/method.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype Method struct {\n\tsymbol *Symbol\n\tparams []*Symbol\n}\n\nfunc (this *Method) Init(symbol *Symbol) {\n\tthis.symbol = symbol\n\tthis.params = make([]*Symbol, 0)\n}\n\nfunc (this *Method) Symbol() *Symbol {\n\treturn this.symbol\n}\n\nfunc (this *Method) HasParam(param_name string) bool {\n\tfor _, param := range this.params {\n\t\tif param.Name() == param_name {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Method) Param(param_name string) *Symbol {\n\tif !this.HasParam(param_name) {\n\t\terr_msg := fmt.Sprintf(\"param (%s) is not found\", param_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor _, param := range this.params {\n\t\tif param.Name() == param_name {\n\t\t\treturn param\n\t\t}\n\t}\n\treturn nil\n}\n\nfunc (this *Method) Params() []*Symbol {\n\treturn this.params\n}\n\nfunc (this *Method) AppendParam(param *Symbol) {\n\tthis.params = append(this.params, param)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/codegen/type_system/symbol.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n)\n\ntype SymbolType int\n\nconst (\n\tVOID SymbolType = iota\n\tCHAR\n\tSHORT\n\tINT\n\tLONG\n\tSTRING\n\tSTRUCT\n)\n\ntype Symbol struct {\n\tsymbol_type SymbolType\n\tstruct_name *string\n\tnum_stars   int\n\n\tname string\n}\n\nfunc (this *Symbol) InitPrimitive(symbol_type SymbolType, num_stars int, name string) {\n\tif symbol_type == STRUCT {\n\t\terr := errors.New(\"symbol type is struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.symbol_type = symbol_type\n\tthis.struct_name = nil\n\tthis.num_stars = num_stars\n\tthis.name = name\n}\n\nfunc (this *Symbol) InitStruct(\n\tsymbol_type SymbolType,\n\tstruct_name string,\n\tnum_stars int,\n\tname string,\n) {\n\tif symbol_type != STRUCT {\n\t\terr := errors.New(\"symbol type is not struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.symbol_type = symbol_type\n\n\tthis.struct_name = new(string)\n\t*this.struct_name = struct_name\n\n\tthis.num_stars = num_stars\n\tthis.name = name\n}\n\nfunc (this *Symbol) SymbolType() SymbolType {\n\treturn this.symbol_type\n}\n\nfunc (this *Symbol) StructName() string {\n\tif this.struct_name == nil {\n\t\terr := errors.New(\"struct name == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.struct_name\n}\n\nfunc (this *Symbol) NumStars() int {\n\treturn this.num_stars\n}\n\nfunc (this *Symbol) Name() string {\n\treturn this.name\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/codegen/type_system/type_system.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype TypeSystem struct {\n\tmethods map[string]*Method\n}\n\nfunc (this *TypeSystem) Init() {\n\tthis.methods = make(map[string]*Method)\n}\n\nfunc (this *TypeSystem) HasMethod(method_name string) bool {\n\t_, found := this.methods[method_name]\n\treturn found\n}\n\nfunc (this *TypeSystem) Method(method_name string) *Method {\n\tif !this.HasMethod(method_name) {\n\t\terr_msg := fmt.Sprintf(\"method (%s) is not found\", method_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\treturn this.methods[method_name]\n}\n\nfunc (this *TypeSystem) AddMethod(method *Method) {\n\tthis.methods[method.Symbol().Name()] = method\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/interpreter.go",
    "content": "package interpreter\n\nimport (\n\t\"path/filepath\"\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/host/interpreter/codegen\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Interpreter struct {\n\troot_dirpath     string\n\tbin_dirpath      string\n\tbenchmark        string\n\tnum_dpus         int\n\tnum_tasklets     int\n\tdata_prep_params int\n\n\tdpu_mram_heap_pointer_name int64\n\n\tbinary *abi.Binary\n}\n\nfunc (this *Interpreter) Init(\n\tcommand_line_parser *misc.CommandLineParser,\n\tdpu_mram_heap_pointer_name int64,\n) {\n\tthis.root_dirpath = command_line_parser.StringParameter(\"root_dirpath\")\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_dpus = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\n\tthis.num_tasklets = int(command_line_parser.IntParameter(\"num_tasklets\"))\n\n\tthis.data_prep_params = int(command_line_parser.IntParameter(\"data_prep_params\"))\n\n\tthis.dpu_mram_heap_pointer_name = dpu_mram_heap_pointer_name\n\n\tthis.binary = new(abi.Binary)\n\tthis.binary.Init(this.benchmark, this.num_dpus, this.num_tasklets)\n}\n\nfunc (this *Interpreter) Interpret() {\n\tthis.Lex()\n\tthis.Parse()\n\tthis.Codegen()\n\n\tbinary_path := filepath.Join(this.bin_dirpath, \"bytecode.txt\")\n\tthis.binary.Dump(binary_path)\n}\n\nfunc (this *Interpreter) Lex() {\n\tsource_code := this.FindSourceCode()\n\n\tlexer_ := new(lexer.Lexer)\n\tlexer_.Init()\n\n\ttoken_stream := lexer_.Lex(source_code)\n\tthis.binary.SetTokenStream(token_stream)\n}\n\nfunc (this *Interpreter) Parse() {\n\tparser_ := new(parser.Parser)\n\tparser_.Init()\n\n\tast := parser_.Parse(this.binary.TokenStream())\n\tthis.binary.SetAst(ast)\n}\n\nfunc (this *Interpreter) Codegen() {\n\tcodegen_ := new(codegen.Codegen)\n\tcodegen_.Init(\n\t\tthis.benchmark,\n\t\tthis.num_dpus,\n\t\tthis.num_tasklets,\n\t\tthis.data_prep_params,\n\t\tthis.dpu_mram_heap_pointer_name,\n\t)\n\n\trelocatable := codegen_.Codegen(this.binary.Ast())\n\tthis.binary.SetRelocatable(relocatable)\n}\n\nfunc (this *Interpreter) FindSourceCode() string {\n\tbenchmark_dirpath := filepath.Join(this.root_dirpath, \"benchmark\", this.benchmark)\n\tc_path := filepath.Join(benchmark_dirpath, \"host\", \"app.c\")\n\treturn c_path\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/keyword_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype KeywordFactory struct {\n\tkeywords map[string]TokenType\n}\n\nfunc (this *KeywordFactory) Init() {\n\tthis.keywords = make(map[string]TokenType)\n}\n\nfunc (this *KeywordFactory) AddKeyword(keyword string, token_type TokenType) {\n\tthis.keywords[keyword] = token_type\n}\n\nfunc (this *KeywordFactory) IsTokenizable(word string) bool {\n\t_, found := this.keywords[word]\n\treturn found\n}\n\nfunc (this *KeywordFactory) Tokenize(word string) *Token {\n\tif _, found := this.keywords[word]; !found {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\ttoken_type := this.keywords[word]\n\n\ttoken := new(Token)\n\ttoken.Init(token_type, \"\")\n\treturn token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/lexer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"strings\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Lexer struct {\n\ttokenizer *Tokenizer\n}\n\nfunc (this *Lexer) Init() {\n\tthis.tokenizer = new(Tokenizer)\n\tthis.tokenizer.Init()\n}\n\nfunc (this *Lexer) Lex(path string) *TokenStream {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tfor _, line := range file_scanner.ReadLines() {\n\t\tline = strings.Replace(line, \"\\n\", \"\", -1)\n\t\ttoken_stream.Merge(this.Tokenize(line))\n\t}\n\n\tend_of_file := new(Token)\n\tend_of_file.Init(END_OF_FILE, \"\")\n\n\ttoken_stream.Append(end_of_file)\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) Tokenize(line string) *TokenStream {\n\ttoken_stream := new(TokenStream)\n\ttoken_stream.Init()\n\n\tprev_pos := 0\n\tfor prev_pos < len(line) {\n\t\tif token_stream.Length() > 0 {\n\t\t\tlast_token := token_stream.Get(token_stream.Length() - 1)\n\n\t\t\tif last_token.TokenType() == INCLUDE {\n\t\t\t\ttoken := this.FindHeader(line, prev_pos)\n\t\t\t\ttoken_stream.Append(token)\n\n\t\t\t\treturn token_stream\n\t\t\t}\n\t\t}\n\n\t\ttoken, length := this.FindTokenWithMaxLength(line, prev_pos)\n\n\t\tif token != nil {\n\t\t\ttoken_stream.Append(token)\n\t\t}\n\n\t\tprev_pos += length\n\t}\n\n\treturn token_stream\n}\n\nfunc (this *Lexer) FindHeader(line string, prev_pos int) *Token {\n\tfor this.IsWhiteSpace(string(line[prev_pos])) {\n\t\tprev_pos++\n\t}\n\n\tword := line[prev_pos:]\n\ttoken := this.tokenizer.Tokenize(word)\n\treturn token\n}\n\nfunc (this *Lexer) FindTokenWithMaxLength(line string, prev_pos int) (*Token, int) {\n\tif prev_pos < 0 {\n\t\terr := errors.New(\"prev pos < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.IsWhiteSpace(string(line[prev_pos])) {\n\t\treturn nil, 1\n\t}\n\n\tif this.IsQuote(string(line[prev_pos])) {\n\t\tnext_quote_pos := this.FindNextQuote(line, prev_pos+1)\n\n\t\tword := line[prev_pos : next_quote_pos+1]\n\n\t\ttoken := this.tokenizer.Tokenize(word)\n\n\t\treturn token, next_quote_pos - prev_pos + 1\n\t}\n\n\tfor i := prev_pos + 1; i <= len(line); i++ {\n\t\tword := line[prev_pos:i]\n\n\t\tif i+1 <= len(line) {\n\t\t\tnext_word := line[prev_pos : i+1]\n\n\t\t\tif this.tokenizer.IsTokenizable(word) && !this.tokenizer.IsTokenizable(next_word) {\n\t\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\t\treturn token, i - prev_pos\n\t\t\t}\n\t\t} else {\n\t\t\ttoken := this.tokenizer.Tokenize(word)\n\t\t\treturn token, i - prev_pos\n\t\t}\n\t}\n\n\terr := errors.New(\"line is not further tokenizable\")\n\tpanic(err)\n}\n\nfunc (this *Lexer) IsWhiteSpace(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \" \" || word == \"\\t\" || word == \"\\n\"\n}\n\nfunc (this *Lexer) IsQuote(word string) bool {\n\tif len(word) != 1 {\n\t\terr := errors.New(\"word size != 1\")\n\t\tpanic(err)\n\t}\n\n\treturn word == \"\\\"\"\n}\n\nfunc (this *Lexer) FindNextQuote(line string, pos int) int {\n\tfor i := pos; i < len(line); i++ {\n\t\tif this.IsQuote(string(line[i])) {\n\t\t\treturn i\n\t\t}\n\t}\n\n\terr := errors.New(\"line does not have the next quote\")\n\tpanic(err)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/regex.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n\t\"regexp\"\n)\n\ntype Regex struct {\n\texpr  string\n\tregex *regexp.Regexp\n\n\ttoken_type TokenType\n}\n\nfunc (this *Regex) Init(expr string, token_type TokenType) {\n\tthis.expr = expr\n\n\tregex, err := regexp.Compile(expr)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\tthis.regex = regex\n\n\tthis.token_type = token_type\n}\n\nfunc (this *Regex) Expr() string {\n\treturn this.expr\n}\n\nfunc (this *Regex) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Regex) IsTokenizable(word string) bool {\n\treturn this.regex.MatchString(word)\n}\n\nfunc (this *Regex) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not matched\")\n\t\tpanic(err)\n\t}\n\n\ttoken := new(Token)\n\ttoken.Init(this.token_type, word)\n\treturn token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/regex_factory.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype RegexFactory struct {\n\tregexes []*Regex\n}\n\nfunc (this *RegexFactory) Init() {\n\tthis.regexes = make([]*Regex, 0)\n}\n\nfunc (this *RegexFactory) HasRegex(expr string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.Expr() == expr {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) AddRegex(expr string, token_type TokenType) {\n\tif this.HasRegex(expr) {\n\t\terr := errors.New(\"regex already exists\")\n\t\tpanic(err)\n\t}\n\n\tregex := new(Regex)\n\tregex.Init(expr, token_type)\n\n\tthis.regexes = append(this.regexes, regex)\n}\n\nfunc (this *RegexFactory) IsTokenizable(word string) bool {\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *RegexFactory) Tokenize(word string) *Token {\n\tif !this.IsTokenizable(word) {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n\n\tfor _, regex := range this.regexes {\n\t\tif regex.IsTokenizable(word) {\n\t\t\ttoken := new(Token)\n\t\t\ttoken.Init(regex.TokenType(), word)\n\t\t\treturn token\n\t\t}\n\t}\n\n\treturn nil\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/token.go",
    "content": "package lexer\n\ntype TokenType int\n\nconst (\n\tEND_OF_FILE TokenType = iota\n\n\tIDENTIFIER\n\tNUMBER\n\tSTRING\n\tHEADER\n\n\tINCLUDE\n\tDEFINE\n\tIFNDEF\n\tIFDEF\n\tBEGINIF\n\tENDIF\n\n\tBREAK\n\tCHAR\n\tCONTINUE\n\tELSE\n\tFOR\n\tIF\n\tINT\n\tLONG\n\tNULL\n\tRETURN\n\tSHORT\n\tSIZEOF\n\tSTRUCT\n\tVOID\n\tWHILE\n\n\tLPAREN\n\tRPAREN\n\tLBRACKET\n\tRBRACKET\n\tLBRACE\n\tRBRACE\n\n\tLESS\n\tLESS_EQ\n\tGREATER\n\tGREATER_EQ\n\tEQ\n\tNOT_EQ\n\n\tPLUS\n\tPLUS_PLUS\n\tMINUS\n\tMINUS_MINUS\n\tSTAR\n\tDIV\n\tMOD\n\n\tLSHIFT\n\tRSHIFT\n\n\tAND\n\tAND_AND\n\tOR\n\tOR_OR\n\tCARET\n\tNOT\n\tTILDE\n\n\tQUESTION\n\tSEMI\n\tCOLON\n\tCOMMA\n\n\tASSIGN\n\tPLUS_ASSIGN\n\tMINUS_ASSIGN\n\tSTAR_ASSIGN\n\tDIV_ASSIGN\n\tMOD_ASSIGN\n\tLSHIFT_ASSIGN\n\tRSHIFT_ASSIGN\n\tAND_ASSIGN\n\tOR_ASSIGN\n\tCARET_ASSIGN\n\n\tARROW\n\tDOT\n)\n\ntype Token struct {\n\ttoken_type TokenType\n\tattribute  string\n}\n\nfunc (this *Token) Init(token_type TokenType, attribute string) {\n\tthis.token_type = token_type\n\tthis.attribute = attribute\n}\n\nfunc (this *Token) TokenType() TokenType {\n\treturn this.token_type\n}\n\nfunc (this *Token) Attribute() string {\n\treturn this.attribute\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/token_stream.go",
    "content": "package lexer\n\ntype TokenStream struct {\n\ttokens []*Token\n}\n\nfunc (this *TokenStream) Init() {\n\tthis.tokens = make([]*Token, 0)\n}\n\nfunc (this *TokenStream) Length() int {\n\treturn len(this.tokens)\n}\n\nfunc (this *TokenStream) Get(pos int) *Token {\n\treturn this.tokens[pos]\n}\n\nfunc (this *TokenStream) Append(token *Token) {\n\tthis.tokens = append(this.tokens, token)\n}\n\nfunc (this *TokenStream) Merge(token_stream *TokenStream) {\n\tfor i := 0; i < token_stream.Length(); i++ {\n\t\tthis.Append(token_stream.Get(i))\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/lexer/tokenizer.go",
    "content": "package lexer\n\nimport (\n\t\"errors\"\n)\n\ntype Tokenizer struct {\n\tkeyword_factory *KeywordFactory\n\tregex_factory   *RegexFactory\n}\n\nfunc (this *Tokenizer) Init() {\n\tthis.InitKeywordFactory()\n\tthis.InitRegexFactory()\n}\n\nfunc (this *Tokenizer) InitKeywordFactory() {\n\tthis.keyword_factory = new(KeywordFactory)\n\tthis.keyword_factory.Init()\n\n\tthis.keyword_factory.AddKeyword(\"#include\", INCLUDE)\n\tthis.keyword_factory.AddKeyword(\"#define\", DEFINE)\n\tthis.keyword_factory.AddKeyword(\"#ifndef\", IFNDEF)\n\tthis.keyword_factory.AddKeyword(\"#ifdef\", IFDEF)\n\tthis.keyword_factory.AddKeyword(\"#if\", BEGINIF)\n\tthis.keyword_factory.AddKeyword(\"#endif\", ENDIF)\n\n\tthis.keyword_factory.AddKeyword(\"break\", BREAK)\n\tthis.keyword_factory.AddKeyword(\"char\", CHAR)\n\tthis.keyword_factory.AddKeyword(\"continue\", CONTINUE)\n\tthis.keyword_factory.AddKeyword(\"else\", ELSE)\n\tthis.keyword_factory.AddKeyword(\"for\", FOR)\n\tthis.keyword_factory.AddKeyword(\"if\", IF)\n\tthis.keyword_factory.AddKeyword(\"int\", INT)\n\tthis.keyword_factory.AddKeyword(\"long\", LONG)\n\tthis.keyword_factory.AddKeyword(\"NULL\", NULL)\n\tthis.keyword_factory.AddKeyword(\"return\", RETURN)\n\tthis.keyword_factory.AddKeyword(\"short\", SHORT)\n\tthis.keyword_factory.AddKeyword(\"sizeof\", SIZEOF)\n\tthis.keyword_factory.AddKeyword(\"struct\", STRUCT)\n\tthis.keyword_factory.AddKeyword(\"void\", VOID)\n\tthis.keyword_factory.AddKeyword(\"while\", WHILE)\n\n\tthis.keyword_factory.AddKeyword(\"(\", LPAREN)\n\tthis.keyword_factory.AddKeyword(\")\", RPAREN)\n\tthis.keyword_factory.AddKeyword(\"[\", LBRACKET)\n\tthis.keyword_factory.AddKeyword(\"]\", RBRACKET)\n\tthis.keyword_factory.AddKeyword(\"{\", LBRACE)\n\tthis.keyword_factory.AddKeyword(\"}\", RBRACE)\n\n\tthis.keyword_factory.AddKeyword(\"<\", LESS)\n\tthis.keyword_factory.AddKeyword(\"<=\", LESS_EQ)\n\tthis.keyword_factory.AddKeyword(\">\", GREATER)\n\tthis.keyword_factory.AddKeyword(\">=\", GREATER_EQ)\n\tthis.keyword_factory.AddKeyword(\"==\", EQ)\n\tthis.keyword_factory.AddKeyword(\"!=\", NOT_EQ)\n\n\tthis.keyword_factory.AddKeyword(\"+\", PLUS)\n\tthis.keyword_factory.AddKeyword(\"++\", PLUS_PLUS)\n\tthis.keyword_factory.AddKeyword(\"-\", MINUS)\n\tthis.keyword_factory.AddKeyword(\"--\", MINUS_MINUS)\n\tthis.keyword_factory.AddKeyword(\"*\", STAR)\n\tthis.keyword_factory.AddKeyword(\"/\", DIV)\n\tthis.keyword_factory.AddKeyword(\"%\", MOD)\n\n\tthis.keyword_factory.AddKeyword(\"<<\", LSHIFT)\n\tthis.keyword_factory.AddKeyword(\">>\", RSHIFT)\n\n\tthis.keyword_factory.AddKeyword(\"&\", AND)\n\tthis.keyword_factory.AddKeyword(\"&&\", AND_AND)\n\tthis.keyword_factory.AddKeyword(\"|\", OR)\n\tthis.keyword_factory.AddKeyword(\"||\", OR_OR)\n\tthis.keyword_factory.AddKeyword(\"^\", CARET)\n\tthis.keyword_factory.AddKeyword(\"!\", NOT)\n\tthis.keyword_factory.AddKeyword(\"~\", TILDE)\n\n\tthis.keyword_factory.AddKeyword(\"?\", QUESTION)\n\tthis.keyword_factory.AddKeyword(\";\", SEMI)\n\tthis.keyword_factory.AddKeyword(\":\", COLON)\n\tthis.keyword_factory.AddKeyword(\",\", COMMA)\n\n\tthis.keyword_factory.AddKeyword(\"=\", ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"+=\", PLUS_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"-=\", MINUS_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"*=\", STAR_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"/=\", DIV_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"%=\", MOD_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"<<=\", LSHIFT_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\">>=\", RSHIFT_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"&=\", AND_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"|=\", OR_ASSIGN)\n\tthis.keyword_factory.AddKeyword(\"^=\", CARET_ASSIGN)\n\n\tthis.keyword_factory.AddKeyword(\"->\", ARROW)\n\tthis.keyword_factory.AddKeyword(\".\", DOT)\n}\n\nfunc (this *Tokenizer) InitRegexFactory() {\n\tthis.regex_factory = new(RegexFactory)\n\tthis.regex_factory.Init()\n\n\tthis.regex_factory.AddRegex(\"^([A-Za-z_])([A-Za-z0-9_]*)$\", IDENTIFIER)\n\tthis.regex_factory.AddRegex(\"^([0-9]+)$\", NUMBER)\n\tthis.regex_factory.AddRegex(\"^\\\"([A-Za-z0-9/_.])*\\\"$\", STRING)\n\tthis.regex_factory.AddRegex(\"^<([A-Za-z0-9/_.]*)>$\", HEADER)\n}\n\nfunc (this *Tokenizer) IsTokenizable(word string) bool {\n\treturn this.keyword_factory.IsTokenizable(word) || this.regex_factory.IsTokenizable(word)\n}\n\nfunc (this *Tokenizer) Tokenize(word string) *Token {\n\tif this.keyword_factory.IsTokenizable(word) {\n\t\treturn this.keyword_factory.Tokenize(word)\n\t} else if this.regex_factory.IsTokenizable(word) {\n\t\treturn this.regex_factory.Tokenize(word)\n\t} else {\n\t\terr := errors.New(\"word is not tokenizable\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/ast.go",
    "content": "package parser\n\ntype Ast struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *Ast) Init(stack_items []*StackItem) {\n\tthis.stack_items = stack_items\n}\n\nfunc (this *Ast) Length() int {\n\treturn len(this.stack_items)\n}\n\nfunc (this *Ast) Get(pos int) *StackItem {\n\treturn this.stack_items[pos]\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/decl/decl.go",
    "content": "package decl\n\ntype DeclType int\n\nconst (\n\tSTRUCT_DEF DeclType = iota\n\tFUNC_DECL\n\tFUNC_DEF\n)\n\ntype Decl struct {\n\tdecl_type DeclType\n\n\tstruct_def *StructDef\n\tfunc_decl  *FuncDecl\n\tfunc_def   *FuncDef\n}\n\nfunc (this *Decl) InitStructDef(struct_def *StructDef) {\n\tthis.decl_type = STRUCT_DEF\n\n\tthis.struct_def = struct_def\n}\n\nfunc (this *Decl) InitFuncDecl(func_decl *FuncDecl) {\n\tthis.decl_type = FUNC_DECL\n\n\tthis.func_decl = func_decl\n}\n\nfunc (this *Decl) InitFuncDef(func_def *FuncDef) {\n\tthis.decl_type = FUNC_DEF\n\n\tthis.func_def = func_def\n}\n\nfunc (this *Decl) DeclType() DeclType {\n\treturn this.decl_type\n}\n\nfunc (this *Decl) StructDef() *StructDef {\n\treturn this.struct_def\n}\n\nfunc (this *Decl) FuncDecl() *FuncDecl {\n\treturn this.func_decl\n}\n\nfunc (this *Decl) FuncDef() *FuncDef {\n\treturn this.func_def\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/decl/func_decl.go",
    "content": "package decl\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/param_list\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype FuncDecl struct {\n\ttype_specifier *type_specifier.TypeSpecifier\n\tidentifier     *lexer.Token\n\tparam_list     *param_list.ParamList\n}\n\nfunc (this *FuncDecl) Init(\n\ttype_specifier *type_specifier.TypeSpecifier,\n\tidentifier *lexer.Token,\n\tparam_list *param_list.ParamList,\n) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier = type_specifier\n\tthis.identifier = identifier\n\tthis.param_list = param_list\n}\n\nfunc (this *FuncDecl) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *FuncDecl) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n\nfunc (this *FuncDecl) ParamList() *param_list.ParamList {\n\treturn this.param_list\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/decl/func_def.go",
    "content": "package decl\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/param_list\"\n\t\"uPIMulator/src/host/interpreter/parser/stmt\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype FuncDef struct {\n\ttype_specifier *type_specifier.TypeSpecifier\n\tidentifier     *lexer.Token\n\tparam_list     *param_list.ParamList\n\tbody           *stmt.Stmt\n}\n\nfunc (this *FuncDef) Init(\n\ttype_specifier *type_specifier.TypeSpecifier,\n\tidentifier *lexer.Token,\n\tparam_list *param_list.ParamList,\n\tbody *stmt.Stmt,\n) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t} else if body.StmtType() != stmt.BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier = type_specifier\n\tthis.identifier = identifier\n\tthis.param_list = param_list\n\tthis.body = body\n}\n\nfunc (this *FuncDef) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *FuncDef) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n\nfunc (this *FuncDef) ParamList() *param_list.ParamList {\n\treturn this.param_list\n}\n\nfunc (this *FuncDef) Body() *stmt.Stmt {\n\treturn this.body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/decl/struct_def.go",
    "content": "package decl\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/stmt\"\n)\n\ntype StructDef struct {\n\tidentifier *lexer.Token\n\tbody       *stmt.Stmt\n}\n\nfunc (this *StructDef) Init(identifier *lexer.Token, body *stmt.Stmt) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t} else if body.StmtType() != stmt.BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.identifier = identifier\n\tthis.body = body\n}\n\nfunc (this *StructDef) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n\nfunc (this *StructDef) Body() *stmt.Stmt {\n\treturn this.body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/directive/define_directive.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype DefineDirective struct {\n\tlvalue *lexer.Token\n\trvalue *expr.Expr\n}\n\nfunc (this *DefineDirective) Init(lvalue *lexer.Token, rvalue *expr.Expr) {\n\tif lvalue.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"lvalue's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.lvalue = lvalue\n\tthis.rvalue = rvalue\n}\n\nfunc (this *DefineDirective) Lvalue() *lexer.Token {\n\treturn this.lvalue\n}\n\nfunc (this *DefineDirective) Rvalue() *expr.Expr {\n\treturn this.rvalue\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/directive/directive.go",
    "content": "package directive\n\ntype DirectiveType int\n\nconst (\n\tINCLUDE DirectiveType = iota\n\tDEFINE\n)\n\ntype Directive struct {\n\tdirective_type DirectiveType\n\n\tinclude_directive *IncludeDirective\n\tdefine_directive  *DefineDirective\n}\n\nfunc (this *Directive) InitIncludeDirective(include_directive *IncludeDirective) {\n\tthis.directive_type = INCLUDE\n\n\tthis.include_directive = include_directive\n}\n\nfunc (this *Directive) InitDefineDirective(define_directive *DefineDirective) {\n\tthis.directive_type = DEFINE\n\n\tthis.define_directive = define_directive\n}\n\nfunc (this *Directive) DirectiveType() DirectiveType {\n\treturn this.directive_type\n}\n\nfunc (this *Directive) IncludeDirective() *IncludeDirective {\n\treturn this.include_directive\n}\n\nfunc (this *Directive) DefineDirective() *DefineDirective {\n\treturn this.define_directive\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/directive/include_directive.go",
    "content": "package directive\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype IncludeDirective struct {\n\theader *lexer.Token\n}\n\nfunc (this *IncludeDirective) Init(header *lexer.Token) {\n\tif header.TokenType() != lexer.HEADER {\n\t\terr := errors.New(\"header's token type is not header\")\n\t\tpanic(err)\n\t}\n\n\tthis.header = header\n}\n\nfunc (this *IncludeDirective) Header() *lexer.Token {\n\treturn this.header\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/additive_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype AdditiveExprType int\n\nconst (\n\tADD AdditiveExprType = iota\n\tSUB\n)\n\ntype AdditiveExpr struct {\n\tadditive_expr_type AdditiveExprType\n\tloperand           *Expr\n\troperand           *Expr\n}\n\nfunc (this *AdditiveExpr) Init(\n\tadditive_expr_type AdditiveExprType,\n\tloperand *Expr,\n\troperand *Expr,\n) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.additive_expr_type = additive_expr_type\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *AdditiveExpr) AdditiveExprType() AdditiveExprType {\n\treturn this.additive_expr_type\n}\n\nfunc (this *AdditiveExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *AdditiveExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/arg_list.go",
    "content": "package expr\n\ntype ArgList struct {\n\targs []*Expr\n}\n\nfunc (this *ArgList) Init() {\n\tthis.args = make([]*Expr, 0)\n}\n\nfunc (this *ArgList) Length() int {\n\treturn len(this.args)\n}\n\nfunc (this *ArgList) Get(pos int) *Expr {\n\treturn this.args[pos]\n}\n\nfunc (this *ArgList) Append(arg *Expr) {\n\tthis.args = append(this.args, arg)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/assignment_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype AssignmentExprType int\n\nconst (\n\tASSIGN AssignmentExprType = iota\n\tSTAR_ASSIGN\n\tDIV_ASSIGN\n\tMOD_ASSIGN\n\tPLUS_ASSIGN\n\tMINUS_ASSIGN\n\tLSHIFT_ASSIGN\n\tRSHIFT_ASSIGN\n\tAND_ASSIGN\n\tCARET_ASSIGN\n\tOR_ASSIGN\n)\n\ntype AssignmentExpr struct {\n\tassignment_expr_type AssignmentExprType\n\tlvalue               *Expr\n\trvalue               *Expr\n}\n\nfunc (this *AssignmentExpr) Init(\n\tassignment_expr_type AssignmentExprType,\n\tlvalue *Expr,\n\trvalue *Expr,\n) {\n\tif lvalue.ExprType() != PRIMARY && lvalue.ExprType() != POSTFIX && lvalue.ExprType() != UNARY {\n\t\terr := errors.New(\"lvalue expr type is wrong\")\n\t\tpanic(err)\n\t} else if rvalue.ExprType() != PRIMARY && rvalue.ExprType() != POSTFIX &&\n\t\trvalue.ExprType() != UNARY &&\n\t\trvalue.ExprType() != MULTIPLICATIVE &&\n\t\trvalue.ExprType() != ADDITIVE &&\n\t\trvalue.ExprType() != SHIFT &&\n\t\trvalue.ExprType() != RELATIONAL &&\n\t\trvalue.ExprType() != EQUALITY &&\n\t\trvalue.ExprType() != BITWISE_AND &&\n\t\trvalue.ExprType() != BITWISE_XOR &&\n\t\trvalue.ExprType() != BITWISE_OR &&\n\t\trvalue.ExprType() != LOGICAL_AND &&\n\t\trvalue.ExprType() != LOGICAL_OR &&\n\t\trvalue.ExprType() != CONDITIONAL {\n\t\terr := errors.New(\"rvalue expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.assignment_expr_type = assignment_expr_type\n\tthis.lvalue = lvalue\n\tthis.rvalue = rvalue\n}\n\nfunc (this *AssignmentExpr) AssignmentExprType() AssignmentExprType {\n\treturn this.assignment_expr_type\n}\n\nfunc (this *AssignmentExpr) Lvalue() *Expr {\n\treturn this.lvalue\n}\n\nfunc (this *AssignmentExpr) Rvalue() *Expr {\n\treturn this.rvalue\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/bitwise_and_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BitwiseAndExpr struct {\n\tloperand *Expr\n\troperand *Expr\n}\n\nfunc (this *BitwiseAndExpr) Init(loperand *Expr, roperand *Expr) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY &&\n\t\tloperand.ExprType() != BITWISE_AND {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY &&\n\t\troperand.ExprType() != BITWISE_AND {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *BitwiseAndExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *BitwiseAndExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/bitwise_or_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BitwiseOrExpr struct {\n\tloperand *Expr\n\troperand *Expr\n}\n\nfunc (this *BitwiseOrExpr) Init(loperand *Expr, roperand *Expr) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY &&\n\t\tloperand.ExprType() != BITWISE_AND &&\n\t\tloperand.ExprType() != BITWISE_XOR &&\n\t\tloperand.ExprType() != BITWISE_OR {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY &&\n\t\troperand.ExprType() != BITWISE_AND &&\n\t\troperand.ExprType() != BITWISE_XOR &&\n\t\troperand.ExprType() != BITWISE_OR {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *BitwiseOrExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *BitwiseOrExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/bitwise_xor_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype BitwiseXorExpr struct {\n\tloperand *Expr\n\troperand *Expr\n}\n\nfunc (this *BitwiseXorExpr) Init(loperand *Expr, roperand *Expr) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY &&\n\t\tloperand.ExprType() != BITWISE_AND &&\n\t\tloperand.ExprType() != BITWISE_XOR {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY &&\n\t\troperand.ExprType() != BITWISE_AND &&\n\t\troperand.ExprType() != BITWISE_XOR {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *BitwiseXorExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *BitwiseXorExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/conditional_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype ConditionalExpr struct {\n\tconditional_expr *Expr\n\ttrue_expr        *Expr\n\tfalse_expr       *Expr\n}\n\nfunc (this *ConditionalExpr) Init(conditional_expr *Expr, true_expr *Expr, false_expr *Expr) {\n\tif conditional_expr.ExprType() != PRIMARY && conditional_expr.ExprType() != POSTFIX &&\n\t\tconditional_expr.ExprType() != UNARY &&\n\t\tconditional_expr.ExprType() != MULTIPLICATIVE &&\n\t\tconditional_expr.ExprType() != ADDITIVE &&\n\t\tconditional_expr.ExprType() != SHIFT &&\n\t\tconditional_expr.ExprType() != RELATIONAL &&\n\t\tconditional_expr.ExprType() != EQUALITY &&\n\t\tconditional_expr.ExprType() != BITWISE_AND &&\n\t\tconditional_expr.ExprType() != BITWISE_XOR &&\n\t\tconditional_expr.ExprType() != BITWISE_OR &&\n\t\tconditional_expr.ExprType() != LOGICAL_AND &&\n\t\tconditional_expr.ExprType() != LOGICAL_OR {\n\t\terr := errors.New(\"conditional_expr expr type is wrong\")\n\t\tpanic(err)\n\t} else if true_expr.ExprType() != PRIMARY && true_expr.ExprType() != POSTFIX &&\n\t\ttrue_expr.ExprType() != UNARY &&\n\t\ttrue_expr.ExprType() != MULTIPLICATIVE &&\n\t\ttrue_expr.ExprType() != ADDITIVE &&\n\t\ttrue_expr.ExprType() != SHIFT &&\n\t\ttrue_expr.ExprType() != RELATIONAL &&\n\t\ttrue_expr.ExprType() != EQUALITY &&\n\t\ttrue_expr.ExprType() != BITWISE_AND &&\n\t\ttrue_expr.ExprType() != BITWISE_XOR &&\n\t\ttrue_expr.ExprType() != BITWISE_OR &&\n\t\ttrue_expr.ExprType() != LOGICAL_AND &&\n\t\ttrue_expr.ExprType() != LOGICAL_OR &&\n\t\ttrue_expr.ExprType() != CONDITIONAL {\n\t\terr := errors.New(\"true_expr expr type is wrong\")\n\t\tpanic(err)\n\t} else if false_expr.ExprType() != PRIMARY && false_expr.ExprType() != POSTFIX &&\n\t\tfalse_expr.ExprType() != UNARY &&\n\t\tfalse_expr.ExprType() != MULTIPLICATIVE &&\n\t\tfalse_expr.ExprType() != ADDITIVE &&\n\t\tfalse_expr.ExprType() != SHIFT &&\n\t\tfalse_expr.ExprType() != RELATIONAL &&\n\t\tfalse_expr.ExprType() != EQUALITY &&\n\t\tfalse_expr.ExprType() != BITWISE_AND &&\n\t\tfalse_expr.ExprType() != BITWISE_XOR &&\n\t\tfalse_expr.ExprType() != BITWISE_OR &&\n\t\tfalse_expr.ExprType() != LOGICAL_AND &&\n\t\tfalse_expr.ExprType() != LOGICAL_OR &&\n\t\tfalse_expr.ExprType() != CONDITIONAL {\n\t\terr := errors.New(\"true_expr expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.conditional_expr = conditional_expr\n\tthis.true_expr = true_expr\n\tthis.false_expr = false_expr\n}\n\nfunc (this *ConditionalExpr) ConditionalExpr() *Expr {\n\treturn this.conditional_expr\n}\n\nfunc (this *ConditionalExpr) TrueExpr() *Expr {\n\treturn this.true_expr\n}\n\nfunc (this *ConditionalExpr) FalseExpr() *Expr {\n\treturn this.false_expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/equality_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype EqualityExprType int\n\nconst (\n\tEQ EqualityExprType = iota\n\tNOT_EQ\n)\n\ntype EqualityExpr struct {\n\tequality_expr_type EqualityExprType\n\tloperand           *Expr\n\troperand           *Expr\n}\n\nfunc (this *EqualityExpr) Init(\n\tequality_expr_type EqualityExprType,\n\tloperand *Expr,\n\troperand *Expr,\n) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.equality_expr_type = equality_expr_type\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *EqualityExpr) EqualityExprType() EqualityExprType {\n\treturn this.equality_expr_type\n}\n\nfunc (this *EqualityExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *EqualityExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/expr.go",
    "content": "package expr\n\ntype ExprType int\n\nconst (\n\tPRIMARY ExprType = iota\n\tPOSTFIX\n\tUNARY\n\tMULTIPLICATIVE\n\tADDITIVE\n\tSHIFT\n\tRELATIONAL\n\tEQUALITY\n\tBITWISE_AND\n\tBITWISE_XOR\n\tBITWISE_OR\n\tLOGICAL_AND\n\tLOGICAL_OR\n\tCONDITIONAL\n\tASSIGNMENT\n)\n\ntype Expr struct {\n\texpr_type ExprType\n\n\tprimary_expr        *PrimaryExpr\n\tpostfix_expr        *PostfixExpr\n\tunary_expr          *UnaryExpr\n\tmultiplicative_expr *MultiplicativeExpr\n\tadditive_expr       *AdditiveExpr\n\tshift_expr          *ShiftExpr\n\trelational_expr     *RelationalExpr\n\tequality_expr       *EqualityExpr\n\tbitwise_and_expr    *BitwiseAndExpr\n\tbitwise_xor_expr    *BitwiseXorExpr\n\tbitwise_or_expr     *BitwiseOrExpr\n\tlogical_and_expr    *LogicalAndExpr\n\tlogical_or_expr     *LogicalOrExpr\n\tconditional_expr    *ConditionalExpr\n\tassignment_expr     *AssignmentExpr\n}\n\nfunc (this *Expr) InitPrimaryExpr(primary_expr *PrimaryExpr) {\n\tthis.expr_type = PRIMARY\n\n\tthis.primary_expr = primary_expr\n}\n\nfunc (this *Expr) InitPostfixExpr(postfix_expr *PostfixExpr) {\n\tthis.expr_type = POSTFIX\n\n\tthis.postfix_expr = postfix_expr\n}\n\nfunc (this *Expr) InitUnaryExpr(unary_expr *UnaryExpr) {\n\tthis.expr_type = UNARY\n\n\tthis.unary_expr = unary_expr\n}\n\nfunc (this *Expr) InitMultiplicativeExpr(multiplicative_expr *MultiplicativeExpr) {\n\tthis.expr_type = MULTIPLICATIVE\n\n\tthis.multiplicative_expr = multiplicative_expr\n}\n\nfunc (this *Expr) InitAdditiveExpr(additive_expr *AdditiveExpr) {\n\tthis.expr_type = ADDITIVE\n\n\tthis.additive_expr = additive_expr\n}\n\nfunc (this *Expr) InitShiftExpr(shift_expr *ShiftExpr) {\n\tthis.expr_type = SHIFT\n\n\tthis.shift_expr = shift_expr\n}\n\nfunc (this *Expr) InitRelationalExpr(relational_expr *RelationalExpr) {\n\tthis.expr_type = RELATIONAL\n\n\tthis.relational_expr = relational_expr\n}\n\nfunc (this *Expr) InitEqualityExpr(equality_expr *EqualityExpr) {\n\tthis.expr_type = EQUALITY\n\n\tthis.equality_expr = equality_expr\n}\n\nfunc (this *Expr) InitBitwiseAndExpr(bitwise_and_expr *BitwiseAndExpr) {\n\tthis.expr_type = BITWISE_AND\n\n\tthis.bitwise_and_expr = bitwise_and_expr\n}\n\nfunc (this *Expr) InitBitwiseXorExpr(bitwise_xor_expr *BitwiseXorExpr) {\n\tthis.expr_type = BITWISE_XOR\n\n\tthis.bitwise_xor_expr = bitwise_xor_expr\n}\n\nfunc (this *Expr) InitBitwiseOrExpr(bitwise_or_expr *BitwiseOrExpr) {\n\tthis.expr_type = BITWISE_OR\n\n\tthis.bitwise_or_expr = bitwise_or_expr\n}\n\nfunc (this *Expr) InitLogicalAndExpr(logical_and_expr *LogicalAndExpr) {\n\tthis.expr_type = LOGICAL_AND\n\n\tthis.logical_and_expr = logical_and_expr\n}\n\nfunc (this *Expr) InitLogicalOrExpr(logical_or_expr *LogicalOrExpr) {\n\tthis.expr_type = LOGICAL_OR\n\n\tthis.logical_or_expr = logical_or_expr\n}\n\nfunc (this *Expr) InitConditionalExpr(conditional_expr *ConditionalExpr) {\n\tthis.expr_type = CONDITIONAL\n\n\tthis.conditional_expr = conditional_expr\n}\n\nfunc (this *Expr) InitAssignmentExpr(assignment_expr *AssignmentExpr) {\n\tthis.expr_type = ASSIGNMENT\n\n\tthis.assignment_expr = assignment_expr\n}\n\nfunc (this *Expr) ExprType() ExprType {\n\treturn this.expr_type\n}\n\nfunc (this *Expr) PrimaryExpr() *PrimaryExpr {\n\treturn this.primary_expr\n}\n\nfunc (this *Expr) PostfixExpr() *PostfixExpr {\n\treturn this.postfix_expr\n}\n\nfunc (this *Expr) UnaryExpr() *UnaryExpr {\n\treturn this.unary_expr\n}\n\nfunc (this *Expr) MultiplicativeExpr() *MultiplicativeExpr {\n\treturn this.multiplicative_expr\n}\n\nfunc (this *Expr) AdditiveExpr() *AdditiveExpr {\n\treturn this.additive_expr\n}\n\nfunc (this *Expr) ShiftExpr() *ShiftExpr {\n\treturn this.shift_expr\n}\n\nfunc (this *Expr) RelationalExpr() *RelationalExpr {\n\treturn this.relational_expr\n}\n\nfunc (this *Expr) BitwiseAndExpr() *BitwiseAndExpr {\n\treturn this.bitwise_and_expr\n}\n\nfunc (this *Expr) BitwiseXorExpr() *BitwiseXorExpr {\n\treturn this.bitwise_xor_expr\n}\n\nfunc (this *Expr) BitwiseOrExpr() *BitwiseOrExpr {\n\treturn this.bitwise_or_expr\n}\n\nfunc (this *Expr) LogicalAndExpr() *LogicalAndExpr {\n\treturn this.logical_and_expr\n}\n\nfunc (this *Expr) LogicalOrExpr() *LogicalOrExpr {\n\treturn this.logical_or_expr\n}\n\nfunc (this *Expr) EqualityExpr() *EqualityExpr {\n\treturn this.equality_expr\n}\n\nfunc (this *Expr) ConditionalExpr() *ConditionalExpr {\n\treturn this.conditional_expr\n}\n\nfunc (this *Expr) AssignmentExpr() *AssignmentExpr {\n\treturn this.assignment_expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/logical_and_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype LogicalAndExpr struct {\n\tloperand *Expr\n\troperand *Expr\n}\n\nfunc (this *LogicalAndExpr) Init(loperand *Expr, roperand *Expr) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY &&\n\t\tloperand.ExprType() != BITWISE_AND &&\n\t\tloperand.ExprType() != BITWISE_XOR &&\n\t\tloperand.ExprType() != BITWISE_OR &&\n\t\tloperand.ExprType() != LOGICAL_AND {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY &&\n\t\troperand.ExprType() != BITWISE_AND &&\n\t\troperand.ExprType() != BITWISE_XOR &&\n\t\troperand.ExprType() != BITWISE_OR &&\n\t\troperand.ExprType() != LOGICAL_AND {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *LogicalAndExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *LogicalAndExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/logical_or_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype LogicalOrExpr struct {\n\tloperand *Expr\n\troperand *Expr\n}\n\nfunc (this *LogicalOrExpr) Init(loperand *Expr, roperand *Expr) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL &&\n\t\tloperand.ExprType() != EQUALITY &&\n\t\tloperand.ExprType() != BITWISE_AND &&\n\t\tloperand.ExprType() != BITWISE_XOR &&\n\t\tloperand.ExprType() != BITWISE_OR &&\n\t\tloperand.ExprType() != LOGICAL_AND &&\n\t\tloperand.ExprType() != LOGICAL_OR {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL &&\n\t\troperand.ExprType() != EQUALITY &&\n\t\troperand.ExprType() != BITWISE_AND &&\n\t\troperand.ExprType() != BITWISE_XOR &&\n\t\troperand.ExprType() != BITWISE_OR &&\n\t\troperand.ExprType() != LOGICAL_AND &&\n\t\troperand.ExprType() != LOGICAL_OR {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *LogicalOrExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *LogicalOrExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/multiplicative_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype MultiplicativeExprType int\n\nconst (\n\tMUL MultiplicativeExprType = iota\n\tDIV\n\tMOD\n)\n\ntype MultiplicativeExpr struct {\n\tmultiplicative_expr_type MultiplicativeExprType\n\tloperand                 *Expr\n\troperand                 *Expr\n}\n\nfunc (this *MultiplicativeExpr) Init(\n\tmultiplicative_expr_type MultiplicativeExprType,\n\tloperand *Expr,\n\troperand *Expr,\n) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.multiplicative_expr_type = multiplicative_expr_type\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *MultiplicativeExpr) MultiplicativeExprType() MultiplicativeExprType {\n\treturn this.multiplicative_expr_type\n}\n\nfunc (this *MultiplicativeExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *MultiplicativeExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/postfix_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype PostfixExprType int\n\nconst (\n\tBRACKET PostfixExprType = iota\n\tCALL\n\tDOT\n\tARROW\n\tPOSTFIX_PLUS_PLUS\n\tPOSTFIX_MINUS_MINUS\n)\n\ntype PostfixExpr struct {\n\tpostfix_expr_type PostfixExprType\n\tbase              *Expr\n\toffset_expr       *Expr\n\targ_list          *ArgList\n\toffset_token      *lexer.Token\n}\n\nfunc (this *PostfixExpr) InitBracket(base *Expr, offset_expr *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = BRACKET\n\tthis.base = base\n\tthis.offset_expr = offset_expr\n}\n\nfunc (this *PostfixExpr) InitCall(base *Expr, arg_list *ArgList) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = CALL\n\tthis.base = base\n\tthis.arg_list = arg_list\n}\n\nfunc (this *PostfixExpr) InitDot(base *Expr, offset_token *lexer.Token) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t} else if offset_token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"offset token's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = DOT\n\tthis.base = base\n\tthis.offset_token = offset_token\n}\n\nfunc (this *PostfixExpr) InitArrow(base *Expr, offset_token *lexer.Token) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t} else if offset_token.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"offset token's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = ARROW\n\tthis.base = base\n\tthis.offset_token = offset_token\n}\n\nfunc (this *PostfixExpr) InitPlusPlus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = POSTFIX_PLUS_PLUS\n\tthis.base = base\n}\n\nfunc (this *PostfixExpr) InitMinusMinus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.postfix_expr_type = POSTFIX_MINUS_MINUS\n\tthis.base = base\n}\n\nfunc (this *PostfixExpr) PostfixExprType() PostfixExprType {\n\treturn this.postfix_expr_type\n}\n\nfunc (this *PostfixExpr) Base() *Expr {\n\treturn this.base\n}\n\nfunc (this *PostfixExpr) OffsetExpr() *Expr {\n\treturn this.offset_expr\n}\n\nfunc (this *PostfixExpr) ArgList() *ArgList {\n\treturn this.arg_list\n}\n\nfunc (this *PostfixExpr) OffsetToken() *lexer.Token {\n\treturn this.offset_token\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/primary_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype PrimaryExprType int\n\nconst (\n\tIDENTIFIER PrimaryExprType = iota\n\tNUMBER\n\tSTRING\n\tNULLPTR\n\tPAREN\n)\n\ntype PrimaryExpr struct {\n\tprimary_expr_type PrimaryExprType\n\ttoken             *lexer.Token\n\texpr              *Expr\n}\n\nfunc (this *PrimaryExpr) InitIdentifier(token *lexer.Token) {\n\tthis.primary_expr_type = IDENTIFIER\n\tthis.token = token\n\tthis.expr = nil\n}\n\nfunc (this *PrimaryExpr) InitNumber(token *lexer.Token) {\n\tthis.primary_expr_type = NUMBER\n\tthis.token = token\n\tthis.expr = nil\n}\n\nfunc (this *PrimaryExpr) InitString(token *lexer.Token) {\n\tthis.primary_expr_type = STRING\n\tthis.token = token\n\tthis.expr = nil\n}\n\nfunc (this *PrimaryExpr) InitNullptr(token *lexer.Token) {\n\tthis.primary_expr_type = NULLPTR\n\tthis.token = token\n\tthis.expr = nil\n}\n\nfunc (this *PrimaryExpr) InitParen(expr *Expr) {\n\tthis.primary_expr_type = PAREN\n\tthis.token = nil\n\tthis.expr = expr\n}\n\nfunc (this *PrimaryExpr) PrimaryExprType() PrimaryExprType {\n\treturn this.primary_expr_type\n}\n\nfunc (this *PrimaryExpr) Token() *lexer.Token {\n\tif this.token == nil {\n\t\terr := errors.New(\"token == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.token\n}\n\nfunc (this *PrimaryExpr) Expr() *Expr {\n\tif this.expr == nil {\n\t\terr := errors.New(\"expr == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/relational_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype RelationalExprType int\n\nconst (\n\tLESS RelationalExprType = iota\n\tLESS_EQ\n\tGREATER\n\tGREATER_EQ\n)\n\ntype RelationalExpr struct {\n\trelational_expr_type RelationalExprType\n\tloperand             *Expr\n\troperand             *Expr\n}\n\nfunc (this *RelationalExpr) Init(\n\trelational_expr_type RelationalExprType,\n\tloperand *Expr,\n\troperand *Expr,\n) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT &&\n\t\tloperand.ExprType() != RELATIONAL {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT &&\n\t\troperand.ExprType() != RELATIONAL {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.relational_expr_type = relational_expr_type\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *RelationalExpr) RelationalExprType() RelationalExprType {\n\treturn this.relational_expr_type\n}\n\nfunc (this *RelationalExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *RelationalExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/shift_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n)\n\ntype ShiftExprType int\n\nconst (\n\tLSHIFT ShiftExprType = iota\n\tRSHIFT\n)\n\ntype ShiftExpr struct {\n\tshift_expr_type ShiftExprType\n\tloperand        *Expr\n\troperand        *Expr\n}\n\nfunc (this *ShiftExpr) Init(\n\tshift_expr_type ShiftExprType,\n\tloperand *Expr,\n\troperand *Expr,\n) {\n\tif loperand.ExprType() != PRIMARY && loperand.ExprType() != POSTFIX &&\n\t\tloperand.ExprType() != UNARY &&\n\t\tloperand.ExprType() != MULTIPLICATIVE &&\n\t\tloperand.ExprType() != ADDITIVE &&\n\t\tloperand.ExprType() != SHIFT {\n\t\terr := errors.New(\"loperand expr type is wrong\")\n\t\tpanic(err)\n\t} else if roperand.ExprType() != PRIMARY && roperand.ExprType() != POSTFIX &&\n\t\troperand.ExprType() != UNARY &&\n\t\troperand.ExprType() != MULTIPLICATIVE &&\n\t\troperand.ExprType() != ADDITIVE &&\n\t\troperand.ExprType() != SHIFT {\n\t\terr := errors.New(\"roperand expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.shift_expr_type = shift_expr_type\n\tthis.loperand = loperand\n\tthis.roperand = roperand\n}\n\nfunc (this *ShiftExpr) ShiftExprType() ShiftExprType {\n\treturn this.shift_expr_type\n}\n\nfunc (this *ShiftExpr) Loperand() *Expr {\n\treturn this.loperand\n}\n\nfunc (this *ShiftExpr) Roperand() *Expr {\n\treturn this.roperand\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/expr/unary_expr.go",
    "content": "package expr\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype UnaryExprType int\n\nconst (\n\tUNARY_PLUS_PLUS UnaryExprType = iota\n\tUNARY_MINUS_MINUS\n\tAND\n\tSTAR\n\tPLUS\n\tMINUS\n\tTILDE\n\tNOT\n\tSIZEOF\n)\n\ntype UnaryExpr struct {\n\tunary_expr_type UnaryExprType\n\tbase            *Expr\n\ttype_specifier  *type_specifier.TypeSpecifier\n}\n\nfunc (this *UnaryExpr) InitPlusPlus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = UNARY_PLUS_PLUS\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitMinusMinus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = UNARY_MINUS_MINUS\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitAnd(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = AND\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitStar(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = STAR\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitPlus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = PLUS\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitMinus(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = MINUS\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitTilde(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = TILDE\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitNot(base *Expr) {\n\tif base.ExprType() != PRIMARY && base.ExprType() != POSTFIX && base.ExprType() != UNARY {\n\t\terr := errors.New(\"base expr type is wrong\")\n\t\tpanic(err)\n\t}\n\n\tthis.unary_expr_type = NOT\n\tthis.base = base\n}\n\nfunc (this *UnaryExpr) InitSizeof(type_specifier *type_specifier.TypeSpecifier) {\n\tthis.unary_expr_type = SIZEOF\n\tthis.type_specifier = type_specifier\n}\n\nfunc (this *UnaryExpr) UnaryExprType() UnaryExprType {\n\treturn this.unary_expr_type\n}\n\nfunc (this *UnaryExpr) Base() *Expr {\n\treturn this.base\n}\n\nfunc (this *UnaryExpr) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/param_list/param.go",
    "content": "package param_list\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype Param struct {\n\ttype_specifier *type_specifier.TypeSpecifier\n\tidentifier     *lexer.Token\n}\n\nfunc (this *Param) Init(type_specifier *type_specifier.TypeSpecifier, identifier *lexer.Token) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier = type_specifier\n\tthis.identifier = identifier\n}\n\nfunc (this *Param) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *Param) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/param_list/param_list.go",
    "content": "package param_list\n\ntype ParamList struct {\n\tparams []*Param\n}\n\nfunc (this *ParamList) Init() {\n\tthis.params = make([]*Param, 0)\n}\n\nfunc (this *ParamList) Length() int {\n\treturn len(this.params)\n}\n\nfunc (this *ParamList) Get(pos int) *Param {\n\treturn this.params[pos]\n}\n\nfunc (this *ParamList) Append(param *Param) {\n\tthis.params = append(this.params, param)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/parser.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/decl\"\n\t\"uPIMulator/src/host/interpreter/parser/directive\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n\t\"uPIMulator/src/host/interpreter/parser/param_list\"\n\t\"uPIMulator/src/host/interpreter/parser/stmt\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype Parser struct {\n\tstack *Stack\n\ttable *Table\n}\n\nfunc (this *Parser) Init() {\n\tthis.stack = new(Stack)\n\tthis.stack.Init()\n\n\tthis.table = new(Table)\n\tthis.table.Init(this.stack)\n\n\tthis.RegisterTypeSpecifierVoid()\n\tthis.RegisterTypeSpecifierChar()\n\tthis.RegisterTypeSpecifierShort()\n\tthis.RegisterTypeSpecifierInt()\n\tthis.RegisterTypeSpecifierLong()\n\tthis.RegisterTypeSpecifierStruct()\n\tthis.RegisterTypeSpecifierStar()\n\n\tthis.RegisterParamListBegin()\n\tthis.RegisterParamListAppend()\n\n\tthis.RegisterArgListBegin()\n\tthis.RegisterArgListAppend()\n\n\tthis.RegisterPrimaryExprIdentifier()\n\tthis.RegisterPrimaryExprNumber()\n\tthis.RegisterPrimaryExprString()\n\tthis.RegisterPrimaryExprNullptr()\n\tthis.RegisterPrimaryExprParen()\n\n\tthis.RegisterPostfixExprBracket()\n\tthis.RegisterPostfixExprCallEmpty()\n\tthis.RegisterPostfixExprCallSingle()\n\tthis.RegisterPostfixExprCallMultiple()\n\tthis.RegisterPostfixExprDot()\n\tthis.RegisterPostfixExprArrow()\n\tthis.RegisterPostfixExprPlusPlus()\n\tthis.RegisterPostfixExprMinusMinus()\n\n\tthis.RegisterUnaryExprPlusPlus()\n\tthis.RegisterUnaryExprMinusMinus()\n\tthis.RegisterUnaryExprAnd()\n\tthis.RegisterUnaryExprStar()\n\tthis.RegisterUnaryExprPlus()\n\tthis.RegisterUnaryExprMinus()\n\tthis.RegisterUnaryExprTilde()\n\tthis.RegisterUnaryExprNot()\n\tthis.RegisterUnaryExprSizeof()\n\n\tthis.RegisterMultiplicativeExprMul()\n\tthis.RegisterMultiplicativeExprDiv()\n\tthis.RegisterMultiplicativeExprMod()\n\n\tthis.RegisterAdditiveExprAdd()\n\tthis.RegisterAdditiveExprSub()\n\n\tthis.RegisterShiftExprLshift()\n\tthis.RegisterShiftExprRshift()\n\n\tthis.RegisterRelationalExprLess()\n\tthis.RegisterRelationalExprLessEq()\n\tthis.RegisterRelationalExprGreater()\n\tthis.RegisterRelationalExprGreaterEq()\n\n\tthis.RegisterEqualityExprEq()\n\tthis.RegisterEqualityExprNotEq()\n\n\tthis.RegisterBitwiseAndExpr()\n\tthis.RegisterBitwiseXorExpr()\n\tthis.RegisterBitwiseOrExpr()\n\n\tthis.RegisterLogicalAndExpr()\n\tthis.RegisterLogicalOrExpr()\n\n\tthis.RegisterConditionalExpr()\n\n\tthis.RegisterAssignmentExprAssign()\n\tthis.RegisterAssignmentExprStarAssign()\n\tthis.RegisterAssignmentExprDivAssign()\n\tthis.RegisterAssignmentExprModAssign()\n\tthis.RegisterAssignmentExprPlusAssign()\n\tthis.RegisterAssignmentExprMinusAssign()\n\tthis.RegisterAssignmentExprLshiftAssign()\n\tthis.RegisterAssignmentExprRshiftAssign()\n\tthis.RegisterAssignmentExprAndAssign()\n\tthis.RegisterAssignmentExprCaretAssign()\n\tthis.RegisterAssignmentExprOrAssign()\n\n\tthis.RegisterConcatExpr()\n\n\tthis.RegisterEmptyStmt()\n\tthis.RegisterVarDeclStmt()\n\tthis.RegisterVarDeclInitStmt()\n\tthis.RegisterForStmt()\n\tthis.RegisterDpuForeachStmt()\n\tthis.RegisterWhileStmt()\n\tthis.RegisterContinueStmt()\n\tthis.RegisterBreakStmt()\n\n\tthis.RegisterIfStmt()\n\tthis.RegisterElseIfStmt()\n\tthis.RegisterElseStmt()\n\n\tthis.RegisterReturnStmtWithoutValue()\n\tthis.RegisterReturnStmtWithValue()\n\n\tthis.RegisterExprStmt()\n\n\tthis.RegisterBlockStmt()\n\n\tthis.RegisterStructDef()\n\n\tthis.RegisterFuncDeclEmpty()\n\tthis.RegisterFuncDeclNonEmpty()\n\n\tthis.RegisterFuncDefEmpty()\n\tthis.RegisterFuncDefNonEmpty()\n\n\tthis.RegisterIncludeDirective()\n\tthis.RegisterDefineDirective()\n}\n\nfunc (this *Parser) Parse(token_stream *lexer.TokenStream) *Ast {\n\tfor i := 0; i < token_stream.Length(); i++ {\n\t\ttoken := token_stream.Get(i)\n\n\t\tfor this.table.IsReducible(token) {\n\t\t\tthis.table.Reduce(token)\n\t\t}\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitToken(token)\n\t\tthis.stack.Push(stack_item)\n\t}\n\n\treturn this.stack.Accept()\n}\n\nfunc (this *Parser) RegisterTypeSpecifierVoid() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.VOID {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitPrimitive(type_specifier.VOID)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierChar() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CHAR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitPrimitive(type_specifier.CHAR)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierShort() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SHORT {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitPrimitive(type_specifier.SHORT)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierInt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.INT {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitPrimitive(type_specifier.INT)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierLong() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LONG {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitPrimitive(type_specifier.LONG)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierStruct() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.STRUCT &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tstruct_identifier := stack_items[1].Expr().PrimaryExpr().Token()\n\n\t\ttype_specifier_ := new(type_specifier.TypeSpecifier)\n\t\ttype_specifier_.InitStruct(type_specifier.STRUCT, struct_identifier)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterTypeSpecifierStar() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TYPE_SPECIFIER &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STAR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := stack_items[0].TypeSpecifier()\n\t\ttype_specifier_.AddStar()\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitTypeSpecifier(type_specifier_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterParamListBegin() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TYPE_SPECIFIER &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := stack_items[0].TypeSpecifier()\n\t\tidentifier := stack_items[1].Expr().PrimaryExpr().Token()\n\n\t\tparam := new(param_list.Param)\n\t\tparam.Init(type_specifier_, identifier)\n\n\t\tparam_list_ := new(param_list.ParamList)\n\t\tparam_list_.Init()\n\t\tparam_list_.Append(param)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitParamList(param_list_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterParamListAppend() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[2].StackItemType() == TYPE_SPECIFIER &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[3].Expr().PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam_list_ := stack_items[0].ParamList()\n\t\ttype_specifier_ := stack_items[2].TypeSpecifier()\n\t\tidentifier := stack_items[3].Expr().PrimaryExpr().Token()\n\n\t\tparam := new(param_list.Param)\n\t\tparam.Init(type_specifier_, identifier)\n\n\t\tparam_list_.Append(param)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitParamList(param_list_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterArgListBegin() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:      true,\n\t\tlexer.LPAREN:        true,\n\t\tlexer.DOT:           true,\n\t\tlexer.ARROW:         true,\n\t\tlexer.STAR:          true,\n\t\tlexer.DIV:           true,\n\t\tlexer.MOD:           true,\n\t\tlexer.PLUS:          true,\n\t\tlexer.MINUS:         true,\n\t\tlexer.LSHIFT:        true,\n\t\tlexer.RSHIFT:        true,\n\t\tlexer.LESS:          true,\n\t\tlexer.LESS_EQ:       true,\n\t\tlexer.GREATER:       true,\n\t\tlexer.GREATER_EQ:    true,\n\t\tlexer.EQ:            true,\n\t\tlexer.NOT_EQ:        true,\n\t\tlexer.AND:           true,\n\t\tlexer.CARET:         true,\n\t\tlexer.OR:            true,\n\t\tlexer.AND_AND:       true,\n\t\tlexer.OR_OR:         true,\n\t\tlexer.QUESTION:      true,\n\t\tlexer.ASSIGN:        true,\n\t\tlexer.STAR_ASSIGN:   true,\n\t\tlexer.DIV_ASSIGN:    true,\n\t\tlexer.MOD_ASSIGN:    true,\n\t\tlexer.PLUS_ASSIGN:   true,\n\t\tlexer.MINUS_ASSIGN:  true,\n\t\tlexer.LSHIFT_ASSIGN: true,\n\t\tlexer.RSHIFT_ASSIGN: true,\n\t\tlexer.AND_ASSIGN:    true,\n\t\tlexer.CARET_ASSIGN:  true,\n\t\tlexer.OR_ASSIGN:     true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\targ1 := stack_items[0].Expr()\n\t\targ2 := stack_items[2].Expr()\n\n\t\targ_list := new(expr.ArgList)\n\t\targ_list.Init()\n\t\targ_list.Append(arg1)\n\t\targ_list.Append(arg2)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitArgList(arg_list)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterArgListAppend() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:      true,\n\t\tlexer.LPAREN:        true,\n\t\tlexer.DOT:           true,\n\t\tlexer.ARROW:         true,\n\t\tlexer.STAR:          true,\n\t\tlexer.DIV:           true,\n\t\tlexer.MOD:           true,\n\t\tlexer.PLUS:          true,\n\t\tlexer.MINUS:         true,\n\t\tlexer.LSHIFT:        true,\n\t\tlexer.RSHIFT:        true,\n\t\tlexer.LESS:          true,\n\t\tlexer.LESS_EQ:       true,\n\t\tlexer.GREATER:       true,\n\t\tlexer.GREATER_EQ:    true,\n\t\tlexer.EQ:            true,\n\t\tlexer.NOT_EQ:        true,\n\t\tlexer.AND:           true,\n\t\tlexer.CARET:         true,\n\t\tlexer.OR:            true,\n\t\tlexer.AND_AND:       true,\n\t\tlexer.OR_OR:         true,\n\t\tlexer.QUESTION:      true,\n\t\tlexer.ASSIGN:        true,\n\t\tlexer.STAR_ASSIGN:   true,\n\t\tlexer.DIV_ASSIGN:    true,\n\t\tlexer.MOD_ASSIGN:    true,\n\t\tlexer.PLUS_ASSIGN:   true,\n\t\tlexer.MINUS_ASSIGN:  true,\n\t\tlexer.LSHIFT_ASSIGN: true,\n\t\tlexer.RSHIFT_ASSIGN: true,\n\t\tlexer.AND_ASSIGN:    true,\n\t\tlexer.CARET_ASSIGN:  true,\n\t\tlexer.OR_ASSIGN:     true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == ARG_LIST &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.COMMA &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\targ_list := stack_items[0].ArgList()\n\t\targ := stack_items[2].Expr()\n\n\t\targ_list.Append(arg)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitArgList(arg_list)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExprIdentifier() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.PrimaryExpr)\n\t\tprimary_expr.InitIdentifier(token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPrimaryExpr(primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExprNumber() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.NUMBER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.PrimaryExpr)\n\t\tprimary_expr.InitNumber(token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPrimaryExpr(primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExprString() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.STRING {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.PrimaryExpr)\n\t\tprimary_expr.InitString(token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPrimaryExpr(primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExprNullptr() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.NULL {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttoken := stack_items[0].Token()\n\n\t\tprimary_expr := new(expr.PrimaryExpr)\n\t\tprimary_expr.InitNullptr(token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPrimaryExpr(primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPrimaryExprParen() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.RPAREN {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\te := stack_items[1].Expr()\n\n\t\tprimary_expr := new(expr.PrimaryExpr)\n\t\tprimary_expr.InitParen(e)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPrimaryExpr(primary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprBracket() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LBRACKET &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.RBRACKET {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\t\toffset_expr := stack_items[2].Expr()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitBracket(base, offset_expr)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprCallEmpty() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.RPAREN {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\n\t\targ_list := new(expr.ArgList)\n\t\targ_list.Init()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitCall(base, arg_list)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprCallSingle() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.PAREN {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\n\t\targ_list := new(expr.ArgList)\n\t\targ_list.Init()\n\t\targ_list.Append(stack_items[1].Expr().PrimaryExpr().Expr())\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitCall(base, arg_list)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprCallMultiple() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == ARG_LIST &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.RPAREN {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\t\targ_list := stack_items[2].ArgList()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitCall(base, arg_list)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprDot() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.DOT &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\t\toffset_token := stack_items[2].Token()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitDot(base, offset_token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprArrow() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.ARROW &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.IDENTIFIER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\t\toffset_token := stack_items[2].Token()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitArrow(base, offset_token)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprPlusPlus() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PLUS_PLUS {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitPlusPlus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterPostfixExprMinusMinus() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MINUS_MINUS {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[0].Expr()\n\n\t\tpostfix_expr := new(expr.PostfixExpr)\n\t\tpostfix_expr.InitMinusMinus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitPostfixExpr(postfix_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprPlusPlus() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.PLUS_PLUS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitPlusPlus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprMinusMinus() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.MINUS_MINUS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitMinusMinus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprAnd() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.AND &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitAnd(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprStar() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.STAR &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitStar(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprPlus() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.PLUS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitPlus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprMinus() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitMinus(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprTilde() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.TILDE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitTilde(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprNot() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.NOT &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbase := stack_items[1].Expr()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitNot(base)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterUnaryExprSizeof() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SIZEOF &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == TYPE_SPECIFIER &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.RPAREN {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := stack_items[2].TypeSpecifier()\n\n\t\tunary_expr := new(expr.UnaryExpr)\n\t\tunary_expr.InitSizeof(type_specifier_)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitUnaryExpr(unary_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterMultiplicativeExprMul() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STAR &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tmultiplicative_expr := new(expr.MultiplicativeExpr)\n\t\tmultiplicative_expr.Init(expr.MUL, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitMultiplicativeExpr(multiplicative_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterMultiplicativeExprDiv() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.DIV &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tmultiplicative_expr := new(expr.MultiplicativeExpr)\n\t\tmultiplicative_expr.Init(expr.DIV, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitMultiplicativeExpr(multiplicative_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterMultiplicativeExprMod() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MOD &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tmultiplicative_expr := new(expr.MultiplicativeExpr)\n\t\tmultiplicative_expr.Init(expr.MOD, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitMultiplicativeExpr(multiplicative_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAdditiveExprAdd() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PLUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tadditive_expr := new(expr.AdditiveExpr)\n\t\tadditive_expr.Init(expr.ADD, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAdditiveExpr(additive_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAdditiveExprSub() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MINUS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tadditive_expr := new(expr.AdditiveExpr)\n\t\tadditive_expr.Init(expr.SUB, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAdditiveExpr(additive_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterShiftExprLshift() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LSHIFT &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tshift_expr := new(expr.ShiftExpr)\n\t\tshift_expr.Init(expr.LSHIFT, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitShiftExpr(shift_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterShiftExprRshift() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.RSHIFT &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tshift_expr := new(expr.ShiftExpr)\n\t\tshift_expr.Init(expr.RSHIFT, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitShiftExpr(shift_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterRelationalExprLess() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LESS &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\trelational_expr := new(expr.RelationalExpr)\n\t\trelational_expr.Init(expr.LESS, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitRelationalExpr(relational_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterRelationalExprLessEq() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LESS_EQ &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\trelational_expr := new(expr.RelationalExpr)\n\t\trelational_expr.Init(expr.LESS_EQ, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitRelationalExpr(relational_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterRelationalExprGreater() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.GREATER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\trelational_expr := new(expr.RelationalExpr)\n\t\trelational_expr.Init(expr.GREATER, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitRelationalExpr(relational_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterRelationalExprGreaterEq() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.GREATER_EQ &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\trelational_expr := new(expr.RelationalExpr)\n\t\trelational_expr.Init(expr.GREATER_EQ, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitRelationalExpr(relational_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterEqualityExprEq() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.EQ &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tequality_expr := new(expr.EqualityExpr)\n\t\tequality_expr.Init(expr.EQ, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitEqualityExpr(equality_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterEqualityExprNotEq() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.NOT_EQ &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tequality_expr := new(expr.EqualityExpr)\n\t\tequality_expr.Init(expr.NOT_EQ, loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitEqualityExpr(equality_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterBitwiseAndExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.AND &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tbitwise_and_expr := new(expr.BitwiseAndExpr)\n\t\tbitwise_and_expr.Init(loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitBitwiseAndExpr(bitwise_and_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterBitwiseXorExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.CARET &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tbitwise_xor_expr := new(expr.BitwiseXorExpr)\n\t\tbitwise_xor_expr.Init(loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitBitwiseXorExpr(bitwise_xor_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterBitwiseOrExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.OR &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tbitwise_or_expr := new(expr.BitwiseOrExpr)\n\t\tbitwise_or_expr.Init(loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitBitwiseOrExpr(bitwise_or_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterLogicalAndExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.AND_AND &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tlogical_and_expr := new(expr.LogicalAndExpr)\n\t\tlogical_and_expr.Init(loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitLogicalAndExpr(logical_and_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterLogicalOrExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.OR_OR &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tloperand := stack_items[0].Expr()\n\t\troperand := stack_items[2].Expr()\n\n\t\tlogical_or_expr := new(expr.LogicalOrExpr)\n\t\tlogical_or_expr.Init(loperand, roperand)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitLogicalOrExpr(logical_or_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterConditionalExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.QUESTION &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.COLON &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcondition_expr := stack_items[0].Expr()\n\t\ttrue_expr := stack_items[2].Expr()\n\t\tfalse_expr := stack_items[4].Expr()\n\n\t\tconditional_expr := new(expr.ConditionalExpr)\n\t\tconditional_expr.Init(condition_expr, true_expr, false_expr)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitConditionalExpr(conditional_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprStarAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.STAR_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.STAR_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprDivAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.DIV_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.DIV_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprModAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MOD_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.MOD_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprPlusAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.PLUS_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.PLUS_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprMinusAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.MINUS_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.MINUS_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprLshiftAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LSHIFT_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.LSHIFT_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprRshiftAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.RSHIFT_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.RSHIFT_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprAndAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.AND_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.AND_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprCaretAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.CARET_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.CARET_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterAssignmentExprOrAssign() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t\tlexer.PLUS:        true,\n\t\tlexer.MINUS:       true,\n\t\tlexer.LSHIFT:      true,\n\t\tlexer.RSHIFT:      true,\n\t\tlexer.LESS:        true,\n\t\tlexer.LESS_EQ:     true,\n\t\tlexer.GREATER:     true,\n\t\tlexer.GREATER_EQ:  true,\n\t\tlexer.EQ:          true,\n\t\tlexer.NOT_EQ:      true,\n\t\tlexer.AND:         true,\n\t\tlexer.CARET:       true,\n\t\tlexer.OR:          true,\n\t\tlexer.AND_AND:     true,\n\t\tlexer.OR_OR:       true,\n\t\tlexer.QUESTION:    true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.OR_ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tassignment_expr := new(expr.AssignmentExpr)\n\t\tassignment_expr.Init(expr.OR_ASSIGN, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAssignmentExpr(assignment_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterConcatExpr() {\n\tprecedence := map[lexer.TokenType]bool{\n\t\tlexer.LBRACKET:    true,\n\t\tlexer.LPAREN:      true,\n\t\tlexer.DOT:         true,\n\t\tlexer.ARROW:       true,\n\t\tlexer.PLUS_PLUS:   true,\n\t\tlexer.MINUS_MINUS: true,\n\t\tlexer.STAR:        true,\n\t\tlexer.DIV:         true,\n\t\tlexer.MOD:         true,\n\t}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[0].Expr()\n\t\trvalue := stack_items[1].Expr()\n\n\t\tadditive_expr := new(expr.AdditiveExpr)\n\t\tadditive_expr.Init(expr.ADD, lvalue, rvalue)\n\n\t\texpr_ := new(expr.Expr)\n\t\texpr_.InitAdditiveExpr(additive_expr)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitExpr(expr_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterEmptyStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 1 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tempty_stmt := new(stmt.EmptyStmt)\n\t\tempty_stmt.Init()\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitEmptyStmt(empty_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterVarDeclStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tvar_decl_stmt := new(stmt.VarDeclStmt)\n\t\tvar_decl_stmt.Init(type_specifier_, identifier)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitVarDeclStmt(var_decl_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterVarDeclInitStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.ASSIGN &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\t\trvalue := stack_items[2].Expr()\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tvar_decl_init_stmt := new(stmt.VarDeclInitStmt)\n\t\tvar_decl_init_stmt.Init(type_specifier_, identifier, rvalue)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitVarDeclInitStmt(var_decl_init_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterForStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 7 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.FOR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == STMT &&\n\t\t\t\tstack_items[3].StackItemType() == STMT &&\n\t\t\t\tstack_items[4].StackItemType() == EXPR &&\n\t\t\t\tstack_items[5].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[5].Token().TokenType() == lexer.RPAREN &&\n\t\t\t\tstack_items[6].StackItemType() == STMT &&\n\t\t\t\tstack_items[6].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tinitialization := stack_items[2].Stmt()\n\t\tcondition_stmt := stack_items[3].Stmt()\n\t\tupdate_expr := stack_items[4].Expr()\n\t\tbody := stack_items[6].Stmt()\n\n\t\tif condition_stmt.StmtType() != stmt.EXPR {\n\t\t\terr := errors.New(\"condition stmt type is not expr\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tcondition_expr := condition_stmt.ExprStmt().Expr()\n\n\t\tu := new(stmt.ExprStmt)\n\t\tu.Init(update_expr)\n\n\t\tupdate_stmt := new(stmt.Stmt)\n\t\tupdate_stmt.InitExprStmt(u)\n\n\t\tfor_stmt := new(stmt.ForStmt)\n\t\tfor_stmt.Init(initialization, condition_expr, update_stmt, body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitForStmt(for_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterDpuForeachStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[0].Expr().ExprType() == expr.POSTFIX &&\n\t\t\t\tstack_items[0].Expr().PostfixExpr().PostfixExprType() == expr.CALL &&\n\t\t\t\tstack_items[0].Expr().PostfixExpr().Base().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[0].Expr().PostfixExpr().Base().PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER &&\n\t\t\t\tstack_items[0].Expr().PostfixExpr().Base().PrimaryExpr().Token().Attribute() == \"DPU_FOREACH\" &&\n\t\t\t\tstack_items[0].Expr().PostfixExpr().ArgList().Length() == 3 &&\n\t\t\t\tstack_items[1].StackItemType() == STMT &&\n\t\t\t\tstack_items[1].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tforeach := stack_items[0].Expr().PostfixExpr().ArgList()\n\t\tbody := stack_items[1].Stmt()\n\n\t\tdpu_foreach_stmt := new(stmt.DpuForeachStmt)\n\t\tdpu_foreach_stmt.Init(foreach, body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitDpuForeachStmt(dpu_foreach_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterWhileStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.WHILE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.PAREN &&\n\t\t\t\tstack_items[2].StackItemType() == STMT &&\n\t\t\t\tstack_items[2].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcondition := stack_items[1].Expr().PrimaryExpr().Expr()\n\t\tbody := stack_items[2].Stmt()\n\n\t\twhile_stmt := new(stmt.WhileStmt)\n\t\twhile_stmt.Init(condition, body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitWhileStmt(while_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterContinueStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.CONTINUE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcontinue_stmt := new(stmt.ContinueStmt)\n\t\tcontinue_stmt.Init()\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitContinueStmt(continue_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterBreakStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.BREAK &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tbreak_stmt := new(stmt.BreakStmt)\n\t\tbreak_stmt.Init()\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitBreakStmt(break_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterIfStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.IF &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.PAREN &&\n\t\t\t\tstack_items[2].StackItemType() == STMT &&\n\t\t\t\tstack_items[2].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tcondition := stack_items[1].Expr().PrimaryExpr().Expr()\n\t\tbody := stack_items[2].Stmt()\n\n\t\tif_stmt := new(stmt.IfStmt)\n\t\tif_stmt.Init(condition, body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitIfStmt(if_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterElseIfStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == STMT &&\n\t\t\t\tstack_items[0].Stmt().StmtType() == stmt.IF &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.ELSE &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.IF &&\n\t\t\t\tstack_items[3].StackItemType() == EXPR &&\n\t\t\t\tstack_items[3].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[3].Expr().PrimaryExpr().PrimaryExprType() == expr.PAREN &&\n\t\t\t\tstack_items[4].StackItemType() == STMT &&\n\t\t\t\tstack_items[4].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tif_stmt := stack_items[0].Stmt().IfStmt()\n\t\tcondition := stack_items[3].Expr().PrimaryExpr().Expr()\n\t\tbody := stack_items[4].Stmt()\n\n\t\tif_stmt.AppendElseIf(condition, body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitIfStmt(if_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterElseStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == STMT &&\n\t\t\t\tstack_items[0].Stmt().StmtType() == stmt.IF &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.ELSE &&\n\t\t\t\tstack_items[2].StackItemType() == STMT &&\n\t\t\t\tstack_items[2].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tif_stmt := stack_items[0].Stmt().IfStmt()\n\t\tbody := stack_items[2].Stmt()\n\n\t\tif_stmt.SetElseBody(body)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitIfStmt(if_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterReturnStmtWithoutValue() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.RETURN &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\treturn_stmt := new(stmt.ReturnStmt)\n\t\treturn_stmt.InitWithoutValue()\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitReturnStmt(return_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterReturnStmtWithValue() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.RETURN &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tvalue := stack_items[1].Expr()\n\n\t\treturn_stmt := new(stmt.ReturnStmt)\n\t\treturn_stmt.InitWithValue(value)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitReturnStmt(return_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterExprStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\texpr_ := stack_items[0].Expr()\n\n\t\texpr_stmt := new(stmt.ExprStmt)\n\t\texpr_stmt.Init(expr_)\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitExprStmt(expr_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterBlockStmt() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\tstack_items[0].Token().TokenType() == lexer.LBRACE &&\n\t\t\tstack_items[len(stack_items)-1].StackItemType() == TOKEN &&\n\t\t\tstack_items[len(stack_items)-1].Token().TokenType() == lexer.RBRACE {\n\t\t\tfor i := 1; i < len(stack_items)-1; i++ {\n\t\t\t\tif stack_items[i].StackItemType() != STMT {\n\t\t\t\t\treturn false\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn true\n\t\t} else {\n\t\t\treturn false\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tblock_stmt := new(stmt.BlockStmt)\n\t\tblock_stmt.Init()\n\n\t\tfor i := 1; i < len(stack_items)-1; i++ {\n\t\t\tblock_stmt.Append(stack_items[i].Stmt())\n\t\t}\n\n\t\tstmt_ := new(stmt.Stmt)\n\t\tstmt_.InitBlockStmt(block_stmt)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitStmt(stmt_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterStructDef() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TYPE_SPECIFIER &&\n\t\t\t\tstack_items[0].TypeSpecifier().TypeSpecifierType() == type_specifier.STRUCT &&\n\t\t\t\tstack_items[0].TypeSpecifier().NumStars() == 0 &&\n\t\t\t\tstack_items[1].StackItemType() == STMT &&\n\t\t\t\tstack_items[1].Stmt().StmtType() == stmt.BLOCK &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.SEMI {\n\t\t\t\tbody := stack_items[1].Stmt().BlockStmt()\n\t\t\t\tfor i := 0; i < body.Length(); i++ {\n\t\t\t\t\tstmt_ := body.Get(i)\n\n\t\t\t\t\tif stmt_.StmtType() != stmt.VAR_DECL {\n\t\t\t\t\t\treturn false\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\ttype_specifier_ := stack_items[0].TypeSpecifier()\n\t\tbody := stack_items[1].Stmt()\n\n\t\tidentifier := type_specifier_.StructIdentifier()\n\n\t\tstruct_def := new(decl.StructDef)\n\t\tstruct_def.Init(identifier, body)\n\n\t\tdecl_ := new(decl.Decl)\n\t\tdecl_.InitStructDef(struct_def)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDecl(decl_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterFuncDeclEmpty() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.RPAREN &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tparam_list_ := new(param_list.ParamList)\n\t\tparam_list_.Init()\n\n\t\tfunc_decl := new(decl.FuncDecl)\n\t\tfunc_decl.Init(type_specifier_, identifier, param_list_)\n\n\t\tdecl_ := new(decl.Decl)\n\t\tdecl_.InitFuncDecl(func_decl)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDecl(decl_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterFuncDeclNonEmpty() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.RPAREN &&\n\t\t\t\tstack_items[4].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[4].Token().TokenType() == lexer.SEMI {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\t\tparam_list_ := stack_items[2].ParamList()\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tfunc_decl := new(decl.FuncDecl)\n\t\tfunc_decl.Init(type_specifier_, identifier, param_list_)\n\n\t\tdecl_ := new(decl.Decl)\n\t\tdecl_.InitFuncDecl(func_decl)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDecl(decl_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterFuncDefEmpty() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 4 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[2].Token().TokenType() == lexer.RPAREN &&\n\t\t\t\tstack_items[3].StackItemType() == STMT &&\n\t\t\t\tstack_items[3].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\t\tbody := stack_items[3].Stmt()\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tparam_list_ := new(param_list.ParamList)\n\t\tparam_list_.Init()\n\n\t\tfunc_def := new(decl.FuncDef)\n\t\tfunc_def.Init(type_specifier_, identifier, param_list_, body)\n\n\t\tdecl_ := new(decl.Decl)\n\t\tdecl_.InitFuncDef(func_def)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDecl(decl_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterFuncDefNonEmpty() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 5 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[0].ParamList().Length() == 1 &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.LPAREN &&\n\t\t\t\tstack_items[2].StackItemType() == PARAM_LIST &&\n\t\t\t\tstack_items[3].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[3].Token().TokenType() == lexer.RPAREN &&\n\t\t\t\tstack_items[4].StackItemType() == STMT &&\n\t\t\t\tstack_items[4].Stmt().StmtType() == stmt.BLOCK {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tparam := stack_items[0].ParamList().Get(0)\n\t\tparam_list_ := stack_items[2].ParamList()\n\t\tbody := stack_items[4].Stmt()\n\n\t\ttype_specifier_ := param.TypeSpecifier()\n\t\tidentifier := param.Identifier()\n\n\t\tfunc_def := new(decl.FuncDef)\n\t\tfunc_def.Init(type_specifier_, identifier, param_list_, body)\n\n\t\tdecl_ := new(decl.Decl)\n\t\tdecl_.InitFuncDef(func_def)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDecl(decl_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterIncludeDirective() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 2 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.INCLUDE &&\n\t\t\t\tstack_items[1].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[1].Token().TokenType() == lexer.HEADER {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\theader := stack_items[1].Token()\n\n\t\tinclude_directive := new(directive.IncludeDirective)\n\t\tinclude_directive.Init(header)\n\n\t\tdirective_ := new(directive.Directive)\n\t\tdirective_.InitIncludeDirective(include_directive)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDirective(directive_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n\nfunc (this *Parser) RegisterDefineDirective() {\n\tprecedence := map[lexer.TokenType]bool{}\n\n\treducible := func(stack_items []*StackItem) bool {\n\t\tif len(stack_items) != 3 {\n\t\t\treturn false\n\t\t} else {\n\t\t\tif stack_items[0].StackItemType() == TOKEN &&\n\t\t\t\tstack_items[0].Token().TokenType() == lexer.DEFINE &&\n\t\t\t\tstack_items[1].StackItemType() == EXPR &&\n\t\t\t\tstack_items[1].Expr().ExprType() == expr.PRIMARY &&\n\t\t\t\tstack_items[1].Expr().PrimaryExpr().PrimaryExprType() == expr.IDENTIFIER &&\n\t\t\t\tstack_items[2].StackItemType() == EXPR {\n\t\t\t\treturn true\n\t\t\t} else {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\n\treduce := func(stack_items []*StackItem) *StackItem {\n\t\tlvalue := stack_items[1].Expr().PrimaryExpr().Token()\n\t\trvalue := stack_items[2].Expr()\n\n\t\tdefine_directive := new(directive.DefineDirective)\n\t\tdefine_directive.Init(lvalue, rvalue)\n\n\t\tdirective_ := new(directive.Directive)\n\t\tdirective_.InitDefineDirective(define_directive)\n\n\t\tstack_item := new(StackItem)\n\t\tstack_item.InitDirective(directive_)\n\n\t\treturn stack_item\n\t}\n\n\trule := new(Rule)\n\trule.Init(precedence, reducible, reduce)\n\n\tthis.table.AddRule(rule)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/rule.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype Reducible func([]*StackItem) bool\ntype Reduce func([]*StackItem) *StackItem\n\ntype Rule struct {\n\tprecedence map[lexer.TokenType]bool\n\n\treducible Reducible\n\treduce    Reduce\n}\n\nfunc (this *Rule) Init(precedence map[lexer.TokenType]bool, reducible Reducible, reduce Reduce) {\n\tthis.precedence = precedence\n\tthis.reducible = reducible\n\tthis.reduce = reduce\n}\n\nfunc (this *Rule) IsReducible(stack_items []*StackItem, token *lexer.Token) bool {\n\tif _, found := this.precedence[token.TokenType()]; found {\n\t\treturn false\n\t} else {\n\t\treturn this.reducible(stack_items)\n\t}\n}\n\nfunc (this *Rule) Reduce(stack_items []*StackItem, token *lexer.Token) *StackItem {\n\tif !this.IsReducible(stack_items, token) {\n\t\terr := errors.New(\"stack items are not reducible\")\n\t\tpanic(err)\n\t}\n\n\treturn this.reduce(stack_items)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stack.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype Stack struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *Stack) Init() {\n\tthis.stack_items = make([]*StackItem, 0)\n}\n\nfunc (this *Stack) Length() int {\n\treturn len(this.stack_items)\n}\n\nfunc (this *Stack) Push(stack_item *StackItem) {\n\tthis.stack_items = append(this.stack_items, stack_item)\n}\n\nfunc (this *Stack) Pop(num int) {\n\tthis.stack_items = this.stack_items[:len(this.stack_items)-num]\n}\n\nfunc (this *Stack) Front(num int) []*StackItem {\n\tstack_items := make([]*StackItem, 0)\n\tfor i := 0; i < num; i++ {\n\t\tstack_item := this.stack_items[len(this.stack_items)-num+i]\n\t\tstack_items = append(stack_items, stack_item)\n\t}\n\treturn stack_items\n}\n\nfunc (this *Stack) CanAccept() bool {\n\tfor i, stack_item := range this.stack_items {\n\t\tif i < len(this.stack_items)-1 {\n\t\t\tif stack_item.StackItemType() != DIRECTIVE && stack_item.StackItemType() != DECL {\n\t\t\t\treturn false\n\t\t\t}\n\t\t} else {\n\t\t\tif stack_item.StackItemType() != TOKEN || stack_item.Token().TokenType() != lexer.END_OF_FILE {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *Stack) Accept() *Ast {\n\tif !this.CanAccept() {\n\t\terr := errors.New(\"stack cannot be accepted\")\n\t\tpanic(err)\n\t}\n\n\tast := new(Ast)\n\tast.Init(this.stack_items[:len(this.stack_items)-1])\n\n\treturn ast\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stack_item.go",
    "content": "package parser\n\nimport (\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/decl\"\n\t\"uPIMulator/src/host/interpreter/parser/directive\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n\t\"uPIMulator/src/host/interpreter/parser/param_list\"\n\t\"uPIMulator/src/host/interpreter/parser/stmt\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype StackItemType int\n\nconst (\n\tTOKEN StackItemType = iota\n\tTYPE_SPECIFIER\n\tPARAM_LIST\n\tARG_LIST\n\tEXPR\n\tSTMT\n\tDECL\n\tDIRECTIVE\n)\n\ntype StackItem struct {\n\tstack_item_type StackItemType\n\n\ttoken          *lexer.Token\n\ttype_specifier *type_specifier.TypeSpecifier\n\tparam_list     *param_list.ParamList\n\targ_list       *expr.ArgList\n\texpr           *expr.Expr\n\tstmt           *stmt.Stmt\n\tdecl           *decl.Decl\n\tdirective      *directive.Directive\n}\n\nfunc (this *StackItem) InitToken(token *lexer.Token) {\n\tthis.stack_item_type = TOKEN\n\n\tthis.token = token\n}\n\nfunc (this *StackItem) InitTypeSpecifier(type_specifier *type_specifier.TypeSpecifier) {\n\tthis.stack_item_type = TYPE_SPECIFIER\n\n\tthis.type_specifier = type_specifier\n}\n\nfunc (this *StackItem) InitParamList(param_list *param_list.ParamList) {\n\tthis.stack_item_type = PARAM_LIST\n\n\tthis.param_list = param_list\n}\n\nfunc (this *StackItem) InitArgList(arg_list *expr.ArgList) {\n\tthis.stack_item_type = ARG_LIST\n\n\tthis.arg_list = arg_list\n}\n\nfunc (this *StackItem) InitExpr(expr *expr.Expr) {\n\tthis.stack_item_type = EXPR\n\n\tthis.expr = expr\n}\n\nfunc (this *StackItem) InitStmt(stmt *stmt.Stmt) {\n\tthis.stack_item_type = STMT\n\n\tthis.stmt = stmt\n}\n\nfunc (this *StackItem) InitDecl(decl *decl.Decl) {\n\tthis.stack_item_type = DECL\n\n\tthis.decl = decl\n}\n\nfunc (this *StackItem) InitDirective(directive *directive.Directive) {\n\tthis.stack_item_type = DIRECTIVE\n\n\tthis.directive = directive\n}\n\nfunc (this *StackItem) StackItemType() StackItemType {\n\treturn this.stack_item_type\n}\n\nfunc (this *StackItem) Token() *lexer.Token {\n\treturn this.token\n}\n\nfunc (this *StackItem) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *StackItem) ParamList() *param_list.ParamList {\n\treturn this.param_list\n}\n\nfunc (this *StackItem) ArgList() *expr.ArgList {\n\treturn this.arg_list\n}\n\nfunc (this *StackItem) Expr() *expr.Expr {\n\treturn this.expr\n}\n\nfunc (this *StackItem) Stmt() *stmt.Stmt {\n\treturn this.stmt\n}\n\nfunc (this *StackItem) Decl() *decl.Decl {\n\treturn this.decl\n}\n\nfunc (this *StackItem) Directive() *directive.Directive {\n\treturn this.directive\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/block_stmt.go",
    "content": "package stmt\n\ntype BlockStmt struct {\n\tstmts []*Stmt\n}\n\nfunc (this *BlockStmt) Init() {\n\tthis.stmts = make([]*Stmt, 0)\n}\n\nfunc (this *BlockStmt) Length() int {\n\treturn len(this.stmts)\n}\n\nfunc (this *BlockStmt) Get(pos int) *Stmt {\n\treturn this.stmts[pos]\n}\n\nfunc (this *BlockStmt) Append(stmt *Stmt) {\n\tthis.stmts = append(this.stmts, stmt)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/break_stmt.go",
    "content": "package stmt\n\ntype BreakStmt struct {\n}\n\nfunc (this *BreakStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/continue_stmt.go",
    "content": "package stmt\n\ntype ContinueStmt struct {\n}\n\nfunc (this *ContinueStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/dpu_foreach_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype DpuForeachStmt struct {\n\tforeach *expr.ArgList\n\tbody    *Stmt\n}\n\nfunc (this *DpuForeachStmt) Init(foreach *expr.ArgList, body *Stmt) {\n\tif foreach.Length() != 3 {\n\t\terr := errors.New(\"arg list's length != 3\")\n\t\tpanic(err)\n\t} else if body.StmtType() != BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.foreach = foreach\n\tthis.body = body\n}\n\nfunc (this *DpuForeachStmt) Foreach() *expr.ArgList {\n\treturn this.foreach\n}\n\nfunc (this *DpuForeachStmt) Body() *Stmt {\n\treturn this.body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/empty_stmt.go",
    "content": "package stmt\n\ntype EmptyStmt struct {\n}\n\nfunc (this *EmptyStmt) Init() {\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/expr_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype ExprStmt struct {\n\texpr *expr.Expr\n}\n\nfunc (this *ExprStmt) Init(expr_ *expr.Expr) {\n\tthis.expr = expr_\n}\n\nfunc (this *ExprStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/for_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype ForStmt struct {\n\tinitialization *Stmt\n\tcondition      *expr.Expr\n\tupdate         *Stmt\n\tbody           *Stmt\n}\n\nfunc (this *ForStmt) Init(initialization *Stmt, condition *expr.Expr, update *Stmt, body *Stmt) {\n\tif body.StmtType() != BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.initialization = initialization\n\tthis.condition = condition\n\tthis.update = update\n\tthis.body = body\n}\n\nfunc (this *ForStmt) Initialization() *Stmt {\n\treturn this.initialization\n}\n\nfunc (this *ForStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *ForStmt) Update() *Stmt {\n\treturn this.update\n}\n\nfunc (this *ForStmt) Body() *Stmt {\n\treturn this.body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/if_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype IfStmt struct {\n\tif_condition *expr.Expr\n\tif_body      *Stmt\n\n\telse_if_conditions []*expr.Expr\n\telse_if_bodies     []*Stmt\n\n\telse_body *Stmt\n}\n\nfunc (this *IfStmt) Init(if_condition *expr.Expr, if_body *Stmt) {\n\tif if_body.StmtType() != BLOCK {\n\t\terr := errors.New(\"if body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.if_condition = if_condition\n\tthis.if_body = if_body\n\n\tthis.else_if_conditions = make([]*expr.Expr, 0)\n\tthis.else_if_bodies = make([]*Stmt, 0)\n\n\tthis.else_body = nil\n}\n\nfunc (this *IfStmt) IfCondition() *expr.Expr {\n\treturn this.if_condition\n}\n\nfunc (this *IfStmt) IfBody() *Stmt {\n\treturn this.if_body\n}\n\nfunc (this *IfStmt) NumElseIfs() int {\n\tif len(this.else_if_conditions) != len(this.else_if_bodies) {\n\t\terr := errors.New(\"lengths of else if conditions and bodies are different\")\n\t\tpanic(err)\n\t}\n\n\treturn len(this.else_if_conditions)\n}\n\nfunc (this *IfStmt) ElseIfCondition(pos int) *expr.Expr {\n\treturn this.else_if_conditions[pos]\n}\n\nfunc (this *IfStmt) ElseIfBody(pos int) *Stmt {\n\treturn this.else_if_bodies[pos]\n}\n\nfunc (this *IfStmt) AppendElseIf(condition *expr.Expr, body *Stmt) {\n\tif body.StmtType() != BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.else_if_conditions = append(this.else_if_conditions, condition)\n\tthis.else_if_bodies = append(this.else_if_bodies, body)\n}\n\nfunc (this *IfStmt) HasElseBody() bool {\n\treturn this.else_body != nil\n}\n\nfunc (this *IfStmt) ElseBody() *Stmt {\n\tif !this.HasElseBody() {\n\t\terr := errors.New(\"else body does not exist\")\n\t\tpanic(err)\n\t}\n\n\treturn this.else_body\n}\n\nfunc (this *IfStmt) SetElseBody(body *Stmt) {\n\tif this.HasElseBody() {\n\t\terr := errors.New(\"else body already exists\")\n\t\tpanic(err)\n\t} else if body.StmtType() != BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.else_body = body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/return_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype ReturnStmt struct {\n\tvalue *expr.Expr\n}\n\nfunc (this *ReturnStmt) InitWithoutValue() {\n\tthis.value = nil\n}\n\nfunc (this *ReturnStmt) InitWithValue(value *expr.Expr) {\n\tthis.value = value\n}\n\nfunc (this *ReturnStmt) HasValue() bool {\n\treturn this.value != nil\n}\n\nfunc (this *ReturnStmt) Value() *expr.Expr {\n\tif !this.HasValue() {\n\t\terr := errors.New(\"value does not exist\")\n\t\tpanic(err)\n\t}\n\n\treturn this.value\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/stmt.go",
    "content": "package stmt\n\ntype StmtType int\n\nconst (\n\tEMPTY StmtType = iota\n\tVAR_DECL\n\tVAR_DECL_INIT\n\tFOR\n\tDPU_FOREACH\n\tWHILE\n\tCONTINUE\n\tBREAK\n\tIF\n\tRETURN\n\tEXPR\n\tBLOCK\n)\n\ntype Stmt struct {\n\tstmt_type StmtType\n\n\tempty_stmt         *EmptyStmt\n\tvar_decl_stmt      *VarDeclStmt\n\tvar_decl_init_stmt *VarDeclInitStmt\n\tfor_stmt           *ForStmt\n\tdpu_foreach_stmt   *DpuForeachStmt\n\twhile_stmt         *WhileStmt\n\tcontinue_stmt      *ContinueStmt\n\tbreak_stmt         *BreakStmt\n\tif_stmt            *IfStmt\n\treturn_stmt        *ReturnStmt\n\texpr_stmt          *ExprStmt\n\tblock_stmt         *BlockStmt\n}\n\nfunc (this *Stmt) InitEmptyStmt(empty_stmt *EmptyStmt) {\n\tthis.stmt_type = EMPTY\n\n\tthis.empty_stmt = empty_stmt\n}\n\nfunc (this *Stmt) InitVarDeclStmt(var_decl_stmt *VarDeclStmt) {\n\tthis.stmt_type = VAR_DECL\n\n\tthis.var_decl_stmt = var_decl_stmt\n}\n\nfunc (this *Stmt) InitVarDeclInitStmt(var_decl_init_stmt *VarDeclInitStmt) {\n\tthis.stmt_type = VAR_DECL_INIT\n\n\tthis.var_decl_init_stmt = var_decl_init_stmt\n}\n\nfunc (this *Stmt) InitForStmt(for_stmt *ForStmt) {\n\tthis.stmt_type = FOR\n\n\tthis.for_stmt = for_stmt\n}\n\nfunc (this *Stmt) InitDpuForeachStmt(dpu_foreach_stmt *DpuForeachStmt) {\n\tthis.stmt_type = DPU_FOREACH\n\n\tthis.dpu_foreach_stmt = dpu_foreach_stmt\n}\n\nfunc (this *Stmt) InitWhileStmt(while_stmt *WhileStmt) {\n\tthis.stmt_type = WHILE\n\n\tthis.while_stmt = while_stmt\n}\n\nfunc (this *Stmt) InitContinueStmt(continue_stmt *ContinueStmt) {\n\tthis.stmt_type = CONTINUE\n\n\tthis.continue_stmt = continue_stmt\n}\n\nfunc (this *Stmt) InitBreakStmt(break_stmt *BreakStmt) {\n\tthis.stmt_type = BREAK\n\n\tthis.break_stmt = break_stmt\n}\n\nfunc (this *Stmt) InitIfStmt(if_stmt *IfStmt) {\n\tthis.stmt_type = IF\n\n\tthis.if_stmt = if_stmt\n}\n\nfunc (this *Stmt) InitReturnStmt(return_stmt *ReturnStmt) {\n\tthis.stmt_type = RETURN\n\n\tthis.return_stmt = return_stmt\n}\n\nfunc (this *Stmt) InitExprStmt(expr_stmt *ExprStmt) {\n\tthis.stmt_type = EXPR\n\n\tthis.expr_stmt = expr_stmt\n}\n\nfunc (this *Stmt) InitBlockStmt(block_stmt *BlockStmt) {\n\tthis.stmt_type = BLOCK\n\n\tthis.block_stmt = block_stmt\n}\n\nfunc (this *Stmt) StmtType() StmtType {\n\treturn this.stmt_type\n}\n\nfunc (this *Stmt) EmptyStmt() *EmptyStmt {\n\treturn this.empty_stmt\n}\n\nfunc (this *Stmt) VarDeclStmt() *VarDeclStmt {\n\treturn this.var_decl_stmt\n}\n\nfunc (this *Stmt) VarDeclInitStmt() *VarDeclInitStmt {\n\treturn this.var_decl_init_stmt\n}\n\nfunc (this *Stmt) ForStmt() *ForStmt {\n\treturn this.for_stmt\n}\n\nfunc (this *Stmt) DpuForeachStmt() *DpuForeachStmt {\n\treturn this.dpu_foreach_stmt\n}\n\nfunc (this *Stmt) WhileStmt() *WhileStmt {\n\treturn this.while_stmt\n}\n\nfunc (this *Stmt) ContinueStmt() *ContinueStmt {\n\treturn this.continue_stmt\n}\n\nfunc (this *Stmt) BreakStmt() *BreakStmt {\n\treturn this.break_stmt\n}\n\nfunc (this *Stmt) IfStmt() *IfStmt {\n\treturn this.if_stmt\n}\n\nfunc (this *Stmt) ReturnStmt() *ReturnStmt {\n\treturn this.return_stmt\n}\n\nfunc (this *Stmt) ExprStmt() *ExprStmt {\n\treturn this.expr_stmt\n}\n\nfunc (this *Stmt) BlockStmt() *BlockStmt {\n\treturn this.block_stmt\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/var_decl_init_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype VarDeclInitStmt struct {\n\ttype_specifier *type_specifier.TypeSpecifier\n\tidentifier     *lexer.Token\n\texpr           *expr.Expr\n}\n\nfunc (this *VarDeclInitStmt) Init(\n\ttype_specifier *type_specifier.TypeSpecifier,\n\tidentifier *lexer.Token,\n\texpr_ *expr.Expr,\n) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier = type_specifier\n\tthis.identifier = identifier\n\tthis.expr = expr_\n}\n\nfunc (this *VarDeclInitStmt) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *VarDeclInitStmt) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n\nfunc (this *VarDeclInitStmt) Expr() *expr.Expr {\n\treturn this.expr\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/var_decl_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n\t\"uPIMulator/src/host/interpreter/parser/type_specifier\"\n)\n\ntype VarDeclStmt struct {\n\ttype_specifier *type_specifier.TypeSpecifier\n\tidentifier     *lexer.Token\n}\n\nfunc (this *VarDeclStmt) Init(\n\ttype_specifier *type_specifier.TypeSpecifier,\n\tidentifier *lexer.Token,\n) {\n\tif identifier.TokenType() != lexer.IDENTIFIER {\n\t\terr := errors.New(\"identifier's token type is not identifier\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier = type_specifier\n\tthis.identifier = identifier\n}\n\nfunc (this *VarDeclStmt) TypeSpecifier() *type_specifier.TypeSpecifier {\n\treturn this.type_specifier\n}\n\nfunc (this *VarDeclStmt) Identifier() *lexer.Token {\n\treturn this.identifier\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/stmt/while_stmt.go",
    "content": "package stmt\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/parser/expr\"\n)\n\ntype WhileStmt struct {\n\tcondition *expr.Expr\n\tbody      *Stmt\n}\n\nfunc (this *WhileStmt) Init(condition *expr.Expr, body *Stmt) {\n\tif body.StmtType() != BLOCK {\n\t\terr := errors.New(\"body's stmt type is not block\")\n\t\tpanic(err)\n\t}\n\n\tthis.condition = condition\n\tthis.body = body\n}\n\nfunc (this *WhileStmt) Condition() *expr.Expr {\n\treturn this.condition\n}\n\nfunc (this *WhileStmt) Body() *Stmt {\n\treturn this.body\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/table.go",
    "content": "package parser\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype Table struct {\n\trules []*Rule\n\n\tstack *Stack\n}\n\nfunc (this *Table) Init(stack *Stack) {\n\tthis.rules = make([]*Rule, 0)\n\n\tthis.stack = stack\n}\n\nfunc (this *Table) AddRule(rule *Rule) {\n\tthis.rules = append(this.rules, rule)\n}\n\nfunc (this *Table) IsReducible(token *lexer.Token) bool {\n\tfor i := 0; i < this.stack.Length(); i++ {\n\t\tstack_items := this.stack.Front(this.stack.Length() - i)\n\n\t\tfor _, rule := range this.rules {\n\t\t\tif rule.IsReducible(stack_items, token) {\n\t\t\t\treturn true\n\t\t\t}\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Table) Reduce(token *lexer.Token) {\n\tfor i := 0; i < this.stack.Length(); i++ {\n\t\tstack_items := this.stack.Front(this.stack.Length() - i)\n\n\t\tfor _, rule := range this.rules {\n\t\t\tif rule.IsReducible(stack_items, token) {\n\t\t\t\tstack_item := rule.Reduce(stack_items, token)\n\n\t\t\t\tthis.stack.Pop(len(stack_items))\n\t\t\t\tthis.stack.Push(stack_item)\n\n\t\t\t\treturn\n\t\t\t}\n\t\t}\n\t}\n\n\terr := errors.New(\"stack is not reducible\")\n\tpanic(err)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/interpreter/parser/type_specifier/type_specifier.go",
    "content": "package type_specifier\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/interpreter/lexer\"\n)\n\ntype TypeSpecifierType int\n\nconst (\n\tVOID TypeSpecifierType = iota\n\tCHAR\n\tSHORT\n\tINT\n\tLONG\n\tSTRUCT\n)\n\ntype TypeSpecifier struct {\n\ttype_specifier_type TypeSpecifierType\n\tstruct_identifier   *lexer.Token\n\tnum_stars           int\n}\n\nfunc (this *TypeSpecifier) InitPrimitive(type_specifier_type TypeSpecifierType) {\n\tif type_specifier_type == STRUCT {\n\t\terr := errors.New(\"type specifier type is a struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier_type = type_specifier_type\n\tthis.struct_identifier = nil\n\tthis.num_stars = 0\n}\n\nfunc (this *TypeSpecifier) InitStruct(\n\ttype_specifier_type TypeSpecifierType,\n\tstruct_identifier *lexer.Token,\n) {\n\tif type_specifier_type != STRUCT {\n\t\terr := errors.New(\"type specifier type is not a struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_specifier_type = type_specifier_type\n\tthis.struct_identifier = struct_identifier\n\tthis.num_stars = 0\n}\n\nfunc (this *TypeSpecifier) TypeSpecifierType() TypeSpecifierType {\n\treturn this.type_specifier_type\n}\n\nfunc (this *TypeSpecifier) StructIdentifier() *lexer.Token {\n\tif this.struct_identifier == nil {\n\t\terr := errors.New(\"struct identifier == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.struct_identifier\n}\n\nfunc (this *TypeSpecifier) NumStars() int {\n\treturn this.num_stars\n}\n\nfunc (this *TypeSpecifier) AddStar() {\n\tthis.num_stars++\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/arena/arena.go",
    "content": "package arena\n\nimport (\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/host/vm/base\"\n\t\"uPIMulator/src/host/vm/type_system\"\n)\n\ntype Arena struct {\n\tpool *Pool\n}\n\nfunc (this *Arena) Init() {\n\tthis.pool = new(Pool)\n\tthis.pool.Init()\n}\n\nfunc (this *Arena) Pool() *Pool {\n\treturn this.pool\n}\n\nfunc (this *Arena) NewChar(value int64) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, 1)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tbyte_stream.Append(uint8(value))\n\n\tthis.pool.Memory().Write(object.Address(), 1, byte_stream)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewShort(value int64) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, 2)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tbyte_stream.Append(uint8(value & 0xFF))\n\tbyte_stream.Append(uint8((value >> 8) & 0xFF))\n\tthis.pool.Memory().Write(object.Address(), 2, byte_stream)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewInt(value int64) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, 4)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tbyte_stream.Append(uint8(value & 0xFF))\n\tbyte_stream.Append(uint8((value >> 8) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 16) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 24) & 0xFF))\n\tthis.pool.Memory().Write(object.Address(), 4, byte_stream)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewLong(value int64) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, 8)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tbyte_stream.Append(uint8(value & 0xFF))\n\tbyte_stream.Append(uint8((value >> 8) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 16) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 24) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 32) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 40) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 48) & 0xFF))\n\tbyte_stream.Append(uint8((value >> 56) & 0xFF))\n\tthis.pool.Memory().Write(object.Address(), 8, byte_stream)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewString(value string) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, int64(len(value)))\n\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\tencoded_byte_stream := ascii_encoder.Encode(value)\n\n\tthis.pool.Memory().Write(object.Address(), encoded_byte_stream.Size(), encoded_byte_stream)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.STRING, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewStruct(struct_name string, size int64) *base.Object {\n\tobject := this.pool.Alloc(base.TEMPORARY, size)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitStruct(type_system.STRUCT, struct_name, 0)\n\n\tobject.SetTypeVariable(type_variable)\n\n\treturn object\n}\n\nfunc (this *Arena) NewPointer(size int64) *base.Object {\n\tobject := this.pool.Alloc(base.UNTEMPORARY, size)\n\n\treturn object\n}\n\nfunc (this *Arena) Free(address int64) {\n\tthis.pool.Free(address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/arena/garbage_collector.go",
    "content": "package arena\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/base\"\n\t\"uPIMulator/src/host/vm/frame\"\n\t\"uPIMulator/src/host/vm/symbol\"\n\t\"uPIMulator/src/host/vm/type_system\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype GarbageCollector struct {\n\tcycle     int64\n\tthreshold int64\n\n\tarena       *Arena\n\tframe_chain *frame.FrameChain\n\tregistry    *type_system.TypeRegistry\n}\n\nfunc (this *GarbageCollector) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.cycle = 0\n\tthis.threshold = config_loader.GarbageCollectionThreshold()\n}\n\nfunc (this *GarbageCollector) ConnectArena(arena *Arena) {\n\tthis.arena = arena\n}\n\nfunc (this *GarbageCollector) ConnectFrameChain(frame_chain *frame.FrameChain) {\n\tthis.frame_chain = frame_chain\n}\n\nfunc (this *GarbageCollector) ConnectRegistry(registry *type_system.TypeRegistry) {\n\tthis.registry = registry\n}\n\nfunc (this *GarbageCollector) MarkAndSweep() {\n\tif this.cycle > this.threshold {\n\t\tobjects := this.Mark()\n\t\tthis.Sweep(objects)\n\n\t\tthis.cycle = 0\n\t}\n\n\tthis.cycle++\n}\n\nfunc (this *GarbageCollector) Mark() []*base.Object {\n\tobjects := make([]*base.Object, 0)\n\tfor _, symbol_ := range this.frame_chain.Symbols() {\n\t\tobjects = append(objects, this.ChaseSymbol(symbol_)...)\n\t}\n\treturn objects\n}\n\nfunc (this *GarbageCollector) Sweep(objects []*base.Object) {\n\tfor _, obj := range this.arena.Pool().Objects() {\n\t\tif obj.ObjectType() == base.TEMPORARY && !this.IsMarked(obj, objects) &&\n\t\t\t!this.frame_chain.HasObject(obj.Address()) &&\n\t\t\tthis.arena.Pool().HasObject(obj.Address()) {\n\t\t\tthis.arena.Free(obj.Address())\n\t\t}\n\t}\n}\n\nfunc (this *GarbageCollector) ChaseSymbol(symbol_ *symbol.Symbol) []*base.Object {\n\tobjects := make([]*base.Object, 0)\n\n\ttype_variable := symbol_.TypeVariable()\n\n\tif type_variable.TypeVariableType() == type_system.VOID {\n\t\tif type_variable.NumStars() == 0 {\n\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else if type_variable.TypeVariableType() == type_system.CHAR {\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else if type_variable.TypeVariableType() == type_system.SHORT {\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else if type_variable.TypeVariableType() == type_system.INT {\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else if type_variable.TypeVariableType() == type_system.LONG {\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else if type_variable.TypeVariableType() == type_system.STRUCT {\n\t\tobjects = append(objects, this.ChaseObject(symbol_.Object())...)\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn objects\n}\n\nfunc (this *GarbageCollector) ChaseObject(object *base.Object) []*base.Object {\n\tobjects := make([]*base.Object, 0)\n\n\tobjects = append(objects, object)\n\n\tif !object.HasTypeVariable() {\n\t\terr := errors.New(\"object does not have a type variable\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := object.TypeVariable()\n\n\tif type_variable.TypeVariableType() == type_system.VOID {\n\t\tif type_variable.NumStars() == 0 {\n\t\t\terr := errors.New(\"num stars == 0\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t}\n\t} else if type_variable.TypeVariableType() == type_system.CHAR {\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t}\n\t} else if type_variable.TypeVariableType() == type_system.SHORT {\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t}\n\t} else if type_variable.TypeVariableType() == type_system.INT {\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t}\n\t} else if type_variable.TypeVariableType() == type_system.LONG {\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t}\n\t} else if type_variable.TypeVariableType() == type_system.STRUCT {\n\t\tif type_variable.NumStars() > 0 {\n\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t} else {\n\t\t\tstruct_name := type_variable.StructName()\n\n\t\t\tskeleton := this.registry.Skeleton(struct_name)\n\n\t\t\tfor i, field := range skeleton.Fields() {\n\t\t\t\tif i == 0 {\n\t\t\t\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\t\t\t\tvalue := this.arena.Pool().Memory().Read(object.Address(), 4).SignedValue()\n\t\t\t\t\t\tobjects = append(objects, this.ChasePointer(value)...)\n\t\t\t\t\t} else {\n\t\t\t\t\t\tobjects = append(objects, this.arena.Pool().Object(object.Address()))\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tfield_offset := this.registry.FieldOffset(skeleton.Name(), field.Name())\n\n\t\t\t\t\tfield_address := object.Address() + field_offset\n\n\t\t\t\t\tif this.arena.Pool().HasObject(field_address) {\n\t\t\t\t\t\tfield_object := this.arena.Pool().Object(field_address)\n\t\t\t\t\t\tobjects = append(objects, this.ChaseObject(field_object)...)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\treturn objects\n}\n\nfunc (this *GarbageCollector) ChasePointer(address int64) []*base.Object {\n\tobject := this.arena.Pool().Object(address)\n\treturn this.ChaseObject(object)\n}\n\nfunc (this *GarbageCollector) IsMarked(object *base.Object, objects []*base.Object) bool {\n\tfor _, obj := range objects {\n\t\tif obj == object {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/arena/memory.go",
    "content": "package arena\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype Memory struct {\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Memory) Init(size int64) {\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Memory) Size() int64 {\n\treturn this.byte_stream.Size()\n}\n\nfunc (this *Memory) Resize(size int64) {\n\tif size < this.byte_stream.Size() {\n\t\terr := errors.New(\"size < byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < size-this.byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Memory) Read(address int64, size int64) *encoding.ByteStream {\n\tfor address+size >= this.byte_stream.Size() {\n\t\tthis.Resize(2 * this.byte_stream.Size())\n\t}\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tbyte_stream.Append(this.byte_stream.Get(int(address + i)))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Memory) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor address+size >= this.byte_stream.Size() {\n\t\tthis.Resize(2 * this.byte_stream.Size())\n\t}\n\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Set(int(address+i), byte_stream.Get(int(i)))\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/arena/pool.go",
    "content": "package arena\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"slices\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/host/vm/base\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Pool struct {\n\toffset  int64\n\tobjects []*base.Object\n\tmemory  *Memory\n}\n\nfunc (this *Pool) Init() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.offset = config_loader.VmBankOffset()\n\n\tthis.objects = make([]*base.Object, 0)\n\n\tthis.memory = new(Memory)\n\tthis.memory.Init(config_loader.VmMemorySize())\n}\n\nfunc (this *Pool) Memory() *Memory {\n\treturn this.memory\n}\n\nfunc (this *Pool) Alloc(object_type base.ObjectType, size int64) *base.Object {\n\tcur_offset := this.offset\n\tif len(this.objects) == 0 {\n\t\tobject := new(base.Object)\n\t\tobject.Init(object_type, cur_offset, size)\n\t\tthis.objects = append(this.objects, object)\n\n\t\tthis.DoZeros(object)\n\n\t\treturn object\n\t} else {\n\t\tfor _, obj := range this.objects {\n\t\t\tif cur_offset+size <= obj.Address() {\n\t\t\t\tobject := new(base.Object)\n\t\t\t\tobject.Init(object_type, cur_offset, size)\n\t\t\t\tthis.objects = append(this.objects, object)\n\n\t\t\t\tsort_fn := func(obj1 *base.Object, obj2 *base.Object) int {\n\t\t\t\t\tif obj1.Address() < obj2.Address() {\n\t\t\t\t\t\treturn -1\n\t\t\t\t\t} else if obj1.Address() == obj2.Address() {\n\t\t\t\t\t\treturn 0\n\t\t\t\t\t} else {\n\t\t\t\t\t\treturn 1\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tslices.SortFunc(this.objects, sort_fn)\n\n\t\t\t\tthis.DoZeros(object)\n\n\t\t\t\treturn object\n\t\t\t} else {\n\t\t\t\tcur_offset = obj.Address() + obj.Size()\n\t\t\t}\n\t\t}\n\n\t\tobject := new(base.Object)\n\t\tobject.Init(object_type, cur_offset, size)\n\t\tthis.objects = append(this.objects, object)\n\n\t\tthis.DoZeros(object)\n\n\t\treturn object\n\t}\n}\n\nfunc (this *Pool) Free(address int64) {\n\tif !this.HasObject(address) {\n\t\terr_msg := fmt.Sprintf(\"object with address (%d) is not found\", address)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor i, object := range this.objects {\n\t\tif object.Address() == address {\n\t\t\tthis.objects = append(this.objects[:i], this.objects[i+1:]...)\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nfunc (this *Pool) HasObject(address int64) bool {\n\tfor _, object := range this.objects {\n\t\tif object.Address() == address {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Pool) Object(address int64) *base.Object {\n\tif !this.HasObject(address) {\n\t\terr_msg := fmt.Sprintf(\"object with address (%d) is not found\", address)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor _, object := range this.objects {\n\t\tif object.Address() == address {\n\t\t\treturn object\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *Pool) HasLastObject(address int64) bool {\n\tfor i := len(this.objects) - 1; i >= 0; i-- {\n\t\tobject := this.objects[i]\n\n\t\tif object.Address() == address {\n\t\t\treturn true\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *Pool) LastObject(address int64) *base.Object {\n\tif !this.HasLastObject(address) {\n\t\terr_msg := fmt.Sprintf(\"object with address (%d) is not found\", address)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor i := len(this.objects) - 1; i >= 0; i-- {\n\t\tobject := this.objects[i]\n\n\t\tif object.Address() == address {\n\t\t\treturn object\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *Pool) Objects() []*base.Object {\n\treturn this.objects\n}\n\nfunc (this *Pool) DoZeros(object *base.Object) {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < object.Size(); i++ {\n\t\tbyte_stream.Append(0)\n\t}\n\n\tthis.memory.Write(object.Address(), object.Size(), byte_stream)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/bank_cycle_job.go",
    "content": "package vm\n\nimport (\n\t\"uPIMulator/src/host/vm/dram/bank\"\n)\n\ntype BankCycleJob struct {\n\tbank *bank.Bank\n}\n\nfunc (this *BankCycleJob) Init(bank_ *bank.Bank) {\n\tthis.bank = bank_\n}\n\nfunc (this *BankCycleJob) Execute() {\n\tthis.bank.Cycle()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/base/object.go",
    "content": "package base\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/type_system\"\n)\n\ntype ObjectType int\n\nconst (\n\tTEMPORARY ObjectType = iota\n\tUNTEMPORARY\n)\n\ntype Object struct {\n\tobject_type   ObjectType\n\ttype_variable *type_system.TypeVariable\n\n\taddress int64\n\tsize    int64\n}\n\nfunc (this *Object) Init(object_type ObjectType, address int64, size int64) {\n\tif address <= 0 {\n\t\terr := errors.New(\"address <= 0\")\n\t\tpanic(err)\n\t} else if size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.object_type = object_type\n\n\tthis.address = address\n\tthis.size = size\n}\n\nfunc (this *Object) ObjectType() ObjectType {\n\treturn this.object_type\n}\n\nfunc (this *Object) HasTypeVariable() bool {\n\treturn this.type_variable != nil\n}\n\nfunc (this *Object) TypeVariable() *type_system.TypeVariable {\n\treturn this.type_variable\n}\n\nfunc (this *Object) SetTypeVariable(type_variable *type_system.TypeVariable) {\n\tif this.type_variable != nil {\n\t\terr := errors.New(\"type variable != nil\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_variable = type_variable\n}\n\nfunc (this *Object) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Object) Size() int64 {\n\treturn this.size\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dpu_compute_cycle_job.go",
    "content": "package vm\n\nimport (\n\t\"uPIMulator/src/device/simulator/dpu\"\n\t\"uPIMulator/src/device/simulator/dpu/logic\"\n)\n\ntype DpuComputeCycleJob struct {\n\tsys_end int64\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DpuComputeCycleJob) Init(sys_end int64, dpu_ *dpu.Dpu) {\n\tthis.sys_end = sys_end\n\n\tthis.dpu = dpu_\n}\n\nfunc (this *DpuComputeCycleJob) Execute() {\n\tfor !this.dpu.IsZombie() {\n\t\tfor _, thread := range this.dpu.Threads() {\n\t\t\tif thread.RegFile().ReadPcReg() == this.sys_end && thread.ThreadState() == logic.SLEEP {\n\t\t\t\tthis.dpu.ThreadScheduler().Shutdown(thread.ThreadId())\n\t\t\t}\n\t\t}\n\n\t\tthis.dpu.Cycle()\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dpu_cycle_job.go",
    "content": "package vm\n\nimport (\n\t\"uPIMulator/src/device/simulator/dpu\"\n)\n\ntype DpuCycleJob struct {\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DpuCycleJob) Init(dpu_ *dpu.Dpu) {\n\tthis.dpu = dpu_\n}\n\nfunc (this *DpuCycleJob) Execute() {\n\tthis.dpu.Cycle()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dpu_load_job.go",
    "content": "package vm\n\nimport (\n\t\"uPIMulator/src/device/simulator/dpu\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/program\"\n)\n\ntype DpuLoadJob struct {\n\ttask *program.Task\n\n\tdpu *dpu.Dpu\n}\n\nfunc (this *DpuLoadJob) Init(task *program.Task, dpu_ *dpu.Dpu) {\n\tthis.task = task\n\tthis.dpu = dpu_\n}\n\nfunc (this *DpuLoadJob) Execute() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.dpu.Dma().\n\t\tTransferToAtomic(config_loader.AtomicOffset(), this.task.Atomic().Size(), this.task.Atomic())\n\tthis.dpu.Dma().\n\t\tTransferToIram(config_loader.IramOffset(), this.task.Iram().Size(), this.task.Iram())\n\tthis.dpu.Dma().\n\t\tTransferToWram(config_loader.WramOffset(), this.task.Wram().Size(), this.task.Wram())\n\tthis.dpu.Dma().\n\t\tTransferToMram(config_loader.MramOffset(), this.task.Mram().Size(), this.task.Mram())\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/array.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Array struct {\n\tchannel_id int\n\trank_id    int\n\tbank_id    int\n\n\taddress int64\n\tsize    int64\n\n\twordline_size int64\n\twordlines     []*Wordline\n}\n\nfunc (this *Array) Init(command_line_parser *misc.CommandLineParser) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.address = 0\n\tthis.size = config_loader.VmBankSize()\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tif this.wordline_size <= 0 {\n\t\terr := errors.New(\"wordline size <= 0\")\n\t\tpanic(err)\n\t} else if this.address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t} else if this.size%this.wordline_size != 0 {\n\t\terr := errors.New(\"size is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\tthis.wordlines = make([]*Wordline, 0)\n\tnum_wordlines := int(this.size / this.wordline_size)\n\tfor i := 0; i < num_wordlines; i++ {\n\t\twordline := new(Wordline)\n\t\twordline.Init(this.address+int64(i)*this.wordline_size, this.wordline_size)\n\t\tthis.wordlines = append(this.wordlines, wordline)\n\t}\n}\n\nfunc (this *Array) Fini() {\n\tfor _, wordline := range this.wordlines {\n\t\twordline.Fini()\n\t}\n}\n\nfunc (this *Array) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *Array) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *Array) Read(address int64) *encoding.ByteStream {\n\treturn this.wordlines[this.Index(address)].Read()\n}\n\nfunc (this *Array) Write(address int64, byte_stream *encoding.ByteStream) {\n\tthis.wordlines[this.Index(address)].Write(byte_stream)\n}\n\nfunc (this *Array) Index(address int64) int {\n\tif address < this.address {\n\t\terr := errors.New(\"address < MRAM offset\")\n\t\tpanic(err)\n\t} else if address+this.wordline_size > this.address+this.size {\n\t\terr := errors.New(\"address + wordline size > MRAM offset + MRAM size\")\n\t\tpanic(err)\n\t} else if address%this.wordline_size != 0 {\n\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int((address - this.address) / this.wordline_size)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/bank.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Bank struct {\n\tchannel_id int\n\trank_id    int\n\tbank_id    int\n\n\twordline_size int64\n\n\tarray      *Array\n\trow_buffer *RowBuffer\n\n\tinput_q *MemoryCommandQ\n\tready_q *MemoryCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *Bank) Init(\n\tchannel_id int,\n\trank_id int,\n\tbank_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if bank_id < 0 {\n\t\terr := errors.New(\"bank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.bank_id = bank_id\n\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.array = new(Array)\n\tthis.array.Init(command_line_parser)\n\n\tthis.row_buffer = new(RowBuffer)\n\tthis.row_buffer.Init(channel_id, rank_id, bank_id, command_line_parser)\n\tthis.row_buffer.ConnectArray(this.array)\n\n\tthis.input_q = new(MemoryCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tname := fmt.Sprintf(\"VmBank[%d_%d_%d]\", channel_id, rank_id, bank_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *Bank) Fini() {\n\tthis.array.Fini()\n\tthis.row_buffer.Fini()\n\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Bank) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Bank) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Bank) DpuId() int {\n\treturn this.bank_id\n}\n\nfunc (this *Bank) RowBuffer() *RowBuffer {\n\treturn this.row_buffer\n}\n\nfunc (this *Bank) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *Bank) IsEmpty() bool {\n\treturn this.row_buffer.IsEmpty() && this.input_q.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *Bank) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Bank) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"bank cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(memory_command)\n}\n\nfunc (this *Bank) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Bank) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"bank cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Bank) Read(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.array.Read(cur_wordline_address)\n\n\t\tfor i := cur_offset; i < cur_offset+cur_size; i++ {\n\t\t\tbyte_stream.Append(mram_byte_stream.Get(int(i)))\n\t\t}\n\n\t\tcur_address += cur_size\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Bank) Write(address int64, size int64, byte_stream *encoding.ByteStream) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tcur_byte_stream_offset := int64(0)\n\tfor cur_address := address; cur_address < address+size; {\n\t\tcur_wordline_address := this.WordlineAddress(cur_address)\n\t\tcur_size := this.Min(cur_wordline_address+this.wordline_size, address+size) - cur_address\n\t\tcur_offset := cur_address % this.wordline_size\n\n\t\tmram_byte_stream := this.array.Read(cur_wordline_address)\n\n\t\tfor i := int64(0); i < cur_size; i++ {\n\t\t\tmram_byte_stream.Set(int(i+cur_offset), byte_stream.Get(int(i+cur_byte_stream_offset)))\n\t\t}\n\n\t\tthis.array.Write(cur_wordline_address, mram_byte_stream)\n\n\t\tcur_address += cur_size\n\t\tcur_byte_stream_offset += cur_size\n\t}\n}\n\nfunc (this *Bank) Flush() {\n\tthis.row_buffer.Flush()\n}\n\nfunc (this *Bank) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceRowBuffer()\n\n\tthis.row_buffer.Cycle()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.stat_factory.Increment(\"vm_memory_cycle\", 1)\n}\n\nfunc (this *Bank) ServiceInputQ() {\n\tif this.input_q.CanPop(1) && this.row_buffer.CanPush() {\n\t\tmemory_command := this.input_q.Pop()\n\t\tthis.row_buffer.Push(memory_command)\n\t}\n}\n\nfunc (this *Bank) ServiceRowBuffer() {\n\tif this.row_buffer.CanPop() && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.row_buffer.Pop()\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\treturn\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\treturn\n\t\t} else if memory_operation == READ {\n\t\t\taddress := memory_command.BankAddress()\n\t\t\tsize := memory_command.Size()\n\t\t\tbyte_stream := memory_command.ByteStream()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetByteStream(address, size, byte_stream)\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else if memory_operation == WRITE {\n\t\t\taddress := memory_command.BankAddress()\n\t\t\tsize := memory_command.Size()\n\n\t\t\tdma_command := memory_command.DmaCommand()\n\t\t\tdma_command.SetAck(address, size)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.ready_q.Push(memory_command)\n\t}\n}\n\nfunc (this *Bank) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *Bank) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/dma_command.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype DmaCommand struct {\n\tmemory_operation MemoryOperation\n\n\tsegment *Segment\n\n\tbyte_stream *encoding.ByteStream\n\tacks        []bool\n\n\ttransfer_command *TransferCommand\n}\n\nfunc (this *DmaCommand) InitRead(segment *Segment, transfer_command *TransferCommand) {\n\tthis.memory_operation = READ\n\n\tthis.segment = segment\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < segment.Size(); i++ {\n\t\tthis.byte_stream.Append(0)\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.transfer_command = transfer_command\n}\n\nfunc (this *DmaCommand) InitWrite(segment *Segment, transfer_command *TransferCommand) {\n\tthis.memory_operation = WRITE\n\n\tthis.segment = segment\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tthis.acks = make([]bool, 0)\n\tfor i := int64(0); i < segment.Size(); i++ {\n\t\tthis.byte_stream.Append(0)\n\t\tthis.acks = append(this.acks, false)\n\t}\n\n\tthis.transfer_command = transfer_command\n}\n\nfunc (this *DmaCommand) Fini() {\n\tif !this.IsReady() {\n\t\terr := errors.New(\"DMA command is not ready\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *DmaCommand) Segment() *Segment {\n\treturn this.segment\n}\n\nfunc (this *DmaCommand) ByteStream(bank_address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(bank_address) + int(i)\n\n\t\tbyte_stream.Append(this.byte_stream.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *DmaCommand) SetByteStream(\n\tbank_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(bank_address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *DmaCommand) SetAck(bank_address int64, size int64) {\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(bank_address) + int(i)\n\n\t\tif this.acks[index] {\n\t\t\terr := errors.New(\"ACK is already set\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.acks[index] = true\n\t}\n}\n\nfunc (this *DmaCommand) IsReady() bool {\n\tfor _, ack := range this.acks {\n\t\tif !ack {\n\t\t\treturn false\n\t\t}\n\t}\n\treturn true\n}\n\nfunc (this *DmaCommand) TransferCommand() *TransferCommand {\n\treturn this.transfer_command\n}\n\nfunc (this *DmaCommand) Index(bank_address int64) int {\n\tif bank_address < this.segment.BankAddress() {\n\t\terr := errors.New(\"bank address < DMA command's segment's bank address\")\n\t\tpanic(err)\n\t} else if bank_address >= this.segment.BankAddress()+this.segment.Size() {\n\t\terr := errors.New(\"bank address >= DMA command's segment's bank address + DMA command's size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(bank_address - this.segment.BankAddress())\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/dma_command_q.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n)\n\ntype DmaCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tdma_commands []*DmaCommand\n\tcycles       []int64\n}\n\nfunc (this *DmaCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.dma_commands = make([]*DmaCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *DmaCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"DMA command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *DmaCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *DmaCommandQ) Length() int {\n\treturn len(this.dma_commands)\n}\n\nfunc (this *DmaCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *DmaCommandQ) IsEmpty() bool {\n\treturn len(this.dma_commands) == 0\n}\n\nfunc (this *DmaCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.dma_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Push(dma_command *DmaCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *DmaCommandQ) PushWithTimer(dma_command *DmaCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"DMA command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.dma_commands = append(this.dma_commands, dma_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *DmaCommandQ) CanPop(num_items int) bool {\n\tif len(this.dma_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *DmaCommandQ) Pop() *DmaCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"DMA command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tdma_command := this.dma_commands[0]\n\n\tthis.dma_commands = this.dma_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn dma_command\n}\n\nfunc (this *DmaCommandQ) Front(pos int) (*DmaCommand, int64) {\n\treturn this.dma_commands[pos], this.cycles[pos]\n}\n\nfunc (this *DmaCommandQ) Remove(pos int) {\n\tthis.dma_commands = append(this.dma_commands[:pos], this.dma_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *DmaCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/memory_command.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype MemoryOperation int\n\nconst (\n\tACTIVATION MemoryOperation = iota\n\tREAD\n\tWRITE\n\tPRECHARGE\n)\n\ntype MemoryCommand struct {\n\tmemory_operation MemoryOperation\n\tbank_address     int64\n\tsize             int64\n\tbyte_stream      *encoding.ByteStream\n\tdma_command      *DmaCommand\n}\n\nfunc (this *MemoryCommand) InitActivation(memory_operation MemoryOperation, bank_address int64) {\n\tthis.memory_operation = memory_operation\n\tthis.bank_address = bank_address\n\tthis.size = 0\n\tthis.byte_stream = nil\n\tthis.dma_command = nil\n}\n\nfunc (this *MemoryCommand) InitRead(\n\tmemory_operation MemoryOperation,\n\tbank_address int64,\n\tsize int64,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != READ {\n\t\terr := errors.New(\"DMA operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.bank_address = bank_address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) InitWrite(\n\tmemory_operation MemoryOperation,\n\tbank_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n\tdma_command *DmaCommand,\n) {\n\tif memory_operation != WRITE {\n\t\terr := errors.New(\"memory operation != WRITE\")\n\t\tpanic(err)\n\t} else if dma_command.MemoryOperation() != WRITE {\n\t\terr := errors.New(\"DMA operation != WRITE\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_operation = memory_operation\n\tthis.bank_address = bank_address\n\tthis.size = size\n\tthis.byte_stream = byte_stream\n\tthis.dma_command = dma_command\n}\n\nfunc (this *MemoryCommand) MemoryOperation() MemoryOperation {\n\treturn this.memory_operation\n}\n\nfunc (this *MemoryCommand) BankAddress() int64 {\n\treturn this.bank_address\n}\n\nfunc (this *MemoryCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *MemoryCommand) ByteStream() *encoding.ByteStream {\n\tif this.byte_stream == nil {\n\t\terr := errors.New(\"byte stream == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.byte_stream\n}\n\nfunc (this *MemoryCommand) SetByteStream(byte_stream *encoding.ByteStream) {\n\tif this.memory_operation != READ {\n\t\terr := errors.New(\"memory operation != READ\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *MemoryCommand) DmaCommand() *DmaCommand {\n\tif this.dma_command == nil {\n\t\terr := errors.New(\"DMA command == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn this.dma_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/memory_command_q.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n)\n\ntype MemoryCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tmemory_commands []*MemoryCommand\n\tcycles          []int64\n}\n\nfunc (this *MemoryCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.memory_commands = make([]*MemoryCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *MemoryCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *MemoryCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *MemoryCommandQ) Length() int {\n\treturn len(this.memory_commands)\n}\n\nfunc (this *MemoryCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *MemoryCommandQ) IsEmpty() bool {\n\treturn len(this.memory_commands) == 0\n}\n\nfunc (this *MemoryCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.memory_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *MemoryCommandQ) PushWithTimer(memory_command *MemoryCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"memory command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.memory_commands = append(this.memory_commands, memory_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *MemoryCommandQ) CanPop(num_items int) bool {\n\tif len(this.memory_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *MemoryCommandQ) Pop() *MemoryCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"memory command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tmemory_command := this.memory_commands[0]\n\n\tthis.memory_commands = this.memory_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn memory_command\n}\n\nfunc (this *MemoryCommandQ) Front(pos int) (*MemoryCommand, int64) {\n\treturn this.memory_commands[pos], this.cycles[pos]\n}\n\nfunc (this *MemoryCommandQ) Remove(pos int) {\n\tthis.memory_commands = append(this.memory_commands[:pos], this.memory_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *MemoryCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/row_buffer.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype RowBuffer struct {\n\tchannel_id int\n\trank_id    int\n\tbank_id    int\n\n\tt_ras         int64\n\tt_rcd         int64\n\tt_cl          int64\n\tt_bl          int64\n\tt_rp          int64\n\twordline_size int64\n\n\tarray       *Array\n\trow_address *int64\n\trow_buffer  *encoding.ByteStream\n\n\tinput_q *MemoryCommandQ\n\tready_q *MemoryCommandQ\n\n\tactivation_q *MemoryCommandQ\n\tio_q         *MemoryCommandQ\n\tbus_q        *MemoryCommandQ\n\tprecharge_q  *MemoryCommandQ\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *RowBuffer) Init(\n\tchannel_id int,\n\trank_id int,\n\tbank_id int,\n\tcommand_line_parser *misc.CommandLineParser,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if bank_id < 0 {\n\t\terr := errors.New(\"bank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.bank_id = bank_id\n\n\tthis.t_ras = command_line_parser.IntParameter(\"t_ras\")\n\tthis.t_rcd = command_line_parser.IntParameter(\"t_rcd\")\n\tthis.t_cl = command_line_parser.IntParameter(\"t_cl\")\n\tthis.t_bl = command_line_parser.IntParameter(\"t_bl\")\n\tthis.t_rp = command_line_parser.IntParameter(\"t_rp\")\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\n\tthis.array = nil\n\tthis.row_address = nil\n\tthis.row_buffer = nil\n\n\tthis.input_q = new(MemoryCommandQ)\n\tthis.input_q.Init(1, 0)\n\n\tthis.ready_q = new(MemoryCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.activation_q = new(MemoryCommandQ)\n\tthis.activation_q.Init(1, this.t_ras)\n\n\tthis.io_q = new(MemoryCommandQ)\n\tthis.io_q.Init(1, this.t_cl)\n\n\tthis.bus_q = new(MemoryCommandQ)\n\tthis.bus_q.Init(1, this.t_bl)\n\n\tthis.precharge_q = new(MemoryCommandQ)\n\tthis.precharge_q.Init(1, this.t_rp)\n\n\tname := fmt.Sprintf(\"VmRowBuffer[%d_%d_%d]\", channel_id, rank_id, bank_id)\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(name)\n}\n\nfunc (this *RowBuffer) Fini() {\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n\tthis.activation_q.Fini()\n\tthis.io_q.Fini()\n\tthis.bus_q.Fini()\n\tthis.precharge_q.Fini()\n}\n\nfunc (this *RowBuffer) ConnectArray(array *Array) {\n\tif this.array != nil {\n\t\terr := errors.New(\"array is already connected\")\n\t\tpanic(err)\n\t}\n\n\tthis.array = array\n}\n\nfunc (this *RowBuffer) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *RowBuffer) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.ready_q.IsEmpty() && this.activation_q.IsEmpty() &&\n\t\tthis.io_q.IsEmpty() &&\n\t\tthis.bus_q.IsEmpty() &&\n\t\tthis.precharge_q.IsEmpty()\n}\n\nfunc (this *RowBuffer) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *RowBuffer) Push(memory_command *MemoryCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"row buffer cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(memory_command)\n}\n\nfunc (this *RowBuffer) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *RowBuffer) Pop() *MemoryCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"row buffer cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *RowBuffer) Flush() {\n\tif this.row_address != nil {\n\t\tthis.WriteToBank()\n\n\t\tthis.row_address = nil\n\t\tthis.row_buffer = nil\n\t}\n}\n\nfunc (this *RowBuffer) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceActivationQ()\n\tthis.ServiceIoQ()\n\tthis.ServiceBusQ()\n\tthis.ServicePrechargeQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tthis.activation_q.Cycle()\n\tthis.io_q.Cycle()\n\tthis.bus_q.Cycle()\n\tthis.precharge_q.Cycle()\n}\n\nfunc (this *RowBuffer) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tmemory_command, _ := this.input_q.Front(0)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == ACTIVATION {\n\t\t\tif this.activation_q.IsEmpty() && this.row_address == nil {\n\t\t\t\tthis.activation_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == READ {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == WRITE {\n\t\t\tif this.io_q.CanPush(1) && this.row_address != nil {\n\t\t\t\tthis.io_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else if memory_operation == PRECHARGE {\n\t\t\tif this.activation_q.IsEmpty() && this.io_q.IsEmpty() && this.bus_q.IsEmpty() && this.precharge_q.IsEmpty() {\n\t\t\t\tthis.precharge_q.Push(memory_command)\n\t\t\t\tthis.input_q.Pop()\n\t\t\t}\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServiceActivationQ() {\n\tif !this.activation_q.IsEmpty() {\n\t\tmemory_command, cycle := this.activation_q.Front(0)\n\n\t\tif cycle == this.t_ras-this.t_rcd {\n\t\t\tif this.row_address != nil {\n\t\t\t\terr := errors.New(\"row buffer is not precharged\")\n\t\t\t\tpanic(err)\n\t\t\t} else if memory_command.BankAddress()%this.wordline_size != 0 {\n\t\t\t\terr := errors.New(\"memory command is not aligned with wordline size\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.row_address = new(int64)\n\t\t\t*this.row_address = memory_command.BankAddress()\n\n\t\t\tthis.row_buffer = this.ReadFromBank()\n\t\t}\n\t}\n\n\tif this.activation_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.activation_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_activations\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceIoQ() {\n\tif this.io_q.CanPop(1) && this.bus_q.CanPush(1) {\n\t\tmemory_command := this.io_q.Pop()\n\t\tthis.bus_q.Push(memory_command)\n\t}\n}\n\nfunc (this *RowBuffer) ServiceBusQ() {\n\tif this.bus_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.bus_q.Pop()\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tmemory_operation := memory_command.MemoryOperation()\n\t\tif memory_operation == READ {\n\t\t\tbyte_stream := this.ReadFromRowBuffer(\n\t\t\t\tmemory_command.BankAddress(),\n\t\t\t\tmemory_command.Size(),\n\t\t\t)\n\t\t\tmemory_command.SetByteStream(byte_stream)\n\n\t\t\tthis.stat_factory.Increment(\"num_reads\", 1)\n\t\t\tthis.stat_factory.Increment(\"read_bytes\", memory_command.Size())\n\t\t} else if memory_operation == WRITE {\n\t\t\tthis.WriteToRowBuffer(memory_command.BankAddress(), memory_command.Size(), memory_command.ByteStream())\n\n\t\t\tthis.stat_factory.Increment(\"num_writes\", 1)\n\t\t\tthis.stat_factory.Increment(\"write_bytes\", memory_command.Size())\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *RowBuffer) ServicePrechargeQ() {\n\tif this.precharge_q.CanPop(1) && this.ready_q.CanPush(1) {\n\t\tmemory_command := this.precharge_q.Pop()\n\n\t\taddress := memory_command.BankAddress()\n\t\tif address%this.wordline_size != 0 {\n\t\t\terr := errors.New(\"address is not aligned with wordline size\")\n\t\t\tpanic(err)\n\t\t} else if address != *this.row_address {\n\t\t\terr := errors.New(\"address != row address\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.WriteToBank()\n\t\tthis.row_address = nil\n\t\tthis.ready_q.Push(memory_command)\n\n\t\tthis.stat_factory.Increment(\"num_precharges\", 1)\n\t}\n}\n\nfunc (this *RowBuffer) ReadFromBank() *encoding.ByteStream {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\treturn this.array.Read(*this.row_address)\n}\n\nfunc (this *RowBuffer) ReadFromRowBuffer(address int64, size int64) *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tbyte_stream.Append(this.row_buffer.Get(index))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *RowBuffer) WriteToBank() {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t}\n\n\tthis.array.Write(*this.row_address, this.row_buffer)\n}\n\nfunc (this *RowBuffer) WriteToRowBuffer(\n\taddress int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(address) + int(i)\n\n\t\tthis.row_buffer.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *RowBuffer) Index(address int64) int {\n\tif this.row_address == nil {\n\t\terr := errors.New(\"row address is not set\")\n\t\tpanic(err)\n\t} else if address < *this.row_address {\n\t\terr := errors.New(\"address < row address\")\n\t\tpanic(err)\n\t} else if address >= *this.row_address+this.wordline_size {\n\t\terr := errors.New(\"address >= row address + wordline size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(address - *this.row_address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/segment.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n)\n\ntype Segment struct {\n\tvm_address int64\n\n\tchannel_id   int\n\trank_id      int\n\tbank_id      int\n\tbank_address int64\n\n\tsize int64\n}\n\nfunc (this *Segment) Init(\n\tvm_address int64,\n\tchannel_id int,\n\trank_id int,\n\tbank_id int,\n\tbank_address int64,\n\tsize int64,\n) {\n\tif vm_address < 0 {\n\t\terr := errors.New(\"VM segment < 0\")\n\t\tpanic(err)\n\t} else if channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if bank_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t} else if bank_address < 0 {\n\t\terr := errors.New(\"bank segment < 0\")\n\t\tpanic(err)\n\t} else if size < 0 {\n\t\terr := errors.New(\"size < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.vm_address = vm_address\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.bank_id = bank_id\n\tthis.bank_address = bank_address\n\tthis.size = size\n}\n\nfunc (this *Segment) VmAddress() int64 {\n\treturn this.vm_address\n}\n\nfunc (this *Segment) ChannelID() int {\n\treturn this.channel_id\n}\n\nfunc (this *Segment) RankID() int {\n\treturn this.rank_id\n}\n\nfunc (this *Segment) BankID() int {\n\treturn this.bank_id\n}\n\nfunc (this *Segment) BankAddress() int64 {\n\treturn this.bank_address\n}\n\nfunc (this *Segment) Size() int64 {\n\treturn this.size\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/transfer_command.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/encoding\"\n)\n\ntype TransferCommandType int\n\nconst (\n\tHOST_TO_DEVICE TransferCommandType = iota\n\tDEVICE_TO_HOST\n)\n\ntype TransferCommandState int\n\nconst (\n\tBEGIN TransferCommandState = iota\n\tMIDDLE\n\tEND\n)\n\ntype TransferCommand struct {\n\ttransfer_command_type  TransferCommandType\n\ttransfer_command_state TransferCommandState\n\n\tvm_address int64\n\n\tchannel_id int\n\trank_id    int\n\tdpu_id     int\n\n\tmram_address int64\n\n\tsize int64\n\n\tbyte_stream     *encoding.ByteStream\n\tvm_dma_commands map[*DmaCommand]bool\n\tdma_commands    map[*dram.DmaCommand]bool\n}\n\nfunc (this *TransferCommand) Init(\n\ttransfer_command_type TransferCommandType,\n\tvm_address int64,\n\tchannel_id int,\n\trank_id int,\n\tdpu_id int,\n\tmram_address int64,\n\tsize int64,\n) {\n\tthis.transfer_command_type = transfer_command_type\n\tthis.transfer_command_state = BEGIN\n\n\tthis.vm_address = vm_address\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.dpu_id = dpu_id\n\tthis.mram_address = mram_address\n\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n\n\tthis.vm_dma_commands = make(map[*DmaCommand]bool)\n\tthis.dma_commands = make(map[*dram.DmaCommand]bool)\n}\n\nfunc (this *TransferCommand) InitFast(vm_address int64, size int64) {\n\tthis.vm_address = vm_address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *TransferCommand) TransferCommandType() TransferCommandType {\n\treturn this.transfer_command_type\n}\n\nfunc (this *TransferCommand) VmAddress() int64 {\n\treturn this.vm_address\n}\n\nfunc (this *TransferCommand) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *TransferCommand) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *TransferCommand) DpuId() int {\n\treturn this.dpu_id\n}\n\nfunc (this *TransferCommand) MramAddress() int64 {\n\treturn this.mram_address\n}\n\nfunc (this *TransferCommand) Size() int64 {\n\treturn this.size\n}\n\nfunc (this *TransferCommand) ByteStream() *encoding.ByteStream {\n\treturn this.byte_stream\n}\n\nfunc (this *TransferCommand) SetByteStream(\n\tvm_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tif size != byte_stream.Size() {\n\t\terr := errors.New(\"size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tindex := this.Index(vm_address) + int(i)\n\n\t\tthis.byte_stream.Set(index, byte_stream.Get(int(i)))\n\t}\n}\n\nfunc (this *TransferCommand) AppendVmDmaCommand(vm_dma_command *DmaCommand) {\n\tthis.vm_dma_commands[vm_dma_command] = true\n}\n\nfunc (this *TransferCommand) AppendDmaCommand(dma_command *dram.DmaCommand) {\n\tthis.dma_commands[dma_command] = true\n}\n\nfunc (this *TransferCommand) AckVmDmaCommand(vm_dma_command *DmaCommand) {\n\tif !vm_dma_command.IsReady() {\n\t\terr := errors.New(\"VM DMA command is not ready\")\n\t\tpanic(err)\n\t}\n\n\tif _, found := this.vm_dma_commands[vm_dma_command]; found {\n\t\tdelete(this.vm_dma_commands, vm_dma_command)\n\t} else {\n\t\terr := errors.New(\"VM DMA command is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *TransferCommand) AckDmaCommand(dma_command *dram.DmaCommand) {\n\tif !dma_command.IsReady() {\n\t\terr := errors.New(\"DMA command is not ready\")\n\t\tpanic(err)\n\t}\n\n\tif _, found := this.dma_commands[dma_command]; found {\n\t\tdelete(this.dma_commands, dma_command)\n\t} else {\n\t\terr := errors.New(\"DMA command is not found\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *TransferCommand) IsVmReady() bool {\n\treturn len(this.vm_dma_commands) == 0\n}\n\nfunc (this *TransferCommand) IsReady() bool {\n\treturn len(this.dma_commands) == 0\n}\n\nfunc (this *TransferCommand) TransferCommandState() TransferCommandState {\n\treturn this.transfer_command_state\n}\n\nfunc (this *TransferCommand) SetTransferCommandState(transfer_command_state TransferCommandState) {\n\tif transfer_command_state == BEGIN {\n\t\terr := errors.New(\"transfer command state is begin\")\n\t\tpanic(err)\n\t} else if transfer_command_state == MIDDLE {\n\t\tif this.transfer_command_state != BEGIN {\n\t\t\terr := errors.New(\"transfer command state is middle, but current transfer command state is not begin\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.transfer_command_state = transfer_command_state\n\t} else if transfer_command_state == END {\n\t\tif this.transfer_command_state != MIDDLE {\n\t\t\terr := errors.New(\"transfer command state is end, but current transfer command state is not middle\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.transfer_command_state = transfer_command_state\n\t} else {\n\t\terr := errors.New(\"transfer command state is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *TransferCommand) Index(vm_address int64) int {\n\tif vm_address < this.vm_address {\n\t\terr := errors.New(\"VM address < transfer command's VM address\")\n\t\tpanic(err)\n\t} else if vm_address >= this.vm_address+this.size {\n\t\terr := errors.New(\"VM address >= transfer command's VM address + transfer command's size\")\n\t\tpanic(err)\n\t}\n\n\treturn int(vm_address - this.vm_address)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/transfer_command_q.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n)\n\ntype TransferCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\ttransfer_commands []*TransferCommand\n\tcycles            []int64\n}\n\nfunc (this *TransferCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.transfer_commands = make([]*TransferCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *TransferCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"transfer command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *TransferCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *TransferCommandQ) Length() int {\n\treturn len(this.transfer_commands)\n}\n\nfunc (this *TransferCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *TransferCommandQ) IsEmpty() bool {\n\treturn len(this.transfer_commands) == 0\n}\n\nfunc (this *TransferCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.transfer_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *TransferCommandQ) Push(transfer_command *TransferCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"transfer command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.transfer_commands = append(this.transfer_commands, transfer_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *TransferCommandQ) PushWithTimer(transfer_command *TransferCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"transfer command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.transfer_commands = append(this.transfer_commands, transfer_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *TransferCommandQ) CanPop(num_items int) bool {\n\tif len(this.transfer_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *TransferCommandQ) Pop() *TransferCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"transfer command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\ttransfer_command := this.transfer_commands[0]\n\n\tthis.transfer_commands = this.transfer_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn transfer_command\n}\n\nfunc (this *TransferCommandQ) Front(pos int) (*TransferCommand, int64) {\n\treturn this.transfer_commands[pos], this.cycles[pos]\n}\n\nfunc (this *TransferCommandQ) Remove(pos int) {\n\tthis.transfer_commands = append(this.transfer_commands[:pos], this.transfer_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *TransferCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/bank/wordline.go",
    "content": "package bank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Wordline struct {\n\taddress int64\n\tsize    int64\n\n\tbyte_stream *encoding.ByteStream\n}\n\nfunc (this *Wordline) Init(address int64, size int64) {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tmram_data_size := int64(config_loader.MramDataWidth() / 8)\n\n\tif address < 0 {\n\t\terr := errors.New(\"address < 0\")\n\t\tpanic(err)\n\t} else if size <= 0 {\n\t\terr := errors.New(\"size <= 0\")\n\t\tpanic(err)\n\t} else if size%mram_data_size != 0 {\n\t\terr := errors.New(\"size is not aligned with MRAM data size\")\n\t\tpanic(err)\n\t}\n\n\tthis.address = address\n\tthis.size = size\n\n\tthis.byte_stream = new(encoding.ByteStream)\n\tthis.byte_stream.Init()\n\tfor i := int64(0); i < size; i++ {\n\t\tthis.byte_stream.Append(0)\n\t}\n}\n\nfunc (this *Wordline) Fini() {\n}\n\nfunc (this *Wordline) Read() *encoding.ByteStream {\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < this.byte_stream.Size(); i++ {\n\t\tbyte_stream.Append(this.byte_stream.Get(int(i)))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Wordline) Write(byte_stream *encoding.ByteStream) {\n\tif this.size != byte_stream.Size() {\n\t\terr := errors.New(\"wordline's size != byte stream's size\")\n\t\tpanic(err)\n\t}\n\n\tfor i := int64(0); i < byte_stream.Size(); i++ {\n\t\tthis.byte_stream.Set(int(i), byte_stream.Get(int(i)))\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/channel/channel.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/host/vm/dram/rank\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Channel struct {\n\tchannel_id int\n\tranks      []*rank.Rank\n\n\tinput_q    *ChannelCommandQ\n\tready_q    *ChannelCommandQ\n\tscoreboard map[*rank.RankCommand]*ChannelCommand\n}\n\nfunc (this *Channel) Init(channel_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\n\tthis.ranks = make([]*rank.Rank, 0)\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tfor i := 0; i < num_ranks_per_channel; i++ {\n\t\trank_ := new(rank.Rank)\n\t\trank_.Init(channel_id, i, command_line_parser)\n\t\tthis.ranks = append(this.ranks, rank_)\n\t}\n\n\tthis.input_q = new(ChannelCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.ready_q = new(ChannelCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.scoreboard = make(map[*rank.RankCommand]*ChannelCommand)\n}\n\nfunc (this *Channel) Fini() {\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Fini()\n\t}\n\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Channel) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *Channel) NumRanks() int {\n\treturn len(this.ranks)\n}\n\nfunc (this *Channel) Ranks() []*rank.Rank {\n\treturn this.ranks\n}\n\nfunc (this *Channel) Banks() []*bank.Bank {\n\tbanks := make([]*bank.Bank, 0)\n\n\tfor _, rank_ := range this.ranks {\n\t\tbanks = append(banks, rank_.Banks()...)\n\t}\n\n\treturn banks\n}\n\nfunc (this *Channel) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Channel) Push(channel_command *ChannelCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"channel cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(channel_command)\n}\n\nfunc (this *Channel) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Channel) Pop() *ChannelCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"channel cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Channel) Read(channel_command *ChannelCommand) {\n\trank_id := channel_command.RankId()\n\n\trank_command := channel_command.RankCommand()\n\n\tthis.ranks[rank_id].Read(rank_command)\n}\n\nfunc (this *Channel) Write(channel_command *ChannelCommand) {\n\trank_id := channel_command.RankId()\n\n\trank_command := channel_command.RankCommand()\n\n\tthis.ranks[rank_id].Write(rank_command)\n}\n\nfunc (this *Channel) Flush() {\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Flush()\n\t}\n}\n\nfunc (this *Channel) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n\n\tfor _, rank_ := range this.ranks {\n\t\trank_.Cycle()\n\t}\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Channel) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tchannel_command, _ := this.input_q.Front(0)\n\n\t\trank_id := channel_command.RankId()\n\t\tif this.ranks[rank_id].CanPush() {\n\t\t\tthis.input_q.Pop()\n\n\t\t\trank_command := channel_command.RankCommand()\n\n\t\t\tthis.ranks[rank_id].Push(rank_command)\n\t\t\tthis.scoreboard[rank_command] = channel_command\n\t\t}\n\t}\n}\n\nfunc (this *Channel) ServiceReadyQ() {\n\tfor _, rank_ := range this.ranks {\n\t\tif rank_.CanPop() && this.ready_q.CanPush(1) {\n\t\t\trank_command := rank_.Pop()\n\t\t\tchannel_command := this.scoreboard[rank_command]\n\n\t\t\tthis.ready_q.Push(channel_command)\n\t\t\tdelete(this.scoreboard, rank_command)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/channel/channel_command.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/host/vm/dram/rank\"\n)\n\ntype ChannelCommand struct {\n\tchannel_id int\n\trank_id    int\n\tbank_id    int\n\n\trank_command   *rank.RankCommand\n\tmemory_command *bank.MemoryCommand\n}\n\nfunc (this *ChannelCommand) Init(\n\tchannel_id int,\n\trank_id int,\n\tbank_id int,\n\tmemory_command *bank.MemoryCommand,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if bank_id < 0 {\n\t\terr := errors.New(\"DPU ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.bank_id = bank_id\n\n\tthis.rank_command = new(rank.RankCommand)\n\tthis.rank_command.Init(channel_id, rank_id, bank_id, memory_command)\n\n\tthis.memory_command = memory_command\n}\n\nfunc (this *ChannelCommand) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *ChannelCommand) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *ChannelCommand) BankId() int {\n\treturn this.bank_id\n}\n\nfunc (this *ChannelCommand) RankCommand() *rank.RankCommand {\n\treturn this.rank_command\n}\n\nfunc (this *ChannelCommand) MemoryCommand() *bank.MemoryCommand {\n\treturn this.memory_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/channel/channel_command_q.go",
    "content": "package channel\n\nimport (\n\t\"errors\"\n)\n\ntype ChannelCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\tchannel_commands []*ChannelCommand\n\tcycles           []int64\n}\n\nfunc (this *ChannelCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.channel_commands = make([]*ChannelCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *ChannelCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"channel command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ChannelCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *ChannelCommandQ) Length() int {\n\treturn len(this.channel_commands)\n}\n\nfunc (this *ChannelCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *ChannelCommandQ) IsEmpty() bool {\n\treturn len(this.channel_commands) == 0\n}\n\nfunc (this *ChannelCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.channel_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelCommandQ) Push(channel_command *ChannelCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_commands = append(this.channel_commands, channel_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *ChannelCommandQ) PushWithTimer(channel_command *ChannelCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"channel command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_commands = append(this.channel_commands, channel_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *ChannelCommandQ) CanPop(num_items int) bool {\n\tif len(this.channel_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *ChannelCommandQ) Pop() *ChannelCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"channel command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\tchannel_command := this.channel_commands[0]\n\n\tthis.channel_commands = this.channel_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn channel_command\n}\n\nfunc (this *ChannelCommandQ) Front(pos int) (*ChannelCommand, int64) {\n\treturn this.channel_commands[pos], this.cycles[pos]\n}\n\nfunc (this *ChannelCommandQ) Remove(pos int) {\n\tthis.channel_commands = append(this.channel_commands[:pos], this.channel_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *ChannelCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/memory_controller.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/device/simulator/channel\"\n\t\"uPIMulator/src/device/simulator/dpu/dram\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\tvm_channel \"uPIMulator/src/host/vm/dram/channel\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryController struct {\n\tvm_channels []*vm_channel.Channel\n\tchannels    []*channel.Channel\n\n\tmemory_scheduler *MemoryScheduler\n\tmemory_mapping   *MemoryMapping\n\n\tinput_q *bank.TransferCommandQ\n\n\tvm_dma_command_q     *bank.DmaCommandQ\n\tvm_channel_command_q *vm_channel.ChannelCommandQ\n\n\tchannel_command_q *channel.ChannelCommandQ\n\n\tvm_wait_q *bank.TransferCommandQ\n\n\tscoreboard map[*dram.DmaCommand]*bank.TransferCommand\n\twait_q     *bank.TransferCommandQ\n\n\tready_q *bank.TransferCommandQ\n}\n\nfunc (this *MemoryController) Init(command_line_parser *misc.CommandLineParser) {\n\tnum_vm_channels := int(command_line_parser.IntParameter(\"num_vm_channels\"))\n\n\tthis.vm_channels = make([]*vm_channel.Channel, 0)\n\tfor i := 0; i < num_vm_channels; i++ {\n\t\tvm_channel_ := new(vm_channel.Channel)\n\t\tvm_channel_.Init(i, command_line_parser)\n\n\t\tthis.vm_channels = append(this.vm_channels, vm_channel_)\n\t}\n\n\tthis.memory_scheduler = new(MemoryScheduler)\n\tthis.memory_scheduler.Init(command_line_parser)\n\n\tthis.memory_mapping = new(MemoryMapping)\n\tthis.memory_mapping.Init(command_line_parser)\n\n\tthis.input_q = new(bank.TransferCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.vm_dma_command_q = new(bank.DmaCommandQ)\n\tthis.vm_dma_command_q.Init(-1, 0)\n\n\tthis.vm_channel_command_q = new(vm_channel.ChannelCommandQ)\n\tthis.vm_channel_command_q.Init(-1, 0)\n\n\tthis.channel_command_q = new(channel.ChannelCommandQ)\n\tthis.channel_command_q.Init(-1, 0)\n\n\tthis.vm_wait_q = new(bank.TransferCommandQ)\n\tthis.vm_wait_q.Init(-1, 0)\n\n\tthis.scoreboard = make(map[*dram.DmaCommand]*bank.TransferCommand)\n\n\tthis.wait_q = new(bank.TransferCommandQ)\n\tthis.wait_q.Init(-1, 0)\n\n\tthis.ready_q = new(bank.TransferCommandQ)\n\tthis.ready_q.Init(-1, 0)\n}\n\nfunc (this *MemoryController) Fini() {\n\tfor _, vm_channel_ := range this.vm_channels {\n\t\tvm_channel_.Fini()\n\t}\n\n\tthis.memory_scheduler.Fini()\n\tthis.memory_mapping.Fini()\n\n\tthis.input_q.Fini()\n\tthis.vm_dma_command_q.Fini()\n\tthis.vm_channel_command_q.Fini()\n\tthis.channel_command_q.Fini()\n\tthis.vm_wait_q.Fini()\n\n\tif len(this.scoreboard) != 0 {\n\t\terr := errors.New(\"scoreboard is not empty\")\n\t\tpanic(err)\n\t}\n\n\tthis.wait_q.Fini()\n\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryController) ConnectChannels(channels []*channel.Channel) {\n\tthis.channels = channels\n}\n\nfunc (this *MemoryController) VmChannels() []*vm_channel.Channel {\n\treturn this.vm_channels\n}\n\nfunc (this *MemoryController) MemoryScheduler() *MemoryScheduler {\n\treturn this.memory_scheduler\n}\n\nfunc (this *MemoryController) Banks() []*bank.Bank {\n\tbanks := make([]*bank.Bank, 0)\n\tfor _, vm_channel_ := range this.vm_channels {\n\t\tbanks = append(banks, vm_channel_.Banks()...)\n\t}\n\treturn banks\n}\n\nfunc (this *MemoryController) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryController) Push(transfer_command *bank.TransferCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory controller cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(transfer_command)\n}\n\nfunc (this *MemoryController) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryController) Pop() *bank.TransferCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory controller cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryController) VmRead(vm_address int64, size int64) *encoding.ByteStream {\n\tsegments := this.memory_mapping.Map(vm_address, size)\n\n\ttransfer_command := new(bank.TransferCommand)\n\ttransfer_command.InitFast(vm_address, size)\n\n\tfor _, segment := range segments {\n\t\tdma_command := new(bank.DmaCommand)\n\t\tdma_command.InitRead(segment, transfer_command)\n\n\t\tchannel_commands := this.memory_scheduler.Generate(dma_command)\n\n\t\tfor _, channel_command := range channel_commands {\n\t\t\tchannel_id := channel_command.ChannelId()\n\n\t\t\tthis.vm_channels[channel_id].Read(channel_command)\n\t\t}\n\n\t\tbyte_stream := dma_command.ByteStream(segment.BankAddress(), segment.Size())\n\n\t\ttransfer_command.SetByteStream(\n\t\t\tdma_command.Segment().VmAddress(),\n\t\t\tdma_command.Segment().Size(),\n\t\t\tbyte_stream,\n\t\t)\n\t}\n\n\treturn transfer_command.ByteStream()\n}\n\nfunc (this *MemoryController) VmWrite(\n\tvm_address int64,\n\tsize int64,\n\tbyte_stream *encoding.ByteStream,\n) {\n\tsegments := this.memory_mapping.Map(vm_address, size)\n\n\ttransfer_command := new(bank.TransferCommand)\n\ttransfer_command.InitFast(vm_address, size)\n\ttransfer_command.SetByteStream(vm_address, size, byte_stream)\n\n\tfor _, segment := range segments {\n\t\tdma_command := new(bank.DmaCommand)\n\t\tdma_command.InitWrite(segment, transfer_command)\n\n\t\tdma_command_byte_stream := new(encoding.ByteStream)\n\t\tdma_command_byte_stream.Init()\n\t\tfor i := int64(0); i < dma_command.Segment().Size(); i++ {\n\t\t\tbyte_ := transfer_command.ByteStream().Get(int(segment.VmAddress() + i - vm_address))\n\t\t\tdma_command_byte_stream.Append(byte_)\n\t\t}\n\n\t\tdma_command.SetByteStream(segment.BankAddress(), segment.Size(), dma_command_byte_stream)\n\n\t\tchannel_commands := this.memory_scheduler.Generate(dma_command)\n\n\t\tfor _, channel_command := range channel_commands {\n\t\t\tchannel_id := channel_command.ChannelId()\n\n\t\t\tthis.vm_channels[channel_id].Write(channel_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) Flush() {\n\tthis.memory_scheduler.Flush()\n\tfor _, vm_channel_ := range this.vm_channels {\n\t\tvm_channel_.Flush()\n\t}\n}\n\nfunc (this *MemoryController) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceVmDmaCommandQ()\n\tthis.ServiceMemoryScheduler()\n\tthis.ServiceVmChannelCommandQ()\n\tthis.ServiceVmChannels()\n\tthis.ServiceChannelCommandQ()\n\tthis.ServiceChannels()\n\tthis.ServiceVmWaitQ()\n\tthis.ServiceWaitQ()\n\n\tthis.memory_scheduler.Cycle()\n\n\tthis.input_q.Cycle()\n\tthis.vm_dma_command_q.Cycle()\n\tthis.vm_channel_command_q.Cycle()\n\tthis.channel_command_q.Cycle()\n\tthis.vm_wait_q.Cycle()\n\tthis.wait_q.Cycle()\n\tthis.ready_q.Cycle()\n\n\tfor _, channel_ := range this.channels {\n\t\tchannel_.Cycle()\n\t}\n}\n\nfunc (this *MemoryController) ServiceInputQ() {\n\t// TODO(bongjoon.hyun@gmail.com): need to check if VM DMA queue or channel command queue can be pushed\n\tif this.input_q.CanPop(1) {\n\t\ttransfer_command := this.input_q.Pop()\n\n\t\tif transfer_command.TransferCommandType() == bank.HOST_TO_DEVICE {\n\t\t\tthis.vm_wait_q.Push(transfer_command)\n\n\t\t\tsegments := this.memory_mapping.Map(\n\t\t\t\ttransfer_command.VmAddress(),\n\t\t\t\ttransfer_command.Size(),\n\t\t\t)\n\n\t\t\tfor _, segment := range segments {\n\t\t\t\tdma_command := new(bank.DmaCommand)\n\t\t\t\tdma_command.InitRead(segment, transfer_command)\n\n\t\t\t\ttransfer_command.AppendVmDmaCommand(dma_command)\n\n\t\t\t\tthis.vm_dma_command_q.Push(dma_command)\n\t\t\t}\n\t\t} else if transfer_command.TransferCommandType() == bank.DEVICE_TO_HOST {\n\t\t\tthis.wait_q.Push(transfer_command)\n\n\t\t\tchannel_id := transfer_command.ChannelId()\n\t\t\trank_id := transfer_command.RankId()\n\t\t\tdpu_id := transfer_command.DpuId()\n\t\t\tmram_address := transfer_command.MramAddress()\n\t\t\tsize := transfer_command.Size()\n\n\t\t\tdma_command := new(dram.DmaCommand)\n\t\t\tdma_command.InitReadFromMram(mram_address, size)\n\n\t\t\tthis.scoreboard[dma_command] = transfer_command\n\n\t\t\tchannel_command := new(channel.ChannelCommand)\n\t\t\tchannel_command.Init(channel_id, rank_id, dpu_id, dma_command)\n\n\t\t\ttransfer_command.AppendDmaCommand(dma_command)\n\n\t\t\tthis.channel_command_q.Push(channel_command)\n\t\t} else {\n\t\t\terr := errors.New(\"transfer command type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceVmDmaCommandQ() {\n\tif this.vm_dma_command_q.CanPop(1) && this.memory_scheduler.CanPush() {\n\t\tdma_command := this.vm_dma_command_q.Pop()\n\n\t\tthis.memory_scheduler.Push(dma_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceMemoryScheduler() {\n\tif this.memory_scheduler.CanPop() && this.vm_channel_command_q.CanPush(1) {\n\t\tvm_channel_command := this.memory_scheduler.Pop()\n\n\t\tthis.vm_channel_command_q.Push(vm_channel_command)\n\t}\n}\n\nfunc (this *MemoryController) ServiceVmChannelCommandQ() {\n\tif this.vm_channel_command_q.CanPop(1) {\n\t\tvm_channel_command, _ := this.vm_channel_command_q.Front(0)\n\n\t\tchannel_id := vm_channel_command.ChannelId()\n\n\t\tif this.vm_channels[channel_id].CanPush() {\n\t\t\tthis.vm_channel_command_q.Pop()\n\n\t\t\tthis.vm_channels[channel_id].Push(vm_channel_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceVmChannels() {\n\tfor _, vm_channel_ := range this.vm_channels {\n\t\tif vm_channel_.CanPop() {\n\t\t\tvm_channel_command := vm_channel_.Pop()\n\n\t\t\tdma_command := vm_channel_command.MemoryCommand().DmaCommand()\n\t\t\ttransfer_command := dma_command.TransferCommand()\n\n\t\t\tif transfer_command.TransferCommandType() == bank.HOST_TO_DEVICE {\n\t\t\t\tsegment := dma_command.Segment()\n\t\t\t\tvm_address := segment.VmAddress()\n\t\t\t\tsize := segment.Size()\n\t\t\t\tbyte_stream := dma_command.ByteStream(segment.BankAddress(), segment.Size())\n\n\t\t\t\ttransfer_command.SetByteStream(vm_address, size, byte_stream)\n\n\t\t\t\tif dma_command.IsReady() {\n\t\t\t\t\ttransfer_command.AckVmDmaCommand(dma_command)\n\t\t\t\t}\n\t\t\t} else if transfer_command.TransferCommandType() == bank.DEVICE_TO_HOST {\n\t\t\t\tif dma_command.IsReady() {\n\t\t\t\t\ttransfer_command.AckVmDmaCommand(dma_command)\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\terr := errors.New(\"transfer command type is not valid\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceChannelCommandQ() {\n\tif this.channel_command_q.CanPop(1) {\n\t\tchannel_command, _ := this.channel_command_q.Front(0)\n\n\t\tchannel_id := channel_command.ChannelId()\n\n\t\tif this.channels[channel_id].CanPush() {\n\t\t\tthis.channel_command_q.Pop()\n\n\t\t\tthis.channels[channel_id].Push(channel_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceChannels() {\n\tfor _, channel_ := range this.channels {\n\t\tif channel_.CanPop() {\n\t\t\tchannel_command := channel_.Pop()\n\n\t\t\tdma_command := channel_command.DmaCommand()\n\n\t\t\ttransfer_command := this.scoreboard[dma_command]\n\t\t\tdelete(this.scoreboard, dma_command)\n\n\t\t\tif transfer_command.TransferCommandType() == bank.HOST_TO_DEVICE {\n\t\t\t\tif dma_command.IsReady() {\n\t\t\t\t\ttransfer_command.AckDmaCommand(dma_command)\n\t\t\t\t}\n\t\t\t} else if transfer_command.TransferCommandType() == bank.DEVICE_TO_HOST {\n\t\t\t\tvm_address := transfer_command.VmAddress()\n\t\t\t\tsize := transfer_command.Size()\n\t\t\t\tbyte_stream := dma_command.ByteStream(dma_command.MramAddress(), dma_command.Size())\n\n\t\t\t\ttransfer_command.SetByteStream(vm_address, size, byte_stream)\n\n\t\t\t\tif dma_command.IsReady() {\n\t\t\t\t\ttransfer_command.AckDmaCommand(dma_command)\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\terr := errors.New(\"transfer command type is not valid\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceVmWaitQ() {\n\tfor i := 0; i < this.vm_wait_q.Length(); i++ {\n\t\ttransfer_command, _ := this.vm_wait_q.Front(i)\n\n\t\tif transfer_command.IsVmReady() && transfer_command.IsReady() &&\n\t\t\ttransfer_command.TransferCommandState() == bank.MIDDLE &&\n\t\t\tthis.ready_q.CanPush(1) {\n\t\t\tthis.vm_wait_q.Remove(i)\n\n\t\t\ttransfer_command.SetTransferCommandState(bank.END)\n\n\t\t\tthis.ready_q.Push(transfer_command)\n\t\t} else if transfer_command.IsVmReady() {\n\t\t\tthis.vm_wait_q.Remove(i)\n\n\t\t\ttransfer_command.SetTransferCommandState(bank.MIDDLE)\n\n\t\t\tthis.wait_q.Push(transfer_command)\n\n\t\t\tchannel_id := transfer_command.ChannelId()\n\t\t\trank_id := transfer_command.RankId()\n\t\t\tdpu_id := transfer_command.DpuId()\n\t\t\tmram_address := transfer_command.MramAddress()\n\t\t\tsize := transfer_command.Size()\n\t\t\tbyte_stream := transfer_command.ByteStream()\n\n\t\t\tdma_command := new(dram.DmaCommand)\n\t\t\tdma_command.InitWriteToMram(mram_address, size, byte_stream)\n\n\t\t\tthis.scoreboard[dma_command] = transfer_command\n\n\t\t\tchannel_command := new(channel.ChannelCommand)\n\t\t\tchannel_command.Init(channel_id, rank_id, dpu_id, dma_command)\n\n\t\t\ttransfer_command.AppendDmaCommand(dma_command)\n\n\t\t\tthis.channel_command_q.Push(channel_command)\n\t\t}\n\t}\n}\n\nfunc (this *MemoryController) ServiceWaitQ() {\n\tfor i := 0; i < this.wait_q.Length(); i++ {\n\t\ttransfer_command, _ := this.wait_q.Front(i)\n\n\t\tif transfer_command.IsReady() && transfer_command.IsVmReady() &&\n\t\t\ttransfer_command.TransferCommandState() == bank.MIDDLE &&\n\t\t\tthis.ready_q.CanPush(1) {\n\t\t\tthis.wait_q.Remove(i)\n\n\t\t\ttransfer_command.SetTransferCommandState(bank.END)\n\n\t\t\tthis.ready_q.Push(transfer_command)\n\t\t} else if transfer_command.IsReady() {\n\t\t\tthis.wait_q.Remove(i)\n\n\t\t\ttransfer_command.SetTransferCommandState(bank.MIDDLE)\n\n\t\t\tthis.vm_wait_q.Push(transfer_command)\n\n\t\t\tsegments := this.memory_mapping.Map(transfer_command.VmAddress(), transfer_command.Size())\n\n\t\t\tfor _, segment := range segments {\n\t\t\t\tdma_command := new(bank.DmaCommand)\n\t\t\t\tdma_command.InitWrite(segment, transfer_command)\n\n\t\t\t\ttransfer_command.AppendVmDmaCommand(dma_command)\n\n\t\t\t\tthis.vm_dma_command_q.Push(dma_command)\n\t\t\t}\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/memory_mapping.go",
    "content": "package dram\n\nimport (\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryMapping struct {\n\tnum_vm_channels          int\n\tnum_vm_ranks_per_channel int\n\tnum_vm_banks_per_rank    int\n\n\tvm_bg0  int\n\tvm_bg1  int\n\tvm_bank int\n\n\tvm_bank_offset int64\n\tvm_bank_size   int64\n}\n\nfunc (this *MemoryMapping) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.num_vm_channels = int(command_line_parser.IntParameter(\"num_vm_channels\"))\n\tthis.num_vm_ranks_per_channel = int(\n\t\tcommand_line_parser.IntParameter(\"num_vm_ranks_per_channel\"),\n\t)\n\tthis.num_vm_banks_per_rank = int(command_line_parser.IntParameter(\"num_vm_banks_per_rank\"))\n\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tthis.vm_bg0 = config_loader.VmBg0()\n\tthis.vm_bg1 = config_loader.VmBg1()\n\tthis.vm_bank = config_loader.VmBank()\n\n\tthis.vm_bank_offset = config_loader.VmBankOffset()\n\tthis.vm_bank_size = config_loader.VmBankSize()\n}\n\nfunc (this *MemoryMapping) Fini() {\n}\n\nfunc (this *MemoryMapping) Map(vm_address int64, vm_size int64) []*bank.Segment {\n\tbegin_address := vm_address\n\tend_address := vm_address + vm_size\n\n\tsegments := make([]*bank.Segment, 0)\n\n\tfor address := begin_address; address < end_address; {\n\t\toffset_address := this.OffsetAddress(address)\n\n\t\tsize := this.Min(\n\t\t\tthis.Min(\n\t\t\t\taddress+this.Offset(),\n\t\t\t\toffset_address+this.Offset(),\n\t\t\t),\n\t\t\tend_address,\n\t\t) - address\n\n\t\tchannel_id := this.ChannelId(address)\n\t\trank_id := this.RankId(address)\n\t\tbank_id := this.BankId(address)\n\t\tbank_address := this.BankAddress(address)\n\n\t\tsegment := new(bank.Segment)\n\t\tsegment.Init(address, channel_id, rank_id, bank_id, bank_address, size)\n\n\t\tsegments = append(segments, segment)\n\n\t\taddress += size\n\t}\n\n\treturn segments\n}\n\nfunc (this *MemoryMapping) ChannelId(address int64) int {\n\treturn int(address / this.ChannelSize())\n}\n\nfunc (this *MemoryMapping) RankId(address int64) int {\n\treturn int((address % this.ChannelSize()) / this.RankSize())\n}\n\nfunc (this *MemoryMapping) BankId(address int64) int {\n\treturn this.Bank(address)*4 + this.Bg1(address)*2 + this.Bg0(address)\n}\n\nfunc (this *MemoryMapping) BankAddress(address int64) int64 {\n\treturn address % this.vm_bank_size\n}\n\nfunc (this *MemoryMapping) ChannelSize() int64 {\n\treturn int64(this.num_vm_ranks_per_channel) * this.RankSize()\n}\n\nfunc (this *MemoryMapping) RankSize() int64 {\n\treturn int64(this.num_vm_banks_per_rank) * this.vm_bank_size\n}\n\nfunc (this *MemoryMapping) Bg0(address int64) int {\n\treturn int(address & (1 << this.vm_bg0) >> this.vm_bg0)\n}\n\nfunc (this *MemoryMapping) Bg1(address int64) int {\n\treturn int(address & (1 << this.vm_bg1) >> this.vm_bg1)\n}\n\nfunc (this *MemoryMapping) Bank(address int64) int {\n\treturn int(address & (3 << this.vm_bank) >> this.vm_bank)\n}\n\nfunc (this *MemoryMapping) Offset() int64 {\n\treturn this.Pow2(this.vm_bg0)\n}\n\nfunc (this *MemoryMapping) OffsetAddress(address int64) int64 {\n\treturn (address / this.Offset()) * this.Offset()\n}\n\nfunc (this *MemoryMapping) Pow2(exponent int) int64 {\n\tvalue := int64(1)\n\tfor i := 0; i < exponent; i++ {\n\t\tvalue *= 2\n\t}\n\treturn value\n}\n\nfunc (this *MemoryMapping) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/memory_scheduler.go",
    "content": "package dram\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/host/vm/dram/channel\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype MemoryScheduler struct {\n\tnum_vm_channels          int\n\tnum_vm_ranks_per_channel int\n\tnum_vm_banks_per_rank    int\n\n\tinput_q        *bank.DmaCommandQ\n\treorder_buffer *channel.ChannelCommandQ\n\tready_q        *channel.ChannelCommandQ\n\n\trow_addresses          map[int]int64\n\twordline_size          int64\n\tmin_access_granularity int64\n\treorder_window_size    int\n\n\tstat_factory *misc.StatFactory\n}\n\nfunc (this *MemoryScheduler) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.num_vm_channels = int(command_line_parser.IntParameter(\"num_vm_channels\"))\n\tthis.num_vm_ranks_per_channel = int(\n\t\tcommand_line_parser.IntParameter(\"num_vm_ranks_per_channel\"),\n\t)\n\tthis.num_vm_banks_per_rank = int(command_line_parser.IntParameter(\"num_vm_banks_per_rank\"))\n\n\tthis.input_q = new(bank.DmaCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.reorder_buffer = new(channel.ChannelCommandQ)\n\tthis.reorder_buffer.Init(-1, 0)\n\n\tthis.ready_q = new(channel.ChannelCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.row_addresses = make(map[int]int64)\n\tthis.wordline_size = command_line_parser.IntParameter(\"wordline_size\")\n\tthis.min_access_granularity = command_line_parser.IntParameter(\"min_access_granularity\")\n\tthis.reorder_window_size = int(command_line_parser.IntParameter(\"reorder_window_size\"))\n\n\tthis.stat_factory = new(misc.StatFactory)\n\tthis.stat_factory.Init(\"MemoryScheduler\")\n}\n\nfunc (this *MemoryScheduler) Fini() {\n\tthis.input_q.Fini()\n\tthis.reorder_buffer.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *MemoryScheduler) StatFactory() *misc.StatFactory {\n\treturn this.stat_factory\n}\n\nfunc (this *MemoryScheduler) IsEmpty() bool {\n\treturn this.input_q.IsEmpty() && this.reorder_buffer.IsEmpty() && this.ready_q.IsEmpty()\n}\n\nfunc (this *MemoryScheduler) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *MemoryScheduler) Push(dma_command *bank.DmaCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"memory scheduler cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(dma_command)\n}\n\nfunc (this *MemoryScheduler) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *MemoryScheduler) Pop() *channel.ChannelCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"memory scheduler cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *MemoryScheduler) Generate(dma_command *bank.DmaCommand) []*channel.ChannelCommand {\n\tbegin_address := dma_command.Segment().BankAddress()\n\tend_address := dma_command.Segment().BankAddress() + dma_command.Segment().Size()\n\n\tchannel_commands := make([]*channel.ChannelCommand, 0)\n\tfor address := begin_address; address < end_address; {\n\t\twordline_address := this.WordlineAddress(address)\n\n\t\tsize := this.Min(\n\t\t\tthis.Min(\n\t\t\t\taddress+this.min_access_granularity,\n\t\t\t\twordline_address+this.wordline_size,\n\t\t\t),\n\t\t\tend_address,\n\t\t) - address\n\n\t\tmemory_operation := dma_command.MemoryOperation()\n\t\tmemory_command := new(bank.MemoryCommand)\n\t\tif memory_operation == bank.READ {\n\t\t\tmemory_command.InitRead(bank.READ, address, size, dma_command)\n\t\t} else if memory_operation == bank.WRITE {\n\t\t\tbyte_stream := dma_command.ByteStream(address, size)\n\t\t\tmemory_command.InitWrite(bank.WRITE, address, size, byte_stream, dma_command)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tchannel_command := new(channel.ChannelCommand)\n\t\tchannel_command.Init(\n\t\t\tdma_command.Segment().ChannelID(),\n\t\t\tdma_command.Segment().RankID(),\n\t\t\tdma_command.Segment().BankID(),\n\t\t\tmemory_command,\n\t\t)\n\n\t\tchannel_commands = append(channel_commands, channel_command)\n\n\t\taddress += size\n\t}\n\treturn channel_commands\n}\n\nfunc (this *MemoryScheduler) Flush() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"memory scheduler cannot be flushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.row_addresses = make(map[int]int64)\n}\n\nfunc (this *MemoryScheduler) Cycle() {\n\tthis.ServiceInputQ()\n\n\tif !this.ReorderFr() {\n\t\tthis.ReorderFcFs()\n\t}\n\n\tthis.input_q.Cycle()\n\tthis.reorder_buffer.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *MemoryScheduler) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\tdma_command := this.input_q.Pop()\n\n\t\tthis.PopulateMemoryCommands(dma_command)\n\t}\n}\n\nfunc (this *MemoryScheduler) PopulateMemoryCommands(dma_command *bank.DmaCommand) {\n\tbegin_address := dma_command.Segment().BankAddress()\n\tend_address := dma_command.Segment().BankAddress() + dma_command.Segment().Size()\n\n\tfor address := begin_address; address < end_address; {\n\t\twordline_address := this.WordlineAddress(address)\n\n\t\tsize := this.Min(\n\t\t\tthis.Min(\n\t\t\t\taddress+this.min_access_granularity,\n\t\t\t\twordline_address+this.wordline_size,\n\t\t\t),\n\t\t\tend_address,\n\t\t) - address\n\n\t\tmemory_operation := dma_command.MemoryOperation()\n\t\tmemory_command := new(bank.MemoryCommand)\n\t\tif memory_operation == bank.READ {\n\t\t\tmemory_command.InitRead(bank.READ, address, size, dma_command)\n\t\t} else if memory_operation == bank.WRITE {\n\t\t\tbyte_stream := dma_command.ByteStream(address, size)\n\t\t\tmemory_command.InitWrite(bank.WRITE, address, size, byte_stream, dma_command)\n\t\t} else {\n\t\t\terr := errors.New(\"memory operation is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\n\t\tchannel_command := new(channel.ChannelCommand)\n\t\tchannel_command.Init(\n\t\t\tdma_command.Segment().ChannelID(),\n\t\t\tdma_command.Segment().RankID(),\n\t\t\tdma_command.Segment().BankID(),\n\t\t\tmemory_command,\n\t\t)\n\n\t\tthis.reorder_buffer.Push(channel_command)\n\n\t\taddress += size\n\t}\n}\n\nfunc (this *MemoryScheduler) ReorderFr() bool {\n\tif this.ready_q.CanPush(1) {\n\t\tfor i := 0; this.reorder_buffer.CanPop(i+1) && i < this.reorder_window_size; i++ {\n\t\t\tchannel_command, _ := this.reorder_buffer.Front(i)\n\t\t\tmemory_command := channel_command.MemoryCommand()\n\n\t\t\twordline_address := this.WordlineAddress(memory_command.BankAddress())\n\n\t\t\tif this.IsOpened(channel_command) &&\n\t\t\t\tthis.RowAddress(channel_command) == wordline_address {\n\t\t\t\tif i != 0 {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fr\", 1)\n\t\t\t\t} else {\n\t\t\t\t\tthis.stat_factory.Increment(\"num_fcfs\", 1)\n\t\t\t\t}\n\n\t\t\t\tthis.reorder_buffer.Remove(i)\n\t\t\t\tthis.ready_q.Push(channel_command)\n\n\t\t\t\treturn true\n\t\t\t}\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *MemoryScheduler) ReorderFcFs() bool {\n\tif this.reorder_buffer.CanPop(1) && this.ready_q.CanPush(3) {\n\t\tchannel_command, _ := this.reorder_buffer.Front(0)\n\n\t\tif this.IsOpened(channel_command) {\n\t\t\tthis.reorder_buffer.Remove(0)\n\n\t\t\tmemory_command := channel_command.MemoryCommand()\n\n\t\t\twordline_address := this.WordlineAddress(memory_command.BankAddress())\n\n\t\t\tprecharge := new(bank.MemoryCommand)\n\t\t\tprecharge.InitActivation(bank.PRECHARGE, this.RowAddress(channel_command))\n\n\t\t\tactivation := new(bank.MemoryCommand)\n\t\t\tactivation.InitActivation(bank.ACTIVATION, wordline_address)\n\n\t\t\tchannel_id := channel_command.ChannelId()\n\t\t\trank_id := channel_command.RankId()\n\t\t\tbank_id := channel_command.BankId()\n\n\t\t\tprecharge_channel_command := new(channel.ChannelCommand)\n\t\t\tprecharge_channel_command.Init(channel_id, rank_id, bank_id, precharge)\n\n\t\t\tactivation_channel_command := new(channel.ChannelCommand)\n\t\t\tactivation_channel_command.Init(channel_id, rank_id, bank_id, activation)\n\n\t\t\tthis.ready_q.Push(precharge_channel_command)\n\t\t\tthis.ready_q.Push(activation_channel_command)\n\t\t\tthis.ready_q.Push(channel_command)\n\n\t\t\tthis.row_addresses[this.UniqueBankId(channel_id, rank_id, bank_id)] = wordline_address\n\n\t\t\treturn true\n\t\t} else {\n\t\t\tthis.reorder_buffer.Remove(0)\n\n\t\t\tmemory_command := channel_command.MemoryCommand()\n\n\t\t\twordline_address := this.WordlineAddress(memory_command.BankAddress())\n\n\t\t\tactivation := new(bank.MemoryCommand)\n\t\t\tactivation.InitActivation(bank.ACTIVATION, wordline_address)\n\n\t\t\tchannel_id := channel_command.ChannelId()\n\t\t\trank_id := channel_command.RankId()\n\t\t\tbank_id := channel_command.BankId()\n\n\t\t\tactivation_channel_command := new(channel.ChannelCommand)\n\t\t\tactivation_channel_command.Init(channel_id, rank_id, bank_id, activation)\n\n\t\t\tthis.ready_q.Push(activation_channel_command)\n\t\t\tthis.ready_q.Push(channel_command)\n\n\t\t\tthis.row_addresses[this.UniqueBankId(channel_id, rank_id, bank_id)] = wordline_address\n\n\t\t\treturn true\n\t\t}\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *MemoryScheduler) IsOpened(channel_command *channel.ChannelCommand) bool {\n\tunique_bank_id := this.UniqueBankId(\n\t\tchannel_command.ChannelId(),\n\t\tchannel_command.RankId(),\n\t\tchannel_command.BankId(),\n\t)\n\n\tif _, found := this.row_addresses[unique_bank_id]; found {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *MemoryScheduler) RowAddress(channel_command *channel.ChannelCommand) int64 {\n\tunique_bank_id := this.UniqueBankId(\n\t\tchannel_command.ChannelId(),\n\t\tchannel_command.RankId(),\n\t\tchannel_command.BankId(),\n\t)\n\n\tif row_address, found := this.row_addresses[unique_bank_id]; found {\n\t\treturn row_address\n\t} else {\n\t\terr := errors.New(\"unique bank is not opened\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *MemoryScheduler) UniqueBankId(channel_id int, rank_id int, bank_id int) int {\n\treturn channel_id*this.num_vm_ranks_per_channel*this.num_vm_banks_per_rank + rank_id*this.num_vm_banks_per_rank + bank_id\n}\n\nfunc (this *MemoryScheduler) WordlineAddress(address int64) int64 {\n\treturn address / this.wordline_size * this.wordline_size\n}\n\nfunc (this *MemoryScheduler) Min(x int64, y int64) int64 {\n\tif x <= y {\n\t\treturn x\n\t} else {\n\t\treturn y\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/rank/rank.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Rank struct {\n\tchannel_id int\n\trank_id    int\n\n\tbanks []*bank.Bank\n\n\tinput_q    *RankCommandQ\n\tready_q    *RankCommandQ\n\tscoreboard map[*bank.MemoryCommand]*RankCommand\n}\n\nfunc (this *Rank) Init(channel_id int, rank_id int, command_line_parser *misc.CommandLineParser) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\n\tthis.banks = make([]*bank.Bank, 0)\n\tnum_vm_banks_per_rank := int(command_line_parser.IntParameter(\"num_vm_banks_per_rank\"))\n\tfor i := 0; i < num_vm_banks_per_rank; i++ {\n\t\tbank_ := new(bank.Bank)\n\t\tbank_.Init(channel_id, rank_id, i, command_line_parser)\n\n\t\tthis.banks = append(this.banks, bank_)\n\t}\n\n\tthis.input_q = new(RankCommandQ)\n\tthis.input_q.Init(-1, 0)\n\n\tthis.ready_q = new(RankCommandQ)\n\tthis.ready_q.Init(-1, 0)\n\n\tthis.scoreboard = make(map[*bank.MemoryCommand]*RankCommand)\n}\n\nfunc (this *Rank) Fini() {\n\tfor _, bank_ := range this.banks {\n\t\tbank_.Fini()\n\t}\n\n\tthis.input_q.Fini()\n\tthis.ready_q.Fini()\n}\n\nfunc (this *Rank) ChannelID() int {\n\treturn this.channel_id\n}\n\nfunc (this *Rank) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *Rank) NumBanks() int {\n\treturn len(this.banks)\n}\n\nfunc (this *Rank) Banks() []*bank.Bank {\n\treturn this.banks\n}\n\nfunc (this *Rank) CanPush() bool {\n\treturn this.input_q.CanPush(1)\n}\n\nfunc (this *Rank) Push(rank_command *RankCommand) {\n\tif !this.CanPush() {\n\t\terr := errors.New(\"rank cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.input_q.Push(rank_command)\n}\n\nfunc (this *Rank) CanPop() bool {\n\treturn this.ready_q.CanPop(1)\n}\n\nfunc (this *Rank) Pop() *RankCommand {\n\tif !this.CanPop() {\n\t\terr := errors.New(\"rank cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\treturn this.ready_q.Pop()\n}\n\nfunc (this *Rank) Read(rank_command *RankCommand) {\n\tbank_id := rank_command.BankId()\n\n\tmemory_command := rank_command.MemoryCommand()\n\n\tbank_address := memory_command.BankAddress()\n\tsize := memory_command.Size()\n\n\tbyte_stream := this.banks[bank_id].Read(bank_address, size)\n\tmemory_command.SetByteStream(byte_stream)\n}\n\nfunc (this *Rank) Write(rank_command *RankCommand) {\n\tbank_id := rank_command.BankId()\n\n\tmemory_command := rank_command.MemoryCommand()\n\n\tbank_address := memory_command.BankAddress()\n\tsize := memory_command.Size()\n\tbyte_stream := memory_command.ByteStream()\n\n\tthis.banks[bank_id].Write(bank_address, size, byte_stream)\n}\n\nfunc (this *Rank) Flush() {\n\tfor _, bank_ := range this.banks {\n\t\tbank_.Flush()\n\t}\n}\n\nfunc (this *Rank) Cycle() {\n\tthis.ServiceInputQ()\n\tthis.ServiceReadyQ()\n\n\tthis.input_q.Cycle()\n\tthis.ready_q.Cycle()\n}\n\nfunc (this *Rank) ServiceInputQ() {\n\tif this.input_q.CanPop(1) {\n\t\trank_command, _ := this.input_q.Front(0)\n\n\t\tbank_id := rank_command.BankId()\n\t\tif this.banks[bank_id].CanPush() {\n\t\t\tthis.input_q.Pop()\n\n\t\t\tmemory_command := rank_command.MemoryCommand()\n\n\t\t\tthis.banks[bank_id].Push(memory_command)\n\t\t\tthis.scoreboard[memory_command] = rank_command\n\t\t}\n\t}\n}\n\nfunc (this *Rank) ServiceReadyQ() {\n\tfor _, bank_ := range this.banks {\n\t\tif bank_.CanPop() && this.ready_q.CanPush(1) {\n\t\t\tmemory_command := bank_.Pop()\n\t\t\trank_command := this.scoreboard[memory_command]\n\n\t\t\tthis.ready_q.Push(rank_command)\n\t\t\tdelete(this.scoreboard, memory_command)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/rank/rank_command.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n)\n\ntype RankCommand struct {\n\tchannel_id int\n\trank_id    int\n\tbank_id    int\n\n\tmemory_command *bank.MemoryCommand\n}\n\nfunc (this *RankCommand) Init(\n\tchannel_id int,\n\trank_id int,\n\tbank_id int,\n\tmemory_command *bank.MemoryCommand,\n) {\n\tif channel_id < 0 {\n\t\terr := errors.New(\"channel ID < 0\")\n\t\tpanic(err)\n\t} else if rank_id < 0 {\n\t\terr := errors.New(\"rank ID < 0\")\n\t\tpanic(err)\n\t} else if bank_id < 0 {\n\t\terr := errors.New(\"bank ID < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.channel_id = channel_id\n\tthis.rank_id = rank_id\n\tthis.bank_id = bank_id\n\n\tthis.memory_command = memory_command\n}\n\nfunc (this *RankCommand) ChannelId() int {\n\treturn this.channel_id\n}\n\nfunc (this *RankCommand) RankId() int {\n\treturn this.rank_id\n}\n\nfunc (this *RankCommand) BankId() int {\n\treturn this.bank_id\n}\n\nfunc (this *RankCommand) MemoryCommand() *bank.MemoryCommand {\n\treturn this.memory_command\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/dram/rank/rank_command_q.go",
    "content": "package rank\n\nimport (\n\t\"errors\"\n)\n\ntype RankCommandQ struct {\n\tsize  int\n\ttimer int64\n\n\trank_commands []*RankCommand\n\tcycles        []int64\n}\n\nfunc (this *RankCommandQ) Init(size int, timer int64) {\n\tif size == 0 {\n\t\terr := errors.New(\"size == 0\")\n\t\tpanic(err)\n\t} else if timer < 0 {\n\t\terr := errors.New(\"timer < 0\")\n\t\tpanic(err)\n\t}\n\n\tthis.size = size\n\tthis.timer = timer\n\n\tthis.rank_commands = make([]*RankCommand, 0)\n\tthis.cycles = make([]int64, 0)\n}\n\nfunc (this *RankCommandQ) Fini() {\n\tif !this.IsEmpty() {\n\t\terr := errors.New(\"rank command queue is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *RankCommandQ) Size() int {\n\treturn this.size\n}\n\nfunc (this *RankCommandQ) Length() int {\n\treturn len(this.rank_commands)\n}\n\nfunc (this *RankCommandQ) Timer() int64 {\n\treturn this.timer\n}\n\nfunc (this *RankCommandQ) IsEmpty() bool {\n\treturn len(this.rank_commands) == 0\n}\n\nfunc (this *RankCommandQ) CanPush(num_items int) bool {\n\tif this.size >= 0 {\n\t\treturn this.size-len(this.rank_commands) >= num_items\n\t} else {\n\t\treturn true\n\t}\n}\n\nfunc (this *RankCommandQ) Push(rank_command *RankCommand) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"rank command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.rank_commands = append(this.rank_commands, rank_command)\n\tthis.cycles = append(this.cycles, this.timer)\n}\n\nfunc (this *RankCommandQ) PushWithTimer(rank_command *RankCommand, timer int64) {\n\tif !this.CanPush(1) {\n\t\terr := errors.New(\"rank command queue cannot be pushed\")\n\t\tpanic(err)\n\t}\n\n\tthis.rank_commands = append(this.rank_commands, rank_command)\n\tthis.cycles = append(this.cycles, timer)\n}\n\nfunc (this *RankCommandQ) CanPop(num_items int) bool {\n\tif len(this.rank_commands) < num_items {\n\t\treturn false\n\t} else {\n\t\tfor i := 0; i < num_items; i++ {\n\t\t\tcycle := this.cycles[i]\n\n\t\t\tif cycle > 0 {\n\t\t\t\treturn false\n\t\t\t}\n\t\t}\n\t\treturn true\n\t}\n}\n\nfunc (this *RankCommandQ) Pop() *RankCommand {\n\tif !this.CanPop(1) {\n\t\terr := errors.New(\"rank command queue cannot be popped\")\n\t\tpanic(err)\n\t}\n\n\trank_command := this.rank_commands[0]\n\n\tthis.rank_commands = this.rank_commands[1:]\n\tthis.cycles = this.cycles[1:]\n\n\treturn rank_command\n}\n\nfunc (this *RankCommandQ) Front(pos int) (*RankCommand, int64) {\n\treturn this.rank_commands[pos], this.cycles[pos]\n}\n\nfunc (this *RankCommandQ) Remove(pos int) {\n\tthis.rank_commands = append(this.rank_commands[:pos], this.rank_commands[pos+1:]...)\n\tthis.cycles = append(this.cycles[:pos], this.cycles[pos+1:]...)\n}\n\nfunc (this *RankCommandQ) Cycle() {\n\tif !this.IsEmpty() {\n\t\tthis.cycles[0] -= 1\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/frame/frame.go",
    "content": "package frame\n\nimport (\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/host/vm/pc\"\n\t\"uPIMulator/src/host/vm/stack\"\n\t\"uPIMulator/src/host/vm/symbol\"\n)\n\ntype Frame struct {\n\tstack            *stack.Stack\n\treturn_stack     *stack.ReturnStack\n\tfast_scope_chain *symbol.ScopeChain\n\targ_scope        *symbol.Scope\n\tpc               *pc.Pc\n}\n\nfunc (this *Frame) Init(label *abi.Label) {\n\tthis.stack = new(stack.Stack)\n\tthis.stack.Init()\n\n\tthis.return_stack = new(stack.ReturnStack)\n\tthis.return_stack.Init()\n\n\tthis.fast_scope_chain = new(symbol.ScopeChain)\n\tthis.fast_scope_chain.Init()\n\n\tthis.arg_scope = new(symbol.Scope)\n\tthis.arg_scope.Init()\n\n\tthis.pc = new(pc.Pc)\n\tthis.pc.Init()\n\tthis.pc.Jump(label)\n}\n\nfunc (this *Frame) Stack() *stack.Stack {\n\treturn this.stack\n}\n\nfunc (this *Frame) ReturnStack() *stack.ReturnStack {\n\treturn this.return_stack\n}\n\nfunc (this *Frame) FastScopeChain() *symbol.ScopeChain {\n\treturn this.fast_scope_chain\n}\n\nfunc (this *Frame) ArgScope() *symbol.Scope {\n\treturn this.arg_scope\n}\n\nfunc (this *Frame) Pc() *pc.Pc {\n\treturn this.pc\n}\n\nfunc (this *Frame) Symbols() []*symbol.Symbol {\n\tsymbols := make([]*symbol.Symbol, 0)\n\tsymbols = append(symbols, this.fast_scope_chain.Symbols()...)\n\tsymbols = append(symbols, this.arg_scope.Symbols()...)\n\treturn symbols\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/frame/frame_chain.go",
    "content": "package frame\n\nimport (\n\t\"errors\"\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/host/vm/symbol\"\n)\n\ntype FrameChain struct {\n\tglobal_scope *symbol.Scope\n\tframes       []*Frame\n}\n\nfunc (this *FrameChain) Init() {\n\tthis.global_scope = new(symbol.Scope)\n\tthis.global_scope.Init()\n\n\tthis.frames = make([]*Frame, 0)\n}\n\nfunc (this *FrameChain) Bootstrap(label *abi.Label) {\n\tframe := new(Frame)\n\tframe.Init(label)\n\n\tthis.frames = append(this.frames, frame)\n}\n\nfunc (this *FrameChain) GlobalScope() *symbol.Scope {\n\treturn this.global_scope\n}\n\nfunc (this *FrameChain) Length() int {\n\treturn len(this.frames)\n}\n\nfunc (this *FrameChain) Symbols() []*symbol.Symbol {\n\tsymbols := make([]*symbol.Symbol, 0)\n\n\tsymbols = append(symbols, this.global_scope.Symbols()...)\n\n\tfor _, frame := range this.frames {\n\t\tsymbols = append(symbols, frame.Symbols()...)\n\t}\n\n\treturn symbols\n}\n\nfunc (this *FrameChain) HasObject(address int64) bool {\n\tfor _, frame := range this.frames {\n\t\tif frame.Stack().HasObject(address) || frame.ReturnStack().HasObject(address) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *FrameChain) NewFrame(label *abi.Label) {\n\tframe := new(Frame)\n\tframe.Init(label)\n\n\tframe.FastScopeChain().NewScope()\n\tfor _, symbol_ := range this.LastFrame().ArgScope().Symbols() {\n\t\tframe.FastScopeChain().AddSymbol(symbol_)\n\t}\n\tthis.LastFrame().ArgScope().Clear()\n\n\tthis.frames = append(this.frames, frame)\n}\n\nfunc (this *FrameChain) DeleteFrame() {\n\tlast_frame := this.LastFrame()\n\n\tif len(this.frames) >= 2 {\n\t\tfor i := 0; i < last_frame.ReturnStack().Length(); i++ {\n\t\t\tstack_item := last_frame.ReturnStack().Front(0)\n\t\t\tlast_frame.ReturnStack().Pop()\n\n\t\t\tthis.frames[len(this.frames)-2].Stack().Push(stack_item)\n\t\t}\n\t}\n\n\tthis.frames = this.frames[:len(this.frames)-1]\n}\n\nfunc (this *FrameChain) Frame(pos int) *Frame {\n\treturn this.frames[pos]\n}\n\nfunc (this *FrameChain) LastFrame() *Frame {\n\treturn this.frames[len(this.frames)-1]\n}\n\nfunc (this *FrameChain) CanAdvance() bool {\n\tfor this.Length() > 0 {\n\t\tlast_frame := this.LastFrame()\n\t\tif last_frame.Pc().CanAdvance() {\n\t\t\treturn true\n\t\t} else {\n\t\t\tthis.DeleteFrame()\n\t\t}\n\t}\n\n\treturn false\n}\n\nfunc (this *FrameChain) Advance() *abi.Bytecode {\n\tif !this.CanAdvance() {\n\t\terr := errors.New(\"frame chain cannot advance\")\n\t\tpanic(err)\n\t}\n\n\treturn this.LastFrame().Pc().Advance()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/pc/pc.go",
    "content": "package pc\n\nimport (\n\t\"uPIMulator/src/host/abi\"\n)\n\ntype Pc struct {\n\tlabel *abi.Label\n\tindex int\n}\n\nfunc (this *Pc) Init() {\n\tthis.label = nil\n\tthis.index = 0\n}\n\nfunc (this *Pc) CanAdvance() bool {\n\treturn this.index < this.label.Length()\n}\n\nfunc (this *Pc) Advance() *abi.Bytecode {\n\tbytecode := this.label.Get(this.index)\n\n\tthis.index++\n\n\treturn bytecode\n}\n\nfunc (this *Pc) Jump(label *abi.Label) {\n\tthis.label = label\n\tthis.index = 0\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/stack/return_stack.go",
    "content": "package stack\n\ntype ReturnStack struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *ReturnStack) Init() {\n\tthis.stack_items = make([]*StackItem, 0)\n}\n\nfunc (this *ReturnStack) Front(pos int) *StackItem {\n\treturn this.stack_items[len(this.stack_items)-1-pos]\n}\n\nfunc (this *ReturnStack) Push(stack_item *StackItem) {\n\tthis.stack_items = append(this.stack_items, stack_item)\n}\n\nfunc (this *ReturnStack) Pop() {\n\tthis.stack_items = this.stack_items[:len(this.stack_items)-1]\n}\n\nfunc (this *ReturnStack) HasObject(address int64) bool {\n\tfor _, stack_item := range this.stack_items {\n\t\tif stack_item.Address() == address {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *ReturnStack) Length() int {\n\treturn len(this.stack_items)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/stack/stack.go",
    "content": "package stack\n\ntype Stack struct {\n\tstack_items []*StackItem\n}\n\nfunc (this *Stack) Init() {\n\tthis.stack_items = make([]*StackItem, 0)\n}\n\nfunc (this *Stack) Front(pos int) *StackItem {\n\treturn this.stack_items[len(this.stack_items)-1-pos]\n}\n\nfunc (this *Stack) Push(stack_item *StackItem) {\n\tthis.stack_items = append(this.stack_items, stack_item)\n}\n\nfunc (this *Stack) Pop() {\n\tthis.stack_items = this.stack_items[:len(this.stack_items)-1]\n}\n\nfunc (this *Stack) HasObject(address int64) bool {\n\tfor _, stack_item := range this.stack_items {\n\t\tif stack_item.Address() == address {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Stack) Length() int {\n\treturn len(this.stack_items)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/stack/stack_item.go",
    "content": "package stack\n\nimport (\n\t\"uPIMulator/src/host/vm/type_system\"\n)\n\ntype StackItem struct {\n\ttype_variable *type_system.TypeVariable\n\taddress       int64\n\tsize          int64\n}\n\nfunc (this *StackItem) Init(type_variable *type_system.TypeVariable, address int64, size int64) {\n\tthis.type_variable = type_variable\n\tthis.address = address\n\tthis.size = size\n}\n\nfunc (this *StackItem) TypeVariable() *type_system.TypeVariable {\n\treturn this.type_variable\n}\n\nfunc (this *StackItem) Address() int64 {\n\treturn this.address\n}\n\nfunc (this *StackItem) Size() int64 {\n\treturn this.size\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/symbol/scope.go",
    "content": "package symbol\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype Scope struct {\n\tsymbols map[string]*Symbol\n}\n\nfunc (this *Scope) Init() {\n\tthis.symbols = make(map[string]*Symbol)\n}\n\nfunc (this *Scope) HasSymbol(symbol_name string) bool {\n\t_, found := this.symbols[symbol_name]\n\treturn found\n}\n\nfunc (this *Scope) Symbol(symbol_name string) *Symbol {\n\tif !this.HasSymbol(symbol_name) {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) is not found\", symbol_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\treturn this.symbols[symbol_name]\n}\n\nfunc (this *Scope) Symbols() []*Symbol {\n\tsymbols := make([]*Symbol, 0)\n\tfor _, symbol := range this.symbols {\n\t\tsymbols = append(symbols, symbol)\n\t}\n\treturn symbols\n}\n\nfunc (this *Scope) AddSymbol(symbol *Symbol) {\n\tif this.HasSymbol(symbol.Name()) {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) already exists\", symbol.Name())\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tthis.symbols[symbol.Name()] = symbol\n}\n\nfunc (this *Scope) HasObject(address int64) bool {\n\tfor _, symbol := range this.symbols {\n\t\tif symbol.Object().Address() == address {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Scope) Clear() {\n\tthis.symbols = make(map[string]*Symbol)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/symbol/scope_chain.go",
    "content": "package symbol\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype ScopeChain struct {\n\tscopes []*Scope\n}\n\nfunc (this *ScopeChain) Init() {\n\tthis.scopes = make([]*Scope, 0)\n}\n\nfunc (this *ScopeChain) NewScope() {\n\tscope := new(Scope)\n\tscope.Init()\n\n\tthis.scopes = append(this.scopes, scope)\n}\n\nfunc (this *ScopeChain) DeleteScope() {\n\tthis.scopes = this.scopes[:len(this.scopes)-1]\n}\n\nfunc (this *ScopeChain) LastScope() *Scope {\n\treturn this.scopes[len(this.scopes)-1]\n}\n\nfunc (this *ScopeChain) HasSymbol(symbol_name string) bool {\n\tfor i := len(this.scopes) - 1; i >= 0; i-- {\n\t\tscope := this.scopes[i]\n\n\t\tif scope.HasSymbol(symbol_name) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *ScopeChain) Symbol(symbol_name string) *Symbol {\n\tif !this.HasSymbol(symbol_name) {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) is not found\", symbol_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor i := len(this.scopes) - 1; i >= 0; i-- {\n\t\tscope := this.scopes[i]\n\n\t\tif scope.HasSymbol(symbol_name) {\n\t\t\treturn scope.Symbol(symbol_name)\n\t\t}\n\t}\n\treturn nil\n}\n\nfunc (this *ScopeChain) Symbols() []*Symbol {\n\tsymbols := make([]*Symbol, 0)\n\n\tfor i := 0; i < len(this.scopes); i++ {\n\t\tscope := this.scopes[i]\n\n\t\tsymbols = append(symbols, scope.Symbols()...)\n\t}\n\n\treturn symbols\n}\n\nfunc (this *ScopeChain) AddSymbol(symbol *Symbol) {\n\tif this.scopes[len(this.scopes)-1].HasSymbol(symbol.Name()) {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) already exists\", symbol.Name())\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tscope := this.scopes[len(this.scopes)-1]\n\tscope.AddSymbol(symbol)\n}\n\nfunc (this *ScopeChain) HasObject(address int64) bool {\n\tfor _, scope := range this.scopes {\n\t\tif scope.HasObject(address) {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/symbol/symbol.go",
    "content": "package symbol\n\nimport (\n\t\"uPIMulator/src/host/vm/base\"\n\t\"uPIMulator/src/host/vm/type_system\"\n)\n\ntype Symbol struct {\n\tname          string\n\ttype_variable *type_system.TypeVariable\n\tobject        *base.Object\n}\n\nfunc (this *Symbol) Init(\n\tname string,\n\ttype_variable *type_system.TypeVariable,\n\tobject *base.Object,\n) {\n\tthis.name = name\n\tthis.type_variable = type_variable\n\tthis.object = object\n}\n\nfunc (this *Symbol) Name() string {\n\treturn this.name\n}\n\nfunc (this *Symbol) TypeVariable() *type_system.TypeVariable {\n\treturn this.type_variable\n}\n\nfunc (this *Symbol) Object() *base.Object {\n\treturn this.object\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/type_system/field.go",
    "content": "package type_system\n\ntype Field struct {\n\ttype_variable *TypeVariable\n\tname          string\n}\n\nfunc (this *Field) Init(type_variable *TypeVariable, name string) {\n\tthis.type_variable = type_variable\n\tthis.name = name\n}\n\nfunc (this *Field) TypeVariable() *TypeVariable {\n\treturn this.type_variable\n}\n\nfunc (this *Field) Name() string {\n\treturn this.name\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/type_system/registry.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype TypeRegistry struct {\n\tskeletons map[string]*Skeleton\n}\n\nfunc (this *TypeRegistry) Init() {\n\tthis.skeletons = make(map[string]*Skeleton)\n}\n\nfunc (this *TypeRegistry) HasSkeleton(skeleton_name string) bool {\n\t_, found := this.skeletons[skeleton_name]\n\treturn found\n}\n\nfunc (this *TypeRegistry) Skeleton(skeleton_name string) *Skeleton {\n\tif !this.HasSkeleton(skeleton_name) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) is not found\", skeleton_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\treturn this.skeletons[skeleton_name]\n}\n\nfunc (this *TypeRegistry) AddSkeleton(skeleton *Skeleton) {\n\tif this.HasSkeleton(skeleton.Name()) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) already exists\", skeleton.Name())\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tthis.skeletons[skeleton.Name()] = skeleton\n}\n\nfunc (this *TypeRegistry) SkeletonSize(skeleton_name string) int64 {\n\tif !this.HasSkeleton(skeleton_name) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) is not found\", skeleton_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tskeleton := this.Skeleton(skeleton_name)\n\n\toffset := int64(0)\n\tfor i := 0; i < skeleton.Length(); i++ {\n\t\tfield := skeleton.Get(i)\n\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\toffset += 4\n\t\t} else {\n\t\t\tif field.TypeVariable().TypeVariableType() == VOID {\n\t\t\t\terr := errors.New(\"type variable type is void\")\n\t\t\t\tpanic(err)\n\t\t\t} else if field.TypeVariable().TypeVariableType() == CHAR {\n\t\t\t\toffset += 1\n\t\t\t} else if field.TypeVariable().TypeVariableType() == SHORT {\n\t\t\t\toffset += 2\n\t\t\t} else if field.TypeVariable().TypeVariableType() == INT {\n\t\t\t\toffset += 4\n\t\t\t} else if field.TypeVariable().TypeVariableType() == LONG {\n\t\t\t\toffset += 8\n\t\t\t} else if field.TypeVariable().TypeVariableType() == STRUCT {\n\t\t\t\toffset += this.SkeletonSize(field.TypeVariable().StructName())\n\t\t\t}\n\t\t}\n\t}\n\treturn offset\n}\n\nfunc (this *TypeRegistry) FieldOffset(skeleton_name string, field_name string) int64 {\n\tif !this.HasSkeleton(skeleton_name) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) is not found\", skeleton_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tskeleton := this.Skeleton(skeleton_name)\n\n\toffset := int64(0)\n\tfor i := 0; i < skeleton.Length(); i++ {\n\t\tfield := skeleton.Get(i)\n\n\t\tif field.Name() == field_name {\n\t\t\tbreak\n\t\t}\n\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\toffset += 4\n\t\t} else {\n\t\t\tif field.TypeVariable().TypeVariableType() == VOID {\n\t\t\t\terr := errors.New(\"type variable type is void\")\n\t\t\t\tpanic(err)\n\t\t\t} else if field.TypeVariable().TypeVariableType() == CHAR {\n\t\t\t\toffset += 1\n\t\t\t} else if field.TypeVariable().TypeVariableType() == SHORT {\n\t\t\t\toffset += 2\n\t\t\t} else if field.TypeVariable().TypeVariableType() == INT {\n\t\t\t\toffset += 4\n\t\t\t} else if field.TypeVariable().TypeVariableType() == LONG {\n\t\t\t\toffset += 8\n\t\t\t} else if field.TypeVariable().TypeVariableType() == STRUCT {\n\t\t\t\toffset += this.SkeletonSize(field.TypeVariable().StructName())\n\t\t\t} else {\n\t\t\t\terr := errors.New(\"type variable type is not valid\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n\treturn offset\n}\n\nfunc (this *TypeRegistry) FieldSize(skeleton_name string, field_name string) int64 {\n\tif !this.HasSkeleton(skeleton_name) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) is not found\", skeleton_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tskeleton := this.Skeleton(skeleton_name)\n\tfield := skeleton.Field(field_name)\n\n\tif field.TypeVariable().NumStars() > 0 {\n\t\treturn 4\n\t} else {\n\t\tif field.TypeVariable().TypeVariableType() == VOID {\n\t\t\terr := errors.New(\"type variable type is void\")\n\t\t\tpanic(err)\n\t\t} else if field.TypeVariable().TypeVariableType() == CHAR {\n\t\t\treturn 1\n\t\t} else if field.TypeVariable().TypeVariableType() == SHORT {\n\t\t\treturn 2\n\t\t} else if field.TypeVariable().TypeVariableType() == INT {\n\t\t\treturn 4\n\t\t} else if field.TypeVariable().TypeVariableType() == LONG {\n\t\t\treturn 8\n\t\t} else if field.TypeVariable().TypeVariableType() == STRUCT {\n\t\t\treturn this.SkeletonSize(field.TypeVariable().StructName())\n\t\t} else {\n\t\t\terr := errors.New(\"type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/type_system/skeleton.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n)\n\ntype Skeleton struct {\n\tname   string\n\tfields []*Field\n}\n\nfunc (this *Skeleton) Init(name string) {\n\tthis.name = name\n}\n\nfunc (this *Skeleton) Name() string {\n\treturn this.name\n}\n\nfunc (this *Skeleton) HasField(field_name string) bool {\n\tfor _, field := range this.fields {\n\t\tif field.Name() == field_name {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *Skeleton) Field(field_name string) *Field {\n\tif !this.HasField(field_name) {\n\t\terr_msg := fmt.Sprintf(\"skeleton (%s) does not have the field (%s)\", this.name, field_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor _, field := range this.fields {\n\t\tif field.Name() == field_name {\n\t\t\treturn field\n\t\t}\n\t}\n\treturn nil\n}\n\nfunc (this *Skeleton) Fields() []*Field {\n\treturn this.fields\n}\n\nfunc (this *Skeleton) Length() int {\n\treturn len(this.fields)\n}\n\nfunc (this *Skeleton) Get(pos int) *Field {\n\treturn this.fields[pos]\n}\n\nfunc (this *Skeleton) Append(field *Field) {\n\tthis.fields = append(this.fields, field)\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/type_system/type_variable.go",
    "content": "package type_system\n\nimport (\n\t\"errors\"\n)\n\ntype TypeVariableType int\n\nconst (\n\tVOID TypeVariableType = iota\n\tCHAR\n\tSHORT\n\tINT\n\tLONG\n\tSTRING\n\tSTRUCT\n)\n\ntype TypeVariable struct {\n\ttype_variable_type TypeVariableType\n\tstruct_name        *string\n\tnum_stars          int\n}\n\nfunc (this *TypeVariable) InitPrimitive(type_variable_type TypeVariableType, num_stars int) {\n\tif type_variable_type == STRUCT {\n\t\terr := errors.New(\"type variable type is struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_variable_type = type_variable_type\n\tthis.struct_name = nil\n\tthis.num_stars = num_stars\n}\n\nfunc (this *TypeVariable) InitStruct(\n\ttype_variable_type TypeVariableType,\n\tstruct_name string,\n\tnum_stars int,\n) {\n\tif type_variable_type != STRUCT {\n\t\terr := errors.New(\"type variable type isn't struct\")\n\t\tpanic(err)\n\t}\n\n\tthis.type_variable_type = type_variable_type\n\n\tthis.struct_name = new(string)\n\t*this.struct_name = struct_name\n\n\tthis.num_stars = num_stars\n}\n\nfunc (this *TypeVariable) TypeVariableType() TypeVariableType {\n\treturn this.type_variable_type\n}\n\nfunc (this *TypeVariable) StructName() string {\n\tif this.struct_name == nil {\n\t\terr := errors.New(\"struct name == nil\")\n\t\tpanic(err)\n\t}\n\n\treturn *this.struct_name\n}\n\nfunc (this *TypeVariable) NumStars() int {\n\treturn this.num_stars\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/host/vm/virtual_machine.go",
    "content": "package vm\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"math\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/device/core\"\n\t\"uPIMulator/src/device/simulator/channel\"\n\t\"uPIMulator/src/device/simulator/dpu\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/host/vm/arena\"\n\t\"uPIMulator/src/host/vm/base\"\n\t\"uPIMulator/src/host/vm/dram\"\n\t\"uPIMulator/src/host/vm/dram/bank\"\n\t\"uPIMulator/src/host/vm/frame\"\n\t\"uPIMulator/src/host/vm/stack\"\n\t\"uPIMulator/src/host/vm/symbol\"\n\t\"uPIMulator/src/host/vm/type_system\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/program\"\n)\n\ntype VirtualMachine struct {\n\tbin_dirpath string\n\n\tnum_channels          int\n\tnum_ranks_per_channel int\n\tnum_dpus_per_rank     int\n\n\tnum_dpus int\n\n\tverbose int\n\n\tapp  *program.App\n\ttask *program.Task\n\n\tarena             *arena.Arena\n\tframe_chain       *frame.FrameChain\n\ttype_registry     *type_system.TypeRegistry\n\tgarbage_collector *arena.GarbageCollector\n\n\tcur_skeleton_name *string\n\n\tmemory_controller *dram.MemoryController\n\tchannels          []*channel.Channel\n\n\tprepare_xfer_buf map[*dpu.Dpu]int64\n\tpush_xfer        map[*bank.TransferCommand]bool\n}\n\nfunc (this *VirtualMachine) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\n\tthis.num_channels = int(command_line_parser.IntParameter(\"num_channels\"))\n\tthis.num_ranks_per_channel = int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tthis.num_dpus_per_rank = int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\n\tthis.num_dpus = this.num_channels * this.num_ranks_per_channel * this.num_dpus_per_rank\n\n\tthis.verbose = int(command_line_parser.IntParameter(\"verbose\"))\n\n\tthis.app = nil\n\tthis.task = nil\n\n\tthis.arena = new(arena.Arena)\n\tthis.arena.Init()\n\n\tthis.frame_chain = new(frame.FrameChain)\n\tthis.frame_chain.Init()\n\n\tthis.type_registry = new(type_system.TypeRegistry)\n\tthis.type_registry.Init()\n\n\tthis.garbage_collector = new(arena.GarbageCollector)\n\tthis.garbage_collector.Init()\n\tthis.garbage_collector.ConnectArena(this.arena)\n\tthis.garbage_collector.ConnectFrameChain(this.frame_chain)\n\tthis.garbage_collector.ConnectRegistry(this.type_registry)\n\n\tthis.cur_skeleton_name = nil\n\n\tthis.memory_controller = new(dram.MemoryController)\n\tthis.memory_controller.Init(command_line_parser)\n\n\tthis.channels = make([]*channel.Channel, 0)\n\tfor i := 0; i < this.num_channels; i++ {\n\t\tchannel_ := new(channel.Channel)\n\t\tchannel_.Init(i, command_line_parser)\n\n\t\tthis.channels = append(this.channels, channel_)\n\t}\n\n\tthis.memory_controller.ConnectChannels(this.channels)\n\n\tthis.prepare_xfer_buf = make(map[*dpu.Dpu]int64)\n\tthis.push_xfer = make(map[*bank.TransferCommand]bool)\n}\n\nfunc (this *VirtualMachine) Fini() {\n\tfor _, channel_ := range this.channels {\n\t\tchannel_.Fini()\n\t}\n\n\tthis.memory_controller.Fini()\n\n\tif len(this.prepare_xfer_buf) != 0 {\n\t\terr := errors.New(\"VM's prepare xfer buf is not empty\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *VirtualMachine) Load(app *program.App, task *program.Task) {\n\tthis.app = app\n\tthis.task = task\n\n\tbootstrap := this.app.Label(\"__bootstrap\")\n\tthis.frame_chain.Bootstrap(bootstrap)\n}\n\nfunc (this *VirtualMachine) CanAdvance() bool {\n\treturn this.frame_chain.CanAdvance()\n}\n\nfunc (this *VirtualMachine) Advance() {\n\tif !this.frame_chain.CanAdvance() {\n\t\terr := errors.New(\"frame chain cannot advance\")\n\t\tpanic(err)\n\t}\n\n\tthis.garbage_collector.MarkAndSweep()\n\n\tbytecode := this.frame_chain.Advance()\n\n\tif this.verbose >= 1 {\n\t\tfmt.Printf(\"%s\\n\", bytecode.Stringify())\n\t}\n\n\tif bytecode.OpCode() == abi.NEW_SCOPE {\n\t\tthis.frame_chain.LastFrame().FastScopeChain().NewScope()\n\t} else if bytecode.OpCode() == abi.DELETE_SCOPE {\n\t\tthis.frame_chain.LastFrame().FastScopeChain().DeleteScope()\n\t} else if bytecode.OpCode() == abi.PUSH_CHAR {\n\t\tvalue := bytecode.Arg1()\n\t\tthis.PushChar(value)\n\t} else if bytecode.OpCode() == abi.PUSH_SHORT {\n\t\tvalue := bytecode.Arg1()\n\t\tthis.PushShort(value)\n\t} else if bytecode.OpCode() == abi.PUSH_INT {\n\t\tvalue := bytecode.Arg1()\n\t\tthis.PushInt(value)\n\t} else if bytecode.OpCode() == abi.PUSH_LONG {\n\t\tvalue := bytecode.Arg1()\n\t\tthis.PushLong(value)\n\t} else if bytecode.OpCode() == abi.PUSH_STRING {\n\t\tvalue := bytecode.Str1()\n\t\tthis.PushString(value)\n\t} else if bytecode.OpCode() == abi.POP {\n\t\tthis.Pop()\n\t} else if bytecode.OpCode() == abi.BEGIN_STRUCT {\n\t\tskeleton_name := bytecode.Str1()\n\t\tthis.BeginStruct(skeleton_name)\n\t} else if bytecode.OpCode() == abi.APPEND_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tfield_name := bytecode.Str1()\n\t\tthis.AppendVoid(num_stars, field_name)\n\t} else if bytecode.OpCode() == abi.APPEND_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tfield_name := bytecode.Str1()\n\t\tthis.AppendChar(num_stars, field_name)\n\t} else if bytecode.OpCode() == abi.APPEND_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tfield_name := bytecode.Str1()\n\t\tthis.AppendShort(num_stars, field_name)\n\t} else if bytecode.OpCode() == abi.APPEND_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tfield_name := bytecode.Str1()\n\t\tthis.AppendInt(num_stars, field_name)\n\t} else if bytecode.OpCode() == abi.APPEND_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tfield_name := bytecode.Str1()\n\t\tthis.AppendLong(num_stars, field_name)\n\t} else if bytecode.OpCode() == abi.APPEND_STRUCT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tstruct_name := bytecode.Str1()\n\t\tfield_name := bytecode.Str2()\n\t\tthis.AppendStruct(num_stars, struct_name, field_name)\n\t} else if bytecode.OpCode() == abi.END_STRUCT {\n\t\tthis.EndStruct()\n\t} else if bytecode.OpCode() == abi.NEW_GLOBAL_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewGlobalVoid(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_GLOBAL_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewGlobalChar(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_GLOBAL_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewGlobalShort(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_GLOBAL_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewGlobalInt(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_GLOBAL_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewGlobalLong(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewFastVoid(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewFastChar(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewFastShort(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewFastInt(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewFastLong(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_FAST_STRUCT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tstruct_name := bytecode.Str1()\n\t\tsymbol_name := bytecode.Str2()\n\t\tthis.NewFastStruct(num_stars, struct_name, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewArgVoid(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewArgChar(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewArgShort(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewArgInt(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.NewArgLong(num_stars, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_ARG_STRUCT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tstruct_name := bytecode.Str1()\n\t\tsymbol_name := bytecode.Str2()\n\t\tthis.NewArgStruct(num_stars, struct_name, symbol_name)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.NewReturnVoid(num_stars)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.NewReturnChar(num_stars)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.NewReturnShort(num_stars)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.NewReturnInt(num_stars)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.NewReturnLong(num_stars)\n\t} else if bytecode.OpCode() == abi.NEW_RETURN_STRUCT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tstruct_name := bytecode.Str1()\n\t\tthis.NewReturnStruct(num_stars, struct_name)\n\t} else if bytecode.OpCode() == abi.SIZEOF_VOID {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.SizeofVoid(num_stars)\n\t} else if bytecode.OpCode() == abi.SIZEOF_CHAR {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.SizeofChar(num_stars)\n\t} else if bytecode.OpCode() == abi.SIZEOF_SHORT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.SizeofShort(num_stars)\n\t} else if bytecode.OpCode() == abi.SIZEOF_INT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.SizeofInt(num_stars)\n\t} else if bytecode.OpCode() == abi.SIZEOF_LONG {\n\t\tnum_stars := bytecode.Arg1()\n\t\tthis.SizeofLong(num_stars)\n\t} else if bytecode.OpCode() == abi.SIZEOF_STRUCT {\n\t\tnum_stars := bytecode.Arg1()\n\t\tstruct_name := bytecode.Str1()\n\t\tthis.SizeofStruct(num_stars, struct_name)\n\t} else if bytecode.OpCode() == abi.GET_IDENTIFIER {\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.GetIdentifier(symbol_name)\n\t} else if bytecode.OpCode() == abi.GET_ARG_IDENTIFIER {\n\t\tsymbol_name := bytecode.Str1()\n\t\tthis.GetArgIdentifier(symbol_name)\n\t} else if bytecode.OpCode() == abi.GET_SUBSCRIPT {\n\t\tthis.GetSubscript()\n\t} else if bytecode.OpCode() == abi.GET_ACCESS {\n\t\tfield_name := bytecode.Str1()\n\t\tthis.GetAccess(field_name)\n\t} else if bytecode.OpCode() == abi.GET_REFERENCE {\n\t\tfield_name := bytecode.Str1()\n\t\tthis.GetReference(field_name)\n\t} else if bytecode.OpCode() == abi.GET_ADDRESS {\n\t\tthis.GetAddress()\n\t} else if bytecode.OpCode() == abi.GET_VALUE {\n\t\tthis.GetValue()\n\t} else if bytecode.OpCode() == abi.ALLOC {\n\t\tthis.Alloc()\n\t} else if bytecode.OpCode() == abi.FREE {\n\t\tthis.Free()\n\t} else if bytecode.OpCode() == abi.ASSERT {\n\t\tthis.Assert()\n\t} else if bytecode.OpCode() == abi.ADD {\n\t\tthis.Add()\n\t} else if bytecode.OpCode() == abi.SUB {\n\t\tthis.Sub()\n\t} else if bytecode.OpCode() == abi.MUL {\n\t\tthis.Mul()\n\t} else if bytecode.OpCode() == abi.DIV {\n\t\tthis.Div()\n\t} else if bytecode.OpCode() == abi.MOD {\n\t\tthis.Mod()\n\t} else if bytecode.OpCode() == abi.LSHIFT {\n\t\tthis.Lshift()\n\t} else if bytecode.OpCode() == abi.RSHIFT {\n\t\tthis.Rshift()\n\t} else if bytecode.OpCode() == abi.NEGATE {\n\t\tthis.Negate()\n\t} else if bytecode.OpCode() == abi.TILDE {\n\t\tthis.Tilde()\n\t} else if bytecode.OpCode() == abi.SQRT {\n\t\tthis.Sqrt()\n\t} else if bytecode.OpCode() == abi.BITWISE_AND {\n\t\tthis.BitwiseAnd()\n\t} else if bytecode.OpCode() == abi.BITWISE_XOR {\n\t\tthis.BitwiseXor()\n\t} else if bytecode.OpCode() == abi.BITWISE_OR {\n\t\tthis.BitwiseOr()\n\t} else if bytecode.OpCode() == abi.LOGICAL_AND {\n\t\tthis.LogicalAnd()\n\t} else if bytecode.OpCode() == abi.LOGICAL_OR {\n\t\tthis.LogicalOr()\n\t} else if bytecode.OpCode() == abi.LOGICAL_NOT {\n\t\tthis.LogicalNot()\n\t} else if bytecode.OpCode() == abi.EQ {\n\t\tthis.Eq()\n\t} else if bytecode.OpCode() == abi.NOT_EQ {\n\t\tthis.NotEq()\n\t} else if bytecode.OpCode() == abi.LESS {\n\t\tthis.Less()\n\t} else if bytecode.OpCode() == abi.LESS_EQ {\n\t\tthis.LessEq()\n\t} else if bytecode.OpCode() == abi.GREATER {\n\t\tthis.Greater()\n\t} else if bytecode.OpCode() == abi.GREATER_EQ {\n\t\tthis.GreaterEq()\n\t} else if bytecode.OpCode() == abi.CONDITIONAL {\n\t\tthis.Conditional()\n\t} else if bytecode.OpCode() == abi.ASSIGN {\n\t\tthis.Assign()\n\t} else if bytecode.OpCode() == abi.ASSIGN_STAR {\n\t\tthis.AssignStar()\n\t} else if bytecode.OpCode() == abi.ASSIGN_DIV {\n\t\tthis.AssignDiv()\n\t} else if bytecode.OpCode() == abi.ASSIGN_MOD {\n\t\tthis.AssignMod()\n\t} else if bytecode.OpCode() == abi.ASSIGN_ADD {\n\t\tthis.AssignAdd()\n\t} else if bytecode.OpCode() == abi.ASSIGN_SUB {\n\t\tthis.AssignSub()\n\t} else if bytecode.OpCode() == abi.ASSIGN_LSHIFT {\n\t\tthis.AssignLshift()\n\t} else if bytecode.OpCode() == abi.ASSIGN_RSHIFT {\n\t\tthis.AssignRshift()\n\t} else if bytecode.OpCode() == abi.ASSIGN_BITWISE_AND {\n\t\tthis.AssignBitwiseAnd()\n\t} else if bytecode.OpCode() == abi.ASSIGN_BITWISE_XOR {\n\t\tthis.AssignBitwiseXor()\n\t} else if bytecode.OpCode() == abi.ASSIGN_BITWISE_OR {\n\t\tthis.AssignBitwiseOr()\n\t} else if bytecode.OpCode() == abi.ASSIGN_PLUS_PLUS {\n\t\tthis.AssignPlusPlus()\n\t} else if bytecode.OpCode() == abi.ASSIGN_MINUS_MINUS {\n\t\tthis.AssignMinusMinus()\n\t} else if bytecode.OpCode() == abi.ASSIGN_RETURN {\n\t\tthis.AssignReturn()\n\t} else if bytecode.OpCode() == abi.JUMP {\n\t\tlabel_name := bytecode.Str1()\n\t\tlabel := this.app.Label(label_name)\n\n\t\tthis.Jump(label)\n\t} else if bytecode.OpCode() == abi.JUMP_IF_ZERO {\n\t\tlabel_name := bytecode.Str1()\n\t\tlabel := this.app.Label(label_name)\n\n\t\tthis.JumpIfZero(label)\n\t} else if bytecode.OpCode() == abi.JUMP_IF_NONZERO {\n\t\tlabel_name := bytecode.Str1()\n\t\tlabel := this.app.Label(label_name)\n\n\t\tthis.JumpIfNonZero(label)\n\t} else if bytecode.OpCode() == abi.CALL {\n\t\tlabel_name := bytecode.Str1()\n\t\tlabel := this.app.Label(label_name)\n\n\t\tthis.Call(label)\n\t} else if bytecode.OpCode() == abi.RETURN {\n\t\tthis.Return()\n\t} else if bytecode.OpCode() == abi.NOP {\n\t\tthis.Nop()\n\t} else if bytecode.OpCode() == abi.DPU_ALLOC {\n\t\tdpu_id := bytecode.Arg1()\n\n\t\tthis.DpuAlloc(dpu_id)\n\t} else if bytecode.OpCode() == abi.DPU_LOAD {\n\t\tthis.DpuLoad()\n\t} else if bytecode.OpCode() == abi.DPU_PREPARE {\n\t\tthis.DpuPrepare()\n\t} else if bytecode.OpCode() == abi.DPU_TRANSFER {\n\t\tthis.DpuTransfer()\n\t} else if bytecode.OpCode() == abi.DPU_COPY_TO {\n\t\tthis.DpuCopyTo()\n\t} else if bytecode.OpCode() == abi.DPU_COPY_FROM {\n\t\tthis.DpuCopyFrom()\n\t} else if bytecode.OpCode() == abi.DPU_LAUNCH {\n\t\tthis.DpuLaunch()\n\t} else if bytecode.OpCode() == abi.DPU_FREE {\n\t\tthis.DpuFree()\n\t} else {\n\t\terr := errors.New(\"op code is not valid\")\n\t\tpanic(err)\n\t}\n\n\tif this.verbose >= 2 {\n\t\tfmt.Printf(\"%s\\n\", this.Stringify())\n\t}\n}\n\nfunc (this *VirtualMachine) PushChar(value int64) {\n\tobject := this.arena.NewChar(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) PushShort(value int64) {\n\tobject := this.arena.NewShort(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) PushInt(value int64) {\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) PushLong(value int64) {\n\tobject := this.arena.NewLong(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) PushString(value string) {\n\tobject := this.arena.NewString(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.STRING, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Pop() {\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) BeginStruct(skeleton_name string) {\n\tskeleton := new(type_system.Skeleton)\n\tskeleton.Init(skeleton_name)\n\n\tthis.type_registry.AddSkeleton(skeleton)\n\n\tthis.cur_skeleton_name = new(string)\n\t*this.cur_skeleton_name = skeleton_name\n}\n\nfunc (this *VirtualMachine) AppendVoid(num_stars int64, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) AppendChar(num_stars int64, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) AppendShort(num_stars int64, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) AppendInt(num_stars int64, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) AppendLong(num_stars int64, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) AppendStruct(num_stars int64, struct_name string, field_name string) {\n\tskeleton := this.type_registry.Skeleton(*this.cur_skeleton_name)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitStruct(type_system.STRUCT, struct_name, int(num_stars))\n\n\tfield := new(type_system.Field)\n\tfield.Init(type_variable, field_name)\n\n\tskeleton.Append(field)\n}\n\nfunc (this *VirtualMachine) EndStruct() {\n\tthis.cur_skeleton_name = nil\n}\n\nfunc (this *VirtualMachine) NewGlobalVoid(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.GlobalScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewGlobalChar(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewChar(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.GlobalScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewGlobalShort(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewShort(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.GlobalScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewGlobalInt(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.GlobalScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewGlobalLong(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewLong(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.GlobalScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastVoid(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastChar(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewChar(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastShort(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewShort(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastInt(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastLong(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewLong(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewFastStruct(num_stars int64, struct_name string, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewStruct(struct_name, this.type_registry.SkeletonSize(struct_name))\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitStruct(type_system.STRUCT, struct_name, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().FastScopeChain().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgVoid(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgChar(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewChar(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgShort(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewShort(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgInt(num_stars int64, symbol_name string) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgLong(num_stars int64, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewLong(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewArgStruct(num_stars int64, struct_name string, symbol_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewStruct(struct_name, this.type_registry.SkeletonSize(struct_name))\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitStruct(type_system.STRUCT, struct_name, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tsymbol_ := new(symbol.Symbol)\n\tsymbol_.Init(symbol_name, type_variable, object)\n\n\tthis.frame_chain.LastFrame().ArgScope().AddSymbol(symbol_)\n}\n\nfunc (this *VirtualMachine) NewReturnVoid(num_stars int64) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NewReturnChar(num_stars int64) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewChar(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.CHAR, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NewReturnShort(num_stars int64) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewShort(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.SHORT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NewReturnInt(num_stars int64) {\n\tobject := this.arena.NewInt(0)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NewReturnLong(num_stars int64) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewLong(0)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.LONG, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NewReturnStruct(num_stars int64, struct_name string) {\n\tvar object *base.Object\n\tif num_stars > 0 {\n\t\tobject = this.arena.NewInt(0)\n\t} else {\n\t\tobject = this.arena.NewStruct(struct_name, this.type_registry.SkeletonSize(struct_name))\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitStruct(type_system.STRUCT, struct_name, int(num_stars))\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().ReturnStack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofVoid(num_stars int64) {\n\tvar value int64\n\tif num_stars == 0 {\n\t\terr := errors.New(\"num stars == 0\")\n\t\tpanic(err)\n\t} else {\n\t\tvalue = 4\n\t}\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofChar(num_stars int64) {\n\tvar value int64\n\tif num_stars == 0 {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 4\n\t}\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofShort(num_stars int64) {\n\tvar value int64\n\tif num_stars == 0 {\n\t\tvalue = 2\n\t} else {\n\t\tvalue = 4\n\t}\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofInt(num_stars int64) {\n\tvalue := int64(4)\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofLong(num_stars int64) {\n\tvar value int64\n\tif num_stars == 0 {\n\t\tvalue = 8\n\t} else {\n\t\tvalue = 4\n\t}\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) SizeofStruct(num_stars int64, struct_name string) {\n\tvar value int64\n\tif num_stars == 0 {\n\t\tvalue = this.type_registry.SkeletonSize(struct_name)\n\t} else {\n\t\tvalue = 4\n\t}\n\n\tobject := this.arena.NewInt(value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.INT, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetIdentifier(symbol_name string) {\n\tvar symbol_ *symbol.Symbol\n\tif this.frame_chain.LastFrame().FastScopeChain().HasSymbol(symbol_name) {\n\t\tsymbol_ = this.frame_chain.LastFrame().FastScopeChain().Symbol(symbol_name)\n\t} else if this.frame_chain.GlobalScope().HasSymbol(symbol_name) {\n\t\tsymbol_ = this.frame_chain.GlobalScope().Symbol(symbol_name)\n\t} else {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) is not found\", symbol_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\ttype_variable := symbol_.TypeVariable()\n\tobject := symbol_.Object()\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetArgIdentifier(symbol_name string) {\n\tvar symbol_ *symbol.Symbol\n\tif this.frame_chain.LastFrame().ArgScope().HasSymbol(symbol_name) {\n\t\tsymbol_ = this.frame_chain.LastFrame().ArgScope().Symbol(symbol_name)\n\t} else {\n\t\terr_msg := fmt.Sprintf(\"symbol (%s) is not found\", symbol_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\ttype_variable := symbol_.TypeVariable()\n\tobject := symbol_.Object()\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetSubscript() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(1)\n\tindex := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\tindex_value := this.arena.Pool().Memory().Read(index.Address(), index.Size()).SignedValue()\n\n\tvar offset int64\n\tvar size int64\n\ttype_variable := new(type_system.TypeVariable)\n\tif base_.TypeVariable().NumStars() == 0 {\n\t\terr := errors.New(\"base is not a pointer\")\n\t\tpanic(err)\n\t} else if base_.TypeVariable().NumStars() == 1 {\n\t\tif base_.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\terr := errors.New(\"type variable type is void\")\n\t\t\tpanic(err)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\toffset = index_value\n\n\t\t\tsize = 1\n\n\t\t\ttype_variable.InitPrimitive(type_system.CHAR, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\toffset = index_value * 2\n\n\t\t\tsize = 2\n\n\t\t\ttype_variable.InitPrimitive(type_system.SHORT, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\toffset = index_value * 4\n\n\t\t\tsize = 4\n\n\t\t\ttype_variable.InitPrimitive(type_system.INT, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\toffset = index_value * 8\n\n\t\t\tsize = 8\n\n\t\t\ttype_variable.InitPrimitive(type_system.LONG, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\tstruct_name := base_.TypeVariable().StructName()\n\n\t\t\toffset = index_value * this.type_registry.SkeletonSize(struct_name)\n\n\t\t\tsize = this.type_registry.SkeletonSize(struct_name)\n\n\t\t\ttype_variable.InitStruct(type_system.STRUCT, struct_name, base_.TypeVariable().NumStars()-1)\n\t\t} else {\n\t\t\terr := errors.New(\"type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else {\n\t\toffset = index_value * 4\n\t\tsize = 4\n\n\t\tif base_.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\ttype_variable.InitPrimitive(type_system.VOID, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\ttype_variable.InitPrimitive(type_system.CHAR, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\ttype_variable.InitPrimitive(type_system.SHORT, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\ttype_variable.InitPrimitive(type_system.INT, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\ttype_variable.InitPrimitive(type_system.LONG, base_.TypeVariable().NumStars()-1)\n\t\t} else if base_.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\tstruct_name := base_.TypeVariable().StructName()\n\n\t\t\ttype_variable.InitStruct(type_system.STRUCT, struct_name, base_.TypeVariable().NumStars()-1)\n\t\t} else {\n\t\t\terr := errors.New(\"type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, base_value+offset, size)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetAccess(field_name string) {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif base_.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"base is a pointer\")\n\t\tpanic(err)\n\t} else if base_.TypeVariable().TypeVariableType() != type_system.STRUCT {\n\t\terr := errors.New(\"base is not a struct\")\n\t\tpanic(err)\n\t}\n\n\tstruct_name := base_.TypeVariable().StructName()\n\n\toffset := this.type_registry.FieldOffset(struct_name, field_name)\n\n\tfield := this.type_registry.Skeleton(struct_name).Field(field_name)\n\n\ttype_variable := field.TypeVariable()\n\n\tvar size int64\n\tif field.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\terr := errors.New(\"void type has no star\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 1\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 2\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tsize = 4\n\t} else if field.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 8\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = this.type_registry.SkeletonSize(base_.TypeVariable().StructName())\n\t\t}\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, base_.Address()+offset, size)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetReference(field_name string) {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif base_.TypeVariable().NumStars() == 0 {\n\t\terr := errors.New(\"base is not a pointer\")\n\t\tpanic(err)\n\t} else if base_.TypeVariable().NumStars() > 1 {\n\t\terr := errors.New(\"base is a multi-dimensional pointer\")\n\t\tpanic(err)\n\t} else if base_.TypeVariable().TypeVariableType() != type_system.STRUCT {\n\t\terr := errors.New(\"base is not a struct\")\n\t\tpanic(err)\n\t}\n\n\tstruct_name := base_.TypeVariable().StructName()\n\n\toffset := this.type_registry.FieldOffset(struct_name, field_name)\n\n\tfield := this.type_registry.Skeleton(struct_name).Field(field_name)\n\n\ttype_variable := field.TypeVariable()\n\n\tvar size int64\n\tif field.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\terr := errors.New(\"void type has no star\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 1\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 2\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tsize = 4\n\t} else if field.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = 8\n\t\t}\n\t} else if field.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\tif field.TypeVariable().NumStars() > 0 {\n\t\t\tsize = 4\n\t\t} else {\n\t\t\tsize = this.type_registry.SkeletonSize(base_.TypeVariable().StructName())\n\t\t}\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\taddress := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, address+offset, size)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetAddress() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tobject := this.arena.NewInt(base_.Address())\n\n\ttype_variable := new(type_system.TypeVariable)\n\tif base_.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\ttype_variable.InitPrimitive(type_system.VOID, base_.TypeVariable().NumStars()+1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\ttype_variable.InitPrimitive(type_system.CHAR, base_.TypeVariable().NumStars()+2)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\ttype_variable.InitPrimitive(type_system.SHORT, base_.TypeVariable().NumStars()+1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.INT {\n\t\ttype_variable.InitPrimitive(type_system.INT, base_.TypeVariable().NumStars()+1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\ttype_variable.InitPrimitive(type_system.LONG, base_.TypeVariable().NumStars()+1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\ttype_variable.InitStruct(type_system.STRUCT, base_.TypeVariable().StructName(), base_.TypeVariable().NumStars()+1)\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GetValue() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\tif base_.TypeVariable().NumStars() < 1 {\n\t\terr := errors.New(\"base is not a pointer\")\n\t\tpanic(err)\n\t}\n\n\tobject := this.arena.Pool().Object(base_value)\n\n\ttype_variable := new(type_system.TypeVariable)\n\tif base_.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\ttype_variable.InitPrimitive(type_system.VOID, base_.TypeVariable().NumStars()-1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\ttype_variable.InitPrimitive(type_system.CHAR, base_.TypeVariable().NumStars()-2)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\ttype_variable.InitPrimitive(type_system.SHORT, base_.TypeVariable().NumStars()-1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.INT {\n\t\ttype_variable.InitPrimitive(type_system.INT, base_.TypeVariable().NumStars()-1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\ttype_variable.InitPrimitive(type_system.LONG, base_.TypeVariable().NumStars()-1)\n\t} else if base_.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\ttype_variable.InitStruct(type_system.STRUCT, base_.TypeVariable().StructName(), base_.TypeVariable().NumStars()-1)\n\t} else {\n\t\terr := errors.New(\"type variable type is not valid\")\n\t\tpanic(err)\n\t}\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Alloc() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\tobject := this.arena.NewPointer(base_value)\n\tpointer := this.arena.NewInt(object.Address())\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_system.VOID, 1)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, pointer.Address(), pointer.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Free() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\tthis.arena.Free(base_value)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) Assert() {\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\tif base_value == 0 {\n\t\terr := errors.New(\"assert\")\n\t\tpanic(err)\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) Add() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value + roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be added\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Sub() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value - roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be subtracted\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Mul() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value * roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Div() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value / roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be divided\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Mod() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value % roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the modular operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Lshift() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value << roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be left shifted\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Rshift() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value >> roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be right shifted\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Negate() {\n\toperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif operand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"operand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\toperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(operand.Address(), operand.Size()).\n\t\tSignedValue()\n\n\tvalue := -operand_value\n\n\tvar object *base.Object\n\tif operand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be negated\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(operand.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Tilde() {\n\toperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif operand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"operand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\toperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(operand.Address(), operand.Size()).\n\t\tSignedValue()\n\n\tvalue := ^operand_value\n\n\tvar object *base.Object\n\tif operand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be tilded\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(operand.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Sqrt() {\n\toperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif operand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"operand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\toperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(operand.Address(), operand.Size()).\n\t\tSignedValue()\n\n\tvalue := int64(math.Sqrt(float64(operand_value)))\n\n\tvar object *base.Object\n\tif operand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be tilded\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(operand.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) BitwiseAnd() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value & roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the bitwise and operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) BitwiseXor() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value ^ roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the bitwise xor operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) BitwiseOr() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvalue := loperand_value | roperand_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the bitwise or operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) LogicalAnd() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value != 0 && roperand_value != 0 {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the bitwise or operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) LogicalOr() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value != 0 || roperand_value != 0 {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the bitwise or operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) LogicalNot() {\n\toperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif operand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"operand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\toperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(operand.Address(), operand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif operand_value != 0 {\n\t\tvalue = 0\n\t} else {\n\t\tvalue = 1\n\t}\n\n\tvar object *base.Object\n\tif operand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if operand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot be tilded\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(operand.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Eq() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value == roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the eq operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) NotEq() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value != roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the not eq operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Less() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value < roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the less operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) LessEq() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value <= roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the less eq operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Greater() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value > roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the greater operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) GreaterEq() {\n\tloperand := this.frame_chain.LastFrame().Stack().Front(1)\n\troperand := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(loperand, roperand)\n\n\tloperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(loperand.Address(), loperand.Size()).\n\t\tSignedValue()\n\troperand_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(roperand.Address(), roperand.Size()).\n\t\tSignedValue()\n\n\tvar value int64\n\tif loperand_value >= roperand_value {\n\t\tvalue = 1\n\t} else {\n\t\tvalue = 0\n\t}\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"loperand and roperand cannot conduct the greater eq operation\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Push(stack_item)\n}\n\nfunc (this *VirtualMachine) Conditional() {\n\tcondition_stack_item := this.frame_chain.LastFrame().Stack().Front(2)\n\ttrue_stack_item := this.frame_chain.LastFrame().Stack().Front(1)\n\tfalse_stack_item := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\n\tcondition_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(condition_stack_item.Address(), condition_stack_item.Size()).\n\t\tSignedValue()\n\n\tif condition_value != 0 {\n\t\tthis.frame_chain.LastFrame().Stack().Push(true_stack_item)\n\t} else {\n\t\tthis.frame_chain.LastFrame().Stack().Push(false_stack_item)\n\t}\n}\n\nfunc (this *VirtualMachine) Assign() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\trvalue_byte_stream := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size())\n\n\tif lvalue.Size() > rvalue_byte_stream.Size() {\n\t\tfor lvalue.Size() != rvalue_byte_stream.Size() {\n\t\t\tif rvalue_byte_stream.Signbit() {\n\t\t\t\trvalue_byte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\trvalue_byte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < rvalue_byte_stream.Size() {\n\t\tfor lvalue.Size() != rvalue_byte_stream.Size() {\n\t\t\trvalue_byte_stream.Remove(int(rvalue_byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), rvalue_byte_stream)\n\n\tif this.arena.Pool().HasObject(lvalue.Address()) {\n\t\tlvalue_object := this.arena.Pool().Object(lvalue.Address())\n\n\t\tif !lvalue_object.HasTypeVariable() {\n\t\t\tlvalue_object.SetTypeVariable(rvalue.TypeVariable())\n\t\t}\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignStar() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value * rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignDiv() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value / rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignMod() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value % rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignAdd() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value + rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignSub() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value - rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignLshift() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value << rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignRshift() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value >> rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignBitwiseAnd() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value & rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignBitwiseXor() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value ^ rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignBitwiseOr() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(1)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t} else if rvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"rvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable_type := this.TypeCast(lvalue, rvalue)\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\trvalue_value := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value | rvalue_value\n\n\tvar object *base.Object\n\tif type_variable_type == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if type_variable_type == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if type_variable_type == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if type_variable_type == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(type_variable_type, 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignPlusPlus() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value + 1\n\n\tvar object *base.Object\n\tif lvalue.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(lvalue.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignMinusMinus() {\n\tlvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tif lvalue.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"lvalue's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\tlvalue_value := this.arena.Pool().Memory().Read(lvalue.Address(), lvalue.Size()).SignedValue()\n\n\tvalue := lvalue_value - 1\n\n\tvar object *base.Object\n\tif lvalue.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tobject = this.arena.NewChar(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tobject = this.arena.NewShort(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tobject = this.arena.NewInt(value)\n\t} else if lvalue.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tobject = this.arena.NewLong(value)\n\t} else {\n\t\terr := errors.New(\"lvalue and rvalue cannot be multiplied\")\n\t\tpanic(err)\n\t}\n\n\ttype_variable := new(type_system.TypeVariable)\n\ttype_variable.InitPrimitive(lvalue.TypeVariable().TypeVariableType(), 0)\n\n\tstack_item := new(stack.StackItem)\n\tstack_item.Init(type_variable, object.Address(), object.Size())\n\n\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\tif lvalue.Size() > byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tif byte_stream.Signbit() {\n\t\t\t\tbyte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\tbyte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < byte_stream.Size() {\n\t\tfor lvalue.Size() != byte_stream.Size() {\n\t\t\tbyte_stream.Remove(int(byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) AssignReturn() {\n\tlvalue := this.frame_chain.LastFrame().ReturnStack().Front(0)\n\trvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\trvalue_byte_stream := this.arena.Pool().Memory().Read(rvalue.Address(), rvalue.Size())\n\n\tif lvalue.Size() > rvalue_byte_stream.Size() {\n\t\tfor lvalue.Size() != rvalue_byte_stream.Size() {\n\t\t\tif rvalue_byte_stream.Signbit() {\n\t\t\t\trvalue_byte_stream.Append(255)\n\t\t\t} else {\n\t\t\t\trvalue_byte_stream.Append(0)\n\t\t\t}\n\t\t}\n\t} else if lvalue.Size() < rvalue_byte_stream.Size() {\n\t\tfor lvalue.Size() != rvalue_byte_stream.Size() {\n\t\t\trvalue_byte_stream.Remove(int(rvalue_byte_stream.Size() - 1))\n\t\t}\n\t}\n\n\tthis.arena.Pool().Memory().Write(lvalue.Address(), lvalue.Size(), rvalue_byte_stream)\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) Jump(label *abi.Label) {\n\tthis.frame_chain.LastFrame().Pc().Jump(label)\n}\n\nfunc (this *VirtualMachine) JumpIfZero(label *abi.Label) {\n\tvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tvalue_value := this.arena.Pool().Memory().Read(value.Address(), value.Size()).SignedValue()\n\n\tif value_value == 0 {\n\t\tthis.frame_chain.LastFrame().Pc().Jump(label)\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) JumpIfNonZero(label *abi.Label) {\n\tvalue := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tvalue_value := this.arena.Pool().Memory().Read(value.Address(), value.Size()).SignedValue()\n\n\tif value_value != 0 {\n\t\tthis.frame_chain.LastFrame().Pc().Jump(label)\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) Call(label *abi.Label) {\n\tthis.frame_chain.NewFrame(label)\n}\n\nfunc (this *VirtualMachine) Return() {\n\tthis.frame_chain.DeleteFrame()\n}\n\nfunc (this *VirtualMachine) Nop() {\n}\n\nfunc (this *VirtualMachine) DpuAlloc(dpu_id int64) {\n\tif int(dpu_id) > this.num_dpus {\n\t\terr := errors.New(\"DpuAlloc allocates more number of DPUs than available\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *VirtualMachine) DpuLoad() {\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init()\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tdpu_load_job := new(DpuLoadJob)\n\t\tdpu_load_job.Init(this.task, dpu_)\n\n\t\tthread_pool.Enque(dpu_load_job)\n\t}\n\n\tthread_pool.Start()\n}\n\nfunc (this *VirtualMachine) DpuPrepare() {\n\tdpu_id := this.frame_chain.LastFrame().Stack().Front(1)\n\tpointer := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tdpu_id_value := this.arena.Pool().Memory().Read(dpu_id.Address(), dpu_id.Size()).SignedValue()\n\tpointer_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(pointer.Address(), pointer.Size()).\n\t\tSignedValue()\n\n\tdpu_ := this.Dpus()[dpu_id_value]\n\n\tthis.prepare_xfer_buf[dpu_] = pointer_value\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) DpuTransfer() {\n\tdirection := this.frame_chain.LastFrame().Stack().Front(4)\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(3)\n\toffset := this.frame_chain.LastFrame().Stack().Front(2)\n\tsize := this.frame_chain.LastFrame().Stack().Front(1)\n\n\tdirection_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(direction.Address(), direction.Size()).\n\t\tSignedValue()\n\toffset_value := this.arena.Pool().Memory().Read(offset.Address(), offset.Size()).SignedValue()\n\tsize_value := this.arena.Pool().Memory().Read(size.Address(), size.Size()).SignedValue()\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tif pointer_value, pointer_found := this.prepare_xfer_buf[dpu_]; pointer_found {\n\t\t\tdelete(this.prepare_xfer_buf, dpu_)\n\n\t\t\tif direction_value == 0 {\n\t\t\t\tif base_.TypeVariable().TypeVariableType() == type_system.STRING {\n\t\t\t\t\tbase_string := this.DecodeString(\n\t\t\t\t\t\tthis.arena.Pool().Memory().Read(base_.Address(), base_.Size()),\n\t\t\t\t\t)\n\t\t\t\t\tbase_string = base_string[1 : len(base_string)-1]\n\n\t\t\t\t\twram_address, wram_address_found := this.task.Addresses()[base_string]\n\t\t\t\t\tif !wram_address_found {\n\t\t\t\t\t\terr_msg := fmt.Sprintf(\"WRAM address (%s) is not found\", base_string)\n\t\t\t\t\t\terr := errors.New(err_msg)\n\t\t\t\t\t\tpanic(err)\n\t\t\t\t\t}\n\n\t\t\t\t\tbyte_stream := this.PrepareByteStream(pointer_value, size_value)\n\t\t\t\t\tdpu_.Dma().\n\t\t\t\t\t\tTransferToWram(wram_address+offset_value, byte_stream.Size(), byte_stream)\n\t\t\t\t} else {\n\t\t\t\t\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\t\t\t\t\tbyte_stream := this.PrepareByteStream(pointer_value, size_value)\n\n\t\t\t\t\tdpu_.Dma().TransferToMram(base_value+offset_value, size_value, byte_stream)\n\t\t\t\t}\n\t\t\t} else if direction_value == 1 {\n\t\t\t\tif base_.TypeVariable().TypeVariableType() == type_system.STRING {\n\t\t\t\t\tbase_string := this.DecodeString(this.arena.Pool().Memory().Read(base_.Address(), base_.Size()))\n\t\t\t\t\tbase_string = base_string[1 : len(base_string)-1]\n\n\t\t\t\t\twram_address, wram_address_found := this.task.Addresses()[base_string]\n\t\t\t\t\tif !wram_address_found {\n\t\t\t\t\t\terr_msg := fmt.Sprintf(\"WRAM address (%s) is not found\", base_string)\n\t\t\t\t\t\terr := errors.New(err_msg)\n\t\t\t\t\t\tpanic(err)\n\t\t\t\t\t}\n\n\t\t\t\t\tbyte_stream := dpu_.Dma().TransferFromWram(wram_address+offset_value, size_value)\n\t\t\t\t\tthis.arena.Pool().Memory().Write(pointer_value, size_value, byte_stream)\n\t\t\t\t} else {\n\t\t\t\t\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\t\t\t\t\tbyte_stream := dpu_.Dma().TransferFromMram(base_value+offset_value, size_value)\n\t\t\t\t\tthis.arena.Pool().Memory().Write(pointer_value, size_value, byte_stream)\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\terr := errors.New(\"direction value is not 0 nor 1\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\t\t}\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) DpuCopyTo() {\n\tdpu_ := this.frame_chain.LastFrame().Stack().Front(4)\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(3)\n\toffset := this.frame_chain.LastFrame().Stack().Front(2)\n\tpointer := this.frame_chain.LastFrame().Stack().Front(1)\n\tsize := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tdpu_value := this.arena.Pool().Memory().Read(dpu_.Address(), dpu_.Size()).SignedValue()\n\toffset_value := this.arena.Pool().Memory().Read(offset.Address(), offset.Size()).SignedValue()\n\tpointer_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(pointer.Address(), pointer.Size()).\n\t\tSignedValue()\n\tsize_value := this.arena.Pool().Memory().Read(size.Address(), size.Size()).SignedValue()\n\n\tif base_.TypeVariable().TypeVariableType() == type_system.STRING {\n\t\tbase_string := this.DecodeString(\n\t\t\tthis.arena.Pool().Memory().Read(base_.Address(), base_.Size()),\n\t\t)\n\t\tbase_string = base_string[1 : len(base_string)-1]\n\n\t\twram_address, wram_address_found := this.task.Addresses()[base_string]\n\t\tif !wram_address_found {\n\t\t\terr_msg := fmt.Sprintf(\"WRAM address (%s) is not found\", base_string)\n\t\t\terr := errors.New(err_msg)\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbyte_stream := this.PrepareByteStream(pointer_value, size_value)\n\t\tthis.Dpus()[dpu_value].Dma().\n\t\t\tTransferToWram(wram_address+offset_value, byte_stream.Size(), byte_stream)\n\t} else {\n\t\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\t\tchannel_id := int(dpu_value) / (this.num_ranks_per_channel * this.num_dpus_per_rank)\n\t\trank_id := (int(dpu_value) % (this.num_ranks_per_channel * this.num_dpus_per_rank)) / this.num_dpus_per_rank\n\t\tdpu_id := int(dpu_value) % this.num_dpus_per_rank\n\n\t\tsimulated_dpu := this.channels[channel_id].Ranks()[rank_id].Dpus()[dpu_id]\n\n\t\tbyte_stream := this.PrepareByteStream(pointer_value, size_value)\n\n\t\tsimulated_dpu.Dma().TransferToMram(base_value+offset_value, size_value, byte_stream)\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) DpuCopyFrom() {\n\tdpu_ := this.frame_chain.LastFrame().Stack().Front(4)\n\tbase_ := this.frame_chain.LastFrame().Stack().Front(3)\n\toffset := this.frame_chain.LastFrame().Stack().Front(2)\n\tpointer := this.frame_chain.LastFrame().Stack().Front(1)\n\tsize := this.frame_chain.LastFrame().Stack().Front(0)\n\n\tdpu_value := this.arena.Pool().Memory().Read(dpu_.Address(), dpu_.Size()).SignedValue()\n\toffset_value := this.arena.Pool().Memory().Read(offset.Address(), offset.Size()).SignedValue()\n\tpointer_value := this.arena.Pool().\n\t\tMemory().\n\t\tRead(pointer.Address(), pointer.Size()).\n\t\tSignedValue()\n\tsize_value := this.arena.Pool().Memory().Read(size.Address(), size.Size()).SignedValue()\n\n\tif base_.TypeVariable().TypeVariableType() == type_system.STRING {\n\t\tbase_string := this.DecodeString(\n\t\t\tthis.arena.Pool().Memory().Read(base_.Address(), base_.Size()),\n\t\t)\n\t\tbase_string = base_string[1 : len(base_string)-1]\n\n\t\twram_address, wram_address_found := this.task.Addresses()[base_string]\n\t\tif !wram_address_found {\n\t\t\terr_msg := fmt.Sprintf(\"WRAM address (%s) is not found\", base_string)\n\t\t\terr := errors.New(err_msg)\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbyte_stream := this.Dpus()[dpu_value].Dma().\n\t\t\tTransferFromWram(wram_address+offset_value, size_value)\n\t\tthis.arena.Pool().Memory().Write(pointer_value, size_value, byte_stream)\n\t} else {\n\t\tbase_value := this.arena.Pool().Memory().Read(base_.Address(), base_.Size()).SignedValue()\n\n\t\tchannel_id := int(dpu_value) / (this.num_ranks_per_channel * this.num_dpus_per_rank)\n\t\trank_id := (int(dpu_value) % (this.num_ranks_per_channel * this.num_dpus_per_rank)) / this.num_dpus_per_rank\n\t\tdpu_id := int(dpu_value) % this.num_dpus_per_rank\n\n\t\tsimulated_dpu := this.channels[channel_id].Ranks()[rank_id].Dpus()[dpu_id]\n\n\t\tbyte_stream := simulated_dpu.Dma().TransferFromMram(base_value+offset_value, size_value)\n\t\tthis.arena.Pool().Memory().Write(pointer_value, size_value, byte_stream)\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) DpuLaunch() {\n\tconfig_loader := new(misc.ConfigLoader)\n\tconfig_loader.Init()\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tthreads := dpu_.Threads()\n\n\t\tfor _, thread := range threads {\n\t\t\tbootstrap := config_loader.IramOffset()\n\t\t\tthread.RegFile().WritePcReg(bootstrap)\n\t\t}\n\n\t\tdpu_.Boot()\n\t}\n\n\tthread_pool := new(core.ThreadPool)\n\tthread_pool.Init()\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tdpu_cycle_job := new(DpuComputeCycleJob)\n\t\tdpu_cycle_job.Init(this.task.SysEnd(), dpu_)\n\n\t\tthread_pool.Enque(dpu_cycle_job)\n\t}\n\n\tthread_pool.Start()\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tdpu_.Unboot()\n\t}\n\n\tthis.frame_chain.LastFrame().Stack().Pop()\n\tthis.frame_chain.LastFrame().Stack().Pop()\n}\n\nfunc (this *VirtualMachine) DpuFree() {\n}\n\nfunc (this *VirtualMachine) Banks() []*bank.Bank {\n\treturn this.memory_controller.Banks()\n}\n\nfunc (this *VirtualMachine) Dpus() []*dpu.Dpu {\n\tdpus := make([]*dpu.Dpu, 0)\n\tfor _, channel_ := range this.channels {\n\t\tdpus = append(dpus, channel_.Dpus()...)\n\t}\n\treturn dpus\n}\n\nfunc (this *VirtualMachine) TypeCast(\n\tloperand *stack.StackItem,\n\troperand *stack.StackItem,\n) type_system.TypeVariableType {\n\tif loperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"loperand's num stars != 0\")\n\t\tpanic(err)\n\t} else if roperand.TypeVariable().NumStars() != 0 {\n\t\terr := errors.New(\"roperand's num stars != 0\")\n\t\tpanic(err)\n\t}\n\n\tif loperand.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\terr := errors.New(\"loperand's type variable type == void\")\n\t\tpanic(err)\n\t} else if loperand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\tif roperand.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\terr := errors.New(\"roperand's type variable type == void\")\n\t\t\tpanic(err)\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\treturn type_system.CHAR\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\treturn type_system.SHORT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\treturn type_system.INT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\terr := errors.New(\"roperand's type variable type == struct\")\n\t\t\tpanic(err)\n\t\t} else {\n\t\t\terr := errors.New(\"roperand's type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if loperand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\tif roperand.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\terr := errors.New(\"roperand's type variable type == void\")\n\t\t\tpanic(err)\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\treturn type_system.SHORT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\treturn type_system.SHORT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\treturn type_system.INT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\terr := errors.New(\"roperand's type variable type == struct\")\n\t\t\tpanic(err)\n\t\t} else {\n\t\t\terr := errors.New(\"roperand's type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if loperand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\tif roperand.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\terr := errors.New(\"roperand's type variable type == void\")\n\t\t\tpanic(err)\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\treturn type_system.INT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\treturn type_system.INT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\treturn type_system.INT\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\terr := errors.New(\"roperand's type variable type == struct\")\n\t\t\tpanic(err)\n\t\t} else {\n\t\t\terr := errors.New(\"roperand's type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if loperand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\tif roperand.TypeVariable().TypeVariableType() == type_system.VOID {\n\t\t\terr := errors.New(\"roperand's type variable type == void\")\n\t\t\tpanic(err)\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.CHAR {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.SHORT {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.INT {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.LONG {\n\t\t\treturn type_system.LONG\n\t\t} else if roperand.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\t\terr := errors.New(\"roperand's type variable type == struct\")\n\t\t\tpanic(err)\n\t\t} else {\n\t\t\terr := errors.New(\"roperand's type variable type is not valid\")\n\t\t\tpanic(err)\n\t\t}\n\t} else if loperand.TypeVariable().TypeVariableType() == type_system.STRUCT {\n\t\terr := errors.New(\"loperand's type variable type == struct\")\n\t\tpanic(err)\n\t} else {\n\t\terr := errors.New(\"loperand's type variable type is not valid\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *VirtualMachine) DecodeString(byte_stream *encoding.ByteStream) string {\n\tascii_encoder := new(encoding.AsciiEncoder)\n\tascii_encoder.Init()\n\n\treturn ascii_encoder.Decode(byte_stream)\n}\n\nfunc (this *VirtualMachine) Checkpoint() {\n\tthis.memory_controller.Flush()\n\n\tfor _, object := range this.arena.Pool().Objects() {\n\t\tvm_address := object.Address()\n\t\tsize := object.Size()\n\n\t\tbyte_stream := this.arena.Pool().Memory().Read(object.Address(), object.Size())\n\n\t\tthis.memory_controller.VmWrite(vm_address, size, byte_stream)\n\t}\n}\n\nfunc (this *VirtualMachine) PrepareByteStream(\n\tpointer int64,\n\tsize int64,\n) *encoding.ByteStream {\n\tobject := this.arena.Pool().Memory().Read(pointer, size)\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor i := int64(0); i < size; i++ {\n\t\tbyte_stream.Append(object.Get(int(i)))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *VirtualMachine) SimulateMemory() {\n\tfor len(this.push_xfer) > 0 {\n\t\tthread_pool := new(core.ThreadPool)\n\t\tthread_pool.Init()\n\n\t\tfor _, bank_ := range this.Banks() {\n\t\t\tbank_cycle_job := new(BankCycleJob)\n\t\t\tbank_cycle_job.Init(bank_)\n\n\t\t\tthread_pool.Enque(bank_cycle_job)\n\t\t}\n\n\t\tfor _, dpu_ := range this.Dpus() {\n\t\t\tdpu_cycle_job := new(DpuCycleJob)\n\t\t\tdpu_cycle_job.Init(dpu_)\n\n\t\t\tthread_pool.Enque(dpu_cycle_job)\n\t\t}\n\n\t\tthread_pool.Start()\n\n\t\tfor _, vm_channel_ := range this.memory_controller.VmChannels() {\n\t\t\tvm_channel_.Cycle()\n\t\t}\n\n\t\tfor _, channel_ := range this.channels {\n\t\t\tchannel_.Cycle()\n\t\t}\n\n\t\tthis.memory_controller.Cycle()\n\n\t\tif this.memory_controller.CanPop() {\n\t\t\ttransfer_command := this.memory_controller.Pop()\n\n\t\t\tif !transfer_command.IsVmReady() {\n\t\t\t\terr := errors.New(\"transfer command is not VM ready\")\n\t\t\t\tpanic(err)\n\t\t\t} else if !transfer_command.IsReady() {\n\t\t\t\terr := errors.New(\"transfer command is not ready\")\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tdelete(this.push_xfer, transfer_command)\n\n\t\t\tif transfer_command.TransferCommandType() == bank.DEVICE_TO_HOST {\n\t\t\t\tthis.arena.Pool().Memory().Write(\n\t\t\t\t\ttransfer_command.VmAddress(),\n\t\t\t\t\ttransfer_command.Size(),\n\t\t\t\t\ttransfer_command.ByteStream(),\n\t\t\t\t)\n\t\t\t}\n\t\t}\n\t}\n}\n\nfunc (this *VirtualMachine) Dump() {\n\tfile_dumper := new(misc.FileDumper)\n\tfile_dumper.Init(filepath.Join(this.bin_dirpath, \"log.txt\"))\n\n\tlines := make([]string, 0)\n\n\tfor _, dpu_ := range this.Dpus() {\n\t\tlines = append(lines, dpu_.StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.ThreadScheduler().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.Logic().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.Logic().CycleRule().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().MemoryScheduler().StatFactory().ToLines()...)\n\t\tlines = append(lines, dpu_.MemoryController().RowBuffer().StatFactory().ToLines()...)\n\t}\n\n\tlines = append(lines, this.memory_controller.MemoryScheduler().StatFactory().ToLines()...)\n\n\tfor _, vm_channel := range this.memory_controller.VmChannels() {\n\t\tfor _, rank_ := range vm_channel.Ranks() {\n\t\t\tfor _, bank_ := range rank_.Banks() {\n\t\t\t\tlines = append(lines, bank_.StatFactory().ToLines()...)\n\t\t\t\tlines = append(lines, bank_.RowBuffer().StatFactory().ToLines()...)\n\t\t\t}\n\t\t}\n\t}\n\n\tfile_dumper.WriteLines(lines)\n}\n\nfunc (this *VirtualMachine) Stringify() string {\n\tss := \"\\n=============== STACK ===============\\n\"\n\n\tfor i := 0; i < this.frame_chain.LastFrame().Stack().Length(); i++ {\n\t\tstack_item := this.frame_chain.LastFrame().Stack().Front(i)\n\n\t\tbyte_stream := this.arena.Pool().Memory().Read(stack_item.Address(), stack_item.Size())\n\n\t\tif byte_stream.Size() <= 8 {\n\t\t\tss += fmt.Sprintf(\"%d: %d\\n\", i, byte_stream.SignedValue())\n\t\t} else {\n\t\t\tss += fmt.Sprintf(\"%d: XXX\\n\", i)\n\t\t}\n\t}\n\n\tss += \"=====================================\\n\"\n\n\treturn ss\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/main.go",
    "content": "package main\n\nimport (\n\t\"fmt\"\n\t\"os\"\n\t\"path/filepath\"\n\t\"uPIMulator/src/device/compiler\"\n\t\"uPIMulator/src/device/linker\"\n\t\"uPIMulator/src/host/interpreter\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/program\"\n\t\"uPIMulator/src/system\"\n)\n\nfunc main() {\n\tcommand_line_parser := InitCommandLineParser()\n\tcommand_line_parser.Parse(os.Args)\n\n\tif command_line_parser.IsArgSet(\"help\") {\n\t\tfmt.Printf(\"%s\", command_line_parser.StringifyHelpMsgs())\n\t} else {\n\t\tcommand_line_validator := new(misc.CommandLineValidator)\n\t\tcommand_line_validator.Init(command_line_parser)\n\t\tcommand_line_validator.Validate()\n\n\t\tconfig_loader := new(misc.ConfigLoader)\n\t\tconfig_loader.Init()\n\n\t\tconfig_validator := new(misc.ConfigValidator)\n\t\tconfig_validator.Init(config_loader)\n\t\tconfig_validator.Validate()\n\n\t\tbin_dirpath := command_line_parser.StringParameter(\"bin_dirpath\")\n\n\t\tif _, err := os.Stat(bin_dirpath); !os.IsNotExist(err) {\n\t\t\tremove_err := os.RemoveAll(bin_dirpath)\n\t\t\tif remove_err != nil {\n\t\t\t\tpanic(remove_err)\n\t\t\t}\n\n\t\t\tmkdir_err := os.MkdirAll(bin_dirpath, os.ModePerm)\n\t\t\tif mkdir_err != nil {\n\t\t\t\tpanic(mkdir_err)\n\t\t\t}\n\t\t}\n\n\t\targs_filepath := filepath.Join(bin_dirpath, \"args.txt\")\n\t\toptions_filepath := filepath.Join(bin_dirpath, \"options.txt\")\n\n\t\targs_file_dumper := new(misc.FileDumper)\n\t\targs_file_dumper.Init(args_filepath)\n\t\targs_file_dumper.WriteLines([]string{command_line_parser.StringifyArgs()})\n\n\t\toptions_file_dumper := new(misc.FileDumper)\n\t\toptions_file_dumper.Init(options_filepath)\n\t\toptions_file_dumper.WriteLines([]string{command_line_parser.StringifyOptions()})\n\n\t\tcompiler_ := new(compiler.Compiler)\n\t\tcompiler_.Init(command_line_parser)\n\t\tcompiler_.Compile()\n\n\t\tlinker_ := new(linker.Linker)\n\t\tlinker_.Init(command_line_parser)\n\t\tlinker_.Link()\n\n\t\ttask := new(program.Task)\n\t\ttask.Init(command_line_parser)\n\n\t\tinterpreter_ := new(interpreter.Interpreter)\n\t\tinterpreter_.Init(command_line_parser, task.SysUsedMramEnd())\n\t\tinterpreter_.Interpret()\n\n\t\tapp := new(program.App)\n\t\tapp.Init(command_line_parser)\n\n\t\tsystem_ := new(system.System)\n\t\tsystem_.Init(command_line_parser)\n\t\tsystem_.Simulate(app, task)\n\t\tsystem_.Dump()\n\t\tsystem_.Fini()\n\t}\n}\n\nfunc InitCommandLineParser() *misc.CommandLineParser {\n\tcommand_line_parser := new(misc.CommandLineParser)\n\tcommand_line_parser.Init()\n\n\t// NOTE(dongjae.lee@kaist.ac.kr): Explanation of verbose levels\n\t// level 0: Only prints simulation output\n\t// level 1: level 0 + prints UPMEM instruction executed per each logic cycle\n\t// level 2: level 1 + prints host VM's stack and UPMEM register file values per each logic cycle\n\tcommand_line_parser.AddOption(misc.INT, \"verbose\", \"1\", \"verbosity of the simulation\")\n\n\tcommand_line_parser.AddOption(misc.STRING, \"benchmark\", \"GEMV\", \"benchmark name\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_channels\", \"1\", \"number of PIM memory channels\")\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"num_ranks_per_channel\",\n\t\t\"1\",\n\t\t\"number of ranks per channel\",\n\t)\n\tcommand_line_parser.AddOption(misc.INT, \"num_dpus_per_rank\", \"4\", \"number of DPUs per rank\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_vm_channels\", \"1\", \"number of VM memory channels\")\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"num_vm_ranks_per_channel\",\n\t\t\"2\",\n\t\t\"number of VM ranks per channel\",\n\t)\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"num_vm_banks_per_rank\",\n\t\t\"16\",\n\t\t\"number of VM banks per rank\",\n\t)\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_tasklets\", \"16\", \"number of tasklets\")\n\tcommand_line_parser.AddOption(misc.STRING, \"data_prep_params\", \"65536\",\n\t\t\"data preparation parameter\")\n\n\tcommand_line_parser.AddOption(\n\t\tmisc.STRING,\n\t\t\"root_dirpath\",\n\t\t\"/home/via/uPIMulator/golang_vm/uPIMulator\",\n\t\t\"path to the root directory\",\n\t)\n\n\tcommand_line_parser.AddOption(misc.STRING, \"bin_dirpath\",\n\t\t\"/home/via/uPIMulator/golang_vm/uPIMulator/bin\", \"path to the bin directory\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"logic_frequency\", \"350\", \"DPU logic frequency in MHz\")\n\tcommand_line_parser.AddOption(misc.INT, \"memory_frequency\", \"2400\",\n\t\t\"DPU MRAM frequency in MHz\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"num_pipeline_stages\", \"14\",\n\t\t\"number of DPU logic pipeline stages\")\n\tcommand_line_parser.AddOption(misc.INT, \"num_revolver_scheduling_cycles\", \"11\",\n\t\t\"number of DPU logic revolver scheduling cycles\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"wordline_size\", \"1024\",\n\t\t\"row buffer size per single DPU's MRAM in bytes\")\n\tcommand_line_parser.AddOption(misc.INT, \"min_access_granularity\", \"8\",\n\t\t\"DPU MRAM's minimum access granularity in bytes\")\n\n\tcommand_line_parser.AddOption(misc.INT, \"reorder_window_size\", \"256\", \"FR-FCFS reorder window size\")\n\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"t_rcd\",\n\t\t\"32\",\n\t\t\"DPU MRAM t_rcd timing parameter [cycle]\",\n\t)\n\tcommand_line_parser.AddOption(\n\t\tmisc.INT,\n\t\t\"t_ras\",\n\t\t\"78\",\n\t\t\"DPU MRAM t_ras timing parameter [cycle]\",\n\t)\n\tcommand_line_parser.AddOption(misc.INT, \"t_rp\", \"32\", \"DPU MRAM t_rp timing parameter [cycle]\")\n\tcommand_line_parser.AddOption(misc.INT, \"t_cl\", \"32\", \"DPU MRAM t_cl timing parameter [cycle]\")\n\tcommand_line_parser.AddOption(misc.INT, \"t_bl\", \"8\", \"DPU MRAM t_bl timing parameter [cycle]\")\n\n\treturn command_line_parser\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/command_line_option.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"strconv\"\n)\n\ntype CommandLineOptionType int\n\nconst (\n\tBOOL = iota\n\tINT\n\tSTRING\n)\n\ntype CommandLineOption struct {\n\tcommand_line_option_type CommandLineOptionType\n\toption                   string\n\tdefault_parameter        string\n\tcustom_parameter         string\n\thelp_msg                 string\n}\n\nfunc (this *CommandLineOption) Init(\n\tcommand_line_option_type CommandLineOptionType,\n\toption string,\n\tdefault_parameter string,\n\thelp_msg string,\n) {\n\tthis.command_line_option_type = command_line_option_type\n\tthis.option = option\n\tthis.default_parameter = default_parameter\n\tthis.custom_parameter = \"\"\n\tthis.help_msg = help_msg\n}\n\nfunc (this *CommandLineOption) CommandLineOptionType() CommandLineOptionType {\n\treturn this.command_line_option_type\n}\n\nfunc (this *CommandLineOption) Option() string {\n\treturn this.option\n}\n\nfunc (this *CommandLineOption) Parameter() string {\n\tif this.custom_parameter == \"\" {\n\t\treturn this.default_parameter\n\t} else {\n\t\treturn this.custom_parameter\n\t}\n}\n\nfunc (this *CommandLineOption) HelpMsg() string {\n\treturn this.help_msg\n}\n\nfunc (this *CommandLineOption) SetCustomParameter(custom_parameter string) {\n\tif this.custom_parameter != \"\" {\n\t\terr_msg := fmt.Sprintf(\"custom parameter (%s) is already set\", custom_parameter)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tthis.custom_parameter = custom_parameter\n}\n\nfunc (this *CommandLineOption) BoolParameter() bool {\n\tif this.Parameter() == \"true\" {\n\t\treturn true\n\t} else if this.Parameter() == \"false\" {\n\t\treturn false\n\t} else {\n\t\terr_msg := fmt.Sprintf(\"parameter (%s) is not true or false\", this.Parameter())\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *CommandLineOption) IntParameter() int64 {\n\tint_parameter, err := strconv.ParseInt(this.Parameter(), 10, 64)\n\n\tif err != nil {\n\t\tpanic(err)\n\t}\n\n\treturn int_parameter\n}\n\nfunc (this *CommandLineOption) StringParameter() string {\n\treturn this.Parameter()\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/command_line_parser.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"slices\"\n\t\"strconv\"\n\t\"strings\"\n)\n\ntype CommandLineParser struct {\n\tcommand_line_options map[string]*CommandLineOption\n\targs                 map[string]bool\n}\n\nfunc (this *CommandLineParser) Init() {\n\tthis.command_line_options = make(map[string]*CommandLineOption)\n\tthis.args = make(map[string]bool)\n}\n\nfunc (this *CommandLineParser) AddOption(\n\tcommand_line_option_type CommandLineOptionType,\n\toption string,\n\tdefault_parameter string,\n\thelp_msg string,\n) {\n\tif _, found := this.command_line_options[option]; found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is already added to the parser\")\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := new(CommandLineOption)\n\tcommand_line_option.Init(command_line_option_type, option, default_parameter, help_msg)\n\tthis.command_line_options[option] = command_line_option\n}\n\nfunc (this *CommandLineParser) Parse(os_args []string) {\n\tfor i := 1; i < len(os_args); i++ {\n\t\tos_arg := os_args[i]\n\n\t\tif os_arg[0:2] == \"--\" {\n\t\t\toption := os_arg[2:]\n\t\t\tcustom_parameter := os_args[i+1]\n\n\t\t\tthis.command_line_options[option].SetCustomParameter(custom_parameter)\n\n\t\t\ti++\n\t\t} else if os_arg[0:1] == \"-\" {\n\t\t\targ := os_arg[1:]\n\n\t\t\tif _, found := this.args[arg]; found {\n\t\t\t\terr_msg := fmt.Sprintf(\"arg (%s) is already set\", arg)\n\t\t\t\terr := errors.New(err_msg)\n\t\t\t\tpanic(err)\n\t\t\t}\n\n\t\t\tthis.args[arg] = true\n\t\t} else {\n\t\t\terr := errors.New(\"command line options are corrupted\")\n\t\t\tpanic(err)\n\t\t}\n\t}\n}\n\nfunc (this *CommandLineParser) BoolParameter(option string) bool {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.BoolParameter()\n}\n\nfunc (this *CommandLineParser) IntParameter(option string) int64 {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.IntParameter()\n}\n\nfunc (this *CommandLineParser) StringParameter(option string) string {\n\tif _, found := this.command_line_options[option]; !found {\n\t\terr_msg := fmt.Sprintf(\"option (%s) is not found\", option)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tcommand_line_option := this.command_line_options[option]\n\treturn command_line_option.StringParameter()\n}\n\nfunc (this *CommandLineParser) DataPrepParams() []int {\n\tstring_params := strings.Split(this.StringParameter(\"data_prep_params\"), \",\")\n\n\tdata_prep_params := make([]int, 0)\n\tfor _, string_param := range string_params {\n\t\tint_param, err := strconv.Atoi(string_param)\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tdata_prep_params = append(data_prep_params, int_param)\n\t}\n\treturn data_prep_params\n}\n\nfunc (this *CommandLineParser) IsArgSet(arg string) bool {\n\tif _, found := this.args[arg]; found {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n\nfunc (this *CommandLineParser) Options() []string {\n\toptions := make([]string, 0)\n\tfor option := range this.command_line_options {\n\t\toptions = append(options, option)\n\t}\n\n\tslices.Sort(options)\n\treturn options\n}\n\nfunc (this *CommandLineParser) Args() []string {\n\targs := make([]string, 0)\n\tfor arg := range this.args {\n\t\targs = append(args, arg)\n\t}\n\n\tslices.Sort(args)\n\treturn args\n}\n\nfunc (this *CommandLineParser) StringifyOptions() string {\n\tstr := \"OPTIONS\\n\"\n\n\tfor option, command_line_option := range this.command_line_options {\n\t\tstr += option + \"  -->  \" + command_line_option.Parameter() + \"\\n\"\n\t}\n\n\treturn str\n}\n\nfunc (this *CommandLineParser) StringifyArgs() string {\n\tstr := \"ARGS\\n\"\n\n\tfor arg := range this.args {\n\t\tstr += arg + \"\\n\"\n\t}\n\n\treturn str\n}\n\nfunc (this *CommandLineParser) StringifyHelpMsgs() string {\n\tstr := \"HELP_MSGS\\n\"\n\n\tfor option, command_line_option := range this.command_line_options {\n\t\tstr += option + \"  -->  \" + command_line_option.HelpMsg() + \"\\n\"\n\t}\n\n\treturn str\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/command_line_validator.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"os\"\n)\n\ntype CommandLineValidator struct {\n\tcommand_line_parser *CommandLineParser\n}\n\nfunc (this *CommandLineValidator) Init(command_line_parser *CommandLineParser) {\n\tthis.command_line_parser = command_line_parser\n}\n\nfunc (this *CommandLineValidator) Validate() {\n\tif this.command_line_parser.IntParameter(\"num_channels\") <= 0 {\n\t\terr := errors.New(\"num_channels <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_ranks_per_channel\") <= 0 {\n\t\terr := errors.New(\"num_ranks <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_dpus_per_rank\") <= 0 {\n\t\terr := errors.New(\"num_dpus <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_vm_channels\") <= 0 {\n\t\terr := errors.New(\"num_vm_channels <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_vm_ranks_per_channel\") <= 0 {\n\t\terr := errors.New(\"num_vm_ranks_per_channel <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_vm_banks_per_rank\") <= 0 {\n\t\terr := errors.New(\"num_vm_banks_per_rank <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_tasklets\") <= 0 {\n\t\terr := errors.New(\"num_tasklets <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif _, stat_err := os.Stat(this.command_line_parser.StringParameter(\"root_dirpath\")); os.IsNotExist(\n\t\tstat_err,\n\t) {\n\t\terr_msg := fmt.Sprintf(\n\t\t\t\"root_dirpath (%s) does not exist\",\n\t\t\tthis.command_line_parser.StringParameter(\"root_dirpath\"),\n\t\t)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"logic_frequency\") <= 0 {\n\t\terr := errors.New(\"logic_frequency <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"memory_frequency\") <= 0 {\n\t\terr := errors.New(\"memory_frequency <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_pipeline_stages\") <= 0 {\n\t\terr := errors.New(\"num_pipeline_stages <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"num_revolver_scheduling_cycles\") < 0 {\n\t\terr := errors.New(\"num_revolver_scheduling_cycles < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"wordline_size\") <= 0 {\n\t\terr := errors.New(\"wordline_size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"min_access_granularity\") <= 0 {\n\t\terr := errors.New(\"min_access_granularity <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_rcd\") < 0 {\n\t\terr := errors.New(\"t_rcd < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_ras\") < 0 {\n\t\terr := errors.New(\"t_ras < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_rp\") < 0 {\n\t\terr := errors.New(\"t_rp < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_cl\") < 0 {\n\t\terr := errors.New(\"t_cl < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.command_line_parser.IntParameter(\"t_bl\") < 0 {\n\t\terr := errors.New(\"t_bl < 0\")\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/config_loader.go",
    "content": "package misc\n\ntype ConfigLoader struct {\n}\n\nfunc (this *ConfigLoader) Init() {\n}\n\nfunc (this *ConfigLoader) AddressWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) AtomicDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) AtomicOffset() int64 {\n\treturn 0\n}\n\nfunc (this *ConfigLoader) AtomicSize() int64 {\n\treturn 256\n}\n\nfunc (this *ConfigLoader) IramDataWidth() int {\n\treturn 96\n}\n\nfunc (this *ConfigLoader) IramOffset() int64 {\n\treturn 384 * 1024\n}\n\nfunc (this *ConfigLoader) IramSize() int64 {\n\treturn 48 * 1024\n}\n\nfunc (this *ConfigLoader) WramDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) WramOffset() int64 {\n\treturn 512\n}\n\nfunc (this *ConfigLoader) WramSize() int64 {\n\treturn 128 * 1024\n}\n\nfunc (this *ConfigLoader) MramDataWidth() int {\n\treturn 32\n}\n\nfunc (this *ConfigLoader) MramOffset() int64 {\n\treturn 512 * 1024\n}\n\nfunc (this *ConfigLoader) MramSize() int64 {\n\treturn 64 * 1024 * 1024\n}\n\nfunc (this *ConfigLoader) StackSize() int64 {\n\treturn 2 * 1024\n}\n\nfunc (this *ConfigLoader) HeapSize() int64 {\n\treturn 4 * 1024\n}\n\nfunc (this *ConfigLoader) NumGpRegisters() int {\n\treturn 24\n}\n\nfunc (this *ConfigLoader) MaxNumTasklets() int {\n\treturn 24\n}\n\nfunc (this *ConfigLoader) VmBankOffset() int64 {\n\treturn 512\n}\n\nfunc (this *ConfigLoader) VmBankSize() int64 {\n\treturn 128 * 1024 * 1024\n}\n\nfunc (this *ConfigLoader) VmBg0() int {\n\treturn 6\n}\n\nfunc (this *ConfigLoader) VmBg1() int {\n\treturn 17\n}\n\nfunc (this *ConfigLoader) VmBank() int {\n\treturn 18\n}\n\nfunc (this *ConfigLoader) VmMemorySize() int64 { return 1024 }\n\nfunc (this *ConfigLoader) GarbageCollectionThreshold() int64 {\n\treturn 100\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/config_validator.go",
    "content": "package misc\n\nimport (\n\t\"errors\"\n)\n\ntype ConfigValidator struct {\n\tconfig_loader *ConfigLoader\n}\n\nfunc (this *ConfigValidator) Init(config_loader *ConfigLoader) {\n\tthis.config_loader = config_loader\n}\n\nfunc (this *ConfigValidator) Validate() {\n\tif this.config_loader.AddressWidth() <= 0 {\n\t\terr := errors.New(\"address width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicDataWidth() <= 0 {\n\t\terr := errors.New(\"atomic data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramDataWidth() <= 0 {\n\t\terr := errors.New(\"IRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramDataWidth() <= 0 {\n\t\terr := errors.New(\"WRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramDataWidth() <= 0 {\n\t\terr := errors.New(\"MRAM data width <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicOffset() < 0 {\n\t\terr := errors.New(\"atomic offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramOffset() < 0 {\n\t\terr := errors.New(\"IRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramOffset() < 0 {\n\t\terr := errors.New(\"WRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramOffset() < 0 {\n\t\terr := errors.New(\"MRAM offset < 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.AtomicSize() <= 0 {\n\t\terr := errors.New(\"atomic size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.IramSize() <= 0 {\n\t\terr := errors.New(\"IRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.WramSize() <= 0 {\n\t\terr := errors.New(\"WRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MramSize() <= 0 {\n\t\terr := errors.New(\"MRAM size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and IRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and WRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.AtomicOffset(),\n\t\tthis.config_loader.AtomicSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"atomic and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t) {\n\t\terr := errors.New(\"IRAM and WRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.IramOffset(),\n\t\tthis.config_loader.IramSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"IRAM and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.AreOverlapped(\n\t\tthis.config_loader.WramOffset(),\n\t\tthis.config_loader.WramSize(),\n\t\tthis.config_loader.MramOffset(),\n\t\tthis.config_loader.MramSize(),\n\t) {\n\t\terr := errors.New(\"WRAM and MRAM are overlapped\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.StackSize() <= 0 {\n\t\terr := errors.New(\"stack size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.HeapSize() <= 0 {\n\t\terr := errors.New(\"heap size <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.NumGpRegisters() <= 0 {\n\t\terr := errors.New(\"num gp registers <= 0\")\n\t\tpanic(err)\n\t}\n\n\tif this.config_loader.MaxNumTasklets() <= 0 {\n\t\terr := errors.New(\"max num tasklets <= 0\")\n\t\tpanic(err)\n\t}\n}\n\nfunc (this *ConfigValidator) AreOverlapped(\n\toffset1 int64,\n\tsize1 int64,\n\toffset2 int64,\n\tsize2 int64,\n) bool {\n\tif offset1 <= offset2 && offset2 <= offset1+size1 {\n\t\treturn true\n\t} else if offset1 <= offset2+size2 && offset2+size2 <= offset1+size1 {\n\t\treturn true\n\t} else if offset2 <= offset1 && offset1 <= offset2+size2 {\n\t\treturn true\n\t} else if offset2 <= offset1+size1 && offset1+size1 <= offset2+size2 {\n\t\treturn true\n\t} else {\n\t\treturn false\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/file_dumper.go",
    "content": "package misc\n\nimport (\n\t\"bufio\"\n\t\"os\"\n)\n\ntype FileDumper struct {\n\tpath string\n}\n\nfunc (this *FileDumper) Init(path string) {\n\tthis.path = path\n}\n\nfunc (this *FileDumper) WriteLines(lines []string) {\n\tfile, create_err := os.Create(this.path)\n\n\tif create_err != nil {\n\t\tpanic(create_err)\n\t}\n\n\twriter := bufio.NewWriter(file)\n\n\tfor _, line := range lines {\n\t\t_, write_err := writer.WriteString(line + \"\\n\")\n\n\t\tif write_err != nil {\n\t\t\tpanic(write_err)\n\t\t}\n\t}\n\n\tflush_err := writer.Flush()\n\tif flush_err != nil {\n\t\tpanic(flush_err)\n\t}\n\n\tclose_err := file.Close()\n\tif close_err != nil {\n\t\tpanic(close_err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/file_scanner.go",
    "content": "package misc\n\nimport (\n\t\"bufio\"\n\t\"os\"\n)\n\ntype FileScanner struct {\n\tpath string\n}\n\nfunc (this *FileScanner) Init(path string) {\n\tthis.path = path\n}\n\nfunc (this *FileScanner) ReadLines() []string {\n\tfile, open_err := os.Open(this.path)\n\n\tif open_err != nil {\n\t\tpanic(open_err)\n\t}\n\n\tscanner := bufio.NewScanner(file)\n\n\tlines := make([]string, 0)\n\tfor scanner.Scan() {\n\t\tlines = append(lines, scanner.Text())\n\t}\n\n\tif scan_err := scanner.Err(); scan_err != nil {\n\t\tpanic(scan_err)\n\t}\n\n\tif close_err := file.Close(); close_err != nil {\n\t\tpanic(close_err)\n\t}\n\n\treturn lines\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/misc/stat_factory.go",
    "content": "package misc\n\nimport (\n\t\"fmt\"\n\t\"slices\"\n)\n\ntype StatFactory struct {\n\tname  string\n\tstats map[string]int64\n}\n\nfunc (this *StatFactory) Init(name string) {\n\tthis.name = name\n\tthis.stats = make(map[string]int64)\n}\n\nfunc (this *StatFactory) Name() string {\n\treturn this.name\n}\n\nfunc (this *StatFactory) Stats() []string {\n\tstats := make([]string, 0)\n\tfor stat, _ := range this.stats {\n\t\tstats = append(stats, stat)\n\t}\n\n\tslices.Sort(stats)\n\treturn stats\n}\n\nfunc (this *StatFactory) Value(stat string) int64 {\n\treturn this.stats[stat]\n}\n\nfunc (this *StatFactory) Increment(stat string, value int64) {\n\tthis.stats[stat] += value\n}\n\nfunc (this *StatFactory) ToLines() []string {\n\tlines := make([]string, 0)\n\tfor stat, value := range this.stats {\n\t\tline := fmt.Sprintf(\"%s_%s: %d\", this.name, stat, value)\n\t\tlines = append(lines, line)\n\t}\n\treturn lines\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/program/app.go",
    "content": "package program\n\nimport (\n\t\"errors\"\n\t\"fmt\"\n\t\"path/filepath\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/host/abi\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype App struct {\n\tbin_dirpath string\n\n\tbenchmark    string\n\tnum_dpus     int\n\tnum_tasklets int\n\n\tlabels []*abi.Label\n}\n\nfunc (this *App) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_tasklets = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\n\tthis.labels = make([]*abi.Label, 0)\n\tthis.LoadLabels()\n}\n\nfunc (this *App) HasLabel(label_name string) bool {\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn true\n\t\t}\n\t}\n\treturn false\n}\n\nfunc (this *App) Label(label_name string) *abi.Label {\n\tif !this.HasLabel(label_name) {\n\t\terr_msg := fmt.Sprintf(\"label (%s) is not found\", label_name)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n\n\tfor _, label := range this.labels {\n\t\tif label.Name() == label_name {\n\t\t\treturn label\n\t\t}\n\t}\n\n\treturn nil\n}\n\nfunc (this *App) LoadLabels() {\n\tpath := filepath.Join(this.bin_dirpath, \"bytecode.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tfor _, line := range file_scanner.ReadLines() {\n\t\tif strings.Contains(line, \":\") {\n\t\t\tlabel_name := line[:len(line)-1]\n\n\t\t\tlabel := new(abi.Label)\n\t\t\tlabel.Init(label_name)\n\n\t\t\tthis.labels = append(this.labels, label)\n\t\t} else {\n\t\t\twords := strings.Split(line, \" \")\n\n\t\t\tvar op_code abi.OpCode\n\t\t\targs := make([]int64, 0)\n\t\t\tstrs := make([]string, 0)\n\t\t\tfor i, word := range words {\n\t\t\t\tif i == 0 {\n\t\t\t\t\top_code = this.ConvertToOpCode(word[1:])\n\t\t\t\t} else {\n\t\t\t\t\tif arg, err := strconv.ParseInt(word, 10, 64); err == nil {\n\t\t\t\t\t\targs = append(args, arg)\n\t\t\t\t\t} else {\n\t\t\t\t\t\tstrs = append(strs, word)\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbytecode := new(abi.Bytecode)\n\t\t\tbytecode.Init(op_code, args, strs)\n\n\t\t\tthis.labels[len(this.labels)-1].Append(bytecode)\n\t\t}\n\t}\n}\n\nfunc (this *App) ConvertToOpCode(op_code string) abi.OpCode {\n\tif op_code == \"NEW_SCOPE\" {\n\t\treturn abi.NEW_SCOPE\n\t} else if op_code == \"DELETE_SCOPE\" {\n\t\treturn abi.DELETE_SCOPE\n\t} else if op_code == \"PUSH_CHAR\" {\n\t\treturn abi.PUSH_CHAR\n\t} else if op_code == \"PUSH_SHORT\" {\n\t\treturn abi.PUSH_SHORT\n\t} else if op_code == \"PUSH_INT\" {\n\t\treturn abi.PUSH_INT\n\t} else if op_code == \"PUSH_LONG\" {\n\t\treturn abi.PUSH_LONG\n\t} else if op_code == \"PUSH_STRING\" {\n\t\treturn abi.PUSH_STRING\n\t} else if op_code == \"POP\" {\n\t\treturn abi.POP\n\t} else if op_code == \"BEGIN_STRUCT\" {\n\t\treturn abi.BEGIN_STRUCT\n\t} else if op_code == \"APPEND_VOID\" {\n\t\treturn abi.APPEND_VOID\n\t} else if op_code == \"APPEND_CHAR\" {\n\t\treturn abi.APPEND_CHAR\n\t} else if op_code == \"APPEND_SHORT\" {\n\t\treturn abi.APPEND_SHORT\n\t} else if op_code == \"APPEND_INT\" {\n\t\treturn abi.APPEND_INT\n\t} else if op_code == \"APPEND_LONG\" {\n\t\treturn abi.APPEND_LONG\n\t} else if op_code == \"APPEND_STRUCT\" {\n\t\treturn abi.APPEND_STRUCT\n\t} else if op_code == \"END_STRUCT\" {\n\t\treturn abi.END_STRUCT\n\t} else if op_code == \"NEW_GLOBAL_VOID\" {\n\t\treturn abi.NEW_GLOBAL_VOID\n\t} else if op_code == \"NEW_GLOBAL_CHAR\" {\n\t\treturn abi.NEW_GLOBAL_CHAR\n\t} else if op_code == \"NEW_GLOBAL_SHORT\" {\n\t\treturn abi.NEW_GLOBAL_SHORT\n\t} else if op_code == \"NEW_GLOBAL_INT\" {\n\t\treturn abi.NEW_GLOBAL_INT\n\t} else if op_code == \"NEW_GLOBAL_LONG\" {\n\t\treturn abi.NEW_GLOBAL_LONG\n\t} else if op_code == \"NEW_FAST_VOID\" {\n\t\treturn abi.NEW_FAST_VOID\n\t} else if op_code == \"NEW_FAST_CHAR\" {\n\t\treturn abi.NEW_FAST_CHAR\n\t} else if op_code == \"NEW_FAST_SHORT\" {\n\t\treturn abi.NEW_FAST_SHORT\n\t} else if op_code == \"NEW_FAST_INT\" {\n\t\treturn abi.NEW_FAST_INT\n\t} else if op_code == \"NEW_FAST_LONG\" {\n\t\treturn abi.NEW_FAST_LONG\n\t} else if op_code == \"NEW_FAST_STRUCT\" {\n\t\treturn abi.NEW_FAST_STRUCT\n\t} else if op_code == \"NEW_ARG_VOID\" {\n\t\treturn abi.NEW_ARG_VOID\n\t} else if op_code == \"NEW_ARG_CHAR\" {\n\t\treturn abi.NEW_ARG_CHAR\n\t} else if op_code == \"NEW_ARG_SHORT\" {\n\t\treturn abi.NEW_ARG_SHORT\n\t} else if op_code == \"NEW_ARG_INT\" {\n\t\treturn abi.NEW_ARG_INT\n\t} else if op_code == \"NEW_ARG_LONG\" {\n\t\treturn abi.NEW_ARG_LONG\n\t} else if op_code == \"NEW_ARG_STRUCT\" {\n\t\treturn abi.NEW_ARG_STRUCT\n\t} else if op_code == \"NEW_RETURN_VOID\" {\n\t\treturn abi.NEW_RETURN_VOID\n\t} else if op_code == \"NEW_RETURN_CHAR\" {\n\t\treturn abi.NEW_RETURN_CHAR\n\t} else if op_code == \"NEW_RETURN_SHORT\" {\n\t\treturn abi.NEW_RETURN_SHORT\n\t} else if op_code == \"NEW_RETURN_INT\" {\n\t\treturn abi.NEW_RETURN_INT\n\t} else if op_code == \"NEW_RETURN_LONG\" {\n\t\treturn abi.NEW_RETURN_LONG\n\t} else if op_code == \"NEW_RETURN_STRUCT\" {\n\t\treturn abi.NEW_RETURN_STRUCT\n\t} else if op_code == \"SIZEOF_VOID\" {\n\t\treturn abi.SIZEOF_VOID\n\t} else if op_code == \"SIZEOF_CHAR\" {\n\t\treturn abi.SIZEOF_CHAR\n\t} else if op_code == \"SIZEOF_SHORT\" {\n\t\treturn abi.SIZEOF_SHORT\n\t} else if op_code == \"SIZEOF_INT\" {\n\t\treturn abi.SIZEOF_INT\n\t} else if op_code == \"SIZEOF_LONG\" {\n\t\treturn abi.SIZEOF_LONG\n\t} else if op_code == \"SIZEOF_STRUCT\" {\n\t\treturn abi.SIZEOF_STRUCT\n\t} else if op_code == \"GET_IDENTIFIER\" {\n\t\treturn abi.GET_IDENTIFIER\n\t} else if op_code == \"GET_ARG_IDENTIFIER\" {\n\t\treturn abi.GET_ARG_IDENTIFIER\n\t} else if op_code == \"GET_SUBSCRIPT\" {\n\t\treturn abi.GET_SUBSCRIPT\n\t} else if op_code == \"GET_ACCESS\" {\n\t\treturn abi.GET_ACCESS\n\t} else if op_code == \"GET_REFERENCE\" {\n\t\treturn abi.GET_REFERENCE\n\t} else if op_code == \"GET_ADDRESS\" {\n\t\treturn abi.GET_ADDRESS\n\t} else if op_code == \"GET_VALUE\" {\n\t\treturn abi.GET_VALUE\n\t} else if op_code == \"ALLOC\" {\n\t\treturn abi.ALLOC\n\t} else if op_code == \"FREE\" {\n\t\treturn abi.FREE\n\t} else if op_code == \"ASSERT\" {\n\t\treturn abi.ASSERT\n\t} else if op_code == \"ADD\" {\n\t\treturn abi.ADD\n\t} else if op_code == \"SUB\" {\n\t\treturn abi.SUB\n\t} else if op_code == \"MUL\" {\n\t\treturn abi.MUL\n\t} else if op_code == \"DIV\" {\n\t\treturn abi.DIV\n\t} else if op_code == \"MOD\" {\n\t\treturn abi.MOD\n\t} else if op_code == \"LSHIFT\" {\n\t\treturn abi.LSHIFT\n\t} else if op_code == \"RSHIFT\" {\n\t\treturn abi.RSHIFT\n\t} else if op_code == \"NEGATE\" {\n\t\treturn abi.NEGATE\n\t} else if op_code == \"TILDE\" {\n\t\treturn abi.TILDE\n\t} else if op_code == \"SQRT\" {\n\t\treturn abi.SQRT\n\t} else if op_code == \"BITWISE_AND\" {\n\t\treturn abi.BITWISE_AND\n\t} else if op_code == \"BITWISE_XOR\" {\n\t\treturn abi.BITWISE_XOR\n\t} else if op_code == \"BITWISE_OR\" {\n\t\treturn abi.BITWISE_OR\n\t} else if op_code == \"LOGICAL_AND\" {\n\t\treturn abi.LOGICAL_AND\n\t} else if op_code == \"LOGICAL_OR\" {\n\t\treturn abi.LOGICAL_OR\n\t} else if op_code == \"LOGICAL_NOT\" {\n\t\treturn abi.LOGICAL_NOT\n\t} else if op_code == \"EQ\" {\n\t\treturn abi.EQ\n\t} else if op_code == \"NOT_EQ\" {\n\t\treturn abi.NOT_EQ\n\t} else if op_code == \"LESS\" {\n\t\treturn abi.LESS\n\t} else if op_code == \"LESS_EQ\" {\n\t\treturn abi.LESS_EQ\n\t} else if op_code == \"GREATER\" {\n\t\treturn abi.GREATER\n\t} else if op_code == \"GREATER_EQ\" {\n\t\treturn abi.GREATER_EQ\n\t} else if op_code == \"CONDITIONAL\" {\n\t\treturn abi.CONDITIONAL\n\t} else if op_code == \"ASSIGN\" {\n\t\treturn abi.ASSIGN\n\t} else if op_code == \"ASSIGN_STAR\" {\n\t\treturn abi.ASSIGN_STAR\n\t} else if op_code == \"ASSIGN_DIV\" {\n\t\treturn abi.ASSIGN_DIV\n\t} else if op_code == \"ASSIGN_MOD\" {\n\t\treturn abi.ASSIGN_MOD\n\t} else if op_code == \"ASSIGN_ADD\" {\n\t\treturn abi.ASSIGN_ADD\n\t} else if op_code == \"ASSIGN_SUB\" {\n\t\treturn abi.ASSIGN_SUB\n\t} else if op_code == \"ASSIGN_LSHIFT\" {\n\t\treturn abi.ASSIGN_LSHIFT\n\t} else if op_code == \"ASSIGN_RSHIFT\" {\n\t\treturn abi.ASSIGN_RSHIFT\n\t} else if op_code == \"ASSIGN_BITWISE_AND\" {\n\t\treturn abi.ASSIGN_BITWISE_AND\n\t} else if op_code == \"ASSIGN_BITWISE_XOR\" {\n\t\treturn abi.ASSIGN_BITWISE_XOR\n\t} else if op_code == \"ASSIGN_BITWISE_OR\" {\n\t\treturn abi.ASSIGN_BITWISE_OR\n\t} else if op_code == \"ASSIGN_PLUS_PLUS\" {\n\t\treturn abi.ASSIGN_PLUS_PLUS\n\t} else if op_code == \"ASSIGN_MINUS_MINUS\" {\n\t\treturn abi.ASSIGN_MINUS_MINUS\n\t} else if op_code == \"ASSIGN_RETURN\" {\n\t\treturn abi.ASSIGN_RETURN\n\t} else if op_code == \"JUMP\" {\n\t\treturn abi.JUMP\n\t} else if op_code == \"JUMP_IF_ZERO\" {\n\t\treturn abi.JUMP_IF_ZERO\n\t} else if op_code == \"JUMP_IF_NONZERO\" {\n\t\treturn abi.JUMP_IF_NONZERO\n\t} else if op_code == \"CALL\" {\n\t\treturn abi.CALL\n\t} else if op_code == \"RETURN\" {\n\t\treturn abi.RETURN\n\t} else if op_code == \"NOP\" {\n\t\treturn abi.NOP\n\t} else if op_code == \"DPU_ALLOC\" {\n\t\treturn abi.DPU_ALLOC\n\t} else if op_code == \"DPU_LOAD\" {\n\t\treturn abi.DPU_LOAD\n\t} else if op_code == \"DPU_PREPARE\" {\n\t\treturn abi.DPU_PREPARE\n\t} else if op_code == \"DPU_TRANSFER\" {\n\t\treturn abi.DPU_TRANSFER\n\t} else if op_code == \"DPU_COPY_TO\" {\n\t\treturn abi.DPU_COPY_TO\n\t} else if op_code == \"DPU_COPY_FROM\" {\n\t\treturn abi.DPU_COPY_FROM\n\t} else if op_code == \"DPU_LAUNCH\" {\n\t\treturn abi.DPU_LAUNCH\n\t} else if op_code == \"DPU_FREE\" {\n\t\treturn abi.DPU_FREE\n\t} else {\n\t\terr_msg := fmt.Sprintf(\"op code (%s) is not valid\", op_code)\n\t\terr := errors.New(err_msg)\n\t\tpanic(err)\n\t}\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/program/task.go",
    "content": "package program\n\nimport (\n\t\"errors\"\n\t\"path/filepath\"\n\t\"strconv\"\n\t\"strings\"\n\t\"uPIMulator/src/encoding\"\n\t\"uPIMulator/src/misc\"\n)\n\ntype Task struct {\n\tbin_dirpath string\n\n\tbenchmark    string\n\tnum_dpus     int\n\tnum_tasklets int\n\n\taddresses map[string]int64\n\tvalues    map[string]int64\n\n\tatomic *encoding.ByteStream\n\tiram   *encoding.ByteStream\n\twram   *encoding.ByteStream\n\tmram   *encoding.ByteStream\n}\n\nfunc (this *Task) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.bin_dirpath = command_line_parser.StringParameter(\"bin_dirpath\")\n\n\tthis.benchmark = command_line_parser.StringParameter(\"benchmark\")\n\n\tnum_channels := int(command_line_parser.IntParameter(\"num_channels\"))\n\tnum_ranks_per_channel := int(command_line_parser.IntParameter(\"num_ranks_per_channel\"))\n\tnum_dpus_per_rank := int(command_line_parser.IntParameter(\"num_dpus_per_rank\"))\n\tthis.num_tasklets = num_channels * num_ranks_per_channel * num_dpus_per_rank\n\n\tthis.InitAddresses()\n\tthis.InitValues()\n\tthis.InitAtomic()\n\tthis.InitIram()\n\tthis.InitWram()\n\tthis.InitMram()\n}\n\nfunc (this *Task) InitAddresses() {\n\tpath := filepath.Join(this.bin_dirpath, \"addresses.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tlines := file_scanner.ReadLines()\n\n\tthis.addresses = make(map[string]int64)\n\n\tfor _, line := range lines {\n\t\twords := strings.Split(line, \":\")\n\n\t\tname := words[0]\n\t\taddress, err := strconv.ParseInt(words[1][1:], 10, 64)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.addresses[name] = address\n\t}\n}\n\nfunc (this *Task) InitValues() {\n\tpath := filepath.Join(this.bin_dirpath, \"values.txt\")\n\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\n\tlines := file_scanner.ReadLines()\n\n\tthis.values = make(map[string]int64)\n\n\tfor _, line := range lines {\n\t\twords := strings.Split(line, \":\")\n\n\t\tname := words[0]\n\t\taddress, err := strconv.ParseInt(words[1][1:], 10, 64)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tthis.values[name] = address\n\t}\n}\n\nfunc (this *Task) InitAtomic() {\n\tpath := filepath.Join(this.bin_dirpath, \"atomic.bin\")\n\n\tthis.atomic = this.InitByteStream(path)\n}\n\nfunc (this *Task) InitIram() {\n\tpath := filepath.Join(this.bin_dirpath, \"iram.bin\")\n\n\tthis.iram = this.InitByteStream(path)\n}\n\nfunc (this *Task) InitWram() {\n\tpath := filepath.Join(this.bin_dirpath, \"wram.bin\")\n\n\tthis.wram = this.InitByteStream(path)\n}\n\nfunc (this *Task) InitMram() {\n\tpath := filepath.Join(this.bin_dirpath, \"mram.bin\")\n\n\tthis.mram = this.InitByteStream(path)\n}\n\nfunc (this *Task) InitByteStream(path string) *encoding.ByteStream {\n\tfile_scanner := new(misc.FileScanner)\n\tfile_scanner.Init(path)\n\tlines := file_scanner.ReadLines()\n\n\tbyte_stream := new(encoding.ByteStream)\n\tbyte_stream.Init()\n\n\tfor _, line := range lines {\n\t\tvalue, err := strconv.Atoi(line)\n\n\t\tif err != nil {\n\t\t\tpanic(err)\n\t\t}\n\n\t\tbyte_stream.Append(uint8(value))\n\t}\n\n\treturn byte_stream\n}\n\nfunc (this *Task) Atomic() *encoding.ByteStream {\n\treturn this.atomic\n}\n\nfunc (this *Task) Iram() *encoding.ByteStream {\n\treturn this.iram\n}\n\nfunc (this *Task) Wram() *encoding.ByteStream {\n\treturn this.wram\n}\n\nfunc (this *Task) Mram() *encoding.ByteStream {\n\treturn this.mram\n}\n\nfunc (this *Task) Addresses() map[string]int64 {\n\treturn this.addresses\n}\n\nfunc (this *Task) Values() map[string]int64 {\n\treturn this.values\n}\n\nfunc (this *Task) SysUsedMramEnd() int64 {\n\tif _, found := this.values[\"__sys_used_mram_end\"]; !found {\n\t\terr := errors.New(\"__sys_used_mram_end is not found\")\n\t\tpanic(err)\n\t}\n\n\treturn this.values[\"__sys_used_mram_end\"]\n}\n\nfunc (this *Task) SysEnd() int64 {\n\tif _, found := this.addresses[\"__sys_end\"]; !found {\n\t\terr := errors.New(\"__sys_end is not found\")\n\t\tpanic(err)\n\t}\n\n\treturn this.addresses[\"__sys_end\"]\n}\n"
  },
  {
    "path": "golang_vm/uPIMulator/src/system/system.go",
    "content": "package system\n\nimport (\n\t\"uPIMulator/src/host/vm\"\n\t\"uPIMulator/src/misc\"\n\t\"uPIMulator/src/program\"\n)\n\ntype System struct {\n\tvm *vm.VirtualMachine\n}\n\nfunc (this *System) Init(command_line_parser *misc.CommandLineParser) {\n\tthis.vm = new(vm.VirtualMachine)\n\tthis.vm.Init(command_line_parser)\n}\n\nfunc (this *System) Fini() {\n\tthis.vm.Fini()\n}\n\nfunc (this *System) Simulate(app *program.App, task *program.Task) {\n\tthis.vm.Load(app, task)\n\n\tfor this.vm.CanAdvance() {\n\t\tthis.vm.Advance()\n\t}\n}\n\nfunc (this *System) Dump() {\n\tthis.vm.Dump()\n}\n"
  },
  {
    "path": "python_cpp/README.md",
    "content": "# ⚙️ Usage\n## Currently Supported Mode\nuPIMulator operates in an execution-driven simulation mode, enabling cycle-accurate performance analysis of PIM-based applications.\n\n## Workflow\nThe typical usage workflow comprises two primary stages:\n\n1. **Binary Generation:** Compile, assemble, and link your application code to generate the required binary files for simulation.\n2. **Cycle-Level Simulation:** Utilize the generated binary files as input to the cycle-level simulator to obtain detailed performance metrics and insights.\n\nWe aim to expand uPIMulator's capabilities and may introduce additional usage modes in future releases.\n\n## Installation & Build\n### Prerequisites\n- **Python:** Python 3.10 or higher\n- **C++ Compiler:** C++20 compliant compiler\n- **CMake:** CMake 3.16 or higher\n- **Docker:** Docker Engine\n- **User Permissions:** Your Ubuntu user account must be a member of the `docker` group.\n- **Operating System:** Ubuntu 18.04 or later (recommended)\n- **Environment Management (Optional):** We recommend using a tool like [Anaconda](https://www.anaconda.com/) for managing your Python environment.\n\n### Installation Steps\n1. **Install Linker Dependencies:** Navigate to the `uPIMulator_frontend` directory and install the required Python packages using `pip`:\n\n   ```bash\n   cd /path/to/uPIMulator/python_cpp/uPIMulator_frontend\n   pip install -r requirements.txt\n   ```\n\n2. **Build the Cycle-level Simulator:** Navigate to the `uPIMulator_backend/script` directory and execute the build script:\n\n   ```bash\n   cd /path/to/uPIMulator/python_cpp/uPIMulator_backend/script\n   sh build.sh\n   ```\n\n> **Note:** Replace `/path/to/uPIMulator` with the actual path to your uPIMulator repository. \n\nIf you encounter any issues during the installation or build process, please refer to the troubleshooting section in the documentation or open an issue on our GitHub repository.\n\n## Binary Files Generation\nWe will use the VA (vector addition) benchmark as an example to demonstrate the binary file generation phase.\nAfter compiling, assembling, and linking, you will find the generated binary files within the `uPIMulator_frontend/bin` directory.\n\n> **Pre-Generated Binaries:** To expedite the setup process, you can utilize our pre-generated binary files available at the following [link](https://drive.google.com/file/d/1kfL-xGn1F18Ezmw81IvAhxEaLiZZOLFR/view?usp=sharing).\n\n### Compilation\n\n```bash\ncd /path/to/uPIMulator/python_cpp/uPIMulator_frontend/src\npython main.py --mode compile --num_tasklets 16 --benchmark VA --num_dpus 1\n```\n\n### Assembly and Linking\n\n```bash\ncd /path/to/uPIMulator/python_cpp/uPIMulator_frontend/src\npython main.py --mode link --num_tasklets 16 --benchmark VA --data_prep_param 1024 --num_dpus 1\n```\n\n> **Troubleshooting:** In the event that the linking command encounters errors, please execute the following Docker build command and then reattempt the compilation and linking steps:\n\n```bash\ndocker build -t bongjoonhyun/compiler -f /path/to/uPIMulator/python_cpp/uPIMulator_frontend/docker/compiler.dockerfile .\n```\n\n> **Supported Benchmarks and Performance Note:** uPIMulator currently supports 13 PrIM benchmarks.\n> Please be aware that the initial compile/assemble/link process may take approximately 30 minutes.\n\n## Cycle-level Simulation\n### Executing a Simulation\nInitiate a cycle-level simulation by providing the following inputs to the `uPIMulator` executable:\n\n- Benchmark name\n- Number of tasklets\n- Absolute path to the directory containing the generated binary files (`bindir`)\n\nYou can further customize the simulation behavior using various command-line options. \n\n### Simulation Output\nThe simulation results will be printed directly to the standard output (`stdout`).\n\n### Example Command\n\n```bash\ncd /path/to/uPIMulator/uPIMulator_backend/build/\n./src/uPIMulator --benchmark VA --num_tasklets 16 --bindir /path/to/uPIMulator/uPIMulator_frontend/bin/1_dpus/ --logdir .\n```\n\n> **Important Note:** Ensure that you provide the absolute path to the `bindir` when executing the simulation.\n\nFeel free to explore different benchmark configurations and utilize the command-line options to tailor the simulation to your specific requirements.\n\n# 📄 Reproducing Figures from the Paper\nThis section provides instructions for replicating the figures presented in our paper.\nWe offer detailed replication manuals for figures used in **Section 4 (Demystifying UPMEM-PIM with uPIMulator)**.\nPlease note that Figure 8 is omitted for brevity.\n\n## Configuration of PrIM Benchmarks\n- **Single DPU Focus:** For Figures 5, 6, 7, and 9, the `num_dpus` parameter must always be set to `1`, as these experiments specifically characterize the behavior of a single DPU.\n- **Data Preparation Parameter:**  When generating the binary files for the PrIM benchmarks, please configure the `data_prep_param` parameter according to the following table:\n\n| Benchmark | `data_prep_param` (Figures 5, 6, 7, 9) | `data_prep_param` (Figure 10) |\n|---|---|---|\n| BS       | 32768 | 131072 |\n| GEMV     | 2048  | 4096   |\n| HST-L    | 131072 | 524288 |\n| HST-S    | 131072 | 524288 |\n| MLP      | 256   | 1024   |\n| RED      | 524288 | 2097152|\n| SCAN-RSS | 262144 | 1048576|\n| SCAN-SSA | 262144 | 1048576|\n| SEL      | 524288 | 2097152|\n| TRNS     | 1024  | 128    |\n| TS       | 2048  | 65536  |\n| UNI      | 524288 | 2097152|\n| VA       | 524288 | 2097152|\n\n## Example Command\n\n```bash\npython main.py --mode link --num_tasklets 16 --benchmark VA --data_prep_param 524288 --num_dpus 1\n``` \n\nPlease ensure you adhere to these configurations to accurately replicate the figures presented in the paper. \n\n## Figure 5: PrIM Compute and Memory Utilization\n<img src=\"../assets/uPIMulator_figure5.png\" width=\"400\"/>\n\nThis figure illustrates the compute utilization (red points) and memory read bandwidth utilization (blue points) of the PrIM benchmarks when executed with 1, 4, and 16 threads (tasklets).\n\n### Calculation Formulas\n\n- **Compute Utilization (IPC):**  `num_instructions` / (`logic_cycle` - `communication_cycle`)\n- **Memory Read Bandwidth Utilization (GB/s):** Please refer to the provided Excel sheet for the calculation at the following [link](../assets/figure5_mem_util_calculator.xlsx)\n\n> **Note:** The required values for these calculations can be obtained from the simulation results generated by uPIMulator. \n\n## Figure 6: DPU Runtime Breakdown\n<img src=\"../assets/uPIMulator_fiture6.png\" width=\"400\"/>\n\nThis figure presents a breakdown of DPU runtime, categorizing cycles into active (black) and various idle states (red, yellow, blue).\nThe following formulas can be used to calculate the proportions of each category:\n\n### Calculation Formulas\n\n- **Issuable Ratio:**  `breakdown_run` / (`logic_cycle` - `communication_cycle`)\n- **Idle (Memory) Ratio:** `breakdown_dma` / (`logic_cycle` - `communication_cycle`)\n- **Idle (Revolver) Ratio:** (`breakdown_etc` - `communication_cycle`) / (`logic_cycle` - `communication_cycle`)\n- **Idle (RF) Ratio:** `backpressuer` / (`logic_cycle` - `communication_cycle`)\n\n> **Note:** The values for the variables in these formulas (e.g., `breakdown_run`, `logic_cycle`) can be extracted from the simulation results generated by uPIMulator. \n\n## Figure 7: Issuable Tasklets\n<img src=\"../assets/uPIMulator_figure7.png\" width=\"400\"/>\n\nFigure 7 visualizes the number of tasklets (threads) that are ready for execution (issuable) by the DPU scheduler at each cycle.\n\n### Replication\nTo reproduce this figure, utilize the provided [Excel sheet](../assets/figure7_active_tasklet_breakdown.xlsx).\nThe spreadsheet includes instructions on how to populate it with the relevant simulation output data, and it will automatically generate the corresponding figure.\n\n> **Important Configuration Note:** Please ensure that the number of threads is configured to **16 tasklets** when running the simulations for this figure.\n> You can achieve this by using the following command-line argument: `--num_tasklets 16`.\n\n## Figure 9: Instruction Mix (Single DPU)\n<img src=\"../assets/uPIMulator_figure9.png\" width=\"400\"/>\n\nFigure 9 provides a breakdown of the instruction mix observed during single-DPU execution.\nTo generate this figure, follow the steps outlined below using the `upmem_profiler` tool and the accompanying Excel sheet.\n\n### Procedure\n\n1. **Build the Profiler**\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_profiler/script\n   bash build.sh\n   ```\n\n2. **Extract Instructions**\n   Run the simulation with the `--verbose 1` flag to capture detailed instruction traces.\n\n   ```bash\n   cd /path/to/uPIMulator/python_cpp/uPIMulator_backend/\n   ./build/src/uPIMulator --benchmark VA --num_tasklets 16 --bindir /path/to/uPIMulator/python_cpp/uPIMulator_frontend/bin/1_dpus/ --logdir . --verbose 1 > trace.txt\n   ```\n\n3. **Run the Profiler**\n   Process the generated trace file using the `upmem_profiler` in `instruction_mix` mode.\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_profiler/\n   ./build/src/upmem_profiler --logpath /path/to/uPIMulator/python_cpp/uPIMulator_backend/trace.txt --mode instruction_mix\n   ```\n\n4. **Generate the Figure**\n   Utilize the profiler's output to populate the provided [Excel sheet](../assets/figure9_instruction_mix.xlsx), which will automatically generate the instruction mix figure.\n\n> **Important Configuration Note:** Similar to Figure 7, the instruction mix analysis in Figure 9 is based on simulations with **16 tasklets**.\n> Ensure that you maintain this configuration (`--num_tasklets 16`) for accurate replication. \n\n## Figure 10: Multi-DPU Latency Breakdown and Speedup\n<img src=\"../assets/uPIMulator_figure10.png\" width=\"400\"/>\n\nFigure 10 presents the latency breakdown and speedup achieved in multi-DPU scenarios.\n\n### Configuring the Number of DPUs\nYou can adjust the number of DPUs by modifying the `num_dpus` parameter in both the `uPIMulator_frontend` and `uPIMulator_backend`.\n\n### Generating the Latency Breakdown\nTo obtain the latency breakdown data for plotting, utilize the `upmem_reg_model` tool located in the `tools/upmem_reg_model/` directory.\nThis tool implements a communication model between the host and DPUs based on linear regression.\n\n### Procedure\n\n1. **Prepare Input Excel:**\n   - We provide a sample input Excel file as a template.\n   - Append a new row to this file, specifying the benchmark name, number of DPUs, and the `data_prep_param` used in your simulation.\n   - Fill in the relevant time values (in milliseconds) obtained from your simulation results, such as kernel execution time.\n\n2. **Run the Regression Model:**\n\n   ```bash\n   cd /path/to/uPIMulator/tools/upmem_reg_model/src\n   python main.py --input_excel_filepath /path/to/your/input_excel_file --output_excel_filepath /path/to/your/output_excel_file\n   ```\n\n3. **Access the Output:** \n   - The linear regression results will be available in the specified output Excel file.\n   - Use this data to create the latency breakdown plots as shown in Figure 10.\n\nPlease ensure that you follow these steps carefully to accurately reproduce the multi-DPU latency breakdown and speedup analysis presented in the paper.\n\n# 🌋 Adding Custom Benchmarks\nuPIMulator empowers you to go beyond the provided PrIM benchmark suite by incorporating your own custom benchmarks.\nThis is particularly beneficial if you have access to UPMEM-PIM hardware and want to evaluate your code's performance in a simulated environment.\n\n## Requirements\nTo successfully integrate a new benchmark, ensure it adheres to the following:\n\n1. **UPMEM-C Language:**  The benchmark must be implemented in UPMEM-C, a C-like language tailored for UPMEM-PIM programming.\nConsult the [UPMEM SDK documentation](https://sdk.upmem.com/2021.4.0/) for detailed programming guidelines.\n\n2. **File Structure and Naming:**  \n   - Maintain the same file hierarchy as the PrIM benchmarks, including a `dpu` subdirectory.\n   - Utilize the same `Makefile` structure used by the PrIM suite for automated compilation.\n\n3. **Communication Variables:**\n   - **Host-to-DPU:** Use the `DPU_INPUT_ARGUMENTS` variable for data transfer from the host to DPUs via WRAM.\n   - **DPU-to-Host:**  Use the `DPU_RESULTS` variable for data transfer from DPUs to the host via WRAM.\n   > **Important:** Deviating from these variable names will result in the linker ignoring the communication during the linking phase.\n\n## Data Preparation\nOnce your benchmark meets the above criteria, it's ready for data input.\nSince UPMEM PIM-enabled memory directly utilizes physical addresses, exercise caution when feeding input/output data. \n\nYou'll need to provide a Python script to handle data preparation for your benchmark.\nThis script should reside in the `uPIMulator_frontend/src/assembler/data_prep` directory and be recognized by `uPIMulator_frontend/src/assembler/assembler.py`.\n\n> **Key Considerations for Data Preparation Scripts: \n> - Data transferred from the host to DPUs using `dpu_push_xfer` must be organized within the `input_dpu_mram_heap_pointer_name` variable in your data preparation script.\n> - Similarly, data transferred from DPUs to the host using `dpu_push_xfer` should be placed within the `output_dpu_mram_heap_pointer_name` variable.\n\n## Reference Examples\nWe have included data preparation scripts for the 13 supported PrIM benchmarks.\nThese serve as excellent references for structuring your custom data preparation scripts.\n\nBy following these guidelines, you can seamlessly integrate your benchmarks into uPIMulator for comprehensive performance evaluation and analysis. \n\nIf you have any questions or encounter any difficulties during the integration process, contact us with any questions or difficulties.\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\n#set(CMAKE_CXX_COMPILER \"/opt/rh/devtoolset-8/root/usr/bin/g++\")\n#set(CMAKE_CXX_COMPILER \"/usr/bin/g++-8\")\nset(CMAKE_CXX_COMPILER \"/usr/bin/g++\")\n\nset(CMAKE_CXX_STANDARD 20)\nset(CMAKE_CXX_FLAGS \"-O3\")\n#set(CMAKE_CXX_FLAGS  \"-g\")\n\nlink_libraries(stdc++fs)\n\nproject(uPIMulator)\n\nadd_subdirectory(src)\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/script/build.sh",
    "content": "#!/bin/bash\n\nmkdir -p ../build\ncd ../build || exit\n# shellcheck disable=SC2035\nrm -rf *\ncmake ..\nmake -j\ncd - || exit"
  },
  {
    "path": "python_cpp/uPIMulator_backend/script/format.sh",
    "content": "#!/bin/bash\n\ncd ../lib\nfind . -regex '.*\\.\\(cpp\\|hpp\\|cc\\|h\\)' -exec clang-format -style=Google -i {} \\;\ncd -\n\ncd ../src\nfind . -regex '.*\\.\\(cpp\\|hpp\\|cc\\|h\\)' -exec clang-format -style=Google -i {} \\;\ncd -\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/script/run.sh",
    "content": "#/bin/bash\n\nnum_dpus=$1\nbenchmark=$2\ndata_size=$3\n\neval \"mkdir -p /home/dongjae/pimulator/new_experiment_result/multi_dpus/trace/${benchmark}/${data_size}/${num_dpus}_dpus\"\n\necho \"${benchmark} - ${data_size}\"\neval \"mkdir -p /home/dongjae/pimulator/new_experiment_result/multi_dpus/log/${benchmark}/${data_size}/${num_dpus}_dpus/${benchmark}.16.\"\nsim_name=\"/home/dongjae/pimulator/simulator/upmem_sim_multi_dpus/build/src/upmem_sim\"\nbin_dir=\"/home/dongjae/pimulator/bin_files/bin_multi/${benchmark}/${data_size}/${num_dpus}_dpus/\"\nlog_dir=\"/home/dongjae/pimulator/new_experiment_result/multi_dpus/log/${benchmark}/${data_size}/${num_dpus}_dpus/${benchmark}.16.\" # Note that you should add '/' at the last position\nlog_path=\"/home/dongjae/pimulator/new_experiment_result/multi_dpus/trace/${benchmark}/${data_size}/${num_dpus}_dpus/\"\ncmd=\"nohup ${sim_name} --benchmark ${benchmark} --num_tasklets 16 --bindir ${bin_dir} --logdir ${log_dir} --num_dpus ${num_dpus} 1> ${log_path}/${benchmark}.16.trace &\"\necho ${cmd}\neval ${cmd}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/script/run_serial.sh",
    "content": "#/bin/bash\n\nnum_dpus=$1\nbenchmark=$2\ndata_size=$3\n\necho \"${benchmark} - ${data_size}\"\neval \"mkdir -p /home/dongjae/pimulator/hpca_2024_log/multi_dpus_validation/${benchmark}/${data_size}/${num_dpus}_dpus/${benchmark}.16.\"\nsim_name=\"/home/dongjae/pimulator/simulator/upmem_sim_multi_dpus/build/src/upmem_sim\"\nbin_dir=\"/home/dongjae/pimulator/bin_files_validation/bin_multi/${benchmark}/${data_size}/${num_dpus}_dpus/\"\nlog_dir=\"/home/dongjae/pimulator/hpca_2024_log/multi_dpus_validation/${benchmark}/${data_size}/${num_dpus}_dpus/${benchmark}.16.\" # Note that you should add '/' at the last position\ncmd=\"nohup ${sim_name} --benchmark ${benchmark} --num_tasklets 16 --bindir ${bin_dir} --logdir ${log_dir} --num_dpus ${num_dpus}\"\necho ${cmd}\neval ${cmd}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\ninclude_directories(.)\n\nfile(GLOB_RECURSE SRCS *.cc)\n\nadd_executable(uPIMulator ${SRCS})\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/_base_cc.cc",
    "content": "#include \"_base_cc.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::abi::cc {\n\n_BaseCC::_BaseCC(std::set<isa::Condition> conditions, isa::Condition condition)\n    : condition_(condition) {\n  assert(conditions.count(condition) != 0);\n}\n\n}  // namespace upmem_sim::abi::cc\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/_base_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC__BASE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC__BASE_CC_H_\n\n#include <set>\n\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass _BaseCC {\n public:\n  explicit _BaseCC(std::set<isa::Condition> conditions,\n                   isa::Condition condition);\n  ~_BaseCC() = default;\n\n  isa::Condition condition() { return condition_; }\n\n private:\n  isa::Condition condition_;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/acquire_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_ACQUIRE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_ACQUIRE_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass AcquireCC : public _BaseCC {\n public:\n  explicit AcquireCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::TRUE}, condition) {}\n  ~AcquireCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/add_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_ADD_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_ADD_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass AddNZCC : public _BaseCC {\n public:\n  explicit AddNZCC(isa::Condition condition)\n      : _BaseCC({isa::C,    isa::NC,   isa::Z,    isa::NZ,   isa::XZ,\n                 isa::XNZ,  isa::OV,   isa::NOV,  isa::PL,   isa::MI,\n                 isa::SZ,   isa::SNZ,  isa::SPL,  isa::SMI,  isa::NC5,\n                 isa::NC6,  isa::NC7,  isa::NC8,  isa::NC9,  isa::NC10,\n                 isa::NC11, isa::NC12, isa::NC13, isa::NC14, isa::TRUE},\n                condition) {}\n  ~AddNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/boot_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_BOOT_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_BOOT_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass BootCC : public _BaseCC {\n public:\n  explicit BootCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::SZ, isa::SNZ,\n                 isa::SPL, isa::SMI, isa::TRUE, isa::FALSE},\n                condition) {}\n  ~BootCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/const_cc_ge0.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_CONST_CC_GE0_H_\n#define UPMEM_SIM_ABI_ISA_CC_CONST_CC_GE0_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ConstCCGE0 : public _BaseCC {\n public:\n  explicit ConstCCGE0(isa::Condition condition)\n      : _BaseCC({isa::PL}, condition) {}\n  ~ConstCCGE0() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/const_cc_geu.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_CONST_CC_GEU_H_\n#define UPMEM_SIM_ABI_ISA_CC_CONST_CC_GEU_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ConstCCGEU : public _BaseCC {\n public:\n  explicit ConstCCGEU(isa::Condition condition)\n      : _BaseCC({isa::GEU}, condition) {}\n  ~ConstCCGEU() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/const_cc_zero.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_CONST_CC_ZERO_H_\n#define UPMEM_SIM_ABI_ISA_CC_CONST_CC_ZERO_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ConstCCZero : public _BaseCC {\n public:\n  explicit ConstCCZero(isa::Condition condition)\n      : _BaseCC({isa::Z}, condition) {}\n  ~ConstCCZero() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/count_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_COUNT_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_COUNT_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass CountNZCC : public _BaseCC {\n public:\n  explicit CountNZCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::SZ, isa::SNZ,\n                 isa::SPL, isa::SMI, isa::MAX, isa::NMAX, isa::TRUE},\n                condition) {}\n  ~CountNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/div_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_DIV_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_DIV_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass DivCC : public _BaseCC {\n public:\n  explicit DivCC(isa::Condition condition)\n      : _BaseCC({isa::SZ, isa::SNZ, isa::SPL, isa::SMI, isa::TRUE, isa::FALSE},\n                condition) {}\n  ~DivCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/div_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_DIV_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_DIV_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass DivNZCC : public _BaseCC {\n public:\n  explicit DivNZCC(isa::Condition condition)\n      : _BaseCC({isa::SZ, isa::SNZ, isa::SPL, isa::SMI, isa::TRUE}, condition) {\n  }\n  ~DivNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/ext_sub_set_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_EXT_SUB_SET_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_EXT_SUB_SET_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ExtSubSetCC : public _BaseCC {\n public:\n  explicit ExtSubSetCC(isa::Condition condition)\n      : _BaseCC({isa::C,    isa::NC,   isa::Z,    isa::NZ,   isa::XZ,  isa::XNZ,\n                 isa::OV,   isa::NOV,  isa::EQ,   isa::NEQ,  isa::PL,  isa::MI,\n                 isa::SZ,   isa::SNZ,  isa::SPL,  isa::SMI,  isa::GES, isa::GEU,\n                 isa::GTS,  isa::GTU,  isa::LES,  isa::LEU,  isa::LTS, isa::LTU,\n                 isa::XGTS, isa::XGTU, isa::XLES, isa::XLEU, isa::TRUE},\n                condition) {}\n  ~ExtSubSetCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/false_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_FALSE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_FALSE_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass FalseCC : public _BaseCC {\n public:\n  explicit FalseCC(isa::Condition condition)\n      : _BaseCC({isa::FALSE}, condition) {}\n  ~FalseCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/imm_shift_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_IMM_SHIFT_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_IMM_SHIFT_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ImmShiftNZCC : public _BaseCC {\n public:\n  explicit ImmShiftNZCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::E, isa::O, isa::PL,\n                 isa::MI, isa::SZ, isa::SNZ, isa::SPL, isa::SMI, isa::SE,\n                 isa::SO, isa::TRUE},\n                condition) {}\n  ~ImmShiftNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/log_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_LOG_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_LOG_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass LogNZCC : public _BaseCC {\n public:\n  explicit LogNZCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::PL, isa::MI, isa::SZ,\n                 isa::SNZ, isa::SPL, isa::SMI, isa::TRUE},\n                condition) {}\n  ~LogNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/log_set_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_LOG_SET_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_LOG_SET_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass LogSetCC : public _BaseCC {\n public:\n  explicit LogSetCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ}, condition) {}\n  ~LogSetCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/mul_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_MUL_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_MUL_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass MulNZCC : public _BaseCC {\n public:\n  explicit MulNZCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::SZ, isa::SNZ,\n                 isa::SPL, isa::SMI, isa::LARGE, isa::SMALL, isa::TRUE},\n                condition) {}\n  ~MulNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/no_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_NO_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_NO_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass NoCC : public _BaseCC {\n public:\n  explicit NoCC(isa::Condition condition) : _BaseCC({}, condition) {}\n  ~NoCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/release_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_RELEASE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_RELEASE_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ReleaseCC : public _BaseCC {\n public:\n  explicit ReleaseCC(isa::Condition condition)\n      : _BaseCC({isa::NZ}, condition) {}\n  ~ReleaseCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/shift_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_SHIFT_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_SHIFT_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass ShiftNZCC : public _BaseCC {\n public:\n  explicit ShiftNZCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::E, isa::O, isa::PL,\n                 isa::MI, isa::SZ, isa::SNZ, isa::SE, isa::SO, isa::SPL,\n                 isa::SMI, isa::SH32, isa::NSH32, isa::TRUE},\n                condition) {}\n  ~ShiftNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/sub_nz_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_SUB_NZ_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_SUB_NZ_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass SubNZCC : public _BaseCC {\n public:\n  explicit SubNZCC(isa::Condition condition)\n      : _BaseCC({isa::C,    isa::NC,   isa::Z,   isa::NZ,  isa::XZ,   isa::XNZ,\n                 isa::OV,   isa::NOV,  isa::MI,  isa::PL,  isa::EQ,   isa::NEQ,\n                 isa::SPL,  isa::SMI,  isa::GES, isa::GEU, isa::GTS,  isa::GTU,\n                 isa::LES,  isa::LEU,  isa::LTS, isa::LTU, isa::XGTS, isa::XGTU,\n                 isa::XLES, isa::XLEU, isa::TRUE},\n                condition) {}\n  ~SubNZCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/sub_set_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_SUB_SET_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_SUB_SET_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass SubSetCC : public _BaseCC {\n public:\n  explicit SubSetCC(isa::Condition condition)\n      : _BaseCC({isa::Z, isa::NZ, isa::XZ, isa::XNZ, isa::EQ, isa::NEQ},\n                condition) {}\n  ~SubSetCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/true_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_TRUE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_TRUE_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass TrueCC : public _BaseCC {\n public:\n  explicit TrueCC(isa::Condition condition) : _BaseCC({isa::TRUE}, condition) {}\n  ~TrueCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/cc/true_false_cc.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_CC_TRUE_FALSE_CC_H_\n#define UPMEM_SIM_ABI_ISA_CC_TRUE_FALSE_CC_H_\n\n#include \"_base_cc.h\"\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::abi::cc {\n\nclass TrueFalseCC : public _BaseCC {\n public:\n  explicit TrueFalseCC(isa::Condition condition)\n      : _BaseCC({isa::TRUE, isa::FALSE}, condition) {}\n  ~TrueFalseCC() = default;\n};\n\n}  // namespace upmem_sim::abi::cc\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/instruction/instruction.cc",
    "content": "#include \"instruction.h\"\n\n#include <sstream>\n\n#include \"abi/cc/acquire_cc.h\"\n#include \"abi/cc/add_nz_cc.h\"\n#include \"abi/cc/boot_cc.h\"\n#include \"abi/cc/count_nz_cc.h\"\n#include \"abi/cc/div_cc.h\"\n#include \"abi/cc/div_nz_cc.h\"\n#include \"abi/cc/ext_sub_set_cc.h\"\n#include \"abi/cc/false_cc.h\"\n#include \"abi/cc/imm_shift_nz_cc.h\"\n#include \"abi/cc/log_nz_cc.h\"\n#include \"abi/cc/log_set_cc.h\"\n#include \"abi/cc/mul_nz_cc.h\"\n#include \"abi/cc/release_cc.h\"\n#include \"abi/cc/shift_nz_cc.h\"\n#include \"abi/cc/sub_nz_cc.h\"\n#include \"abi/cc/sub_set_cc.h\"\n#include \"abi/cc/true_cc.h\"\n#include \"abi/cc/true_false_cc.h\"\n\nnamespace upmem_sim::abi::instruction {\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         int64_t imm, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  if (suffix_ == RICI) {\n    init_rici(ra, imm, condition, pc);\n  } else if (suffix_ == ZRICI) {\n    init_zrici(ra, imm, condition, pc);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rri(rc, ra, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, int64_t imm, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  if (suffix_ == RRIC) {\n    init_rric(rc, ra, imm, condition);\n  } else if (suffix_ == RRIF) {\n    init_rrif(rc, ra, imm, condition);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                         int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rrici(rc, ra, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, reg::SrcReg *rb)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_rrr(rc, ra, rb);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, reg::SrcReg *rb,\n                         isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_rrrc(rc, ra, rb, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, reg::SrcReg *rb,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_rrrci(rc, ra, rb, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zri(ra, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         int64_t imm, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  if (suffix_ == ZRIC) {\n    init_zric(ra, imm, condition);\n  } else if (suffix_ == ZRIF) {\n    init_zrif(ra, imm, condition);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         reg::SrcReg *rb)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_zrr(ra, rb);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         reg::SrcReg *rb, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_zrrc(ra, rb, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         reg::SrcReg *rb, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_zrrci(ra, rb, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rri(dc, ra, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, int64_t imm, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  if (suffix == S_RRIC or suffix == U_RRIC) {\n    init_s_rric(dc, ra, imm, condition);\n  } else if (suffix == S_RRIF or suffix == U_RRIF) {\n    init_s_rrif(dc, ra, imm, condition);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                         int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rrici(dc, ra, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::SrcReg *rb)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_s_rrr(dc, ra, rb);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::SrcReg *rb,\n                         isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_s_rrrc(dc, ra, rb, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::SrcReg *rb,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_s_rrrci(dc, ra, rb, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rr(rc, ra);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rrc(rc, ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rrci(rc, ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zr(ra);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zrc(ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zrci(ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rr(dc, ra);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rrc(dc, ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rrci(dc, ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::PairReg *db, int64_t imm,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(db != nullptr);\n\n  init_drdici(dc, ra, db, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_rrri(rc, ra, rb, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_rrrici(rc, ra, rb, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         reg::SrcReg *rb, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  if (suffix == ZRRI) {\n    init_zrri(ra, rb, imm);\n  } else if (suffix == DMA_RRI) {\n    init_dma_rri(ra, rb, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                         reg::SrcReg *rb, int64_t imm, isa::Condition condition,\n                         int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_zrrici(ra, rb, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_s_rrri(dc, ra, rb, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_s_rrrici(dc, ra, rb, imm, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         int64_t imm, reg::SrcReg *ra)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rir(rc, imm, ra);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         int64_t imm, reg::SrcReg *ra, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rirc(rc, imm, ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         int64_t imm, reg::SrcReg *ra, isa::Condition condition,\n                         int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_rirci(rc, imm, ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                         reg::SrcReg *ra)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zir(imm, ra);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                         reg::SrcReg *ra, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zirc(imm, ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                         reg::SrcReg *ra, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_zirci(imm, ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         int64_t imm, reg::SrcReg *ra, isa::Condition condition)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rirc(dc, imm, ra, condition);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         int64_t imm, reg::SrcReg *ra, isa::Condition condition,\n                         int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  init_s_rirci(dc, imm, ra, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n\n  init_r(rc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n\n  init_rci(rc, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  init_z();\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  if (suffix == ZCI) {\n    init_zci(condition, pc);\n  } else if (suffix == CI) {\n    init_ci(condition, pc);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n\n  init_s_r(dc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n\n  init_s_rci(dc, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  init_i(imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                         reg::PairReg *db, isa::Condition condition, int64_t pc)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(db != nullptr);\n\n  init_ddci(dc, db, condition, pc);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                         reg::GPReg *rc, reg::SrcReg *ra, int64_t off)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(rc != nullptr);\n  assert(ra != nullptr);\n\n  init_erri(endian, rc, ra, off);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                         reg::PairReg *dc, reg::SrcReg *ra, int64_t off)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(dc != nullptr);\n  assert(ra != nullptr);\n\n  if (suffix == S_ERRI or suffix == U_ERRI) {\n    init_s_erri(endian, dc, ra, off);\n  } else if (suffix == EDRI) {\n    init_edri(endian, dc, ra, off);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                         reg::SrcReg *ra, int64_t off, int64_t imm)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n\n  init_erii(endian, ra, off, imm);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                         reg::SrcReg *ra, int64_t off, reg::SrcReg *rb)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(rb != nullptr);\n\n  init_erir(endian, ra, off, rb);\n}\n\nInstruction::Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                         reg::SrcReg *ra, int64_t off, reg::PairReg *db)\n    : op_code_(op_code),\n      suffix_(suffix),\n      rc_(nullptr),\n      ra_(nullptr),\n      rb_(nullptr),\n      dc_(nullptr),\n      db_(nullptr),\n      condition_(nullptr),\n      imm_(nullptr),\n      off_(nullptr),\n      pc_(nullptr),\n      endian_(nullptr),\n      thread_(nullptr) {\n  assert(ra != nullptr);\n  assert(db != nullptr);\n\n  init_erid(endian, ra, off, db);\n}\n\nInstruction::~Instruction() {\n  delete rc_;\n  delete dc_;\n  delete db_;\n  delete condition_;\n  delete imm_;\n  delete off_;\n  delete pc_;\n  delete endian_;\n}\n\nreg::GPReg *Instruction::rc() {\n  assert(rc_ != nullptr);\n  return rc_;\n}\n\nreg::SrcReg *Instruction::ra() {\n  assert(ra_ != nullptr);\n  return ra_;\n}\n\nreg::SrcReg *Instruction::rb() {\n  assert(rb_ != nullptr);\n  return rb_;\n}\n\nreg::PairReg *Instruction::dc() {\n  assert(dc_ != nullptr);\n  return dc_;\n}\n\nreg::PairReg *Instruction::db() {\n  assert(db_ != nullptr);\n  return db_;\n}\n\nisa::Condition Instruction::condition() {\n  assert(condition_ != nullptr);\n  return *condition_;\n}\n\nabi::word::Immediate *Instruction::imm() {\n  assert(imm_ != nullptr);\n  return imm_;\n}\n\nabi::word::Immediate *Instruction::off() {\n  assert(off_ != nullptr);\n  return off_;\n}\n\nabi::word::Immediate *Instruction::pc() {\n  assert(pc_ != nullptr);\n  return pc_;\n}\n\nisa::Endian Instruction::endian() {\n  assert(endian_ != nullptr);\n  return *endian_;\n}\n\nsimulator::dpu::Thread *Instruction::thread() {\n  assert(thread_ != nullptr);\n  return thread_;\n}\n\nvoid Instruction::set_thread(simulator::dpu::Thread *thread) {\n  assert(thread != nullptr);\n  assert(thread_ == nullptr);\n\n  thread_ = thread;\n}\n\nvoid Instruction::init_rici(reg::SrcReg *ra, int64_t imm,\n                            isa::Condition condition, int64_t pc) {\n  assert(Instruction::rici_op_codes().count(op_code_));\n  assert(suffix_ == RICI);\n\n  ra_ = ra;\n  imm_ = new word::Immediate(word::SIGNED, 16, imm);\n\n  if (Instruction::acquire_rici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AcquireCC(condition).condition());\n  } else if (Instruction::release_rici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ReleaseCC(condition).condition());\n  } else if (Instruction::boot_rici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::BootCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_rri(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm) {\n  assert(Instruction::rri_op_codes().count(op_code_));\n  assert(suffix_ == RRI);\n\n  rc_ = rc;\n  ra_ = ra;\n\n  if (Instruction::add_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 32, imm);\n  } else if (Instruction::asr_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else if (Instruction::call_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_rric(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                            isa::Condition condition) {\n  assert(Instruction::rric_op_codes().count(op_code_));\n  assert(suffix_ == RRIC);\n\n  rc_ = rc;\n  ra_ = ra;\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::sub_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  } else if (Instruction::asr_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::asr_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::sub_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_rrici(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrici_op_codes().count(op_code_));\n  assert(suffix_ == RRICI);\n\n  rc_ = rc;\n  ra_ = ra;\n\n  if (Instruction::add_rrici_op_codes().count(op_code_) or\n      Instruction::and_rrici_op_codes().count(op_code_) or\n      Instruction::sub_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 8, imm);\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ImmShiftNZCC(condition).condition());\n  } else if (Instruction::sub_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_rrif(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                            isa::Condition condition) {\n  assert(Instruction::rrif_op_codes().count(op_code_));\n  assert(suffix_ == RRIF);\n\n  rc_ = rc;\n  ra_ = ra;\n  imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  condition_ = new isa::Condition(cc::FalseCC(condition).condition());\n}\n\nvoid Instruction::init_rrr(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb) {\n  assert(Instruction::rrr_op_codes().count(op_code_));\n  assert(suffix_ == RRR);\n\n  rc_ = rc;\n  ra_ = ra;\n  rb_ = rb;\n}\n\nvoid Instruction::init_rrrc(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                            isa::Condition condition) {\n  assert(Instruction::rrrc_op_codes().count(op_code_));\n  assert(suffix_ == RRRC);\n\n  rc_ = rc;\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::rsub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n  } else if (Instruction::sub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_rrrci(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrrci_op_codes().count(op_code_));\n  assert(suffix_ == RRRCI);\n\n  rc_ = rc;\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ShiftNZCC(condition).condition());\n  } else if (Instruction::mul_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::MulNZCC(condition).condition());\n  } else if (Instruction::rsub_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_zri(reg::SrcReg *ra, int64_t imm) {\n  assert(Instruction::rri_op_codes().count(op_code_));\n  assert(suffix_ == ZRI);\n\n  ra_ = ra;\n\n  if (Instruction::add_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 32, imm);\n  } else if (Instruction::asr_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else if (Instruction::call_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 28, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_zric(reg::SrcReg *ra, int64_t imm,\n                            isa::Condition condition) {\n  assert(Instruction::rric_op_codes().count(op_code_));\n  assert(suffix_ == ZRIC);\n\n  ra_ = ra;\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::sub_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 27, imm);\n  } else if (Instruction::asr_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::asr_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::sub_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_zrici(reg::SrcReg *ra, int64_t imm,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrrci_op_codes().count(op_code_));\n  assert(suffix_ == ZRICI);\n\n  ra_ = ra;\n\n  if (Instruction::add_rrici_op_codes().count(op_code_) or\n      Instruction::and_rrici_op_codes().count(op_code_) or\n      Instruction::sub_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 11, imm);\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ImmShiftNZCC(condition).condition());\n  } else if (Instruction::sub_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_zrif(reg::SrcReg *ra, int64_t imm,\n                            isa::Condition condition) {\n  assert(Instruction::rrif_op_codes().count(op_code_));\n  assert(suffix_ == ZRIF);\n\n  ra_ = ra;\n  imm_ = new word::Immediate(word::SIGNED, 27, imm);\n  condition_ = new isa::Condition(cc::FalseCC(condition).condition());\n}\n\nvoid Instruction::init_zrr(reg::SrcReg *ra, reg::SrcReg *rb) {\n  assert(Instruction::rrr_op_codes().count(op_code_));\n  assert(suffix_ == ZRR);\n\n  ra_ = ra;\n  rb_ = rb;\n}\n\nvoid Instruction::init_zrrc(reg::SrcReg *ra, reg::SrcReg *rb,\n                            isa::Condition condition) {\n  assert(Instruction::rrrc_op_codes().count(op_code_));\n  assert(suffix_ == ZRRC);\n\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::rsub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n  } else if (Instruction::sub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_zrrci(reg::SrcReg *ra, reg::SrcReg *rb,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrrci_op_codes().count(op_code_));\n  assert(suffix_ == ZRRCI);\n\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ShiftNZCC(condition).condition());\n  } else if (Instruction::mul_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::MulNZCC(condition).condition());\n  } else if (Instruction::rsub_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_rri(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm) {\n  assert(Instruction::rri_op_codes().count(op_code_));\n  assert(suffix_ == S_RRI or suffix_ == U_RRI);\n\n  dc_ = dc;\n  ra_ = ra;\n\n  if (Instruction::add_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 32, imm);\n  } else if (Instruction::asr_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else if (Instruction::call_rri_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_s_rric(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                              isa::Condition condition) {\n  assert(Instruction::rric_op_codes().count(op_code_));\n  assert(suffix_ == S_RRIC or suffix_ == U_RRIC);\n\n  dc_ = dc;\n  ra_ = ra;\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::sub_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  } else if (Instruction::asr_rric_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rric_op_codes().count(op_code_) or\n      Instruction::asr_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::sub_rric_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_s_rrici(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                               isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrici_op_codes().count(op_code_));\n  assert(suffix_ == S_RRICI or suffix_ == U_RRICI);\n\n  dc_ = dc;\n  ra_ = ra;\n\n  if (Instruction::add_rrici_op_codes().count(op_code_) or\n      Instruction::and_rrici_op_codes().count(op_code_) or\n      Instruction::sub_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::SIGNED, 8, imm);\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (Instruction::add_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ImmShiftNZCC(condition).condition());\n  } else if (Instruction::sub_rrici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_rrif(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                              isa::Condition condition) {\n  assert(Instruction::rrif_op_codes().count(op_code_));\n  assert(suffix_ == S_RRIF or suffix_ == U_RRIF);\n\n  dc_ = dc;\n  ra_ = ra;\n  imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  condition_ = new isa::Condition(cc::FalseCC(condition).condition());\n}\n\nvoid Instruction::init_s_rrr(reg::PairReg *dc, reg::SrcReg *ra,\n                             reg::SrcReg *rb) {\n  assert(Instruction::rrr_op_codes().count(op_code_));\n  assert(suffix_ == S_RRR or suffix_ == U_RRR);\n\n  dc_ = dc;\n  ra_ = ra;\n  rb_ = rb;\n}\n\nvoid Instruction::init_s_rrrc(reg::PairReg *dc, reg::SrcReg *ra,\n                              reg::SrcReg *rb, isa::Condition condition) {\n  assert(Instruction::rrrc_op_codes().count(op_code_));\n  assert(suffix_ == S_RRRC or suffix_ == U_RRRC);\n\n  dc_ = dc;\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n  } else if (Instruction::rsub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n  } else if (Instruction::sub_rrrc_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ExtSubSetCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Instruction::init_s_rrrci(reg::PairReg *dc, reg::SrcReg *ra,\n                               reg::SrcReg *rb, isa::Condition condition,\n                               int64_t pc) {\n  assert(Instruction::rrrci_op_codes().count(op_code_));\n  assert(suffix_ == S_RRRCI or suffix_ == U_RRRCI);\n\n  dc_ = dc;\n  ra_ = ra;\n  rb_ = rb;\n\n  if (Instruction::add_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::AddNZCC(condition).condition());\n  } else if (Instruction::and_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::asr_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::ShiftNZCC(condition).condition());\n  } else if (Instruction::mul_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::MulNZCC(condition).condition());\n  } else if (Instruction::rsub_rrrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_rr(reg::GPReg *rc, reg::SrcReg *ra) {\n  assert(Instruction::rr_op_codes().count(op_code_));\n  assert(suffix_ == RR);\n\n  rc_ = rc;\n  ra_ = ra;\n}\n\nvoid Instruction::init_rrc(reg::GPReg *rc, reg::SrcReg *ra,\n                           isa::Condition condition) {\n  assert(Instruction::rrc_op_codes().count(op_code_));\n  assert(suffix_ == RRC);\n\n  rc_ = rc;\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n}\n\nvoid Instruction::init_rrci(reg::GPReg *rc, reg::SrcReg *ra,\n                            isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrci_op_codes().count(op_code_));\n  assert(suffix_ == RRCI);\n\n  rc_ = rc;\n  ra_ = ra;\n\n  if (Instruction::cao_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::CountNZCC(condition).condition());\n  } else if (Instruction::extsb_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::time_cfg_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_zr(reg::SrcReg *ra) {\n  assert(Instruction::rr_op_codes().count(op_code_));\n  assert(suffix_ == ZR);\n\n  ra_ = ra;\n}\n\nvoid Instruction::init_zrc(reg::SrcReg *ra, isa::Condition condition) {\n  assert(Instruction::rrc_op_codes().count(op_code_));\n  assert(suffix_ == ZRC);\n\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n}\n\nvoid Instruction::init_zrci(reg::SrcReg *ra, isa::Condition condition,\n                            int64_t pc) {\n  assert(Instruction::rrci_op_codes().count(op_code_));\n  assert(suffix_ == ZRCI);\n\n  ra_ = ra;\n\n  if (Instruction::cao_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::CountNZCC(condition).condition());\n  } else if (Instruction::extsb_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::time_cfg_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_rr(reg::PairReg *dc, reg::SrcReg *ra) {\n  assert(Instruction::rr_op_codes().count(op_code_));\n  assert(suffix_ == S_RR or suffix_ == U_RR);\n\n  dc_ = dc;\n  ra_ = ra;\n}\n\nvoid Instruction::init_s_rrc(reg::PairReg *dc, reg::SrcReg *ra,\n                             isa::Condition condition) {\n  assert(Instruction::rrc_op_codes().count(op_code_));\n  assert(suffix_ == S_RRC or suffix_ == U_RRC);\n\n  dc_ = dc;\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::LogSetCC(condition).condition());\n}\n\nvoid Instruction::init_s_rrci(reg::PairReg *dc, reg::SrcReg *ra,\n                              isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrci_op_codes().count(op_code_));\n  assert(suffix_ == S_RRCI or suffix_ == U_RRCI);\n\n  dc_ = dc;\n  ra_ = ra;\n\n  if (Instruction::cao_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::CountNZCC(condition).condition());\n  } else if (Instruction::extsb_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::LogNZCC(condition).condition());\n  } else if (Instruction::time_cfg_rrci_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_drdici(reg::PairReg *dc, reg::SrcReg *ra,\n                              reg::PairReg *db, int64_t imm,\n                              isa::Condition condition, int64_t pc) {\n  assert(Instruction::drdici_op_codes().count(op_code_));\n  assert(suffix_ == DRDICI);\n\n  dc_ = dc;\n  ra_ = ra;\n  db_ = db;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n\n  if (Instruction::div_step_drdici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::DivCC(condition).condition());\n  } else if (Instruction::mul_step_drdici_op_codes().count(op_code_)) {\n    condition_ = new isa::Condition(cc::BootCC(condition).condition());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_rrri(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                            int64_t imm) {\n  assert(Instruction::rrri_op_codes().count(op_code_));\n  assert(suffix_ == RRRI);\n\n  rc_ = rc;\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n}\n\nvoid Instruction::init_rrrici(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                              int64_t imm, isa::Condition condition,\n                              int64_t pc) {\n  assert(Instruction::rrrici_op_codes().count(op_code_));\n  assert(suffix_ == RRRICI);\n\n  rc_ = rc;\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  condition_ = new isa::Condition(cc::DivNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_zrri(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm) {\n  assert(Instruction::rrri_op_codes().count(op_code_));\n  assert(suffix_ == ZRRI);\n\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n}\n\nvoid Instruction::init_zrrici(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                              isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrrici_op_codes().count(op_code_));\n  assert(suffix_ == ZRRICI);\n\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  condition_ = new isa::Condition(cc::DivNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_rrri(reg::PairReg *dc, reg::SrcReg *ra,\n                              reg::SrcReg *rb, int64_t imm) {\n  assert(Instruction::rrri_op_codes().count(op_code_));\n  assert(suffix_ == S_RRRI or suffix_ == U_RRRI);\n\n  dc_ = dc;\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n}\n\nvoid Instruction::init_s_rrrici(reg::PairReg *dc, reg::SrcReg *ra,\n                                reg::SrcReg *rb, int64_t imm,\n                                isa::Condition condition, int64_t pc) {\n  assert(Instruction::rrrici_op_codes().count(op_code_));\n  assert(suffix_ == S_RRRICI or suffix_ == U_RRRICI);\n\n  dc_ = dc;\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 5, imm);\n  condition_ = new isa::Condition(cc::DivNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_rir(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra) {\n  assert(Instruction::rir_op_codes().count(op_code_));\n  assert(suffix_ == RIR);\n\n  rc_ = rc;\n  imm_ = new word::Immediate(word::UNSIGNED, 32, imm);\n  ra_ = ra;\n}\n\nvoid Instruction::init_rirc(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra,\n                            isa::Condition condition) {\n  assert(Instruction::rirc_op_codes().count(op_code_));\n  assert(suffix_ == RIRC);\n\n  rc_ = rc;\n  imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n}\n\nvoid Instruction::init_rirci(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rirci_op_codes().count(op_code_));\n  assert(suffix_ == RIRCI);\n\n  rc_ = rc;\n  imm_ = new word::Immediate(word::SIGNED, 8, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_zir(int64_t imm, reg::SrcReg *ra) {\n  assert(Instruction::rir_op_codes().count(op_code_));\n  assert(suffix_ == ZIR);\n\n  imm_ = new word::Immediate(word::UNSIGNED, 32, imm);\n  ra_ = ra;\n}\n\nvoid Instruction::init_zirc(int64_t imm, reg::SrcReg *ra,\n                            isa::Condition condition) {\n  assert(Instruction::rirc_op_codes().count(op_code_));\n  assert(suffix_ == ZIRC);\n\n  imm_ = new word::Immediate(word::SIGNED, 27, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n}\n\nvoid Instruction::init_zirci(int64_t imm, reg::SrcReg *ra,\n                             isa::Condition condition, int64_t pc) {\n  assert(Instruction::rirci_op_codes().count(op_code_));\n  assert(suffix_ == ZIRCI);\n\n  imm_ = new word::Immediate(word::SIGNED, 11, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_rirc(reg::PairReg *dc, int64_t imm, reg::SrcReg *ra,\n                              isa::Condition condition) {\n  assert(Instruction::rirc_op_codes().count(op_code_));\n  assert(suffix_ == S_RIRC or suffix_ == U_RIRC);\n\n  dc_ = dc;\n  imm_ = new word::Immediate(word::SIGNED, 24, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubSetCC(condition).condition());\n}\n\nvoid Instruction::init_s_rirci(reg::PairReg *dc, int64_t imm, reg::SrcReg *ra,\n                               isa::Condition condition, int64_t pc) {\n  assert(Instruction::rirci_op_codes().count(op_code_));\n  assert(suffix_ == S_RIRCI or suffix_ == U_RIRCI);\n\n  dc_ = dc;\n  imm_ = new word::Immediate(word::SIGNED, 8, imm);\n  ra_ = ra;\n  condition_ = new isa::Condition(cc::SubNZCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_r(reg::GPReg *rc) {\n  assert(Instruction::r_op_codes().count(op_code_));\n  assert(suffix_ == R);\n\n  rc_ = rc;\n}\n\nvoid Instruction::init_rci(reg::GPReg *rc, isa::Condition condition,\n                           int64_t pc) {\n  assert(Instruction::rci_op_codes().count(op_code_));\n  assert(suffix_ == RCI);\n\n  rc_ = rc;\n  condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_z() {\n  assert(Instruction::r_op_codes().count(op_code_) or op_code_ == NOP);\n  assert(suffix_ == Z);\n}\n\nvoid Instruction::init_zci(isa::Condition condition, int64_t pc) {\n  assert(Instruction::rci_op_codes().count(op_code_));\n  assert(suffix_ == ZCI);\n\n  condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_s_r(reg::PairReg *dc) {\n  assert(Instruction::r_op_codes().count(op_code_));\n  assert(suffix_ == S_R or suffix_ == U_R);\n\n  dc_ = dc;\n}\n\nvoid Instruction::init_s_rci(reg::PairReg *dc, isa::Condition condition,\n                             int64_t pc) {\n  assert(Instruction::rci_op_codes().count(op_code_));\n  assert(suffix_ == S_RCI or suffix_ == U_RCI);\n\n  dc_ = dc;\n  condition_ = new isa::Condition(cc::TrueCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_ci(isa::Condition condition, int64_t pc) {\n  assert(Instruction::ci_op_codes().count(op_code_));\n  assert(suffix_ == CI);\n\n  condition_ = new isa::Condition(cc::BootCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_i(int64_t imm) {\n  assert(Instruction::i_op_codes().count(op_code_));\n  assert(suffix_ == I);\n\n  imm_ = new word::Immediate(word::SIGNED, 24, imm);\n}\n\nvoid Instruction::init_ddci(reg::PairReg *dc, reg::PairReg *db,\n                            isa::Condition condition, int64_t pc) {\n  assert(Instruction::ddci_op_codes().count(op_code_));\n  assert(suffix_ == DDCI);\n\n  dc_ = dc;\n  db_ = db;\n  condition_ = new isa::Condition(cc::TrueFalseCC(condition).condition());\n  pc_ = new word::Immediate(word::UNSIGNED,\n                            util::ConfigLoader::iram_address_width(), pc);\n}\n\nvoid Instruction::init_erri(isa::Endian endian, reg::GPReg *rc, reg::SrcReg *ra,\n                            int64_t off) {\n  assert(Instruction::erri_op_codes().count(op_code_));\n  assert(suffix_ == ERRI);\n\n  endian_ = new isa::Endian(endian);\n  rc_ = rc;\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n}\n\nvoid Instruction::init_s_erri(isa::Endian endian, reg::PairReg *dc,\n                              reg::SrcReg *ra, int64_t off) {\n  assert(Instruction::erri_op_codes().count(op_code_));\n  assert(suffix_ == S_ERRI or suffix_ == U_ERRI);\n\n  endian_ = new isa::Endian(endian);\n  dc_ = dc;\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n}\n\nvoid Instruction::init_edri(isa::Endian endian, reg::PairReg *dc,\n                            reg::SrcReg *ra, int64_t off) {\n  assert(Instruction::edri_op_codes().count(op_code_));\n  assert(suffix_ == EDRI);\n\n  endian_ = new isa::Endian(endian);\n  dc_ = dc;\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n}\n\nvoid Instruction::init_erii(isa::Endian endian, reg::SrcReg *ra, int64_t off,\n                            int64_t imm) {\n  assert(Instruction::erii_op_codes().count(op_code_));\n  assert(suffix_ == ERII);\n\n  endian_ = new isa::Endian(endian);\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n  imm_ = new word::Immediate(word::SIGNED, 16, imm);\n}\n\nvoid Instruction::init_erir(isa::Endian endian, reg::SrcReg *ra, int64_t off,\n                            reg::SrcReg *rb) {\n  assert(Instruction::erir_op_codes().count(op_code_));\n  assert(suffix_ == ERIR);\n\n  endian_ = new isa::Endian(endian);\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n  rb_ = rb;\n}\n\nvoid Instruction::init_erid(isa::Endian endian, reg::SrcReg *ra, int64_t off,\n                            reg::PairReg *db) {\n  assert(Instruction::erid_op_codes().count(op_code_));\n  assert(suffix_ == ERID);\n\n  endian_ = new isa::Endian(endian);\n  ra_ = ra;\n  off_ = new word::Immediate(word::SIGNED, 24, off);\n  db_ = db;\n}\n\nvoid Instruction::init_dma_rri(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm) {\n  assert(Instruction::dma_rri_op_codes().count(op_code_));\n  assert(suffix_ == DMA_RRI);\n\n  ra_ = ra;\n  rb_ = rb;\n  imm_ = new word::Immediate(word::UNSIGNED, 8, imm);\n}\n\n}  // namespace upmem_sim::abi::instruction\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/instruction/instruction.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_INSTRUCTION_INSTRUCTION_H_\n#define UPMEM_SIM_ABI_ISA_INSTRUCTION_INSTRUCTION_H_\n\n#include <set>\n\n#include \"abi/instruction/op_code.h\"\n#include \"abi/instruction/suffix.h\"\n#include \"abi/isa/condition.h\"\n#include \"abi/isa/endian.h\"\n#include \"abi/reg/pair_reg.h\"\n#include \"abi/reg/src_reg.h\"\n#include \"abi/word/immediate.h\"\n#include \"simulator/dpu/thread.h\"\n\nnamespace upmem_sim::abi::instruction {\n\nclass Instruction {\n public:\n  static std::set<OpCode> acquire_rici_op_codes() { return {ACQUIRE}; }\n  static std::set<OpCode> release_rici_op_codes() { return {RELEASE}; }\n  static std::set<OpCode> boot_rici_op_codes() { return {BOOT, RESUME}; }\n  static std::set<OpCode> rici_op_codes() {\n    std::set<OpCode> acquire_rici_op_codes =\n        Instruction::acquire_rici_op_codes();\n    std::set<OpCode> release_rici_op_codes =\n        Instruction::release_rici_op_codes();\n    std::set<OpCode> boot_rici_op_codes = Instruction::boot_rici_op_codes();\n\n    std::set<OpCode> rici_op_codes = {};\n    rici_op_codes.insert(acquire_rici_op_codes.begin(),\n                         acquire_rici_op_codes.end());\n    rici_op_codes.insert(release_rici_op_codes.begin(),\n                         release_rici_op_codes.end());\n    rici_op_codes.insert(boot_rici_op_codes.begin(), boot_rici_op_codes.end());\n    return rici_op_codes;\n  }\n\n  static std::set<OpCode> add_rri_op_codes() {\n    return {ADD, ADDC, AND, OR, XOR};\n  }\n  static std::set<OpCode> asr_rri_op_codes() {\n    return {ASR, LSL, LSL1, LSL1X, LSLX, LSR, LSR1, LSR1X, LSRX, ROL, ROR};\n  }\n  static std::set<OpCode> call_rri_op_codes() { return {CALL}; }\n  static std::set<OpCode> rri_op_codes() {\n    std::set<OpCode> add_rri_op_codes = Instruction::add_rri_op_codes();\n    std::set<OpCode> asr_rri_op_codes = Instruction::asr_rri_op_codes();\n    std::set<OpCode> call_rri_op_codes = Instruction::call_rri_op_codes();\n\n    std::set<OpCode> rri_op_codes = {};\n    rri_op_codes.insert(add_rri_op_codes.begin(), add_rri_op_codes.end());\n    rri_op_codes.insert(asr_rri_op_codes.begin(), asr_rri_op_codes.end());\n    rri_op_codes.insert(call_rri_op_codes.begin(), call_rri_op_codes.end());\n    return rri_op_codes;\n  }\n\n  static std::set<OpCode> add_rric_op_codes() {\n    return {ADD, ADDC, AND, ANDN, NAND, NOR, NXOR, OR, ORN, XOR, HASH};\n  }\n  static std::set<OpCode> asr_rric_op_codes() {\n    return {ASR, LSL, LSL1, LSL1X, LSLX, LSR, LSR1, LSR1X, LSRX, ROL, ROR};\n  }\n  static std::set<OpCode> sub_rric_op_codes() { return {SUB, SUBC}; }\n  static std::set<OpCode> rric_op_codes() {\n    std::set<OpCode> add_rric_op_codes = Instruction::add_rric_op_codes();\n    std::set<OpCode> asr_rric_op_codes = Instruction::asr_rric_op_codes();\n    std::set<OpCode> sub_rric_op_codes = Instruction::sub_rric_op_codes();\n\n    std::set<OpCode> rric_op_codes = {};\n    rric_op_codes.insert(add_rric_op_codes.begin(), add_rric_op_codes.end());\n    rric_op_codes.insert(asr_rric_op_codes.begin(), asr_rric_op_codes.end());\n    rric_op_codes.insert(sub_rric_op_codes.begin(), sub_rric_op_codes.end());\n    return rric_op_codes;\n  }\n\n  static std::set<OpCode> add_rrici_op_codes() { return {ADD, ADDC}; }\n  static std::set<OpCode> and_rrici_op_codes() {\n    return {AND, ANDN, NAND, NOR, NXOR, OR, ORN, XOR, HASH};\n  }\n  static std::set<OpCode> asr_rrici_op_codes() {\n    return {ASR, LSL, LSL1, LSL1X, LSLX, LSR, LSR1, LSR1X, LSRX, ROL, ROR};\n  }\n  static std::set<OpCode> sub_rrici_op_codes() { return {SUB, SUBC}; }\n  static std::set<OpCode> rrici_op_codes() {\n    std::set<OpCode> add_rrici_op_codes = Instruction::add_rrici_op_codes();\n    std::set<OpCode> and_rrici_op_codes = Instruction::and_rrici_op_codes();\n    std::set<OpCode> asr_rrici_op_codes = Instruction::asr_rrici_op_codes();\n    std::set<OpCode> sub_rrici_op_codes = Instruction::sub_rrici_op_codes();\n\n    std::set<OpCode> rrici_op_codes = {};\n    rrici_op_codes.insert(add_rrici_op_codes.begin(), add_rrici_op_codes.end());\n    rrici_op_codes.insert(and_rrici_op_codes.begin(), and_rrici_op_codes.end());\n    rrici_op_codes.insert(asr_rrici_op_codes.begin(), asr_rrici_op_codes.end());\n    rrici_op_codes.insert(sub_rrici_op_codes.begin(), sub_rrici_op_codes.end());\n    return rrici_op_codes;\n  }\n\n  static std::set<OpCode> rrif_op_codes() {\n    return {ADD, ADDC, AND, ANDN, NAND, NOR, NXOR,\n            OR,  ORN,  SUB, SUBC, XOR,  HASH};\n  }\n\n  static std::set<OpCode> rrr_op_codes() {\n    return {ADD,       ADDC,      AND,       ANDN,      ASR,       CMPB4,\n            LSL,       LSL1,      LSL1X,     LSLX,      LSR,       LSR1,\n            LSR1X,     LSRX,      MUL_SH_SH, MUL_SH_SL, MUL_SH_UH, MUL_SH_UL,\n            MUL_SL_SH, MUL_SL_SL, MUL_SL_UH, MUL_SL_UL, MUL_UH_UH, MUL_UH_UL,\n            MUL_UL_UH, MUL_UL_UL, NAND,      NOR,       NXOR,      OR,\n            ORN,       ROL,       ROR,       RSUB,      RSUBC,     SUB,\n            SUBC,      XOR,       HASH,      CALL};\n  }\n\n  static std::set<OpCode> add_rrrc_op_codes() {\n    return {ADD,       ADDC,      AND,       ANDN,      ASR,       CMPB4,\n            LSL,       LSL1,      LSL1X,     LSLX,      LSR,       LSR1,\n            LSR1X,     LSRX,      MUL_SH_SH, MUL_SH_SL, MUL_SH_UH, MUL_SH_UL,\n            MUL_SL_SH, MUL_SL_SL, MUL_SL_UH, MUL_SL_UL, MUL_UH_UH, MUL_UH_UL,\n            MUL_UL_UH, MUL_UL_UL, NAND,      NOR,       NXOR,      ROL,\n            ROR,       OR,        ORN,       XOR,       HASH,      CALL};\n  }\n  static std::set<OpCode> rsub_rrrc_op_codes() { return {RSUB, RSUBC}; }\n  static std::set<OpCode> sub_rrrc_op_codes() { return {SUB, SUBC}; }\n  static std::set<OpCode> rrrc_op_codes() {\n    std::set<OpCode> add_rrrc_op_codes = Instruction::add_rrrc_op_codes();\n    std::set<OpCode> rsub_rrrc_op_codes = Instruction::rsub_rrrc_op_codes();\n    std::set<OpCode> sub_rrrc_op_codes = Instruction::sub_rrrc_op_codes();\n\n    std::set<OpCode> rrrc_op_codes = {};\n    rrrc_op_codes.insert(add_rrrc_op_codes.begin(), add_rrrc_op_codes.end());\n    rrrc_op_codes.insert(rsub_rrrc_op_codes.begin(), rsub_rrrc_op_codes.end());\n    rrrc_op_codes.insert(sub_rrrc_op_codes.begin(), sub_rrrc_op_codes.end());\n    return rrrc_op_codes;\n  }\n\n  static std::set<OpCode> add_rrrci_op_codes() { return {ADD, ADDC}; }\n  static std::set<OpCode> and_rrrci_op_codes() {\n    return {AND, ANDN, NAND, NOR, NXOR, OR, ORN, XOR, HASH};\n  }\n  static std::set<OpCode> asr_rrrci_op_codes() {\n    return {ASR, CMPB4, LSL,   LSL1, LSL1X, LSLX,\n            LSR, LSR1,  LSR1X, LSRX, ROL,   ROR};\n  }\n  static std::set<OpCode> mul_rrrci_op_codes() {\n    return {MUL_SH_SH, MUL_SH_SL, MUL_SH_UH, MUL_SH_UL, MUL_SL_SH, MUL_SL_SL,\n            MUL_SL_UH, MUL_SL_UL, MUL_UH_UH, MUL_UH_UL, MUL_UL_UH, MUL_UL_UL};\n  }\n  static std::set<OpCode> rsub_rrrci_op_codes() {\n    return {RSUB, RSUBC, SUB, SUBC};\n  }\n  static std::set<OpCode> rrrci_op_codes() {\n    std::set<OpCode> add_rrrci_op_codes = Instruction::add_rrrci_op_codes();\n    std::set<OpCode> and_rrrci_op_codes = Instruction::and_rrrci_op_codes();\n    std::set<OpCode> asr_rrrci_op_codes = Instruction::asr_rrici_op_codes();\n    std::set<OpCode> mul_rrrci_op_codes = Instruction::mul_rrrci_op_codes();\n    std::set<OpCode> rsub_rrrci_op_codes = Instruction::rsub_rrrci_op_codes();\n\n    std::set<OpCode> rrrci_op_codes = {};\n    rrrci_op_codes.insert(add_rrrci_op_codes.begin(), add_rrrci_op_codes.end());\n    rrrci_op_codes.insert(and_rrrci_op_codes.begin(), and_rrrci_op_codes.end());\n    rrrci_op_codes.insert(asr_rrrci_op_codes.begin(), asr_rrrci_op_codes.end());\n    rrrci_op_codes.insert(mul_rrrci_op_codes.begin(), mul_rrrci_op_codes.end());\n    rrrci_op_codes.insert(rsub_rrrci_op_codes.begin(),\n                          rsub_rrrci_op_codes.end());\n    return rrrci_op_codes;\n  }\n\n  static std::set<OpCode> rr_op_codes() {\n    return {CAO, CLO, CLS, CLZ, EXTSB, EXTSH, EXTUB, EXTUH, SATS, TIME_CFG};\n  }\n\n  static std::set<OpCode> rrc_op_codes() {\n    return {CAO, CLO, CLS, CLZ, EXTSB, EXTSH, EXTUB, EXTUH, SATS};\n  }\n\n  static std::set<OpCode> cao_rrci_op_codes() { return {CAO, CLO, CLS, CLZ}; }\n  static std::set<OpCode> extsb_rrci_op_codes() {\n    return {EXTSB, EXTSH, EXTUB, EXTUH, SATS};\n  }\n  static std::set<OpCode> time_cfg_rrci_op_codes() { return {TIME_CFG}; }\n  static std::set<OpCode> rrci_op_codes() {\n    std::set<OpCode> cao_rrci_op_codes = Instruction::cao_rrci_op_codes();\n    std::set<OpCode> extsb_rrci_op_codes = Instruction::extsb_rrci_op_codes();\n    std::set<OpCode> time_cfg_rrci_op_codes =\n        Instruction::time_cfg_rrci_op_codes();\n\n    std::set<OpCode> rrci_op_codes = {};\n    rrci_op_codes.insert(cao_rrci_op_codes.begin(), cao_rrci_op_codes.end());\n    rrci_op_codes.insert(extsb_rrci_op_codes.begin(),\n                         extsb_rrci_op_codes.end());\n    rrci_op_codes.insert(time_cfg_rrci_op_codes.begin(),\n                         time_cfg_rrci_op_codes.end());\n    return rrci_op_codes;\n  }\n\n  static std::set<OpCode> div_step_drdici_op_codes() { return {DIV_STEP}; }\n  static std::set<OpCode> mul_step_drdici_op_codes() { return {MUL_STEP}; }\n  static std::set<OpCode> drdici_op_codes() {\n    std::set<OpCode> div_step_drdici_op_codes =\n        Instruction::div_step_drdici_op_codes();\n    std::set<OpCode> mul_step_drdici_op_codes =\n        Instruction::mul_step_drdici_op_codes();\n\n    std::set<OpCode> drdici_op_codes = {};\n    drdici_op_codes.insert(div_step_drdici_op_codes.begin(),\n                           div_step_drdici_op_codes.end());\n    drdici_op_codes.insert(mul_step_drdici_op_codes.begin(),\n                           mul_step_drdici_op_codes.end());\n    return drdici_op_codes;\n  }\n\n  static std::set<OpCode> rrri_op_codes() {\n    return {LSL_ADD, LSL_SUB, LSR_ADD, ROL_ADD};\n  }\n  static std::set<OpCode> rrrici_op_codes() {\n    return {LSL_ADD, LSL_SUB, LSR_ADD, ROL_ADD};\n  }\n\n  static std::set<OpCode> rir_op_codes() { return {SUB, SUBC}; }\n  static std::set<OpCode> rirc_op_codes() { return {SUB, SUBC}; }\n  static std::set<OpCode> rirci_op_codes() { return {SUB, SUBC}; }\n\n  static std::set<OpCode> r_op_codes() { return {TIME}; }\n  static std::set<OpCode> rci_op_codes() { return {TIME}; }\n\n  static std::set<OpCode> ci_op_codes() { return {STOP}; }\n  static std::set<OpCode> i_op_codes() { return {FAULT}; }\n\n  static std::set<OpCode> movd_ddci_op_codes() { return {MOVD}; }\n  static std::set<OpCode> swapd_ddci_op_codes() { return {SWAPD}; }\n  static std::set<OpCode> ddci_op_codes() {\n    std::set<OpCode> movd_ddci_op_codes = Instruction::movd_ddci_op_codes();\n    std::set<OpCode> swapd_ddci_op_codes = Instruction::swapd_ddci_op_codes();\n\n    std::set<OpCode> ddci_op_codes = {};\n    ddci_op_codes.insert(movd_ddci_op_codes.begin(), movd_ddci_op_codes.end());\n    ddci_op_codes.insert(swapd_ddci_op_codes.begin(),\n                         swapd_ddci_op_codes.end());\n    return ddci_op_codes;\n  }\n\n  static std::set<OpCode> erri_op_codes() { return {LBS, LBU, LHS, LHU, LW}; }\n  static std::set<OpCode> edri_op_codes() { return {LD}; }\n\n  static std::set<OpCode> erii_op_codes() {\n    return {SB, SB_ID, SD, SD_ID, SH, SH_ID, SW, SW_ID, SD, SD_ID};\n  }\n  static std::set<OpCode> erir_op_codes() { return {SB, SH, SW}; }\n  static std::set<OpCode> erid_op_codes() { return {SD}; }\n\n  static std::set<OpCode> ldma_dma_rri_op_codes() { return {LDMA}; }\n  static std::set<OpCode> ldmai_dma_rri_op_codes() { return {LDMAI}; }\n  static std::set<OpCode> sdma_dma_rri_op_codes() { return {SDMA}; }\n  static std::set<OpCode> dma_rri_op_codes() {\n    std::set<OpCode> ldma_dma_rri_op_codes =\n        Instruction::ldma_dma_rri_op_codes();\n    std::set<OpCode> ldmai_dma_rri_op_codes =\n        Instruction::ldmai_dma_rri_op_codes();\n    std::set<OpCode> sdma_dma_rri_op_codes =\n        Instruction::sdma_dma_rri_op_codes();\n\n    std::set<OpCode> dma_rri_op_codes = {};\n    dma_rri_op_codes.insert(ldma_dma_rri_op_codes.begin(),\n                            ldma_dma_rri_op_codes.end());\n    dma_rri_op_codes.insert(ldmai_dma_rri_op_codes.begin(),\n                            ldmai_dma_rri_op_codes.end());\n    dma_rri_op_codes.insert(sdma_dma_rri_op_codes.begin(),\n                            sdma_dma_rri_op_codes.end());\n    return dma_rri_op_codes;\n  }\n\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       int64_t imm, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, int64_t imm, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, reg::SrcReg *rb);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, reg::SrcReg *rb,\n                       isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, reg::SrcReg *rb,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       int64_t imm, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       reg::SrcReg *rb);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       reg::SrcReg *rb, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       reg::SrcReg *rb, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, int64_t imm, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::SrcReg *rb);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::SrcReg *rb,\n                       isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::SrcReg *rb,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::PairReg *db, int64_t imm,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       reg::SrcReg *rb, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::SrcReg *ra,\n                       reg::SrcReg *rb, int64_t imm, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       int64_t imm, reg::SrcReg *ra);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       int64_t imm, reg::SrcReg *ra, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       int64_t imm, reg::SrcReg *ra, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                       reg::SrcReg *ra);\n  explicit Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                       reg::SrcReg *ra, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, int64_t imm,\n                       reg::SrcReg *ra, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       int64_t imm, reg::SrcReg *ra, isa::Condition condition);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       int64_t imm, reg::SrcReg *ra, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::GPReg *rc,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Condition condition,\n                       int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, reg::PairReg *dc,\n                       reg::PairReg *db, isa::Condition condition, int64_t pc);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                       reg::GPReg *rc, reg::SrcReg *ra, int64_t off);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                       reg::PairReg *dc, reg::SrcReg *ra, int64_t off);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                       reg::SrcReg *ra, int64_t off, int64_t imm);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                       reg::SrcReg *ra, int64_t off, reg::SrcReg *rb);\n  explicit Instruction(OpCode op_code, Suffix suffix, isa::Endian endian,\n                       reg::SrcReg *ra, int64_t off, reg::PairReg *db);\n\n  ~Instruction();\n\n  OpCode op_code() { return op_code_; }\n  Suffix suffix() { return suffix_; }\n\n  reg::GPReg *rc();\n  reg::SrcReg *ra();\n  reg::SrcReg *rb();\n\n  reg::PairReg *dc();\n  reg::PairReg *db();\n\n  isa::Condition condition();\n\n  abi::word::Immediate *imm();\n  abi::word::Immediate *off();\n  abi::word::Immediate *pc();\n  isa::Endian endian();\n\n  simulator::dpu::Thread *thread();\n  void set_thread(simulator::dpu::Thread *thread);\n\n protected:\n  void init_rici(reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                 int64_t pc);\n  void init_rri(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm);\n  void init_rric(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                 isa::Condition condition);\n  void init_rrici(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                  isa::Condition condition, int64_t pc);\n  void init_rrif(reg::GPReg *rc, reg::SrcReg *ra, int64_t imm,\n                 isa::Condition condition);\n  void init_rrr(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb);\n  void init_rrrc(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                 isa::Condition condition);\n  void init_rrrci(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                  isa::Condition condition, int64_t pc);\n  void init_zri(reg::SrcReg *ra, int64_t imm);\n  void init_zric(reg::SrcReg *ra, int64_t imm, isa::Condition condition);\n  void init_zrici(reg::SrcReg *ra, int64_t imm, isa::Condition condition,\n                  int64_t pc);\n  void init_zrif(reg::SrcReg *ra, int64_t imm, isa::Condition condition);\n  void init_zrr(reg::SrcReg *ra, reg::SrcReg *rb);\n  void init_zrrc(reg::SrcReg *ra, reg::SrcReg *rb, isa::Condition condition);\n  void init_zrrci(reg::SrcReg *ra, reg::SrcReg *rb, isa::Condition condition,\n                  int64_t pc);\n  void init_s_rri(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm);\n  void init_s_rric(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                   isa::Condition condition);\n  void init_s_rrici(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                    isa::Condition condition, int64_t pc);\n  void init_s_rrif(reg::PairReg *dc, reg::SrcReg *ra, int64_t imm,\n                   isa::Condition condition);\n  void init_s_rrr(reg::PairReg *dc, reg::SrcReg *ra, reg::SrcReg *rb);\n  void init_s_rrrc(reg::PairReg *dc, reg::SrcReg *ra, reg::SrcReg *rb,\n                   isa::Condition condition);\n  void init_s_rrrci(reg::PairReg *dc, reg::SrcReg *ra, reg::SrcReg *rb,\n                    isa::Condition condition, int64_t pc);\n  void init_rr(reg::GPReg *rc, reg::SrcReg *ra);\n  void init_rrc(reg::GPReg *rc, reg::SrcReg *ra, isa::Condition condition);\n  void init_rrci(reg::GPReg *rc, reg::SrcReg *ra, isa::Condition condition,\n                 int64_t pc);\n  void init_zr(reg::SrcReg *ra);\n  void init_zrc(reg::SrcReg *ra, isa::Condition condition);\n  void init_zrci(reg::SrcReg *ra, isa::Condition condition, int64_t pc);\n  void init_s_rr(reg::PairReg *dc, reg::SrcReg *ra);\n  void init_s_rrc(reg::PairReg *dc, reg::SrcReg *ra, isa::Condition condition);\n  void init_s_rrci(reg::PairReg *dc, reg::SrcReg *ra, isa::Condition condition,\n                   int64_t pc);\n  void init_drdici(reg::PairReg *dc, reg::SrcReg *ra, reg::PairReg *db,\n                   int64_t imm, isa::Condition condition, int64_t pc);\n  void init_rrri(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm);\n  void init_rrrici(reg::GPReg *rc, reg::SrcReg *ra, reg::SrcReg *rb,\n                   int64_t imm, isa::Condition condition, int64_t pc);\n  void init_zrri(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm);\n  void init_zrrici(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm,\n                   isa::Condition condition, int64_t pc);\n  void init_s_rrri(reg::PairReg *dc, reg::SrcReg *ra, reg::SrcReg *rb,\n                   int64_t imm);\n  void init_s_rrrici(reg::PairReg *dc, reg::SrcReg *ra, reg::SrcReg *rb,\n                     int64_t imm, isa::Condition condition, int64_t pc);\n  void init_rir(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra);\n  void init_rirc(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra,\n                 isa::Condition condition);\n  void init_rirci(reg::GPReg *rc, int64_t imm, reg::SrcReg *ra,\n                  isa::Condition condition, int64_t pc);\n  void init_zir(int64_t imm, reg::SrcReg *ra);\n  void init_zirc(int64_t imm, reg::SrcReg *ra, isa::Condition condition);\n  void init_zirci(int64_t imm, reg::SrcReg *ra, isa::Condition condition,\n                  int64_t pc);\n  void init_s_rirc(reg::PairReg *dc, int64_t imm, reg::SrcReg *ra,\n                   isa::Condition condition);\n  void init_s_rirci(reg::PairReg *dc, int64_t imm, reg::SrcReg *ra,\n                    isa::Condition condition, int64_t pc);\n  void init_r(reg::GPReg *rc);\n  void init_rci(reg::GPReg *rc, isa::Condition condition, int64_t pc);\n  void init_z();\n  void init_zci(isa::Condition condition, int64_t pc);\n  void init_s_r(reg::PairReg *dc);\n  void init_s_rci(reg::PairReg *dc, isa::Condition condition, int64_t pc);\n  void init_ci(isa::Condition condition, int64_t pc);\n  void init_i(int64_t imm);\n  void init_ddci(reg::PairReg *dc, reg::PairReg *db, isa::Condition condition,\n                 int64_t pc);\n  void init_erri(isa::Endian endian, reg::GPReg *rc, reg::SrcReg *ra,\n                 int64_t off);\n  void init_s_erri(isa::Endian endian, reg::PairReg *dc, reg::SrcReg *ra,\n                   int64_t off);\n  void init_edri(isa::Endian endian, reg::PairReg *dc, reg::SrcReg *ra,\n                 int64_t off);\n  void init_erii(isa::Endian endian, reg::SrcReg *ra, int64_t off, int64_t imm);\n  void init_erir(isa::Endian endian, reg::SrcReg *ra, int64_t off,\n                 reg::SrcReg *rb);\n  void init_erid(isa::Endian endian, reg::SrcReg *ra, int64_t off,\n                 reg::PairReg *db);\n  void init_dma_rri(reg::SrcReg *ra, reg::SrcReg *rb, int64_t imm);\n\n private:\n  OpCode op_code_;\n  Suffix suffix_;\n\n  reg::GPReg *rc_;\n  reg::SrcReg *ra_;\n  reg::SrcReg *rb_;\n\n  reg::PairReg *dc_;\n  reg::PairReg *db_;\n\n  isa::Condition *condition_;\n\n  abi::word::Immediate *imm_;\n  abi::word::Immediate *off_;\n  abi::word::Immediate *pc_;\n\n  isa::Endian *endian_;\n\n  simulator::dpu::Thread *thread_;\n};\n\n}  // namespace upmem_sim::abi::instruction\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/instruction/op_code.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_INSTRUCTION_OP_CODE_H_\n#define UPMEM_SIM_ABI_ISA_INSTRUCTION_OP_CODE_H_\n\nnamespace upmem_sim::abi::instruction {\n\nenum OpCode {\n  ACQUIRE,\n  RELEASE,\n\n  ADD,\n  ADDC,\n  AND,\n  ANDN,\n  ASR,\n  CAO,\n  CLO,\n  CLS,\n  CLZ,\n  CMPB4,\n  DIV_STEP,\n  EXTSB,\n  EXTSH,\n  EXTUB,\n  EXTUH,\n  LSL,\n  LSL_ADD,\n  LSL_SUB,\n  LSL1,\n  LSL1X,\n  LSLX,\n  LSR,\n  LSR_ADD,\n  LSR1,\n  LSR1X,\n  LSRX,\n  MUL_SH_SH,\n  MUL_SH_SL,\n  MUL_SH_UH,\n  MUL_SH_UL,\n  MUL_SL_SH,\n  MUL_SL_SL,\n  MUL_SL_UH,\n  MUL_SL_UL,\n  MUL_STEP,\n  MUL_UH_UH,\n  MUL_UH_UL,\n  MUL_UL_UH,\n  MUL_UL_UL,\n  NAND,\n  NOR,\n  NXOR,\n  OR,\n  ORN,\n  ROL,\n  ROL_ADD,\n  ROR,\n  RSUB,\n  RSUBC,\n  SUB,\n  SUBC,\n  XOR,\n\n  BOOT,\n  RESUME,\n  STOP,\n\n  CALL,\n\n  FAULT,\n  NOP,\n  SATS,\n  MOVD,\n  SWAPD,\n\n  HASH,\n  TIME,\n  TIME_CFG,\n\n  LBS,\n  LBU,\n  LD,\n  LHS,\n  LHU,\n  LW,\n\n  SB,\n  SB_ID,\n  SD,\n  SD_ID,\n  SH,\n  SH_ID,\n  SW,\n  SW_ID,\n\n  LDMA,\n  LDMAI,\n  SDMA\n};\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/instruction/suffix.h",
    "content": "#ifndef UPMEM_SIM_ISA_SUFFIX_H_\n#define UPMEM_SIM_ISA_SUFFIX_H_\n\nnamespace upmem_sim::abi::instruction {\n\nenum Suffix {\n  RICI,\n\n  RRI,\n  RRIC,\n  RRICI,\n  RRIF,\n  RRR,\n  RRRC,\n  RRRCI,\n\n  ZRI,\n  ZRIC,\n  ZRICI,\n  ZRIF,\n  ZRR,\n  ZRRC,\n  ZRRCI,\n\n  S_RRI,\n  S_RRIC,\n  S_RRICI,\n  S_RRIF,\n  S_RRR,\n  S_RRRC,\n  S_RRRCI,\n\n  U_RRI,\n  U_RRIC,\n  U_RRICI,\n  U_RRIF,\n  U_RRR,\n  U_RRRC,\n  U_RRRCI,\n\n  RR,\n  RRC,\n  RRCI,\n\n  ZR,\n  ZRC,\n  ZRCI,\n\n  S_RR,\n  S_RRC,\n  S_RRCI,\n\n  U_RR,\n  U_RRC,\n  U_RRCI,\n\n  DRDICI,\n\n  RRRI,\n  RRRICI,\n\n  ZRRI,\n  ZRRICI,\n\n  S_RRRI,\n  S_RRRICI,\n\n  U_RRRI,\n  U_RRRICI,\n\n  RIR,\n  RIRC,\n  RIRCI,\n\n  ZIR,\n  ZIRC,\n  ZIRCI,\n\n  S_RIRC,\n  S_RIRCI,\n\n  U_RIRC,\n  U_RIRCI,\n\n  R,\n  RCI,\n\n  Z,\n  ZCI,\n\n  S_R,\n  S_RCI,\n\n  U_R,\n  U_RCI,\n\n  CI,\n  I,\n\n  DDCI,\n\n  ERRI,\n\n  S_ERRI,\n  U_ERRI,\n\n  EDRI,\n\n  ERII,\n  ERIR,\n  ERID,\n\n  DMA_RRI\n};\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/isa/condition.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_INSTRUCTION_CONDITION_H_\n#define UPMEM_SIM_ABI_ISA_INSTRUCTION_CONDITION_H_\n\nnamespace upmem_sim::abi::isa {\n\nenum Condition {\n  TRUE,\n  FALSE,\n\n  Z,\n  NZ,\n\n  E,\n  O,\n\n  PL,\n  MI,\n\n  OV,\n  NOV,\n\n  C,\n  NC,\n\n  SZ,\n  SNZ,\n\n  SPL,\n  SMI,\n\n  SO,\n  SE,\n\n  NC5,\n  NC6,\n  NC7,\n  NC8,\n  NC9,\n  NC10,\n  NC11,\n  NC12,\n  NC13,\n  NC14,\n\n  MAX,\n  NMAX,\n\n  SH32,\n  NSH32,\n\n  EQ,\n  NEQ,\n\n  LTU,\n  LEU,\n  GTU,\n  GEU,\n\n  LTS,\n  LES,\n  GTS,\n  GES,\n\n  XZ,\n  XNZ,\n\n  XLEU,\n  XGTU,\n\n  XLES,\n  XGTS,\n\n  SMALL,\n  LARGE\n};\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/isa/endian.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_INSTRUCTION_ENDIAN_H_\n#define UPMEM_SIM_ABI_ISA_INSTRUCTION_ENDIAN_H_\n\nnamespace upmem_sim::abi::isa {\n\nenum Endian { LITTLE, BIG };\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/isa/exception.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_EXCEPTION_H_\n#define UPMEM_SIM_ABI_ISA_EXCEPTION_H_\n\nnamespace upmem_sim::abi::isa {\n\nenum Exception {\n  MEMORY_FAULT,\n  DMA_FAULT,\n  HEAP_FULL,\n  DIVISION_BY_ZERO,\n  ASSERT,\n  HALT,\n  PRINT_OVERFLOW,\n  ALREADY_PROFILING,\n  NOT_PROFILING\n};\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/isa/flag.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_FLAG_H_\n#define UPMEM_SIM_ABI_ISA_FLAG_H_\n\nnamespace upmem_sim::abi::isa {\n\nenum Flag { ZERO, CARRY };\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/gp_reg.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_REG_GP_REG_H_\n#define UPMEM_SIM_ABI_ISA_REG_GP_REG_H_\n\n#include <cassert>\n#include <string>\n\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::abi::reg {\n\nclass GPReg {\n public:\n  explicit GPReg(RegIndex index) : index_(index) {\n    assert(0 <= index and index < util::ConfigLoader::num_gp_registers());\n  }\n  ~GPReg() = default;\n\n  RegIndex index() { return index_; }\n\n private:\n  RegIndex index_;\n};\n\n}  // namespace upmem_sim::abi::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/pair_reg.cc",
    "content": "#include \"pair_reg.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::abi::reg {\n\nPairReg::PairReg(RegIndex index) {\n  assert(index % 2 == 0);\n\n  even_reg_ = new GPReg(index);\n  odd_reg_ = new GPReg(index + 1);\n}\n\nPairReg::~PairReg() {\n  delete even_reg_;\n  delete odd_reg_;\n}\n\n}  // namespace upmem_sim::abi::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/pair_reg.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_REG_PAIR_REG_H_\n#define UPMEM_SIM_ABI_ISA_REG_PAIR_REG_H_\n\n#include <cassert>\n\n#include \"gp_reg.h\"\n\nnamespace upmem_sim::abi::reg {\n\nclass PairReg {\n public:\n  explicit PairReg(RegIndex index);\n  ~PairReg();\n\n  GPReg *even_reg() { return even_reg_; }\n  GPReg *odd_reg() { return odd_reg_; }\n\n private:\n  GPReg *even_reg_;\n  GPReg *odd_reg_;\n};\n\n}  // namespace upmem_sim::abi::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/sp_reg.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_REG_SP_REG_H_\n#define UPMEM_SIM_ABI_ISA_REG_SP_REG_H_\n\nnamespace upmem_sim::abi::reg {\n\nenum SPReg { ZERO, ONE, LNEG, MNEG, ID, ID2, ID4, ID8 };\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/src_reg.cc",
    "content": "#include \"src_reg.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::abi::reg {\n\nSrcReg::~SrcReg() {\n  delete gp_reg_;\n  delete sp_reg_;\n}\n\nGPReg *SrcReg::gp_reg() {\n  assert(is_gp_reg());\n  return gp_reg_;\n}\n\nSPReg *SrcReg::sp_reg() {\n  assert(is_sp_reg());\n  return sp_reg_;\n}\n\n}  // namespace upmem_sim::abi::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/reg/src_reg.h",
    "content": "#ifndef UPMEM_SIM_ABI_ISA_REG_SRC_REG_H_\n#define UPMEM_SIM_ABI_ISA_REG_SRC_REG_H_\n\n#include \"gp_reg.h\"\n#include \"sp_reg.h\"\n\nnamespace upmem_sim::abi::reg {\n\nclass SrcReg {\n public:\n  explicit SrcReg(GPReg *reg)\n      : gp_reg_(new GPReg(reg->index())), sp_reg_(nullptr) {}\n  explicit SrcReg(SPReg *reg) : gp_reg_(nullptr), sp_reg_(new SPReg(*reg)) {}\n  ~SrcReg();\n\n  bool is_gp_reg() { return gp_reg_ != nullptr; }\n  bool is_sp_reg() { return sp_reg_ != nullptr; }\n\n  GPReg *gp_reg();\n  SPReg *sp_reg();\n\n private:\n  GPReg *gp_reg_;\n  SPReg *sp_reg_;\n};\n\n}  // namespace upmem_sim::abi::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/_base_word.cc",
    "content": "#include \"abi/word/_base_word.h\"\n\n#include <algorithm>\n#include <cassert>\n#include <cmath>\n\nnamespace upmem_sim::abi::word {\n\n_BaseWord::_BaseWord(int width) {\n  assert(width > 0);\n  bits_.resize(width);\n}\n\nint64_t _BaseWord::bit_slice(Representation representation, int begin,\n                             int end) {\n  assert(0 <= begin and begin < end and end <= width());\n  assert(end - begin < 64);\n\n  int slice_width = end - begin;\n  int64_t value = 0;\n  for (int i = 0; i < slice_width; i++) {\n    if (bit(begin + i)) {\n      if (representation == SIGNED and i == slice_width - 1) {\n        value -= static_cast<int64_t>(pow(2, i));\n      } else {\n        value += static_cast<int64_t>(pow(2, i));\n      }\n    }\n  }\n  return value;\n}\n\nvoid _BaseWord::set_bit_slice(int begin, int end, int64_t value) {\n  assert(0 <= begin and begin < end and end <= width());\n  assert(end - begin < 64);\n\n  if (value >= 0) {\n    set_positive_bit_slice(begin, end, value);\n  } else {\n    set_negative_bit_slice(begin, end, value);\n  }\n}\n\nencoder::ByteStream *_BaseWord::to_byte_stream() {\n  int num_bytes = ceil(width() / 8.0);\n  auto byte_stream = new encoder::ByteStream();\n  for (int i = 0; i < num_bytes; i++) {\n    int begin = 8 * i;\n    int end = std::min(begin + 8, width());\n\n    auto byte = static_cast<int>(bit_slice(UNSIGNED, begin, end));\n    byte_stream->append(byte);\n  }\n  return byte_stream;\n}\n\nvoid _BaseWord::from_byte_stream(encoder::ByteStream *byte_stream) {\n  for (int i = 0; i < byte_stream->size(); i++) {\n    int begin = 8 * i;\n    int end = std::min(begin + 8, width());\n\n    int64_t byte = byte_stream->byte(i);\n    set_bit_slice(begin, end, byte);\n  }\n}\n\nvoid _BaseWord::set_positive_bit_slice(int begin, int end, int64_t value) {\n  assert(0 <= begin and begin < end and end <= width());\n  assert(value >= 0);\n\n  int slice_width = end - begin;\n  for (int i = 0; i < slice_width; i++) {\n    if (value % 2) {\n      set_bit(begin + i);\n    } else {\n      clear_bit(begin + i);\n    }\n\n    value /= 2;\n  }\n\n  assert(value == 0);\n}\n\nvoid _BaseWord::set_negative_bit_slice(int begin, int end, int64_t value) {\n  assert(0 <= begin and begin < end and end <= width());\n  assert(value < 0);\n\n  set_bit(end - 1);\n\n  if (begin + 1 < end) {\n    int slice_width = end - begin;\n    value += static_cast<int64_t>(pow(2, slice_width - 1));\n    set_positive_bit_slice(begin, end - 1, value);\n  }\n}\n\n}  // namespace upmem_sim::abi::word\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/_base_word.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD__BASE_WORD_H_\n#define UPMEM_SIM_ABI_WORD__BASE_WORD_H_\n\n#include <cstdint>\n#include <vector>\n\n#include \"abi/word/representation.h\"\n#include \"encoder/byte_stream.h\"\n#include \"main.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass _BaseWord {\n public:\n  explicit _BaseWord(int width);\n  ~_BaseWord() = default;\n\n  int width() { return static_cast<int>(bits_.size()); }\n  Address size() { return width() / 8; }\n\n  bool sign_bit() { return bit(width() - 1); }\n  bool bit(int index) { return bits_[index]; }\n  void set_bit(int index) { bits_[index] = true; }\n  void clear_bit(int index) { bits_[index] = false; }\n\n  int64_t bit_slice(Representation representation, int begin, int end);\n  void set_bit_slice(int begin, int end, int64_t value);\n\n  int64_t value(Representation representation) {\n    return bit_slice(representation, 0, width());\n  }\n  void set_value(int64_t value) { set_bit_slice(0, width(), value); }\n\n  encoder::ByteStream *to_byte_stream();\n  void from_byte_stream(encoder::ByteStream *byte_stream);\n\n protected:\n  void set_positive_bit_slice(int begin, int end, int64_t value);\n  void set_negative_bit_slice(int begin, int end, int64_t value);\n\n private:\n  std::vector<bool> bits_;\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/data_address_word.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_DATA_ADDRESS_WORD_H_\n#define UPMEM_SIM_ABI_WORD_DATA_ADDRESS_WORD_H_\n\n#include \"abi/word/_base_word.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass DataAddressWord : public _BaseWord {\n public:\n  DataAddressWord() : _BaseWord(util::ConfigLoader::mram_address_width()) {\n    assert(util::ConfigLoader::atomic_address_width() ==\n               util::ConfigLoader::wram_address_width() and\n           util::ConfigLoader::atomic_address_width() ==\n               util::ConfigLoader::mram_address_width());\n  }\n  ~DataAddressWord() = default;\n\n  Address address() { return value(UNSIGNED); }\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/data_word.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_DATA_WORD_H_\n#define UPMEM_SIM_ABI_WORD_DATA_WORD_H_\n\n#include \"abi/word/_base_word.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass DataWord : public _BaseWord {\n public:\n  DataWord() : _BaseWord(util::ConfigLoader::mram_data_width()) {\n    assert(util::ConfigLoader::atomic_data_width() ==\n               util::ConfigLoader::wram_data_width() and\n           util::ConfigLoader::atomic_data_width() ==\n               util::ConfigLoader::mram_data_width());\n  }\n  ~DataWord() = default;\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/immediate.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_IMMEDIATE_H_\n#define UPMEM_SIM_ABI_WORD_IMMEDIATE_H_\n\n#include <cstdint>\n\n#include \"abi/word/_base_word.h\"\n#include \"abi/word/representation.h\"\n#include \"encoder/byte_stream.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass Immediate {\n public:\n  Immediate(Representation representation, int width, int64_t value)\n      : representation_(representation), word_(new _BaseWord(width)) {\n    word_->set_value(value);\n  }\n  ~Immediate() { delete word_; }\n\n  Representation representation() { return representation_; }\n  int width() { return word_->width(); }\n\n  bool bit(int index) { return word_->bit(index); }\n  int64_t bit_slice(int begin, int end) {\n    return word_->bit_slice(representation_, begin, end);\n  }\n  int64_t value() { return word_->value(representation_); }\n  encoder::ByteStream *to_byte_stream() { return word_->to_byte_stream(); }\n\n private:\n  Representation representation_;\n  _BaseWord *word_;\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/instruction_address_word.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_INSTRUCTION_ADDRESS_WORD_H_\n#define UPMEM_SIM_ABI_WORD_INSTRUCTION_ADDRESS_WORD_H_\n\n#include \"abi/word/_base_word.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass InstructionAddressWord : public _BaseWord {\n public:\n  InstructionAddressWord()\n      : _BaseWord(util::ConfigLoader::iram_address_width()) {}\n  ~InstructionAddressWord() = default;\n\n  Address address() { return value(UNSIGNED); }\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/instruction_word.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_INSTRUCTION_WORD_H_\n#define UPMEM_SIM_ABI_WORD_INSTRUCTION_WORD_H_\n\n#include \"abi/word/_base_word.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::abi::word {\n\nclass InstructionWord : public _BaseWord {\n public:\n  InstructionWord() : _BaseWord(util::ConfigLoader::iram_data_width()) {}\n  ~InstructionWord() = default;\n};\n\n}  // namespace upmem_sim::abi::word\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/abi/word/representation.h",
    "content": "#ifndef UPMEM_SIM_ABI_WORD_REPRESENTATION_H_\n#define UPMEM_SIM_ABI_WORD_REPRESENTATION_H_\n\nnamespace upmem_sim::abi::word {\n\nenum Representation { UNSIGNED, SIGNED };\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/condition_converter.cc",
    "content": "#include \"converter/condition_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string ConditionConverter::to_string(abi::isa::Condition condition) {\n  if (condition == abi::isa::TRUE) {\n    return \"true\";\n  } else if (condition == abi::isa::FALSE) {\n    return \"false\";\n  } else if (condition == abi::isa::Z) {\n    return \"z\";\n  } else if (condition == abi::isa::NZ) {\n    return \"nz\";\n  } else if (condition == abi::isa::E) {\n    return \"e\";\n  } else if (condition == abi::isa::O) {\n    return \"o\";\n  } else if (condition == abi::isa::PL) {\n    return \"pl\";\n  } else if (condition == abi::isa::MI) {\n    return \"mi\";\n  } else if (condition == abi::isa::OV) {\n    return \"ov\";\n  } else if (condition == abi::isa::NOV) {\n    return \"nov\";\n  } else if (condition == abi::isa::C) {\n    return \"c\";\n  } else if (condition == abi::isa::NC) {\n    return \"nc\";\n  } else if (condition == abi::isa::SZ) {\n    return \"sz\";\n  } else if (condition == abi::isa::SNZ) {\n    return \"snz\";\n  } else if (condition == abi::isa::SPL) {\n    return \"spl\";\n  } else if (condition == abi::isa::SMI) {\n    return \"smi\";\n  } else if (condition == abi::isa::SO) {\n    return \"so\";\n  } else if (condition == abi::isa::SE) {\n    return \"se\";\n  } else if (condition == abi::isa::NC5) {\n    return \"nc5\";\n  } else if (condition == abi::isa::NC6) {\n    return \"nc6\";\n  } else if (condition == abi::isa::NC7) {\n    return \"nc7\";\n  } else if (condition == abi::isa::NC8) {\n    return \"nc8\";\n  } else if (condition == abi::isa::NC9) {\n    return \"nc9\";\n  } else if (condition == abi::isa::NC10) {\n    return \"nc10\";\n  } else if (condition == abi::isa::NC11) {\n    return \"nc11\";\n  } else if (condition == abi::isa::NC12) {\n    return \"nc12\";\n  } else if (condition == abi::isa::NC13) {\n    return \"nc13\";\n  } else if (condition == abi::isa::NC14) {\n    return \"nc14\";\n  } else if (condition == abi::isa::MAX) {\n    return \"max\";\n  } else if (condition == abi::isa::NMAX) {\n    return \"nmax\";\n  } else if (condition == abi::isa::SH32) {\n    return \"sh32\";\n  } else if (condition == abi::isa::NSH32) {\n    return \"nsh32\";\n  } else if (condition == abi::isa::EQ) {\n    return \"eq\";\n  } else if (condition == abi::isa::NEQ) {\n    return \"neq\";\n  } else if (condition == abi::isa::LTU) {\n    return \"ltu\";\n  } else if (condition == abi::isa::LEU) {\n    return \"leu\";\n  } else if (condition == abi::isa::GTU) {\n    return \"gtu\";\n  } else if (condition == abi::isa::GEU) {\n    return \"geu\";\n  } else if (condition == abi::isa::LTS) {\n    return \"lts\";\n  } else if (condition == abi::isa::LES) {\n    return \"les\";\n  } else if (condition == abi::isa::GTS) {\n    return \"gts\";\n  } else if (condition == abi::isa::GES) {\n    return \"ges\";\n  } else if (condition == abi::isa::XZ) {\n    return \"xz\";\n  } else if (condition == abi::isa::XNZ) {\n    return \"xnz\";\n  } else if (condition == abi::isa::XLEU) {\n    return \"xleu\";\n  } else if (condition == abi::isa::XGTU) {\n    return \"xgtu\";\n  } else if (condition == abi::isa::XLES) {\n    return \"xles\";\n  } else if (condition == abi::isa::XGTS) {\n    return \"xgts\";\n  } else if (condition == abi::isa::SMALL) {\n    return \"small\";\n  } else if (condition == abi::isa::LARGE) {\n    return \"large\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/condition_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_CONDITION_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_CONDITION_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::converter {\n\nclass ConditionConverter {\n public:\n  static std::string to_string(abi::isa::Condition condition);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/endian_converter.cc",
    "content": "#include \"converter/endian_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string EndianConverter::to_string(abi::isa::Endian endian) {\n  if (endian == abi::isa::LITTLE) {\n    return \"!little\";\n  } else if (endian == abi::isa::BIG) {\n    return \"!big\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/endian_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_ENDIAN_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_ENDIAN_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/isa/endian.h\"\n\nnamespace upmem_sim::converter {\n\nclass EndianConverter {\n public:\n  static std::string to_string(abi::isa::Endian endian);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/flag_converter.cc",
    "content": "#include \"converter/flag_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string FlagConverter::to_string(abi::isa::Flag flag) {\n  if (flag == abi::isa::ZERO) {\n    return \"zero\";\n  } else if (flag == abi::isa::CARRY) {\n    return \"carry\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/flag_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_FLAG_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_FLAG_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/isa/flag.h\"\n\nnamespace upmem_sim::converter {\n\nclass FlagConverter {\n public:\n  static std::string to_string(abi::isa::Flag flag);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/instruction_converter.cc",
    "content": "#include \"converter/instruction_converter.h\"\n\n#include <sstream>\n\n#include \"converter/condition_converter.h\"\n#include \"converter/endian_converter.h\"\n#include \"converter/op_code_converter.h\"\n#include \"converter/reg_converter.h\"\n#include \"converter/suffix_converter.h\"\n\nnamespace upmem_sim::converter {\n\nstd::string InstructionConverter::to_string(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n\n  ss << \"[\" << instruction->thread()->id() << \"] \";\n  ss << OpCodeConverter::to_string(instruction->op_code()) << \", \";\n  ss << SuffixConverter::to_string(instruction->suffix()) << \", \";\n\n  abi::instruction::Suffix suffix = instruction->suffix();\n  if (suffix == abi::instruction::RICI) {\n    ss << to_string_rici(instruction);\n  } else if (suffix == abi::instruction::RRI) {\n    ss << to_string_rri(instruction);\n  } else if (suffix == abi::instruction::RRIC) {\n    ss << to_string_rric(instruction);\n  } else if (suffix == abi::instruction::RRICI) {\n    ss << to_string_rrici(instruction);\n  } else if (suffix == abi::instruction::RRIF) {\n    ss << to_string_rrif(instruction);\n  } else if (suffix == abi::instruction::RRR) {\n    ss << to_string_rrr(instruction);\n  } else if (suffix == abi::instruction::RRRC) {\n    ss << to_string_rrrc(instruction);\n  } else if (suffix == abi::instruction::RRRCI) {\n    ss << to_string_rrrci(instruction);\n  } else if (suffix == abi::instruction::ZRI) {\n    ss << to_string_zri(instruction);\n  } else if (suffix == abi::instruction::ZRIC) {\n    ss << to_string_zric(instruction);\n  } else if (suffix == abi::instruction::ZRICI) {\n    ss << to_string_zrici(instruction);\n  } else if (suffix == abi::instruction::ZRIF) {\n    ss << to_string_zrif(instruction);\n  } else if (suffix == abi::instruction::ZRR) {\n    ss << to_string_zrr(instruction);\n  } else if (suffix == abi::instruction::ZRRC) {\n    ss << to_string_zrrc(instruction);\n  } else if (suffix == abi::instruction::ZRRCI) {\n    ss << to_string_zrrci(instruction);\n  } else if (suffix == abi::instruction::S_RRI or\n             suffix == abi::instruction::U_RRI) {\n    ss << to_string_s_rri(instruction);\n  } else if (suffix == abi::instruction::S_RRIC or\n             suffix == abi::instruction::U_RRIC) {\n    ss << to_string_s_rric(instruction);\n  } else if (suffix == abi::instruction::S_RRICI or\n             suffix == abi::instruction::U_RRICI) {\n    ss << to_string_s_rrici(instruction);\n  } else if (suffix == abi::instruction::S_RRIF or\n             suffix == abi::instruction::U_RRIF) {\n    ss << to_string_s_rrif(instruction);\n  } else if (suffix == abi::instruction::S_RRR or\n             suffix == abi::instruction::U_RRR) {\n    ss << to_string_s_rrr(instruction);\n  } else if (suffix == abi::instruction::S_RRRC or\n             suffix == abi::instruction::U_RRRC) {\n    ss << to_string_s_rrrc(instruction);\n  } else if (suffix == abi::instruction::S_RRRCI or\n             suffix == abi::instruction::U_RRRCI) {\n    ss << to_string_s_rrrci(instruction);\n  } else if (suffix == abi::instruction::RR) {\n    ss << to_string_rr(instruction);\n  } else if (suffix == abi::instruction::RRC) {\n    ss << to_string_rrc(instruction);\n  } else if (suffix == abi::instruction::RRCI) {\n    ss << to_string_rrci(instruction);\n  } else if (suffix == abi::instruction::ZR) {\n    ss << to_string_zr(instruction);\n  } else if (suffix == abi::instruction::ZRC) {\n    ss << to_string_zrc(instruction);\n  } else if (suffix == abi::instruction::ZRCI) {\n    ss << to_string_zrci(instruction);\n  } else if (suffix == abi::instruction::S_RR or\n             suffix == abi::instruction::U_RR) {\n    ss << to_string_s_rr(instruction);\n  } else if (suffix == abi::instruction::S_RRC or\n             suffix == abi::instruction::U_RRC) {\n    ss << to_string_s_rrc(instruction);\n  } else if (suffix == abi::instruction::S_RRCI or\n             suffix == abi::instruction::U_RRCI) {\n    ss << to_string_s_rrci(instruction);\n  } else if (suffix == abi::instruction::DRDICI) {\n    ss << to_string_drdici(instruction);\n  } else if (suffix == abi::instruction::RRRI) {\n    ss << to_string_rrri(instruction);\n  } else if (suffix == abi::instruction::RRRICI) {\n    ss << to_string_rrrici(instruction);\n  } else if (suffix == abi::instruction::ZRRI) {\n    ss << to_string_zrri(instruction);\n  } else if (suffix == abi::instruction::ZRRICI) {\n    ss << to_string_zrrici(instruction);\n  } else if (suffix == abi::instruction::S_RRRI or\n             suffix == abi::instruction::U_RRRI) {\n    ss << to_string_s_rrri(instruction);\n  } else if (suffix == abi::instruction::S_RRRICI or\n             suffix == abi::instruction::U_RRRICI) {\n    ss << to_string_s_rrici(instruction);\n  } else if (suffix == abi::instruction::RIR) {\n    ss << to_string_rir(instruction);\n  } else if (suffix == abi::instruction::RIRC) {\n    ss << to_string_rirc(instruction);\n  } else if (suffix == abi::instruction::RIRCI) {\n    ss << to_string_rirci(instruction);\n  } else if (suffix == abi::instruction::ZIR) {\n    ss << to_string_zir(instruction);\n  } else if (suffix == abi::instruction::ZIRC) {\n    ss << to_string_zirc(instruction);\n  } else if (suffix == abi::instruction::ZIRCI) {\n    ss << to_string_zirci(instruction);\n  } else if (suffix == abi::instruction::S_RIRC or\n             suffix == abi::instruction::U_RIRC) {\n    ss << to_string_rirc(instruction);\n  } else if (suffix == abi::instruction::S_RIRCI or\n             suffix == abi::instruction::U_RIRCI) {\n    ss << to_string_rirci(instruction);\n  } else if (suffix == abi::instruction::R) {\n    ss << to_string_r(instruction);\n  } else if (suffix == abi::instruction::RCI) {\n    ss << to_string_rci(instruction);\n  } else if (suffix == abi::instruction::Z) {\n    ss << to_string_z(instruction);\n  } else if (suffix == abi::instruction::ZCI) {\n    ss << to_string_zci(instruction);\n  } else if (suffix == abi::instruction::S_R or\n             suffix == abi::instruction::U_R) {\n    ss << to_string_s_r(instruction);\n  } else if (suffix == abi::instruction::S_RCI or\n             suffix == abi::instruction::U_RCI) {\n    ss << to_string_s_rci(instruction);\n  } else if (suffix == abi::instruction::CI) {\n    ss << to_string_ci(instruction);\n  } else if (suffix == abi::instruction::I) {\n    ss << to_string_i(instruction);\n  } else if (suffix == abi::instruction::DDCI) {\n    ss << to_string_ddci(instruction);\n  } else if (suffix == abi::instruction::ERRI) {\n    ss << to_string_erri(instruction);\n  } else if (suffix == abi::instruction::S_ERRI or\n             suffix == abi::instruction::U_ERRI) {\n    ss << to_string_s_erri(instruction);\n  } else if (suffix == abi::instruction::EDRI) {\n    ss << to_string_edri(instruction);\n  } else if (suffix == abi::instruction::ERII) {\n    ss << to_string_erii(instruction);\n  } else if (suffix == abi::instruction::ERIR) {\n    ss << to_string_erir(instruction);\n  } else if (suffix == abi::instruction::ERID) {\n    ss << to_string_erid(instruction);\n  } else if (suffix == abi::instruction::DMA_RRI) {\n    ss << to_string_dma_rri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rric(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrif(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zric(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrif(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rric(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrif(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rr(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_drdici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->db()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rrrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zrrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rrrici(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rir(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rirc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rirci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zir(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zirc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zirci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rirc(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rirci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << instruction->imm()->value() << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_r(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_rci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_z(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_zci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_r(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_rci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_ci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_i(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_ddci(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->db()) << \", \";\n  ss << ConditionConverter::to_string(instruction->condition()) << \", \";\n  ss << instruction->pc()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_erri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->rc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_s_erri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_edri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->dc()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_erii(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value() << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_erir(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value() << \", \";\n  ss << RegConverter::to_string(instruction->rb());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_erid(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << EndianConverter::to_string(instruction->endian()) << \", \";\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << instruction->off()->value() << \", \";\n  ss << RegConverter::to_string(instruction->db());\n  return ss.str();\n}\n\nstd::string InstructionConverter::to_string_dma_rri(\n    abi::instruction::Instruction *instruction) {\n  std::stringstream ss;\n  ss << RegConverter::to_string(instruction->ra()) << \", \";\n  ss << RegConverter::to_string(instruction->rb()) << \", \";\n  ss << instruction->imm()->value();\n  return ss.str();\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/instruction_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_INSTRUCTION_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_INSTRUCTION_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/instruction/instruction.h\"\n\nnamespace upmem_sim::converter {\n\nclass InstructionConverter {\n public:\n  static std::string to_string(abi::instruction::Instruction *instruction);\n\n protected:\n  static std::string to_string_rici(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_rri(abi::instruction::Instruction *instruction);\n  static std::string to_string_rric(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrici(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_rrif(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrr(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrrc(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrrci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_zri(abi::instruction::Instruction *instruction);\n  static std::string to_string_zric(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrici(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_zrif(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrr(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrrc(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrrci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_rri(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rric(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrici(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrif(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrr(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrrc(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrrci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_rr(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrc(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrci(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_zr(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrc(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrci(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_rr(abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrc(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_drdici(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_rrri(abi::instruction::Instruction *instruction);\n  static std::string to_string_rrrici(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_zrri(abi::instruction::Instruction *instruction);\n  static std::string to_string_zrrici(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_rrri(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rrrici(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_rir(abi::instruction::Instruction *instruction);\n  static std::string to_string_rirc(abi::instruction::Instruction *instruction);\n  static std::string to_string_rirci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_zir(abi::instruction::Instruction *instruction);\n  static std::string to_string_zirc(abi::instruction::Instruction *instruction);\n  static std::string to_string_zirci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_rirc(\n      abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rirci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_r(abi::instruction::Instruction *instruction);\n  static std::string to_string_rci(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_z(abi::instruction::Instruction *instruction);\n  static std::string to_string_zci(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_r(abi::instruction::Instruction *instruction);\n  static std::string to_string_s_rci(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_ci(abi::instruction::Instruction *instruction);\n  static std::string to_string_i(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_ddci(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_erri(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_s_erri(\n      abi::instruction::Instruction *instruction);\n\n  static std::string to_string_edri(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_erii(abi::instruction::Instruction *instruction);\n  static std::string to_string_erir(abi::instruction::Instruction *instruction);\n  static std::string to_string_erid(abi::instruction::Instruction *instruction);\n\n  static std::string to_string_dma_rri(\n      abi::instruction::Instruction *instruction);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/op_code_converter.cc",
    "content": "#include \"converter/op_code_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string OpCodeConverter::to_string(abi::instruction::OpCode op_code) {\n  if (op_code == abi::instruction::ACQUIRE) {\n    return \"acquire\";\n  } else if (op_code == abi::instruction::RELEASE) {\n    return \"release\";\n  } else if (op_code == abi::instruction::ADD) {\n    return \"add\";\n  } else if (op_code == abi::instruction::ADDC) {\n    return \"addc\";\n  } else if (op_code == abi::instruction::AND) {\n    return \"and\";\n  } else if (op_code == abi::instruction::ANDN) {\n    return \"andn\";\n  } else if (op_code == abi::instruction::ASR) {\n    return \"asr\";\n  } else if (op_code == abi::instruction::CAO) {\n    return \"cao\";\n  } else if (op_code == abi::instruction::CLO) {\n    return \"clo\";\n  } else if (op_code == abi::instruction::CLS) {\n    return \"cls\";\n  } else if (op_code == abi::instruction::CLZ) {\n    return \"clz\";\n  } else if (op_code == abi::instruction::CMPB4) {\n    return \"cmpb4\";\n  } else if (op_code == abi::instruction::DIV_STEP) {\n    return \"div_step\";\n  } else if (op_code == abi::instruction::EXTSB) {\n    return \"extsb\";\n  } else if (op_code == abi::instruction::EXTSH) {\n    return \"extsh\";\n  } else if (op_code == abi::instruction::EXTUB) {\n    return \"extub\";\n  } else if (op_code == abi::instruction::EXTUH) {\n    return \"extuh\";\n  } else if (op_code == abi::instruction::LSL) {\n    return \"lsl\";\n  } else if (op_code == abi::instruction::LSL_ADD) {\n    return \"lsl_add\";\n  } else if (op_code == abi::instruction::LSL_SUB) {\n    return \"lsl_sub\";\n  } else if (op_code == abi::instruction::LSL1) {\n    return \"lsl1\";\n  } else if (op_code == abi::instruction::LSL1X) {\n    return \"lsl1x\";\n  } else if (op_code == abi::instruction::LSLX) {\n    return \"lslx\";\n  } else if (op_code == abi::instruction::LSR) {\n    return \"lsr\";\n  } else if (op_code == abi::instruction::LSR_ADD) {\n    return \"lsr_add\";\n  } else if (op_code == abi::instruction::LSR1) {\n    return \"lsr1\";\n  } else if (op_code == abi::instruction::LSR1X) {\n    return \"lsr1x\";\n  } else if (op_code == abi::instruction::LSRX) {\n    return \"lsrx\";\n  } else if (op_code == abi::instruction::MUL_SH_SH) {\n    return \"mul_sh_sh\";\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    return \"mul_sh_sl\";\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    return \"mul_sh_uh\";\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    return \"mul_sh_ul\";\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    return \"mul_sl_sh\";\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    return \"mul_sl_sl\";\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    return \"mul_sl_uh\";\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    return \"mul_sl_ul\";\n  } else if (op_code == abi::instruction::MUL_STEP) {\n    return \"mul_step\";\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    return \"mul_uh_uh\";\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    return \"mul_uh_ul\";\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    return \"mul_ul_uh\";\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    return \"mul_ul_ul\";\n  } else if (op_code == abi::instruction::NAND) {\n    return \"nand\";\n  } else if (op_code == abi::instruction::NOR) {\n    return \"nor\";\n  } else if (op_code == abi::instruction::NXOR) {\n    return \"nxor\";\n  } else if (op_code == abi::instruction::OR) {\n    return \"or\";\n  } else if (op_code == abi::instruction::ORN) {\n    return \"orn\";\n  } else if (op_code == abi::instruction::ROL) {\n    return \"rol\";\n  } else if (op_code == abi::instruction::ROL_ADD) {\n    return \"rol_add\";\n  } else if (op_code == abi::instruction::ROR) {\n    return \"ror\";\n  } else if (op_code == abi::instruction::RSUB) {\n    return \"rsub\";\n  } else if (op_code == abi::instruction::RSUBC) {\n    return \"rsubc\";\n  } else if (op_code == abi::instruction::SUB) {\n    return \"sub\";\n  } else if (op_code == abi::instruction::SUBC) {\n    return \"subc\";\n  } else if (op_code == abi::instruction::XOR) {\n    return \"xor\";\n  } else if (op_code == abi::instruction::BOOT) {\n    return \"boot\";\n  } else if (op_code == abi::instruction::RESUME) {\n    return \"resume\";\n  } else if (op_code == abi::instruction::STOP) {\n    return \"stop\";\n  } else if (op_code == abi::instruction::CALL) {\n    return \"call\";\n  } else if (op_code == abi::instruction::FAULT) {\n    return \"fault\";\n  } else if (op_code == abi::instruction::NOP) {\n    return \"nop\";\n  } else if (op_code == abi::instruction::SATS) {\n    return \"sats\";\n  } else if (op_code == abi::instruction::MOVD) {\n    return \"movd\";\n  } else if (op_code == abi::instruction::SWAPD) {\n    return \"swapd\";\n  } else if (op_code == abi::instruction::HASH) {\n    return \"hash\";\n  } else if (op_code == abi::instruction::TIME) {\n    return \"time\";\n  } else if (op_code == abi::instruction::TIME_CFG) {\n    return \"time_cfg\";\n  } else if (op_code == abi::instruction::LBS) {\n    return \"lbs\";\n  } else if (op_code == abi::instruction::LBU) {\n    return \"lbu\";\n  } else if (op_code == abi::instruction::LD) {\n    return \"ld\";\n  } else if (op_code == abi::instruction::LHS) {\n    return \"lhs\";\n  } else if (op_code == abi::instruction::LHU) {\n    return \"lhu\";\n  } else if (op_code == abi::instruction::LW) {\n    return \"lw\";\n  } else if (op_code == abi::instruction::SB) {\n    return \"sb\";\n  } else if (op_code == abi::instruction::SB_ID) {\n    return \"sb_id\";\n  } else if (op_code == abi::instruction::SD) {\n    return \"sd\";\n  } else if (op_code == abi::instruction::SD_ID) {\n    return \"sd_id\";\n  } else if (op_code == abi::instruction::SH) {\n    return \"sh\";\n  } else if (op_code == abi::instruction::SH_ID) {\n    return \"sh_id\";\n  } else if (op_code == abi::instruction::SW) {\n    return \"sw\";\n  } else if (op_code == abi::instruction::SW_ID) {\n    return \"sw_id\";\n  } else if (op_code == abi::instruction::LDMA) {\n    return \"ldma\";\n  } else if (op_code == abi::instruction::LDMAI) {\n    return \"ldmai\";\n  } else if (op_code == abi::instruction::SDMA) {\n    return \"sdma\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/op_code_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_OP_CODE_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_OP_CODE_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/instruction/op_code.h\"\n\nnamespace upmem_sim::converter {\n\nclass OpCodeConverter {\n public:\n  static std::string to_string(abi::instruction::OpCode op_code);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/reg_converter.cc",
    "content": "#include \"converter/reg_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string RegConverter::to_string(abi::reg::SPReg sp_reg) {\n  if (sp_reg == abi::reg::ZERO) {\n    return \"zero\";\n  } else if (sp_reg == abi::reg::ONE) {\n    return \"one\";\n  } else if (sp_reg == abi::reg::LNEG) {\n    return \"lneg\";\n  } else if (sp_reg == abi::reg::MNEG) {\n    return \"mneg\";\n  } else if (sp_reg == abi::reg::ID) {\n    return \"id\";\n  } else if (sp_reg == abi::reg::ID2) {\n    return \"id2\";\n  } else if (sp_reg == abi::reg::ID4) {\n    return \"id4\";\n  } else if (sp_reg == abi::reg::ID8) {\n    return \"id8\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nstd::string RegConverter::to_string(abi::reg::SrcReg *src_reg) {\n  if (src_reg->is_gp_reg()) {\n    return to_string(src_reg->gp_reg());\n  } else if (src_reg->is_sp_reg()) {\n    return to_string(*src_reg->sp_reg());\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/reg_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_REG_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_REG_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/reg/gp_reg.h\"\n#include \"abi/reg/pair_reg.h\"\n#include \"abi/reg/sp_reg.h\"\n#include \"abi/reg/src_reg.h\"\n\nnamespace upmem_sim::converter {\n\nclass RegConverter {\n public:\n  static std::string to_string(abi::reg::GPReg *gp_reg) {\n    return \"r\" + std::to_string(gp_reg->index());\n  }\n  static std::string to_string(abi::reg::PairReg *pair_reg) {\n    return \"d\" + std::to_string(pair_reg->even_reg()->index());\n  }\n  static std::string to_string(abi::reg::SPReg sp_reg);\n  static std::string to_string(abi::reg::SrcReg *src_reg);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/reg_file_converter.cc",
    "content": "#include \"converter/reg_file_converter.h\"\n\n#include <sstream>\n\n#include \"converter/condition_converter.h\"\n#include \"converter/flag_converter.h\"\n#include \"converter/reg_converter.h\"\n\nnamespace upmem_sim::converter {\n\nstd::string RegFileConverter::to_string(simulator::reg::RegFile *reg_file) {\n  std::stringstream ss;\n  for (RegIndex index = 0; index < util::ConfigLoader::num_gp_registers();\n       index++) {\n    auto gp_reg = new abi::reg::GPReg(index);\n    ss << RegConverter::to_string(gp_reg) << \": \"\n       << reg_file->read_gp_reg(gp_reg, abi::word::SIGNED) << std::endl;\n    delete gp_reg;\n  }\n\n  /*\n  ss << \"pc: \" << reg_file->read_pc_reg() << std::endl;\n\n  for (abi::isa::Condition condition = abi::isa::TRUE; condition !=\n  abi::isa::LARGE; condition = static_cast<abi::isa::Condition>(condition + 1))\n  { ss << ConditionConverter::to_string(condition) << \": \" <<\n  reg_file->condition(condition) << std::endl;\n  }\n\n  for (abi::isa::Flag flag = abi::isa::ZERO; flag != abi::isa::CARRY; flag =\n  static_cast<abi::isa::Flag>(flag + 1)) { ss << FlagConverter::to_string(flag)\n  << \": \" << reg_file->flag(flag) << std::endl;\n  }\n  */\n\n  return ss.str();\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/reg_file_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_REG_FILE_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_REG_FILE_CONVERTER_H_\n\n#include <string>\n\n#include \"simulator/reg/reg_file.h\"\n\nnamespace upmem_sim::converter {\n\nclass RegFileConverter {\n public:\n  static std::string to_string(simulator::reg::RegFile *reg_file);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/suffix_converter.cc",
    "content": "#include \"converter/suffix_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::converter {\n\nstd::string SuffixConverter::to_string(abi::instruction::Suffix suffix) {\n  if (suffix == abi::instruction::RICI) {\n    return \"rici\";\n  } else if (suffix == abi::instruction::RRI) {\n    return \"rri\";\n  } else if (suffix == abi::instruction::RRIC) {\n    return \"rric\";\n  } else if (suffix == abi::instruction::RRICI) {\n    return \"rrici\";\n  } else if (suffix == abi::instruction::RRIF) {\n    return \"rrif\";\n  } else if (suffix == abi::instruction::RRR) {\n    return \"rrr\";\n  } else if (suffix == abi::instruction::RRRC) {\n    return \"rrrc\";\n  } else if (suffix == abi::instruction::RRRCI) {\n    return \"rrrci\";\n  } else if (suffix == abi::instruction::ZRI) {\n    return \"zri\";\n  } else if (suffix == abi::instruction::ZRIC) {\n    return \"zric\";\n  } else if (suffix == abi::instruction::ZRICI) {\n    return \"zrici\";\n  } else if (suffix == abi::instruction::ZRIF) {\n    return \"zrif\";\n  } else if (suffix == abi::instruction::ZRR) {\n    return \"zrr\";\n  } else if (suffix == abi::instruction::ZRRC) {\n    return \"zrrc\";\n  } else if (suffix == abi::instruction::ZRRCI) {\n    return \"zrrci\";\n  } else if (suffix == abi::instruction::S_RRI) {\n    return \"s_rri\";\n  } else if (suffix == abi::instruction::S_RRIC) {\n    return \"s_rric\";\n  } else if (suffix == abi::instruction::S_RRICI) {\n    return \"s_rrici\";\n  } else if (suffix == abi::instruction::S_RRIF) {\n    return \"s_rrif\";\n  } else if (suffix == abi::instruction::S_RRR) {\n    return \"s_rrr\";\n  } else if (suffix == abi::instruction::S_RRRC) {\n    return \"s_rrrc\";\n  } else if (suffix == abi::instruction::S_RRRCI) {\n    return \"s_rrrci\";\n  } else if (suffix == abi::instruction::U_RRI) {\n    return \"u_rri\";\n  } else if (suffix == abi::instruction::U_RRIC) {\n    return \"u_rric\";\n  } else if (suffix == abi::instruction::U_RRICI) {\n    return \"u_rrici\";\n  } else if (suffix == abi::instruction::U_RRIF) {\n    return \"u_rrif\";\n  } else if (suffix == abi::instruction::U_RRR) {\n    return \"u_rrr\";\n  } else if (suffix == abi::instruction::U_RRRC) {\n    return \"u_rrrc\";\n  } else if (suffix == abi::instruction::U_RRRCI) {\n    return \"u_rrrci\";\n  } else if (suffix == abi::instruction::RR) {\n    return \"rr\";\n  } else if (suffix == abi::instruction::RRC) {\n    return \"rrc\";\n  } else if (suffix == abi::instruction::RRCI) {\n    return \"rrci\";\n  } else if (suffix == abi::instruction::ZR) {\n    return \"zr\";\n  } else if (suffix == abi::instruction::ZRC) {\n    return \"zrc\";\n  } else if (suffix == abi::instruction::ZRCI) {\n    return \"zrci\";\n  } else if (suffix == abi::instruction::S_RR) {\n    return \"s_rr\";\n  } else if (suffix == abi::instruction::S_RRC) {\n    return \"s_rrc\";\n  } else if (suffix == abi::instruction::S_RRCI) {\n    return \"s_rrci\";\n  } else if (suffix == abi::instruction::U_RR) {\n    return \"u_rr\";\n  } else if (suffix == abi::instruction::U_RRC) {\n    return \"u_rrc\";\n  } else if (suffix == abi::instruction::U_RRCI) {\n    return \"u_rrci\";\n  } else if (suffix == abi::instruction::DRDICI) {\n    return \"drdici\";\n  } else if (suffix == abi::instruction::RRRI) {\n    return \"rrri\";\n  } else if (suffix == abi::instruction::RRRICI) {\n    return \"rrrici\";\n  } else if (suffix == abi::instruction::ZRRI) {\n    return \"zrri\";\n  } else if (suffix == abi::instruction::ZRRICI) {\n    return \"zrrici\";\n  } else if (suffix == abi::instruction::S_RRRI) {\n    return \"s_rrri\";\n  } else if (suffix == abi::instruction::S_RRRICI) {\n    return \"s_rrrici\";\n  } else if (suffix == abi::instruction::U_RRRI) {\n    return \"u_rrri\";\n  } else if (suffix == abi::instruction::U_RRRICI) {\n    return \"u_rrrici\";\n  } else if (suffix == abi::instruction::RIR) {\n    return \"rir\";\n  } else if (suffix == abi::instruction::RIRC) {\n    return \"rirc\";\n  } else if (suffix == abi::instruction::RIRCI) {\n    return \"rirci\";\n  } else if (suffix == abi::instruction::ZIR) {\n    return \"zir\";\n  } else if (suffix == abi::instruction::ZIRC) {\n    return \"zirc\";\n  } else if (suffix == abi::instruction::ZIRCI) {\n    return \"zirci\";\n  } else if (suffix == abi::instruction::S_RIRC) {\n    return \"s_rirc\";\n  } else if (suffix == abi::instruction::S_RIRCI) {\n    return \"s_rirci\";\n  } else if (suffix == abi::instruction::U_RIRC) {\n    return \"u_rirc\";\n  } else if (suffix == abi::instruction::U_RIRCI) {\n    return \"u_rirci\";\n  } else if (suffix == abi::instruction::R) {\n    return \"r\";\n  } else if (suffix == abi::instruction::RCI) {\n    return \"rci\";\n  } else if (suffix == abi::instruction::Z) {\n    return \"z\";\n  } else if (suffix == abi::instruction::ZCI) {\n    return \"zci\";\n  } else if (suffix == abi::instruction::S_R) {\n    return \"s_r\";\n  } else if (suffix == abi::instruction::S_RCI) {\n    return \"s_rci\";\n  } else if (suffix == abi::instruction::U_R) {\n    return \"u_r\";\n  } else if (suffix == abi::instruction::U_RCI) {\n    return \"u_rci\";\n  } else if (suffix == abi::instruction::CI) {\n    return \"ci\";\n  } else if (suffix == abi::instruction::I) {\n    return \"i\";\n  } else if (suffix == abi::instruction::DDCI) {\n    return \"ddci\";\n  } else if (suffix == abi::instruction::ERRI) {\n    return \"erri\";\n  } else if (suffix == abi::instruction::S_ERRI) {\n    return \"s_erri\";\n  } else if (suffix == abi::instruction::U_ERRI) {\n    return \"u_erri\";\n  } else if (suffix == abi::instruction::EDRI) {\n    return \"edri\";\n  } else if (suffix == abi::instruction::ERII) {\n    return \"erii\";\n  } else if (suffix == abi::instruction::ERIR) {\n    return \"erir\";\n  } else if (suffix == abi::instruction::ERID) {\n    return \"erid\";\n  } else if (suffix == abi::instruction::DMA_RRI) {\n    return \"dma_rri\";\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::converter\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/converter/suffix_converter.h",
    "content": "#ifndef UPMEM_SIM_CONVERTER_SUFFIX_CONVERTER_H_\n#define UPMEM_SIM_CONVERTER_SUFFIX_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/instruction/suffix.h\"\n\nnamespace upmem_sim::converter {\n\nclass SuffixConverter {\n public:\n  static std::string to_string(abi::instruction::Suffix suffix);\n};\n\n}  // namespace upmem_sim::converter\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/encoder/byte.h",
    "content": "#ifndef UPMEM_SIM_ENCODER_BYTE_H_\n#define UPMEM_SIM_ENCODER_BYTE_H_\n\n#include <cassert>\n\nnamespace upmem_sim::encoder {\n\nclass Byte {\n public:\n  explicit Byte(int value) : value_(value) {\n    assert(0 <= value and value < 256);\n  }\n  ~Byte() = default;\n\n  int value() { return value_; }\n\n private:\n  int value_;\n};\n\n}  // namespace upmem_sim::encoder\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/encoder/byte_stream.cc",
    "content": "#include \"encoder/byte_stream.h\"\n\n#include <fstream>\n\nnamespace upmem_sim::encoder {\n\nByteStream::ByteStream(std::vector<int> bytes) {\n  bytes_.resize(bytes.size());\n  for (int i = 0; i < bytes_.size(); i++) {\n    bytes_[i] = new Byte(bytes[i]);\n  }\n}\n\nByteStream::ByteStream(std::string filename) {\n  std::ifstream ifs(filename);\n  int byte;\n  while (ifs >> byte) {\n    append(byte);\n  }\n}\n\nByteStream::~ByteStream() {\n  for (auto &byte : bytes_) {\n    delete byte;\n  }\n}\n\nstd::vector<int> ByteStream::bytes() {\n  std::vector<int> bytes;\n  bytes.resize(bytes_.size());\n  for (int i = 0; i < size(); i++) {\n    bytes[i] = byte(i);\n  }\n  return std::move(bytes);\n}\n\nvoid ByteStream::merge(ByteStream *byte_stream) {\n  int size = static_cast<int>(bytes_.size());\n  bytes_.resize(bytes_.size() + byte_stream->bytes_.size());\n  for (int i = 0; i < byte_stream->size(); i++) {\n    bytes_[i + size] = new Byte(static_cast<int>(byte_stream->byte(i)));\n  }\n}\n\nByteStream *ByteStream::slice(int begin, int end) {\n  assert(0 <= begin and begin < end and end <= size());\n\n  auto *byte_stream = new ByteStream();\n  for (int i = begin; i < end; i++) {\n    byte_stream->append(byte(i));\n  }\n  return byte_stream;\n}\n\n}  // namespace upmem_sim::encoder\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/encoder/byte_stream.h",
    "content": "#ifndef UPMEM_SIM_ENCODER_BYTE_STREAM_H_\n#define UPMEM_SIM_ENCODER_BYTE_STREAM_H_\n\n#include <string>\n#include <vector>\n\n#include \"encoder/byte.h\"\n#include \"main.h\"\n\nnamespace upmem_sim::encoder {\n\nclass ByteStream {\n public:\n  explicit ByteStream() = default;\n  explicit ByteStream(std::vector<int> bytes);\n  explicit ByteStream(std::string filename);\n\n  ~ByteStream();\n\n  Address size() { return static_cast<int>(bytes_.size()); }\n  int byte(int index) { return bytes_[index]->value(); }\n  std::vector<int> bytes();\n\n  void append(int value) { bytes_.push_back(new Byte(value)); }\n  void merge(ByteStream *byte_stream);\n\n  ByteStream *slice(int begin, int end);\n\n private:\n  std::vector<Byte *> bytes_;\n};\n\n}  // namespace upmem_sim::encoder\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/encoder/instruction_encoder.cc",
    "content": "#include \"encoder/instruction_encoder.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::encoder {\n\nabi::instruction::Instruction *InstructionEncoder::decode(\n    ByteStream *byte_stream) {\n  auto instruction_word = new abi::word::InstructionWord();\n  instruction_word->from_byte_stream(byte_stream);\n\n  abi::instruction::OpCode op_code = decode_op_code(instruction_word);\n  abi::instruction::Suffix suffix = decode_suffix(instruction_word);\n\n  abi::instruction::Instruction *instruction = nullptr;\n  if (suffix == abi::instruction::RICI) {\n    instruction = decode_rici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRI) {\n    instruction = decode_rri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRIC) {\n    instruction = decode_rric(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRICI) {\n    instruction = decode_rrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRIF) {\n    instruction = decode_rrif(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRR) {\n    instruction = decode_rrr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRRC) {\n    instruction = decode_rrrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRRCI) {\n    instruction = decode_rrrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRI) {\n    instruction = decode_zri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRIC) {\n    instruction = decode_zric(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRICI) {\n    instruction = decode_zrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRIF) {\n    instruction = decode_zrif(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRR) {\n    instruction = decode_zrr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRRC) {\n    instruction = decode_zrrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRRCI) {\n    instruction = decode_zrrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRI or\n             suffix == abi::instruction::U_RRI) {\n    instruction = decode_s_rri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRIC or\n             suffix == abi::instruction::U_RRIC) {\n    instruction = decode_s_rric(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRICI or\n             suffix == abi::instruction::U_RRICI) {\n    instruction = decode_s_rrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRIF or\n             suffix == abi::instruction::U_RRIF) {\n    instruction = decode_s_rrif(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRR or\n             suffix == abi::instruction::U_RRR) {\n    instruction = decode_s_rrr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRRC or\n             suffix == abi::instruction::U_RRRC) {\n    instruction = decode_s_rrrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRRCI or\n             suffix == abi::instruction::U_RRRCI) {\n    instruction = decode_s_rrrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RR) {\n    instruction = decode_rr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRC) {\n    instruction = decode_rrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRCI) {\n    instruction = decode_rrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZR) {\n    instruction = decode_zr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRC) {\n    instruction = decode_zrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRCI) {\n    instruction = decode_zrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RR or\n             suffix == abi::instruction::U_RR) {\n    instruction = decode_s_rr(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRC or\n             suffix == abi::instruction::U_RRC) {\n    instruction = decode_s_rrc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRCI or\n             suffix == abi::instruction::U_RRCI) {\n    instruction = decode_s_rrci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::DRDICI) {\n    instruction = decode_drdici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRRI) {\n    instruction = decode_rrri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RRRICI) {\n    instruction = decode_rrrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRRI) {\n    instruction = decode_zrri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZRRICI) {\n    instruction = decode_zrrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRRI or\n             suffix == abi::instruction::U_RRRI) {\n    instruction = decode_s_rrri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RRRICI or\n             suffix == abi::instruction::U_RRRICI) {\n    instruction = decode_s_rrrici(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RIR) {\n    instruction = decode_rir(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RIRC) {\n    instruction = decode_rirc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RIRCI) {\n    instruction = decode_rirci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZIR) {\n    instruction = decode_zir(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZIRC) {\n    instruction = decode_zirc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZIRCI) {\n    instruction = decode_zirci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RIRC or\n             suffix == abi::instruction::U_RIRC) {\n    instruction = decode_s_rirc(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RIRCI or\n             suffix == abi::instruction::U_RIRCI) {\n    instruction = decode_s_rirci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::R) {\n    instruction = decode_r(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::RCI) {\n    instruction = decode_rci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::Z) {\n    instruction = decode_z(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ZCI) {\n    instruction = decode_zci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_R or\n             suffix == abi::instruction::U_R) {\n    instruction = decode_s_r(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_RCI or\n             suffix == abi::instruction::U_RCI) {\n    instruction = decode_s_rci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::CI) {\n    instruction = decode_ci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::I) {\n    instruction = decode_i(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::DDCI) {\n    instruction = decode_ddci(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ERRI) {\n    instruction = decode_erri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::S_ERRI or\n             suffix == abi::instruction::U_ERRI) {\n    instruction = decode_s_erri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::EDRI) {\n    instruction = decode_edri(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ERII) {\n    instruction = decode_erii(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ERIR) {\n    instruction = decode_erir(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::ERID) {\n    instruction = decode_erid(op_code, suffix, instruction_word);\n  } else if (suffix == abi::instruction::DMA_RRI) {\n    instruction = decode_dma_rri(op_code, suffix, instruction_word);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  delete instruction_word;\n  return instruction;\n}\n\nabi::instruction::OpCode InstructionEncoder::decode_op_code(\n    abi::word::InstructionWord *instruction_word) {\n  return static_cast<abi::instruction::OpCode>(instruction_word->bit_slice(\n      abi::word::UNSIGNED, op_code_begin(), op_code_end()));\n}\n\nabi::instruction::Suffix InstructionEncoder::decode_suffix(\n    abi::word::InstructionWord *instruction_word) {\n  return static_cast<abi::instruction::Suffix>(instruction_word->bit_slice(\n      abi::word::UNSIGNED, suffix_begin(), suffix_end()));\n}\n\nabi::reg::GPReg *InstructionEncoder::decode_gp_reg(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  auto index = static_cast<RegIndex>(\n      instruction_word->bit_slice(abi::word::UNSIGNED, begin, end));\n  return new abi::reg::GPReg(index);\n}\n\nabi::reg::SrcReg *InstructionEncoder::decode_src_reg(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  auto index = static_cast<RegIndex>(\n      instruction_word->bit_slice(abi::word::UNSIGNED, begin, end));\n  if (index < util::ConfigLoader::num_gp_registers()) {\n    return new abi::reg::SrcReg(new abi::reg::GPReg(index));\n  } else {\n    return new abi::reg::SrcReg(\n        new abi::reg::SPReg(static_cast<abi::reg::SPReg>(\n            index - util::ConfigLoader::num_gp_registers())));\n  }\n}\n\nabi::reg::PairReg *InstructionEncoder::decode_pair_reg(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  auto index = static_cast<RegIndex>(\n      instruction_word->bit_slice(abi::word::UNSIGNED, begin, end));\n  return new abi::reg::PairReg(index);\n}\n\nint64_t InstructionEncoder::decode_imm(\n    abi::word::InstructionWord *instruction_word, int begin, int end,\n    abi::word::Representation representation) {\n  return instruction_word->bit_slice(representation, begin, end);\n}\n\nint64_t InstructionEncoder::decode_off(\n    abi::word::InstructionWord *instruction_word, int begin, int end,\n    abi::word::Representation representation) {\n  return decode_imm(instruction_word, begin, end, representation);\n}\n\nabi::isa::Condition InstructionEncoder::decode_condition(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  return static_cast<abi::isa::Condition>(\n      instruction_word->bit_slice(abi::word::UNSIGNED, begin, end));\n}\n\nint64_t InstructionEncoder::decode_pc(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  return decode_imm(instruction_word, begin, end, abi::word::UNSIGNED);\n}\n\nabi::isa::Endian InstructionEncoder::decode_endian(\n    abi::word::InstructionWord *instruction_word, int begin, int end) {\n  return static_cast<abi::isa::Endian>(\n      instruction_word->bit_slice(abi::word::UNSIGNED, begin, end));\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RICI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end = imm_begin + 16;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, imm, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 32;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::call_rri_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 24;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rric(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rric_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRIC);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rric_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rric_op_codes().count(op_code)) {\n    imm_end = imm_begin + 24;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, imm,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRICI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::and_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rrici_op_codes().count(op_code)) {\n    imm_end = imm_begin + 8;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrif(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRIF);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, imm,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRR);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, rb);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRRC);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, rb,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRRCI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, rb,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 32;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::call_rri_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 28;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zric(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rric_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRIC);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rric_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rric_op_codes().count(op_code)) {\n    imm_end = imm_begin + 27;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, imm, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRICI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::and_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rrici_op_codes().count(op_code)) {\n    imm_end = imm_begin + 11;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, imm, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrif(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRIF);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, imm, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRR);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRRC);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRRCI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRI or\n         suffix == abi::instruction::U_RRI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 32;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::call_rri_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 24;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rric(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rric_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRIC or\n         suffix == abi::instruction::U_RRIC);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rric_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rric_op_codes().count(op_code)) {\n    imm_end = imm_begin + 24;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, imm,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRICI or\n         suffix == abi::instruction::U_RRICI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end;\n  int64_t imm;\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::and_rrici_op_codes().count(op_code) or\n      abi::instruction::Instruction::sub_rrici_op_codes().count(op_code)) {\n    imm_end = imm_begin + 8;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    imm_end = imm_begin + 5;\n    imm = decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrif(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRIF or\n         suffix == abi::instruction::U_RRIF);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int imm_begin = ra_end;\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, imm,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRR or\n         suffix == abi::instruction::U_RRR);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, rb);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRRC or\n         suffix == abi::instruction::U_RRRC);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, rb,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRRCI or\n         suffix == abi::instruction::U_RRRCI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int condition_begin = rb_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, rb,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RR);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRC);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRCI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZR);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRC);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRCI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rr(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rr_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RR or suffix == abi::instruction::U_RR);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRC or\n         suffix == abi::instruction::U_RRC);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRCI or\n         suffix == abi::instruction::U_RRCI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_drdici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::drdici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::DRDICI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int db_begin = ra_end;\n  int db_end = db_begin + register_width();\n  abi::reg::PairReg *db = decode_pair_reg(instruction_word, db_begin, db_end);\n\n  int imm_begin = db_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, db, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRRI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, rb, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rrrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RRRICI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, ra, rb, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRRI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zrrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZRRICI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRRI or\n         suffix == abi::instruction::U_RRRI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, rb, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rrrici(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rrrici_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RRICI or\n         suffix == abi::instruction::U_RRRICI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 5;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int condition_begin = imm_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, ra, rb, imm,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rir(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rir_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RIR);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int imm_begin = rc_end;\n  int imm_end = imm_begin + 32;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, imm, ra);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rirc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RIRC);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int imm_begin = rc_end;\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, imm, ra,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rirci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RIRCI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int imm_begin = rc_end;\n  int imm_end = imm_begin + 8;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, imm, ra,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zir(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rir_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZIR);\n\n  int imm_begin = suffix_end();\n  int imm_end = imm_begin + 32;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, imm, ra);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zirc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZIRC);\n\n  int imm_begin = suffix_end();\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, imm, ra, condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zirci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZIRCI);\n\n  int imm_begin = suffix_end();\n  int imm_end = imm_begin + 8;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, imm, ra, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rirc(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirc_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RIRC or\n         suffix == abi::instruction::U_RIRC);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int imm_begin = dc_end;\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, imm, ra,\n                                           condition);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rirci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rirci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RIRCI or\n         suffix == abi::instruction::U_RIRCI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int imm_begin = dc_end;\n  int imm_end = imm_begin + 8;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  int ra_begin = imm_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int condition_begin = ra_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, imm, ra,\n                                           condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_r(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::r_op_codes().count(op_code));\n  assert(suffix == abi::instruction::R);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_rci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::RCI);\n\n  int rc_begin = suffix_end();\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int condition_begin = rc_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, rc, condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_z(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::r_op_codes().count(op_code) or\n         op_code == abi::instruction::NOP);\n  assert(suffix == abi::instruction::Z);\n\n  return new abi::instruction::Instruction(op_code, suffix);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_zci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ZCI);\n\n  int condition_begin = suffix_end();\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_r(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::r_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_R or suffix == abi::instruction::U_R);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_rci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::rci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_RCI or\n         suffix == abi::instruction::U_RCI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int condition_begin = dc_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_ci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::ci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::CI);\n\n  int condition_begin = suffix_end();\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, condition, pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_i(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::i_op_codes().count(op_code));\n  assert(suffix == abi::instruction::I);\n\n  int imm_begin = suffix_end();\n  int imm_end = imm_begin + 24;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_ddci(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::ddci_op_codes().count(op_code));\n  assert(suffix == abi::instruction::DDCI);\n\n  int dc_begin = suffix_end();\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int db_begin = dc_end;\n  int db_end = db_begin + register_width();\n  abi::reg::PairReg *db = decode_pair_reg(instruction_word, db_begin, db_end);\n\n  int condition_begin = db_end;\n  int condition_end = condition_begin + condition_width();\n  abi::isa::Condition condition =\n      decode_condition(instruction_word, condition_begin, condition_end);\n\n  int pc_begin = condition_end;\n  int pc_end = pc_begin + pc_width();\n  int64_t pc = decode_pc(instruction_word, pc_begin, pc_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, dc, db, condition,\n                                           pc);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_erri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::erri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ERRI);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int rc_begin = endian_end;\n  int rc_end = rc_begin + register_width();\n  abi::reg::GPReg *rc = decode_gp_reg(instruction_word, rc_begin, rc_end);\n\n  int ra_begin = rc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, rc, ra,\n                                           off);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_s_erri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::erri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::S_ERRI or\n         suffix == abi::instruction::U_ERRI);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int dc_begin = endian_end;\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, dc, ra,\n                                           off);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_edri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::edri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::EDRI);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int dc_begin = endian_end;\n  int dc_end = dc_begin + register_width();\n  abi::reg::PairReg *dc = decode_pair_reg(instruction_word, dc_begin, dc_end);\n\n  int ra_begin = dc_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, dc, ra,\n                                           off);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_erii(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::erii_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ERII);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int ra_begin = endian_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  int imm_begin = off_end;\n  int imm_end = imm_begin + 16;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::SIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, ra, off,\n                                           imm);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_erir(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::erir_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ERIR);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int ra_begin = endian_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  int rb_begin = off_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, ra, off,\n                                           rb);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_erid(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::erid_op_codes().count(op_code));\n  assert(suffix == abi::instruction::ERID);\n\n  int endian_begin = suffix_end();\n  int endian_end = endian_begin + endian_width();\n  abi::isa::Endian endian =\n      decode_endian(instruction_word, endian_begin, endian_end);\n\n  int ra_begin = endian_end;\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int off_begin = ra_end;\n  int off_end = off_begin + 24;\n  int64_t off =\n      decode_off(instruction_word, off_begin, off_end, abi::word::SIGNED);\n\n  int db_begin = off_end;\n  int db_end = db_begin + register_width();\n  abi::reg::PairReg *db = decode_pair_reg(instruction_word, db_begin, db_end);\n\n  return new abi::instruction::Instruction(op_code, suffix, endian, ra, off,\n                                           db);\n}\n\nabi::instruction::Instruction *InstructionEncoder::decode_dma_rri(\n    abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n    abi::word::InstructionWord *instruction_word) {\n  assert(abi::instruction::Instruction::dma_rri_op_codes().count(op_code));\n  assert(suffix == abi::instruction::DMA_RRI);\n\n  int ra_begin = suffix_end();\n  int ra_end = ra_begin + register_width();\n  abi::reg::SrcReg *ra = decode_src_reg(instruction_word, ra_begin, ra_end);\n\n  int rb_begin = ra_end;\n  int rb_end = rb_begin + register_width();\n  abi::reg::SrcReg *rb = decode_src_reg(instruction_word, rb_begin, rb_end);\n\n  int imm_begin = rb_end;\n  int imm_end = imm_begin + 8;\n  int64_t imm =\n      decode_imm(instruction_word, imm_begin, imm_end, abi::word::UNSIGNED);\n\n  return new abi::instruction::Instruction(op_code, suffix, ra, rb, imm);\n}\n\n}  // namespace upmem_sim::encoder\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/encoder/instruction_encoder.h",
    "content": "#ifndef UPMEM_SIM_ENCODER_INSTRUCTION_ENCODER_H_\n#define UPMEM_SIM_ENCODER_INSTRUCTION_ENCODER_H_\n\n#include <cmath>\n\n#include \"abi/instruction/instruction.h\"\n#include \"abi/instruction/op_code.h\"\n#include \"abi/instruction/suffix.h\"\n#include \"abi/word/instruction_word.h\"\n#include \"encoder/byte_stream.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::encoder {\n\nclass InstructionEncoder {\n public:\n  static abi::instruction::Instruction *decode(ByteStream *byte_stream);\n\n protected:\n  static abi::instruction::OpCode decode_op_code(\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Suffix decode_suffix(\n      abi::word::InstructionWord *instruction_word);\n  static abi::reg::GPReg *decode_gp_reg(\n      abi::word::InstructionWord *instruction_word, int begin, int end);\n  static abi::reg::SrcReg *decode_src_reg(\n      abi::word::InstructionWord *instruction_word, int begin, int end);\n  static abi::reg::PairReg *decode_pair_reg(\n      abi::word::InstructionWord *instruction_word, int begin, int end);\n  static int64_t decode_imm(abi::word::InstructionWord *instruction_word,\n                            int begin, int end,\n                            abi::word::Representation representation);\n  static int64_t decode_off(abi::word::InstructionWord *instruction_word,\n                            int begin, int end,\n                            abi::word::Representation representation);\n  static abi::isa::Condition decode_condition(\n      abi::word::InstructionWord *instruction_word, int begin, int end);\n  static int64_t decode_pc(abi::word::InstructionWord *instruction_word,\n                           int begin, int end);\n  static abi::isa::Endian decode_endian(\n      abi::word::InstructionWord *instruction_word, int begin, int end);\n\n  static abi::instruction::Instruction *decode_rici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rric(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrif(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zric(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrif(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rric(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrif(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rr(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_drdici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rrrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zrrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rrrici(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rir(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rirc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rirci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zir(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zirc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zirci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rirc(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rirci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_r(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_rci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_z(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_zci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_r(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_rci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_ci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_i(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_ddci(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_erri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_s_erri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_edri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_erii(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_erir(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_erid(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n  static abi::instruction::Instruction *decode_dma_rri(\n      abi::instruction::OpCode op_code, abi::instruction::Suffix suffix,\n      abi::word::InstructionWord *instruction_word);\n\n  static int op_code_begin() { return 0; }\n  static int op_code_end() { return op_code_begin() + op_code_width(); }\n\n  static int suffix_begin() { return op_code_end(); }\n  static int suffix_end() { return suffix_begin() + suffix_width(); }\n\n  static int op_code_width() {\n    return ceil(log2(1.0 + abi::instruction::SDMA));\n  }\n  static int suffix_width() {\n    return ceil(log2(1.0 + abi::instruction::DMA_RRI));\n  }\n  static int register_width() {\n    return ceil(log2(util::ConfigLoader::num_gp_registers() + abi::reg::ID8));\n  }\n  static int condition_width() { return ceil(log2(1.0 + abi::isa::LARGE)); }\n  static int pc_width() { return util::ConfigLoader::iram_address_width(); }\n  static int endian_width() { return ceil(log2(1.0 + abi::isa::BIG)); }\n};\n\n}  // namespace upmem_sim::encoder\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/initializer/int_initializer.cc",
    "content": "#include \"initializer/int_initializer.h\"\n\n#include <cassert>\n#include <cmath>\n#include <random>\n\nnamespace upmem_sim::initializer {\n\nint64_t IntInitializer::value_by_range(int64_t min_value, int64_t max_value) {\n  assert(min_value < max_value);\n\n  std::random_device random_device;\n  std::mt19937 generator(random_device());\n  std::uniform_int_distribution<int64_t> distribution;\n\n  int64_t range = max_value - min_value;\n  return distribution(generator) % range + min_value;\n}\n\nint64_t IntInitializer::value_by_width(abi::word::Representation representation,\n                                       int width) {\n  if (representation == abi::word::UNSIGNED) {\n    return value_by_range(0, static_cast<int64_t>(pow(2, width)));\n  } else {\n    return value_by_range(-static_cast<int64_t>(pow(2, width - 1)),\n                          static_cast<int64_t>(pow(2, width - 1)));\n  }\n}\n\n}  // namespace upmem_sim::initializer\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/initializer/int_initializer.h",
    "content": "#ifndef UPMEM_SIM_INITIALIZER_INT_INITIALIZER_H_\n#define UPMEM_SIM_INITIALIZER_INT_INITIALIZER_H_\n\n#include <cstdint>\n\n#include \"abi/word/representation.h\"\n\nnamespace upmem_sim::initializer {\n\nclass IntInitializer {\n public:\n  static int64_t value_by_range(int64_t min_value, int64_t max_value);\n  static int64_t value_by_width(abi::word::Representation representation,\n                                int width);\n};\n\n}  // namespace upmem_sim::initializer\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/initializer/str_initializer.h",
    "content": "#ifndef UPMEM_SIM_INITIALIZER_STR_INITIALIZER_H_\n#define UPMEM_SIM_INITIALIZER_STR_INITIALIZER_H_\n\n#include <string>\n\nnamespace upmem_sim::initializer {\n\nclass StrInitializer {\n public:\n  static std::string identifier(int width);\n};\n\n}  // namespace upmem_sim::initializer\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/initializer/str_initialzier.cc",
    "content": "#include <cassert>\n#include <cmath>\n#include <random>\n\n#include \"initializer/str_initializer.h\"\n\nnamespace upmem_sim::initializer {\n\nstd::string StrInitializer::identifier(int width) {\n  assert(width > 0);\n\n  std::string characters =\n      \"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789._\";\n\n  std::random_device random_device;\n  std::mt19937 generator(random_device());\n  std::uniform_int_distribution<int64_t> distribution;\n\n  std::string identifier = \"\";\n  for (int i = 0; i < width; i++) {\n    int index = static_cast<int>(distribution(generator) % characters.length());\n    identifier += characters.substr(index, 1);\n  }\n\n  return identifier;\n}\n\n}  // namespace upmem_sim::initializer\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/main.cc",
    "content": "#include <iostream>\n\n#include \"simulator/system.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim {\n\nutil::ArgumentParser *init_argument_parser() {\n  auto argument_parser = new util::ArgumentParser();\n\n  // NOTE(dongjae.lee@kaist.ac.kr): Explanation of verbose level\n  // level 0: Only prints simulation output\n  // level 1: level 0 + prints UPMEM instruction executed per each logic cycle\n  // level 2: level + prints UPMEM register file values per each logic cycle\n  argument_parser->add_option(\"verbose\", util::ArgumentParser::INT, \"0\");\n\n  argument_parser->add_option(\"benchmark\", util::ArgumentParser::STRING, \"TRNS\");\n  argument_parser->add_option(\"num_dpus\", util::ArgumentParser::INT, \"1\");\n  argument_parser->add_option(\"num_tasklets\", util::ArgumentParser::INT, \"16\");\n\n  argument_parser->add_option(\"bindir\", util::ArgumentParser::STRING,\n                              \"/home/via/uPIMulator_frontend/bin\");\n  argument_parser->add_option(\"logdir\", util::ArgumentParser::STRING,\n                              \"/home/via/uPIMulator_backend/log\");\n\n  argument_parser->add_option(\"logic_frequency\", util::ArgumentParser::INT,\n                              \"350\");\n  argument_parser->add_option(\"memory_frequency\", util::ArgumentParser::INT,\n                              \"2400\");  // based on DDR4-2400\n\n  argument_parser->add_option(\"num_pipeline_stages\", util::ArgumentParser::INT,\n                              \"14\");\n  argument_parser->add_option(\"num_revolver_scheduling_cycles\",\n                              util::ArgumentParser::INT, \"11\");\n\n  argument_parser->add_option(\"wordline_size\", util::ArgumentParser::INT,\n                              \"1024\");\n\n  argument_parser->add_option(\"t_rcd\", util::ArgumentParser::INT,\n                              \"32\");  // based on DDR4-2400\n  argument_parser->add_option(\"t_ras\", util::ArgumentParser::INT,\n                              \"78\");  // based on DDR4-2400\n  argument_parser->add_option(\"t_rp\", util::ArgumentParser::INT,\n                              \"32\");  // based on DDR4-2400\n  argument_parser->add_option(\"t_cl\", util::ArgumentParser::INT,\n                              \"32\");  // based on DDR4-2400\n  argument_parser->add_option(\"t_bl\", util::ArgumentParser::INT,\n                              \"8\");  // based on DDR4-2400\n\n  argument_parser->add_option(\"memory_scheduling_policy\",\n                              util::ArgumentParser::STRING, \"frfcfs\");\n\n  argument_parser->add_option(\"rank_read_bandwidth\", util::ArgumentParser::INT,\n                              \"1\"); //1\n  argument_parser->add_option(\"rank_write_bandwidth\", util::ArgumentParser::INT,\n                              \"3\"); //3\n\n  return argument_parser;\n}\n\n}  // namespace upmem_sim\n\nint main(int argc, char **argv) {\n  upmem_sim::util::ArgumentParser *argument_parser =\n      upmem_sim::init_argument_parser();\n  argument_parser->parse(argc, argv);\n\n  auto system = new upmem_sim::simulator::System(argument_parser);\n  system->init();\n  while (not system->is_finished()) {\n    system->cycle();\n  }\n  system->fini();\n\n  for (auto &option : argument_parser->options()) {\n    if (argument_parser->option_type(option) ==\n        upmem_sim::util::ArgumentParser::INT) {\n      std::cout << option << \": \" << argument_parser->get_int_parameter(option)\n                << std::endl;\n    } else if (argument_parser->option_type(option) ==\n               upmem_sim::util::ArgumentParser::STRING) {\n        std::cout << option << \": \"\n                << argument_parser->get_string_parameter(option) << std::endl;\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n  }\n\n  upmem_sim::util::StatFactory *system_stat_factory = system->stat_factory();\n  for (auto &stat : system_stat_factory->stats()) {\n      std::cout << stat << \": \" << system_stat_factory->value(stat) << std::endl;\n  }\n  delete system_stat_factory;\n\n  delete argument_parser;\n  delete system;\n\n  return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/main.h",
    "content": "#ifndef UPMEM_SIM_MAIN_H_\n#define UPMEM_SIM_MAIN_H_\n\n#include <cstdint>\n\nnamespace upmem_sim {\n\nusing SimTime = int64_t;\n\nusing Address = int64_t;\nusing DPUID = int;\nusing ThreadID = int;\nusing RegIndex = int;\n\n}  // namespace upmem_sim\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/basic/queue.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_BASIC_QUEUE_H_\n#define UPMEM_SIM_SIMULATOR_BASIC_QUEUE_H_\n\n#include <cassert>\n#include <iostream>\n#include <queue>\n\nnamespace upmem_sim::simulator::basic {\n\ntemplate <typename T>\nclass Queue {\n public:\n  explicit Queue(int size) : size_(size) { assert(size != 0); }\n  ~Queue() { assert(q_.empty()); }\n\n  bool empty() { return q_.empty(); }\n  int size() { return q_.size(); }\n\n  bool can_push(int num_items);\n  bool can_push() { return can_push(1); }\n  void push(T *item);\n  bool can_pop() { return not q_.empty(); }\n  T *pop();\n  void cycle() = delete;\n\n  T *front();\n\n private:\n  int size_;\n  std::queue<T *> q_;\n};\n\ntemplate <typename T>\nbool Queue<T>::can_push(int num_items) {\n  if (size_ >= 0) {\n    return size_ - q_.size() >= num_items;\n  } else {\n    return true;\n  }\n}\n\ntemplate <typename T>\nvoid Queue<T>::push(T *item) {\n  assert(can_push());\n\n  q_.push(item);\n}\n\ntemplate <typename T>\nT *Queue<T>::pop() {\n  assert(can_pop());\n\n  T *item = q_.front();\n  q_.pop();\n  return item;\n}\n\ntemplate <typename T>\nT *Queue<T>::front() {\n  if (q_.empty()) {\n    return nullptr;\n  } else {\n    return q_.front();\n  }\n}\n\n}  // namespace upmem_sim::simulator::basic\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/basic/timer_queue.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_BASIC_TIMER_QUEUE_H_\n#define UPMEM_SIM_SIMULATOR_BASIC_TIMER_QUEUE_H_\n\n#include <cassert>\n#include <tuple>\n#include <vector>\n\n#include \"main.h\"\n\nnamespace upmem_sim::simulator::basic {\n\ntemplate <typename T>\nclass TimerQueue {\n public:\n  explicit TimerQueue(int size);\n  explicit TimerQueue(int size, SimTime timer);\n  ~TimerQueue() { assert(q_.empty()); }\n\n  bool empty() { return q_.empty(); }\n  int size() { return q_.size(); }\n\n  bool can_push(int num_items);\n  bool can_push() { return can_push(1); }\n  void push(T *item);\n  void push(T *item, SimTime timer);\n  bool can_pop();\n  T *pop();\n  void cycle();\n\n  std::tuple<T *, int> front();\n\n private:\n  int size_;\n  SimTime timer_;\n  std::vector<std::tuple<T *, int>> q_;\n};\n\ntemplate <typename T>\nTimerQueue<T>::TimerQueue(int size) : size_(size), timer_(0) {\n  assert(size != 0);\n}\n\ntemplate <typename T>\nTimerQueue<T>::TimerQueue(int size, SimTime timer) : size_(size), timer_(timer) {\n  assert(size != 0);\n  assert(timer > 0);\n}\n\ntemplate <typename T>\nbool TimerQueue<T>::can_push(int num_items) {\n  if (size_ >= 0) {\n    return size_ - q_.size() >= num_items;\n  } else {\n    return true;\n  }\n}\n\ntemplate <typename T>\nvoid TimerQueue<T>::push(T *item) {\n  assert(can_push());\n\n  push(item, timer_);\n}\n\ntemplate <typename T>\nvoid TimerQueue<T>::push(T *item, SimTime timer) {\n  assert(can_push());\n\n  q_.push_back({item, timer});\n}\n\ntemplate <typename T>\nbool TimerQueue<T>::can_pop() {\n  if (q_.empty()) {\n    return false;\n  } else {\n    auto [item, timer] = q_[0];\n    if (timer <= 0) {\n      return true;\n    } else {\n      return false;\n    }\n  }\n}\n\ntemplate <typename T>\nT *TimerQueue<T>::pop() {\n  assert(can_pop());\n  auto [item, timer] = q_[0];\n  q_.erase(q_.begin());\n  return item;\n}\n\ntemplate <typename T>\nstd::tuple<T *, int> TimerQueue<T>::front() {\n  if (q_.empty()) {\n    return {nullptr, 0};\n  } else {\n    return q_[0];\n  }\n}\n\ntemplate <typename T>\nvoid TimerQueue<T>::cycle() {\n  if (not q_.empty()) {\n    auto &[item, timer] = q_[0];\n    timer -= 1;\n  }\n}\n\n}  // namespace upmem_sim::simulator::basic\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/cpu.cc",
    "content": "#include \"simulator/cpu/cpu.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nCPU::~CPU() {\n  delete init_thread_;\n  delete sched_thread_;\n  delete fini_thread_;\n}\n\nvoid CPU::connect_rank(rank::Rank* rank) {\n  init_thread_->connect_rank(rank);\n  sched_thread_->connect_rank(rank);\n  fini_thread_->connect_rank(rank);\n}\n\n}  // namespace upmem_sim::simulator::cpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/cpu.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_CPU_CPU_H_\n#define UPMEM_SIM_SIMULATOR_CPU_CPU_H_\n\n#include \"simulator/cpu/fini_thread.h\"\n#include \"simulator/cpu/init_thread.h\"\n#include \"simulator/cpu/sched_thread.h\"\n#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nclass CPU {\n public:\n  explicit CPU(util::ArgumentParser *argument_parser)\n      : init_thread_(new InitThread(argument_parser)),\n        sched_thread_(new SchedThread(argument_parser)),\n        fini_thread_(new FiniThread(argument_parser)) {}\n  ~CPU();\n\n  void connect_rank(rank::Rank *rank);\n\n  int num_executions() { return fini_thread_->num_executions(); }\n\n  void init() { init_thread_->init(); }\n  void launch() { init_thread_->launch(); }\n  void sched(int execution) { sched_thread_->sched(execution); }\n  void check(int execution) { sched_thread_->check(execution); }\n  void fini() {}\n  void cycle() { fini_thread_->cycle(); }\n\n private:\n  InitThread *init_thread_;\n  SchedThread *sched_thread_;\n  FiniThread *fini_thread_;\n};\n\n}  // namespace upmem_sim::simulator::cpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/fini_thread.cc",
    "content": "#include \"simulator/cpu/fini_thread.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nvoid FiniThread::connect_rank(rank::Rank *rank) {\n  assert(rank != nullptr);\n  assert(rank_ == nullptr);\n\n  rank_ = rank;\n}\n\nvoid FiniThread::cycle() {\n  for (auto &dpu : rank_->dpus()) {\n    for (auto &thread : dpu->scheduler()->threads()) {\n      if (thread->reg_file()->read_pc_reg() == sys_end_pointer() and\n          thread->state() == dpu::Thread::SLEEP) {\n        dpu->scheduler()->shutdown(thread->id());\n      }\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator::cpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/fini_thread.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_CPU_FINI_THREAD_H_\n#define UPMEM_SIM_SIMULATOR_CPU_FINI_THREAD_H_\n\n#include \"simulator/cpu/thread.h\"\n#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nclass FiniThread : public Thread {\n public:\n  explicit FiniThread(util::ArgumentParser *argument_parser)\n      : Thread(argument_parser), rank_(nullptr) {}\n  ~FiniThread() = default;\n\n  void connect_rank(rank::Rank *rank);\n\n  void fini() = delete;\n\n  void cycle();\n\n private:\n  rank::Rank *rank_;\n};\n\n}  // namespace upmem_sim::simulator::cpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/init_thread.cc",
    "content": "#include \"simulator/cpu/init_thread.h\"\n\n#include <iostream>\n\nnamespace upmem_sim::simulator::cpu {\n\nvoid InitThread::connect_rank(rank::Rank *rank) {\n  assert(rank != nullptr);\n  assert(rank_ == nullptr);\n\n  rank_ = rank;\n}\n\nvoid InitThread::init() {\n  dma_transfer_to_atomic();\n  dma_transfer_to_iram();\n  dma_transfer_to_wram();\n  dma_transfer_to_mram();\n\n  std::cout << \"init completed...\" << std::endl;\n}\n\nvoid InitThread::launch() {\n  rank_->launch();\n\n  std::cout << \"launch completed...\" << std::endl;\n}\n\nvoid InitThread::dma_transfer_to_atomic() {\n  auto byte_stream = load_byte_stream(\"atomic\");\n  for (auto &dpu : rank_->dpus()) {\n    dpu->dma()->transfer_to_atomic(util::ConfigLoader::atomic_offset(),\n                                   byte_stream);\n  }\n  delete byte_stream;\n\n  std::cout << \"DMA to atomic completed...\" << std::endl;\n}\n\nvoid InitThread::dma_transfer_to_iram() {\n  auto byte_stream = load_byte_stream(\"iram\");\n  for (auto &dpu : rank_->dpus()) {\n    dpu->dma()->transfer_to_iram(util::ConfigLoader::iram_offset(),\n                                 byte_stream);\n  }\n  delete byte_stream;\n\n  std::cout << \"DMA to IRAM completed...\" << std::endl;\n}\n\nvoid InitThread::dma_transfer_to_wram() {\n  auto byte_stream = load_byte_stream(\"wram\");\n  for (auto &dpu : rank_->dpus()) {\n    dpu->dma()->transfer_to_wram(util::ConfigLoader::wram_offset(),\n                                 byte_stream);\n  }\n  delete byte_stream;\n\n  std::cout << \"DMA to WRAM completed...\" << std::endl;\n}\n\nvoid InitThread::dma_transfer_to_mram() {\n  auto byte_stream = load_byte_stream(\"mram\");\n  for (auto &dpu : rank_->dpus()) {\n    dpu->dma()->transfer_to_mram(util::ConfigLoader::mram_offset(),\n                                 byte_stream);\n  }\n  delete byte_stream;\n\n  std::cout << \"DMA to MRAM completed...\" << std::endl;\n}\n\n}  // namespace upmem_sim::simulator::cpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/init_thread.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_CPU_INIT_THREAD_H_\n#define UPMEM_SIM_SIMULATOR_CPU_INIT_THREAD_H_\n\n#include \"simulator/cpu/thread.h\"\n#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nclass InitThread : public Thread {\n public:\n  explicit InitThread(util::ArgumentParser *argument_parser)\n      : Thread(argument_parser), rank_(nullptr) {}\n  ~InitThread() = default;\n\n  void connect_rank(rank::Rank *rank);\n\n  void init();\n  void launch();\n\n  void cycle() = delete;\n\n protected:\n  void dma_transfer_to_atomic();\n  void dma_transfer_to_iram();\n  void dma_transfer_to_wram();\n  void dma_transfer_to_mram();\n\n private:\n  rank::Rank *rank_;\n};\n\n}  // namespace upmem_sim::simulator::cpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/sched_thread.cc",
    "content": "#include \"simulator/cpu/sched_thread.h\"\n\n#include <iostream>\n#include <sstream>\n\n#include \"main.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nvoid SchedThread::connect_rank(rank::Rank *rank) {\n  assert(rank != nullptr);\n  assert(rank_ == nullptr);\n\n  rank_ = rank;\n}\n\nvoid SchedThread::sched(int execution) {\n  dma_transfer_input_dpu_mram_heap_pointer_name(execution);\n  dma_transfer_dpu_input_arguments(execution);\n\n  std::cout << \"sched \" << execution << \" completed...\" << std::endl;\n}\n\nvoid SchedThread::check(int execution) {\n  dma_transfer_output_dpu_mram_heap_pointer_name(execution);\n  dma_transfer_dpu_results(execution);\n\n  std::cout << \"check \" << execution << \" completed...\" << std::endl;\n}\n\nvoid SchedThread::dma_transfer_input_dpu_mram_heap_pointer_name(int execution) {\n  std::set<rank::RankMessage*> rank_messages;\n  for (DPUID dpu_id = 0; dpu_id < num_dpus(); dpu_id++) {\n    std::stringstream ss;\n    ss << \"input_dpu_mram_heap_pointer_name.dpu_id\" << dpu_id << \".\"\n       << execution;\n\n    std::string bin_filename;\n    ss >> bin_filename;\n\n    auto byte_stream = load_byte_stream(bin_filename);\n\n    if (byte_stream != nullptr) {\n      auto rank_message = new rank::RankMessage(\n          rank::RankMessage::WRITE, dpu_id, sys_used_mram_end_pointer(),\n          byte_stream->size(), byte_stream);\n      rank_->write(rank_message);\n      rank_messages.insert(rank_message);\n\n      rank_->dpus()[dpu_id]->dma()->transfer_to_mram(\n          sys_used_mram_end_pointer(), byte_stream);\n\n      delete byte_stream;\n    }\n  }\n\n  for (auto & rank_message : rank_messages) {\n    while (not rank_message->ack()) {\n      rank_->cycle();\n    }\n\n    delete rank_message;\n  }\n}\n\nvoid SchedThread::dma_transfer_dpu_input_arguments(int execution) {\n  std::set<rank::RankMessage*> rank_messages;\n  for (DPUID dpu_id = 0; dpu_id < num_dpus(); dpu_id++) {\n    std::stringstream ss;\n    ss << \"dpu_input_arguments.dpu_id\" << dpu_id << \".\" << execution;\n\n    std::string bin_filename;\n    ss >> bin_filename;\n\n    auto byte_stream = load_byte_stream(bin_filename);\n\n    if (byte_stream != nullptr) {\n      auto rank_message = new rank::RankMessage(\n          rank::RankMessage::WRITE, dpu_id, dpu_input_arguments_pointer(),\n          byte_stream->size(), byte_stream);\n      rank_->write(rank_message);\n      rank_messages.insert(rank_message);\n\n      rank_->dpus()[dpu_id]->dma()->transfer_to_wram(\n          dpu_input_arguments_pointer(), byte_stream);\n\n      delete byte_stream;\n    }\n  }\n\n  for (auto & rank_message : rank_messages) {\n    while (not rank_message->ack()) {\n      rank_->cycle();\n    }\n    delete rank_message;\n  }\n}\n\nvoid SchedThread::dma_transfer_output_dpu_mram_heap_pointer_name(\n    int execution) {\n  std::set<rank::RankMessage*> rank_messages;\n  for (DPUID dpu_id = 0; dpu_id < num_dpus(); dpu_id++) {\n    std::stringstream ss;\n    ss << \"output_dpu_mram_heap_pointer_name.dpu_id\" << dpu_id << \".\"\n       << execution;\n\n    std::string bin_filename;\n    ss >> bin_filename;\n\n    auto byte_stream = load_byte_stream(bin_filename);\n\n    if (byte_stream != nullptr) {\n      auto rank_message = new rank::RankMessage(rank::RankMessage::READ, dpu_id,\n                                                sys_used_mram_end_pointer(),\n                                                byte_stream->size());\n      rank_->read(rank_message);\n      rank_messages.insert(rank_message);\n\n      encoder::ByteStream *mram_byte_stream =\n          rank_->dpus()[dpu_id]->dma()->transfer_from_mram(\n              sys_used_mram_end_pointer(), byte_stream->size());\n\n      assert(byte_stream->size() == mram_byte_stream->size());\n      for (int i = 0; i < byte_stream->size(); i++) {\n        assert(byte_stream->byte(i) == mram_byte_stream->byte(i));\n      }\n\n      delete byte_stream;\n      delete mram_byte_stream;\n    }\n  }\n\n  for (auto & rank_message : rank_messages) {\n    while (not rank_message->ack()) {\n      rank_->cycle();\n    }\n    delete rank_message;\n  }\n}\n\nvoid SchedThread::dma_transfer_dpu_results(int execution) {\n  std::set<rank::RankMessage*> rank_messages;\n  for (DPUID dpu_id = 0; dpu_id < num_dpus(); dpu_id++) {\n    std::stringstream ss;\n    ss << \"dpu_results.dpu_id\" << dpu_id << \".\" << execution;\n\n    std::string bin_filename;\n    ss >> bin_filename;\n\n    auto byte_stream = load_byte_stream(bin_filename);\n\n    if (byte_stream != nullptr) {\n      auto rank_message =\n          new rank::RankMessage(rank::RankMessage::READ, dpu_id,\n                                dpu_results_pointer(), byte_stream->size());\n      rank_->read(rank_message);\n      rank_messages.insert(rank_message);\n\n      encoder::ByteStream *wram_byte_stream =\n          rank_->dpus()[dpu_id]->dma()->transfer_from_wram(\n              dpu_results_pointer(), byte_stream->size());\n\n      assert(byte_stream->size() == wram_byte_stream->size());\n      for (int i = 0; i < byte_stream->size(); i++) {\n        assert(byte_stream->byte(i) == wram_byte_stream->byte(i));\n      }\n\n      delete byte_stream;\n      delete wram_byte_stream;\n    }\n  }\n\n  for (auto & rank_message : rank_messages) {\n    while (not rank_message->ack()) {\n      rank_->cycle();\n    }\n    delete rank_message;\n  }\n}\n\n}  // namespace upmem_sim::simulator::cpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/sched_thread.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_CPU_SCHED_THREAD_H_\n#define UPMEM_SIM_SIMULATOR_CPU_SCHED_THREAD_H_\n\n#include \"simulator/cpu/thread.h\"\n#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nclass SchedThread : public Thread {\n public:\n  explicit SchedThread(util::ArgumentParser *argument_parser)\n      : Thread(argument_parser), rank_(nullptr) {}\n  ~SchedThread() = default;\n\n  void connect_rank(rank::Rank *rank);\n\n  void sched(int execution);\n  void check(int execution);\n\n  void cycle() = delete;\n\n protected:\n  void dma_transfer_input_dpu_mram_heap_pointer_name(int execution);\n  void dma_transfer_dpu_input_arguments(int execution);\n\n  void dma_transfer_output_dpu_mram_heap_pointer_name(int execution);\n  void dma_transfer_dpu_results(int execution);\n\n private:\n  rank::Rank *rank_;\n};\n\n}  // namespace upmem_sim::simulator::cpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/thread.cc",
    "content": "#include \"simulator/cpu/thread.h\"\n\n#include <filesystem>\n#include <fstream>\n#include <sstream>\n\nnamespace upmem_sim::simulator::cpu {\n\nThread::Thread(util::ArgumentParser *argument_parser)\n    : bindir_(argument_parser->get_string_parameter(\"bindir\")),\n      benchmark_(argument_parser->get_string_parameter(\"benchmark\")),\n      num_dpus_(\n          static_cast<int>(argument_parser->get_int_parameter(\"num_dpus\"))),\n      num_tasklets_(static_cast<int>(\n          argument_parser->get_int_parameter(\"num_tasklets\"))) {\n  assert(0 < num_dpus_);\n  assert(0 < num_tasklets_ and\n         num_tasklets_ <= util::ConfigLoader::max_num_tasklets());\n\n  init_dpu_transfer_pointer();\n  init_num_executions();\n}\n\nencoder::ByteStream *Thread::load_byte_stream(std::string filename) {\n  std::string bin_filepath = bindir_ + \"/\" + benchmark_ + \".\" +\n                             std::to_string(num_tasklets_) + \"/\" + filename +\n                             \".bin\";\n  if (std::filesystem::exists(bin_filepath)) {\n    auto byte_stream = new encoder::ByteStream(bin_filepath);\n    return byte_stream;\n  } else {\n    return nullptr;\n  }\n}\n\nvoid Thread::init_dpu_transfer_pointer() {\n  std::string bin_filepath = bindir_ + \"/\" + benchmark_ + \".\" +\n                             std::to_string(num_tasklets_) +\n                             \"/dpu_transfer_pointer.bin\";\n  std::ifstream ifs(bin_filepath);\n\n  ifs >> sys_used_mram_end_pointer_ >> dpu_input_arguments_pointer_ >>\n      dpu_results_pointer_ >> sys_end_pointer_;\n}\n\nvoid Thread::init_num_executions() {\n  std::string bin_filepath = bindir_ + \"/\" + benchmark_ + \".\" +\n                             std::to_string(num_tasklets_) +\n                             \"/num_executions.bin\";\n  std::ifstream ifs(bin_filepath);\n\n  ifs >> num_executions_;\n}\n\n}  // namespace upmem_sim::simulator::cpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/cpu/thread.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_CPU_THREAD_H_\n#define UPMEM_SIM_SIMULATOR_CPU_THREAD_H_\n\n#include \"simulator/dpu/dpu.h\"\n\nnamespace upmem_sim::simulator::cpu {\n\nclass Thread {\n public:\n  explicit Thread(util::ArgumentParser *argument_parser);\n  ~Thread() = default;\n\n  std::string benchmark() { return benchmark_; }\n  int num_dpus() { return num_dpus_; }\n  int num_tasklets() { return num_tasklets_; }\n\n  Address sys_used_mram_end_pointer() { return sys_used_mram_end_pointer_; }\n  Address dpu_input_arguments_pointer() { return dpu_input_arguments_pointer_; }\n  Address dpu_results_pointer() { return dpu_results_pointer_; }\n  Address sys_end_pointer() { return sys_end_pointer_; }\n\n  int num_executions() { return num_executions_; }\n\n protected:\n  encoder::ByteStream *load_byte_stream(std::string filename);\n\n  void init_dpu_transfer_pointer();\n  void init_num_executions();\n\n private:\n  std::string bindir_;\n  std::string benchmark_;\n\n  int num_dpus_;\n  int num_tasklets_;\n\n  Address sys_used_mram_end_pointer_;\n  Address dpu_input_arguments_pointer_;\n  Address dpu_results_pointer_;\n  Address sys_end_pointer_;\n\n  int num_executions_;\n};\n\n}  // namespace upmem_sim::simulator::cpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/alu.cc",
    "content": "#include \"simulator/dpu/alu.h\"\n\n#include <cassert>\n#include <cmath>\n#include <functional>\n\n#include \"abi/word/data_word.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nint64_t ALU::atomic_address_hash(int64_t operand1, int64_t operand2) {\n  assert(operand1 + operand2 < 256);\n  auto [result, carry, overflow] = add(operand1, operand2);\n  return result;\n}\n\nstd::tuple<int64_t, bool, bool> ALU::add(int64_t operand1, int64_t operand2) {\n  return addc(operand1, operand2, false);\n}\n\nstd::tuple<int64_t, bool, bool> ALU::addc(int64_t operand1, int64_t operand2,\n                                          bool carry_flag) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  int64_t result = data_word1->value(abi::word::UNSIGNED) +\n                   data_word2->value(abi::word::UNSIGNED) + carry_flag;\n\n  int64_t max_unsigned_value =\n      static_cast<int64_t>(pow(2, abi::word::DataWord().width())) - 1;\n  bool carry;\n  if (result > max_unsigned_value) {\n    result %= static_cast<int64_t>(pow(2, abi::word::DataWord().width()));\n    carry = true;\n  } else {\n    carry = false;\n  }\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(result);\n\n  bool overflow;\n  if (data_word1->sign_bit() and data_word2->sign_bit() and\n      not result_data_word->sign_bit()) {\n    overflow = true;\n  } else if (not data_word1->sign_bit() and not data_word2->sign_bit() and\n             result_data_word->sign_bit()) {\n    overflow = true;\n  } else {\n    overflow = false;\n  }\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return {result, carry, overflow};\n}\n\nstd::tuple<int64_t, bool, bool> ALU::sub(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  int64_t result;\n  bool carry;\n  if (data_word1->value(abi::word::UNSIGNED) >=\n      data_word2->value(abi::word::UNSIGNED)) {\n    result = data_word1->value(abi::word::UNSIGNED) -\n             data_word2->value(abi::word::UNSIGNED);\n    carry = false;\n  } else {\n    result = static_cast<int64_t>(pow(2, abi::word::DataWord().width())) +\n             data_word1->value(abi::word::UNSIGNED) -\n             data_word2->value(abi::word::UNSIGNED);\n    carry = true;\n  }\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(result);\n\n  bool overflow;\n  if (data_word1->sign_bit() and not data_word2->sign_bit() and\n      result_data_word->sign_bit()) {\n    overflow = true;\n  } else if (not data_word1->sign_bit() and data_word2->sign_bit() and\n             not result_data_word->sign_bit()) {\n    overflow = true;\n  } else {\n    overflow = false;\n  }\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return {result, carry, overflow};\n}\n\nstd::tuple<int64_t, bool, bool> ALU::subc(int64_t operand1, int64_t operand2,\n                                          bool carry_flag) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  int64_t result;\n  bool carry;\n  if (data_word1->value(abi::word::UNSIGNED) + carry_flag >=\n      data_word2->value(abi::word::UNSIGNED)) {\n    result = data_word1->value(abi::word::UNSIGNED) -\n             data_word2->value(abi::word::UNSIGNED) - carry_flag;\n    carry = false;\n  } else {\n    result = static_cast<int64_t>(pow(2, abi::word::DataWord().width())) +\n             data_word1->value(abi::word::UNSIGNED) -\n             data_word2->value(abi::word::UNSIGNED) - carry_flag;\n    carry = true;\n  }\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(result);\n\n  bool overflow;\n  if (data_word1->sign_bit() and not data_word2->sign_bit() and\n      result_data_word->sign_bit()) {\n    overflow = true;\n  } else if (not data_word1->sign_bit() and data_word2->sign_bit() and\n             not result_data_word->sign_bit()) {\n    overflow = true;\n  } else {\n    overflow = false;\n  }\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return {result, carry, overflow};\n}\n\nint64_t ALU::and_(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (data_word1->bit(i) and data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else {\n      result_data_word->clear_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::nand(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (data_word1->bit(i) and data_word2->bit(i)) {\n      result_data_word->clear_bit(i);\n    } else {\n      result_data_word->set_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::andn(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (not data_word1->bit(i) and data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else {\n      result_data_word->clear_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::or_(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (data_word1->bit(i) or data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else {\n      result_data_word->clear_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::nor(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (data_word1->bit(i) or data_word2->bit(i)) {\n      result_data_word->clear_bit(i);\n    } else {\n      result_data_word->set_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::orn(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (not data_word1->bit(i) or data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else {\n      result_data_word->clear_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::xor_(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (not data_word1->bit(i) and data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else if (data_word1->bit(i) and not data_word2->bit(i)) {\n      result_data_word->set_bit(i);\n    } else {\n      result_data_word->clear_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::nxor(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (not data_word1->bit(i) and data_word2->bit(i)) {\n      result_data_word->clear_bit(i);\n    } else if (data_word1->bit(i) and not data_word2->bit(i)) {\n      result_data_word->clear_bit(i);\n    } else {\n      result_data_word->set_bit(i);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::asr(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n  bool msb = data_word->sign_bit();\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i + shift_value >= result_data_word->width()) {\n      if (msb) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    } else {\n      if (data_word->bit(static_cast<int>(i + shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::lsl(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i < shift_value) {\n      result_data_word->clear_bit(i);\n    } else {\n      if (data_word->bit(static_cast<int>(i - shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nstd::tuple<int64_t, bool, bool> ALU::lsl_add(int64_t operand1, int64_t operand2,\n                                             int64_t shift) {\n  return add(operand1, lsl(operand2, shift));\n}\n\nstd::tuple<int64_t, bool, bool> ALU::lsl_sub(int64_t operand1, int64_t operand2,\n                                             int64_t shift) {\n  return sub(operand1, lsl(operand2, shift));\n}\n\nint64_t ALU::lsl1(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i < shift_value) {\n      result_data_word->set_bit(i);\n    } else {\n      if (data_word->bit(static_cast<int>(i - shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::lsl1x(int64_t operand, int64_t shift) {\n  throw std::bad_function_call();\n}\n\nint64_t ALU::lslx(int64_t operand, int64_t shift) {\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  if (shift_value == 0) {\n    return 0;\n  } else {\n    return lsr(operand, abi::word::DataWord().width() - shift_value);\n  }\n}\n\nint64_t ALU::lsr(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i + shift_value >= result_data_word->width()) {\n      result_data_word->clear_bit(i);\n    } else {\n      if (data_word->bit(static_cast<int>(i + shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nstd::tuple<int64_t, bool, bool> ALU::lsr_add(int64_t operand1, int64_t operand2,\n                                             int64_t shift) {\n  return add(operand1, lsr(operand2, shift));\n}\n\nint64_t ALU::lsr1(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i + shift_value >= result_data_word->width()) {\n      result_data_word->set_bit(i);\n    } else {\n      if (data_word->bit(static_cast<int>(i + shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::lsr1x(int64_t operand, int64_t shift) {\n  throw std::bad_function_call();\n}\n\nint64_t ALU::lsrx(int64_t operand, int64_t shift) {\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  if (shift_value == 0) {\n    return 0;\n  } else {\n    return lsl(operand, abi::word::DataWord().width() - shift_value);\n  }\n}\n\nint64_t ALU::rol(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i < shift_value) {\n      if (data_word->bit(\n              static_cast<int>(i + data_word->width() - shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    } else {\n      if (data_word->bit(static_cast<int>(i - shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nstd::tuple<int64_t, bool, bool> ALU::rol_add(int64_t operand1, int64_t operand2,\n                                             int64_t shift) {\n  return add(operand1, rol(operand2, shift));\n}\n\nint64_t ALU::ror(int64_t operand, int64_t shift) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto shift_data_word = new abi::word::DataWord();\n  shift_data_word->set_value(shift);\n  auto shift_value = shift_data_word->bit_slice(abi::word::UNSIGNED, 0, 5);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < result_data_word->width(); i++) {\n    if (i + shift_value >= result_data_word->width()) {\n      if (data_word->bit(\n              static_cast<int>((i + shift_value) % data_word->width()))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    } else {\n      if (data_word->bit(static_cast<int>(i + shift_value))) {\n        result_data_word->set_bit(i);\n      } else {\n        result_data_word->clear_bit(i);\n      }\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::cao(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  int64_t ones = 0;\n  for (int i = 0; i < data_word->width(); i++) {\n    if (data_word->bit(i)) {\n      ones += 1;\n    }\n  }\n\n  delete data_word;\n\n  return ones;\n}\n\nint64_t ALU::clo(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  int64_t leading_ones = 0;\n  for (int i = 0; i < data_word->width(); i++) {\n    if (data_word->bit(data_word->width() - 1 - i)) {\n      leading_ones += 1;\n    } else {\n      break;\n    }\n  }\n  delete data_word;\n\n  return leading_ones;\n}\n\nint64_t ALU::cls(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  bool msb = data_word->sign_bit();\n  int64_t leading_sign_bits = 0;\n  for (int i = 0; i < data_word->width(); i++) {\n    if (data_word->bit(data_word->width() - 1 - i) == msb) {\n      leading_sign_bits += 1;\n    } else {\n      break;\n    }\n  }\n\n  delete data_word;\n  return leading_sign_bits;\n}\n\nint64_t ALU::clz(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  int64_t leading_zeros = 0;\n  for (int i = 0; i < data_word->width(); i++) {\n    if (not data_word->bit(data_word->width() - 1 - i)) {\n      leading_zeros += 1;\n    } else {\n      break;\n    }\n  }\n\n  delete data_word;\n\n  return leading_zeros;\n}\n\nint64_t ALU::cmpb4(int64_t operand1, int64_t operand2) {\n  assert(abi::word::DataWord().width() == 4 * 8);\n\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  for (int i = 0; i < 4; i++) {\n    int begin = 8 * i;\n    int end = 8 * (i + 1);\n\n    int64_t byte1 = data_word1->bit_slice(abi::word::UNSIGNED, begin, end);\n    int64_t byte2 = data_word2->bit_slice(abi::word::UNSIGNED, begin, end);\n\n    if (byte1 == byte2) {\n      result_data_word->set_bit_slice(begin, end, 1);\n    } else {\n      result_data_word->set_bit_slice(begin, end, 0);\n    }\n  }\n\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::extsb(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n  int64_t result = data_word->bit_slice(abi::word::SIGNED, 0, 8);\n  delete data_word;\n  return result;\n}\n\nint64_t ALU::extsh(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n  int64_t result = data_word->bit_slice(abi::word::SIGNED, 0, 16);\n  delete data_word;\n  return result;\n}\n\nint64_t ALU::extub(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n  int64_t result = data_word->bit_slice(abi::word::UNSIGNED, 0, 8);\n  delete data_word;\n  return result;\n}\n\nint64_t ALU::extuh(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n  int64_t result = data_word->bit_slice(abi::word::UNSIGNED, 0, 16);\n  delete data_word;\n  return result;\n}\n\nint64_t ALU::mul_sh_sh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 8, 16) *\n                              data_word2->bit_slice(abi::word::SIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sh_sl(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 8, 16) *\n                              data_word2->bit_slice(abi::word::UNSIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sh_uh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(\n      data_word1->bit_slice(abi::word::SIGNED, 8, 16) *\n      data_word2->bit_slice(abi::word::UNSIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sh_ul(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 8, 16) *\n                              data_word2->bit_slice(abi::word::UNSIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sl_sh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 0, 8) *\n                              data_word2->bit_slice(abi::word::SIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sl_sl(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 0, 8) *\n                              data_word2->bit_slice(abi::word::SIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sl_uh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(\n      data_word1->bit_slice(abi::word::SIGNED, 0, 8) *\n      data_word2->bit_slice(abi::word::UNSIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_sl_ul(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::SIGNED, 0, 8) *\n                              data_word2->bit_slice(abi::word::UNSIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::SIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_uh_uh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(\n      data_word1->bit_slice(abi::word::UNSIGNED, 8, 16) *\n      data_word2->bit_slice(abi::word::UNSIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_uh_ul(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(\n      data_word1->bit_slice(abi::word::UNSIGNED, 8, 16) *\n      data_word2->bit_slice(abi::word::UNSIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_ul_uh(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(\n      data_word1->bit_slice(abi::word::UNSIGNED, 0, 8) *\n      data_word2->bit_slice(abi::word::UNSIGNED, 8, 16));\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::mul_ul_ul(int64_t operand1, int64_t operand2) {\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(data_word1->bit_slice(abi::word::UNSIGNED, 0, 8) *\n                              data_word2->bit_slice(abi::word::UNSIGNED, 0, 8));\n  int64_t result = result_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word1;\n  delete data_word2;\n  delete result_data_word;\n\n  return result;\n}\n\nint64_t ALU::sats(int64_t operand) { throw std::bad_function_call(); }\n\nint64_t ALU::hash(int64_t operand1, int64_t operand2) {\n  throw std::bad_function_call();\n}\n\nstd::tuple<int64_t, int64_t> ALU::signed_extension(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto even_data_word = new abi::word::DataWord();\n  if (data_word->sign_bit()) {\n    even_data_word->set_value(-1);\n  }\n  int64_t even = even_data_word->value(abi::word::UNSIGNED);\n\n  auto odd_data_word = new abi::word::DataWord();\n  odd_data_word->set_value(data_word->value(abi::word::UNSIGNED));\n  int64_t odd = odd_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete even_data_word;\n  delete odd_data_word;\n\n  return {even, odd};\n}\n\nstd::tuple<int64_t, int64_t> ALU::unsigned_extension(int64_t operand) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(operand);\n\n  auto even_data_word = new abi::word::DataWord();\n  even_data_word->set_value(0);\n  int64_t even = even_data_word->value(abi::word::UNSIGNED);\n\n  auto odd_data_word = new abi::word::DataWord();\n  odd_data_word->set_value(data_word->value(abi::word::UNSIGNED));\n  int64_t odd = odd_data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n  delete even_data_word;\n  delete odd_data_word;\n\n  return {even, odd};\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/alu.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_ALU_H_\n#define UPMEM_SIM_SIMULATOR_DPU_ALU_H_\n\n#include <cstdint>\n#include <tuple>\n\nnamespace upmem_sim::simulator::dpu {\n\nclass ALU {\n public:\n  static int64_t atomic_address_hash(int64_t operand1, int64_t operand2);\n\n  static std::tuple<int64_t, bool, bool> add(int64_t operand1,\n                                             int64_t operand2);\n  static std::tuple<int64_t, bool, bool> addc(int64_t operand1,\n                                              int64_t operand2,\n                                              bool carry_flag);\n\n  static std::tuple<int64_t, bool, bool> sub(int64_t operand1,\n                                             int64_t operand2);\n  static std::tuple<int64_t, bool, bool> subc(int64_t operand1,\n                                              int64_t operand2,\n                                              bool carry_flag);\n\n  static int64_t and_(int64_t operand1, int64_t operand2);\n  static int64_t nand(int64_t operand1, int64_t operand2);\n  static int64_t andn(int64_t operand1, int64_t operand2);\n  static int64_t or_(int64_t operand1, int64_t operand2);\n  static int64_t nor(int64_t operand1, int64_t operand2);\n  static int64_t orn(int64_t operand1, int64_t operand2);\n  static int64_t xor_(int64_t operand1, int64_t operand2);\n  static int64_t nxor(int64_t operand1, int64_t operand2);\n\n  static int64_t asr(int64_t operand, int64_t shift);\n  static int64_t lsl(int64_t operand, int64_t shift);\n\n  static std::tuple<int64_t, bool, bool> lsl_add(int64_t operand1,\n                                                 int64_t operand2,\n                                                 int64_t shift);\n  static std::tuple<int64_t, bool, bool> lsl_sub(int64_t operand1,\n                                                 int64_t operand2,\n                                                 int64_t shift);\n\n  static int64_t lsl1(int64_t operand, int64_t shift);\n  static int64_t lsl1x(int64_t operand, int64_t shift);\n  static int64_t lslx(int64_t operand, int64_t shift);\n\n  static int64_t lsr(int64_t operand, int64_t shift);\n\n  static std::tuple<int64_t, bool, bool> lsr_add(int64_t operand1,\n                                                 int64_t operand2,\n                                                 int64_t shift);\n\n  static int64_t lsr1(int64_t operand, int64_t shift);\n  static int64_t lsr1x(int64_t operand, int64_t shift);\n  static int64_t lsrx(int64_t operand, int64_t shift);\n\n  static int64_t rol(int64_t operand, int64_t shift);\n\n  static std::tuple<int64_t, bool, bool> rol_add(int64_t operand1,\n                                                 int64_t operand2,\n                                                 int64_t shift);\n\n  static int64_t ror(int64_t operand, int64_t shift);\n\n  static int64_t cao(int64_t operand);\n  static int64_t clo(int64_t operand);\n  static int64_t cls(int64_t operand);\n  static int64_t clz(int64_t operand);\n\n  static int64_t cmpb4(int64_t operand1, int64_t operand2);\n\n  static int64_t extsb(int64_t operand);\n  static int64_t extsh(int64_t operand);\n  static int64_t extub(int64_t operand);\n  static int64_t extuh(int64_t operand);\n\n  static int64_t mul_sh_sh(int64_t operand1, int64_t operand2);\n  static int64_t mul_sh_sl(int64_t operand1, int64_t operand2);\n  static int64_t mul_sh_uh(int64_t operand1, int64_t operand2);\n  static int64_t mul_sh_ul(int64_t operand1, int64_t operand2);\n  static int64_t mul_sl_sh(int64_t operand1, int64_t operand2);\n  static int64_t mul_sl_sl(int64_t operand1, int64_t operand2);\n  static int64_t mul_sl_uh(int64_t operand1, int64_t operand2);\n  static int64_t mul_sl_ul(int64_t operand1, int64_t operand2);\n  static int64_t mul_uh_uh(int64_t operand1, int64_t operand2);\n  static int64_t mul_uh_ul(int64_t operand1, int64_t operand2);\n  static int64_t mul_ul_uh(int64_t operand1, int64_t operand2);\n  static int64_t mul_ul_ul(int64_t operand1, int64_t operand2);\n\n  static int64_t sats(int64_t operand);\n  static int64_t hash(int64_t operand1, int64_t operand2);\n\n  static std::tuple<int64_t, int64_t> signed_extension(int64_t operand);\n  static std::tuple<int64_t, int64_t> unsigned_extension(int64_t operand);\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/cycle_rule.cc",
    "content": "#include \"simulator/dpu/cycle_rule.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nCycleRule::CycleRule(util::ArgumentParser *argument_parser)\n    : input_q_(new basic::Queue<abi::instruction::Instruction>(1)),\n      wait_q_(new basic::TimerQueue<abi::instruction::Instruction>(1)),\n      ready_q_(new basic::Queue<abi::instruction::Instruction>(1)),\n      stat_factory_(new util::StatFactory(\"CycleRule\")) {\n  int num_tasklets =\n      static_cast<int>(argument_parser->get_int_parameter(\"num_tasklets\"));\n  prev_write_gp_regs_.resize(num_tasklets);\n  cur_read_gp_regs_.resize(num_tasklets);\n}\n\nCycleRule::~CycleRule() {\n  delete input_q_;\n  delete wait_q_;\n  delete ready_q_;\n\n  for (auto &prev_write_gp_regs : prev_write_gp_regs_) {\n    for (auto &gp_reg : prev_write_gp_regs) {\n      delete gp_reg;\n    }\n  }\n\n  for (auto &cur_read_gp_regs : cur_read_gp_regs_) {\n    for (auto &gp_reg : cur_read_gp_regs) {\n      delete gp_reg;\n    }\n  }\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *CycleRule::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n  stat_factory->merge(stat_factory_);\n  return stat_factory;\n}\n\nvoid CycleRule::push(abi::instruction::Instruction *instruction) {\n  assert(instruction != nullptr);\n  input_q_->push(instruction);\n}\n\nvoid CycleRule::cycle() {\n  service_input_q();\n  service_ready_q();\n\n  wait_q_->cycle();\n}\n\nvoid CycleRule::service_input_q() {\n  if (input_q_->can_pop() and wait_q_->can_push()) {\n    abi::instruction::Instruction *instruction = input_q_->pop();\n    int extra_cycle = calculate_extra_cycles(instruction);\n\n    wait_q_->push(instruction, extra_cycle);\n\n    stat_factory_->increment(\"cycle_rule\", extra_cycle);\n    stat_factory_->increment(\n        std::to_string(instruction->thread()->id()) + \"_cycle_rule\",\n        extra_cycle);\n  }\n}\n\nvoid CycleRule::service_ready_q() {\n  if (wait_q_->can_pop() and ready_q_->can_push()) {\n    abi::instruction::Instruction *instruction = wait_q_->pop();\n    ready_q_->push(instruction);\n\n    for (auto &gp_reg : prev_write_gp_regs_[instruction->thread()->id()]) {\n      delete gp_reg;\n    }\n    prev_write_gp_regs_[instruction->thread()->id()].clear();\n\n    for (auto &gp_reg : cur_read_gp_regs_[instruction->thread()->id()]) {\n      delete gp_reg;\n    }\n    cur_read_gp_regs_[instruction->thread()->id()].clear();\n\n    prev_write_gp_regs_[instruction->thread()->id()] =\n        collect_write_gp_regs(instruction);\n  }\n}\n\nint CycleRule::calculate_extra_cycles(\n    abi::instruction::Instruction *instruction) {\n  cur_read_gp_regs_[instruction->thread()->id()] =\n      collect_read_gp_regs(instruction);\n\n  auto [even_counter, odd_counter] = calculate_counters(instruction);\n\n  return even_counter / 2 + odd_counter / 2;\n}\n\nstd::tuple<int, int> CycleRule::calculate_counters(\n    abi::instruction::Instruction *instruction) {\n  std::set<upmem_sim::abi::reg::GPReg *> registers =\n      merge(prev_write_gp_regs_[instruction->thread()->id()],\n            cur_read_gp_regs_[instruction->thread()->id()]);\n\n  int even_counter = 0;\n  int odd_counter = 0;\n  for (auto &register_ : registers) {\n    if (register_->index() % 2 == 0) {\n      even_counter += 1;\n    } else {\n      odd_counter += 1;\n    }\n  }\n  return {even_counter, odd_counter};\n}\n\nstd::set<abi::reg::GPReg *> CycleRule::collect_read_gp_regs(\n    abi::instruction::Instruction *instruction) {\n  abi::instruction::Suffix suffix = instruction->suffix();\n  if (suffix == abi::instruction::RICI or suffix == abi::instruction::RRI or\n      suffix == abi::instruction::RRIC or suffix == abi::instruction::RRICI or\n      suffix == abi::instruction::RRIF or suffix == abi::instruction::ZRI or\n      suffix == abi::instruction::ZRIC or suffix == abi::instruction::ZRICI or\n      suffix == abi::instruction::ZRIF or suffix == abi::instruction::S_RRI or\n      suffix == abi::instruction::U_RRI or suffix == abi::instruction::S_RRIC or\n      suffix == abi::instruction::U_RRIC or\n      suffix == abi::instruction::S_RRICI or\n      suffix == abi::instruction::U_RRICI or\n      suffix == abi::instruction::S_RRIF or\n      suffix == abi::instruction::U_RRIF or suffix == abi::instruction::RR or\n      suffix == abi::instruction::RRC or suffix == abi::instruction::RRCI or\n      suffix == abi::instruction::ZR or suffix == abi::instruction::ZRC or\n      suffix == abi::instruction::ZRCI or suffix == abi::instruction::S_RR or\n      suffix == abi::instruction::U_RR or suffix == abi::instruction::S_RRC or\n      suffix == abi::instruction::U_RRC or suffix == abi::instruction::S_RRCI or\n      suffix == abi::instruction::U_RRCI or suffix == abi::instruction::RIR or\n      suffix == abi::instruction::RIRC or suffix == abi::instruction::RIRCI or\n      suffix == abi::instruction::ZIR or suffix == abi::instruction::ZIRC or\n      suffix == abi::instruction::ZIRCI or suffix == abi::instruction::S_RIRC or\n      suffix == abi::instruction::U_RIRC or\n      suffix == abi::instruction::S_RIRCI or\n      suffix == abi::instruction::U_RIRCI or suffix == abi::instruction::ERRI or\n      suffix == abi::instruction::S_ERRI or\n      suffix == abi::instruction::U_ERRI or suffix == abi::instruction::EDRI or\n      suffix == abi::instruction::ERII) {\n    if (instruction->ra()->is_gp_reg()) {\n      return {new abi::reg::GPReg(instruction->ra()->gp_reg()->index())};\n    } else {\n      return {};\n    }\n  } else if (suffix == abi::instruction::RRR or\n             suffix == abi::instruction::RRRC or\n             suffix == abi::instruction::RRRCI or\n             suffix == abi::instruction::ZRR or\n             suffix == abi::instruction::ZRRC or\n             suffix == abi::instruction::ZRRCI or\n             suffix == abi::instruction::S_RRR or\n             suffix == abi::instruction::U_RRR or\n             suffix == abi::instruction::S_RRRC or\n             suffix == abi::instruction::U_RRRC or\n             suffix == abi::instruction::S_RRRCI or\n             suffix == abi::instruction::U_RRRCI or\n             suffix == abi::instruction::RRRI or\n             suffix == abi::instruction::RRRICI or\n             suffix == abi::instruction::ZRRI or\n             suffix == abi::instruction::ZRRICI or\n             suffix == abi::instruction::S_RRRI or\n             suffix == abi::instruction::U_RRRI or\n             suffix == abi::instruction::S_RRRICI or\n             suffix == abi::instruction::U_RRRICI or\n             suffix == abi::instruction::ERIR or\n             suffix == abi::instruction::DMA_RRI) {\n    if (instruction->ra()->is_gp_reg() and instruction->rb()->is_gp_reg()) {\n      return {new abi::reg::GPReg(instruction->ra()->gp_reg()->index()),\n              new abi::reg::GPReg(instruction->rb()->gp_reg()->index())};\n    } else if (instruction->ra()->is_gp_reg()) {\n      return {new abi::reg::GPReg(instruction->ra()->gp_reg()->index())};\n    } else if (instruction->rb()->is_gp_reg()) {\n      return {new abi::reg::GPReg(instruction->rb()->gp_reg()->index())};\n    } else {\n      return {};\n    }\n  } else if (suffix == abi::instruction::DRDICI or\n             suffix == abi::instruction::ERID) {\n    if (instruction->ra()->is_gp_reg()) {\n      return {new abi::reg::GPReg(instruction->ra()->gp_reg()->index()),\n              new abi::reg::GPReg(instruction->db()->even_reg()->index()),\n              new abi::reg::GPReg(instruction->db()->odd_reg()->index())};\n    } else {\n      return {new abi::reg::GPReg(instruction->db()->even_reg()->index()),\n              new abi::reg::GPReg(instruction->db()->odd_reg()->index())};\n    }\n  } else if (suffix == abi::instruction::R or suffix == abi::instruction::RCI or\n             suffix == abi::instruction::Z or suffix == abi::instruction::ZCI or\n             suffix == abi::instruction::S_R or\n             suffix == abi::instruction::U_R or\n             suffix == abi::instruction::S_RCI or\n             suffix == abi::instruction::U_RCI or\n             suffix == abi::instruction::CI or suffix == abi::instruction::I) {\n    return {};\n  } else if (suffix == abi::instruction::DDCI) {\n    return {new abi::reg::GPReg(instruction->db()->even_reg()->index()),\n            new abi::reg::GPReg(instruction->db()->odd_reg()->index())};\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nstd::set<abi::reg::GPReg *> CycleRule::collect_write_gp_regs(\n    abi::instruction::Instruction *instruction) {\n  abi::instruction::Suffix suffix = instruction->suffix();\n  if (suffix == abi::instruction::RICI or suffix == abi::instruction::ZRI or\n      suffix == abi::instruction::ZRIC or suffix == abi::instruction::ZRICI or\n      suffix == abi::instruction::ZRIF or suffix == abi::instruction::ZRR or\n      suffix == abi::instruction::ZRRC or suffix == abi::instruction::ZRRCI or\n      suffix == abi::instruction::ZR or suffix == abi::instruction::ZRC or\n      suffix == abi::instruction::ZRCI or suffix == abi::instruction::ZRRI or\n      suffix == abi::instruction::ZRRICI or suffix == abi::instruction::ZIR or\n      suffix == abi::instruction::ZIRC or suffix == abi::instruction::ZIRCI or\n      suffix == abi::instruction::Z or suffix == abi::instruction::ZCI or\n      suffix == abi::instruction::CI or suffix == abi::instruction::I or\n      suffix == abi::instruction::ERII or suffix == abi::instruction::ERIR or\n      suffix == abi::instruction::ERID or suffix == abi::instruction::DMA_RRI) {\n    return {};\n  } else if (suffix == abi::instruction::RRI or\n             suffix == abi::instruction::RRIC or\n             suffix == abi::instruction::RRICI or\n             suffix == abi::instruction::RRIF or\n             suffix == abi::instruction::RRR or\n             suffix == abi::instruction::RRRC or\n             suffix == abi::instruction::RRRCI or\n             suffix == abi::instruction::RR or\n             suffix == abi::instruction::RRC or\n             suffix == abi::instruction::RRCI or\n             suffix == abi::instruction::RRRI or\n             suffix == abi::instruction::RRRICI or\n             suffix == abi::instruction::RIR or\n             suffix == abi::instruction::RIRC or\n             suffix == abi::instruction::RIRCI or\n             suffix == abi::instruction::R or suffix == abi::instruction::RCI or\n             suffix == abi::instruction::ERRI) {\n    return {new abi::reg::GPReg(instruction->rc()->index())};\n  } else if (suffix == abi::instruction::S_RRI or\n             suffix == abi::instruction::U_RRI or\n             suffix == abi::instruction::S_RRIC or\n             suffix == abi::instruction::U_RRIC or\n             suffix == abi::instruction::S_RRICI or\n             suffix == abi::instruction::U_RRICI or\n             suffix == abi::instruction::S_RRIF or\n             suffix == abi::instruction::U_RRIF or\n             suffix == abi::instruction::S_RRR or\n             suffix == abi::instruction::U_RRR or\n             suffix == abi::instruction::S_RRRC or\n             suffix == abi::instruction::U_RRRC or\n             suffix == abi::instruction::S_RRRCI or\n             suffix == abi::instruction::U_RRRCI or\n             suffix == abi::instruction::S_RR or\n             suffix == abi::instruction::U_RR or\n             suffix == abi::instruction::S_RRC or\n             suffix == abi::instruction::U_RRC or\n             suffix == abi::instruction::S_RRCI or\n             suffix == abi::instruction::U_RRCI or\n             suffix == abi::instruction::DRDICI or\n             suffix == abi::instruction::S_RRRI or\n             suffix == abi::instruction::U_RRRI or\n             suffix == abi::instruction::S_RRRICI or\n             suffix == abi::instruction::U_RRRICI or\n             suffix == abi::instruction::S_RIRC or\n             suffix == abi::instruction::U_RIRC or\n             suffix == abi::instruction::S_RIRCI or\n             suffix == abi::instruction::U_RIRCI or\n             suffix == abi::instruction::S_R or\n             suffix == abi::instruction::U_R or\n             suffix == abi::instruction::DDCI or\n             suffix == abi::instruction::S_ERRI or\n             suffix == abi::instruction::U_ERRI or\n             suffix == abi::instruction::EDRI) {\n    return {new abi::reg::GPReg(instruction->dc()->even_reg()->index()),\n            new abi::reg::GPReg(instruction->dc()->odd_reg()->index())};\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nstd::set<abi::reg::GPReg *> CycleRule::merge(\n    std::set<abi::reg::GPReg *> regs1, std::set<abi::reg::GPReg *> regs2) {\n  std::set<abi::reg::GPReg *> regs;\n\n  auto finder = [&regs](RegIndex index) {\n    for (auto &reg : regs) {\n      if (reg->index() == index) {\n        return true;\n      }\n    }\n    return false;\n  };\n\n  for (auto &reg : regs1) {\n    if (not finder(reg->index())) {\n      regs.insert(reg);\n    }\n  }\n\n  for (auto &reg : regs2) {\n    if (not finder(reg->index())) {\n      regs.insert(reg);\n    }\n  }\n\n  return std::move(regs);\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/cycle_rule.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_CYCLE_RULE_H_\n#define UPMEM_SIM_SIMULATOR_DPU_CYCLE_RULE_H_\n\n#include \"abi/instruction/instruction.h\"\n#include \"simulator/basic/queue.h\"\n#include \"simulator/basic/timer_queue.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass CycleRule {\n public:\n  explicit CycleRule(util::ArgumentParser *argument_parser);\n  ~CycleRule();\n\n  util::StatFactory *stat_factory();\n\n  bool empty() {\n    return input_q_->empty() and wait_q_->empty() and ready_q_->empty();\n  }\n  bool can_push() { return input_q_->can_push(); }\n  void push(abi::instruction::Instruction *instruction);\n  bool can_pop() { return ready_q_->can_pop(); }\n  abi::instruction::Instruction *pop() { return ready_q_->pop(); }\n  void cycle();\n\n protected:\n  void service_input_q();\n  void service_ready_q();\n\n  int calculate_extra_cycles(abi::instruction::Instruction *instruction);\n  std::tuple<int, int> calculate_counters(\n      abi::instruction::Instruction *instruction);\n\n  static std::set<abi::reg::GPReg *> collect_read_gp_regs(\n      abi::instruction::Instruction *instruction);\n  static std::set<abi::reg::GPReg *> collect_write_gp_regs(\n      abi::instruction::Instruction *instruction);\n  static std::set<abi::reg::GPReg *> merge(std::set<abi::reg::GPReg *> regs1,\n                                           std::set<abi::reg::GPReg *> regs2);\n\n private:\n  basic::Queue<abi::instruction::Instruction> *input_q_;\n  basic::TimerQueue<abi::instruction::Instruction> *wait_q_;\n  basic::Queue<abi::instruction::Instruction> *ready_q_;\n\n  std::vector<std::set<abi::reg::GPReg *>> prev_write_gp_regs_;\n  std::vector<std::set<abi::reg::GPReg *>> cur_read_gp_regs_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dma.cc",
    "content": "#include \"simulator/dpu/dma.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nDMA::~DMA() {\n  delete input_q_;\n  delete ready_q_;\n}\n\nvoid DMA::connect_atomic(sram::Atomic *atomic) {\n  assert(atomic != nullptr);\n  assert(atomic_ == nullptr);\n\n  atomic_ = atomic;\n}\n\nvoid DMA::connect_iram(sram::IRAM *iram) {\n  assert(iram != nullptr);\n  assert(iram_ == nullptr);\n\n  iram_ = iram;\n}\n\nvoid DMA::connect_operand_collector(OperandCollector *operand_collector) {\n  assert(operand_collector != nullptr);\n  assert(operand_collector_ == nullptr);\n\n  operand_collector_ = operand_collector;\n}\n\nvoid DMA::connect_memory_controller(dram::MemoryController *memory_controller) {\n  assert(memory_controller != nullptr);\n  assert(memory_controller_ == nullptr);\n\n  memory_controller_ = memory_controller;\n}\n\nvoid DMA::transfer_to_atomic(Address address,\n                             encoder::ByteStream *byte_stream) {\n  for (int i = 0; i < byte_stream->size(); i++) {\n    assert(byte_stream->byte(i) == 0);\n  }\n}\n\nvoid DMA::transfer_to_iram(Address address, encoder::ByteStream *byte_stream) {\n  assert(address == iram_->address());\n  assert(byte_stream->size() % abi::word::InstructionWord().size() == 0);\n\n  int num_instructions = static_cast<int>(byte_stream->size() /\n                                          abi::word::InstructionWord().size());\n  for (int i = 0; i < num_instructions; i++) {\n    Address begin = i * abi::word::InstructionWord().size();\n    Address end = (i + 1) * abi::word::InstructionWord().size();\n\n    encoder::ByteStream *instruction_byte_stream =\n        byte_stream->slice(static_cast<int>(begin), static_cast<int>(end));\n    iram_->write(util::ConfigLoader::iram_offset() + begin,\n                 instruction_byte_stream);\n    delete instruction_byte_stream;\n  }\n}\n\nencoder::ByteStream *DMA::transfer_from_wram(Address address, Address size) {\n  auto byte_stream = new encoder::ByteStream();\n  for (int i = 0; i < size; i++) {\n    byte_stream->append(static_cast<int>(operand_collector_->lbu(address + i)));\n  }\n  return byte_stream;\n}\n\nvoid DMA::transfer_to_wram(Address address, encoder::ByteStream *byte_stream) {\n  for (int i = 0; i < byte_stream->size(); i++) {\n    operand_collector_->sb(address + i, byte_stream->byte(i));\n  }\n}\n\nencoder::ByteStream *DMA::transfer_from_mram(Address address, Address size) {\n  memory_controller_->flush();\n  std::vector<int> bytes = memory_controller_->read(address, size);\n  return new encoder::ByteStream(bytes);\n}\n\nvoid DMA::transfer_to_mram(Address address, encoder::ByteStream *byte_stream) {\n  memory_controller_->write(address, byte_stream->size(), byte_stream);\n}\n\nvoid DMA::transfer_from_wram_to_mram(\n    Address wram_address, Address mram_address, Address size,\n    abi::instruction::Instruction *instruction) {\n  assert(can_push());\n\n  encoder::ByteStream *byte_stream = transfer_from_wram(wram_address, size);\n\n  std::vector<int> bytes = byte_stream->bytes();\n\n  delete byte_stream;\n\n  auto dma_command = new DMACommand(DMACommand::WRITE, wram_address,\n                                    mram_address, size, bytes, instruction);\n  input_q_->push(dma_command);\n}\n\nvoid DMA::transfer_from_mram_to_wram(\n    Address wram_address, Address mram_address, Address size,\n    abi::instruction::Instruction *instruction) {\n  assert(can_push());\n\n  auto dma_command = new DMACommand(DMACommand::READ, wram_address,\n                                    mram_address, size, instruction);\n  input_q_->push(dma_command);\n}\n\nvoid DMA::cycle() {\n  service_input_q();\n  service_ready_q();\n}\n\nvoid DMA::service_input_q() {\n  if (input_q_->can_pop() and memory_controller_->can_push()) {\n    DMACommand *dma_command = input_q_->pop();\n    memory_controller_->push(dma_command);\n  }\n}\n\nvoid DMA::service_ready_q() {\n  if (memory_controller_->can_pop() and ready_q_->can_push()) {\n    DMACommand *dma_command = memory_controller_->pop();\n    ready_q_->push(dma_command);\n\n    if (dma_command->operation() == DMACommand::READ) {\n      auto byte_stream = new encoder::ByteStream(dma_command->bytes());\n\n      transfer_to_wram(dma_command->wram_address(), byte_stream);\n\n      delete byte_stream;\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dma.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_DMA_H_\n#define UPMEM_SIM_SIMULATOR_DPU_DMA_H_\n\n#include \"simulator/dpu/operand_collector.h\"\n#include \"simulator/dram/memory_controller.h\"\n#include \"simulator/sram/atomic.h\"\n#include \"simulator/sram/iram.h\"\n#include \"simulator/sram/wram.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass DMA {\n public:\n  explicit DMA()\n      : atomic_(nullptr),\n        iram_(nullptr),\n        operand_collector_(nullptr),\n        memory_controller_(nullptr),\n        input_q_(new basic::Queue<DMACommand>(\n            util::ConfigLoader::max_num_tasklets())),\n        ready_q_(new basic::Queue<DMACommand>(\n            util::ConfigLoader::max_num_tasklets())) {}\n  ~DMA();\n\n  void connect_atomic(sram::Atomic *atomic);\n  void connect_iram(sram::IRAM *iram);\n  void connect_operand_collector(OperandCollector *operand_collector);\n  void connect_memory_controller(dram::MemoryController *memory_controller);\n\n  void transfer_to_atomic(Address address, encoder::ByteStream *byte_stream);\n\n  void transfer_to_iram(Address address, encoder::ByteStream *byte_stream);\n\n  encoder::ByteStream *transfer_from_wram(Address address, Address size);\n  void transfer_to_wram(Address address, encoder::ByteStream *byte_stream);\n\n  encoder::ByteStream *transfer_from_mram(Address address, Address size);\n  void transfer_to_mram(Address address, encoder::ByteStream *byte_stream);\n\n  void transfer_from_wram_to_mram(Address wram_address, Address mram_address,\n                                  Address size,\n                                  abi::instruction::Instruction *instruction);\n  void transfer_from_mram_to_wram(Address wram_address, Address mram_address,\n                                  Address size,\n                                  abi::instruction::Instruction *instruction);\n\n  bool can_push() { return input_q_->can_push(); }\n  void push(DMACommand *dma_command) = delete;\n  bool can_pop() { return ready_q_->can_pop(); }\n  DMACommand *pop() { return ready_q_->pop(); }\n  void cycle();\n\n protected:\n  void service_input_q();\n  void service_ready_q();\n\n private:\n  sram::Atomic *atomic_;\n  sram::IRAM *iram_;\n  OperandCollector *operand_collector_;\n  dram::MemoryController *memory_controller_;\n\n  basic::Queue<DMACommand> *input_q_;\n  basic::Queue<DMACommand> *ready_q_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dma_command.cc",
    "content": "#include \"simulator/dpu/dma_command.h\"\n\n#include <iostream>\n\n#include \"abi/word/data_word.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nDMACommand::DMACommand(Operation operation, Address mram_address, Address size)\n    : operation_(operation),\n      wram_address_(nullptr),\n      mram_address_(new abi::word::DataAddressWord()),\n      size_(size),\n      instruction_(nullptr) {\n  assert(operation == READ);\n  assert(mram_address >= util::ConfigLoader::mram_offset());\n  assert(mram_address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(size % util::ConfigLoader::min_access_granularity() == 0);\n\n  mram_address_->set_value(mram_address);\n  bytes_.resize(size);\n  acks_.resize(size);\n}\n\nDMACommand::DMACommand(Operation operation, Address wram_address,\n                       Address mram_address, Address size,\n                       abi::instruction::Instruction *instruction)\n    : operation_(operation),\n      wram_address_(new abi::word::DataAddressWord()),\n      mram_address_(new abi::word::DataAddressWord()),\n      size_(size),\n      instruction_(instruction) {\n  assert(operation == READ);\n  assert(wram_address >= util::ConfigLoader::wram_offset());\n  assert(wram_address + size_ <=\n         util::ConfigLoader::wram_offset() + util::ConfigLoader::wram_size());\n  assert(mram_address >= util::ConfigLoader::mram_offset());\n  assert(mram_address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(size % util::ConfigLoader::min_access_granularity() == 0);\n  assert(instruction->op_code() == abi::instruction::LDMA);\n\n  wram_address_->set_value(wram_address);\n  mram_address_->set_value(mram_address);\n  bytes_.resize(size);\n  acks_.resize(size);\n}\n\nDMACommand::DMACommand(Operation operation, Address mram_address, Address size,\n                       std::vector<int> bytes)\n    : operation_(operation),\n      wram_address_(nullptr),\n      mram_address_(new abi::word::DataAddressWord()),\n      size_(size),\n      bytes_(bytes),\n      instruction_(nullptr) {\n  assert(operation == WRITE);\n  assert(mram_address >= util::ConfigLoader::mram_offset());\n  assert(mram_address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(size % util::ConfigLoader::min_access_granularity() == 0);\n  assert(size == bytes.size());\n\n  mram_address_->set_value(mram_address);\n  bytes_.resize(size);\n  acks_.resize(size);\n}\n\nDMACommand::DMACommand(Operation operation, Address wram_address,\n                       Address mram_address, Address size,\n                       std::vector<int> bytes,\n                       abi::instruction::Instruction *instruction)\n    : operation_(operation),\n      wram_address_(new abi::word::DataAddressWord()),\n      mram_address_(new abi::word::DataAddressWord()),\n      size_(size),\n      bytes_(bytes),\n      instruction_(instruction) {\n  assert(operation == WRITE);\n  assert(wram_address >= util::ConfigLoader::wram_offset());\n  assert(wram_address + size_ <=\n         util::ConfigLoader::wram_offset() + util::ConfigLoader::wram_size());\n  assert(mram_address >= util::ConfigLoader::mram_offset());\n  assert(mram_address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(size % util::ConfigLoader::min_access_granularity() == 0);\n  assert(size == bytes.size());\n  assert(instruction->op_code() == abi::instruction::SDMA);\n\n  wram_address_->set_value(wram_address);\n  mram_address_->set_value(mram_address);\n  bytes_.resize(size);\n  acks_.resize(size);\n}\n\nDMACommand::~DMACommand() {\n  assert(is_ready());\n\n  delete wram_address_;\n  delete mram_address_;\n}\n\nabi::instruction::Instruction *DMACommand::instruction() {\n  assert(has_instruction());\n  return instruction_;\n}\n\nstd::vector<int> DMACommand::bytes() {\n  if (operation_ == READ) {\n    assert(is_ready());\n  }\n\n  return bytes_;\n}\n\nstd::vector<int> DMACommand::bytes(Address mram_address, Address size) {\n  std::vector<int> bytes;\n  bytes.resize(size);\n  std::copy(bytes_.begin() + index(mram_address),\n            bytes_.begin() + index(mram_address) + size, bytes.begin());\n  return std::move(bytes);\n}\n\nvoid DMACommand::set_bytes(Address mram_address, Address size,\n                           std::vector<int> bytes) {\n  assert(size == bytes.size());\n\n  std::copy(bytes.begin(), bytes.end(), bytes_.begin() + index(mram_address));\n}\n\nvoid DMACommand::ack_bytes(Address mram_address, Address size) {\n  for (int i = 0; i < size; i++) {\n    assert(not acks_[index(mram_address) + i]);\n    acks_[index(mram_address) + i] = true;\n  }\n}\n\nint DMACommand::index(Address mram_address) {\n  assert(this->mram_address() <= mram_address and\n         mram_address <= this->mram_address() + size_);\n\n  return static_cast<int>(mram_address - this->mram_address());\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dma_command.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_DMA_COMMAND_H_\n#define UPMEM_SIM_SIMULATOR_DPU_DMA_COMMAND_H_\n\n#include <algorithm>\n\n#include \"abi/instruction/instruction.h\"\n#include \"abi/word/data_address_word.h\"\n#include \"abi/word/data_word.h\"\n#include \"main.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass DMACommand {\n public:\n  enum Operation { READ = 0, WRITE };\n\n  explicit DMACommand(Operation operation, Address mram_address, Address size);\n  explicit DMACommand(Operation operation, Address wram_address,\n                      Address mram_address, Address size,\n                      abi::instruction::Instruction *instruction);\n  explicit DMACommand(Operation operation, Address mram_address, Address size,\n                      std::vector<int> bytes);\n  explicit DMACommand(Operation operation, Address wram_address,\n                      Address mram_address, Address size,\n                      std::vector<int> bytes,\n                      abi::instruction::Instruction *instruction);\n  ~DMACommand();\n\n  Operation operation() { return operation_; }\n  Address wram_address() { return wram_address_->address(); }\n  Address mram_address() { return mram_address_->address(); }\n  Address size() { return size_; }\n  bool has_instruction() { return instruction_ != nullptr; }\n  abi::instruction::Instruction *instruction();\n\n  std::vector<int> bytes();\n  std::vector<int> bytes(Address mram_address, Address size);\n\n  void set_bytes(Address mram_address, Address size, std::vector<int> bytes);\n  void ack_bytes(Address mram_address, Address size);\n\n  bool is_ready() {\n    return std::all_of(acks_.begin(), acks_.end(),\n                       [](bool ack) { return ack; });\n  }\n\n protected:\n  int index(Address mram_address);\n\n private:\n  Operation operation_;\n  abi::word::DataAddressWord *wram_address_;\n  abi::word::DataAddressWord *mram_address_;\n  Address size_;\n  abi::instruction::Instruction *instruction_;\n  std::vector<int> bytes_;\n  std::vector<bool> acks_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dpu.cc",
    "content": "#include \"simulator/dpu/dpu.h\"\n\n#include <cmath>\n#include <iostream>\n\nnamespace upmem_sim::simulator::dpu {\n\nDPU::DPU(DPUID dpu_id, util::ArgumentParser *argument_parser)\n    : dpu_id_(dpu_id),\n      atomic_(new sram::Atomic()),\n      iram_(new sram::IRAM()),\n      wram_(new sram::WRAM()),\n      mram_(new dram::MRAM(argument_parser)),\n      logic_(new Logic(dpu_id, argument_parser)),\n      dma_(new DMA()),\n      operand_collector_(new OperandCollector()),\n      memory_controller_(new dram::MemoryController(argument_parser)),\n      stat_factory_(new util::StatFactory(\"DPU#\" + std::to_string(dpu_id))) {\n  int num_threads =\n      static_cast<int>(argument_parser->get_int_parameter(\"num_tasklets\"));\n\n  assert(0 <= num_threads and\n         num_threads <= util::ConfigLoader::max_num_tasklets());\n\n  threads_.resize(num_threads);\n  for (ThreadID id = 0; id < num_threads; id++) {\n    threads_[id] = new Thread(id);\n  }\n\n  scheduler_ = new RevolverScheduler(argument_parser, threads_);\n\n  logic_->connect_scheduler(scheduler_);\n  logic_->connect_atomic(atomic_);\n  logic_->connect_iram(iram_);\n  logic_->connect_operand_collector(operand_collector_);\n  logic_->connect_dma(dma_);\n\n  dma_->connect_atomic(atomic_);\n  dma_->connect_iram(iram_);\n  dma_->connect_operand_collector(operand_collector_);\n  dma_->connect_memory_controller(memory_controller_);\n\n  operand_collector_->connect_wram(wram_);\n\n  memory_controller_->connect_mram(mram_);\n\n  logic_frequency_ =\n      static_cast<int>(argument_parser->get_int_parameter(\"logic_frequency\"));\n  memory_frequency_ =\n      static_cast<int>(argument_parser->get_int_parameter(\"memory_frequency\"));\n  frequency_ratio_ = static_cast<double>(memory_frequency_) /\n                     static_cast<double>(logic_frequency_);\n}\n\nDPU::~DPU() {\n  for (auto &thread : threads_) {\n    delete thread;\n  }\n\n  delete scheduler_;\n  delete atomic_;\n  delete iram_;\n  delete wram_;\n  delete mram_;\n  delete logic_;\n  delete dma_;\n  delete operand_collector_;\n  delete memory_controller_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *DPU::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  util::StatFactory *logic_stat_factory = logic_->stat_factory();\n  util::StatFactory *memory_stat_factory = memory_controller_->stat_factory();\n\n  for (auto &thread : threads_) {\n    std::map<ThreadStatus, int64_t> status_tracker = thread->status_tracker();\n    for (const auto &stat : status_tracker) {\n      stat_factory_->increment(\n          std::to_string(thread->id()) + \"_latency_breakdown_\" + stat.first,\n          stat.second);\n    }\n  }\n\n  stat_factory->merge(stat_factory_);\n  stat_factory->merge(logic_stat_factory);\n  stat_factory->merge(memory_stat_factory);\n\n  delete logic_stat_factory;\n  delete memory_stat_factory;\n\n  return stat_factory;\n}\n\nbool DPU::is_zombie() {\n  for (auto &thread : threads_) {\n    if (thread->state() != Thread::ZOMBIE) {\n      return false;\n    }\n  }\n\n  return logic_->empty() and memory_controller_->empty();\n}\n\nvoid DPU::cycle() {\n  scheduler_->cycle();\n  logic_->cycle();\n  dma_->cycle();\n  int num_memory_cycles = static_cast<int>(\n      floor(frequency_ratio_ *\n            static_cast<double>(stat_factory_->value(\"cycle\"))) -\n      floor(frequency_ratio_ *\n            static_cast<double>(stat_factory_->value(\"cycle\") - 1)));\n  for (int i = 0; i < num_memory_cycles; i++) {\n    memory_controller_->cycle();\n  }\n\n  stat_factory_->increment(\"cycle\");\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/dpu.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_DPU_H_\n#define UPMEM_SIM_SIMULATOR_DPU_DPU_H_\n\n#include \"simulator/dpu/dma.h\"\n#include \"simulator/dpu/logic.h\"\n#include \"simulator/dpu/operand_collector.h\"\n#include \"simulator/dram/memory_controller.h\"\n#include \"simulator/dram/mram.h\"\n#include \"simulator/sram/atomic.h\"\n#include \"simulator/sram/iram.h\"\n#include \"simulator/sram/wram.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass DPU {\n public:\n  explicit DPU(DPUID dpu_id, util::ArgumentParser *argument_parser);\n  ~DPU();\n\n  DPUID dpu_id() { return dpu_id_; }\n\n  RevolverScheduler *scheduler() { return scheduler_; }\n  DMA *dma() { return dma_; }\n\n  util::StatFactory *stat_factory();\n\n  bool is_zombie();\n  void boot() { scheduler_->boot(0); }\n  void cycle();\n\n private:\n  DPUID dpu_id_;\n\n  std::vector<Thread *> threads_;\n\n  RevolverScheduler *scheduler_;\n  sram::Atomic *atomic_;\n  sram::IRAM *iram_;\n  sram::WRAM *wram_;\n  dram::MRAM *mram_;\n  Logic *logic_;\n  DMA *dma_;\n  OperandCollector *operand_collector_;\n  dram::MemoryController *memory_controller_;\n\n  int logic_frequency_;\n  int memory_frequency_;\n  double frequency_ratio_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/logic.cc",
    "content": "#include \"simulator/dpu/logic.h\"\n\n#include <cmath>\n#include <functional>\n#include <iostream>\n\n#include \"converter/instruction_converter.h\"\n#include \"converter/reg_file_converter.h\"\n#include \"simulator/dpu/alu.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nLogic::~Logic() {\n  delete pipeline_;\n  delete cycle_rule_;\n  delete wait_instruction_q_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *Logic::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  util::StatFactory *cycle_rule_stat_factory = cycle_rule_->stat_factory();\n  util::StatFactory *scheduler_stat_factory =\n      scheduler_->stat_factory();\n\n  stat_factory->merge(stat_factory_);\n  stat_factory->merge(cycle_rule_stat_factory);\n  stat_factory->merge(scheduler_stat_factory);\n\n  delete cycle_rule_stat_factory;\n  delete scheduler_stat_factory;\n\n  return stat_factory;\n}\n\nvoid Logic::connect_scheduler(RevolverScheduler *scheduler) {\n  assert(scheduler != nullptr);\n  assert(scheduler_ == nullptr);\n\n  scheduler_ = scheduler;\n}\n\nvoid Logic::connect_atomic(sram::Atomic *atomic) {\n  assert(atomic != nullptr);\n  assert(atomic_ == nullptr);\n\n  atomic_ = atomic;\n}\n\nvoid Logic::connect_iram(sram::IRAM *iram) {\n  assert(iram != nullptr);\n  assert(iram_ == nullptr);\n\n  iram_ = iram;\n}\n\nvoid Logic::connect_operand_collector(OperandCollector *operand_collector) {\n  assert(operand_collector != nullptr);\n  assert(operand_collector_ == nullptr);\n\n  operand_collector_ = operand_collector;\n}\n\nvoid Logic::connect_dma(DMA *dma) {\n  assert(dma != nullptr);\n  assert(dma_ == nullptr);\n\n  dma_ = dma;\n}\n\nvoid Logic::cycle() {\n  stat_factory_->overwrite(\"mram_address\", -1);        \n  stat_factory_->overwrite(\"mram_access_thread\", -1);  \n  stat_factory_->overwrite(\"mram_access_size\", -1); \n\n  service_scheduler();\n\n  service_pipeline();\n  service_cycle_rule();\n  service_logic();\n\n  service_dma();\n\n  pipeline_->cycle();\n  cycle_rule_->cycle();\n\n  stat_factory_->increment(\"logic_cycle\");\n}\n\nvoid Logic::service_scheduler() {\n  if (pipeline_->can_push() and cycle_rule_->can_push() and\n      wait_instruction_q_->can_push()) {\n    // if (pipeline_->can_push() and wait_instruction_q_->can_push()) {\n    Thread *thread = scheduler_->schedule();\n    if (thread != nullptr) {\n      int chosen_thread_id = thread->id();\n      abi::instruction::Instruction *instruction =\n          iram_->read(thread->reg_file()->read_pc_reg());\n      instruction->set_thread(thread);\n      pipeline_->push(instruction);\n\n      if (instruction->suffix() != abi::instruction::DMA_RRI) {\n        if (verbose_ >= 1) {\n          std::cout << \"{\" << dpu_id_ << \"}\";\n          std::cout << converter::InstructionConverter::to_string(instruction) << std::endl;\n        }\n        \n        execute_instruction(instruction);\n\n        if (verbose_ >= 2) {\n          std::cout << converter::RegFileConverter::to_string(instruction->thread()->reg_file()) << std::endl;\n        }\n      } else {\n        scheduler_->block(thread->id());\n        instruction->thread()->reg_file()->increment_pc_reg();\n        wait_instruction_q_->push(instruction);\n      }\n\n      stat_factory_->increment(\"num_instructions\");\n      stat_factory_->increment(std::to_string(instruction->thread()->id()) +\n                               \"_num_instructions\");\n\n      for (auto &th : scheduler_->threads()) {\n        if (th->state() == Thread::BLOCK) {\n          th->update_thread_status(\"WAIT_DATA\", 1);\n        } else if (th->state() == Thread::RUNNABLE and\n                   chosen_thread_id != th->id()) {\n          th->update_thread_status(\"WAIT_SCHEDULE\", 1);\n        }\n      }\n    } else {\n      for (auto &th : scheduler_->threads()) {\n        if (th->state() == Thread::BLOCK) {\n          th->update_thread_status(\"WAIT_DATA\", 1);\n        }\n      }\n    }\n\n    stat_factory_->increment(\"active_tasklets_\" +\n                  std::to_string(scheduler_->get_issuable_threads()));\n\n  } else {\n    stat_factory_->increment(\"backpressuer\");\n    stat_factory_->increment(\"active_tasklets_\" + std::to_string(0));\n  }\n}\n\nvoid Logic::service_pipeline() {\n  if (pipeline_->can_pop() and cycle_rule_->can_push()) {\n    abi::instruction::Instruction *instruction = pipeline_->pop();\n\n    if (instruction != nullptr) {\n      abi::instruction::Suffix suffix = instruction->suffix();\n      if (suffix == abi::instruction::ERRI or\n          suffix == abi::instruction::EDRI or\n          suffix == abi::instruction::ERII or\n          suffix == abi::instruction::ERIR or\n          suffix == abi::instruction::ERID) {  // spm access\n        instruction->thread()->update_thread_status(\"SPM_ACCESS\",\n                                                    num_pipeline_stages_);\n      } else if (suffix == abi::instruction::RICI) {  // sync\n        instruction->thread()->update_thread_status(\"WAIT_SYNC\",\n                                                    num_pipeline_stages_);\n      } else if (suffix != abi::instruction::DMA_RRI) {\n        instruction->thread()->update_thread_status(\"ARITHMETIC\",\n                                                    num_pipeline_stages_);\n      }\n\n      cycle_rule_->push(instruction);\n    }\n  }\n}\n\nvoid Logic::service_cycle_rule() {\n  if (cycle_rule_->can_pop()) {\n    abi::instruction::Instruction *instruction = cycle_rule_->pop();\n\n    if (instruction->suffix() != abi::instruction::DMA_RRI) {\n      delete instruction;\n    } else {\n      if (verbose_ >= 1) {\n        std::cout << \"{\" << dpu_id_ << \"}\";\n        std::cout << converter::InstructionConverter::to_string(instruction) << std::endl;\n      }\n      execute_instruction(instruction);\n\n      if (verbose_ >= 2) {\n        std::cout << converter::RegFileConverter::to_string(instruction->thread()->reg_file()) << std::endl;\n      }\n    }\n  }\n}\n\nvoid Logic::service_logic() {}\n\nvoid Logic::service_dma() {\n  if (wait_instruction_q_->can_pop() and dma_->can_pop()) {\n    DMACommand *dma_command = dma_->pop();\n    abi::instruction::Instruction *instruction = wait_instruction_q_->pop();\n\n    assert(dma_command->instruction() == instruction);\n\n    scheduler_->awake(instruction->thread()->id());\n\n    delete dma_command;\n    delete instruction;\n  }\n}\n\nvoid Logic::execute_instruction(abi::instruction::Instruction *instruction) {\n  abi::instruction::Suffix suffix = instruction->suffix();\n\n  if (suffix == abi::instruction::RICI) {\n    execute_rici(instruction);\n  } else if (suffix == abi::instruction::RRI) {\n    execute_rri(instruction);\n  } else if (suffix == abi::instruction::RRIC) {\n    execute_rric(instruction);\n  } else if (suffix == abi::instruction::RRICI) {\n    execute_rrici(instruction);\n  } else if (suffix == abi::instruction::RRIF) {\n    execute_rrif(instruction);\n  } else if (suffix == abi::instruction::RRR) {\n    execute_rrr(instruction);\n  } else if (suffix == abi::instruction::RRRC) {\n    execute_rrrc(instruction);\n  } else if (suffix == abi::instruction::RRRCI) {\n    execute_rrrci(instruction);\n  } else if (suffix == abi::instruction::ZRI) {\n    execute_zri(instruction);\n  } else if (suffix == abi::instruction::ZRIC) {\n    execute_zric(instruction);\n  } else if (suffix == abi::instruction::ZRICI) {\n    execute_zrici(instruction);\n  } else if (suffix == abi::instruction::ZRIF) {\n    execute_zrif(instruction);\n  } else if (suffix == abi::instruction::ZRR) {\n    execute_zrr(instruction);\n  } else if (suffix == abi::instruction::ZRRC) {\n    execute_zrrc(instruction);\n  } else if (suffix == abi::instruction::ZRRCI) {\n    execute_zrrci(instruction);\n  } else if (suffix == abi::instruction::S_RRI) {\n    execute_s_rri(instruction);\n  } else if (suffix == abi::instruction::S_RRIC) {\n    execute_s_rric(instruction);\n  } else if (suffix == abi::instruction::S_RRICI) {\n    execute_s_rrici(instruction);\n  } else if (suffix == abi::instruction::S_RRIF) {\n    execute_s_rrif(instruction);\n  } else if (suffix == abi::instruction::S_RRR) {\n    execute_s_rrr(instruction);\n  } else if (suffix == abi::instruction::S_RRRC) {\n    execute_s_rrrc(instruction);\n  } else if (suffix == abi::instruction::S_RRRCI) {\n    execute_s_rrrci(instruction);\n  } else if (suffix == abi::instruction::U_RRI) {\n    execute_u_rri(instruction);\n  } else if (suffix == abi::instruction::U_RRIC) {\n    execute_u_rric(instruction);\n  } else if (suffix == abi::instruction::U_RRICI) {\n    execute_u_rrici(instruction);\n  } else if (suffix == abi::instruction::U_RRIF) {\n    execute_u_rrif(instruction);\n  } else if (suffix == abi::instruction::U_RRR) {\n    execute_u_rrr(instruction);\n  } else if (suffix == abi::instruction::U_RRRC) {\n    execute_u_rrrc(instruction);\n  } else if (suffix == abi::instruction::U_RRRCI) {\n    execute_u_rrrci(instruction);\n  } else if (suffix == abi::instruction::RR) {\n    execute_rr(instruction);\n  } else if (suffix == abi::instruction::RRC) {\n    execute_rrc(instruction);\n  } else if (suffix == abi::instruction::RRCI) {\n    execute_rrci(instruction);\n  } else if (suffix == abi::instruction::ZR) {\n    execute_zr(instruction);\n  } else if (suffix == abi::instruction::ZRC) {\n    execute_zrc(instruction);\n  } else if (suffix == abi::instruction::ZRCI) {\n    execute_zrci(instruction);\n  } else if (suffix == abi::instruction::S_RR) {\n    execute_s_rr(instruction);\n  } else if (suffix == abi::instruction::S_RRC) {\n    execute_s_rrc(instruction);\n  } else if (suffix == abi::instruction::S_RRCI) {\n    execute_s_rrci(instruction);\n  } else if (suffix == abi::instruction::U_RR) {\n    execute_u_rr(instruction);\n  } else if (suffix == abi::instruction::U_RRC) {\n    execute_u_rrc(instruction);\n  } else if (suffix == abi::instruction::U_RRCI) {\n    execute_u_rrci(instruction);\n  } else if (suffix == abi::instruction::DRDICI) {\n    execute_drdici(instruction);\n  } else if (suffix == abi::instruction::RRRI) {\n    execute_rrri(instruction);\n  } else if (suffix == abi::instruction::RRRICI) {\n    execute_rrrici(instruction);\n  } else if (suffix == abi::instruction::ZRRI) {\n    execute_zrri(instruction);\n  } else if (suffix == abi::instruction::ZRRICI) {\n    execute_zrrici(instruction);\n  } else if (suffix == abi::instruction::S_RRRI) {\n    execute_s_rrri(instruction);\n  } else if (suffix == abi::instruction::S_RRRICI) {\n    execute_s_rrrici(instruction);\n  } else if (suffix == abi::instruction::U_RRRI) {\n    execute_u_rrri(instruction);\n  } else if (suffix == abi::instruction::U_RRRICI) {\n    execute_u_rrrici(instruction);\n  } else if (suffix == abi::instruction::RIR) {\n    execute_rir(instruction);\n  } else if (suffix == abi::instruction::RIRC) {\n    execute_rirc(instruction);\n  } else if (suffix == abi::instruction::RIRCI) {\n    execute_rirci(instruction);\n  } else if (suffix == abi::instruction::ZIR) {\n    execute_zir(instruction);\n  } else if (suffix == abi::instruction::ZIRC) {\n    execute_zirc(instruction);\n  } else if (suffix == abi::instruction::ZIRCI) {\n    execute_zirci(instruction);\n  } else if (suffix == abi::instruction::S_RIRC) {\n    execute_s_rirc(instruction);\n  } else if (suffix == abi::instruction::S_RIRCI) {\n    execute_s_rirci(instruction);\n  } else if (suffix == abi::instruction::U_RIRC) {\n    execute_u_rirc(instruction);\n  } else if (suffix == abi::instruction::U_RIRCI) {\n    execute_u_rirci(instruction);\n  } else if (suffix == abi::instruction::R) {\n    execute_r(instruction);\n  } else if (suffix == abi::instruction::RCI) {\n    execute_rci(instruction);\n  } else if (suffix == abi::instruction::Z) {\n    execute_z(instruction);\n  } else if (suffix == abi::instruction::ZCI) {\n    execute_zci(instruction);\n  } else if (suffix == abi::instruction::S_R) {\n    execute_s_r(instruction);\n  } else if (suffix == abi::instruction::S_RCI) {\n    execute_s_rci(instruction);\n  } else if (suffix == abi::instruction::U_R) {\n    execute_u_r(instruction);\n  } else if (suffix == abi::instruction::U_RCI) {\n    execute_u_rci(instruction);\n  } else if (suffix == abi::instruction::CI) {\n    execute_ci(instruction);\n  } else if (suffix == abi::instruction::I) {\n    execute_i(instruction);\n  } else if (suffix == abi::instruction::DDCI) {\n    execute_ddci(instruction);\n  } else if (suffix == abi::instruction::ERRI) {\n    execute_erri(instruction);\n  } else if (suffix == abi::instruction::S_ERRI) {\n    execute_s_erri(instruction);\n  } else if (suffix == abi::instruction::U_ERRI) {\n    execute_u_erri(instruction);\n  } else if (suffix == abi::instruction::EDRI) {\n    execute_edri(instruction);\n  } else if (suffix == abi::instruction::ERII) {\n    execute_erii(instruction);\n  } else if (suffix == abi::instruction::ERIR) {\n    execute_erir(instruction);\n  } else if (suffix == abi::instruction::ERID) {\n    execute_erid(instruction);\n  } else if (suffix == abi::instruction::DMA_RRI) {\n    execute_dma_rri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_rici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::acquire_rici_op_codes().count(op_code)) {\n    execute_acquire_rici(instruction);\n  } else if (abi::instruction::Instruction::release_rici_op_codes().count(\n                 op_code)) {\n    execute_release_rici(instruction);\n  } else if (abi::instruction::Instruction::boot_rici_op_codes().count(\n                 op_code)) {\n    execute_boot_rici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_acquire_rici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::acquire_rici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::UNSIGNED);\n  int64_t imm = instruction->imm()->value();\n  Address atomic_address = ALU::atomic_address_hash(ra, imm);\n\n  bool can_acquire = atomic_->can_acquire(atomic_address);\n  if (can_acquire) {\n    atomic_->acquire(atomic_address, instruction->thread()->id());\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_acquire_cc(instruction, not can_acquire);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, not can_acquire, false);\n}\n\nvoid Logic::execute_release_rici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::release_rici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::UNSIGNED);\n  int64_t imm = instruction->imm()->value();\n  Address atomic_address = ALU::atomic_address_hash(ra, imm);\n\n  bool can_release =\n      atomic_->can_release(atomic_address, instruction->thread()->id());\n  if (can_release) {\n    atomic_->release(atomic_address, instruction->thread()->id());\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_acquire_cc(instruction, not can_release);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, not can_release, false);\n}\n\nvoid Logic::execute_boot_rici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::boot_rici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::UNSIGNED);\n  int64_t imm = instruction->imm()->value();\n  Address thread_id = ALU::atomic_address_hash(ra, imm);\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::BOOT) {\n    bool can_boot = scheduler_->boot(static_cast<ThreadID>(thread_id));\n    set_boot_cc(instruction, ra, not can_boot);\n    set_flags(instruction, not can_boot, false);\n  } else if (op_code == abi::instruction::RESUME) {\n    bool can_resume = scheduler_->awake(static_cast<ThreadID>(thread_id));\n    set_boot_cc(instruction, ra, not can_resume);\n    set_flags(instruction, not can_resume, false);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n}\n\nvoid Logic::execute_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    execute_add_rri(instruction);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    execute_asr_rri(instruction);\n  } else if (abi::instruction::Instruction::call_rri_op_codes().count(\n                 op_code)) {\n    execute_call_rri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_call_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::call_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  Address result;\n  bool carry;\n  bool overflow;\n  if (imm == 0) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else {\n    std::tie(result, carry, overflow) =\n        ALU::add(ra * abi::word::InstructionWord().size(), imm);\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  Address pc = instruction->thread()->reg_file()->read_pc_reg();\n  instruction->thread()->reg_file()->write_gp_reg(\n      instruction->rc(), pc + abi::word::InstructionWord().size());\n\n  instruction->thread()->reg_file()->write_pc_reg(result);\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRIC);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rric_op_codes().count(op_code)) {\n    execute_add_rric(instruction);\n  } else if (abi::instruction::Instruction::asr_rric_op_codes().count(\n                 op_code)) {\n    execute_asr_rric(instruction);\n  } else if (abi::instruction::Instruction::sub_rric_op_codes().count(\n                 op_code)) {\n    execute_sub_rric(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_rric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_rric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_rric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_ext_sub_set_cc(instruction, ra, imm, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code)) {\n    execute_add_rrici(instruction);\n  } else if (abi::instruction::Instruction::and_rrici_op_codes().count(\n                 op_code)) {\n    execute_and_rrici(instruction);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    execute_asr_rrici(instruction);\n  } else if (abi::instruction::Instruction::sub_rrici_op_codes().count(\n                 op_code)) {\n    execute_sub_rrici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_imm_shift_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rrif(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRIF);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rrr(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrr_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CALL) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  if (op_code == abi::instruction::CALL) {\n    Address pc = instruction->thread()->reg_file()->read_pc_reg();\n    instruction->thread()->reg_file()->write_gp_reg(\n        instruction->rc(), pc + abi::word::InstructionWord().size());\n    instruction->thread()->reg_file()->write_pc_reg(result);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRC);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrrc_op_codes().count(op_code)) {\n    execute_add_rrrc(instruction);\n  } else if (abi::instruction::Instruction::rsub_rrrc_op_codes().count(\n                 op_code)) {\n    execute_rsub_rrrc(instruction);\n  } else if (abi::instruction::Instruction::sub_rrrc_op_codes().count(\n                 op_code)) {\n    execute_sub_rrrc(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_rrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rsub_rrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rsub_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_set_cc(instruction, ra, rb, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_sub_rrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_ext_sub_set_cc(instruction, ra, rb, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrrci_op_codes().count(op_code)) {\n    execute_add_rrrci(instruction);\n  } else if (abi::instruction::Instruction::and_rrrci_op_codes().count(\n                 op_code)) {\n    execute_and_rrrci(instruction);\n  } else if (abi::instruction::Instruction::asr_rrrci_op_codes().count(\n                 op_code)) {\n    execute_asr_rrrci(instruction);\n  } else if (abi::instruction::Instruction::mul_rrrci_op_codes().count(\n                 op_code)) {\n    execute_mul_rrrci(instruction);\n  } else if (abi::instruction::Instruction::rsub_rrrci_op_codes().count(\n                 op_code)) {\n    execute_rsub_rrrci(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_mul_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::mul_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_mul_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_rsub_rrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rsub_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, rb, result, carry, overflow);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_zri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    execute_add_zri(instruction);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    execute_asr_zri(instruction);\n  } else if (abi::instruction::Instruction::call_rri_op_codes().count(\n                 op_code)) {\n    execute_call_zri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_zri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_zri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_call_zri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::call_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  Address result;\n  bool carry;\n  bool overflow;\n  if (imm == 0) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else {\n    std::tie(result, carry, overflow) =\n        ALU::add(ra * abi::word::InstructionWord().size(), imm);\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  Address pc = instruction->thread()->reg_file()->read_pc_reg();\n  instruction->thread()->reg_file()->write_pc_reg(result);\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRIC);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rric_op_codes().count(op_code)) {\n    execute_add_zric(instruction);\n  } else if (abi::instruction::Instruction::asr_rric_op_codes().count(\n                 op_code)) {\n    execute_asr_zric(instruction);\n  } else if (abi::instruction::Instruction::sub_rric_op_codes().count(\n                 op_code)) {\n    execute_sub_zric(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_zric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_zric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_zric(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rric_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRIC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_ext_sub_set_cc(instruction, ra, imm, result, carry, overflow);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_zrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code)) {\n    execute_add_zrici(instruction);\n  } else if (abi::instruction::Instruction::and_rrici_op_codes().count(\n                 op_code)) {\n    execute_and_zrici(instruction);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    execute_asr_zrici(instruction);\n  } else if (abi::instruction::Instruction::sub_rrici_op_codes().count(\n                 op_code)) {\n    execute_sub_zrici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_zrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_zrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_zrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_imm_shift_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_zrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrif(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRIF);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrr(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrr_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CALL) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  if (op_code == abi::instruction::CALL) {\n    instruction->thread()->reg_file()->write_pc_reg(result);\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRC);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrrc_op_codes().count(op_code)) {\n    execute_add_zrrc(instruction);\n  } else if (abi::instruction::Instruction::rsub_rrrc_op_codes().count(\n                 op_code)) {\n    execute_rsub_zrrc(instruction);\n  } else if (abi::instruction::Instruction::sub_rrrc_op_codes().count(\n                 op_code)) {\n    execute_sub_zrrc(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_zrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rsub_zrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rsub_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_set_cc(instruction, ra, rb, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_sub_zrrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_ext_sub_set_cc(instruction, ra, rb, result, carry, overflow);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrrci_op_codes().count(op_code)) {\n    execute_add_zrrci(instruction);\n  } else if (abi::instruction::Instruction::and_rrrci_op_codes().count(\n                 op_code)) {\n    execute_and_zrrci(instruction);\n  } else if (abi::instruction::Instruction::asr_rrrci_op_codes().count(\n                 op_code)) {\n    execute_asr_zrrci(instruction);\n  } else if (abi::instruction::Instruction::mul_rrrci_op_codes().count(\n                 op_code)) {\n    execute_mul_zrrci(instruction);\n  } else if (abi::instruction::Instruction::rsub_rrrci_op_codes().count(\n                 op_code)) {\n    execute_rsub_zrrci(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, rb);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, rb);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, rb);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, rb);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, rb);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, rb);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, rb);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, rb);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, rb);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, rb);\n  } else if (op_code == abi::instruction::CMPB4) {\n    result = ALU::cmpb4(ra, rb);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, rb);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, rb);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, rb);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, rb);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, rb);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, rb);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, rb);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, rb);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, rb);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_mul_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::mul_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::MUL_SH_SH) {\n    result = ALU::mul_sh_sh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_SL) {\n    result = ALU::mul_sh_sl(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_UH) {\n    result = ALU::mul_sh_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SH_UL) {\n    result = ALU::mul_sh_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_SH) {\n    result = ALU::mul_sl_sh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_SL) {\n    result = ALU::mul_sl_sl(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_UH) {\n    result = ALU::mul_sl_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_SL_UL) {\n    result = ALU::mul_sl_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UH_UH) {\n    result = ALU::mul_uh_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UH_UL) {\n    result = ALU::mul_uh_ul(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UL_UH) {\n    result = ALU::mul_ul_uh(ra, rb);\n  } else if (op_code == abi::instruction::MUL_UL_UL) {\n    result = ALU::mul_ul_ul(ra, rb);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_mul_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_rsub_zrrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rsub_rrrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::RSUB) {\n    std::tie(result, carry, overflow) = ALU::sub(rb, ra);\n  } else if (op_code == abi::instruction::RSUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        rb, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, rb);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, rb, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, rb, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_s_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    execute_add_s_rri(instruction);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    execute_asr_s_rri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_s_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_s_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_s_rric(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code)) {\n    execute_add_s_rrici(instruction);\n  } else if (abi::instruction::Instruction::and_rrici_op_codes().count(\n                 op_code)) {\n    execute_and_s_rrici(instruction);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    execute_asr_s_rrici(instruction);\n  } else if (abi::instruction::Instruction::sub_rrici_op_codes().count(\n                 op_code)) {\n    execute_sub_s_rrici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_s_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_s_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_s_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_imm_shift_nz_cc(instruction, ra, result);\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_s_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_s_rrif(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::S_RRIF);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::signed_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_s_rrr(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrrc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rri_op_codes().count(op_code)) {\n    execute_add_u_rri(instruction);\n  } else if (abi::instruction::Instruction::asr_rri_op_codes().count(op_code)) {\n    execute_asr_u_rri(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_u_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_asr_u_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_u_rric(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::add_rrici_op_codes().count(op_code)) {\n    execute_add_u_rrici(instruction);\n  } else if (abi::instruction::Instruction::and_rrici_op_codes().count(\n                 op_code)) {\n    execute_and_u_rrici(instruction);\n  } else if (abi::instruction::Instruction::asr_rrici_op_codes().count(\n                 op_code)) {\n    execute_asr_u_rrici(instruction);\n  } else if (abi::instruction::Instruction::sub_rrici_op_codes().count(\n                 op_code)) {\n    execute_sub_u_rrici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_add_u_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::add_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_add_nz_cc(instruction, ra, result, carry, overflow);\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_and_u_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::and_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_asr_u_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::asr_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ASR) {\n    result = ALU::asr(ra, imm);\n  } else if (op_code == abi::instruction::LSL) {\n    result = ALU::lsl(ra, imm);\n  } else if (op_code == abi::instruction::LSL1) {\n    result = ALU::lsl1(ra, imm);\n  } else if (op_code == abi::instruction::LSL1X) {\n    result = ALU::lsl1x(ra, imm);\n  } else if (op_code == abi::instruction::LSLX) {\n    result = ALU::lslx(ra, imm);\n  } else if (op_code == abi::instruction::LSR) {\n    result = ALU::lsr(ra, imm);\n  } else if (op_code == abi::instruction::LSR1) {\n    result = ALU::lsr1(ra, imm);\n  } else if (op_code == abi::instruction::LSR1X) {\n    result = ALU::lsr1x(ra, imm);\n  } else if (op_code == abi::instruction::LSRX) {\n    result = ALU::lsrx(ra, imm);\n  } else if (op_code == abi::instruction::ROL) {\n    result = ALU::rol(ra, imm);\n  } else if (op_code == abi::instruction::ROR) {\n    result = ALU::ror(ra, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_imm_shift_nz_cc(instruction, ra, result);\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_sub_u_rrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sub_rrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_u_rrif(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrif_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::U_RRIF);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::ADD) {\n    std::tie(result, carry, overflow) = ALU::add(ra, imm);\n  } else if (op_code == abi::instruction::ADDC) {\n    std::tie(result, carry, overflow) = ALU::addc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::AND) {\n    result = ALU::and_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ANDN) {\n    result = ALU::andn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NAND) {\n    result = ALU::nand(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NOR) {\n    result = ALU::nor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::NXOR) {\n    result = ALU::nxor(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::OR) {\n    result = ALU::or_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::ORN) {\n    result = ALU::orn(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(ra, imm);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        ra, imm, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else if (op_code == abi::instruction::XOR) {\n    result = ALU::xor_(ra, imm);\n    carry = false;\n    overflow = false;\n  } else if (op_code == abi::instruction::HASH) {\n    result = ALU::hash(ra, imm);\n    carry = false;\n    overflow = false;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n\n  auto [even, odd] = ALU::unsigned_extension(result);\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_u_rrr(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrrc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_rr(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rr_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else if (op_code == abi::instruction::TIME_CFG) {\n    throw std::bad_function_call();\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_rrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else if (op_code == abi::instruction::TIME_CFG) {\n    throw std::bad_function_call();\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_rrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRCI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::cao_rrci_op_codes().count(op_code)) {\n    execute_cao_rrci(instruction);\n  } else if (abi::instruction::Instruction::extsb_rrci_op_codes().count(\n                 op_code)) {\n    execute_extsb_rrci(instruction);\n  } else if (abi::instruction::Instruction::time_cfg_rrci_op_codes().count(\n                 op_code)) {\n    execute_time_cfg_rrci(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_cao_rrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::cao_rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_count_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_extsb_rrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::extsb_rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_time_cfg_rrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_zr(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rr_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else if (op_code == abi::instruction::TIME_CFG) {\n    throw std::bad_function_call();\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_zrc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else if (op_code == abi::instruction::TIME_CFG) {\n    throw std::bad_function_call();\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_set_cc(instruction, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_zrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRCI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::cao_rrci_op_codes().count(op_code)) {\n    execute_cao_zrci(instruction);\n  } else if (abi::instruction::Instruction::extsb_rrci_op_codes().count(\n                 op_code)) {\n    execute_extsb_zrci(instruction);\n  } else if (abi::instruction::Instruction::time_cfg_rrci_op_codes().count(\n                 op_code)) {\n    execute_time_cfg_zrci(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_cao_zrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::cao_rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::CAO) {\n    result = ALU::cao(ra);\n  } else if (op_code == abi::instruction::CLO) {\n    result = ALU::clo(ra);\n  } else if (op_code == abi::instruction::CLS) {\n    result = ALU::cls(ra);\n  } else if (op_code == abi::instruction::CLZ) {\n    result = ALU::clz(ra);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_count_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_extsb_zrci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::extsb_rrci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::EXTSB) {\n    result = ALU::extsb(ra);\n  } else if (op_code == abi::instruction::EXTSH) {\n    result = ALU::extsh(ra);\n  } else if (op_code == abi::instruction::EXTUB) {\n    result = ALU::extub(ra);\n  } else if (op_code == abi::instruction::EXTUH) {\n    result = ALU::extuh(ra);\n  } else if (op_code == abi::instruction::SATS) {\n    result = ALU::sats(ra);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_log_nz_cc(instruction, ra, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n}\n\nvoid Logic::execute_time_cfg_zrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rr(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rr(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_drdici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::drdici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DRDICI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::div_step_drdici_op_codes().count(\n          op_code)) {\n    execute_div_step_drdici(instruction);\n  } else if (abi::instruction::Instruction::mul_step_drdici_op_codes().count(\n                 op_code)) {\n    execute_mul_step_drdici(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_div_step_drdici(\n    abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::div_step_drdici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DRDICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t dbe = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->even_reg(), abi::word::SIGNED);\n  int64_t dbo = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->odd_reg(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  auto dbo_data_word = new abi::word::DataWord();\n  dbo_data_word->set_value(dbo);\n\n  auto ra_shift_data_word = new abi::word::DataWord();\n  ra_shift_data_word->set_value(ALU::lsl(ra, imm));\n\n  auto [result, carry, overflow] = ALU::sub(dbo, ALU::lsl(ra, imm));\n\n  int64_t dce;\n  int64_t dco;\n  if (dbo_data_word->value(abi::word::UNSIGNED) >=\n      ra_shift_data_word->value(abi::word::UNSIGNED)) {\n    dce = ALU::lsl1(dbe, 1);\n    dco = result;\n  } else {\n    dce = ALU::lsl(dbe, 1);\n    dco = instruction->thread()->reg_file()->read_gp_reg(\n        instruction->dc()->odd_reg(), abi::word::SIGNED);\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_div_cc(instruction, ra);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->even_reg(),\n                                                  dce);\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->odd_reg(),\n                                                  dco);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, false);\n\n  delete dbo_data_word;\n  delete ra_shift_data_word;\n}\n\nvoid Logic::execute_mul_step_drdici(\n    abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::mul_step_drdici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DRDICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t dbe = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->even_reg(), abi::word::SIGNED);\n  int64_t dbo = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->odd_reg(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result1 = ALU::lsr(dbe, 1);\n  auto [result2, carry, overflow] = ALU::sub(ALU::and_(dbe, 1), 1);\n\n  int64_t dco;\n  if (result2 == 0) {\n    std::tie(dco, carry, overflow) = ALU::add(dbo, ALU::lsl(ra, imm));\n  } else {\n    dco = instruction->thread()->reg_file()->read_gp_reg(\n        instruction->dc()->odd_reg(), abi::word::SIGNED);\n  }\n  int64_t dce = ALU::lsr(dbe, 1);\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_boot_cc(instruction, ra, result1);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->even_reg(),\n                                                  dce);\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->odd_reg(),\n                                                  dco);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result1, false);\n}\n\nvoid Logic::execute_rrri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LSL_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsl_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSL_SUB) {\n    std::tie(result, carry, overflow) = ALU::lsl_sub(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSR_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsr_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::ROL_ADD) {\n    std::tie(result, carry, overflow) = ALU::rol_add(ra, rb, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rrrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RRRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LSL_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsl_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSL_SUB) {\n    std::tie(result, carry, overflow) = ALU::lsl_sub(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSR_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsr_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::ROL_ADD) {\n    std::tie(result, carry, overflow) = ALU::rol_add(ra, rb, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_div_nz_cc(instruction, ra);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LSL_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsl_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSL_SUB) {\n    std::tie(result, carry, overflow) = ALU::lsl_sub(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSR_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsr_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::ROL_ADD) {\n    std::tie(result, carry, overflow) = ALU::rol_add(ra, rb, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zrrici(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rrrici_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZRRICI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LSL_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsl_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSL_SUB) {\n    std::tie(result, carry, overflow) = ALU::lsl_sub(ra, rb, imm);\n  } else if (op_code == abi::instruction::LSR_ADD) {\n    std::tie(result, carry, overflow) = ALU::lsr_add(ra, rb, imm);\n  } else if (op_code == abi::instruction::ROL_ADD) {\n    std::tie(result, carry, overflow) = ALU::rol_add(ra, rb, imm);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_div_nz_cc(instruction, ra);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_s_rrri(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rrrici(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrri(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rrrici(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_rir(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rir_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RIR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rirc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rirc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RIRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_set_cc(instruction, ra, imm, result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 1);\n  } else {\n    instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), 0);\n  }\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_rirci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rirci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::RIRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zir(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rir_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZIR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zirc(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rirc_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZIRC);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_set_cc(instruction, ra, imm, result);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_zirci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::rirci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ZIRCI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  int64_t result;\n  bool carry;\n  bool overflow;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SUB) {\n    std::tie(result, carry, overflow) = ALU::sub(imm, ra);\n  } else if (op_code == abi::instruction::SUBC) {\n    std::tie(result, carry, overflow) = ALU::subc(\n        imm, ra, instruction->thread()->reg_file()->flag(abi::isa::CARRY));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  set_sub_nz_cc(instruction, ra, imm, result, carry, overflow);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n\n  set_flags(instruction, result, carry);\n}\n\nvoid Logic::execute_s_rirc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rirci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rirc(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rirci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_r(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_rci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_z(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::r_op_codes().count(\n             instruction->op_code()) or\n         instruction->op_code() == abi::instruction::NOP);\n  assert(instruction->suffix() == abi::instruction::Z);\n\n  instruction->thread()->reg_file()->increment_pc_reg();\n}\n\nvoid Logic::execute_zci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_r(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_s_rci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_r(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_rci(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_ci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::ci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::CI);\n\n  instruction->thread()->reg_file()->clear_conditions();\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n    scheduler_->sleep(instruction->thread()->id());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n    scheduler_->sleep(instruction->thread()->id());\n  }\n}\n\nvoid Logic::execute_i(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_ddci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::ddci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DDCI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::movd_ddci_op_codes().count(op_code)) {\n    execute_movd_ddci(instruction);\n  } else if (abi::instruction::Instruction::swapd_ddci_op_codes().count(\n                 op_code)) {\n    execute_swapd_ddci(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_movd_ddci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::movd_ddci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DDCI);\n\n  int64_t dbe = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->even_reg(), abi::word::SIGNED);\n  int64_t dbo = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->odd_reg(), abi::word::SIGNED);\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->even_reg(),\n                                                  dbe);\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->odd_reg(),\n                                                  dbo);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n}\n\nvoid Logic::execute_swapd_ddci(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::swapd_ddci_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DDCI);\n\n  int64_t dbe = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->even_reg(), abi::word::SIGNED);\n  int64_t dbo = instruction->thread()->reg_file()->read_gp_reg(\n      instruction->db()->odd_reg(), abi::word::SIGNED);\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->even_reg(),\n                                                  dbo);\n  instruction->thread()->reg_file()->write_gp_reg(instruction->dc()->odd_reg(),\n                                                  dbe);\n\n  if (instruction->thread()->reg_file()->condition(instruction->condition())) {\n    instruction->thread()->reg_file()->write_pc_reg(instruction->pc()->value());\n  } else {\n    instruction->thread()->reg_file()->increment_pc_reg();\n  }\n}\n\nvoid Logic::execute_erri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::erri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ERRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t off = instruction->off()->value();\n\n  auto [address, carry, overflow] = ALU::add(ra, off);\n\n  int64_t result;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LBS) {\n    result = operand_collector_->lbs(address);\n  } else if (op_code == abi::instruction::LBU) {\n    result = operand_collector_->lbu(address);\n  } else if (op_code == abi::instruction::LHS) {\n    result = operand_collector_->lhs(address);\n  } else if (op_code == abi::instruction::LHU) {\n    result = operand_collector_->lhu(address);\n  } else if (op_code == abi::instruction::LW) {\n    result = operand_collector_->lw(address);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_gp_reg(instruction->rc(), result);\n  instruction->thread()->reg_file()->increment_pc_reg();\n}\n\nvoid Logic::execute_s_erri(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_u_erri(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_edri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::edri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::EDRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t off = instruction->off()->value();\n\n  auto [address, carry, overflow] = ALU::add(ra, off);\n\n  int64_t even;\n  int64_t odd;\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::LD) {\n    std::tie(even, odd) = operand_collector_->ld(address);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->write_pair_reg(instruction->dc(), even,\n                                                    odd);\n  instruction->thread()->reg_file()->increment_pc_reg();\n}\n\nvoid Logic::execute_erii(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::erii_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ERII);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t off = instruction->off()->value();\n  int64_t imm = instruction->imm()->value();\n\n  auto [address, carry, overflow] = ALU::add(ra, off);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SB) {\n    operand_collector_->sb(address, imm);\n  } else if (op_code == abi::instruction::SB_ID) {\n    operand_collector_->sb(address, ALU::or_(instruction->thread()->id(), imm));\n  } else if (op_code == abi::instruction::SH) {\n    operand_collector_->sh(address, imm);\n  } else if (op_code == abi::instruction::SH_ID) {\n    operand_collector_->sh(address, ALU::or_(instruction->thread()->id(), imm));\n  } else if (op_code == abi::instruction::SW) {\n    operand_collector_->sw(address, imm);\n  } else if (op_code == abi::instruction::SW_ID) {\n    operand_collector_->sw(address, ALU::or_(instruction->thread()->id(), imm));\n  } else if (op_code == abi::instruction::SD) {\n    auto [even, odd] = ALU::unsigned_extension(imm);\n    operand_collector_->sd(address, even, odd);\n  } else if (op_code == abi::instruction::SD_ID) {\n    auto [even, odd] =\n        ALU::unsigned_extension(ALU::or_(instruction->thread()->id(), imm));\n    operand_collector_->sd(address, even, odd);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n}\n\nvoid Logic::execute_erir(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::erir_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ERIR);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t off = instruction->off()->value();\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  auto rb_data_word = new abi::word::DataWord();\n  rb_data_word->set_value(rb);\n\n  auto [address, carry, overflow] = ALU::add(ra, off);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SB) {\n    operand_collector_->sb(address,\n                           rb_data_word->bit_slice(abi::word::UNSIGNED, 0, 8));\n  } else if (op_code == abi::instruction::SH) {\n    operand_collector_->sh(address,\n                           rb_data_word->bit_slice(abi::word::UNSIGNED, 0, 16));\n  } else if (op_code == abi::instruction::SW) {\n    operand_collector_->sw(address,\n                           rb_data_word->bit_slice(abi::word::UNSIGNED, 0, 32));\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n\n  delete rb_data_word;\n}\n\nvoid Logic::execute_erid(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::erid_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::ERID);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t off = instruction->off()->value();\n  auto [even, odd] = instruction->thread()->reg_file()->read_pair_reg(\n      instruction->db(), abi::word::SIGNED);\n\n  auto [address, carry, overflow] = ALU::add(ra, off);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (op_code == abi::instruction::SD) {\n    operand_collector_->sd(address, even, odd);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  instruction->thread()->reg_file()->clear_conditions();\n  instruction->thread()->reg_file()->increment_pc_reg();\n}\n\nvoid Logic::execute_dma_rri(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::dma_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DMA_RRI);\n\n  abi::instruction::OpCode op_code = instruction->op_code();\n  if (abi::instruction::Instruction::ldma_dma_rri_op_codes().count(op_code)) {\n    execute_ldma(instruction);\n  } else if (abi::instruction::Instruction::ldmai_dma_rri_op_codes().count(\n                 op_code)) {\n    execute_ldmai(instruction);\n  } else if (abi::instruction::Instruction::sdma_dma_rri_op_codes().count(\n                 op_code)) {\n    execute_sdma(instruction);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid Logic::execute_ldma(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::ldma_dma_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DMA_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  Address wram_end_address =\n      util::ConfigLoader::wram_offset() + util::ConfigLoader::wram_size();\n  auto wram_end_address_width =\n      static_cast<Address>(floor(log2(wram_end_address)) + 1);\n  auto wram_mask = static_cast<Address>(pow(2, wram_end_address_width) - 1);\n  Address wram_address = ALU::and_(ra, wram_mask);\n\n  Address mram_end_address =\n      util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size();\n  auto mram_end_address_width =\n      static_cast<Address>(floor(log2(mram_end_address)) + 1);\n  auto mram_mask = static_cast<Address>(pow(2, mram_end_address_width) - 1);\n  Address mram_address = ALU::and_(rb, mram_mask);\n\n  Address min_access_granularity = util::ConfigLoader::min_access_granularity();\n  Address size = (1 + ALU::and_(imm + ALU::and_(ALU::lsr(ra, 24), 255), 255)) *\n                 min_access_granularity;\n\n  dma_->transfer_from_mram_to_wram(wram_address, mram_address, size,\n                                   instruction);\n\n  stat_factory_->overwrite(\"mram_address\", mram_address); \n  stat_factory_->overwrite(\"mram_access_thread\",\n                           instruction->thread()->id());\n  stat_factory_->overwrite(\"mram_access_size\", size); \n\n  instruction->thread()->reg_file()->clear_conditions();\n}\n\nvoid Logic::execute_ldmai(abi::instruction::Instruction *instruction) {\n  throw std::bad_function_call();\n}\n\nvoid Logic::execute_sdma(abi::instruction::Instruction *instruction) {\n  assert(abi::instruction::Instruction::sdma_dma_rri_op_codes().count(\n      instruction->op_code()));\n  assert(instruction->suffix() == abi::instruction::DMA_RRI);\n\n  int64_t ra = instruction->thread()->reg_file()->read_src_reg(\n      instruction->ra(), abi::word::SIGNED);\n  int64_t rb = instruction->thread()->reg_file()->read_src_reg(\n      instruction->rb(), abi::word::SIGNED);\n  int64_t imm = instruction->imm()->value();\n\n  Address wram_end_address =\n      util::ConfigLoader::wram_offset() + util::ConfigLoader::wram_size();\n  auto wram_end_address_width =\n      static_cast<Address>(floor(log2(wram_end_address)) + 1);\n  auto wram_mask = static_cast<Address>(pow(2, wram_end_address_width) - 1);\n  Address wram_address = ALU::and_(ra, wram_mask);\n\n  Address mram_end_address =\n      util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size();\n  auto mram_end_address_width =\n      static_cast<Address>(floor(log2(mram_end_address)) + 1);\n  auto mram_mask = static_cast<Address>(pow(2, mram_end_address_width) - 1);\n  Address mram_address = ALU::and_(rb, mram_mask);\n\n  Address min_access_granularity = util::ConfigLoader::min_access_granularity();\n  Address size = (1 + ALU::and_(imm + ALU::and_(ALU::lsr(ra, 24), 255), 255)) *\n                 min_access_granularity;\n\n  dma_->transfer_from_wram_to_mram(wram_address, mram_address, size,\n                                   instruction);\n\n  stat_factory_->overwrite(\"mram_address\", mram_address);\n  stat_factory_->overwrite(\"mram_access_thread\",\n                           instruction->thread()->id());\n  stat_factory_->overwrite(\"mram_access_size\", size); \n\n  instruction->thread()->reg_file()->clear_conditions();\n}\n\nvoid Logic::set_acquire_cc(abi::instruction::Instruction *instruction,\n                           int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n}\n\nvoid Logic::set_add_nz_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1, int64_t result, bool carry,\n                          bool overflow) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (carry) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::C);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (overflow) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::OV);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NOV);\n  }\n\n  if (result >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::PL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MI);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n\n  auto result_data_word = new abi::word::DataWord();\n  result_data_word->set_value(result);\n\n  if (result_data_word->bit(6)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC5);\n  }\n  if (result_data_word->bit(7)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC6);\n  }\n  if (result_data_word->bit(8)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC7);\n  }\n  if (result_data_word->bit(9)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC8);\n  }\n  if (result_data_word->bit(10)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC9);\n  }\n  if (result_data_word->bit(11)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC10);\n  }\n  if (result_data_word->bit(12)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC11);\n  }\n  if (result_data_word->bit(13)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC12);\n  }\n  if (result_data_word->bit(14)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC13);\n  }\n  if (result_data_word->bit(15)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC14);\n  }\n\n  delete result_data_word;\n}\n\nvoid Logic::set_boot_cc(abi::instruction::Instruction *instruction,\n                        int64_t operand1, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n}\n\nvoid Logic::set_count_nz_cc(abi::instruction::Instruction *instruction,\n                            int64_t operand1, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n\n  if (result == abi::word::DataWord().width()) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MAX);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NMAX);\n  }\n}\n\nvoid Logic::set_div_cc(abi::instruction::Instruction *instruction,\n                       int64_t operand1) {\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n}\n\nvoid Logic::set_div_nz_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1) {\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n}\n\nvoid Logic::set_ext_sub_set_cc(abi::instruction::Instruction *instruction,\n                               int64_t operand1, int64_t operand2,\n                               int64_t result, bool carry, bool overflow) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (carry) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::C);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (overflow) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::OV);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NOV);\n  }\n\n  if (result >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::PL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MI);\n  }\n\n  if (operand1 == operand2) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::EQ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NEQ);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  if (data_word1->value(abi::word::UNSIGNED) <\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LTU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) <=\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LEU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) >\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GTU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) >=\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GEU);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) <\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LTS);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) <=\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LES);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) >\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GTS);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) >=\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GES);\n  }\n\n  if (carry or instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XLEU);\n  }\n\n  if (carry and not instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XGTU);\n  }\n\n  if (instruction->thread()->reg_file()->flag(abi::isa::ZERO) and\n      (result < 0 or overflow)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XLES);\n  }\n\n  if (not instruction->thread()->reg_file()->flag(abi::isa::ZERO) and\n      (result >= 0 or overflow)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XGTS);\n  }\n\n  delete data_word1;\n  delete data_word2;\n}\n\nvoid Logic::set_imm_shift_nz_cc(abi::instruction::Instruction *instruction,\n                                int64_t operand1, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (result % 2 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::E);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::O);\n  }\n\n  if (result >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::PL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MI);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 % 2 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SE);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SO);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n}\n\nvoid Logic::set_log_nz_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (result >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::PL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MI);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n}\n\nvoid Logic::set_log_set_cc(abi::instruction::Instruction *instruction,\n                           int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n}\n\nvoid Logic::set_mul_nz_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (operand1 == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SNZ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n\n  if (result < 256) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMALL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LARGE);\n  }\n}\n\nvoid Logic::set_sub_nz_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1, int64_t operand2, int64_t result,\n                          bool carry, bool overflow) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (carry) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::C);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NC);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (overflow) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::OV);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NOV);\n  }\n\n  if (result >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::PL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::MI);\n  }\n\n  if (operand1 == operand2) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::EQ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NEQ);\n  }\n\n  if (operand1 >= 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SPL);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::SMI);\n  }\n\n  auto data_word1 = new abi::word::DataWord();\n  data_word1->set_value(operand1);\n\n  auto data_word2 = new abi::word::DataWord();\n  data_word2->set_value(operand2);\n\n  if (data_word1->value(abi::word::UNSIGNED) <\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LTU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) <=\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LEU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) >\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GTU);\n  }\n\n  if (data_word1->value(abi::word::UNSIGNED) >=\n      data_word2->value(abi::word::UNSIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GEU);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) <\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LTS);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) <=\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::LES);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) >\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GTS);\n  }\n\n  if (data_word1->value(abi::word::SIGNED) >=\n      data_word2->value(abi::word::SIGNED)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::GES);\n  }\n\n  if (carry or instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XLEU);\n  }\n\n  if (carry and not instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XGTU);\n  }\n\n  if (instruction->thread()->reg_file()->flag(abi::isa::ZERO) and\n      (result < 0 or overflow)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XLES);\n  }\n\n  if (not instruction->thread()->reg_file()->flag(abi::isa::ZERO) and\n      (result >= 0 or overflow)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XGTS);\n  }\n\n  delete data_word1;\n  delete data_word2;\n}\n\nvoid Logic::set_sub_set_cc(abi::instruction::Instruction *instruction,\n                           int64_t operand1, int64_t operand2, int64_t result) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::Z);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NZ);\n  }\n\n  if (result == 0 and instruction->thread()->reg_file()->flag(abi::isa::ZERO)) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XZ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::XNZ);\n  }\n\n  if (operand1 == operand2) {\n    instruction->thread()->reg_file()->set_condition(abi::isa::EQ);\n  } else {\n    instruction->thread()->reg_file()->set_condition(abi::isa::NEQ);\n  }\n}\n\nvoid Logic::set_flags(abi::instruction::Instruction *instruction,\n                      int64_t result, bool carry) {\n  if (result == 0) {\n    instruction->thread()->reg_file()->set_flag(abi::isa::ZERO);\n  } else {\n    instruction->thread()->reg_file()->clear_flag(abi::isa::ZERO);\n  }\n\n  if (carry) {\n    instruction->thread()->reg_file()->set_flag(abi::isa::CARRY);\n  } else {\n    instruction->thread()->reg_file()->clear_flag(abi::isa::CARRY);\n  }\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/logic.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_LOGIC_H_\n#define UPMEM_SIM_SIMULATOR_DPU_LOGIC_H_\n\n#include \"simulator/dpu/cycle_rule.h\"\n#include \"simulator/dpu/dma.h\"\n#include \"simulator/dpu/operand_collector.h\"\n#include \"simulator/dpu/pipeline.h\"\n#include \"simulator/dpu/revolver_scheduler.h\"\n#include \"simulator/dram/memory_controller.h\"\n#include \"simulator/sram/atomic.h\"\n#include \"simulator/sram/iram.h\"\n#include \"simulator/sram/wram.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass Logic {\n public:\n  explicit Logic(DPUID dpu_id, util::ArgumentParser *argument_parser)\n      : verbose_(argument_parser->get_int_parameter(\"verbose\")),\n        dpu_id_(dpu_id),\n        scheduler_(nullptr),\n        atomic_(nullptr),\n        iram_(nullptr),\n        dma_(nullptr),\n        pipeline_(new Pipeline(argument_parser)),\n        cycle_rule_(new CycleRule(argument_parser)),\n        operand_collector_(nullptr),\n        wait_instruction_q_(new basic::Queue<abi::instruction::Instruction>(\n            util::ConfigLoader::max_num_tasklets())),\n        stat_factory_(new util::StatFactory(\"Logic\")),\n        num_pipeline_stages_(\n            argument_parser->get_int_parameter(\"num_pipeline_stages\")) {}\n  ~Logic();\n\n  DPUID dpu_id() { return dpu_id_; }\n\n  util::StatFactory *stat_factory();\n\n  void connect_scheduler(RevolverScheduler *scheduler);\n  void connect_atomic(sram::Atomic *atomic);\n  void connect_iram(sram::IRAM *iram);\n  void connect_operand_collector(OperandCollector *operand_collector);\n  void connect_dma(DMA *dma);\n\n  bool empty() {\n    return pipeline_->empty() and cycle_rule_->empty() and\n           wait_instruction_q_->empty();\n  }\n  void cycle();\n\n protected:\n  void service_scheduler();\n  void service_pipeline();\n  void service_cycle_rule();\n  void service_logic();\n  void service_dma();\n\n  void execute_instruction(abi::instruction::Instruction *instruction);\n\n  void execute_rici(abi::instruction::Instruction *instruction);\n  void execute_acquire_rici(abi::instruction::Instruction *instruction);\n  void execute_release_rici(abi::instruction::Instruction *instruction);\n  void execute_boot_rici(abi::instruction::Instruction *instruction);\n\n  void execute_rri(abi::instruction::Instruction *instruction);\n  void execute_add_rri(abi::instruction::Instruction *instruction);\n  void execute_asr_rri(abi::instruction::Instruction *instruction);\n  void execute_call_rri(abi::instruction::Instruction *instruction);\n\n  void execute_rric(abi::instruction::Instruction *instruction);\n  void execute_add_rric(abi::instruction::Instruction *instruction);\n  void execute_asr_rric(abi::instruction::Instruction *instruction);\n  void execute_sub_rric(abi::instruction::Instruction *instruction);\n\n  void execute_rrici(abi::instruction::Instruction *instruction);\n  void execute_add_rrici(abi::instruction::Instruction *instruction);\n  void execute_and_rrici(abi::instruction::Instruction *instruction);\n  void execute_asr_rrici(abi::instruction::Instruction *instruction);\n  void execute_sub_rrici(abi::instruction::Instruction *instruction);\n\n  void execute_rrif(abi::instruction::Instruction *instruction);\n\n  void execute_rrr(abi::instruction::Instruction *instruction);\n\n  void execute_rrrc(abi::instruction::Instruction *instruction);\n  void execute_add_rrrc(abi::instruction::Instruction *instruction);\n  void execute_rsub_rrrc(abi::instruction::Instruction *instruction);\n  void execute_sub_rrrc(abi::instruction::Instruction *instruction);\n\n  void execute_rrrci(abi::instruction::Instruction *instruction);\n  void execute_add_rrrci(abi::instruction::Instruction *instruction);\n  void execute_and_rrrci(abi::instruction::Instruction *instruction);\n  void execute_asr_rrrci(abi::instruction::Instruction *instruction);\n  void execute_mul_rrrci(abi::instruction::Instruction *instruction);\n  void execute_rsub_rrrci(abi::instruction::Instruction *instruction);\n\n  void execute_zri(abi::instruction::Instruction *instruction);\n  void execute_add_zri(abi::instruction::Instruction *instruction);\n  void execute_asr_zri(abi::instruction::Instruction *instruction);\n  void execute_call_zri(abi::instruction::Instruction *instruction);\n\n  void execute_zric(abi::instruction::Instruction *instruction);\n  void execute_add_zric(abi::instruction::Instruction *instruction);\n  void execute_asr_zric(abi::instruction::Instruction *instruction);\n  void execute_sub_zric(abi::instruction::Instruction *instruction);\n\n  void execute_zrici(abi::instruction::Instruction *instruction);\n  void execute_add_zrici(abi::instruction::Instruction *instruction);\n  void execute_and_zrici(abi::instruction::Instruction *instruction);\n  void execute_asr_zrici(abi::instruction::Instruction *instruction);\n  void execute_sub_zrici(abi::instruction::Instruction *instruction);\n\n  void execute_zrif(abi::instruction::Instruction *instruction);\n\n  void execute_zrr(abi::instruction::Instruction *instruction);\n\n  void execute_zrrc(abi::instruction::Instruction *instruction);\n  void execute_add_zrrc(abi::instruction::Instruction *instruction);\n  void execute_rsub_zrrc(abi::instruction::Instruction *instruction);\n  void execute_sub_zrrc(abi::instruction::Instruction *instruction);\n\n  void execute_zrrci(abi::instruction::Instruction *instruction);\n  void execute_add_zrrci(abi::instruction::Instruction *instruction);\n  void execute_and_zrrci(abi::instruction::Instruction *instruction);\n  void execute_asr_zrrci(abi::instruction::Instruction *instruction);\n  void execute_mul_zrrci(abi::instruction::Instruction *instruction);\n  void execute_rsub_zrrci(abi::instruction::Instruction *instruction);\n\n  void execute_s_rri(abi::instruction::Instruction *instruction);\n  void execute_add_s_rri(abi::instruction::Instruction *instruction);\n  void execute_asr_s_rri(abi::instruction::Instruction *instruction);\n\n  void execute_s_rric(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrici(abi::instruction::Instruction *instruction);\n  void execute_add_s_rrici(abi::instruction::Instruction *instruction);\n  void execute_and_s_rrici(abi::instruction::Instruction *instruction);\n  void execute_asr_s_rrici(abi::instruction::Instruction *instruction);\n  void execute_sub_s_rrici(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrif(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrr(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrrc(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrrci(abi::instruction::Instruction *instruction);\n\n  void execute_u_rri(abi::instruction::Instruction *instruction);\n  void execute_add_u_rri(abi::instruction::Instruction *instruction);\n  void execute_asr_u_rri(abi::instruction::Instruction *instruction);\n\n  void execute_u_rric(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrici(abi::instruction::Instruction *instruction);\n  void execute_add_u_rrici(abi::instruction::Instruction *instruction);\n  void execute_and_u_rrici(abi::instruction::Instruction *instruction);\n  void execute_asr_u_rrici(abi::instruction::Instruction *instruction);\n  void execute_sub_u_rrici(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrif(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrr(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrrc(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrrci(abi::instruction::Instruction *instruction);\n\n  void execute_rr(abi::instruction::Instruction *instruction);\n\n  void execute_rrc(abi::instruction::Instruction *instruction);\n\n  void execute_rrci(abi::instruction::Instruction *instruction);\n  void execute_cao_rrci(abi::instruction::Instruction *instruction);\n  void execute_extsb_rrci(abi::instruction::Instruction *instruction);\n  void execute_time_cfg_rrci(abi::instruction::Instruction *instruction);\n\n  void execute_zr(abi::instruction::Instruction *instruction);\n\n  void execute_zrc(abi::instruction::Instruction *instruction);\n\n  void execute_zrci(abi::instruction::Instruction *instruction);\n  void execute_cao_zrci(abi::instruction::Instruction *instruction);\n  void execute_extsb_zrci(abi::instruction::Instruction *instruction);\n  void execute_time_cfg_zrci(abi::instruction::Instruction *instruction);\n\n  void execute_s_rr(abi::instruction::Instruction *instruction);\n  void execute_s_rrc(abi::instruction::Instruction *instruction);\n  void execute_s_rrci(abi::instruction::Instruction *instruction);\n\n  void execute_u_rr(abi::instruction::Instruction *instruction);\n  void execute_u_rrc(abi::instruction::Instruction *instruction);\n  void execute_u_rrci(abi::instruction::Instruction *instruction);\n\n  void execute_drdici(abi::instruction::Instruction *instruction);\n  void execute_div_step_drdici(abi::instruction::Instruction *instruction);\n  void execute_mul_step_drdici(abi::instruction::Instruction *instruction);\n\n  void execute_rrri(abi::instruction::Instruction *instruction);\n  void execute_rrrici(abi::instruction::Instruction *instruction);\n\n  void execute_zrri(abi::instruction::Instruction *instruction);\n  void execute_zrrici(abi::instruction::Instruction *instruction);\n\n  void execute_s_rrri(abi::instruction::Instruction *instruction);\n  void execute_s_rrrici(abi::instruction::Instruction *instruction);\n\n  void execute_u_rrri(abi::instruction::Instruction *instruction);\n  void execute_u_rrrici(abi::instruction::Instruction *instruction);\n\n  void execute_rir(abi::instruction::Instruction *instruction);\n  void execute_rirc(abi::instruction::Instruction *instruction);\n  void execute_rirci(abi::instruction::Instruction *instruction);\n\n  void execute_zir(abi::instruction::Instruction *instruction);\n  void execute_zirc(abi::instruction::Instruction *instruction);\n  void execute_zirci(abi::instruction::Instruction *instruction);\n\n  void execute_s_rirc(abi::instruction::Instruction *instruction);\n  void execute_s_rirci(abi::instruction::Instruction *instruction);\n\n  void execute_u_rirc(abi::instruction::Instruction *instruction);\n  void execute_u_rirci(abi::instruction::Instruction *instruction);\n\n  void execute_r(abi::instruction::Instruction *instruction);\n  void execute_rci(abi::instruction::Instruction *instruction);\n\n  void execute_z(abi::instruction::Instruction *instruction);\n  void execute_zci(abi::instruction::Instruction *instruction);\n\n  void execute_s_r(abi::instruction::Instruction *instruction);\n  void execute_s_rci(abi::instruction::Instruction *instruction);\n\n  void execute_u_r(abi::instruction::Instruction *instruction);\n  void execute_u_rci(abi::instruction::Instruction *instruction);\n\n  void execute_ci(abi::instruction::Instruction *instruction);\n  void execute_i(abi::instruction::Instruction *instruction);\n\n  void execute_ddci(abi::instruction::Instruction *instruction);\n  void execute_movd_ddci(abi::instruction::Instruction *instruction);\n  void execute_swapd_ddci(abi::instruction::Instruction *instruction);\n\n  void execute_erri(abi::instruction::Instruction *instruction);\n  void execute_s_erri(abi::instruction::Instruction *instruction);\n  void execute_u_erri(abi::instruction::Instruction *instruction);\n  void execute_edri(abi::instruction::Instruction *instruction);\n\n  void execute_erii(abi::instruction::Instruction *instruction);\n  void execute_erir(abi::instruction::Instruction *instruction);\n  void execute_erid(abi::instruction::Instruction *instruction);\n\n  void execute_dma_rri(abi::instruction::Instruction *instruction);\n  void execute_ldma(abi::instruction::Instruction *instruction);\n  void execute_ldmai(abi::instruction::Instruction *instruction);\n  void execute_sdma(abi::instruction::Instruction *instruction);\n\n  void set_acquire_cc(abi::instruction::Instruction *instruction,\n                      int64_t result);\n  void set_add_nz_cc(abi::instruction::Instruction *instruction,\n                     int64_t operand1, int64_t result, bool carry,\n                     bool overflow);\n  void set_boot_cc(abi::instruction::Instruction *instruction, int64_t operand1,\n                   int64_t result);\n  void set_count_nz_cc(abi::instruction::Instruction *instruction,\n                       int64_t operand1, int64_t result);\n  void set_div_cc(abi::instruction::Instruction *instruction, int64_t operand1);\n  void set_div_nz_cc(abi::instruction::Instruction *instruction,\n                     int64_t operand1);\n  void set_ext_sub_set_cc(abi::instruction::Instruction *instruction,\n                          int64_t operand1, int64_t operand2, int64_t result,\n                          bool carry, bool overflow);\n  void set_imm_shift_nz_cc(abi::instruction::Instruction *instruction,\n                           int64_t operand1, int64_t result);\n  void set_log_nz_cc(abi::instruction::Instruction *instruction,\n                     int64_t operand1, int64_t result);\n  void set_log_set_cc(abi::instruction::Instruction *instruction,\n                      int64_t result);\n  void set_mul_nz_cc(abi::instruction::Instruction *instruction,\n                     int64_t operand1, int64_t result);\n  void set_sub_nz_cc(abi::instruction::Instruction *instruction,\n                     int64_t operand1, int64_t operand2, int64_t result,\n                     bool carry, bool overflow);\n  void set_sub_set_cc(abi::instruction::Instruction *instruction,\n                      int64_t operand1, int64_t operand2, int64_t result);\n\n  void set_flags(abi::instruction::Instruction *instruction, int64_t result,\n                 bool carry);\n\n private:\n  DPUID dpu_id_;\n  int verbose_;\n\n  RevolverScheduler *scheduler_;\n  sram::Atomic *atomic_;\n  sram::IRAM *iram_;\n  DMA *dma_;\n\n  Pipeline *pipeline_;\n  int num_pipeline_stages_;\n  CycleRule *cycle_rule_;\n  OperandCollector *operand_collector_;\n\n  basic::Queue<abi::instruction::Instruction> *wait_instruction_q_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/operand_collector.cc",
    "content": "#include \"simulator/dpu/operand_collector.h\"\n\n#include <tuple>\n\nnamespace upmem_sim::simulator::dpu {\n\nvoid OperandCollector::connect_wram(sram::WRAM *wram) {\n  assert(wram != nullptr);\n  assert(wram_ == nullptr);\n\n  wram_ = wram;\n}\n\nint64_t OperandCollector::lbs(Address address) {\n  Address data_word_size = abi::word::DataWord().size();\n  Address base_address = (address / data_word_size) * data_word_size;\n  Address offset = address % data_word_size;\n\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(wram_->read(base_address));\n\n  int64_t result =\n      data_word->bit_slice(abi::word::SIGNED, static_cast<int>(8 * offset),\n                           static_cast<int>(8 * (offset + 1)));\n\n  delete data_word;\n\n  return result;\n}\n\nint64_t OperandCollector::lbu(Address address) {\n  Address data_word_size = abi::word::DataWord().size();\n  Address base_address = (address / data_word_size) * data_word_size;\n  Address offset = address % data_word_size;\n\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(wram_->read(base_address));\n\n  int64_t result =\n      data_word->bit_slice(abi::word::UNSIGNED, static_cast<int>(8 * offset),\n                           static_cast<int>(8 * (offset + 1)));\n\n  delete data_word;\n\n  return result;\n}\n\nint64_t OperandCollector::lhs(Address address) {\n  auto data_word = new abi::word::DataWord();\n\n  data_word->set_bit_slice(0, 8, lbs(address));\n  data_word->set_bit_slice(8, 16, lbs(address + 1));\n\n  int64_t result = data_word->bit_slice(abi::word::SIGNED, 0, 16);\n\n  delete data_word;\n\n  return result;\n}\n\nint64_t OperandCollector::lhu(Address address) {\n  auto data_word = new abi::word::DataWord();\n\n  data_word->set_bit_slice(0, 8, lbu(address));\n  data_word->set_bit_slice(8, 16, lbu(address + 1));\n\n  int64_t result = data_word->bit_slice(abi::word::UNSIGNED, 0, 16);\n\n  delete data_word;\n\n  return result;\n}\n\nint64_t OperandCollector::lw(Address address) {\n  auto data_word = new abi::word::DataWord();\n\n  data_word->set_bit_slice(0, 8, lbu(address));\n  data_word->set_bit_slice(8, 16, lbu(address + 1));\n  data_word->set_bit_slice(16, 24, lbu(address + 2));\n  data_word->set_bit_slice(24, 32, lbu(address + 3));\n\n  int64_t result = data_word->value(abi::word::UNSIGNED);\n\n  delete data_word;\n\n  return result;\n}\n\nstd::tuple<int64_t, int64_t> OperandCollector::ld(Address address) {\n  return {lw(address + abi::word::DataWord().size()), lw(address)};\n}\n\nvoid OperandCollector::sb(Address address, int64_t value) {\n  Address data_word_size = abi::word::DataWord().size();\n  Address base_address = (address / data_word_size) * data_word_size;\n  Address offset = address % data_word_size;\n\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(wram_->read(base_address));\n  data_word->set_bit_slice(static_cast<int>(8 * offset),\n                           static_cast<int>(8 * (offset + 1)), value);\n\n  wram_->write(base_address, data_word->value(abi::word::UNSIGNED));\n\n  delete data_word;\n}\n\nvoid OperandCollector::sh(Address address, int64_t value) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(value);\n\n  sb(address, data_word->bit_slice(abi::word::UNSIGNED, 0, 8));\n  sb(address + 1, data_word->bit_slice(abi::word::UNSIGNED, 8, 16));\n\n  delete data_word;\n}\n\nvoid OperandCollector::sw(Address address, int64_t value) {\n  auto data_word = new abi::word::DataWord();\n  data_word->set_value(value);\n\n  sb(address, data_word->bit_slice(abi::word::UNSIGNED, 0, 8));\n  sb(address + 1, data_word->bit_slice(abi::word::UNSIGNED, 8, 16));\n  sb(address + 2, data_word->bit_slice(abi::word::UNSIGNED, 16, 24));\n  sb(address + 3, data_word->bit_slice(abi::word::UNSIGNED, 24, 32));\n\n  delete data_word;\n}\n\nvoid OperandCollector::sd(Address address, int64_t even, int64_t odd) {\n  sw(address + abi::word::DataWord().size(), even);\n  sw(address, odd);\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/operand_collector.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_OPERAND_COLLECTOR_H_\n#define UPMEM_SIM_SIMULATOR_DPU_OPERAND_COLLECTOR_H_\n\n#include \"simulator/sram/wram.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass OperandCollector {\n public:\n  explicit OperandCollector() : wram_(nullptr) {}\n  ~OperandCollector() = default;\n\n  void connect_wram(sram::WRAM *wram);\n\n  int64_t lbs(Address address);\n  int64_t lbu(Address address);\n\n  int64_t lhs(Address address);\n  int64_t lhu(Address address);\n\n  int64_t lw(Address address);\n  std::tuple<int64_t, int64_t> ld(Address address);\n\n  void sb(Address address, int64_t value);\n  void sh(Address address, int64_t value);\n  void sw(Address address, int64_t value);\n  void sd(Address address, int64_t even, int64_t odd);\n\n  void cycle() = delete;\n\n private:\n  sram::WRAM *wram_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/pipeline.cc",
    "content": "#include \"simulator/dpu/pipeline.h\"\n\n#include \"converter/instruction_converter.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nPipeline::Pipeline(util::ArgumentParser *argument_parser)\n    : input_q_(new basic::Queue<abi::instruction::Instruction>(1)),\n      ready_q_(new basic::Queue<abi::instruction::Instruction>(1)) {\n  int num_pipeline_stages = static_cast<int>(\n      argument_parser->get_int_parameter(\"num_pipeline_stages\"));\n  assert(num_pipeline_stages > 1);\n  wait_q_ =\n      new basic::Queue<abi::instruction::Instruction>(num_pipeline_stages - 1);\n\n  while (wait_q_->can_push()) {\n    wait_q_->push(nullptr);\n  }\n  ready_q_->push(nullptr);\n}\n\nPipeline::~Pipeline() {\n  while (wait_q_->can_pop()) {\n    if (wait_q_->front() != nullptr) {\n      converter::InstructionConverter::to_string(wait_q_->front());\n    }\n\n    assert(wait_q_->pop() == nullptr);\n  }\n\n  while (ready_q_->can_pop()) {\n    assert(ready_q_->pop() == nullptr);\n  }\n\n  delete input_q_;\n  delete wait_q_;\n  delete ready_q_;\n}\n\nvoid Pipeline::push(abi::instruction::Instruction *instruction) {\n  assert(can_push());\n  assert(instruction != nullptr);\n\n  input_q_->push(instruction);\n}\n\nvoid Pipeline::cycle() {\n  service_input_q();\n  service_wait_q();\n}\n\nbool Pipeline::empty_wait_q() {\n  std::queue<abi::instruction::Instruction *> wait_q;\n  while (wait_q_->can_pop()) {\n    abi::instruction::Instruction *instruction = wait_q_->pop();\n    wait_q.push(instruction);\n  }\n\n  while (not wait_q.empty()) {\n    abi::instruction::Instruction *instruction = wait_q.front();\n    wait_q.pop();\n\n    wait_q_->push(instruction);\n    if (instruction != nullptr) {\n      return false;\n    }\n  }\n  return true;\n}\n\nvoid Pipeline::service_input_q() {\n  if (input_q_->can_pop() and wait_q_->can_push()) {\n    abi::instruction::Instruction *instruction = input_q_->pop();\n    wait_q_->push(instruction);\n  } else if (wait_q_->can_push()) {\n    wait_q_->push(nullptr);\n  }\n}\n\nvoid Pipeline::service_wait_q() {\n  if (wait_q_->can_pop() and ready_q_->can_push()) {\n    abi::instruction::Instruction *instruction = wait_q_->pop();\n    ready_q_->push(instruction);\n  }\n}\n\n}  // namespace upmem_sim::simulator::dpu\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/pipeline.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_PIPELINE_H_\n#define UPMEM_SIM_SIMULATOR_DPU_PIPELINE_H_\n\n#include \"abi/instruction/instruction.h\"\n#include \"simulator/basic/queue.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nclass Pipeline {\n public:\n  explicit Pipeline(util::ArgumentParser *argument_parser);\n  ~Pipeline();\n\n  bool empty() {\n    return empty_input_q() and empty_wait_q() and empty_ready_q();\n  }\n  bool can_push() { return input_q_->can_push(); }\n  void push(abi::instruction::Instruction *instruction);\n  bool can_pop() { return ready_q_->can_pop(); }\n  abi::instruction::Instruction *pop() { return ready_q_->pop(); }\n  void cycle();\n\n protected:\n  bool empty_input_q() { return input_q_->empty(); }\n  bool empty_wait_q();\n  bool empty_ready_q() {\n    return ready_q_->empty() or ready_q_->front() == nullptr;\n  }\n\n  void service_input_q();\n  void service_wait_q();\n\n private:\n  basic::Queue<abi::instruction::Instruction> *input_q_;\n  basic::Queue<abi::instruction::Instruction> *wait_q_;\n  basic::Queue<abi::instruction::Instruction> *ready_q_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/revolver_scheduler.cc",
    "content": "#include \"simulator/dpu/revolver_scheduler.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nRevolverScheduler::RevolverScheduler(util::ArgumentParser *argument_parser,\n                                     std::vector<Thread *> threads)\n    : thread_q_(new basic::Queue<Thread>(threads.size())),\n      stat_factory_(new util::StatFactory(\"RevolverScheduler\")) { \n  num_revolver_scheduling_cycles_ = static_cast<int>(\n      argument_parser->get_int_parameter(\"num_revolver_scheduling_cycles\"));\n\n  assert(num_revolver_scheduling_cycles_ > 0);\n\n  threads_ = threads;\n\n  for (auto &thread : threads) {\n    thread_q_->push(thread);\n  }\n}\n\nRevolverScheduler::~RevolverScheduler() {\n  while (thread_q_->can_pop()) {\n    thread_q_->pop();\n  }\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *RevolverScheduler::stat_factory() { \n  auto stat_factory = new util::StatFactory(\"\");\n  stat_factory->merge(stat_factory_);\n  return stat_factory;\n}\n\nThread *RevolverScheduler::schedule() {\n  bool is_blocked = false;\n  for (int i = 0; i < thread_q_->size(); i++) {\n    Thread *thread = thread_q_->pop();\n    thread_q_->push(thread);\n\n    if (thread->issue_cycle() >= num_revolver_scheduling_cycles_) {\n      if (thread->state() == Thread::RUNNABLE) {\n        thread->reset_issue_cycle();\n\n        stat_factory_->increment(\"breakdown_run\");\n\n        return thread;\n      } else if (thread->state() == Thread::BLOCK) {\n        is_blocked = true;\n      }\n    }\n  }\n\n  if (is_blocked) {\n    stat_factory_->increment(\"breakdown_dma\");\n  } else {\n    stat_factory_->increment(\"breakdown_etc\");\n  }\n\n  return nullptr;\n}\n\nbool RevolverScheduler::boot(ThreadID id) {\n  Thread *thread = threads_[id];\n  assert(thread->id() == id);\n\n  if (thread->state() == Thread::EMBRYO) {\n    thread->set_state(Thread::RUNNABLE);\n    return true;\n  } else if (thread->state() == Thread::ZOMBIE) {\n    thread->set_state(Thread::RUNNABLE);\n    return true;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nbool RevolverScheduler::sleep(ThreadID id) {\n  Thread *thread = threads_[id];\n  assert(thread->id() == id);\n\n  if (thread->state() == Thread::RUNNABLE) {\n    thread->set_state(Thread::SLEEP);\n    return true;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nbool RevolverScheduler::block(ThreadID id) {\n  Thread *thread = threads_[id];\n  assert(thread->id() == id);\n\n  if (thread->state() == Thread::RUNNABLE) {\n    thread->set_state(Thread::BLOCK);\n    return true;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nbool RevolverScheduler::awake(ThreadID id) {\n  Thread *thread = threads_[id];\n  assert(thread->id() == id);\n\n  if (thread->state() == Thread::EMBRYO) {\n    thread->set_state(Thread::RUNNABLE);\n    return true;\n  } else if (thread->state() == Thread::SLEEP) {\n    thread->set_state(Thread::RUNNABLE);\n    return true;\n  } else if (thread->state() == Thread::BLOCK) {\n    thread->set_state(Thread::RUNNABLE);\n    return true;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nbool RevolverScheduler::shutdown(ThreadID id) {\n  Thread *thread = threads_[id];\n  assert(thread->id() == id);\n\n  if (thread->state() == Thread::SLEEP) {\n    thread->set_state(Thread::ZOMBIE);\n    return true;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nvoid RevolverScheduler::cycle() {\n  int num_active_tasklets = 0, num_embryo = 0, num_sleep = 0, num_block = 0,\n      num_zombie = 0;\n\n  for (auto &thread : threads_) {\n    if (thread->state() == Thread::RUNNABLE and\n        thread->issue_cycle() < num_revolver_scheduling_cycles_) {\n      stat_factory_->increment(\"revolver_wait\");                 \n      stat_factory_->increment(std::to_string(thread->id()) +\n                               \"_revolver_wait\");\n    }\n\n    thread->increment_issue_cycle();\n\n    if (thread->state() == Thread::RUNNABLE)\n      num_active_tasklets++;\n    else if (thread->state() == Thread::EMBRYO)\n      num_embryo++;\n    else if (thread->state() == Thread::SLEEP)\n      num_sleep++;\n    else if (thread->state() == Thread::BLOCK)\n      num_block++;\n    else if (thread->state() == Thread::ZOMBIE)\n      num_zombie++;\n    else\n      assert(0);\n  }\n  assert(num_active_tasklets <= 16);\n  stat_factory_->overwrite(\"current_active_tasklets\",\n                           num_active_tasklets); \n\n  stat_factory_->increment(\"active_tasklets_\" +\n                           std::to_string(num_active_tasklets));\n\n  stat_factory_->increment(\"total_EMBRYO\", num_embryo);\n  stat_factory_->increment(\"total_RUNNABLE\", num_active_tasklets);\n  stat_factory_->increment(\"total_SLEEP\", num_sleep);\n  stat_factory_->increment(\"total_BLOCK\", num_block);\n  stat_factory_->increment(\"total_ZOMBIE\", num_zombie);\n\n  issuable_threads_ = num_active_tasklets;\n}\n\n}  // namespace upmem_sim::simulator::dpu"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/revolver_scheduler.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_REVOLVER_SCHEDULER_H_\n#define UPMEM_SIM_SIMULATOR_DPU_REVOLVER_SCHEDULER_H_\n\n#include <vector>\n\n#include \"simulator/basic/queue.h\"\n#include \"simulator/dpu/thread.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\" \n\nnamespace upmem_sim::simulator::dpu {\n\nclass RevolverScheduler {\n public:\n  explicit RevolverScheduler(util::ArgumentParser *argument_parser,\n                             std::vector<Thread *> threads);\n  ~RevolverScheduler();\n\n  util::StatFactory *stat_factory();\n  std::vector<Thread *> threads() { return threads_; }\n\n  Thread *schedule();\n\n  bool boot(ThreadID id);\n  bool sleep(ThreadID id);\n  bool block(ThreadID id);\n  bool awake(ThreadID id);\n  bool shutdown(ThreadID id);\n\n  void cycle();\n\n  int get_issuable_threads() { return issuable_threads_; };\n\n private:\n  int num_revolver_scheduling_cycles_;\n  int issuable_threads_;\n\n  std::vector<Thread *> threads_;\n  basic::Queue<Thread> *thread_q_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/thread.cc",
    "content": "#include \"simulator/dpu/thread.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nThread::~Thread() {\n  assert(state_ == ZOMBIE);\n  delete reg_file_;\n}\n\n}  // namespace upmem_sim::simulator::dpu"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dpu/thread.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DPU_THREAD_H_\n#define UPMEM_SIM_SIMULATOR_DPU_THREAD_H_\n\n#include <cassert>\n#include <map>\n\n#include \"simulator/reg/reg_file.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::simulator::dpu {\n\nusing ThreadStatus = std::string;\n\nclass Thread {\n public:\n  enum State { EMBRYO = 0, RUNNABLE, SLEEP, BLOCK, ZOMBIE };\n\n  explicit Thread(ThreadID id)\n      : id_(id),\n        state_(EMBRYO),\n        reg_file_(new reg::RegFile(id_)),\n        issue_cycle_(0) {\n    assert(0 <= id and id < upmem_sim::util::ConfigLoader::max_num_tasklets());\n    status_tracker_.emplace(\"WAIT_DATA\", 0);\n    status_tracker_.emplace(\"WAIT_SYNC\", 0);\n    status_tracker_.emplace(\"ARITHMETIC\", 0);\n    status_tracker_.emplace(\"SPM_ACCESS\", 0);\n    status_tracker_.emplace(\"WAIT_SCHEDULE\", 0);\n  }\n  ~Thread();\n\n  ThreadID id() { return id_; }\n  State state() { return state_; }\n  void set_state(State state) { state_ = state; }\n  reg::RegFile *reg_file() { return reg_file_; }\n  int issue_cycle() { return issue_cycle_; }\n  void increment_issue_cycle() { issue_cycle_ += 1; }\n  void reset_issue_cycle() { issue_cycle_ = 0; }\n\n  void update_thread_status(ThreadStatus status, int64_t value) {\n    status_tracker_[std::move(status)] += value;\n  }\n  std::map<ThreadStatus, int64_t> &status_tracker() { return status_tracker_; }\n\n private:\n  ThreadID id_;\n  State state_;\n  std::map<ThreadStatus, int64_t> status_tracker_;\n  reg::RegFile *reg_file_;\n  int issue_cycle_;\n};\n\n}  // namespace upmem_sim::simulator::dpu\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/fifo_scheduler.cc",
    "content": "#include \"simulator/dram/fifo_scheduler.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nvoid FIFOScheduler::cycle() {\n  service_input_q();\n  service_output_q();\n}\n\nvoid FIFOScheduler::service_input_q() {\n  if (input_q_->can_pop()) {\n    dpu::DMACommand *dma_command = input_q_->pop();\n    service_dma_command(dma_command);\n  }\n}\n\nvoid FIFOScheduler::service_dma_command(dpu::DMACommand *dma_command) {\n  Address begin_address = dma_command->mram_address();\n  Address end_address = dma_command->mram_address() + dma_command->size();\n  Address address = begin_address;\n  while (address < end_address) {\n    Address min_access_granularity =\n        util::ConfigLoader::min_access_granularity();\n    Address wordline_address =\n        (address / wordline_size_) * wordline_size_ + wordline_size_;\n    Address size =\n        std::min(std::min(address + min_access_granularity, wordline_address),\n                 end_address) -\n        address;\n\n    reorder_buffer_.push_back({dma_command, address, size});\n\n    address += size;\n  }\n}\n\nvoid FIFOScheduler::service_output_q() {\n  if (not reorder_buffer_.empty()) {\n    service_fcfs();\n  }\n}\n\nbool FIFOScheduler::service_fcfs() {\n  auto [dma_command, address, size] = reorder_buffer_[0];\n  Address wordline_address = (address / wordline_size_) * wordline_size_;\n\n  if (row_address_ == nullptr and ready_q_->can_push(2)) {\n    reorder_buffer_.erase(reorder_buffer_.begin());\n\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::ACTIVATION, wordline_address));\n\n    row_address_ = new abi::word::DataAddressWord();\n    row_address_->set_value(wordline_address);\n\n    if (dma_command->operation() == dpu::DMACommand::READ) {\n      ready_q_->push(\n          new MemoryCommand(MemoryCommand::READ, address, size, dma_command));\n    } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n      ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                       dma_command->bytes(address, size),\n                                       dma_command));\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n\n    stat_factory_->increment(\"row_buffer_miss\");\n\n    return true;\n  } else if (row_address_ != nullptr and\n             row_address_->address() == wordline_address and\n             ready_q_->can_push(1)) {\n    reorder_buffer_.erase(reorder_buffer_.begin());\n\n    if (dma_command->operation() == dpu::DMACommand::READ) {\n      ready_q_->push(\n          new MemoryCommand(MemoryCommand::READ, address, size, dma_command));\n    } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n      ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                       dma_command->bytes(address, size),\n                                       dma_command));\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n\n    stat_factory_->increment(\"row_buffer_hit\");\n\n    return true;\n  } else if (row_address_ != nullptr and\n             row_address_->address() != wordline_address and\n             ready_q_->can_push(3)) {\n    reorder_buffer_.erase(reorder_buffer_.begin());\n\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::PRECHARGE, row_address_->address()));\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::ACTIVATION, wordline_address));\n\n    row_address_->set_value(wordline_address);\n\n    if (dma_command->operation() == dpu::DMACommand::READ) {\n      ready_q_->push(\n          new MemoryCommand(MemoryCommand::READ, address, size, dma_command));\n    } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n      ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                       dma_command->bytes(address, size),\n                                       dma_command));\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n\n    stat_factory_->increment(\"row_buffer_miss\");\n\n    return true;\n  } else {\n    return false;\n  }\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/fifo_scheduler.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_FIFO_SCHEDULER_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_FIFO_SCHEDULER_H_\n\n#include \"simulator/dram/scheduler.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass FIFOScheduler : public Scheduler {\n public:\n  explicit FIFOScheduler(util::ArgumentParser *argument_parser)\n      : Scheduler(argument_parser) {}\n  ~FIFOScheduler() { assert(reorder_buffer_.empty()); }\n\n  void cycle() final;\n\n protected:\n  void service_input_q();\n  void service_dma_command(dpu::DMACommand *dma_command);\n  void service_output_q();\n\n  bool service_fcfs();\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/frfcfs_scheduler.cc",
    "content": "#include \"simulator/dram/frfcfs_scheduler.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nvoid FRFCFSScheduler::cycle() {\n  service_input_q();\n  service_output_q();\n}\n\nvoid FRFCFSScheduler::service_input_q() {\n  if (input_q_->can_pop()) {\n    dpu::DMACommand *dma_command = input_q_->pop();\n    service_dma_command(dma_command);\n  }\n}\n\nvoid FRFCFSScheduler::service_dma_command(dpu::DMACommand *dma_command) {\n  Address begin_address = dma_command->mram_address();\n  Address end_address = dma_command->mram_address() + dma_command->size();\n  Address address = begin_address;\n  while (address < end_address) {\n    Address min_access_granularity =\n        util::ConfigLoader::min_access_granularity();\n    Address wordline_address =\n        (address / wordline_size_) * wordline_size_ + wordline_size_;\n    Address size =\n        std::min(std::min(address + min_access_granularity, wordline_address),\n                 end_address) -\n        address;\n\n    reorder_buffer_.push_back({dma_command, address, size});\n\n    address += size;\n  }\n}\n\nvoid FRFCFSScheduler::service_output_q() {\n  if (not reorder_buffer_.empty()) {\n    bool is_fr = service_fr();\n\n    if (not is_fr) {\n      service_fcfs();\n    }\n  }\n}\n\nbool FRFCFSScheduler::service_fr() {\n  if (row_address_ == nullptr) {\n    return false;\n  } else {\n    for (int i = 0; i < reorder_buffer_.size(); i++) {\n      auto [dma_command, address, size] = reorder_buffer_[i];\n\n      Address wordline_address = (address / wordline_size_) * wordline_size_;\n\n      if (row_address_->address() == wordline_address and\n          ready_q_->can_push(1)) {\n        if (dma_command->operation() == dpu::DMACommand::READ) {\n          ready_q_->push(new MemoryCommand(MemoryCommand::READ, address, size,\n                                           dma_command));\n          reorder_buffer_.erase(reorder_buffer_.begin() + i);\n        } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n          ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                           dma_command->bytes(address, size),\n                                           dma_command));\n          reorder_buffer_.erase(reorder_buffer_.begin() + i);\n        } else {\n          throw std::invalid_argument(\"\");\n        }\n\n        if (i != 0) {\n          stat_factory_->increment(\"num_fr\");\n        } else {\n          stat_factory_->increment(\"num_fcfs\");\n        }\n\n        stat_factory_->increment(\"row_buffer_hit\");\n\n        return true;\n      }\n    }\n    return false;\n  }\n}\n\nbool FRFCFSScheduler::service_fcfs() {\n  if (row_address_ == nullptr and ready_q_->can_push(2)) {\n    auto [dma_command, address, size] = reorder_buffer_[0];\n    reorder_buffer_.erase(reorder_buffer_.begin());\n\n    Address wordline_address = (address / wordline_size_) * wordline_size_;\n\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::ACTIVATION, wordline_address));\n\n    row_address_ = new abi::word::DataAddressWord();\n    row_address_->set_value(wordline_address);\n\n    if (dma_command->operation() == dpu::DMACommand::READ) {\n      ready_q_->push(\n          new MemoryCommand(MemoryCommand::READ, address, size, dma_command));\n    } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n      ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                       dma_command->bytes(address, size),\n                                       dma_command));\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n\n    stat_factory_->increment(\"row_buffer_miss\");\n\n    return true;\n  } else if (row_address_ != nullptr and ready_q_->can_push(3)) {\n    auto [dma_command, address, size] = reorder_buffer_[0];\n    reorder_buffer_.erase(reorder_buffer_.begin());\n\n    Address wordline_address = (address / wordline_size_) * wordline_size_;\n\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::PRECHARGE, row_address_->address()));\n    ready_q_->push(\n        new MemoryCommand(MemoryCommand::ACTIVATION, wordline_address));\n\n    row_address_->set_value(wordline_address);\n\n    if (dma_command->operation() == dpu::DMACommand::READ) {\n      ready_q_->push(\n          new MemoryCommand(MemoryCommand::READ, address, size, dma_command));\n    } else if (dma_command->operation() == dpu::DMACommand::WRITE) {\n      ready_q_->push(new MemoryCommand(MemoryCommand::WRITE, address, size,\n                                       dma_command->bytes(address, size),\n                                       dma_command));\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n\n    stat_factory_->increment(\"row_buffer_miss\");\n\n    return true;\n  } else {\n    return false;\n  }\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/frfcfs_scheduler.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_FRFCFS_SCHEDULER_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_FRFCFS_SCHEDULER_H_\n\n#include \"simulator/dram/scheduler.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass FRFCFSScheduler : public Scheduler {\n public:\n  explicit FRFCFSScheduler(util::ArgumentParser *argument_parser)\n      : Scheduler(argument_parser) {}\n  ~FRFCFSScheduler() { assert(reorder_buffer_.empty()); }\n\n  void cycle() final;\n\n protected:\n  void service_input_q();\n  void service_dma_command(dpu::DMACommand *dma_command);\n  void service_output_q();\n\n  bool service_fr();\n  bool service_fcfs();\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/memory_command.cc",
    "content": "#include \"simulator/dram/memory_command.h\"\n\n#include <cassert>\n\n#include \"abi/word/data_word.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nMemoryCommand::MemoryCommand(Operation operation, Address address)\n    : operation_(operation),\n      address_(new abi::word::DataAddressWord()),\n      size_(0),\n      dma_command_(nullptr) {\n  assert(operation == ACTIVATION or operation == PRECHARGE);\n  assert(address >= util::ConfigLoader::mram_offset());\n  assert(address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n\n  address_->set_value(address);\n}\n\nMemoryCommand::MemoryCommand(Operation operation, Address address, Address size,\n                             dpu::DMACommand *dma_command)\n    : operation_(operation),\n      address_(new abi::word::DataAddressWord()),\n      size_(size),\n      dma_command_(dma_command) {\n  assert(operation == READ);\n  assert(address >= util::ConfigLoader::mram_offset());\n  assert(address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(dma_command->operation() == dpu::DMACommand::Operation::READ);\n\n  address_->set_value(address);\n}\n\nMemoryCommand::MemoryCommand(Operation operation, Address address, Address size,\n                             std::vector<int> bytes,\n                             dpu::DMACommand *dma_command)\n    : operation_(operation),\n      address_(new abi::word::DataAddressWord()),\n      size_(size),\n      bytes_(bytes),\n      dma_command_(dma_command) {\n  assert(operation == WRITE);\n  assert(address >= util::ConfigLoader::mram_offset());\n  assert(address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(dma_command->operation() == dpu::DMACommand::Operation::WRITE);\n\n  address_->set_value(address);\n}\n\nMemoryCommand::~MemoryCommand() { delete address_; }\n\nstd::vector<int> MemoryCommand::bytes() {\n  assert(operation_ == READ or operation_ == WRITE);\n  return bytes_;\n}\n\ndpu::DMACommand *MemoryCommand::dma_command() {\n  assert(dma_command_ != nullptr);\n  return dma_command_;\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/memory_command.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_MEMORY_COMMAND_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_MEMORY_COMMAND_H_\n\n#include \"abi/word/data_address_word.h\"\n#include \"abi/word/data_word.h\"\n#include \"simulator/dpu/dma_command.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass MemoryCommand {\n public:\n  enum Operation {\n    ACTIVATION = 0,\n    READ,\n    WRITE,\n    PRECHARGE,\n  };\n\n  explicit MemoryCommand(Operation operation, Address address);\n  explicit MemoryCommand(Operation operation, Address address, Address size,\n                         dpu::DMACommand *dma_command);\n  explicit MemoryCommand(Operation operation, Address address, Address size,\n                         std::vector<int> bytes, dpu::DMACommand *dma_command);\n  ~MemoryCommand();\n\n  Operation operation() { return operation_; }\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n  std::vector<int> bytes();\n  void set_bytes(std::vector<int> bytes) { bytes_ = bytes; }\n  dpu::DMACommand *dma_command();\n\n private:\n  Operation operation_;\n  abi::word::DataAddressWord *address_;\n  Address size_;\n  std::vector<int> bytes_;\n  dpu::DMACommand *dma_command_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/memory_controller.cc",
    "content": "#include \"simulator/dram/memory_controller.h\"\n\n#include \"simulator/dram/fifo_scheduler.h\"\n#include \"simulator/dram/frfcfs_scheduler.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nMemoryController::MemoryController(util::ArgumentParser *argument_parser)\n    : wordline_size_(argument_parser->get_int_parameter(\"wordline_size\")),\n      row_buffer_(new RowBuffer(argument_parser)),\n      mram_(nullptr),\n      input_q_(new basic::Queue<dpu::DMACommand>(-1)),\n      wait_q_(new basic::Queue<dpu::DMACommand>(-1)),\n      memory_command_q_(new basic::Queue<MemoryCommand>(1)),\n      ready_q_(new basic::Queue<dpu::DMACommand>(-1)),\n      stat_factory_(new util::StatFactory(\"MemoryController\")) {\n  std::string memory_scheduling_policy =\n      argument_parser->get_string_parameter(\"memory_scheduling_policy\");\n  if (memory_scheduling_policy == \"fifo\") {\n    scheduler_ = new FIFOScheduler(argument_parser);\n  } else if (memory_scheduling_policy == \"frfcfs\") {\n    scheduler_ = new FRFCFSScheduler(argument_parser);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\nMemoryController::~MemoryController() {\n  delete scheduler_;\n  delete row_buffer_;\n  delete input_q_;\n  delete wait_q_;\n  delete memory_command_q_;\n  delete ready_q_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *MemoryController::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  util::StatFactory *scheduler_stat_factory = scheduler_->stat_factory();\n  util::StatFactory *row_buffer_stat_factory = row_buffer_->stat_factory();\n\n  stat_factory->merge(stat_factory_);\n  stat_factory->merge(scheduler_stat_factory);\n  stat_factory->merge(row_buffer_stat_factory);\n\n  delete scheduler_stat_factory;\n  delete row_buffer_stat_factory;\n\n  return stat_factory;\n}\n\nvoid MemoryController::connect_mram(MRAM *mram) {\n  assert(mram != nullptr);\n  assert(mram_ == nullptr);\n\n  mram_ = mram;\n  row_buffer_->connect_mram(mram);\n}\n\nvoid MemoryController::push(dpu::DMACommand *dma_command) {\n  assert(dma_command != nullptr);\n  input_q_->push(dma_command);\n}\n\ndpu::DMACommand *MemoryController::pop() {\n  assert(can_pop());\n  return ready_q_->pop();\n}\n\ndpu::DMACommand *MemoryController::front() {\n  assert(can_pop());\n  return ready_q_->front();\n}\n\nstd::vector<int> MemoryController::read(Address address, Address size) {\n  Address end_address = address + size;\n\n  Address cur_address = address;\n\n  std::vector<int> bytes;\n  while (cur_address < end_address) {\n    Address cur_wordline_address =\n        (cur_address / wordline_size_) * wordline_size_;\n    Address cur_size =\n        std::min(cur_wordline_address + wordline_size_, end_address) -\n        cur_address;\n    int cur_offset = cur_address % wordline_size_;\n\n    std::vector<int> mram_bytes = mram_->read(cur_wordline_address);\n\n    bytes.insert(bytes.end(), mram_bytes.begin() + cur_offset,\n                 mram_bytes.begin() + cur_offset + cur_size);\n\n    cur_address += cur_size;\n  }\n\n  return std::move(bytes);\n}\n\nvoid MemoryController::write(Address address, Address size,\n                             std::vector<int> bytes) {\n  assert(bytes.size() == size);\n\n  Address end_address = address + size;\n\n  Address cur_address = address;\n  int cur_bytes_offset = 0;\n  while (cur_address < end_address) {\n    Address cur_wordline_address =\n        (cur_address / wordline_size_) * wordline_size_;\n    Address cur_size =\n        std::min(cur_wordline_address + wordline_size_, end_address) -\n        cur_address;\n    int cur_offset = cur_address % wordline_size_;\n\n    std::vector<int> mram_bytes = mram_->read(cur_wordline_address);\n\n    std::copy(bytes.begin() + cur_bytes_offset,\n              bytes.begin() + cur_bytes_offset + cur_size,\n              mram_bytes.begin() + cur_offset);\n\n    mram_->write(cur_wordline_address, mram_bytes);\n\n    cur_address += cur_size;\n    cur_bytes_offset += cur_size;\n  }\n}\n\nvoid MemoryController::write(Address address, Address size,\n                             encoder::ByteStream *byte_stream) {\n  assert(byte_stream->size() == size);\n\n  std::vector<int> bytes = byte_stream->bytes();\n\n  Address end_address = address + size;\n\n  Address cur_address = address;\n  int cur_bytes_offset = 0;\n  while (cur_address < end_address) {\n    Address cur_wordline_address =\n        (cur_address / wordline_size_) * wordline_size_;\n    Address cur_size =\n        std::min(cur_wordline_address + wordline_size_, end_address) -\n        cur_address;\n    int cur_offset = cur_address % wordline_size_;\n\n    std::vector<int> mram_bytes = mram_->read(cur_wordline_address);\n\n    std::copy(bytes.begin() + cur_bytes_offset,\n              bytes.begin() + cur_bytes_offset + cur_size,\n              mram_bytes.begin() + cur_offset);\n\n    mram_->write(cur_wordline_address, mram_bytes);\n\n    cur_address += cur_size;\n    cur_bytes_offset += cur_size;\n  }\n}\n\nvoid MemoryController::flush() {\n  scheduler_->flush();\n  row_buffer_->flush();\n}\n\nvoid MemoryController::cycle() {\n  service_input_q();\n  service_scheduler();\n  service_memory_command_q();\n  service_row_buffer();\n  service_wait_q();\n\n  scheduler_->cycle();\n  row_buffer_->cycle();\n\n  stat_factory_->increment(\"mem_cycle\");\n}\n\nvoid MemoryController::service_input_q() {\n  if (input_q_->can_pop() and scheduler_->can_push() and wait_q_->can_push()) {\n    dpu::DMACommand *dma_command = input_q_->pop();\n    scheduler_->push(dma_command);\n    wait_q_->push(dma_command);\n  }\n}\n\nvoid MemoryController::service_scheduler() {\n  if (scheduler_->can_pop() and memory_command_q_->can_push()) {\n    MemoryCommand *memory_command = scheduler_->pop();\n    memory_command_q_->push(memory_command);\n  }\n}\n\nvoid MemoryController::service_memory_command_q() {\n  if (memory_command_q_->can_pop() and row_buffer_->can_push()) {\n    MemoryCommand *memory_command = memory_command_q_->pop();\n    row_buffer_->push(memory_command);\n  }\n}\n\nvoid MemoryController::service_row_buffer() {\n  if (row_buffer_->can_pop()) {\n    MemoryCommand *memory_command = row_buffer_->pop();\n\n    if (memory_command->operation() == MemoryCommand::ACTIVATION or\n        memory_command->operation() == MemoryCommand::PRECHARGE) {\n      delete memory_command;\n    } else if (memory_command->operation() == MemoryCommand::READ) {\n      memory_command->dma_command()->set_bytes(memory_command->address(),\n                                               memory_command->size(),\n                                               memory_command->bytes());\n      memory_command->dma_command()->ack_bytes(memory_command->address(),\n                                               memory_command->size());\n      delete memory_command;\n    } else if (memory_command->operation() == MemoryCommand::WRITE) {\n      memory_command->dma_command()->ack_bytes(memory_command->address(),\n                                               memory_command->size());\n      delete memory_command;\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n  }\n}\n\nvoid MemoryController::service_wait_q() {\n  if (not wait_q_->empty()) {\n    dpu::DMACommand *dma_command = wait_q_->front();\n\n    if (dma_command->is_ready() and ready_q_->can_push()) {\n      wait_q_->pop();\n      ready_q_->push(dma_command);\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/memory_controller.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_MEMORY_CONTROLLER_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_MEMORY_CONTROLLER_H_\n\n#include \"simulator/dram/mram.h\"\n#include \"simulator/dram/row_buffer.h\"\n#include \"simulator/dram/scheduler.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass MemoryController {\n public:\n  explicit MemoryController(util::ArgumentParser *argument_parser);\n  ~MemoryController();\n\n  util::StatFactory *stat_factory();\n\n  void connect_mram(MRAM *mram);\n\n  bool empty() {\n    return input_q_->empty() and wait_q_->empty() and\n           memory_command_q_->empty() and ready_q_->empty() and\n           scheduler_->empty() and row_buffer_->empty();\n  }\n\n  bool can_push() { return input_q_->can_push(); }\n  void push(dpu::DMACommand *dma_command);\n  bool can_pop() { return ready_q_->can_pop(); }\n  dpu::DMACommand *pop();\n  dpu::DMACommand *front();\n\n  std::vector<int> read(Address address, Address size);\n\n  void write(Address address, Address size, std::vector<int> bytes);\n  void write(Address address, Address size, encoder::ByteStream *byte_stream);\n\n  void flush();\n\n  void cycle();\n\n protected:\n  void service_input_q();\n  void service_scheduler();\n  void service_memory_command_q();\n  void service_row_buffer();\n  void service_wait_q();\n\n private:\n  Address wordline_size_;\n\n  Scheduler *scheduler_;\n  RowBuffer *row_buffer_;\n  MRAM *mram_;\n\n  basic::Queue<dpu::DMACommand> *input_q_;\n  basic::Queue<dpu::DMACommand> *wait_q_;\n  basic::Queue<MemoryCommand> *memory_command_q_;\n  basic::Queue<dpu::DMACommand> *ready_q_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/mram.cc",
    "content": "#include \"simulator/dram/mram.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nMRAM::MRAM(util::ArgumentParser *argument_parser)\n    : address_(new abi::word::DataAddressWord()),\n      size_(util::ConfigLoader::mram_size()) {\n  address_->set_value(util::ConfigLoader::mram_offset());\n\n  wordline_size_ = argument_parser->get_int_parameter(\"wordline_size\");\n\n  assert(wordline_size_ > 0);\n  assert(wordline_size_ % util::ConfigLoader::min_access_granularity() == 0);\n  assert(address() % wordline_size_ == 0);\n  assert(size_ % wordline_size_ == 0);\n\n  num_wordlines_ =\n      static_cast<int>(util::ConfigLoader::mram_size() / wordline_size_);\n\n  wordlines_.resize(num_wordlines_);\n  for (int i = 0; i < num_wordlines_; i++) {\n    wordlines_[i] =\n        new Wordline(argument_parser, address() + i * wordline_size_);\n  }\n}\n\nMRAM::~MRAM() {\n  delete address_;\n\n  for (int i = 0; i < num_wordlines_; i++) {\n    delete wordlines_[i];\n  }\n}\n\nstd::vector<int> MRAM::read(Address address) {\n  return std::move(wordlines_[index(address)]->read());\n}\n\nvoid MRAM::write(Address address, std::vector<int> bytes) {\n  wordlines_[index(address)]->write(std::move(bytes));\n}\n\nvoid MRAM::write(Address address, encoder::ByteStream *byte_stream) {\n  wordlines_[index(address)]->write(byte_stream);\n}\n\nint MRAM::index(Address address) {\n  assert(address >= this->address());\n  assert(address + abi::word::DataWord().size() <= this->address() + size_);\n  assert(address % wordline_size_ == 0);\n\n  return static_cast<int>((address - this->address()) / wordline_size_);\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/mram.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_MRAM_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_MRAM_H_\n\n#include <vector>\n\n#include \"abi/word/data_address_word.h\"\n#include \"simulator/dram/wordline.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass MRAM {\n public:\n  explicit MRAM(util::ArgumentParser *argument_parser);\n  ~MRAM();\n\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n\n  std::vector<int> read(Address address);\n\n  void write(Address address, std::vector<int> bytes);\n  void write(Address address, encoder::ByteStream *byte_stream);\n\n  void cycle() = delete;\n\n protected:\n  int index(Address address);\n\n private:\n  abi::word::DataAddressWord *address_;\n  Address size_;\n  std::vector<Wordline *> wordlines_;\n\n  Address wordline_size_;\n  int num_wordlines_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/row_buffer.cc",
    "content": "#include \"simulator/dram/row_buffer.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nRowBuffer::RowBuffer(util::ArgumentParser *argument_parser)\n    : mram_(nullptr),\n      row_address_(nullptr),\n      input_q_(new basic::Queue<MemoryCommand>(1)),\n      ready_q_(new basic::Queue<MemoryCommand>(-1)),\n      stat_factory_(new util::StatFactory(\"row_buffer\")) {\n  timing_parameters_[\"t_ras\"] =\n      static_cast<int>(argument_parser->get_int_parameter(\"t_ras\"));\n  timing_parameters_[\"t_rcd\"] =\n      static_cast<int>(argument_parser->get_int_parameter(\"t_rcd\"));\n  timing_parameters_[\"t_cl\"] =\n      static_cast<int>(argument_parser->get_int_parameter(\"t_cl\"));\n  timing_parameters_[\"t_bl\"] =\n      static_cast<int>(argument_parser->get_int_parameter(\"t_bl\"));\n  timing_parameters_[\"t_rp\"] =\n      static_cast<int>(argument_parser->get_int_parameter(\"t_rp\"));\n\n  assert(timing_parameters_[\"t_ras\"] > 0);\n  assert(timing_parameters_[\"t_rcd\"] > 0);\n  assert(timing_parameters_[\"t_cl\"] > 0);\n  assert(timing_parameters_[\"t_bl\"] > 0);\n  assert(timing_parameters_[\"t_rp\"] > 0);\n\n  wordline_size_ = argument_parser->get_int_parameter(\"wordline_size\");\n\n  assert(wordline_size_ > 0);\n\n  activation_q_ =\n      new basic::TimerQueue<MemoryCommand>(1, timing_parameters_[\"t_ras\"]);\n  io_q_ = new basic::TimerQueue<MemoryCommand>(1, timing_parameters_[\"t_cl\"]);\n  bus_q_ = new basic::TimerQueue<MemoryCommand>(1, timing_parameters_[\"t_bl\"]);\n  precharge_q_ =\n      new basic::TimerQueue<MemoryCommand>(1, timing_parameters_[\"t_rp\"]);\n}\n\nRowBuffer::~RowBuffer() {\n  delete row_address_;\n  delete input_q_;\n  delete ready_q_;\n  delete activation_q_;\n  delete io_q_;\n  delete bus_q_;\n  delete precharge_q_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *RowBuffer::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  stat_factory->merge(stat_factory_);\n\n  return stat_factory;\n}\n\nvoid RowBuffer::connect_mram(MRAM *mram) {\n  assert(mram != nullptr);\n  assert(mram_ == nullptr);\n\n  mram_ = mram;\n}\n\nvoid RowBuffer::push(MemoryCommand *memory_command) {\n  assert(memory_command != nullptr);\n  assert(can_push());\n  input_q_->push(memory_command);\n}\n\nMemoryCommand *RowBuffer::pop() {\n  assert(can_pop());\n  return ready_q_->pop();\n}\n\nvoid RowBuffer::flush() {\n  if (row_address_ != nullptr) {\n    write_to_mram();\n    delete row_address_;\n    row_address_ = nullptr;\n  }\n}\n\nvoid RowBuffer::cycle() {\n  service_input_q();\n  service_activation_q();\n  service_io_q();\n  service_bus_q();\n  service_precharge_q();\n\n  activation_q_->cycle();\n  io_q_->cycle();\n  bus_q_->cycle();\n  precharge_q_->cycle();\n}\n\nvoid RowBuffer::service_input_q() {\n  if (input_q_->can_pop()) {\n    MemoryCommand *memory_command = input_q_->front();\n\n    if (memory_command->operation() == MemoryCommand::ACTIVATION) {\n      if (activation_q_->empty() and row_address_ == nullptr) {\n        activation_q_->push(memory_command);\n        input_q_->pop();\n      }\n    } else if (memory_command->operation() == MemoryCommand::READ) {\n      if (io_q_->can_push() and row_address_ != nullptr) {\n        io_q_->push(memory_command);\n        input_q_->pop();\n      }\n    } else if (memory_command->operation() == MemoryCommand::WRITE) {\n      if (io_q_->can_push() and row_address_ != nullptr) {\n        io_q_->push(memory_command);\n        input_q_->pop();\n      }\n    } else if (memory_command->operation() == MemoryCommand::PRECHARGE) {\n      if (activation_q_->empty() and io_q_->empty() and bus_q_->empty() and\n          precharge_q_->empty()) {\n        precharge_q_->push(memory_command);\n        input_q_->pop();\n      }\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n  }\n}\n\nvoid RowBuffer::service_activation_q() {\n  auto [memory_command, cycle] = activation_q_->front();\n  if (cycle == timing_parameters_[\"t_ras\"] - timing_parameters_[\"t_rcd\"]) {\n    assert(row_address_ == nullptr);\n\n    assert(memory_command->address() % wordline_size_ == 0);\n    row_address_ = new abi::word::DataAddressWord();\n    row_address_->set_value(memory_command->address());\n\n    row_buffer_ = read_from_mram();\n  }\n\n  if (activation_q_->can_pop() and ready_q_->can_push()) {\n    activation_q_->pop();\n    ready_q_->push(memory_command);\n\n    stat_factory_->increment(\"num_activations\");\n  }\n}\n\nvoid RowBuffer::service_io_q() {\n  if (io_q_->can_pop() and bus_q_->can_push()) {\n    MemoryCommand *memory_command = io_q_->pop();\n    bus_q_->push(memory_command);\n  }\n}\n\nvoid RowBuffer::service_bus_q() {\n  if (bus_q_->can_pop() and ready_q_->can_push()) {\n    MemoryCommand *memory_command = bus_q_->pop();\n    ready_q_->push(memory_command);\n\n    if (memory_command->operation() == MemoryCommand::READ) {\n      std::vector<int> bytes = read_from_row_buffer(memory_command->address(),\n                                                    memory_command->size());\n      memory_command->set_bytes(bytes);\n\n      stat_factory_->increment(\"num_reads\");\n      if (memory_command->dma_command()->has_instruction()) {\n        stat_factory_->increment(\n            std::to_string(\n                memory_command->dma_command()->instruction()->thread()->id()) +\n            \"_num_reads\");\n      }\n\n      stat_factory_->increment(\"read_bytes\", memory_command->size());\n      if (memory_command->dma_command()->has_instruction()) {\n        stat_factory_->increment(\n            std::to_string(\n                memory_command->dma_command()->instruction()->thread()->id()) +\n                \"_read_bytes\",\n            memory_command->size());\n      }\n    } else if (memory_command->operation() == MemoryCommand::WRITE) {\n      write_to_row_buffer(memory_command->address(), memory_command->size(),\n                          memory_command->bytes());\n\n      stat_factory_->increment(\"num_writes\");\n      if (memory_command->dma_command()->has_instruction()) {\n        stat_factory_->increment(\n            std::to_string(\n                memory_command->dma_command()->instruction()->thread()->id()) +\n            \"_num_writes\");\n      }\n\n      stat_factory_->increment(\"write_bytes\", memory_command->size());\n      if (memory_command->dma_command()->has_instruction()) {\n        stat_factory_->increment(\n            std::to_string(\n                memory_command->dma_command()->instruction()->thread()->id()) +\n                \"_write_bytes\",\n            memory_command->size());\n      }\n    } else {\n      throw std::invalid_argument(\"\");\n    }\n  }\n}\n\nvoid RowBuffer::service_precharge_q() {\n  if (precharge_q_->can_pop() and ready_q_->can_push()) {\n    MemoryCommand *memory_command = precharge_q_->pop();\n\n    assert(memory_command->address() % wordline_size_ == 0);\n    assert(memory_command->address() == row_address_->address());\n\n    write_to_mram();\n    delete row_address_;\n    row_address_ = nullptr;\n    ready_q_->push(memory_command);\n\n    stat_factory_->increment(\"num_precharges\");\n  }\n}\n\nstd::vector<int> RowBuffer::read_from_mram() {\n  assert(row_address_ != nullptr);\n  return std::move(mram_->read(row_address_->address()));\n}\n\nstd::vector<int> RowBuffer::read_from_row_buffer(Address address,\n                                                 Address size) {\n  assert(row_address_ != nullptr);\n\n  std::vector<int> bytes;\n  bytes.resize(size);\n  std::copy(row_buffer_.begin() + index(address),\n            row_buffer_.begin() + index(address + size), bytes.begin());\n  return std::move(bytes);\n}\n\nvoid RowBuffer::write_to_mram() {\n  assert(row_address_ != nullptr);\n\n  mram_->write(row_address_->address(), std::move(row_buffer_));\n}\n\nvoid RowBuffer::write_to_row_buffer(Address address, Address size,\n                                    std::vector<int> bytes) {\n  assert(size == bytes.size());\n\n  std::copy(bytes.begin(), bytes.end(), row_buffer_.begin() + index(address));\n}\n\nint RowBuffer::index(Address address) {\n  assert(row_address_->address() <= address and\n         address <= row_address_->address() + wordline_size_);\n\n  return static_cast<int>(address - row_address_->address());\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/row_buffer.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_ROW_BUFFER_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_ROW_BUFFER_H_\n\n#include <map>\n#include <string>\n\n#include \"simulator/basic/queue.h\"\n#include \"simulator/basic/timer_queue.h\"\n#include \"simulator/dram/memory_command.h\"\n#include \"simulator/dram/mram.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass RowBuffer {\n public:\n  explicit RowBuffer(util::ArgumentParser *argument_parser);\n  ~RowBuffer();\n\n  util::StatFactory *stat_factory();\n\n  void connect_mram(MRAM *mram);\n\n  bool empty() {\n    return input_q_->empty() and ready_q_->empty() and\n           activation_q_->empty() and io_q_->empty() and bus_q_->empty() and\n           precharge_q_->empty();\n  }\n\n  bool can_push() { return input_q_->can_push(); }\n  void push(MemoryCommand *memory_command);\n  bool can_pop() { return ready_q_->can_pop(); }\n  MemoryCommand *pop();\n\n  void flush();\n\n  void cycle();\n\n protected:\n  void service_input_q();\n  void service_activation_q();\n  void service_io_q();\n  void service_bus_q();\n  void service_precharge_q();\n\n  std::vector<int> read_from_mram();\n  std::vector<int> read_from_row_buffer(Address address, Address size);\n\n  void write_to_mram();\n  void write_to_row_buffer(Address address, Address size,\n                           std::vector<int> bytes);\n\n  int index(Address address);\n\n private:\n  std::map<std::string, int> timing_parameters_;\n  Address wordline_size_;\n\n  MRAM *mram_;\n  abi::word::DataAddressWord *row_address_;\n  std::vector<int> row_buffer_;\n\n  basic::Queue<MemoryCommand> *input_q_;\n  basic::Queue<MemoryCommand> *ready_q_;\n\n  basic::TimerQueue<MemoryCommand> *activation_q_;\n  basic::TimerQueue<MemoryCommand> *io_q_;\n  basic::TimerQueue<MemoryCommand> *bus_q_;\n  basic::TimerQueue<MemoryCommand> *precharge_q_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/scheduler.cc",
    "content": "#include \"simulator/dram/scheduler.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nScheduler::Scheduler(util::ArgumentParser *argument_parser)\n    : input_q_(new basic::Queue<dpu::DMACommand>(-1)),\n      ready_q_(new basic::Queue<MemoryCommand>(3)),\n      row_address_(nullptr),\n      stat_factory_(new util::StatFactory(\"Scheduler\")) {\n  wordline_size_ = argument_parser->get_int_parameter(\"wordline_size\");\n\n  assert(wordline_size_ > 0);\n  assert(wordline_size_ % util::ConfigLoader::min_access_granularity() == 0);\n}\n\nScheduler::~Scheduler() {\n  delete input_q_;\n  delete ready_q_;\n  delete row_address_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *Scheduler::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  stat_factory->merge(stat_factory_);\n\n  return stat_factory;\n}\n\nvoid Scheduler::push(dpu::DMACommand *dma_command) {\n  assert(dma_command != nullptr);\n  input_q_->push(dma_command);\n}\n\nMemoryCommand *Scheduler::pop() {\n  assert(can_pop());\n  return ready_q_->pop();\n}\n\nvoid Scheduler::flush() {\n  delete row_address_;\n  row_address_ = nullptr;\n}\n\n}  // namespace upmem_sim::simulator::dram"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/scheduler.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_SCHEDULER_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_SCHEDULER_H_\n\n#include \"simulator/basic/queue.h\"\n#include \"simulator/dpu/dma_command.h\"\n#include \"simulator/dram/memory_command.h\"\n#include \"util/argument_parser.h\"\n#include \"util/stat_factory.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass Scheduler {\n public:\n  using MemoryReference = std::tuple<dpu::DMACommand *, Address, Address>;\n\n  explicit Scheduler(util::ArgumentParser *argument_parser);\n  ~Scheduler();\n\n  util::StatFactory *stat_factory();\n\n  bool empty() {\n    return input_q_->empty() and ready_q_->empty() and reorder_buffer_.empty();\n  }\n\n  bool can_push() { return input_q_->can_push(); }\n  void push(dpu::DMACommand *dma_command);\n  bool can_pop() { return ready_q_->can_pop(); }\n  MemoryCommand *pop();\n\n  void flush();\n\n  virtual void cycle() = 0;\n\n protected:\n  basic::Queue<dpu::DMACommand> *input_q_;\n  basic::Queue<MemoryCommand> *ready_q_;\n  abi::word::DataAddressWord *row_address_;\n\n  std::vector<MemoryReference> reorder_buffer_;\n\n  Address wordline_size_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/wordline.cc",
    "content": "#include \"simulator/dram/wordline.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nWordline::Wordline(util::ArgumentParser *argument_parser, Address address)\n    : address_(new abi::word::DataAddressWord()),\n      size_(argument_parser->get_int_parameter(\"wordline_size\")) {\n  assert(address >= util::ConfigLoader::mram_offset());\n  assert(address + size_ <=\n         util::ConfigLoader::mram_offset() + util::ConfigLoader::mram_size());\n  assert(address % size_ == 0);\n  assert(size_ % util::ConfigLoader::min_access_granularity() == 0);\n  assert(size_ % abi::word::DataWord().size() == 0);\n\n  address_->set_value(address);\n\n  data_words_.resize(num_data_words());\n  for (int i = 0; i < num_data_words(); i++) {\n    data_words_[i] = new abi::word::DataWord();\n  }\n}\n\nWordline::~Wordline() {\n  delete address_;\n\n  for (int i = 0; i < num_data_words(); i++) {\n    delete data_words_[i];\n  }\n}\n\nstd::vector<int> Wordline::read() {\n  auto byte_stream = new encoder::ByteStream();\n\n  for (int i = 0; i < num_data_words(); i++) {\n    auto data_word_byte_stream = data_words_[i]->to_byte_stream();\n    byte_stream->merge(data_word_byte_stream);\n    delete data_word_byte_stream;\n  }\n\n  std::vector<int> bytes = byte_stream->bytes();\n\n  delete byte_stream;\n\n  return std::move(bytes);\n}\n\nvoid Wordline::write(std::vector<int> bytes) {\n  assert(bytes.size() == size_);\n\n  Address data_word_size = abi::word::DataWord().size();\n  for (int i = 0; i < num_data_words(); i++) {\n    for (int j = 0; j < data_word_size; j++) {\n      int index = static_cast<int>(i * data_word_size + j);\n\n      data_words_[i]->set_bit_slice(8 * j, 8 * (j + 1), bytes[index]);\n    }\n  }\n}\n\nvoid Wordline::write(encoder::ByteStream *byte_stream) {\n  assert(byte_stream->size() == size_);\n\n  for (int i = 0; i < num_data_words(); i++) {\n    encoder::ByteStream *slice = byte_stream->slice(8 * i, 8 * (i + 1));\n    data_words_[i]->from_byte_stream(slice);\n    delete slice;\n  }\n}\n\n}  // namespace upmem_sim::simulator::dram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/dram/wordline.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_DRAM_WORDLINE_H_\n#define UPMEM_SIM_SIMULATOR_DRAM_WORDLINE_H_\n\n#include <vector>\n\n#include \"abi/word/data_address_word.h\"\n#include \"abi/word/data_word.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_sim::simulator::dram {\n\nclass Wordline {\n public:\n  explicit Wordline(util::ArgumentParser *argument_parser, Address address);\n  ~Wordline();\n\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n\n  std::vector<int> read();\n\n  void write(std::vector<int> bytes);\n  void write(encoder::ByteStream *byte_stream);\n\n  void cycle() = delete;\n\n protected:\n  int num_data_words() {\n    return static_cast<int>(size_ / abi::word::DataWord().size());\n  }\n\n private:\n  abi::word::DataAddressWord *address_;\n  Address size_;\n  std::vector<abi::word::DataWord *> data_words_;\n};\n\n}  // namespace upmem_sim::simulator::dram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/rank/rank.cc",
    "content": "#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator::rank {\n\nRank::Rank(util::ArgumentParser* argument_parser)\n    : read_bandwidth_(\n          argument_parser->get_int_parameter(\"rank_read_bandwidth\")),\n      write_bandwidth_(\n          argument_parser->get_int_parameter(\"rank_write_bandwidth\")),\n      stat_factory_(new util::StatFactory(\"Rank\")) {\n  assert(read_bandwidth_ > 0);\n  assert(write_bandwidth_ > 0);\n\n  int num_dpus =\n      static_cast<int>(argument_parser->get_int_parameter(\"num_dpus\"));\n  dpus_.resize(num_dpus);\n  communication_qs_.resize(num_dpus);\n  for (DPUID dpu_id = 0; dpu_id < num_dpus; dpu_id++) {\n    dpus_[dpu_id] = new dpu::DPU(dpu_id, argument_parser);\n    communication_qs_[dpu_id] = new basic::TimerQueue<RankMessage>(-1);\n  }\n}\n\nRank::~Rank() {\n  for (auto& dpu : dpus_) {\n    delete dpu;\n  }\n\n  for (auto & communication_q : communication_qs_) {\n    delete communication_q;\n  }\n\n  delete stat_factory_;\n}\n\nutil::StatFactory* Rank::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  stat_factory->merge(stat_factory_);\n\n  for (auto& dpu : dpus_) {\n    util::StatFactory* dpu_stat_factory = dpu->stat_factory();\n\n    stat_factory->merge(dpu_stat_factory);\n\n    delete dpu_stat_factory;\n  }\n\n  return stat_factory;\n}\n\nvoid Rank::launch() {\n  for (auto& dpu : dpus_) {\n    for (auto& thread : dpu->scheduler()->threads()) {\n      Address bootstrap = util::ConfigLoader::iram_offset();\n      thread->reg_file()->write_pc_reg(bootstrap);\n    }\n    dpu->boot();\n  }\n}\n\nbool Rank::is_zombie() {\n  for (auto& dpu : dpus_) {\n    if (not dpu->is_zombie()) {\n      return false;\n    }\n  }\n  return true;\n}\n\nvoid Rank::read(upmem_sim::simulator::rank::RankMessage*rank_message) {\n  assert(rank_message->operation() == RankMessage::READ);\n  assert(0 <= rank_message->dpu_id() and rank_message->dpu_id() < dpus_.size());\n\n  basic::TimerQueue<RankMessage>* communication_q = communication_qs_[rank_message->dpu_id()];\n  assert(communication_q->can_push());\n\n  SimTime latency = static_cast<SimTime>(10 * rank_message->size() / read_bandwidth_);\n  communication_q->push(rank_message, latency);\n\n  stat_factory_->increment(\"num_reads\");\n  stat_factory_->increment(\"read_bytes\", rank_message->size());\n}\n\nvoid Rank::write(RankMessage*rank_message) {\n  assert(rank_message->operation() == RankMessage::WRITE);\n  assert(0 <= rank_message->dpu_id() and rank_message->dpu_id() < dpus_.size());\n\n\n  basic::TimerQueue<RankMessage>* communication_q = communication_qs_[rank_message->dpu_id()];\n  assert(communication_q->can_push());\n\n  SimTime latency = static_cast<SimTime>(10 * rank_message->size() / write_bandwidth_);\n  communication_q->push(rank_message, latency);\n\n  stat_factory_->increment(\"num_writes\");\n  stat_factory_->increment(\"write_bytes\", rank_message->size());\n}\n\nvoid Rank::cycle() {\n  service_sequence_q();\n\n  for (auto& dpu : dpus_) {\n    dpu->cycle();\n  }\n\n  bool is_communication_q_empty = true;\n  for (auto & communication_q : communication_qs_) {\n    communication_q->cycle();\n\n    if (not communication_q->empty()) {\n      is_communication_q_empty = false;\n    }\n  }\n\n  if (not is_communication_q_empty) {\n    stat_factory_->increment(\"communication_cycle\");\n  }\n\n  stat_factory_->increment(\"rank_cycle\");\n}\n\nvoid Rank::service_sequence_q() {\n  for (auto &communication_q : communication_qs_) {\n    if (communication_q->can_pop()) {\n      RankMessage * rank_message = communication_q->pop();\n      rank_message->set_ack();\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator::rank\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/rank/rank.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_RANK_RANK_H_\n#define UPMEM_SIM_SIMULATOR_RANK_RANK_H_\n\n#include <vector>\n\n#include \"main.h\"\n#include \"simulator/basic/timer_queue.h\"\n#include \"simulator/dpu/dpu.h\"\n#include \"simulator/rank/rank_message.h\"\n\nnamespace upmem_sim::simulator::rank {\n\nclass Rank {\n public:\n  explicit Rank(util::ArgumentParser *argument_parser);\n  ~Rank();\n\n  util::StatFactory *stat_factory();\n\n  std::vector<dpu::DPU *> dpus() { return dpus_; }\n\n  void launch();\n  bool is_zombie();\n\n  void read(RankMessage *rank_message);\n  void write(RankMessage *rank_message);\n\n  void cycle();\n\n protected:\n  void service_sequence_q();\n\n private:\n  Address read_bandwidth_;\n  Address write_bandwidth_;\n\n  std::vector<dpu::DPU *> dpus_;\n  std::vector<basic::TimerQueue<RankMessage>*> communication_qs_;\n\n  util::StatFactory *stat_factory_;\n};\n\n}  // namespace upmem_sim::simulator::rank\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/rank/rank_message.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_RANK_SEQUENCE_MESSAGE_H_\n#define UPMEM_SIM_SIMULATOR_RANK_SEQUENCE_MESSAGE_H_\n\n#include \"encoder/byte_stream.h\"\n#include \"main.h\"\n\nnamespace upmem_sim::simulator::rank {\n\nclass RankMessage {\n public:\n  enum Operation { READ = 0, WRITE };\n\n  explicit RankMessage(Operation operation, DPUID dpu_id, Address address,\n                       Address size)\n      : operation_(operation),\n        dpu_id_(dpu_id),\n        address_(address),\n        size_(size),\n        ack_(false) {}\n  explicit RankMessage(Operation operation, DPUID dpu_id, Address address,\n                       Address size, encoder::ByteStream* byte_stream)\n      : operation_(operation),\n        dpu_id_(dpu_id),\n        address_(address),\n        size_(size),\n        byte_stream_(byte_stream),\n        ack_(false) {\n    assert(byte_stream->size() == size);\n  }\n\n  ~RankMessage() = default;\n\n  Operation operation() { return operation_; }\n\n  DPUID dpu_id() { return dpu_id_; }\n\n  Address address() { return address_; }\n  Address size() { return size_; }\n\n  encoder::ByteStream* byte_stream() { return byte_stream_; }\n\n  bool ack() { return ack_; }\n  void set_ack() {\n    assert(not ack_);\n    ack_ = true;\n  }\n\n private:\n  Operation operation_;\n  DPUID dpu_id_;\n  Address address_;\n  Address size_;\n  encoder::ByteStream* byte_stream_;\n  bool ack_;\n};\n\n}  // namespace upmem_sim::simulator::rank\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/condition_reg.cc",
    "content": "#include \"simulator/reg/condition_reg.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::simulator::reg {\n\nbool ConditionReg::condition(abi::isa::Condition condition) {\n  if (condition == abi::isa::TRUE) {\n    return true;\n  } else if (condition == abi::isa::FALSE) {\n    return false;\n  } else {\n    return bits_[condition];\n  }\n}\n\nvoid ConditionReg::set_condition(abi::isa::Condition condition) {\n  assert(condition != abi::isa::TRUE and condition != abi::isa::FALSE);\n  bits_[condition] = true;\n}\n\nvoid ConditionReg::clear_condition(abi::isa::Condition condition) {\n  assert(condition != abi::isa::TRUE and condition != abi::isa::FALSE);\n  bits_[condition] = false;\n}\n\nvoid ConditionReg::clear_conditions() {\n  for (abi::isa::Condition condition = abi::isa::TRUE;\n       condition <= abi::isa::LARGE;\n       condition = static_cast<abi::isa::Condition>(condition + 1)) {\n    if (condition == abi::isa::TRUE or condition == abi::isa::FALSE) {\n      continue;\n    } else {\n      clear_condition(condition);\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/condition_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_CONDITION_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_CONDITION_REG_H_\n\n#include <vector>\n\n#include \"abi/isa/condition.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass ConditionReg {\n public:\n  explicit ConditionReg() { bits_.resize(abi::isa::LARGE + 1); }\n  ~ConditionReg() = default;\n\n  bool condition(abi::isa::Condition condition);\n  void set_condition(abi::isa::Condition condition);\n  void clear_condition(abi::isa::Condition condition);\n  void clear_conditions();\n  void cycle() = delete;\n\n private:\n  std::vector<bool> bits_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/exception_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_EXCEPTION_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_EXCEPTION_REG_H_\n\n#include <vector>\n\n#include \"abi/isa/exception.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass ExceptionReg {\n public:\n  explicit ExceptionReg() { bits_.resize(abi::isa::NOT_PROFILING + 1); }\n  ~ExceptionReg() = default;\n\n  bool exception(abi::isa::Exception exception) { return bits_[exception]; }\n  void set_exception(abi::isa::Exception exception) { bits_[exception] = true; }\n  void clear_exception(abi::isa::Exception exception) {\n    bits_[exception] = false;\n  }\n  void cycle() = delete;\n\n private:\n  std::vector<bool> bits_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/flag_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_FLAG_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_FLAG_REG_H_\n\n#include <vector>\n\n#include \"abi/isa/flag.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass FlagReg {\n public:\n  explicit FlagReg() { bits_.resize(abi::isa::CARRY + 1); }\n  ~FlagReg() = default;\n\n  bool flag(abi::isa::Flag flag) { return bits_[flag]; }\n  void set_flag(abi::isa::Flag flag) { bits_[flag] = true; }\n  void clear_flag(abi::isa::Flag flag) { bits_[flag] = false; }\n  void cycle() = delete;\n\n private:\n  std::vector<bool> bits_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/gp_reg.cc",
    "content": "#include \"simulator/reg/gp_reg.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nGPReg::~GPReg() {\n  delete gp_reg_;\n  delete word_;\n}\n\n}  // namespace upmem_sim::simulator::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/gp_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_GP_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_GP_REG_H_\n\n#include \"abi/reg/gp_reg.h\"\n#include \"abi/word/data_word.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass GPReg {\n public:\n  explicit GPReg(RegIndex index)\n      : gp_reg_(new abi::reg::GPReg(index)), word_(new abi::word::DataWord()) {}\n  ~GPReg();\n\n  RegIndex index() { return gp_reg_->index(); }\n  int64_t read(abi::word::Representation representation) {\n    return word_->value(representation);\n  }\n  void write(int64_t value) { word_->set_value(value); }\n  void cycle() = delete;\n\n private:\n  abi::reg::GPReg *gp_reg_;\n  abi::word::DataWord *word_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/pc_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_PC_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_PC_REG_H_\n\n#include \"abi/word/instruction_address_word.h\"\n#include \"abi/word/instruction_word.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass PCReg {\n public:\n  explicit PCReg() : word_(new abi::word::InstructionAddressWord()) {}\n  ~PCReg() { delete word_; }\n\n  int64_t read() { return word_->address(); }\n  void write(int64_t value) { word_->set_value(value); }\n  void increment() { write(read() + abi::word::InstructionWord().size()); }\n  void cycle() = delete;\n\n private:\n  abi::word::InstructionAddressWord *word_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/reg_file.cc",
    "content": "#include \"simulator/reg/reg_file.h\"\n\n#include <stdexcept>\n#include <tuple>\n\nnamespace upmem_sim::simulator::reg {\n\nRegFile::RegFile(ThreadID id)\n    : sp_reg_(new SPReg(id)),\n      pc_reg_(new PCReg()),\n      condition_reg_(new ConditionReg()),\n      flag_reg_(new FlagReg()),\n      exception_reg_(new ExceptionReg()) {\n  for (RegIndex index = 0; index < util::ConfigLoader::num_gp_registers();\n       index++) {\n    gp_regs_.push_back(new GPReg(index));\n  }\n}\n\nRegFile::~RegFile() {\n  for (RegIndex index = 0; index < util::ConfigLoader::num_gp_registers();\n       index++) {\n    delete gp_regs_[index];\n  }\n  delete sp_reg_;\n  delete pc_reg_;\n  delete condition_reg_;\n  delete flag_reg_;\n  delete exception_reg_;\n}\n\nstd::tuple<int64_t, int64_t> RegFile::read_pair_reg(\n    abi::reg::PairReg *pair_reg, abi::word::Representation representation) {\n  int64_t even = read_gp_reg(pair_reg->even_reg(), representation);\n  int64_t odd = read_gp_reg(pair_reg->odd_reg(), abi::word::UNSIGNED);\n  return {even, odd};\n}\n\nint64_t RegFile::read_src_reg(abi::reg::SrcReg *src_reg,\n                              abi::word::Representation representation) {\n  if (src_reg->is_gp_reg()) {\n    return read_gp_reg(src_reg->gp_reg(), representation);\n  } else {\n    return read_sp_reg(*src_reg->sp_reg(), representation);\n  }\n}\n\nvoid RegFile::write_pair_reg(abi::reg::PairReg *pair_reg, int64_t even,\n                             int64_t odd) {\n  write_gp_reg(pair_reg->even_reg(), even);\n  write_gp_reg(pair_reg->odd_reg(), odd);\n}\n\n}  // namespace upmem_sim::simulator::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/reg_file.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_REG_FILE_H_\n#define UPMEM_SIM_SIMULATOR_REG_REG_FILE_H_\n\n#include \"abi/reg/pair_reg.h\"\n#include \"abi/reg/src_reg.h\"\n#include \"simulator/reg/condition_reg.h\"\n#include \"simulator/reg/exception_reg.h\"\n#include \"simulator/reg/flag_reg.h\"\n#include \"simulator/reg/gp_reg.h\"\n#include \"simulator/reg/pc_reg.h\"\n#include \"simulator/reg/sp_reg.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass RegFile {\n public:\n  explicit RegFile(ThreadID id);\n  ~RegFile();\n\n  int64_t read_gp_reg(abi::reg::GPReg *gp_reg,\n                      abi::word::Representation representation) {\n    return gp_regs_[gp_reg->index()]->read(representation);\n  }\n  int64_t read_sp_reg(abi::reg::SPReg sp_reg,\n                      abi::word::Representation representation) {\n    return sp_reg_->read(sp_reg, representation);\n  }\n  std::tuple<int64_t, int64_t> read_pair_reg(\n      abi::reg::PairReg *pair_reg, abi::word::Representation representation);\n  int64_t read_src_reg(abi::reg::SrcReg *src_reg,\n                       abi::word::Representation representation);\n\n  int64_t read_pc_reg() { return pc_reg_->read(); }\n  bool condition(abi::isa::Condition condition) {\n    return condition_reg_->condition(condition);\n  }\n  bool flag(abi::isa::Flag flag) { return flag_reg_->flag(flag); }\n  bool exception(abi::isa::Exception exception) {\n    return exception_reg_->exception(exception);\n  }\n\n  void write_gp_reg(abi::reg::GPReg *gp_reg, int64_t value) {\n    gp_regs_[gp_reg->index()]->write(value);\n  }\n  void write_pair_reg(abi::reg::PairReg *pair_reg, int64_t even, int64_t odd);\n  void write_pc_reg(int64_t value) { pc_reg_->write(value); }\n  void increment_pc_reg() { pc_reg_->increment(); }\n\n  void set_condition(abi::isa::Condition condition) {\n    condition_reg_->set_condition(condition);\n  }\n  void clear_condition(abi::isa::Condition condition) {\n    condition_reg_->clear_condition(condition);\n  }\n  void clear_conditions() { condition_reg_->clear_conditions(); }\n\n  void set_flag(abi::isa::Flag flag) { flag_reg_->set_flag(flag); }\n  void clear_flag(abi::isa::Flag flag) { flag_reg_->clear_flag(flag); }\n\n  void set_exception(abi::isa::Exception exception) {\n    exception_reg_->set_exception(exception);\n  }\n  void clear_exception(abi::isa::Exception exception) {\n    exception_reg_->clear_exception(exception);\n  }\n\n  void cycle() = delete;\n\n private:\n  std::vector<GPReg *> gp_regs_;\n  SPReg *sp_reg_;\n  PCReg *pc_reg_;\n  ConditionReg *condition_reg_;\n  FlagReg *flag_reg_;\n  ExceptionReg *exception_reg_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/sp_reg.cc",
    "content": "#include \"simulator/reg/sp_reg.h\"\n\n#include <stdexcept>\n\nnamespace upmem_sim::simulator::reg {\n\nSPReg::SPReg(ThreadID id)\n    : zero_(new abi::word::DataWord()),\n      one_(new abi::word::DataWord()),\n      lneg_(new abi::word::DataWord()),\n      mneg_(new abi::word::DataWord()),\n      id_(new abi::word::DataWord()),\n      id2_(new abi::word::DataWord()),\n      id4_(new abi::word::DataWord()),\n      id8_(new abi::word::DataWord()) {\n  zero_->set_value(0);\n  one_->set_value(1);\n  lneg_->set_value(-1);\n  mneg_->set_bit(mneg_->width() - 1);\n  id_->set_value(id);\n  id2_->set_value(2 * id);\n  id4_->set_value(4 * id);\n  id8_->set_value(8 * id);\n}\n\nSPReg::~SPReg() {\n  delete zero_;\n  delete one_;\n  delete lneg_;\n  delete mneg_;\n  delete id_;\n  delete id2_;\n  delete id4_;\n  delete id8_;\n}\n\nint64_t SPReg::read(abi::reg::SPReg sp_reg,\n                    abi::word::Representation representation) {\n  if (sp_reg == abi::reg::ZERO) {\n    return zero_->value(representation);\n  } else if (sp_reg == abi::reg::ONE) {\n    return one_->value(representation);\n  } else if (sp_reg == abi::reg::LNEG) {\n    return lneg_->value(representation);\n  } else if (sp_reg == abi::reg::MNEG) {\n    return mneg_->value(representation);\n  } else if (sp_reg == abi::reg::ID) {\n    return id_->value(representation);\n  } else if (sp_reg == abi::reg::ID2) {\n    return id2_->value(representation);\n  } else if (sp_reg == abi::reg::ID4) {\n    return id4_->value(representation);\n  } else if (sp_reg == abi::reg::ID8) {\n    return id8_->value(representation);\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n}  // namespace upmem_sim::simulator::reg\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/reg/sp_reg.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_REG_SP_REG_H_\n#define UPMEM_SIM_SIMULATOR_REG_SP_REG_H_\n\n#include \"abi/reg/sp_reg.h\"\n#include \"abi/word/data_word.h\"\n\nnamespace upmem_sim::simulator::reg {\n\nclass SPReg {\n public:\n  explicit SPReg(ThreadID id);\n  ~SPReg();\n\n  int64_t read(abi::reg::SPReg sp_reg,\n               abi::word::Representation representation);\n  void cycle() = delete;\n\n private:\n  abi::word::DataWord *zero_;\n  abi::word::DataWord *one_;\n  abi::word::DataWord *lneg_;\n  abi::word::DataWord *mneg_;\n  abi::word::DataWord *id_;\n  abi::word::DataWord *id2_;\n  abi::word::DataWord *id4_;\n  abi::word::DataWord *id8_;\n};\n\n}  // namespace upmem_sim::simulator::reg\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/atomic.cc",
    "content": "#include \"simulator/sram/atomic.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nAtomic::Atomic() {\n  address_ = new abi::word::DataAddressWord();\n  address_->set_value(util::ConfigLoader::atomic_offset());\n\n  size_ = util::ConfigLoader::atomic_size();\n\n  locks_.resize(size_);\n  for (int i = 0; i < size_; i++) {\n    locks_[i] = new Lock();\n  }\n}\n\nAtomic::~Atomic() {\n  delete address_;\n\n  for (int i = 0; i < size_; i++) {\n    delete locks_[i];\n  }\n}\n\nint Atomic::index(Address address) {\n  assert(address >= this->address());\n  assert(address < this->address() + size_);\n  assert(this->address() <= address and address < this->address() + size_);\n\n  return static_cast<int>(address - this->address());\n}\n\n}  // namespace upmem_sim::simulator::sram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/atomic.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_SRAM_ATOMIC_H_\n#define UPMEM_SIM_SIMULATOR_SRAM_ATOMIC_H_\n\n#include <vector>\n\n#include \"abi/word/data_address_word.h\"\n#include \"simulator/sram/lock.h\"\n#include \"util/config_loader.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nclass Atomic {\n public:\n  explicit Atomic();\n  ~Atomic();\n\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n\n  bool can_acquire(Address address) {\n    return locks_[index(address)]->can_acquire();\n  }\n  void acquire(Address address, ThreadID id) {\n    locks_[index(address)]->acquire(id);\n  }\n  bool can_release(Address address, ThreadID id) {\n    return locks_[index(address)]->can_release(id);\n  }\n  void release(Address address, ThreadID id) {\n    locks_[index(address)]->release(id);\n  }\n  void cycle() = delete;\n\n protected:\n  int index(Address address);\n\n private:\n  abi::word::DataAddressWord *address_;\n  Address size_;\n\n  std::vector<Lock *> locks_;\n};\n\n}  // namespace upmem_sim::simulator::sram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/iram.cc",
    "content": "#include \"simulator/sram/iram.h\"\n\n#include \"encoder/instruction_encoder.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nIRAM::IRAM() {\n  address_ = new abi::word::InstructionAddressWord();\n  address_->set_value(util::ConfigLoader::iram_offset());\n\n  size_ = util::ConfigLoader::iram_size();\n\n  assert(address() % abi::word::InstructionWord().size() == 0);\n  assert(size_ % abi::word::InstructionWord().size() == 0);\n\n  cells_.resize(num_instruction_words());\n  for (int i = 0; i < num_instruction_words(); i++) {\n    cells_[i] = new abi::word::InstructionWord();\n  }\n}\n\nIRAM::~IRAM() {\n  delete address_;\n\n  for (int i = 0; i < size_ / num_instruction_words(); i++) {\n    delete cells_[i];\n  }\n}\n\nabi::instruction::Instruction *IRAM::read(Address address) {\n  encoder::ByteStream *byte_stream = cells_[index(address)]->to_byte_stream();\n  abi::instruction::Instruction *instruction =\n      encoder::InstructionEncoder::decode(byte_stream);\n  delete byte_stream;\n  return instruction;\n}\n\nvoid IRAM::write(Address address, encoder::ByteStream *byte_stream) {\n  cells_[index(address)]->from_byte_stream(byte_stream);\n}\n\nint IRAM::index(Address address) {\n  assert(address >= this->address());\n  assert(address + abi::word::InstructionWord().size() <=\n         this->address() + size_);\n  assert((address - this->address()) % abi::word::InstructionWord().size() ==\n         0);\n\n  return static_cast<int>((address - this->address()) /\n                          abi::word::InstructionWord().size());\n}\n\n}  // namespace upmem_sim::simulator::sram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/iram.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_SRAM_IRAM_H_\n#define UPMEM_SIM_SIMULATOR_SRAM_IRAM_H_\n\n#include \"abi/instruction/instruction.h\"\n#include \"abi/word/instruction_address_word.h\"\n#include \"abi/word/instruction_word.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nclass IRAM {\n public:\n  explicit IRAM();\n  ~IRAM();\n\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n\n  abi::instruction::Instruction *read(Address address);\n  void write(Address address, encoder::ByteStream *byte_stream);\n  void cycle() = delete;\n\n protected:\n  static int num_instruction_words() {\n    return static_cast<int>(util::ConfigLoader::iram_size() /\n                            abi::word::InstructionWord().size());\n  }\n  int index(Address address);\n\n private:\n  abi::word::InstructionAddressWord *address_;\n  Address size_;\n  std::vector<abi::word::InstructionWord *> cells_;\n};\n\n}  // namespace upmem_sim::simulator::sram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/lock.cc",
    "content": "#include \"simulator/sram/lock.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nvoid Lock::acquire(ThreadID id) {\n  assert(can_acquire());\n  id_ = new ThreadID(id);\n}\n\nvoid Lock::release(ThreadID id) {\n  assert(can_release(id));\n\n  delete id_;\n  id_ = nullptr;\n}\n\n}  // namespace upmem_sim::simulator::sram\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/lock.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_SRAM_LOCK_H_\n#define UPMEM_SIM_SIMULATOR_SRAM_LOCK_H_\n\n#include <cassert>\n\n#include \"main.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nclass Lock {\n public:\n  explicit Lock() : id_(nullptr) {}\n  ~Lock() { assert(id_ == nullptr); }\n\n  bool can_acquire() { return id_ == nullptr; }\n  void acquire(ThreadID id);\n  bool can_release(ThreadID id) { return id_ == nullptr or *id_ == id; }\n  void release(ThreadID id);\n  void cycle() = delete;\n\n private:\n  ThreadID *id_;\n};\n\n}  // namespace upmem_sim::simulator::sram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/wram.cc",
    "content": "#include \"simulator/sram/wram.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nWRAM::WRAM() {\n  address_ = new abi::word::DataAddressWord();\n  address_->set_value(util::ConfigLoader::wram_offset());\n\n  size_ = util::ConfigLoader::wram_size();\n\n  assert(address() % abi::word::DataWord().size() == 0);\n  assert(size_ % abi::word::DataWord().size() == 0);\n\n  cells_.resize(num_data_words());\n  for (int i = 0; i < num_data_words(); i++) {\n    cells_[i] = new abi::word::DataWord();\n  }\n}\n\nWRAM::~WRAM() {\n  delete address_;\n\n  for (int i = 0; i < num_data_words(); i++) {\n    delete cells_[i];\n  }\n}\n\nint64_t WRAM::read(Address address) {\n  return cells_[index(address)]->value(abi::word::UNSIGNED);\n}\n\nvoid WRAM::write(Address address, int64_t value) {\n  cells_[index(address)]->set_value(value);\n}\n\nvoid WRAM::write(Address address, encoder::ByteStream *byte_stream) {\n  cells_[index(address)]->from_byte_stream(byte_stream);\n}\n\nint WRAM::index(Address address) {\n  assert(address >= this->address());\n  assert(address + abi::word::DataWord().size() <= this->address() + size_);\n  assert((address - this->address()) % abi::word::DataWord().size() == 0);\n\n  return static_cast<int>((address - this->address()) /\n                          abi::word::DataWord().size());\n}\n\n}  // namespace upmem_sim::simulator::sram"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/sram/wram.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_SRAM_WRAM_H_\n#define UPMEM_SIM_SIMULATOR_SRAM_WRAM_H_\n\n#include \"abi/word/data_address_word.h\"\n#include \"abi/word/data_word.h\"\n\nnamespace upmem_sim::simulator::sram {\n\nclass WRAM {\n public:\n  explicit WRAM();\n  ~WRAM();\n\n  Address address() { return address_->address(); }\n  Address size() { return size_; }\n\n  int64_t read(Address address);\n\n  void write(Address address, int64_t value);\n  void write(Address address, encoder::ByteStream *byte_stream);\n\n  void cycle() = delete;\n\n protected:\n  static int num_data_words() {\n    return static_cast<int>(util::ConfigLoader::wram_size() /\n                            abi::word::DataWord().size());\n  }\n  int index(Address address);\n\n private:\n  abi::word::DataAddressWord *address_;\n  Address size_;\n  std::vector<abi::word::DataWord *> cells_;\n};\n\n}  // namespace upmem_sim::simulator::sram\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/system.cc",
    "content": "#include \"simulator/system.h\"\n\nnamespace upmem_sim::simulator {\n\nSystem::System(util::ArgumentParser *argument_parser)\n    : cpu_(new cpu::CPU(argument_parser)),\n      rank_(new rank::Rank(argument_parser)),\n      execuion_(0), \n      stat_factory_(new util::StatFactory(\"System\")) {\n  benchmark = argument_parser->get_string_parameter(\"benchmark\");\n\n  cpu_->connect_rank(rank_);\n}\n\nSystem::~System() {\n  delete cpu_;\n  delete rank_;\n\n  delete stat_factory_;\n}\n\nutil::StatFactory *System::stat_factory() {\n  auto stat_factory = new util::StatFactory(\"\");\n\n  util::StatFactory *rank_stat_factory = rank_->stat_factory();\n\n  stat_factory->merge(stat_factory_);\n  stat_factory->merge(rank_stat_factory);\n\n  delete rank_stat_factory;\n\n  return stat_factory;\n}\n\nvoid System::init() {\n  cpu_->init();\n  cpu_->sched(execuion_);\n  cpu_->launch();\n}\n\nvoid System::cycle() {\n  cpu_->cycle();\n  rank_->cycle();\n\n  if (is_zombie()) {\n    cpu_->check(execuion_);\n    execuion_ += 1;\n\n    if (not is_finished()) {\n      if(benchmark == \"TRNS\"){\n        cpu_->init();\n      }\n      cpu_->sched(execuion_);\n      cpu_->launch();\n    }\n  }\n}\n\n}  // namespace upmem_sim::simulator\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/simulator/system.h",
    "content": "#ifndef UPMEM_SIM_SIMULATOR_SYSTEM_H_\n#define UPMEM_SIM_SIMULATOR_SYSTEM_H_\n\n#include \"simulator/cpu/cpu.h\"\n#include \"simulator/dpu/dpu.h\"\n#include \"simulator/rank/rank.h\"\n\nnamespace upmem_sim::simulator {\n\nclass System {\n public:\n  explicit System(util::ArgumentParser *argument_parser);\n  ~System();\n\n  util::StatFactory *stat_factory();\n\n  bool is_finished() { return execuion_ == cpu_->num_executions(); }\n\n  void init();\n  void fini() { cpu_->fini(); }\n  void cycle();\n\n protected:\n  bool is_zombie() { return rank_->is_zombie(); }\n\n private:\n  cpu::CPU *cpu_;\n  rank::Rank *rank_;\n\n  int execuion_;\n\n  util::StatFactory *stat_factory_;\n\n  // Tae\n  std::string benchmark;\n};\n\n}  // namespace upmem_sim::simulator\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/util/argument_parser.cc",
    "content": "#include \"util/argument_parser.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::util {\n\nvoid ArgumentParser::add_option(Option option, OptionType option_type,\n                                Parameter default_parameter) {\n  assert(not option_types_.count(option));\n  assert(not default_parameters_.count(option));\n  assert(not custom_parameters_.count(option));\n\n  option_types_[option] = option_type;\n  default_parameters_[option] = default_parameter;\n}\n\nvoid ArgumentParser::parse(int argc, char **argv) {\n  assert(argc % 2 == 1);\n\n  for (int i = 1; i < argc; i += 2) {\n    for (auto &[option, _] : option_types_) {\n      std::string argv_option = std::string(argv[i]);\n\n      assert(argv_option.substr(0, 2) == \"--\");\n\n      if (option == argv_option.substr(2)) {\n        assert(not custom_parameters_.count(option));\n\n        std::string argv_parameter = std::string(argv[i + 1]);\n        custom_parameters_[option] = argv_parameter;\n      }\n    }\n  }\n}\n\nstd::set<ArgumentParser::Option> ArgumentParser::options() {\n  std::set<Option> options;\n  for (auto &[option, _] : option_types_) {\n    options.insert(option);\n  }\n  return std::move(options);\n}\n\nstd::string ArgumentParser::get_string_parameter(Option option) {\n  assert(option_types_[option] == STRING);\n\n  if (custom_parameters_.count(option)) {\n    return custom_parameters_[option];\n  } else {\n    return default_parameters_[option];\n  }\n}\n\nint64_t ArgumentParser::get_int_parameter(Option option) {\n  assert(option_types_[option] == INT);\n\n  if (custom_parameters_.count(option)) {\n    return std::stoi(custom_parameters_[option]);\n  } else {\n    return std::stoi(default_parameters_[option]);\n  }\n}\n\n}  // namespace upmem_sim::util\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/util/argument_parser.h",
    "content": "#ifndef UPMEM_SIM_UTIL_ARGUMENT_PARSER_H_\n#define UPMEM_SIM_UTIL_ARGUMENT_PARSER_H_\n\n#include <map>\n#include <set>\n#include <string>\n\nnamespace upmem_sim::util {\n\nclass ArgumentParser {\n public:\n  using Option = std::string;\n  using Parameter = std::string;\n\n  enum OptionType { STRING = 0, INT };\n\n  explicit ArgumentParser() = default;\n  ~ArgumentParser() = default;\n\n  void add_option(Option option, OptionType option_type,\n                  Parameter default_parameter);\n  void parse(int argc, char **argv);\n\n  std::set<Option> options();\n  OptionType option_type(Option option) { return option_types_[option]; }\n\n  std::string get_string_parameter(Option option);\n  int64_t get_int_parameter(Option option);\n\n private:\n  std::map<Option, OptionType> option_types_;\n  std::map<Option, Parameter> default_parameters_;\n  std::map<Option, Parameter> custom_parameters_;\n};\n\n}  // namespace upmem_sim::util\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/util/config_loader.h",
    "content": "#ifndef UPMEM_SIM_UTIL_CONFIG_LOADER_H_\n#define UPMEM_SIM_UTIL_CONFIG_LOADER_H_\n\n#include \"main.h\"\n\nnamespace upmem_sim::util {\n\nclass ConfigLoader {\n public:\n  static int atomic_address_width() { return 32; }\n  static int atomic_data_width() { return 32; }\n  static Address atomic_offset() { return 0; }\n  static Address atomic_size() { return 256; }\n\n  static int iram_address_width() { return 32; }\n  static int iram_data_width() { return 96; }\n  static Address iram_offset() { return 384 * 1024; }\n  static Address iram_size() { return 48 * 1024; }\n\n  static int wram_address_width() { return 32; }\n  static int wram_data_width() { return 32; }\n  static Address wram_offset() { return 512; }\n  static Address wram_size() { return 128 * 1024; }\n\n  static Address stack_size() { return 2 * 1024; }\n  static Address heap_size() { return 4 * 1024; }\n\n  static int mram_address_width() { return 32; }\n  static int mram_data_width() { return 32; }\n  static Address mram_offset() { return 512 * 1024; }\n  static Address mram_size() { return 64 * 1024 * 1024; }\n\n  static int num_gp_registers() { return 24; }\n  static int max_num_tasklets() { return 24; }\n  static int min_access_granularity() { return 8; }\n};\n\n}  // namespace upmem_sim::util\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/util/stat_factory.cc",
    "content": "#include \"util/stat_factory.h\"\n\n#include <cassert>\n\nnamespace upmem_sim::util {\n\nstd::set<std::string> StatFactory::stats() {\n  std::set<std::string> stats;\n  for (auto &[stat, _] : stats_) {\n    stats.insert(stat);\n  }\n  return std::move(stats);\n}\n\nvoid StatFactory::increment(std::string stat, int64_t value) {\n  if (stats_.count(stat)) {\n    stats_[stat] += value;\n  } else {\n    stats_[stat] = value;\n  }\n}\n\nvoid StatFactory::overwrite(std::string stat, int64_t value) {\n  stats_[stat] = value;\n}\n\nvoid StatFactory::merge(StatFactory *stat_factory) {\n  for (auto &[stat, value] : stat_factory->stats_) {\n    if (stats_.count(stat_factory->name() + \"/\" + stat)) {\n      stats_[stat_factory->name() + \"/\" + stat] += value;\n    } else {\n      stats_[stat_factory->name() + \"/\" + stat] = value;\n    }\n  }\n}\n\n}  // namespace upmem_sim::util\n"
  },
  {
    "path": "python_cpp/uPIMulator_backend/src/util/stat_factory.h",
    "content": "#ifndef UPMEM_SIM_UTIL_STAT_FACTORY_H_\n#define UPMEM_SIM_UTIL_STAT_FACTORY_H_\n\n#include <map>\n#include <set>\n#include <string>\n\nnamespace upmem_sim::util {\n\nclass StatFactory {\n public:\n  explicit StatFactory(std::string name) : name_(name) {}\n  ~StatFactory() = default;\n\n  std::string name() { return name_; }\n\n  std::set<std::string> stats();\n  int64_t value(std::string stat) { return stats_[stat]; }\n\n  void increment(std::string stat) { increment(stat, 1); }\n  void increment(std::string stat, int64_t value);\n  void overwrite(std::string stat, int64_t value);\n\n  void merge(StatFactory *stat_factory);\n\n private:\n  std::string name_;\n  std::map<std::string, int64_t> stats_;\n};\n\n}  // namespace upmem_sim::util\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/.flake8",
    "content": "# Autoformatter friendly flake8 config (all formatting rules disabled)\n[flake8]\nextend-ignore = D1, D2, E1, E2, E3, E501, W1, W2, W3, W5\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/.hadolint.yaml",
    "content": "# Following source doesn't work in most setups\nignored:\n  - SC1090\n  - SC1091\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/.isort.cfg",
    "content": "[settings]\nprofile=black\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/.markdownlint.yaml",
    "content": "# Autoformatter friendly markdownlint config (all formatting rules disabled)\ndefault: true\nblank_lines: false\nbullet: false\nhtml: false\nindentation: false\nline_length: false\nspaces: false\nurl: false\nwhitespace: false\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/.shellcheckrc",
    "content": "enable=all\nsource-path=SCRIPTDIR\ndisable=SC2154\n\n# If you're having issues with shellcheck following source, disable the errors via:\n# disable=SC1090\n# disable=SC1091\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nOP ?= ADD\nTYPE ?= INT32\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP} -D${TYPE}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP} -D${TYPE}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/dpu/task.c",
    "content": "/*\n* Execution of arithmetic operations with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Arithmetic operation\nstatic void update(T *bufferA, T scalar) {\n    //#pragma unroll\n    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){\n        // WRAM READ\n        T temp = bufferA[i];\n#ifdef ADD\n        temp += scalar; // ADD \n#elif SUB\n        temp -= scalar; // SUB\n#elif MUL\n        temp *= scalar; // MUL \n#elif DIV\n        temp /= scalar; // DIV\n#endif\n        // WRAM WRITE\n        bufferA[i] = temp;\n    }\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n    perfcounter_cycles cycles;\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n    T scalar = (T)input_size_dpu; // Simply use this number as a scalar\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n\n        // Update\n        update(cache_A, scalar);\n\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/host/app.c",
    "content": "/**\n* app.c\n* Arithmetic Throughput Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void update_host(T* C, T* A, unsigned int nr_elements) {\n    for (unsigned int i = 0; i < nr_elements; i++) {\n#if ADD\n        C[i] = A[i] + (nr_elements / NR_DPUS);\n#elif SUB\n        C[i] = A[i] - (nr_elements / NR_DPUS);\n#elif MUL\n        C[i] = A[i] * (nr_elements / NR_DPUS);\n#elif DIV\n        C[i] = A[i] / (nr_elements / NR_DPUS);\n#endif\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n    C2 = malloc(input_size * sizeof(T));\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        update_host(C2, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n#ifdef ADD\n    printf(\"ADD\\n\");\n#elif SUB\n    printf(\"SUB\\n\");\n#elif MUL\n    printf(\"MUL\\n\");\n#elif DIV\n    printf(\"DIV\\n\");\n#endif\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C2[i] != bufferB[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C2[i], bufferB[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/run.sh",
    "content": "#!/bin/bash\n\nfor i in ADD SUB MUL DIV\ndo\n\tfor j in INT32 FLOAT UINT32 INT64 DOUBLE UINT64\n\tdo \t\n\t\tfor k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 \n\t\tdo\n                    NR_DPUS=1 NR_TASKLETS=$k BL=10 OP=$i TYPE=$j make all\n                    wait\n                    ./bin/host_code -w 0 -e 1 -i 1048576 > profile/${i}_${j}_tl${k}.txt\n                    wait\n                    make clean\n                    wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#elif UINT64\n#define T uint64_t\n#elif INT32\n#define T int32_t\n#elif INT64\n#define T int64_t\n#elif FLOAT\n#define T float\n#elif DOUBLE\n#define T double\n#endif\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Arithmetic-Throughput/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nCPU_BASE_DIR := baselines/cpu\nGPU_BASE_DIR := baselines/gpu\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\nCPU_BASE_TARGET := ${BUILDDIR}/cpu_baseline\nGPU_BASE_TARGET := ${BUILDDIR}/gpu_baseline\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\nCPU_BASE_SOURCES := $(wildcard ${CPU_BASE_DIR}/*.c)\nGPU_BASE_SOURCES := $(wildcard ${GPU_BASE_DIR}/*.cu)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} \nCPU_BASE_FLAGS := -O3 -fopenmp\nGPU_BASE_FLAGS := -O3\n\nall: ${HOST_TARGET} ${DPU_TARGET} ${CPU_BASE_TARGET}\n\ngpu: ${GPU_BASE_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\n${CPU_BASE_TARGET}: ${CPU_BASE_SOURCES}\n\t$(CC) -o $@ ${CPU_BASE_SOURCES} ${CPU_BASE_FLAGS}\n\n${GPU_BASE_TARGET}: ${GPU_BASE_SOURCES}\n\tnvcc -o $@ ${GPU_BASE_SOURCES} ${GPU_BASE_FLAGS}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/cpu/Makefile",
    "content": "all:\n\t\tgcc -o bfs -fopenmp app.c \n\nclean:\n\t\trm bfs\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/cpu/README",
    "content": "Breadth-First Search (BFS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./bfs -f ../../data/loc-gowalla_edges.txt \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/cpu/app.c",
    "content": "\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdint.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/graph.h\"\n#include \"../../support/params.h\"\n#include \"../../support/timer.h\"\n#include \"../../support/utils.h\"\n\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Initialize BFS data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading graph %s\", p.fileName);\n    struct COOGraph cooGraph = readCOOGraph(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    Graph has %d nodes and %d edges\", cooGraph.numNodes, cooGraph.numEdges);\n    struct CSRGraph csrGraph = coo2csr(cooGraph);\n    uint32_t* nodeLevel = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* nodeLevelRef = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    for(uint32_t i = 0; i < csrGraph.numNodes; ++i) {\n        nodeLevel[i] = UINT32_MAX; // Unreachable\n        nodeLevelRef[i] = UINT32_MAX; // Unreachable\n    }\n    uint32_t srcNode = 0;\n\n    // Initialize frontier double buffers\n    uint32_t* buffer1 = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* buffer2 = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* prevFrontier = buffer1;\n    uint32_t* currFrontier = buffer2;\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU (OpenMP)\");\n    omp_set_num_threads(4);\n    Timer timer;\n    startTimer(&timer);\n    nodeLevel[srcNode] = 0;\n    prevFrontier[0] = srcNode;\n    uint32_t numPrevFrontier = 1;\n    for(uint32_t level = 1; numPrevFrontier > 0; ++level) {\n\n        uint32_t numCurrFrontier = 0;\n\n        // Visit nodes in the previous frontier\n        #pragma omp parallel for\n        for(uint32_t i = 0; i < numPrevFrontier; ++i) {\n            uint32_t node = prevFrontier[i];\n            for(uint32_t edge = csrGraph.nodePtrs[node]; edge < csrGraph.nodePtrs[node + 1]; ++edge) {\n                uint32_t neighbor = csrGraph.neighborIdxs[edge];\n                uint32_t justVisited = 0;\n                #pragma omp critical\n                {\n                    if(nodeLevel[neighbor] == UINT32_MAX) { // Node not previously visited\n                        nodeLevel[neighbor] = level;\n                        justVisited = 1;\n                    }\n                }\n                if(justVisited) {\n                    uint32_t currFrontierIdx;\n                    #pragma omp critical\n                    {\n                        currFrontierIdx = numCurrFrontier++;\n                    }\n                    currFrontier[currFrontierIdx] = neighbor;\n                }\n            }\n        }\n\n        // Swap buffers\n        uint32_t* tmp = prevFrontier;\n        prevFrontier = currFrontier;\n        currFrontier = tmp;\n        numPrevFrontier = numCurrFrontier;\n\n    }\n    stopTimer(&timer);\n    if(p.verbosity == 0) PRINT(\"%f\", getElapsedTime(timer)*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"Elapsed time: %f ms\", getElapsedTime(timer)*1e3);\n\n    // Calculating result on CPU sequentially\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU (sequential)\");\n    startTimer(&timer);\n    nodeLevelRef[srcNode] = 0;\n    prevFrontier[0] = srcNode;\n    numPrevFrontier = 1;\n    for(uint32_t level = 1; numPrevFrontier > 0; ++level) {\n\n        uint32_t numCurrFrontier = 0;\n\n        // Visit nodes in the previous frontier\n        for(uint32_t i = 0; i < numPrevFrontier; ++i) {\n            uint32_t node = prevFrontier[i];\n            for(uint32_t edge = csrGraph.nodePtrs[node]; edge < csrGraph.nodePtrs[node + 1]; ++edge) {\n                uint32_t neighbor = csrGraph.neighborIdxs[edge];\n                uint32_t justVisited = 0;\n                if(nodeLevelRef[neighbor] == UINT32_MAX) { // Node not previously visited\n                    nodeLevelRef[neighbor] = level;\n                    justVisited = 1;\n                }\n                if(justVisited) {\n                    uint32_t currFrontierIdx;\n                    currFrontierIdx = numCurrFrontier++;\n                    currFrontier[currFrontierIdx] = neighbor;\n                }\n            }\n        }\n\n        // Swap buffers\n        uint32_t* tmp = prevFrontier;\n        prevFrontier = currFrontier;\n        currFrontier = tmp;\n        numPrevFrontier = numCurrFrontier;\n\n    }\n    stopTimer(&timer);\n    if(p.verbosity == 0) PRINT(\"%f\", getElapsedTime(timer)*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"Elapsed time: %f ms\", getElapsedTime(timer)*1e3);\n\n    // Verifying result\n    PRINT_INFO(p.verbosity >= 1, \"Verifying the result\");\n    for(uint32_t nodeIdx = 0; nodeIdx < csrGraph.numNodes; ++nodeIdx) {\n        if(nodeLevel[nodeIdx] != nodeLevelRef[nodeIdx]) {\n            PRINT_ERROR(\"Mismatch at node %u (CPU sequential result = level %u, CPU parallel result = level %u)\", nodeIdx, nodeLevelRef[nodeIdx], nodeLevel[nodeIdx]);\n        }\n    }\n\n\n    // Deallocate data structures\n    freeCOOGraph(cooGraph);\n    freeCSRGraph(csrGraph);\n    free(nodeLevel);\n    free(buffer1);\n    free(buffer2);\n\n    return 0;\n\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app.cu -I/usr/local/cuda/include -lm -o bfs\n\nclean:\n\trm bfs\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/gpu/README",
    "content": "Breadth-First Search (BFS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./bfs -f ../../data/loc-gowalla_edges.txt \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/baselines/gpu/app.cu",
    "content": "\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdint.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/graph.h\"\n#include \"../../support/params.h\"\n#include \"../../support/timer.h\"\n#include \"../../support/utils.h\"\n\n__global__ void bfs_kernel(CSRGraph csrGraph, uint32_t* nodeLevel, uint32_t* prevFrontier, uint32_t* currFrontier, uint32_t numPrevFrontier, uint32_t* numCurrFrontier,  uint32_t level) {\n    uint32_t i = blockIdx.x*blockDim.x + threadIdx.x;\n    if(i < numPrevFrontier) {\n        uint32_t node = prevFrontier[i];\n        for(uint32_t edge = csrGraph.nodePtrs[node]; edge < csrGraph.nodePtrs[node + 1]; ++edge) {\n            uint32_t neighbor = csrGraph.neighborIdxs[edge];\n            if(atomicCAS(&nodeLevel[neighbor], UINT32_MAX, level) == UINT32_MAX) { // Node not previously visited\n                uint32_t currFrontierIdx = atomicAdd(numCurrFrontier, 1);\n                currFrontier[currFrontierIdx] = neighbor;\n            }\n        }\n    }\n}\n\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Initialize BFS data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading graph %s\", p.fileName);\n    struct COOGraph cooGraph = readCOOGraph(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    Graph has %d nodes and %d edges\", cooGraph.numNodes, cooGraph.numEdges);\n    struct CSRGraph csrGraph = coo2csr(cooGraph);\n    uint32_t* nodeLevel_cpu = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* nodeLevel_gpu = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    for(uint32_t i = 0; i < csrGraph.numNodes; ++i) {\n        nodeLevel_cpu[i] = UINT32_MAX; // Unreachable\n        nodeLevel_gpu[i] = UINT32_MAX; // Unreachable\n    }\n    uint32_t srcNode = 0;\n\n    // Allocate GPU memory\n    CSRGraph csrGraph_d;\n    csrGraph_d.numNodes = csrGraph.numNodes;\n    csrGraph_d.numEdges = csrGraph.numEdges;\n    cudaMalloc((void**) &csrGraph_d.nodePtrs, (csrGraph_d.numNodes + 1)*sizeof(uint32_t));\n    cudaMalloc((void**) &csrGraph_d.neighborIdxs, csrGraph_d.numEdges*sizeof(uint32_t));\n    uint32_t* nodeLevel_d;\n    cudaMalloc((void**) &nodeLevel_d, csrGraph_d.numNodes*sizeof(uint32_t));\n    uint32_t* buffer1_d;\n    cudaMalloc((void**) &buffer1_d, csrGraph_d.numNodes*sizeof(uint32_t));\n    uint32_t* buffer2_d;\n    cudaMalloc((void**) &buffer2_d, csrGraph_d.numNodes*sizeof(uint32_t));\n    uint32_t* numCurrFrontier_d;\n    cudaMalloc((void**) &numCurrFrontier_d, sizeof(uint32_t));\n    uint32_t* prevFrontier_d = buffer1_d;\n    uint32_t* currFrontier_d = buffer2_d;\n\n    // Copy data to GPU\n    cudaMemcpy(csrGraph_d.nodePtrs, csrGraph.nodePtrs, (csrGraph_d.numNodes + 1)*sizeof(uint32_t), cudaMemcpyHostToDevice);\n    cudaMemcpy(csrGraph_d.neighborIdxs, csrGraph.neighborIdxs, csrGraph_d.numEdges*sizeof(uint32_t), cudaMemcpyHostToDevice);\n    nodeLevel_gpu[srcNode] = 0;\n    cudaMemcpy(nodeLevel_d, nodeLevel_gpu, csrGraph_d.numNodes*sizeof(uint32_t), cudaMemcpyHostToDevice);\n    cudaMemcpy(prevFrontier_d, &srcNode, sizeof(uint32_t), cudaMemcpyHostToDevice);\n    cudaDeviceSynchronize();\n\n    // Calculating result on GPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on GPU\");\n    Timer timer;\n    startTimer(&timer);\n    uint32_t numPrevFrontier = 1;\n    uint32_t numThreadsPerBlock = 256;\n    for(uint32_t level = 1; numPrevFrontier > 0; ++level) {\n\n        // Visit nodes in previous frontier\n        cudaMemset(numCurrFrontier_d, 0, sizeof(uint32_t));\n        uint32_t numBlocks = (numPrevFrontier + numThreadsPerBlock - 1)/numThreadsPerBlock;\n        bfs_kernel <<< numBlocks, numThreadsPerBlock >>> (csrGraph_d, nodeLevel_d, prevFrontier_d, currFrontier_d, numPrevFrontier, numCurrFrontier_d, level);\n\n        // Swap buffers\n        uint32_t* tmp = prevFrontier_d;\n        prevFrontier_d = currFrontier_d;\n        currFrontier_d = tmp;\n        cudaMemcpy(&numPrevFrontier, numCurrFrontier_d, sizeof(uint32_t), cudaMemcpyDeviceToHost);\n\n    }\n    cudaDeviceSynchronize();\n    stopTimer(&timer);\n    if(p.verbosity == 0) PRINT(\"%f\", getElapsedTime(timer)*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"Elapsed time: %f ms\", getElapsedTime(timer)*1e3);\n\n    // Copy data from GPU\n    cudaMemcpy(nodeLevel_gpu, nodeLevel_d, csrGraph_d.numNodes*sizeof(uint32_t), cudaMemcpyDeviceToHost);\n    cudaDeviceSynchronize();\n\n    // Initialize frontier double buffers for CPU\n    uint32_t* buffer1 = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* buffer2 = (uint32_t*) malloc(csrGraph.numNodes*sizeof(uint32_t));\n    uint32_t* prevFrontier = buffer1;\n    uint32_t* currFrontier = buffer2;\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU\");\n    nodeLevel_cpu[srcNode] = 0;\n    prevFrontier[0] = srcNode;\n    numPrevFrontier = 1;\n    for(uint32_t level = 1; numPrevFrontier > 0; ++level) { \n\n        uint32_t numCurrFrontier = 0;\n\n        // Visit nodes in the previous frontier\n        for(uint32_t i = 0; i < numPrevFrontier; ++i) {\n            uint32_t node = prevFrontier[i];\n            for(uint32_t edge = csrGraph.nodePtrs[node]; edge < csrGraph.nodePtrs[node + 1]; ++edge) {\n                uint32_t neighbor = csrGraph.neighborIdxs[edge];\n                if(nodeLevel_cpu[neighbor] == UINT32_MAX) { // Node not previously visited\n                    nodeLevel_cpu[neighbor] = level;\n                    currFrontier[numCurrFrontier] = neighbor;\n                    ++numCurrFrontier;\n                }\n            }\n        }\n\n        // Swap buffers\n        uint32_t* tmp = prevFrontier;\n        prevFrontier = currFrontier;\n        currFrontier = tmp;\n        numPrevFrontier = numCurrFrontier;\n\n    }\n\n    // Verify result\n    PRINT_INFO(p.verbosity >= 1, \"Verifying the result\");\n    for(uint32_t i = 0; i < csrGraph.numNodes; ++i) {\n        if(nodeLevel_cpu[i] != nodeLevel_gpu[i]) {\n            printf(\"Mismatch detected at node %u (CPU result = %u, GPU result = %u)\\n\", i, nodeLevel_cpu[i], nodeLevel_gpu[i]);\n            exit(0);\n        }\n    }\n\n    // Deallocate data structures\n    freeCOOGraph(cooGraph);\n    freeCSRGraph(csrGraph);\n    free(nodeLevel_cpu);\n    free(nodeLevel_gpu);\n    free(buffer1);\n    free(buffer2);\n\n    return 0;\n\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/dpu/dpu-utils.h",
    "content": "\n#ifndef _DPU_UTILS_H_\n#define _DPU_UTILS_H_\n\n#include <mram.h>\n\n#define PRINT_ERROR(fmt, ...) printf(\"\\033[0;31mERROR:\\033[0m   \"fmt\"\\n\", ##__VA_ARGS__)\n\nstatic uint64_t load8B(uint32_t ptr_m, uint32_t idx, uint64_t* cache_w) {\n    mram_read((__mram_ptr void const*)(ptr_m + idx*sizeof(uint64_t)), cache_w, 8);\n    return cache_w[0];\n}\n\nstatic void store8B(uint64_t val, uint32_t ptr_m, uint32_t idx, uint64_t* cache_w) {\n    cache_w[0] = val;\n    mram_write(cache_w, (__mram_ptr void*)(ptr_m + idx*sizeof(uint64_t)), 8);\n}\n\nstatic uint32_t load4B(uint32_t ptr_m, uint32_t idx, uint64_t* cache_w) {\n    // Load 8B\n    uint32_t ptr_idx_m = ptr_m + idx*sizeof(uint32_t);\n    uint32_t offset = ((uint32_t)ptr_idx_m)%8;\n    uint32_t ptr_block_m = ptr_idx_m - offset;\n    mram_read((__mram_ptr void const*)ptr_block_m, cache_w, 8);\n    // Extract 4B\n    uint32_t* cache_32_w = (uint32_t*) cache_w;\n    return cache_32_w[offset/4];\n}\n\nstatic void store4B(uint32_t val, uint32_t ptr_m, uint32_t idx, uint64_t* cache_w) {\n    // Load 8B\n    uint32_t ptr_idx_m = ptr_m + idx*sizeof(uint32_t);\n    uint32_t offset = ((uint32_t)ptr_idx_m)%8;\n    uint32_t ptr_block_m = ptr_idx_m - offset;\n    mram_read((__mram_ptr void const*)ptr_block_m, cache_w, 8);\n    // Modify 4B\n    uint32_t* cache_32_w = (uint32_t*) cache_w;\n    cache_32_w[offset/4] = val;\n    // Write back 8B\n    mram_write(cache_w, (__mram_ptr void*)ptr_block_m, 8);\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/dpu/task.c",
    "content": "/*\n* BFS with multiple tasklets\n*\n*/\n#include <stdio.h>\n\n#include <alloc.h>\n#include <barrier.h>\n#include <defs.h>\n#include <mram.h>\n#include <mutex.h>\n#include <perfcounter.h>\n\n#include \"dpu-utils.h\"\n#include \"../support/common.h\"\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nBARRIER_INIT(bfsBarrier, NR_TASKLETS);\nMUTEX_INIT(nextFrontierMutex);\n\n// main\nint main() {\n\n    if(me() == 0) {\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Load parameters\n    uint32_t params_m = (uint32_t) DPU_MRAM_HEAP_POINTER;\n    struct DPUParams* params_w = (struct DPUParams*) mem_alloc(ROUND_UP_TO_MULTIPLE_OF_8(sizeof(struct DPUParams)));\n    mram_read((__mram_ptr void const*)params_m, params_w, ROUND_UP_TO_MULTIPLE_OF_8(sizeof(struct DPUParams)));\n\n    // Extract parameters\n    uint32_t numGlobalNodes = params_w->numNodes;\n    uint32_t startNodeIdx = params_w->dpuStartNodeIdx;\n    uint32_t numNodes = params_w->dpuNumNodes;\n    uint32_t nodePtrsOffset = params_w->dpuNodePtrsOffset;\n    uint32_t level = params_w->level;\n    uint32_t nodePtrs_m = params_w->dpuNodePtrs_m;\n    uint32_t neighborIdxs_m = params_w->dpuNeighborIdxs_m;\n    uint32_t nodeLevel_m = params_w->dpuNodeLevel_m;\n    uint32_t visited_m = params_w->dpuVisited_m;\n    uint32_t currentFrontier_m = params_w->dpuCurrentFrontier_m;\n    uint32_t nextFrontier_m = params_w->dpuNextFrontier_m;\n\n    if(numNodes > 0) {\n\n        // Sanity check\n        if(me() == 0) {\n            if(numGlobalNodes%64 != 0) {\n                //PRINT_ERROR(\"The number of nodes in the graph is not a multiple of 64!\");\n            }\n            if(startNodeIdx%64 != 0 || numNodes%64 != 0) {\n                //PRINT_ERROR(\"The number of nodes assigned to the DPU is not aligned to or a multiple of 64!\");\n            }\n        }\n\n        // Allocate WRAM cache for each tasklet to use throughout\n        uint64_t* cache_w = mem_alloc(sizeof(uint64_t));\n\n        // Update current frontier and visited list based on the next frontier from the previous iteration\n        for(uint32_t nodeTileIdx = me(); nodeTileIdx < numGlobalNodes/64; nodeTileIdx += NR_TASKLETS) {\n\n            // Get the next frontier tile from MRAM\n            uint64_t nextFrontierTile = load8B(nextFrontier_m, nodeTileIdx, cache_w);\n\n            // Process next frontier tile if it is not empty \n            if(nextFrontierTile) {\n\n                // Mark everything that was previously added to the next frontier as visited\n                uint64_t visitedTile = load8B(visited_m, nodeTileIdx, cache_w);\n                visitedTile |= nextFrontierTile;\n                store8B(visitedTile, visited_m, nodeTileIdx, cache_w);\n\n                // Clear the next frontier\n                store8B(0, nextFrontier_m, nodeTileIdx, cache_w);\n\n            }\n\n            // Extract the current frontier from the previous next frontier and update node levels\n            uint32_t startTileIdx = startNodeIdx/64;\n            uint32_t numTiles = numNodes/64;\n            if(startTileIdx <= nodeTileIdx && nodeTileIdx < startTileIdx + numTiles) {\n\n                // Update current frontier\n                store8B(nextFrontierTile, currentFrontier_m, nodeTileIdx - startTileIdx, cache_w);\n\n                // Update node levels\n                if(nextFrontierTile) {\n                    for(uint32_t node = nodeTileIdx*64; node < (nodeTileIdx + 1)*64; ++node) {\n                        if(isSet(nextFrontierTile, node%64)) {\n                            store4B(level, nodeLevel_m, node - startNodeIdx, cache_w); // No false sharing so no need for locks\n                        }\n                    }\n                }\n            }\n\n        }\n\n        // Wait until all tasklets have updated the current frontier\n        barrier_wait(&bfsBarrier);\n\n        // Identify tasklet's nodes\n        uint32_t numNodesPerTasklet = (numNodes + NR_TASKLETS - 1)/NR_TASKLETS;\n        uint32_t taskletNodesStart = me()*numNodesPerTasklet;\n        uint32_t taskletNumNodes;\n        if(taskletNodesStart > numNodes) {\n            taskletNumNodes = 0;\n        } else if(taskletNodesStart + numNodesPerTasklet > numNodes) {\n            taskletNumNodes = numNodes - taskletNodesStart;\n        } else {\n            taskletNumNodes = numNodesPerTasklet;\n        }\n\n        // Visit neighbors of the current frontier\n        mutex_id_t mutexID = MUTEX_GET(nextFrontierMutex);\n        for(uint32_t node = taskletNodesStart; node < taskletNodesStart + taskletNumNodes; ++node) {\n            uint32_t nodeTileIdx = node/64;\n            uint64_t currentFrontierTile = load8B(currentFrontier_m, nodeTileIdx, cache_w); // TODO: Optimize: load tile then loop over nodes in the tile\n            if(isSet(currentFrontierTile, node%64)) { // If the node is in the current frontier\n                // Visit its neighbors\n                uint32_t nodePtr = load4B(nodePtrs_m, node, cache_w) - nodePtrsOffset;\n                uint32_t nextNodePtr = load4B(nodePtrs_m, node + 1, cache_w) - nodePtrsOffset; // TODO: Optimize: might be in the same 8B as nodePtr\n                for(uint32_t i = nodePtr; i < nextNodePtr; ++i) {\n                    uint32_t neighbor = load4B(neighborIdxs_m, i, cache_w); // TODO: Optimize: sequential access to neighbors can use sequential reader\n                    uint32_t neighborTileIdx = neighbor/64;\n                    uint64_t visitedTile = load8B(visited_m, neighborTileIdx, cache_w);\n                    if(!isSet(visitedTile, neighbor%64)) { // Neighbor not previously visited\n                        // Add neighbor to next frontier\n                        mutex_lock(mutexID); // TODO: Optimize: use more locks to reduce contention\n                        uint64_t nextFrontierTile = load8B(nextFrontier_m, neighborTileIdx, cache_w);\n                        setBit(nextFrontierTile, neighbor%64);\n                        store8B(nextFrontierTile, nextFrontier_m, neighborTileIdx, cache_w);\n                        mutex_unlock(mutexID);\n                    }\n                }\n            }\n        }\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/host/app.c",
    "content": "/**\n* app.c\n* BFS Host Application Source File\n*\n*/\n#include <dpu.h>\n#include <dpu_log.h>\n\n#include <assert.h>\n#include <getopt.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n#include \"mram-management.h\"\n#include \"../support/common.h\"\n#include \"../support/graph.h\"\n#include \"../support/params.h\"\n#include \"../support/timer.h\"\n#include \"../support/utils.h\"\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#define DPU_BINARY \"./bin/dpu_code\"\n\n// Main of the Host Application\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Timer and profiling\n    Timer timer;\n    float loadTime = 0.0f, dpuTime = 0.0f, hostTime = 0.0f, retrieveTime = 0.0f;\n    #if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n    double tenergy=0;\n    #endif\n\n    // Allocate DPUs and load binary\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t numDPUs;\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &numDPUs));\n    PRINT_INFO(p.verbosity >= 1, \"Allocated %d DPU(s)\", numDPUs);\n\n    // Initialize BFS data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading graph %s\", p.fileName);\n    struct COOGraph cooGraph = readCOOGraph(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    Graph has %d nodes and %d edges\", cooGraph.numNodes, cooGraph.numEdges);\n    struct CSRGraph csrGraph = coo2csr(cooGraph);\n    uint32_t numNodes = csrGraph.numNodes;\n    uint32_t* nodePtrs = csrGraph.nodePtrs;\n    uint32_t* neighborIdxs = csrGraph.neighborIdxs;\n    uint32_t* nodeLevel = calloc(numNodes, sizeof(uint32_t)); // Node's BFS level (initially all 0 meaning not reachable)\n    uint64_t* visited = calloc(numNodes/64, sizeof(uint64_t)); // Bit vector with one bit per node\n    uint64_t* currentFrontier = calloc(numNodes/64, sizeof(uint64_t)); // Bit vector with one bit per node\n    uint64_t* nextFrontier = calloc(numNodes/64, sizeof(uint64_t)); // Bit vector with one bit per node\n    setBit(nextFrontier[0], 0); // Initialize frontier to first node\n    uint32_t level = 1;\n\n    // Partition data structure across DPUs\n    uint32_t numNodesPerDPU = ROUND_UP_TO_MULTIPLE_OF_64((numNodes - 1)/numDPUs + 1);\n    PRINT_INFO(p.verbosity >= 1, \"Assigning %u nodes per DPU\", numNodesPerDPU);\n    struct DPUParams dpuParams[numDPUs];\n    uint32_t dpuParams_m[numDPUs];\n    unsigned int dpuIdx = 0;\n    DPU_FOREACH (dpu_set, dpu) {\n\n        // Allocate parameters\n        struct mram_heap_allocator_t allocator;\n        init_allocator(&allocator);\n        dpuParams_m[dpuIdx] = mram_heap_alloc(&allocator, sizeof(struct DPUParams));\n\n        // Find DPU's nodes\n        uint32_t dpuStartNodeIdx = dpuIdx*numNodesPerDPU;\n        uint32_t dpuNumNodes;\n        if(dpuStartNodeIdx > numNodes) {\n            dpuNumNodes = 0;\n        } else if(dpuStartNodeIdx + numNodesPerDPU > numNodes) {\n            dpuNumNodes = numNodes - dpuStartNodeIdx;\n        } else {\n            dpuNumNodes = numNodesPerDPU;\n        }\n        dpuParams[dpuIdx].dpuNumNodes = dpuNumNodes;\n        PRINT_INFO(p.verbosity >= 2, \"    DPU %u:\", dpuIdx);\n        PRINT_INFO(p.verbosity >= 2, \"        Receives %u nodes\", dpuNumNodes);\n\n        // Partition edges and copy data\n        if(dpuNumNodes > 0) {\n\n            // Find DPU's CSR graph partition\n            uint32_t* dpuNodePtrs_h = &nodePtrs[dpuStartNodeIdx];\n            uint32_t dpuNodePtrsOffset = dpuNodePtrs_h[0];\n            uint32_t* dpuNeighborIdxs_h = neighborIdxs + dpuNodePtrsOffset;\n            uint32_t dpuNumNeighbors = dpuNodePtrs_h[dpuNumNodes] - dpuNodePtrsOffset;\n            uint32_t* dpuNodeLevel_h = &nodeLevel[dpuStartNodeIdx];\n\n            // Allocate MRAM\n            uint32_t dpuNodePtrs_m = mram_heap_alloc(&allocator, (dpuNumNodes + 1)*sizeof(uint32_t));\n            uint32_t dpuNeighborIdxs_m = mram_heap_alloc(&allocator, dpuNumNeighbors*sizeof(uint32_t));\n            uint32_t dpuNodeLevel_m = mram_heap_alloc(&allocator, dpuNumNodes*sizeof(uint32_t));\n            uint32_t dpuVisited_m = mram_heap_alloc(&allocator, numNodes/64*sizeof(uint64_t));\n            uint32_t dpuCurrentFrontier_m = mram_heap_alloc(&allocator, dpuNumNodes/64*sizeof(uint64_t));\n            uint32_t dpuNextFrontier_m = mram_heap_alloc(&allocator, numNodes/64*sizeof(uint64_t));\n            PRINT_INFO(p.verbosity >= 2, \"        Total memory allocated is %d bytes\", allocator.totalAllocated);\n\n            // Set up DPU parameters\n            dpuParams[dpuIdx].numNodes = numNodes;\n            dpuParams[dpuIdx].dpuStartNodeIdx = dpuStartNodeIdx;\n            dpuParams[dpuIdx].dpuNodePtrsOffset = dpuNodePtrsOffset;\n            dpuParams[dpuIdx].level = level;\n            dpuParams[dpuIdx].dpuNodePtrs_m = dpuNodePtrs_m;\n            dpuParams[dpuIdx].dpuNeighborIdxs_m = dpuNeighborIdxs_m;\n            dpuParams[dpuIdx].dpuNodeLevel_m = dpuNodeLevel_m;\n            dpuParams[dpuIdx].dpuVisited_m = dpuVisited_m;\n            dpuParams[dpuIdx].dpuCurrentFrontier_m = dpuCurrentFrontier_m;\n            dpuParams[dpuIdx].dpuNextFrontier_m = dpuNextFrontier_m;\n\n            // Send data to DPU\n            PRINT_INFO(p.verbosity >= 2, \"        Copying data to DPU\");\n            startTimer(&timer);\n            copyToDPU(dpu, (uint8_t*)dpuNodePtrs_h, dpuNodePtrs_m, (dpuNumNodes + 1)*sizeof(uint32_t));\n            copyToDPU(dpu, (uint8_t*)dpuNeighborIdxs_h, dpuNeighborIdxs_m, dpuNumNeighbors*sizeof(uint32_t));\n            copyToDPU(dpu, (uint8_t*)dpuNodeLevel_h, dpuNodeLevel_m, dpuNumNodes*sizeof(uint32_t));\n            copyToDPU(dpu, (uint8_t*)visited, dpuVisited_m, numNodes/64*sizeof(uint64_t));\n            copyToDPU(dpu, (uint8_t*)nextFrontier, dpuNextFrontier_m, numNodes/64*sizeof(uint64_t));\n            // NOTE: No need to copy current frontier because it is written before being read\n            stopTimer(&timer);\n            loadTime += getElapsedTime(timer);\n\n        }\n\n        // Send parameters to DPU\n        PRINT_INFO(p.verbosity >= 2, \"        Copying parameters to DPU\");\n        startTimer(&timer);\n        copyToDPU(dpu, (uint8_t*)&dpuParams[dpuIdx], dpuParams_m[dpuIdx], sizeof(struct DPUParams));\n        stopTimer(&timer);\n        loadTime += getElapsedTime(timer);\n\n        ++dpuIdx;\n\n    }\n    PRINT_INFO(p.verbosity >= 1, \"    CPU-DPU Time: %f ms\", loadTime*1e3);\n\n    // Iterate until next frontier is empty\n    uint32_t nextFrontierEmpty = 0;\n    while(!nextFrontierEmpty) {\n\n        PRINT_INFO(p.verbosity >= 1, \"Processing current frontier for level %u\", level);\n\n\t#if ENERGY\n\tDPU_ASSERT(dpu_probe_start(&probe));\n\t#endif\n        // Run all DPUs\n        PRINT_INFO(p.verbosity >= 1, \"    Booting DPUs\");\n        startTimer(&timer);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        stopTimer(&timer);\n        dpuTime += getElapsedTime(timer);\n        PRINT_INFO(p.verbosity >= 2, \"    Level DPU Time: %f ms\", getElapsedTime(timer)*1e3);\n\t#if ENERGY\n    \tDPU_ASSERT(dpu_probe_stop(&probe));\n    \tdouble energy;\n    \tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n\ttenergy += energy;\n\t#endif\n\n\n\n        // Copy back next frontier from all DPUs and compute their union as the current frontier\n        startTimer(&timer);\n        dpuIdx = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            uint32_t dpuNumNodes = dpuParams[dpuIdx].dpuNumNodes;\n            if(dpuNumNodes > 0) {\n                if(dpuIdx == 0) {\n                    copyFromDPU(dpu, dpuParams[dpuIdx].dpuNextFrontier_m, (uint8_t*)currentFrontier, numNodes/64*sizeof(uint64_t));\n                } else {\n                    copyFromDPU(dpu, dpuParams[dpuIdx].dpuNextFrontier_m, (uint8_t*)nextFrontier, numNodes/64*sizeof(uint64_t));\n                    for(uint32_t i = 0; i < numNodes/64; ++i) {\n                        currentFrontier[i] |= nextFrontier[i];\n                    }\n                }\n                ++dpuIdx;\n            }\n        }\n\n        // Check if the next frontier is empty, and copy data to DPU if not empty\n        nextFrontierEmpty = 1;\n        for(uint32_t i = 0; i < numNodes/64; ++i) {\n            if(currentFrontier[i]) {\n                nextFrontierEmpty = 0;\n                break;\n            }\n        }\n        if(!nextFrontierEmpty) {\n            ++level;\n            dpuIdx = 0;\n            DPU_FOREACH (dpu_set, dpu) {\n                uint32_t dpuNumNodes = dpuParams[dpuIdx].dpuNumNodes;\n                if(dpuNumNodes > 0) {\n                    // Copy current frontier to all DPUs (place in next frontier and DPU will update visited and copy to current frontier)\n                    copyToDPU(dpu, (uint8_t*)currentFrontier, dpuParams[dpuIdx].dpuNextFrontier_m, numNodes/64*sizeof(uint64_t));\n                    // Copy new level to DPU\n                    dpuParams[dpuIdx].level = level;\n                    copyToDPU(dpu, (uint8_t*)&dpuParams[dpuIdx], dpuParams_m[dpuIdx], sizeof(struct DPUParams));\n                    ++dpuIdx;\n                }\n            }\n        }\n        stopTimer(&timer);\n        hostTime += getElapsedTime(timer);\n        PRINT_INFO(p.verbosity >= 2, \"    Level Inter-DPU Time: %f ms\", getElapsedTime(timer)*1e3);\n\n    }\n    PRINT_INFO(p.verbosity >= 1, \"DPU Kernel Time: %f ms\", dpuTime*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"Inter-DPU Time: %f ms\", hostTime*1e3);\n    #if ENERGY\n    PRINT_INFO(p.verbosity >= 1, \"    DPU Energy: %f J\", tenergy);\n    #endif\n\n    // Copy back node levels\n    PRINT_INFO(p.verbosity >= 1, \"Copying back the result\");\n    startTimer(&timer);\n    dpuIdx = 0;\n    DPU_FOREACH (dpu_set, dpu) {\n        uint32_t dpuNumNodes = dpuParams[dpuIdx].dpuNumNodes;\n        if(dpuNumNodes > 0) {\n            uint32_t dpuStartNodeIdx = dpuIdx*numNodesPerDPU;\n            copyFromDPU(dpu, dpuParams[dpuIdx].dpuNodeLevel_m, (uint8_t*)(nodeLevel + dpuStartNodeIdx), dpuNumNodes*sizeof(float));\n        }\n        ++dpuIdx;\n    }\n    stopTimer(&timer);\n    retrieveTime += getElapsedTime(timer);\n    PRINT_INFO(p.verbosity >= 1, \"    DPU-CPU Time: %f ms\", retrieveTime*1e3);\n    if(p.verbosity == 0) PRINT(\"CPU-DPU Time(ms): %f    DPU Kernel Time (ms): %f    Inter-DPU Time (ms): %f    DPU-CPU Time (ms): %f\", loadTime*1e3, dpuTime*1e3, hostTime*1e3, retrieveTime*1e3);\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU\");\n    uint32_t* nodeLevelReference = calloc(numNodes, sizeof(uint32_t)); // Node's BFS level (initially all 0 meaning not reachable)\n    memset(nextFrontier, 0, numNodes/64*sizeof(uint64_t));\n    setBit(nextFrontier[0], 0); // Initialize frontier to first node\n    nextFrontierEmpty = 0;\n    level = 1;\n    while(!nextFrontierEmpty) {\n        // Update current frontier and visited list based on the next frontier from the previous iteration\n        for(uint32_t nodeTileIdx = 0; nodeTileIdx < numNodes/64; ++nodeTileIdx) {\n            uint64_t nextFrontierTile = nextFrontier[nodeTileIdx];\n            currentFrontier[nodeTileIdx] = nextFrontierTile;\n            if(nextFrontierTile) {\n                visited[nodeTileIdx] |= nextFrontierTile;\n                nextFrontier[nodeTileIdx] = 0;\n                for(uint32_t node = nodeTileIdx*64; node < (nodeTileIdx + 1)*64; ++node) {\n                    if(isSet(nextFrontierTile, node%64)) {\n                        nodeLevelReference[node] = level;\n                    }\n                }\n            }\n        }\n        // Visit neighbors of the current frontier\n        nextFrontierEmpty = 1;\n        for(uint32_t nodeTileIdx = 0; nodeTileIdx < numNodes/64; ++nodeTileIdx) {\n            uint64_t currentFrontierTile = currentFrontier[nodeTileIdx];\n            if(currentFrontierTile) {\n                for(uint32_t node = nodeTileIdx*64; node < (nodeTileIdx + 1)*64; ++node) {\n                    if(isSet(currentFrontierTile, node%64)) { // If the node is in the current frontier\n                        // Visit its neighbors\n                        uint32_t nodePtr = nodePtrs[node];\n                        uint32_t nextNodePtr = nodePtrs[node + 1];\n                        for(uint32_t i = nodePtr; i < nextNodePtr; ++i) {\n                            uint32_t neighbor = neighborIdxs[i];\n                            if(!isSet(visited[neighbor/64], neighbor%64)) { // Neighbor not previously visited\n                                // Add neighbor to next frontier\n                                setBit(nextFrontier[neighbor/64], neighbor%64);\n                                nextFrontierEmpty = 0;\n                            }\n                        }\n                    }\n                }\n            }\n        }\n        ++level;\n    }\n\n    // Verify the result\n    PRINT_INFO(p.verbosity >= 1, \"Verifying the result\");\n    for(uint32_t nodeIdx = 0; nodeIdx < numNodes; ++nodeIdx) {\n        if(nodeLevel[nodeIdx] != nodeLevelReference[nodeIdx]) {\n            PRINT_ERROR(\"Mismatch at node %u (CPU result = level %u, DPU result = level %u)\", nodeIdx, nodeLevelReference[nodeIdx], nodeLevel[nodeIdx]);\n        }\n    }\n\n    // Display DPU Logs\n    if(p.verbosity >= 2) {\n        PRINT_INFO(p.verbosity >= 2, \"Displaying DPU Logs:\");\n        dpuIdx = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            PRINT(\"DPU %u:\", dpuIdx);\n            DPU_ASSERT(dpu_log_read(dpu, stdout));\n            ++dpuIdx;\n        }\n    }\n\n    // Deallocate data structures\n    freeCOOGraph(cooGraph);\n    freeCSRGraph(csrGraph);\n    free(nodeLevel);\n    free(visited);\n    free(currentFrontier);\n    free(nextFrontier);\n    free(nodeLevelReference);\n\n    return 0;\n\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/host/mram-management.h",
    "content": "\n#ifndef _MRAM_MANAGEMENT_H_\n#define _MRAM_MANAGEMENT_H_\n\n#include \"../support/common.h\"\n#include \"../support/utils.h\"\n\n#define DPU_CAPACITY (64 << 20) // A DPU's capacity is 64 MiB\n\nstruct mram_heap_allocator_t {\n    uint32_t totalAllocated;\n};\n\nstatic void init_allocator(struct mram_heap_allocator_t* allocator) {\n    allocator->totalAllocated = 0;\n}\n\nstatic uint32_t mram_heap_alloc(struct mram_heap_allocator_t* allocator, uint32_t size) {\n    uint32_t ret = allocator->totalAllocated;\n    allocator->totalAllocated += ROUND_UP_TO_MULTIPLE_OF_8(size);\n    if(allocator->totalAllocated > DPU_CAPACITY) {\n        PRINT_ERROR(\"        Total memory allocated is %d bytes which exceeds the DPU capacity (%d bytes)!\", allocator->totalAllocated, DPU_CAPACITY);\n        exit(0);\n    }\n    return ret;\n}\n\nstatic void copyToDPU(struct dpu_set_t dpu, uint8_t* hostPtr, uint32_t mramIdx, uint32_t size) {\n    DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, mramIdx, hostPtr, ROUND_UP_TO_MULTIPLE_OF_8(size)));\n}\n\nstatic void copyFromDPU(struct dpu_set_t dpu, uint32_t mramIdx, uint8_t* hostPtr, uint32_t size) {\n    DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, mramIdx, hostPtr, ROUND_UP_TO_MULTIPLE_OF_8(size)));\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define ROUND_UP_TO_MULTIPLE_OF_2(x)    ((((x) + 1)/2)*2)\n#define ROUND_UP_TO_MULTIPLE_OF_8(x)    ((((x) + 7)/8)*8)\n#define ROUND_UP_TO_MULTIPLE_OF_64(x)   ((((x) + 63)/64)*64)\n\n#define setBit(val, idx) (val) |= (1 << (idx))\n#define isSet(val, idx)  ((val) & (1 << (idx)))\n\nstruct DPUParams {\n    uint32_t dpuNumNodes; /* The number of nodes assigned to this DPU */\n    uint32_t numNodes; /* Total number of nodes in the graph  */\n    uint32_t dpuStartNodeIdx; /* The index of the first node assigned to this DPU  */\n    uint32_t dpuNodePtrsOffset; /* Offset of the node pointers */\n    uint32_t level; /* The current BFS level */\n    uint32_t dpuNodePtrs_m;\n    uint32_t dpuNeighborIdxs_m;\n    uint32_t dpuNodeLevel_m;\n    uint32_t dpuVisited_m;\n    uint32_t dpuCurrentFrontier_m;\n    uint32_t dpuNextFrontier_m;\n};\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/support/graph.h",
    "content": "#ifndef _GRAPH_H_\n#define _GRAPH_H_\n\n#include <assert.h>\n#include <stdio.h>\n\n#include \"common.h\"\n#include \"utils.h\"\n\nstruct COOGraph {\n    uint32_t numNodes;\n    uint32_t numEdges;\n    uint32_t* nodeIdxs;\n    uint32_t* neighborIdxs;\n};\n\nstruct CSRGraph {\n    uint32_t numNodes;\n    uint32_t numEdges;\n    uint32_t* nodePtrs;\n    uint32_t* neighborIdxs;\n};\n\nstatic struct COOGraph readCOOGraph(const char* fileName) {\n\n    struct COOGraph cooGraph;\n\n    // Initialize fields\n    FILE* fp = fopen(fileName, \"r\");\n    uint32_t numNodes, numCols;\n    assert(fscanf(fp, \"%u\", &numNodes));\n    assert(fscanf(fp, \"%u\", &numCols));\n    if(numNodes == numCols) {\n        cooGraph.numNodes = numNodes;\n    } else {\n        PRINT_WARNING(\"    Adjacency matrix is not square. Padding matrix to be square.\");\n        cooGraph.numNodes = (numNodes > numCols)? numNodes : numCols;\n    }\n    if(cooGraph.numNodes%64 != 0) {\n        PRINT_WARNING(\"    Adjacency matrix dimension is %u which is not a multiple of 64 nodes.\", cooGraph.numNodes);\n        cooGraph.numNodes += (64 - cooGraph.numNodes%64);\n        PRINT_WARNING(\"        Padding to %u which is a multiple of 64 nodes.\", cooGraph.numNodes);\n    }\n    assert(fscanf(fp, \"%u\", &cooGraph.numEdges));\n    cooGraph.nodeIdxs = (uint32_t*) malloc(cooGraph.numEdges*sizeof(uint32_t));\n    cooGraph.neighborIdxs = (uint32_t*) malloc(cooGraph.numEdges*sizeof(uint32_t));\n\n    // Read the neighborIdxs\n    for(uint32_t edgeIdx = 0; edgeIdx < cooGraph.numEdges; ++edgeIdx) {\n        uint32_t nodeIdx;\n        assert(fscanf(fp, \"%u\", &nodeIdx));\n        cooGraph.nodeIdxs[edgeIdx] = nodeIdx;\n        uint32_t neighborIdx;\n        assert(fscanf(fp, \"%u\", &neighborIdx));\n        cooGraph.neighborIdxs[edgeIdx] = neighborIdx;\n    }\n\n    return cooGraph;\n\n}\n\nstatic void freeCOOGraph(struct COOGraph cooGraph) {\n    free(cooGraph.nodeIdxs);\n    free(cooGraph.neighborIdxs);\n}\n\nstatic struct CSRGraph coo2csr(struct COOGraph cooGraph) {\n\n    struct CSRGraph csrGraph;\n\n    // Initialize fields\n    csrGraph.numNodes = cooGraph.numNodes;\n    csrGraph.numEdges = cooGraph.numEdges;\n    csrGraph.nodePtrs = (uint32_t*) calloc(ROUND_UP_TO_MULTIPLE_OF_2(csrGraph.numNodes + 1), sizeof(uint32_t));\n    csrGraph.neighborIdxs = (uint32_t*)malloc(ROUND_UP_TO_MULTIPLE_OF_8(csrGraph.numEdges*sizeof(uint32_t)));\n\n    // Histogram nodeIdxs\n    for(uint32_t i = 0; i < cooGraph.numEdges; ++i) {\n        uint32_t nodeIdx = cooGraph.nodeIdxs[i];\n        csrGraph.nodePtrs[nodeIdx]++;\n    }\n\n    // Prefix sum nodePtrs\n    uint32_t sumBeforeNextNode = 0;\n    for(uint32_t nodeIdx = 0; nodeIdx < csrGraph.numNodes; ++nodeIdx) {\n        uint32_t sumBeforeNode = sumBeforeNextNode;\n        sumBeforeNextNode += csrGraph.nodePtrs[nodeIdx];\n        csrGraph.nodePtrs[nodeIdx] = sumBeforeNode;\n    }\n    csrGraph.nodePtrs[csrGraph.numNodes] = sumBeforeNextNode;\n\n    // Bin the neighborIdxs\n    for(uint32_t i = 0; i < cooGraph.numEdges; ++i) {\n        uint32_t nodeIdx = cooGraph.nodeIdxs[i];\n        uint32_t neighborListIdx = csrGraph.nodePtrs[nodeIdx]++;\n        csrGraph.neighborIdxs[neighborListIdx] = cooGraph.neighborIdxs[i];\n    }\n\n    // Restore nodePtrs\n    for(uint32_t nodeIdx = csrGraph.numNodes - 1; nodeIdx > 0; --nodeIdx) {\n        csrGraph.nodePtrs[nodeIdx] = csrGraph.nodePtrs[nodeIdx - 1];\n    }\n    csrGraph.nodePtrs[0] = 0;\n\n    return csrGraph;\n\n}\n\nstatic void freeCSRGraph(struct CSRGraph csrGraph) {\n    free(csrGraph.nodePtrs);\n    free(csrGraph.neighborIdxs);\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/support/params.h",
    "content": "\n#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n#include \"utils.h\"\n\nstatic void usage() {\n    PRINT(  \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -f <F>    input matrix file name (default=data/roadNet-CA.txt)\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -v <V>    verbosity\"\n            \"\\n    -h        help\"\n            \"\\n\\n\");\n}\n\ntypedef struct Params {\n  const char* fileName;\n  unsigned int verbosity;\n} Params;\n\nstatic struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.fileName      = \"data/roadNet-CA.txt\";\n    p.verbosity     = 1;\n    int opt;\n    while((opt = getopt(argc, argv, \"f:v:h\")) >= 0) {\n        switch(opt) {\n            case 'f': p.fileName    = optarg;       break;\n            case 'v': p.verbosity   = atoi(optarg); break;\n            case 'h': usage(); exit(0);\n            default:\n                      PRINT_ERROR(\"Unrecognized option!\");\n                      usage();\n                      exit(0);\n        }\n    }\n\n    return p;\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/support/timer.h",
    "content": "\n#ifndef _TIMER_H_\n#define _TIMER_H_\n\n#include <stdio.h>\n#include <sys/time.h>\n\ntypedef struct Timer {\n    struct timeval startTime;\n    struct timeval endTime;\n} Timer;\n\nstatic void startTimer(Timer* timer) {\n    gettimeofday(&(timer->startTime), NULL);\n}\n\nstatic void stopTimer(Timer* timer) {\n    gettimeofday(&(timer->endTime), NULL);\n}\n\nstatic float getElapsedTime(Timer timer) {\n    return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec)\n                   + (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BFS/support/utils.h",
    "content": "\n#ifndef _UTILS_H_\n#define _UTILS_H_\n\n#define PRINT_ERROR(fmt, ...)       fprintf(stderr, \"\\033[0;31mERROR:\\033[0m   \" fmt \"\\n\", ##__VA_ARGS__)\n#define PRINT_WARNING(fmt, ...)     fprintf(stderr, \"\\033[0;35mWARNING:\\033[0m \" fmt \"\\n\", ##__VA_ARGS__)\n#define PRINT_INFO(cond, fmt, ...)  if(cond) printf(\"\\033[0;32mINFO:\\033[0m    \" fmt \"\\n\", ##__VA_ARGS__);\n#define PRINT(fmt, ...)             printf(fmt \"\\n\", ##__VA_ARGS__)\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\nPROBLEM_SIZE ?= 2\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DPROBLEM_SIZE=${PROBLEM_SIZE}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -i 262144\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/cpu/Makefile",
    "content": "all:\n\tgcc bs_omp.c -o bs_omp -fopenmp\nrun:\n\t./bs_omp 262144 16777216\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/cpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./bs_omp 2048576 16777216\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/cpu/bs_omp.c",
    "content": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n#include <stdint.h>\n#include \"timer.h\"\n\n#define DTYPE uint64_t\n/*\n* @brief creates a \"test file\" by filling a bufferwith values\n*/\nvoid create_test_file(DTYPE * input, uint64_t  nr_elements, DTYPE * querys, uint64_t n_querys) {\n\n  uint64_t max = UINT64_MAX;\n  uint64_t min = 0;\n\n  srand(time(NULL));\n\n  input[0] = 1;\n  for (uint64_t i = 1; i < nr_elements; i++) {\n        input[i] = input[i - 1] + (rand() % 10) + 1;\n  }\n\n  for(uint64_t i = 0; i < n_querys; i++)\n  {\n\tquerys[i] = input[rand() % (nr_elements - 2)];\n  }\n}\n\n/**\n* @brief compute output in the host\n*/\nuint64_t binarySearch(DTYPE * input, uint64_t input_size, DTYPE* querys, unsigned n_querys)\n{\n\n\tuint64_t found = -1;\n\tuint64_t q, r, l, m;\n\t\n       #pragma omp parallel for private(q,r,l,m)\n     \tfor(q = 0; q < n_querys; q++)\n      \t{\n\t\tl = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) \n\t\t{\n\t    \t\tm = l + (r - l) / 2;\n\n\t    \t\t// Check if x is present at mid\n\t     \t\tif (input[m] == querys[q])\n\t\t\t{\t\n\t\t    \t\tfound += m;\n\t\t\t\tbreak;\n\t\t\t}\n\t    \t\t// If x greater, ignore left half\n\t    \t\tif (input[m] < querys[q])\n\t\t\t    \tl = m + 1;\n\n\t    \t\t// If x is smaller, ignore right half\n\t\t\telse\n\t\t    \t\tr = m - 1;\n\t\t\n\t\t}\n       \t}\n\n      \treturn found;\n}\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    Timer timer;\n    uint64_t input_size = atol(argv[1]);\n    uint64_t n_querys = atol(argv[2]);\n\n    printf(\"Vector size: %lu, num searches: %lu\\n\", input_size, n_querys);\n\t\n    DTYPE * input = malloc((input_size) * sizeof(DTYPE));\n    DTYPE * querys = malloc((n_querys) * sizeof(DTYPE));\n\n    DTYPE result_host = -1;\n\n    // Create an input file with arbitrary data.\n    create_test_file(input, input_size, querys, n_querys);\n\t\n    start(&timer, 0, 0);\n    result_host = binarySearch(input, input_size - 1, querys, n_querys);   \n    stop(&timer, 0);\n\n\n    int status = (result_host);\n    if (status) {\n        printf(\"[OK] Execution time: \");\n\tprint(&timer, 0, 1);\n\tprintf(\"ms.\\n\");\n    } else {\n        printf(\"[ERROR]\\n\");\n    }\n    free(input);\n\n\n    return status ? 0 : 1;\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/cpu/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/Makefile",
    "content": "all:\n\tnvcc -arch=sm_30 -m64 -Xcompiler -fPIC -shared -o cu_binary_search.so binary_search.cu -std=c++11\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/README",
    "content": "Binary Search (BS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    python3 run.py\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/binary_search.cu",
    "content": "#include <cuda.h>\r\n#include <limits.h>\r\n#include \"binary_search.h\"\r\n\r\n#include <chrono>\r\n#include <iostream>\r\n\r\n#define BLOCKDIM 512\r\n#define SEARCH_CHUNK 16\r\n#define BLOCK_CHUNK (BLOCKDIM*SEARCH_CHUNK)\r\n\r\n\r\n__global__ void search_kernel(const long int *arr,\r\n    const long int len, const long int *querys, const long int num_querys, long int *res, bool *flag)\r\n{\r\n    int search;\r\n    if(*flag == false) {\r\n        int tid = threadIdx.x;\r\n        __shared__ int s_arr[BLOCK_CHUNK];\r\n\r\n        /* Since each value is being copied to shared memory, the rest of the\r\n        following uncommented code is unncessary, since a direct comparison\r\n        can be done at the time of copy below. */\r\n        // for(int i = 0; i < BLOCKDIM; ++i) {\r\n        //     int shared_loc = i*SEARCH_CHUNK + tid;\r\n        //     int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n        //     if(arr[global_loc] == search) {\r\n        //         *flag = true;\r\n        //         *res = global_loc;\r\n        //     }\r\n        //     __syncthreads();\r\n        // }\r\n\r\n        /* Copy chunk of array that this entire block of threads will read\r\n        from the slower global memory to the faster shared memory. */\r\n        for(long int i = 0; i < SEARCH_CHUNK; ++i) {\r\n            int shared_loc = tid*SEARCH_CHUNK + i;\r\n            int global_loc = shared_loc + BLOCK_CHUNK * blockIdx.x;\r\n\r\n            /* Make sure to stay within the bounds of the global array,\r\n            else assign a dummy value. */\r\n            if(global_loc < len) {\r\n              s_arr[shared_loc] = arr[global_loc];\r\n            }\r\n            else {\r\n              s_arr[shared_loc] = INT_MAX;\r\n            }\r\n        }\r\n        __syncthreads();\r\n\r\n        for(long int i = 0; i < num_querys; i++)\r\n        {\r\n            search = querys[i];\r\n            /* For each runtime, set the initial search range. */\r\n            int L = 0;\r\n            int R = SEARCH_CHUNK - 1;\r\n            int m = (L + R) / 2;\r\n\r\n            /* Pointer to the part of the shared array for this runtime. */\r\n            int *s_ptr = &s_arr[tid*SEARCH_CHUNK];\r\n\r\n            /* Each runtime will search a chunk of the block array.\r\n            Many blocks will not find a solution so the search must\r\n            be allowed to fail on a per block basis. The loop will\r\n            break (fail) when L >= R. */\r\n            while(L <= R && *flag == false)\r\n            {\r\n                if(s_ptr[m] < search) {\r\n                    L = m + 1;\r\n                }\r\n                else if(s_ptr[m] > search) {\r\n                    R = m - 1;\r\n                }\r\n                else {\r\n                    *flag = true;\r\n                    *res = m += tid*SEARCH_CHUNK + BLOCK_CHUNK * blockIdx.x;\r\n                }\r\n\r\n                m = (L + R) / 2;\r\n            }\r\n        }\r\n    }\r\n}\r\n\r\n\r\n\r\nint binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys)\r\n{\r\n    long int *d_arr, *d_querys, *d_res;\r\n    bool *d_flag;\r\n\r\n    size_t arr_size = len * sizeof(long int);\r\n    size_t querys_size = num_querys * sizeof(long int);\r\n    size_t res_size = sizeof(long int);\r\n    size_t flag_size = sizeof(bool);\r\n\r\n    cudaMalloc(&d_arr, arr_size);\r\n    cudaMalloc(&d_querys, querys_size);\r\n    cudaMalloc(&d_res, res_size);\r\n    cudaMalloc(&d_flag, flag_size);\r\n\r\n    cudaMemcpy(d_arr, arr, arr_size, cudaMemcpyHostToDevice);\r\n    cudaMemcpy(d_querys, querys, querys_size, cudaMemcpyHostToDevice);\r\n    cudaMemset(d_flag, 0, flag_size);\r\n\r\n    /* Set res value to -1, so that if the function returns -1, that\r\n    indicates an algorithm failure. */\r\n    cudaMemset(d_res, -0x1, res_size);\r\n\r\n    int blockSize = BLOCKDIM;\r\n    int gridSize = (len-1)/BLOCK_CHUNK + 1;\r\n\r\n    auto start = std::chrono::high_resolution_clock::now();\r\n    search_kernel<<<gridSize,blockSize>>>(d_arr, len, d_querys, num_querys ,d_res, d_flag);\r\n    cudaDeviceSynchronize();\r\n    auto end = std::chrono::high_resolution_clock::now();\r\n    std::cout << \"Kernel Time: \" <<\r\n        std::chrono::duration_cast<std::chrono::milliseconds>(end-start).count() <<\r\n        \" ms\" << std::endl;\r\n\r\n    long int res;\r\n    cudaMemcpy(&res, d_res, res_size, cudaMemcpyDeviceToHost);\r\n\r\n    return res;\r\n}\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/binary_search.h",
    "content": "#ifndef BINARY_SEARCH_H\r\n#define BINARY_SEARCH_H\r\n\r\n#ifdef _WIN32\r\n  #include <windows.h>\r\n  #define DLL_EXPORT __declspec(dllexport)\r\n#else\r\n  #define DLL_EXPORT\r\n#endif\r\n\r\n\r\nextern \"C\" {\r\n\r\n    int DLL_EXPORT binary_search(const long int *arr, const long int len, const long int *querys, const long int num_querys);\r\n\r\n}\r\n\r\n#endif /* BINARY_SEARCH_H */\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/cpu_lib.py",
    "content": "# -*- coding: utf-8 -*-\n\n\ndef binary_search(arr, search):\n\n    L = 0\n    R = len(arr)\n\n    while L <= R:\n\n        if L > R:\n            return -1  # Error code 1\n\n        m = (L + R) / 2\n        if arr[m] < search:\n            L = m + 1\n        elif arr[m] > search:\n            R = m - 1\n        else:\n            return m\n\n    return -2  # Error code 2\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/cu_lib_import.py",
    "content": "# -*- coding: utf-8 -*-\r\n\r\n__all__ = [\r\n    \"binary_search\",\r\n]\r\n\r\n\r\nimport os.path as path\r\nimport platform\r\nfrom ctypes import *\r\n\r\nfrom numpy.ctypeslib import load_library, ndpointer\r\n\r\n## Load the DLL\r\nif platform.system() == \"Linux\":\r\n    cuda_lib = load_library(\"cu_binary_search.so\", path.dirname(path.realpath(__file__)))\r\nelif platform.system() == \"Windows\":\r\n    cuda_lib = load_library(\"cu_binary_search.dll\", path.dirname(path.realpath(__file__)))\r\n\r\n\r\n## Define argtypes for all functions to import\r\nargtype_defs = {\r\n    \"binary_search\": [ndpointer(\"i8\"), c_int, ndpointer(\"i8\"), c_int],\r\n}\r\n\r\n\r\n## Import functions from DLL\r\nfor func, argtypes in argtype_defs.items():\r\n    locals().update({func: cuda_lib[func]})\r\n    locals()[func].argtypes = argtypes\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/baselines/gpu/run.py",
    "content": "# -*- coding: utf-8 -*-\n\nimport time\n\nimport numpy as np\n\n# Local Imports\nfrom cu_lib_import import binary_search as gpu_search\n\n# Set an array label to create\narr_len = 2048576\nnum_querys = 16777216\n\n# Dummy array created\narr = np.arange(0, arr_len, 1).astype(\"i8\")\n\n# Random search querys created\nquerys = np.random.randint(1, arr_len, num_querys)\n\n# GPU search function call\nt0 = time.time()\nres_gpu = gpu_search(arr, len(arr), querys, len(querys))\nprint(\"Total GPU Time: %i ms\" % ((time.time() - t0) * 1e003))\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/dpu/task.c",
    "content": "/*\n* Binary Search with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include <perfcounter.h>\n#include \"common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Search\nDTYPE __attribute__ ((noinline)) search(DTYPE *bufferA, DTYPE searching_for) {\n  DTYPE found = -2;\n  if(bufferA[0] <= searching_for)\n  {\n    found = -1;\n    for (uint32_t i = 0; i < BLOCK_SIZE / sizeof(DTYPE); i++){\n      if(bufferA[i] == searching_for)\n      {\n        found = i;\n        break;\n      }\n    }\n  }\n  return found;\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n  // Kernel\n  return kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n  unsigned int tasklet_id = me();\n  #if PRINT\n  printf(\"tasklet_id = %u\\n\", tasklet_id);\n  #endif\n  if(tasklet_id == 0){\n    mem_reset(); // Reset the heap\n  }\n  // Barrier\n  barrier_wait(&my_barrier);\n\n  DTYPE searching_for, found;\n  uint64_t input_size = DPU_INPUT_ARGUMENTS.input_size;\n\n  // Address of the current processing block in MRAM\n  uint32_t start_mram_block_addr_A       = (uint32_t) DPU_MRAM_HEAP_POINTER;\n  uint32_t start_mram_block_addr_aux     = start_mram_block_addr_A;\n  uint32_t end_mram_block_addr_A         = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n  uint32_t current_mram_block_addr_query = end_mram_block_addr_A + tasklet_id * (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS) * sizeof(DTYPE);\n\n  // Initialize a local cache to store the MRAM block\n  DTYPE *cache_A     = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_A = (DTYPE *) mem_alloc(BLOCK_SIZE);\n  DTYPE *cache_aux_B = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n  dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n  // TODO(bongjoon.hyun@gmail.com): original PrIM benchmark uses uint64_t for targets' type\n  for(uint32_t targets = 0; targets < (DPU_INPUT_ARGUMENTS.slice_per_dpu / NR_TASKLETS); targets++)\n  {\n    found = -1;\n\n    mram_read((__mram_ptr void const *) current_mram_block_addr_query, &searching_for, 8);\n    current_mram_block_addr_query += 8;\n\n    bool end = false;\n\n    // Initialize input vector boundaries\n    start_mram_block_addr_A    = (uint32_t) DPU_MRAM_HEAP_POINTER;\n    start_mram_block_addr_aux  = start_mram_block_addr_A;\n    end_mram_block_addr_A      = start_mram_block_addr_A + sizeof(DTYPE) * input_size;\n\n    uint32_t current_mram_block_addr_A = start_mram_block_addr_A;\n\n    // Bring first and last values to WRAM\n    mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_aux_A, BLOCK_SIZE);\n    mram_read((__mram_ptr void const *) (end_mram_block_addr_A - BLOCK_SIZE * sizeof(DTYPE)),   cache_aux_B, BLOCK_SIZE);\n\n    current_mram_block_addr_A = (start_mram_block_addr_A + end_mram_block_addr_A) / 2;\n    while(!end)\n    {\n      // Load cache with current MRAM block\n      mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n\n      // Search inside block\n      found = search(cache_A, searching_for);\n\n      // If found > -1, we found the searching_for query\n      if(found > -1)\n      {\n        result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        break;\n      }\n\n      // If found == -2, we need to discard right part of the input vector\n      if(found == -2)\n      {\n        end_mram_block_addr_A     = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + start_mram_block_addr_A) / 2;\n      }\n\n      // If found == -1, we need to discard left part of the input vector\n      else if (found == -1)\n      {\n        start_mram_block_addr_A   = current_mram_block_addr_A;\n        current_mram_block_addr_A = (current_mram_block_addr_A + end_mram_block_addr_A) / 2;\n      }\n\n      // Start boundary check\n      if(current_mram_block_addr_A < (start_mram_block_addr_aux + BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) current_mram_block_addr_A, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          end = true;\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n\n      // End boundary check\n      if(current_mram_block_addr_A > (end_mram_block_addr_A - BLOCK_SIZE))\n      {\n        end = true;\n        mram_read((__mram_ptr void const *) end_mram_block_addr_A - BLOCK_SIZE, cache_A, BLOCK_SIZE);\n        found = search(cache_A, searching_for);\n\n        if(found > -1)\n        {\n          result->found = found + (current_mram_block_addr_A - start_mram_block_addr_aux) / sizeof(DTYPE);\n        }\n      }\n    }\n  }\n  return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/host/app.c",
    "content": "/**\n* app.c\n* BS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <time.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"params.h\"\n#include \"timer.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#define DPU_BINARY \"./bin/bs_dpu\"\n\n// Create input arrays\nvoid create_test_file(DTYPE * input, DTYPE * querys, uint64_t  nr_elements, uint64_t nr_querys) {\n\n\tinput[0] = 1;\n\tfor (uint64_t i = 1; i < nr_elements; i++) {\n\t\tinput[i] = input[i - 1] + 1;\n\t}\n\tfor (uint64_t i = 0; i < nr_querys; i++) {\n\t\tquerys[i] = i;\n\t}\n}\n\n// Compute output in the host\nint64_t binarySearch(DTYPE * input, DTYPE * querys, DTYPE input_size, uint64_t num_querys)\n{\n\tuint64_t result = -1;\n\tDTYPE r;\n\tfor(uint64_t q = 0; q < num_querys; q++)\n\t{\n\t\tDTYPE l = 0;\n\t\tr = input_size;\n\t\twhile (l <= r) {\n\t\t\tDTYPE m = l + (r - l) / 2;\n\n\t\t\t// Check if x is present at mid\n\t\t\tif (input[m] == querys[q])\n\t\t\tresult = m;\n\n\t\t\t// If x greater, ignore left half\n\t\t\tif (input[m] < querys[q])\n\t\t\tl = m + 1;\n\n\t\t\t// If x is smaller, ignore right half\n\t\t\telse\n\t\t\tr = m - 1;\n\t\t}\n\t}\n\treturn result;\n}\n\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\tuint64_t input_size = INPUT_SIZE;\n\tuint64_t num_querys = p.num_querys;\n\tDTYPE result_host = -1;\n\tDTYPE result_dpu  = -1;\n\n\t// Create the timer\n\tTimer timer;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n\t#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n\t#endif\n\n\t// Query number adjustement for proper partitioning\n\tif(num_querys % (nr_of_dpus * NR_TASKLETS))\n\tnum_querys = num_querys + (nr_of_dpus * NR_TASKLETS - num_querys % (nr_of_dpus * NR_TASKLETS));\n\n\tassert(num_querys % (nr_of_dpus * NR_TASKLETS) == 0 && \"Input dimension\");    // Allocate input and querys vectors\n\n\tDTYPE * input  = malloc((input_size) * sizeof(DTYPE));\n\tDTYPE * querys = malloc((num_querys) * sizeof(DTYPE));\n\n\t// Create an input file with arbitrary data\n\tcreate_test_file(input, querys, input_size, num_querys);\n\n\t// Compute host solution\n\tstart(&timer, 0, 0);\n\tresult_host = binarySearch(input, querys, input_size - 1, num_querys);\n\tstop(&timer, 0);\n\n\t// Create kernel arguments\n\tuint64_t slice_per_dpu          = num_querys / nr_of_dpus;\n\tdpu_arguments_t input_arguments = {input_size, slice_per_dpu, 0};\n\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\t\t// Perform input transfers\n\t\tuint64_t i = 0;\n\n\t\tif (rep >= p.n_warmup)\n\t\tstart(&timer, 1, rep - p.n_warmup);\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, querys + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size * sizeof(DTYPE), slice_per_dpu * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n\t\t\t#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n\t\t\t#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n\t\t\t#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n\t\t\t#endif\n\t\t}\n\t\t// Print logs if required\n\t\t#if PRINT\n\t\tunsigned int each_dpu = 0;\n\t\tprintf(\"Display DPU Logs\\n\");\n\t\tDPU_FOREACH(dpu_set, dpu)\n\t\t{\n\t\t\tprintf(\"DPU#%d:\\n\", each_dpu);\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t\teach_dpu++;\n\t\t}\n\t\t#endif\n\n\t\t// Retrieve results\n\t\tif (rep >= p.n_warmup)\n\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\tdpu_results_t* results_retrieve[nr_of_dpus];\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tresults_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tfor(unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++)\n\t\t\t{\n\t\t\t\tif(results_retrieve[i][each_tasklet].found > result_dpu)\n\t\t\t\t{\n\t\t\t\t\tresult_dpu = results_retrieve[i][each_tasklet].found;\n\t\t\t\t}\n\t\t\t}\n\t\t\tfree(results_retrieve[i]);\n\t\t}\n\t\tif(rep >= p.n_warmup)\n\t\tstop(&timer, 3);\n\t}\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, p.n_reps);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n\t#if ENERGY\n\tdouble energy;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n\tprintf(\"DPU Energy (J): %f\\t\", energy * num_iterations);\n\t#endif\n\n\tint status = (result_dpu == result_host);\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] results are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] results differ!\\n\");\n\t}\n\n\tfree(input);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n\treturn status ? 0 : 1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifdef TL\n#define TASKLETS_INITIALIZER TASKLETS(TL, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU TL\n#else\n#define TASKLETS_INITIALIZER TASKLETS(16, main, 2048, 2)\n#define NB_OF_TASKLETS_PER_DPU 16\n#endif\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int64_t\n\n// Vector size\n#define INPUT_SIZE 2048576\n\ntypedef struct {\n\tuint64_t input_size;\n\tuint64_t slice_per_dpu;\n\tenum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    DTYPE found;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n  long  num_querys;\n  unsigned   n_warmup;\n  unsigned   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    problem size (default=2 queries)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.num_querys    = PROBLEM_SIZE;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"h:i:w:e:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.num_querys    = atol(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break; \n\tdefault:\n        \tfprintf(stderr, \"\\nUnrecognized option!\\n\");\n        \tusage();\n        \texit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n  #endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/BS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nTRANSFER ?= PUSH\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TRANSFER_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TRANSFER})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TRANSFER}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TRANSFER}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/dpu/task.c",
    "content": "/*\n* Empty kernel with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n#if PRINT\n    unsigned int tasklet_id = me();\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/host/app.c",
    "content": "/**\n* app.c\n* CPU-DPU Communication Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, \"nrThreadPerPool=8\", &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    C = malloc(input_size * sizeof(T));\n    C2 = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C;\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        printf(\"Load input data\\n\");\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        // Copy input arrays\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        i = 0;\n#ifdef SERIAL\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n#elif BROADCAST\n        DPU_ASSERT(dpu_broadcast_to(dpu_set, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n#else\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n#endif\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        //DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        i = 0;\n#ifdef SERIAL\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferC + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n#else\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n#endif\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    double time_load = timer.time[1] / (1000 * p.n_reps);\n    printf(\"CPU-DPU Bandwidth (GB/s): %f\\n\", (input_size * 8)/(time_load*1e6));\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"\\n\");\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n    double time_retrieve = timer.time[3] / (1000 * p.n_reps);\n    printf(\"DPU-CPU Bandwidth (GB/s): %f\\n\", (input_size * 8)/(time_retrieve*1e6));\n\n    // Check output\n    bool status = true;\n#ifdef BROADCAST\n    for (i = 0; i < input_size/nr_of_dpus; i++) {\n        if(B[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, B[i], bufferA[i]);\n#endif\n        }\n    }\n#else\n    for (i = 0; i < input_size; i++) {\n        if(B[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, B[i], bufferA[i]);\n#endif\n        }\n    }\n#endif\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 2 4 8 16 32 64 \ndo\n\tfor j in 1 \n\tdo \t\n\t\tfor k in SERIAL PUSH BROADCAST\n\t\tdo\n\t\t\tfor l in 1 4 16 64 256 1024 4096 16384 65536 262144 1048576 4194304 \n\t\t\tdo\n\t\t\t\tNR_DPUS=$i NR_TASKLETS=$j BL=10 TRANSFER=$k make all\n\t\t\t\twait\n\t\t\t\t./bin/host_code -w 5 -e 20 -i ${l} >& profile/${i}_tl${j}_TR${k}_i${l}.txt\n\t\t\t\twait\n\t\t\t\tmake clean\n\t\t\t\twait\n\t\t\tdone\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/CPU-DPU/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/cpu/Makefile",
    "content": "all:\n\t\tgcc -o gemv -fopenmp gemv_openmp.c \n\nclean:\n\t\trm gemv\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/cpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/cpu/gemv_openmp.c",
    "content": "#include <stdlib.h>\n#include <stdio.h>\n#include \"../../support/timer.h\"\n#include \"gemv_utils.h\"\n\nint main(int argc, char *argv[])\n{\n  const size_t rows = 20480;\n  const size_t cols = 8192;\n\n  double **A, *b, *x;\n\n  b = (double*) malloc(sizeof(double)*rows);\n  x = (double*) malloc(sizeof(double)*cols);\n\n  allocate_dense(rows, cols, &A);\n\n  make_hilbert_mat(rows,cols, &A);\n\n#pragma omp parallel\n    {\n#pragma omp for\n    for (size_t i = 0; i < cols; i++) {\n      x[i] = (double) i+1 ;\n    }\n\n#pragma omp for\n    for (size_t i = 0; i < rows; i++) {\n      b[i] = (double) 0.0;\n    }\n    }\n\n  Timer timer;\n  start(&timer, 0, 0);\n\n\n   gemv(A, x, rows, cols, &b);\n   \n   stop(&timer, 0);\n\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n#if 0\n  print_vec(x, rows);\n  print_mat(A, rows, cols);\n  print_vec(b, rows);\n#endif\n\n  printf(\"sum(x) = %f, sum(Ax) = %f\\n\", sum_vec(x,cols), sum_vec(b,rows));\n  return 0;\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i ++ )\n  for (size_t j = 0; j < cols; j ++ ) {\n    (*b)[i] = (*b)[i] + A[i][j]*x[j];\n  }\n}\n\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A) {\n#pragma omp parallel for\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      (*A)[i][j] = 1.0/( (double) i + (double) j + 1.0);\n    }\n  }\n}\n\ndouble sum_vec(double* vec, size_t rows) {\n  double sum = 0.0;\n#pragma omp parallel for reduction(+:sum)\n  for (int i = 0; i < rows; i++) sum = sum + vec[i];\n  return sum;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/cpu/gemv_utils.h",
    "content": "void allocate_dense(size_t rows,size_t  cols, double*** dense) {\n\n  *dense = malloc(sizeof(double)*rows);\n  **dense = malloc(sizeof(double)*rows*cols);\n\n  for (size_t i=0; i < rows; i++ ) {\n    (*dense)[i] = (*dense)[0] + i*cols;\n  }\n\n}\n\nvoid print_mat(double** A, size_t rows, size_t cols) {\n  for (size_t i = 0; i < rows; i++) {\n    for (size_t j = 0; j < cols; j++) {\n      printf(\"%f \", A[i][j]);\n    }\n    printf(\"\\n\");\n  }\n}\n\nvoid print_vec(double* b, size_t rows) {\n  for (size_t i = 0; i < rows; i++) {\n    printf(\"%f\\n\", b[i]);\n  }\n}\n\nvoid gemv(double** A, double* x, size_t rows, size_t cols, double** b);\nvoid make_hilbert_mat(size_t rows, size_t cols, double*** A);\ndouble sum_vec(double* vec, size_t rows);\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc gemv.cu -I/usr/local/cuda/include -lm -o gemv\n\nclean:\n\trm gemv\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/gpu/README",
    "content": "Matrix-Vector Multiplication (GEMV)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./gemv\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/baselines/gpu/gemv.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n\n#define THREAD 128\n\n#define T int\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\nstruct timeval tv;\ngettimeofday(&tv, NULL);\nreturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n/* for CPU */\nint i, j;\nint *bdim, *c, *ans, *h_ans;\n//double start, stop;\n//double cpu_time, gpu_time;\nint n = 8192;\nint m = 20480;\n\nbdim = (T*)malloc(sizeof(T) *m*n);\nc = (T*)malloc(sizeof(T) *n);\nans = (T*)malloc(sizeof(T) *m);\nh_ans = (T*)malloc(sizeof(T) *m);\n\n/* for GPU */\nT *d_bdim, *d_c, *d_ans;\ncudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\ncudaMalloc((void **)&d_c, sizeof(T)*n);\ncudaMalloc((void **)&d_ans, sizeof(T)*m);\n\nfor(i = 0; i < n; i++)\n{\nc[i] = 1;\nfor(j = 0; j < m; j++)\nbdim[i*m+j] = 1;\n}\n\n//start = gettime();\ncgemv(m, n, bdim, c, ans);\n//stop = gettime();\n//cpu_time=stop - start;\n\n// Event creation\ncudaEvent_t start, stop;\ncudaEventCreate(&start);\ncudaEventCreate(&stop);\nfloat time1 = 0;\n\n\ncudaMemcpy(d_bdim, bdim, sizeof(T)*m*n, cudaMemcpyHostToDevice);\ncudaMemcpy(d_c, c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n// Start timer\ncudaEventRecord( start, 0 );\n//start = gettime();\ngemv<<<m, THREAD>>>(m, n, d_bdim, d_c, d_ans);\n//stop = gettime();\n// End timer\ncudaEventRecord( stop, 0 );\ncudaEventSynchronize( stop );\ncudaEventElapsedTime( &time1, start, stop );\n\n//gpu_time=stop - start;\n\ncudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\n//printf(\"cpu_time : %.6f[sec]\\n\",cpu_time);\n//printf(\"gpu_time : %.6f[sec]\\n\",gpu_time);\n//printf(\"%f x\\n\", cpu_time / gpu_time);\n\n\nfor(i = 0; i < m; i++)\nprintf(\"%d -- %d\\n\", ans[i], h_ans[i]);\n\nprintf(\"Execution time = %f ms\\n\", time1);\n\n\nfree(bdim);\nfree(c);\nfree(ans);\nfree(h_ans);\ncudaFree(d_bdim);\ncudaFree(d_c);\ncudaFree(d_ans);\n\nreturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\nint i;\nint div = n/THREAD;\n__shared__ T tmp[THREAD];\n\ntmp[threadIdx.x] = 0.0;\n\nfor(i = 0; i < div; i++)\n{\ntmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n}\nif(threadIdx.x < m%THREAD)\ntmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n__syncthreads();\n\nfor(i = THREAD / 2; i > 31; i = i / 2)\n{\nif(threadIdx.x < i)\ntmp[threadIdx.x] += tmp[threadIdx.x + i];\n__syncthreads();\n}\n\nif(threadIdx.x < 16)\n{\ntmp[threadIdx.x] += tmp[threadIdx.x + 16];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 8];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 4];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 2];\n__syncthreads();\ntmp[threadIdx.x] += tmp[threadIdx.x + 1];\n__syncthreads();\n}\n\n\nif(threadIdx.x == 0)\nd_ans[blockIdx.x] = tmp[0];\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\nint i, j;\n\nfor(i = 0; i < m; i++)\nfor(j = 0; j < n; j++)\nd_ans[i] += adim[i*n+j] * b[j];\n\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/host/app.c",
    "content": "/**\n * app.c\n * GEMV Host Application Source File\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/gemv_dpu\"\n#endif\n\nstatic T* A;\nstatic T* B;\nstatic T* C;\nstatic T* C_dpu;\n\n// Create input arrays\nstatic void init_data(T* A, T* B, unsigned int m_size, unsigned int n_size) {\n\tsrand(0);\n\n\tfor (unsigned int i = 0; i < m_size * n_size; i++)\n\t{\n\t\tA[i] = (unsigned int) (rand()%50);\n\t}\n\n\tfor (unsigned int i = 0; i < n_size; i++)\n\t{\n\t\tB[i] = (unsigned int) (rand()%50);\n\t}\n}\n\n// Compute output in the host\nstatic void gemv_host(T* C, T* A, T* B, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int i = 0; i < m_size; i++)\n\t{\n\t\tC[i] = 0;\n\t}\n\n\tfor (unsigned int m = 0; m < m_size; m++) {\n\t\tfor (unsigned int n = 0; n < n_size; n++)\n\t\t{\n\t\t\tC[m] += A[m * n_size + n] * B[n];\n\t\t}\n\t}\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned int i;\n\tunsigned int m_size = p.m_size;\n\tunsigned int n_size = p.n_size;\n\n\t// Initialize help data\n\tdpu_info = (struct dpu_info_t *) malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tdpu_arguments_t *input_args = (dpu_arguments_t *) malloc(nr_of_dpus * sizeof(dpu_arguments_t));\n\tuint32_t max_rows_per_dpu = 0;\n\tuint32_t n_size_pad = n_size;\n\tif(n_size % 2 == 1)\n\t{\n\t\tn_size_pad++;\n\t}\n\n\ti = 0;\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tuint32_t rows_per_dpu;\n\t\tuint32_t prev_rows_dpu = 0;\n\t\tuint32_t chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tuint32_t rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows)\n\t\t\trows_per_dpu++;\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows)\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\telse\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\t// Keep max rows for parallel transfers\n\t\tuint32_t rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) // 4-byte elements\n\t\t\trows_per_dpu_pad++;\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu)\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\t// Copy input arguments to DPU\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = malloc(max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(T));\n\tB = malloc(n_size_pad * sizeof(T));\n\tC = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\n\t// Initialize data with arbitrary data\n\tinit_data(A, B, m_size, n_size);\n\n\t// Timer\n\tTimer timer;\n\n\t// Compute output on CPU (performance comparison and verification purposes)\n\tstart(&timer, 0, 0);\n\tgemv_host(C, A, B, m_size, n_size);\n\tstop(&timer, 0);\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\t// Input arguments\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t// Copy input arguments to DPU\n\t\t\tinput_args[i].max_rows = max_rows_per_dpu;\n\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n\t\t// Copy input array and vector\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A + dpu_info[i].prev_rows_dpu * n_size));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n#if PRINT\n\t\t// Display DPU Logs\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t}\n#endif\n\n\t\t// Retrieve results\n\t\tC_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\t}\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, 1);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\n\t// Check output\n\tbool status = true;\n\tunsigned int n,j;\n\ti = 0;\n\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = false;\n#if PRINT\n\t//\t\t\tprintf(\"%d: %d -- %d\\n\", i, C[i], C_dpu[n * max_rows_per_dpu + j]);\n#endif\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n\t}\n\n\t// Deallocation\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n    uint32_t rows_per_dpu;\n    uint32_t rows_per_dpu_pad;\n    uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=8192 elements)\"\n            \"\\n    -n <I>    n_size (default=8192 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 8192;\n    p.n_size        = 8192;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/GEMV/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nNR_HISTO ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_NR_DPUS_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${NR_DPUS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DNR_HISTO=${NR_HISTO} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/dpu/task.c",
    "content": "/*\n* Histogram (HST-L) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n#include <atomic_bit.h>\n#include <mutex.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\nATOMIC_BIT_INIT(barriers_mutexes)[NR_HISTO];\nbarrier_t barriers[NR_HISTO];\n\n// Mutex\nmutex_id_t my_mutex[NR_HISTO];\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, uint32_t histo_id, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = (input[j] * bins) >> DEPTH;\n        mutex_lock(my_mutex[histo_id]);\n        histo[d] += 1;\n        mutex_unlock(my_mutex[histo_id]);\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    unsigned int l_tasklet_id = tasklet_id / NR_HISTO;\n    unsigned int nr_l_tasklet = NR_TASKLETS / NR_HISTO;\n    unsigned int my_histo_id = tasklet_id & (NR_HISTO - 1);\n\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n        // Initialize barriers\n        for (unsigned int each_barrier = 0; each_barrier < NR_HISTO; each_barrier++) {\n            barriers[each_barrier].wait_queue = 0xff;\n            barriers[each_barrier].count = nr_l_tasklet;\n            barriers[each_barrier].initial_count = nr_l_tasklet;\n            barriers[each_barrier].lock = (uint8_t) &ATOMIC_BIT_GET(barriers_mutexes)[each_barrier];\n        }\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    if (tasklet_id < NR_HISTO){ // Allocate DPU histogram\n        uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n        message[tasklet_id] = histo;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    uint32_t *my_histo = message[my_histo_id];\n\n    // Initialize local histogram\n    for(unsigned int i = l_tasklet_id; i < bins; i += nr_l_tasklet){\n        my_histo[i] = 0;\n    }\n    // Barrier\n    barrier_wait(&barriers[my_histo_id]);\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(my_histo, bins, cache_A, my_histo_id, l_size_bytes >> DIV);\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\n        for (unsigned int j = 0; j < NR_HISTO; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n    \t        mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/host/app.c",
    "content": "/**\n* app.c\n* HST-L Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\nstatic unsigned int* histo;\n\n// Create input arrays\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Compute output in the host\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus) {\n    if(!exp){\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    unsigned int input_size; // Size of input image\n    unsigned int dpu_s = p.dpu_s;\n    if(p.exp == 0)\n        input_size = p.input_size * nr_of_dpus; // Size of input image\n    else if(p.exp == 1)\n        input_size = p.input_size; // Size of input image\n\telse\n        input_size = p.input_size * dpu_s; // Size of input image\n\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    histo_host = malloc(p.bins * sizeof(unsigned int));\n    histo = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data\n    read_input(A, p);\n    if(p.exp == 0){\n        for(unsigned int j = 1; j < nr_of_dpus; j++){\n            memcpy(&A[j * input_size_dpu_8bytes], &A[0], input_size_dpu_8bytes * sizeof(T));\n        }\n    }\n    else if(p.exp == 2){\n        for(unsigned int j = 1; j < dpu_s; j++)\n            memcpy(&A[j * p.input_size], &A[0], p.input_size * sizeof(T));\n    }\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\tinput_size\\t%u\\n\", NR_TASKLETS, BL, input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n        memset(histo_host, 0, p.bins * sizeof(unsigned int));\n        memset(histo, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        histogram_host(histo_host, A, p.bins, p.input_size, 1, nr_of_dpus);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        i = 0;\n\t    dpu_arguments_t input_arguments[NR_DPUS];\n\t    for(i=0; i<nr_of_dpus-1; i++) {\n\t        input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].bins=p.bins;\n\t        input_arguments[i].kernel=kernel;\n\t    }\n\t    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].bins=p.bins;\n\t    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, histo + p.bins * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), p.bins * sizeof(unsigned int), DPU_XFER_DEFAULT));\n\t\t\n        // Final histogram merging\n        for(i = 1; i < nr_of_dpus; i++){\n            for(unsigned int j = 0; j < p.bins; j++){\n                histo[j] += histo[j + i * p.bins];\n            }\t\t\t\n        }\t\t\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    if(p.exp == 1) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else if(p.exp == 2) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(dpu_s * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, dpu_s * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else\n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(nr_of_dpus * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, nr_of_dpus * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(histo_host);\n    free(histo);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n\t        NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n\t\t    wait\n            ./bin/host_code -w 2 -e 5 -b ${b} > profile/HSTL_${b}_tl${k}_dpu${i}.txt\n\t\t    wait\n\t\t    make clean\n\t\t    wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-L/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o hist -fopenmp app_baseline.c \n\nclean:\n\trm hist\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/cpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hist -y 1006632960 -t 4\n\nFor more options:\n\n    ./hsti -h\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/cpu/app_baseline.c",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n* The macros DPU_BINARY and NR_TASKLETS are directly\n* used in the static functions, and are not passed as arguments of these functions.\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  n_threads;\n}Params;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus, int t) {\n\n    omp_set_num_threads(t);\n\n    if(!exp){\n        #pragma omp parallel for\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        #pragma omp parallel for\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            #pragma omp atomic update\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Params ---------------------------------------------------------------------\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n    p.exp           = 1;\n    p.file_name     = \"../../input/image_VanHateren.iml\";\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    uint32_t nr_of_dpus;\n    \n    const unsigned int input_size = p.input_size; // Size of input image\n    if(!p.exp)\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n    else\n        assert(input_size % p.n_threads == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    if(!p.exp)\n        histo_host = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n        histo_host = malloc(p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    read_input(A, p);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n\tif(!p.exp)\n            memset(histo_host, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n    else\n            memset(histo_host, 0, p.bins * sizeof(unsigned int));\n\n    histogram_host(histo_host, A, p.bins, input_size, p.exp, nr_of_dpus, p.n_threads);\n\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L/usr/local/cuda/lib64 -lm\n\nINC=-I/usr/local/cuda/include\n\nDEP=kernel.cpp kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/partitioner.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cpp kernel.cu\nEXE=hsti\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/README",
    "content": "Histogram - input partition (HST)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./hsti -n 1006632960 -g 512\n\nFor more options:\n\n    ./hsti -h\n\n\nNote:\nThe input folder contains one image from Van Hateren's natural image database \n(http://www.kyb.tuebingen.mpg.de/?id=227). Image pixels are 12-bit depth. Thus, \nfor calculation of the B-bin histogram of an image, the corresponding histogram \nbin is computed as ((pixel * B) >> 12).\nMonochrome images from other databases or synthetic images can also be used. The \nread input function (in main.cpp) might need to be changed accordingly. If image \npixels are b-bit depth and the histogram contains B bins, the histogram bin will \nbe computed as ((pixel * B) >> b).\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include \"support/partitioner.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads--------------------------------------------------------------------------------------\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int n_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *worklist\n#endif\n    ) {\n    std::vector<std::thread> cpu_threads;\n    for(int k = 0; k < n_threads; k++) {\n        cpu_threads.push_back(std::thread([=]() {\n\n#ifdef CUDA_8_0\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads, worklist);\n#else\n            Partitioner p = partitioner_create(n_tasks, alpha, k, n_threads);\n#endif\n\n            unsigned int Hs[bins];\n            // Local histogram initialization\n            for(int i = 0; i < bins; i++) {\n                Hs[i] = 0;\n            }\n\n            for(int i = cpu_first(&p); cpu_more(&p); i = cpu_next(&p)) {\n                for(int j = 0; j < chunk; j++) {\n                    // Read pixel\n                    unsigned int d = ((data[i * chunk + j] * bins) >> 12);\n\n                    // Vote in histogram\n                    Hs[d]++;\n                }\n            }\n\n            // Merge to global histogram\n            for(int i = 0; i < bins; i++) {\n                (&histo[i])->fetch_add(Hs[i]);\n            }\n\n        }));\n    }\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#define _CUDA_COMPILER_\n\n#include \"support/common.h\"\n#include \"support/partitioner.h\"\n\n// CUDA kernel ------------------------------------------------------------------------------------------\n__global__ void Histogram_kernel(int size, int bins, int n_tasks, float alpha, unsigned int *data,\n    unsigned int *histo\n#ifdef CUDA_8_0\n    , int *worklist\n#endif\n    ) {\n\n    extern __shared__ unsigned int l_mem[];\n    unsigned int* l_histo = l_mem;\n#ifdef CUDA_8_0\n    int* l_tmp = (int*)&l_histo[bins];\n#endif\n    \n#ifdef CUDA_8_0\n    Partitioner p = partitioner_create(n_tasks, alpha, worklist, l_tmp);\n#else\n    Partitioner p = partitioner_create(n_tasks, alpha);\n#endif\n    \n    // Block and runtime index\n    const int bx = blockIdx.x;\n    const int tx = threadIdx.x;\n    const int bD = blockDim.x;\n    const int gD = gridDim.x;\n\n    // Sub-histograms initialization\n    for(int pos = tx; pos < bins; pos += bD) {\n        l_histo[pos] = 0;\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Main loop\n    for(int i = gpu_first(&p); gpu_more(&p); i = gpu_next(&p)) {\n    \n        // Global memory read\n        unsigned int d = data[i * bD + tx];\n\n        // Atomic vote in shared memory\n        atomicAdd(&l_histo[((d * bins) >> 12)], 1);\n    }\n\n    __syncthreads(); // Intra-block synchronization\n\n    // Merge per-block histograms and write to global memory\n    for(int pos = tx; pos < bins; pos += bD) {\n// Atomic addition in global memory\n#ifdef CUDA_8_0\n        atomicAdd_system(histo + pos, l_histo[pos]);\n#else\n        atomicAdd(histo + pos, l_histo[pos]);\n#endif\n    }\n}\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n    ){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    Histogram_kernel<<<dimGrid, dimBlock, l_mem_size>>>(size, bins, n_tasks, alpha, \n        data, histo\n#ifdef CUDA_8_0\n        , worklist\n#endif\n        );\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda_runtime.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads(std::atomic_uint *histo, unsigned int *data, int size, int bins, int num_threads, int chunk, int n_tasks, float alpha\n#ifdef CUDA_8_0\n    , std::atomic_int *wl\n#endif\n    );\n\ncudaError_t call_Histogram_kernel(int blocks, int threads, int size, int bins, int n_tasks, float alpha, \n    unsigned int *data, unsigned int *histo, int l_mem_size\n#ifdef CUDA_8_0\n    , int* worklist\n#endif\n\t\t);\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int   device;\n    int   n_gpu_threads;\n    int   n_gpu_blocks;\n    int   n_threads;\n    int   n_warmup;\n    int   n_reps;\n    float alpha;\n    int   in_size;\n    int   n_bins;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 256;\n        n_gpu_blocks = 16;\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        alpha         = 0.2;\n        in_size       = 1536 * 1024 * 640;\n        n_bins        = 256;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:a:n:b:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'a': alpha         = atof(optarg); break;\n            case 'n': in_size       = atoi(optarg); break;\n            case 'b': n_bins        = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        if(alpha == 0.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n        } else if(alpha == 1.0) {\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else if(alpha > 0.0 && alpha < 1.0) {\n            assert(n_gpu_threads > 0 && \"Invalid # of device threads!\");\n            assert(n_gpu_blocks > 0 && \"Invalid # of device blocks!\");\n            assert(n_threads > 0 && \"Invalid # of host threads!\");\n        } else {\n#ifdef CUDA_8_0\n            assert((n_gpu_threads > 0 && n_gpu_blocks > 0 || n_threads > 0) && \"Invalid # of host + device workers!\");\n#else\n            assert(0 && \"Illegal value for -a\");\n#endif\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./hsti [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=256)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    -a <A>    fraction of input elements to process on host (default=0.2)\"\n#ifdef CUDA_8_0\n                \"\\n              NOTE: Dynamic partitioning used when <A> is not between 0.0 and 1.0\"\n#else\n                \"\\n              NOTE: <A> must be between 0.0 and 1.0\"\n#endif\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n                \"\\n    -n <N>    input size (default=1572864, i.e., 1536x1024)\"\n                \"\\n    -b <B>    # of bins in histogram (default=256)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(unsigned int *input, const Params &p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, \"./input/image_VanHateren.iml\");\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(int y = 0; y < p.in_size; y++) {\n            int fr   = fread(&temp, sizeof(unsigned short), 1, File);\n            input[y] = (unsigned int)ByteSwap16(temp);\n            if(input[y] >= 4096)\n                input[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate buffers\n    timer.start(\"Allocation\");\n    int n_tasks = divceil(p.in_size, p.n_gpu_threads);\n#ifdef CUDA_8_0\n    unsigned int *h_in;\n    cudaStatus = cudaMallocManaged(&h_in, p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo;\n    cudaStatus = cudaMallocManaged(&h_histo, p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    d_in     = h_in;\n    std::atomic_uint *d_histo  = h_histo;\n    std::atomic_int * worklist;\n    cudaStatus = cudaMallocManaged(&worklist, sizeof(std::atomic_int));\n#else\n    unsigned int *    h_in          = (unsigned int *)malloc(p.in_size * sizeof(unsigned int));\n    std::atomic_uint *h_histo       = (std::atomic_uint *)malloc(p.n_bins * sizeof(std::atomic_uint));\n    unsigned int *    h_histo_merge = (unsigned int *)malloc(p.n_bins * sizeof(unsigned int));\n    unsigned int *    d_in;\n    cudaStatus = cudaMalloc((void**)&d_in, p.in_size * sizeof(unsigned int));\n    unsigned int *    d_histo;\n    cudaStatus = cudaMalloc((void**)&d_histo, p.n_bins * sizeof(unsigned int));\n    ALLOC_ERR(h_in, h_histo, h_histo_merge);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in, p);\n#ifdef CUDA_8_0\n    for(int i = 0; i < p.n_bins; i++) {\n        h_histo[i].store(0);\n    }\n#else\n    memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n#endif\n    cudaDeviceSynchronize();\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n\n#ifndef CUDA_8_0\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    cudaStatus = cudaMemcpy(d_in, h_in, p.in_size * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaDeviceSynchronize();\n    CUDA_ERR();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n#endif\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n#ifdef CUDA_8_0\n        if(p.alpha < 0.0 || p.alpha > 1.0) { // Dynamic partitioning\n            worklist[0].store(0);\n        }\n        for(int i = 0; i < p.n_bins; i++) {\n            h_histo[i].store(0);\n        }\n#else\n        memset(h_histo, 0, p.n_bins * sizeof(unsigned int));\n        cudaStatus = cudaMemcpy(d_histo, h_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyHostToDevice);\n        cudaDeviceSynchronize();\n        CUDA_ERR();\n#endif\n\n        if(rep >= p.n_warmup)\n            timer.start(\"Kernel\");\n\n        p.n_gpu_blocks = p.in_size / p.n_gpu_threads;\n\n        // Launch GPU threads\n        // Kernel launch\n        if(p.n_gpu_blocks > 0) {\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n            cudaStatus = call_Histogram_kernel(p.n_gpu_blocks, p.n_gpu_threads, p.in_size, p.n_bins, n_tasks, \n                p.alpha, d_in, (unsigned int*)d_histo, p.n_bins * sizeof(unsigned int)\n#ifdef CUDA_8_0\n                + sizeof(int), (int*)worklist\n#endif\n                );\n            CUDA_ERR();\n        }\n\n        // Launch CPU threads\n        std::thread main_thread(run_cpu_threads, h_histo, h_in, p.in_size, p.n_bins, p.n_threads, p.n_gpu_threads,\n            n_tasks, p.alpha\n#ifdef CUDA_8_0\n            , worklist\n#endif\n            );\n\n        cudaDeviceSynchronize();\n        main_thread.join();\n\n        if(rep >= p.n_warmup)\n            timer.stop(\"Kernel\");\n    }\n    timer.print(\"Kernel\", p.n_reps);\n\n#ifndef CUDA_8_0\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    cudaStatus = cudaMemcpy(h_histo_merge, d_histo, p.n_bins * sizeof(unsigned int), cudaMemcpyDeviceToHost);\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    for(unsigned int i = 0; i < p.n_bins; ++i) {\n        h_histo_merge[i] += (unsigned int)h_histo[i];\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n#endif\n\n    // Verify answer\n#ifdef CUDA_8_0\n    verify((unsigned int *)h_histo, h_in, p.in_size, p.n_bins);\n#else\n    verify((unsigned int *)h_histo_merge, h_in, p.in_size, p.n_bins);\n#endif\n\n    // Free memory\n    timer.start(\"Deallocation\");\n#ifdef CUDA_8_0\n    cudaStatus = cudaFree(h_in);\n    cudaStatus = cudaFree(h_histo);\n    cudaStatus = cudaFree(worklist);\n#else\n    free(h_in);\n    free(h_histo);\n    free(h_histo_merge);\n    cudaStatus = cudaFree(d_in);\n    cudaStatus = cudaFree(d_histo);\n#endif\n    CUDA_ERR();\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Kernel\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/support/partitioner.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#ifndef _PARTITIONER_H_\r\n#define _PARTITIONER_H_\r\n\r\n#ifndef _CUDA_COMPILER_\r\n#include <iostream>\r\n#endif\r\n\r\n#if !defined(_CUDA_COMPILER_) && defined(CUDA_8_0)\r\n#include <atomic>\r\n#endif\r\n\r\n// Partitioner definition -----------------------------------------------------\r\n\r\ntypedef struct Partitioner {\r\n\r\n    int n_tasks;\r\n    int cut;\r\n    int current;\r\n#ifndef _CUDA_COMPILER_\r\n    int thread_id;\r\n    int n_threads;\r\n#endif\r\n\r\n\r\n#ifdef CUDA_8_0\r\n    // CUDA 8.0 support for dynamic partitioning\r\n    int strategy;\r\n#ifdef _CUDA_COMPILER_\r\n    int *worklist;\r\n    int *tmp;\r\n#else\r\n    std::atomic_int *worklist;\r\n#endif\r\n#endif\r\n\r\n} Partitioner;\r\n\r\n// Partitioning strategies\r\n#define STATIC_PARTITIONING 0\r\n#define DYNAMIC_PARTITIONING 1\r\n\r\n// Create a partitioner -------------------------------------------------------\r\n\r\n#ifdef _CUDA_COMPILER_\r\n__device__\r\n#endif\r\ninline Partitioner partitioner_create(int n_tasks, float alpha\r\n#ifndef _CUDA_COMPILER_\r\n    , int thread_id, int n_threads\r\n#endif\r\n#ifdef CUDA_8_0\r\n#ifdef _CUDA_COMPILER_\r\n    , int *worklist\r\n    , int *tmp\r\n#else\r\n    , std::atomic_int *worklist\r\n#endif\r\n#endif\r\n    ) {\r\n    Partitioner p;\r\n    p.n_tasks = n_tasks;\r\n#ifndef _CUDA_COMPILER_\r\n    p.thread_id = thread_id;\r\n    p.n_threads = n_threads;\r\n#endif\r\n    if(alpha >= 0.0 && alpha <= 1.0) {\r\n        p.cut = p.n_tasks * alpha;\r\n#ifdef CUDA_8_0\r\n        p.strategy = STATIC_PARTITIONING;\r\n#endif\r\n    } else {\r\n#ifdef CUDA_8_0\r\n        p.strategy = DYNAMIC_PARTITIONING;\r\n        p.worklist = worklist;\r\n#ifdef _CUDA_COMPILER_\r\n        p.tmp = tmp;\r\n#endif\r\n#endif\r\n    }\r\n    return p;\r\n}\r\n\r\n// Partitioner iterators: first() ---------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->thread_id;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_first(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->cut + blockIdx.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: more() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline bool cpu_more(const Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        return (p->current < p->n_tasks);\r\n    } else\r\n#endif\r\n    {\r\n        return (p->current < p->cut);\r\n    }\r\n}\r\n\r\n#else\r\n\r\n__device__ inline bool gpu_more(const Partitioner *p) {\r\n    return (p->current < p->n_tasks);\r\n}\r\n\r\n#endif\r\n\r\n// Partitioner iterators: next() ----------------------------------------------\r\n\r\n#ifndef _CUDA_COMPILER_\r\n\r\ninline int cpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        p->current = p->worklist->fetch_add(1);\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + p->n_threads;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#else\r\n\r\n__device__ inline int gpu_next(Partitioner *p) {\r\n#ifdef CUDA_8_0\r\n    if(p->strategy == DYNAMIC_PARTITIONING) {\r\n        if(threadIdx.y == 0 && threadIdx.x == 0) {\r\n            p->tmp[0] = atomicAdd_system(p->worklist, 1);\r\n        }\r\n        __syncthreads();\r\n        p->current = p->tmp[0];\r\n    } else\r\n#endif\r\n    {\r\n        p->current = p->current + gridDim.x;\r\n    }\r\n    return p->current;\r\n}\r\n\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n#include <string.h>\n\ninline int compare_output(unsigned int *outp, unsigned int *outpCPU, int bins) {\n    for(int i = 0; i < bins; i++) {\n        if(outp[i] != outpCPU[i]) {\n            printf(\"Test failed\\n\");\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential implementation for comparison purposes\ninline void HistogramCPU(unsigned int *histo, unsigned int *data, int size, int bins) {\n    for(int i = 0; i < size; i++) {\n        // Read pixel\n        unsigned int d = ((data[i] * bins) >> 12);\n        // Vote in histogram\n        histo[d]++;\n    }\n}\n\ninline void verify(unsigned int *histo, unsigned int *input, int size, int bins) {\n    unsigned int *gold = (unsigned int *)malloc(bins * sizeof(unsigned int));\n    memset(gold, 0, bins * sizeof(unsigned int));\n    HistogramCPU(gold, input, size, bins);\n    compare_output(histo, gold, bins);\n    free(gold);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/dpu/task.c",
    "content": "/*\n* Histogram (HST-S) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Array for communication between adjacent tasklets\nuint32_t* message[NR_TASKLETS];\n// DPU histogram\nuint32_t* histo_dpu;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Histogram in each tasklet\nvoid __attribute__ ((noinline)) histogram(uint32_t* histo, uint32_t bins, T *input, unsigned int l_size){\n    for(unsigned int j = 0; j < l_size; j++) {\n        T d = input[j];\n        histo[(d * bins) >> DEPTH] += 1;\n    }\n}\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n    uint32_t bins = DPU_INPUT_ARGUMENTS.bins;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_histo = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local histogram\n    uint32_t *histo = (uint32_t *) mem_alloc(bins * sizeof(uint32_t));\n\n    // Initialize local histogram\n    for(unsigned int i = 0; i < bins; i++){\n        histo[i] = 0;\n    }\n\n    // Compute histogram\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\n        // Histogram in each tasklet\n        histogram(histo, bins, cache_A, l_size_bytes >> DIV);\n\n    }\n    message[tasklet_id] = histo;\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t *histo_dpu = message[0];\n\n    for (unsigned int i = tasklet_id; i < bins; i += NR_TASKLETS){\n        uint32_t b = 0;\t\t\n        for (unsigned int j = 0; j < NR_TASKLETS; j++){\t\t\t\n            b += *(message[j] + i);\n        }\n        histo_dpu[i] = b;\n    }\n\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Write dpu histogram to current MRAM block\n    if(tasklet_id == 0){\n        if(bins * sizeof(uint32_t) <= 2048)\n            mram_write(histo_dpu, (__mram_ptr void*)(mram_base_addr_histo), bins * sizeof(uint32_t));\n        else \n            for(unsigned int offset = 0; offset < ((bins * sizeof(uint32_t)) >> 11); offset++){\n                mram_write(histo_dpu + (offset << 9), (__mram_ptr void*)(mram_base_addr_histo + (offset << 11)), 2048);\n            }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/host/app.c",
    "content": "/**\n* app.c\n* HST-S Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <math.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic unsigned int* histo_host;\nstatic unsigned int* histo;\n\n// Create input arrays\nstatic void read_input(T* A, const Params p) {\n\n    char  dctFileName[100];\n    FILE *File = NULL;\n\n    // Open input file\n    unsigned short temp;\n    sprintf(dctFileName, p.file_name);\n    if((File = fopen(dctFileName, \"rb\")) != NULL) {\n        for(unsigned int y = 0; y < p.input_size; y++) {\n            fread(&temp, sizeof(unsigned short), 1, File);\n            A[y] = (unsigned int)ByteSwap16(temp);\n            if(A[y] >= 4096)\n                A[y] = 4095;\n        }\n        fclose(File);\n    } else {\n        printf(\"%s does not exist\\n\", dctFileName);\n        exit(1);\n    }\n}\n\n// Compute output in the host\nstatic void histogram_host(unsigned int* histo, T* A, unsigned int bins, unsigned int nr_elements, int exp, unsigned int nr_of_dpus) {\n    if(!exp){\n        for (unsigned int i = 0; i < nr_of_dpus; i++) {\n            for (unsigned int j = 0; j < nr_elements; j++) {\n                T d = A[j];\n                histo[i * bins + ((d * bins) >> DEPTH)] += 1;\n            }\n        }\n    }\n    else{\n        for (unsigned int j = 0; j < nr_elements; j++) {\n            T d = A[j];\n            histo[(d * bins) >> DEPTH] += 1;\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    unsigned int input_size; // Size of input image\n    unsigned int dpu_s = p.dpu_s;\n    if(p.exp == 0)\n        input_size = p.input_size * nr_of_dpus; // Size of input image\n    else if(p.exp == 1)\n        input_size = p.input_size; // Size of input image\n    else\n        input_size = p.input_size * dpu_s; // Size of input image\n\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    histo_host = malloc(p.bins * sizeof(unsigned int));\n    histo = malloc(nr_of_dpus * p.bins * sizeof(unsigned int));\n\n    // Create an input file with arbitrary data\n    read_input(A, p);\n    if(p.exp == 0){\n        for(unsigned int j = 1; j < nr_of_dpus; j++){\n            memcpy(&A[j * input_size_dpu_8bytes], &A[0], input_size_dpu_8bytes * sizeof(T));\n        }\n    }\n    else if(p.exp == 2){\n        for(unsigned int j = 1; j < dpu_s; j++)\n            memcpy(&A[j * p.input_size], &A[0], p.input_size * sizeof(T));\n    }\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\tinput_size\\t%u\\n\", NR_TASKLETS, BL, input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n        memset(histo_host, 0, p.bins * sizeof(unsigned int));\n        memset(histo, 0, nr_of_dpus * p.bins * sizeof(unsigned int));\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        histogram_host(histo_host, A, p.bins, p.input_size, 1, nr_of_dpus);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        i = 0;\n\t    dpu_arguments_t input_arguments[NR_DPUS];\n\t    for(i=0; i<nr_of_dpus-1; i++) {\n\t        input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t        input_arguments[i].bins=p.bins;\n\t        input_arguments[i].kernel=kernel;\n\t    }\n\t    input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n\t    input_arguments[nr_of_dpus-1].bins=p.bins;\n\t    input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, histo + p.bins * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), p.bins * sizeof(unsigned int), DPU_XFER_DEFAULT));\n\n        // Final histogram merging\n        for(i = 1; i < nr_of_dpus; i++){\n            for(unsigned int j = 0; j < p.bins; j++){\n                histo[j] += histo[j + i * p.bins];\n            }\t\t\t\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(p.exp == 1) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else if(p.exp == 2) \n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(dpu_s * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, dpu_s * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    else\n        for (unsigned int j = 0; j < p.bins; j++) {\n            if(nr_of_dpus * histo_host[j] != histo[j]){ \n                status = false;\n#if PRINT\n                printf(\"%u - %u: %u -- %u\\n\", j, j, nr_of_dpus * histo_host[j], histo[j]);\n#endif\n            }\n        }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(histo_host);\n    free(histo);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor b in 64 128 256 512 1024 2048 4096\n\tdo\n    \tfor k in 1 2 4 8 16\n\t    do\n            NR_DPUS=$i NR_TASKLETS=$k BL=10 make all\n            wait\n            ./bin/host_code -w 2 -e 5 -b ${b} -x 1 > profile/HSTS_${b}_tl${k}_dpu${i}.txt\n            wait\n            make clean\n            wait\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#define REGS (BLOCK_SIZE >> 2) // 32 bits\n\n// Pixel depth\n#define DEPTH 12\n#define ByteSwap16(n) (((((unsigned int)n) << 8) & 0xFF00) | ((((unsigned int)n) >> 8) & 0x00FF))\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n    uint32_t bins;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   bins;\n    int   n_warmup;\n    int   n_reps;\n    const char *file_name;\n    int  exp;\n    int  dpu_s;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1, 2) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=1536*1024 elements)\"\n        \"\\n    -b <B>    histogram size (default=256 bins)\"\n        \"\\n    -f <F>    input image file (default=../input/image_VanHateren.iml)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1536 * 1024;\n    p.bins          = 256;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.file_name     = \"./input/image_VanHateren.iml\";\n    p.dpu_s         = 64;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:b:w:e:f:x:z:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'b': p.bins          = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'f': p.file_name     = optarg; break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'z': p.dpu_s         = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/HST-S/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16 \nBL ?= 10\nNR_DPUS ?= 1 \n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -m 1024 -n 1024\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_10_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_11_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_12_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_13_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_14_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_15_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_16",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_16_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_17_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_18_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_19_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_1_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_20_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_21_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_22_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_23_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_24_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_2_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_3_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_4_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_5_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_6_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_7_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_8_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/_NR_TASKLETS_9_BL_10.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/cpu/Makefile",
    "content": "all:\n\tgcc mlp_openmp.c -o mlp_openmp -fopenmp -std=c99\nrun:\n\t./mlp_openmp\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/cpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp_openmp\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/cpu/mlp_openmp.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include \"../../support/timer.h\"\n#include \"../../support/common.h\"\n\nT** A;\nT* B;\nT* C;\n\n// Create input arrays\nstatic void init_data(T** A, T* B, unsigned int m_size, unsigned int n_size){\n    for (unsigned int l = 0; l < NUM_LAYERS; l++)\n\t\tfor (unsigned int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l][i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l][i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\tfor (unsigned int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t}\n}\n\n// Compute output in the host\nstatic void mlp_host(T* C, T** A, T* B, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\t#pragma omp parallel for\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl][m * n_size + n] * B[n];\n\t\t\t}\n\t\t\tC[m] = max(0, C[m]);\n\t\t}\n\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\nstatic uint64_t mlp_host_sum(uint64_t n_size, uint64_t m_size) {\n  uint64_t sum = 0;\n  for (uint64_t m = 0; m < n_size; m++){\n    sum += B[m];\n  }\n  return sum;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  char* dpu_type;\n  int   nr_of_ranks;\n  int   input_size_n;\n  int   input_size_m;\n  int   n_warmup;\n  int   n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -d <D>    DPU type (default=fsim)\"\n    \"\\n    -r <R>    # of ranks (default=2)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -i <I>    input size (default=8M elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.dpu_type      = \"fsim\";\n    p.nr_of_ranks   = 1;\n    p.input_size_n  = 1 << 9;\n    p.input_size_m  = 1 << 9;\n    p.n_warmup      = 2;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:r:i:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'd': p.dpu_type        = optarg; break;\n        case 'r': p.nr_of_ranks     = atoi(optarg); break;\n        case 'n': p.input_size_n    = atoi(optarg); break;\n        case 'm': p.input_size_m    = atoi(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(p.nr_of_ranks > 0 && \"Invalid # of ranks!\");\n\n    return p;\n  }\n\n  /**\n  * @brief Main of the Host Application.\n  */\n  int main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n    uint64_t n_size = 8192;\n    uint64_t m_size = 20480;\n\n    Timer timer;\n    A = malloc(NUM_LAYERS * sizeof(T*));\n    for(int l = 0; l < NUM_LAYERS; l++)\n        A[l] = malloc(n_size*m_size*sizeof(unsigned int));\n    B = malloc(m_size*sizeof(unsigned int));\n    C = malloc(m_size*sizeof(unsigned int));\n\n    // Create an input file with arbitrary data.\n    init_data(A, B, m_size, n_size);\n\n    start(&timer, 0, 1);\n    mlp_host(C, A, B, n_size, m_size);\n    stop(&timer, 0);\n\n    uint32_t sum = mlp_host_sum(n_size, m_size);\n   \n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    printf(\"SUM = %d \\n\", sum);\n\n    for(int l = 0; l < NUM_LAYERS; l++)\n        free(A[l]);\n    free(A);\n    free(B);\n    free(C);\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc mlp.cu -I/usr/local/cuda/include -lm -o mlp\n\nclean:\n\trm mlp\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/gpu/README",
    "content": "Multilayer Perceptron (MLP)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./mlp\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/baselines/gpu/mlp.cu",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/time.h>\n#include <cuda.h>\n#include \"../../support/common.h\"\n\n#define THREAD 128\n\n__global__ void gemv(int m, int n, T *adim, T *b, T *d_ans);\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans);\n\ndouble gettime()\n{\n\tstruct timeval tv;\n\tgettimeofday(&tv, NULL);\n\treturn tv.tv_sec + (double)tv.tv_usec*1.0e-6;\n}\n\nint main(int argc, char **argv)\n{\n\t/* for CPU */\n\tint i, j;\n\tT **bdim; \n\tT *c, *ans, *h_ans, *h_c;\n\tint n = 8192;\n\tint m = 20480;\n\n\tbdim = (T**) malloc(NUM_LAYERS * sizeof(T*));\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tbdim[l] = (T*)malloc(sizeof(T)*m*n);\n\tc = (T*)malloc(sizeof(T) *n);\n\th_c = (T*)malloc(sizeof(T) *n);\n\tans = (T*)malloc(sizeof(T) *m);\n\th_ans = (T*)malloc(sizeof(T) *m);\n\n\t/* for GPU */\n\tT *d_bdim; \n\tT *d_c, *d_ans;\n\tcudaMalloc((void **)&d_bdim, sizeof(T)*m*n);\n\tcudaMalloc((void **)&d_c, sizeof(T)*n);\n\tcudaMalloc((void **)&d_ans, sizeof(T)*m);\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(i % 50 < 48)\n\t\t{\n\t\t\tc[i] = 0;\n\t\t\th_c[i] = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tc[i] = i % 2;\n\t\t\th_c[i] = i % 2;\n\t\t}\n\t}\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfor(i = 0; i < n; i++)\n\t\t{\n\t\t\tfor(j = 0; j < m; j++){\n\t\t\t\tif(j % 100 < 98)\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = 0;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\n\t\t\t\t\tbdim[l][i*m+j] = (l + i) % 2;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tfor(j = 0; j < m; j++){\n\t\tans[j] = 0;\n\t\th_ans[j] = 0;\n\t}\n\t// Computation on the host for verification\n\tT* vector = c;\n\tT* output = ans;\n\tT* matrix;\n\tint mm = m;\n\tint nn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tmatrix = bdim[l];\n\t\tcgemv(mm, nn, matrix, vector, output);\n\t\tvector = output;\n                h_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\t// Event creation\n\tcudaEvent_t start, stop;\n\tcudaEventCreate(&start);\n\tcudaEventCreate(&stop);\n\tfloat time1 = 0;\n\tfloat time2 = 0;\n\tcudaMemcpy(d_ans, h_ans, sizeof(T)*m, cudaMemcpyHostToDevice);\n\tcudaMemcpy(d_c, h_c, sizeof(T)*n, cudaMemcpyHostToDevice);\n\n\tvector = d_c;\n\toutput = d_ans;\n\tmm = m;\n\tnn = n;\n\tfor(int l = 0; l < NUM_LAYERS; l++){\n\t\tcudaMemcpy(d_bdim, bdim[l], sizeof(T)*m*n, cudaMemcpyHostToDevice);\n\t\tmatrix = d_bdim;\n\t\t// Start timer\n\t\tcudaEventRecord( start, 0 );\n\t\tgemv<<<mm, THREAD>>>(mm, nn, matrix, vector, output);\n\t\t// End timer\n\t\tcudaEventRecord( stop, 0 );\n\t\tcudaEventSynchronize( stop );\n\t\tcudaEventElapsedTime( &time2, start, stop );\n\t\ttime1 += time2;\n\t\tvector = output;\n\t\td_ans = output;\n\t\tmm = n; nn = m;\n\t}\n\n\tcudaMemcpy(h_ans, d_ans, sizeof(T)*m, cudaMemcpyDeviceToHost);\n\tcudaMemcpy(h_c, d_c, sizeof(T)*n, cudaMemcpyDeviceToHost);\n\n\tfor(i = 0; i < m; i++)\n\t{\n\t\tif(ans[i] != h_ans[i])\n\t\tprintf(\"ERROR in Ans %d -> %d -- %d\\n\", i, ans[i], h_ans[i]);\n        }\n\n\tfor(i = 0; i < n; i++)\n\t{\n\t\tif(c[i] != h_c[i])\n\t\tprintf(\"ERROR in C %d -> %d -- %d\\n\", i, c[i], h_c[i]);\n\t}\n\tprintf(\"Execution time = %f ms\\n\", time1);\n\n\n\tfor(int l = 0; l < NUM_LAYERS; l++)\n\t\tfree(bdim[l]);\n\n\n\tfree(bdim);\n\tfree(c);\n\tfree(ans);\n\tfree(h_c);\n\tcudaFree(d_bdim);\n\tcudaFree(d_c);\n\tcudaFree(d_ans);\n\tcudaEventDestroy(start);\n\tcudaEventDestroy(stop);\n\n\treturn 0;\n} \n\n__global__ void gemv(int m, int n, T* adim, T* b, T* d_ans)\n{\n\tint i;\n\tint div = n/THREAD;\n\t__shared__ T tmp[THREAD];\n\n\ttmp[threadIdx.x] = 0.0;\n\n\tfor(i = 0; i < div; i++){\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+i*THREAD+threadIdx.x] * b[i * THREAD + threadIdx.x];\n\t}\n\tif(threadIdx.x < m%THREAD)\n\t\ttmp[threadIdx.x] += adim[blockIdx.x*n+THREAD*div+threadIdx.x] * b[THREAD * div + threadIdx.x];\n\n\t__syncthreads();\n\n\tfor(i = THREAD / 2; i > 31; i = i / 2)\n\t{\n\t\tif(threadIdx.x < i)\n\t\t\ttmp[threadIdx.x] += tmp[threadIdx.x + i];\n\t\t__syncthreads();\n\t}\n\n\tif(threadIdx.x < 16)\n\t{\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 16];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 8];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 4];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 2];\n\t\t__syncthreads();\n\t\ttmp[threadIdx.x] += tmp[threadIdx.x + 1];\n\t\t__syncthreads();\n\t}\n\n\n\tif(threadIdx.x == 0)\n\t\td_ans[blockIdx.x] = max(0, tmp[0]);\n\n}\n\nvoid cgemv(int m, int n, T *adim, T *b, T *d_ans)\n{\n\tint i, j;\n\n\tfor(i = 0; i < m; i++){\n\t\tfor(j = 0; j < n; j++)\n\t\t\td_ans[i] += adim[i*n+j] * b[j];\n\t\td_ans[i] = max(0, d_ans[i]);\n\t}\n\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/dpu/task.c",
    "content": "/*\n * Matrix vector multiplication with multiple tasklet\n *\n */\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// GEMV\nvoid __attribute__ ((noinline)) gemv(T *bufferC, T *bufferA, T *bufferB, int pos) {\n\tfor (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++) {\n\t\tbufferC[pos] += bufferA[i] * bufferB[i];\n\t}\n\treturn;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif (tasklet_id == 0){ // Initialize once the cycle counter\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\tint32_t n_size = DPU_INPUT_ARGUMENTS.n_size;\n\tint32_t n_size_pad = DPU_INPUT_ARGUMENTS.n_size_pad;\n\tuint32_t nr_rows = DPU_INPUT_ARGUMENTS.nr_rows;\n\tuint32_t max_rows = DPU_INPUT_ARGUMENTS.max_rows;\n\n\n\tunsigned int nrows = nr_rows;\n\tunsigned int rows_per_tasklet; \n\tunsigned int start_row;\n\tunsigned int chunks = nrows / (NR_TASKLETS + NR_TASKLETS);\n\tunsigned int dbl_chunks = chunks + chunks;                                                                       \n\trows_per_tasklet = dbl_chunks;\n\tunsigned int rest_rows = nrows % (NR_TASKLETS + NR_TASKLETS);\n\n\tif ((tasklet_id + tasklet_id) < rest_rows)\n\t\trows_per_tasklet += 2;\n\tif (rest_rows > 0) {\n\t\tif ((tasklet_id + tasklet_id) >= rest_rows) {\n\t\t\tunsigned int hlf_rest_rows = rest_rows >> 1;\n\t\t\tif ((rest_rows & 1) == 1)\n\t\t\t\tstart_row = (hlf_rest_rows + 1) * (dbl_chunks + 2) + (tasklet_id - 1 - hlf_rest_rows) * dbl_chunks;\n\t\t\telse\n\t\t\t\tstart_row = (hlf_rest_rows) * (dbl_chunks + 2) + (tasklet_id - hlf_rest_rows) * dbl_chunks;\n\t\t} else \n\t\t\tstart_row = tasklet_id * (dbl_chunks + 2);\n\t} else {\n\t\tstart_row = tasklet_id * (dbl_chunks);\n\t}\n\n\t// Address of the current row in MRAM\n\tuint32_t mram_base_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + start_row * n_size * sizeof(T));\n\tuint32_t mram_base_addr_B = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T));\n\tuint32_t mram_base_addr_C = (uint32_t) (DPU_MRAM_HEAP_POINTER + max_rows * n_size_pad * sizeof(T) + n_size_pad * sizeof(T) + start_row * sizeof(T));\n\tuint32_t mram_temp_addr_A = mram_base_addr_A;\n\tuint32_t mram_temp_addr_B = mram_base_addr_B;\n\n\t// Inititalize a local cache to store the MRAM block\n\tT *cache_A = (T *) mem_alloc(BLOCK_SIZE + 8);\n\tT *cache_A_aux = (T *) mem_alloc(8);\n\tT *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\tT *cache_C = (T *) mem_alloc(8);\n\n\tint offset = 0;\n\n\t// Iterate over nr_rows\n\tfor (unsigned int i = start_row; i < start_row + rows_per_tasklet; i += 2) {\n\n\t\tmram_temp_addr_A = (uint32_t) (DPU_MRAM_HEAP_POINTER + i * n_size * sizeof(T));\n\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\tcache_C[0] = 0;\n\t\tcache_C[1] = 0;\n\t\tfor(unsigned int pos = 0; pos < 2 && i + pos < nr_rows; pos++){\n\t\t\tint n = 0, j;\n\t\t\tfor (n = 0; n < (int32_t) (n_size - (BLOCK_SIZE/sizeof(T))); n += (BLOCK_SIZE / sizeof(T)))\n\t\t\t{\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\t\tif(offset)\n\t\t\t\t{\n\n\t\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) - 1; off++)\n\t\t\t\t\t{\n\t\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t\t}\n\n\t\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE), cache_A_aux, 8);\n\n\t\t\t\t\tcache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t\t}\n\n\t\t\t\t// Compute GEMV\n\t\t\t\tgemv(cache_C, cache_A, cache_B, pos);\n\n\t\t\t\t// Update memory addresses\n\t\t\t\tmram_temp_addr_A += BLOCK_SIZE;\n\t\t\t\tmram_temp_addr_B += BLOCK_SIZE;\n\t\t\t}\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A), cache_A, BLOCK_SIZE);\n\n\n\t\t\tif(offset)\n\t\t\t{\n\t\t\t\tfor(unsigned int off = 0; off < (BLOCK_SIZE / sizeof(T)) -1; off++)\n\t\t\t\t{\n\n\t\t\t\t\tcache_A[off] = cache_A[off + 1];\n\t\t\t\t}\n\n\t\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_A + BLOCK_SIZE ), cache_A_aux, 8);\n\n  \t\t\t       cache_A[BLOCK_SIZE / sizeof(T) - 1] = cache_A_aux[0];\n\t\t\t}\n\n\n\t\t\tmram_read((__mram_ptr void const*) (mram_temp_addr_B), cache_B, BLOCK_SIZE);\n\n\t\t\tfor (j = 0; j < (int) (n_size - n); j++) {\n\t\t\t\t// Compute GEMV\n\t\t\t\tif(j >= (int)(BLOCK_SIZE / sizeof(T))){ \n\t\t\t\t\tprintf(\"error\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tcache_C[pos] += cache_A[j] * cache_B[j];\n\t\t\t}\n\n\n\t\t\tmram_temp_addr_A += (BLOCK_SIZE - ((BLOCK_SIZE / sizeof(T)) - (n_size - n)) * sizeof(T));\n\t\t\tmram_temp_addr_B = mram_base_addr_B;\n\n\t\t\tif(mram_temp_addr_A % 8 != 0)\n\t\t\t{\n\t\t\t\toffset = 1;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\toffset = 0;\n\t\t\t}\n\t\t}\n\t\t// Write cache to current MRAM block\n\t\tmram_write(cache_C, (__mram_ptr void *) (mram_base_addr_C), 8);\n\n\t\t// Update memory address\n\t\tmram_base_addr_C += 2 * sizeof(T);\n\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/host/app.c",
    "content": "/**\n * app.c\n * MLP Host Application Source File\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/mlp_dpu\"\n#endif\n\nstatic T** A;\nstatic T* B;\nstatic T* B_host;\nstatic T* B_tmp;\nstatic T* C;\nstatic T* C_dpu;\n\n// Create input arrays\nstatic void init_data(T** A, T* B, T* B_host, unsigned int m_size, unsigned int n_size) {\n\tfor (unsigned int l = 0; l < NUM_LAYERS; l++)\n\t\tfor (unsigned int i = 0; i < m_size * n_size; i++){\n\t\t\tif(i % 100 < 98){\n\t\t\t\tA[l][i] = 0;\n\t\t\t}else{\n\t\t\t\tA[l][i] = (l+i) % 2;\n\t\t\t}\n\t\t}\n\tfor (unsigned int i = 0; i < n_size; i++){\n\t\tif(i % 50 < 48){\n\t\t\tB[i] = 0;\n\t\t}\n\t\telse{\n\t\t\tB[i] = i % 2;\n\t\t}\n\t\tB_host[i] = B[i];\n\t}\n}\n\n// Compute output in the host\nstatic void mlp_host(T* C, T** A, T* B, unsigned int m_size, unsigned int n_size) {\n\n\tfor (unsigned int nl = 0; nl < NUM_LAYERS; nl++){\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tC[m] = 0;\n\t\t}\n\t\tfor (unsigned int m = 0; m < m_size; m++){\n\t\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\t\tC[m] += A[nl][m * n_size + n] * B[n];\n\t\t\t}\n\t\t\tC[m] = max(0, C[m]);\n\t\t}\n\t\tfor (unsigned int n = 0; n < n_size; n++){\n\t\t\tB[n] = C[n];\n\t\t}\n\t}\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\tstruct Params p = input_params(argc, argv);\n\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned int i, l;\n\tunsigned int m_size = p.m_size;\n\tunsigned int n_size = p.n_size;\n\n\t// Initialize help data\n\tdpu_info = (struct dpu_info_t *) malloc(nr_of_dpus * sizeof(struct dpu_info_t));\n\tdpu_arguments_t *input_args = (dpu_arguments_t *) malloc(nr_of_dpus * sizeof(dpu_arguments_t));\n\tuint32_t max_rows_per_dpu = 0;\n\tuint32_t n_size_pad = n_size;\n\tif(n_size % 2 == 1){\n\t\tn_size_pad++;\n\t}\n\n\t// Timer\n\tTimer timer;\n\ti = 0;\n\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\tuint32_t rows_per_dpu;\n\t\tuint32_t prev_rows_dpu = 0;\n\t\tuint32_t chunks = m_size / nr_of_dpus;\n\t\trows_per_dpu = chunks;\n\t\tuint32_t rest_rows = m_size % nr_of_dpus;\n\t\tif (i < rest_rows)\n\t\t\trows_per_dpu++;\n\t\tif (rest_rows > 0) {\n\t\t\tif (i >= rest_rows)\n\t\t\t\tprev_rows_dpu = rest_rows * (chunks + 1) + (i - rest_rows) * chunks;\n\t\t\telse\n\t\t\t\tprev_rows_dpu = i * (chunks + 1);\n\t\t} else {\n\t\t\tprev_rows_dpu = i * chunks;\n\t\t}\n\n\t\t// Keep max rows for parallel transfers\n\t\tuint32_t rows_per_dpu_pad = rows_per_dpu;\n\t\tif (rows_per_dpu_pad % 2 == 1) // 4-byte elements\n\t\t\trows_per_dpu_pad++;\n\t\tif (rows_per_dpu_pad > max_rows_per_dpu)\n\t\t\tmax_rows_per_dpu = rows_per_dpu_pad;\n\n\t\tdpu_info[i].rows_per_dpu = rows_per_dpu;\n\t\tdpu_info[i].rows_per_dpu_pad = rows_per_dpu_pad;\n\t\tdpu_info[i].prev_rows_dpu = prev_rows_dpu;\n\n\t\t// Copy input arguments to DPU\n\t\tinput_args[i].n_size = n_size;\n\t\tinput_args[i].n_size_pad = n_size_pad;\n\t\tinput_args[i].nr_rows = rows_per_dpu;\n\t}\n\n\tA = (T**)malloc(NUM_LAYERS * sizeof(T*));\n\tfor(l = 0; l < NUM_LAYERS; l++)\n\t\tA[l] = (T*)malloc( max_rows_per_dpu * nr_of_dpus * n_size_pad * sizeof(T));\n\n\n\tB = (T*)malloc(n_size * sizeof(T));\n\tB_host = (T*)malloc(n_size * sizeof(T));\n\tC = (T*)malloc(m_size * sizeof(T));\n\tC_dpu = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\tB_tmp = malloc(max_rows_per_dpu * nr_of_dpus * sizeof(T));\n\n\tinit_data(A, B, B_host, m_size, n_size);\n\n\t// Compute output on CPU (performance comparison and verification purposes)\n\tstart(&timer, 0, 0);\n\tmlp_host(C, A, B_host, m_size, n_size);\n\tstop(&timer, 0);\n\n\tfor (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\t// Input arguments\n\t\ti = 0;\n\t\t// Copy input arguments to DPU\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tinput_args[i].max_rows = max_rows_per_dpu;\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n\n\t\t// Copy input array and vector\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A[0] + dpu_info[i].prev_rows_dpu * n_size));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n\n\t\tfor(int lay = 1; lay < NUM_LAYERS; lay++){\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t\tstart(&timer, 4, rep - p.n_warmup);\n\t\t\ti = 0;\n\n\t\t\t// Copy C_dpu\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\t// B = C\n\t\t\tunsigned int n, j;\n\t\t\ti = 0;\n\t\t\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\t\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\t\t\tB_tmp[i] = C_dpu[n * max_rows_per_dpu + j];\n\t\t\t\t\ti++;\n\t\t\t\t}\n\t\t\t}\n\t\t\ti = 0;\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, B_tmp));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) , n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\t// Copy next matrix of weights\n\t\t\ti = 0;\n\t\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, A[lay] + dpu_info[i].prev_rows_dpu * n_size));\n\t\t\t}\n\t\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, max_rows_per_dpu * n_size_pad * sizeof(T), DPU_XFER_DEFAULT));\n\n\t\t\tif(rep >= p.n_warmup)\n\t\t\t\tstop(&timer, 4);\n\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t{\n\t\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t\t}\n\n\t\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\t\tif (rep >= p.n_warmup)\n\t\t\t{\n\t\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t\t}\n\t\t}\n\n#if PRINT\n\t\t// Display DPU Logs\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n\t\t}\n#endif\n\n\t\t// Retrieve results\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, C_dpu + i * max_rows_per_dpu));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, max_rows_per_dpu * n_size_pad * sizeof(T) + n_size_pad * sizeof(T), max_rows_per_dpu * sizeof(T), DPU_XFER_DEFAULT));\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\t}\n\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 0, 1);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"Inter-DPU Time (ms): \");\n\tprint(&timer, 4, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\tprintf(\"\\n\\n\");\n\n\t// Check output\n\tbool status = true;\n\tunsigned int n, j;\n\ti = 0;\n\tfor (n = 0; n < nr_of_dpus; n++) {\n\t\tfor (j = 0; j < dpu_info[n].rows_per_dpu; j++) {\n\t\t\tif(C[i] != C_dpu[n * max_rows_per_dpu + j]) {\n\t\t\t\tstatus = false;\n#if PRINT\n\t\t\t\tprintf(\"%d: %d -- %d\\n\", i, C[i], C_dpu[n * max_rows_per_dpu + j]);\n#endif\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t}\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n\t}\n\n\t// Deallocation\n\tfor(i = 0; i < NUM_LAYERS; i++)\n\t\tfree(A[i]);\n\tfree(A);\n\tfree(B);\n\tfree(C);\n\tfree(C_dpu);\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t n_size;\n    uint32_t n_size_pad;\n    uint32_t nr_rows;\n    uint32_t max_rows;\n} dpu_arguments_t;\n\n// Specific information for each DPU\nstruct dpu_info_t {\n  uint32_t rows_per_dpu;\n  uint32_t rows_per_dpu_pad;\n  uint32_t prev_rows_dpu;\n};\nstruct dpu_info_t *dpu_info;\n\n#define NUM_LAYERS 3 \n#define max(x, y) (x > y ? x : y)\n#define min(x, y) (x < y ? x : y)\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int32_t\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int  m_size;\n    unsigned int  n_size;\n    unsigned int  n_warmup;\n    unsigned int  n_reps;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -m <I>    m_size (default=2048 elements)\"\n            \"\\n    -n <I>    n_size (default=2048 elements)\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.m_size        = 163840;\n    p.n_size        = 4096;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hm:n:w:e:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'm': p.m_size        = atoi(optarg); break;\n            case 'n': p.n_size        = atoi(optarg); break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MLP/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n    //printf(\"Time (ms): %f\\t\",((timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n    //                  (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec)) / 1000);\r\n \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nOP ?= READ\nMEM ?= MRAM\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP},${MEM})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP} -D${MEM}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP} -D${MEM}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/dpu/copy.c",
    "content": "/*\n* MRAM-WRAM R/W Latency with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n        __mram_ptr void const* address_A = (__mram_ptr void const*)(mram_base_addr_A + byte_index);\n        __mram_ptr void* address_B = (__mram_ptr void*)(mram_base_addr_B + byte_index);\n#ifdef READ\n        // Barrier\n        timer_start(&cycles); // START TIMER\n#endif\n        // Load cache with current MRAM block\n        mram_read(address_A, cache_A, BLOCK_SIZE);\n#ifdef READ\n        // Barrier\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n#endif\n\n#ifdef WRITE\n        // Barrier\n        timer_start(&cycles); // START TIMER\n#endif\n        // Write cache to current MRAM block\n        mram_write(cache_A, address_B, BLOCK_SIZE);\n#ifdef WRITE\n        // Barrier\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n#endif\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/host/app.c",
    "content": "/**\n* app.c\n* MRAM Latency Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void stream_host(T* C, T* A, unsigned int nr_elements) {\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        C[i] = A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n    assert(input_size % (nr_of_dpus * NR_TASKLETS) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n    C2 = malloc(input_size * sizeof(T));\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        stream_host(C2, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C2[i] != bufferB[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C2[i], bufferB[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/run.sh",
    "content": "#!/bin/bash\n\nfor i in 3 4 5 6 7 8 9 10 11\ndo\n\tfor j in 1 \n\tdo\n\t\tNR_DPUS=1 NR_TASKLETS=$j BL=$i OP=READ make all\n\t\twait\n\t\t./bin/host_code -w 0 -e 1 -i 2097152 > profile/read_tl${j}_bl${i}.txt\n\t\twait\n\t\tmake clean \n\t\twait\n\n\t\tNR_DPUS=1 NR_TASKLETS=$j BL=$i OP=WRITE make all\n\t\twait\n\t\t./bin/host_code -w 0 -e 1 -i 2097152 > profile/write_tl${j}_bl${i}.txt\n\t\twait\n\t\tmake clean \n\t\twait\n        done\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/MRAM-Latency/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/.conf",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 13\nBL ?= 1024 \nBL_IN ?= 4 \nNR_DPUS ?= 1 \nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -DBL_IN=${BL_IN}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_10_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_11_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_12_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_13_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_14_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_15_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_16_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_17_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_18_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_19_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_1_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_20_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_21_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_22_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_23_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_24_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_2_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_3_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_4_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_5_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_6_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_7_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_8_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/_NR_TASKLETS_9_BL_1024",
    "content": ""
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/cpu/Makefile",
    "content": "# C compiler\nCC = g++\nICC = icc\nCC_FLAGS = -g -O3 -fopenmp\nOFFLOAD_CC_FLAGS = -offload-option,mic,compiler,\"-no-opt-prefetch\"\n\nall: needle needle_offload\n\nneedle: \n\t$(CC) $(CC_FLAGS) needle.cpp -o needle \n\nneedle_offload:\n\t$(ICC) $(CC_FLAGS) $(OFFLOAD_CC_FLAGS) -DOMP_OFFLOAD needle.cpp -o needle_offload\n\nclean:\n\trm -f needle needle_offload\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/cpu/README",
    "content": "Needleman-Wunsch (NW)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./needle 46080 10 4\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/cpu/needle.cpp",
    "content": "#define LIMIT -999\n//#define TRACE\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <math.h>\n#include <sys/time.h>\n#include <omp.h>\n#define OPENMP\n//#define NUM_THREAD 4\n\n#define BLOCK_SIZE 16\n\n////////////////////////////////////////////////////////////////////////////////\n// declaration, forward\nvoid runTest( int argc, char** argv);\n\n// Returns the current system time in microseconds \nlong long get_time()\n{\n    struct timeval tv;\n    gettimeofday(&tv, NULL);\n    return (tv.tv_sec * 1000000) + tv.tv_usec;\n\n}\n\n#ifdef OMP_OFFLOAD\n#pragma omp declare target\n#endif\nint maximum( int a,\n        int b,\n        int c){\n\n    int k;\n    if( a <= b )\n        k = b;\n    else \n        k = a;\n\n    if( k <=c )\n        return(c);\n    else\n        return(k);\n}\n#ifdef OMP_OFFLOAD\n#pragma omp end declare target\n#endif\n\n\nint blosum62[24][24] = {\n    { 4, -1, -2, -2,  0, -1, -1,  0, -2, -1, -1, -1, -1, -2, -1,  1,  0, -3, -2,  0, -2, -1,  0, -4},\n    {-1,  5,  0, -2, -3,  1,  0, -2,  0, -3, -2,  2, -1, -3, -2, -1, -1, -3, -2, -3, -1,  0, -1, -4},\n    {-2,  0,  6,  1, -3,  0,  0,  0,  1, -3, -3,  0, -2, -3, -2,  1,  0, -4, -2, -3,  3,  0, -1, -4},\n    {-2, -2,  1,  6, -3,  0,  2, -1, -1, -3, -4, -1, -3, -3, -1,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    { 0, -3, -3, -3,  9, -3, -4, -3, -3, -1, -1, -3, -1, -2, -3, -1, -1, -2, -2, -1, -3, -3, -2, -4},\n    {-1,  1,  0,  0, -3,  5,  2, -2,  0, -3, -2,  1,  0, -3, -1,  0, -1, -2, -1, -2,  0,  3, -1, -4},\n    {-1,  0,  0,  2, -4,  2,  5, -2,  0, -3, -3,  1, -2, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -2,  0, -1, -3, -2, -2,  6, -2, -4, -4, -2, -3, -3, -2,  0, -2, -2, -3, -3, -1, -2, -1, -4},\n    {-2,  0,  1, -1, -3,  0,  0, -2,  8, -3, -3, -1, -2, -1, -2, -1, -2, -2,  2, -3,  0,  0, -1, -4},\n    {-1, -3, -3, -3, -1, -3, -3, -4, -3,  4,  2, -3,  1,  0, -3, -2, -1, -3, -1,  3, -3, -3, -1, -4},\n    {-1, -2, -3, -4, -1, -2, -3, -4, -3,  2,  4, -2,  2,  0, -3, -2, -1, -2, -1,  1, -4, -3, -1, -4},\n    {-1,  2,  0, -1, -3,  1,  1, -2, -1, -3, -2,  5, -1, -3, -1,  0, -1, -3, -2, -2,  0,  1, -1, -4},\n    {-1, -1, -2, -3, -1,  0, -2, -3, -2,  1,  2, -1,  5,  0, -2, -1, -1, -1, -1,  1, -3, -1, -1, -4},\n    {-2, -3, -3, -3, -2, -3, -3, -3, -1,  0,  0, -3,  0,  6, -4, -2, -2,  1,  3, -1, -3, -3, -1, -4},\n    {-1, -2, -2, -1, -3, -1, -1, -2, -2, -3, -3, -1, -2, -4,  7, -1, -1, -4, -3, -2, -2, -1, -2, -4},\n    { 1, -1,  1,  0, -1,  0,  0,  0, -1, -2, -2,  0, -1, -2, -1,  4,  1, -3, -2, -2,  0,  0,  0, -4},\n    { 0, -1,  0, -1, -1, -1, -1, -2, -2, -1, -1, -1, -1, -2, -1,  1,  5, -2, -2,  0, -1, -1,  0, -4},\n    {-3, -3, -4, -4, -2, -2, -3, -2, -2, -3, -2, -3, -1,  1, -4, -3, -2, 11,  2, -3, -4, -3, -2, -4},\n    {-2, -2, -2, -3, -2, -1, -2, -3,  2, -1, -1, -2, -1,  3, -3, -2, -2,  2,  7, -1, -3, -2, -1, -4},\n    { 0, -3, -3, -3, -1, -2, -2, -3, -3,  3,  1, -2,  1, -1, -2, -2,  0, -3, -1,  4, -3, -2, -1, -4},\n    {-2, -1,  3,  4, -3,  0,  1, -1,  0, -3, -4,  0, -3, -3, -2,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    {-1,  0,  0,  1, -3,  3,  4, -2,  0, -3, -3,  1, -1, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -1, -1, -1, -2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2,  0,  0, -2, -1, -1, -1, -1, -1, -4},\n    {-4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4,  1}\n};\n\ndouble gettime() {\n    struct timeval t;\n    gettimeofday(&t,NULL);\n    return t.tv_sec+t.tv_usec*1e-6;\n}\n\n////////////////////////////////////////////////////////////////////////////////\n// Program main\n////////////////////////////////////////////////////////////////////////////////\n    int\nmain( int argc, char** argv) \n{\n    runTest( argc, argv);\n\n    return EXIT_SUCCESS;\n}\n\nvoid usage(int argc, char **argv)\n{\n    fprintf(stderr, \"Usage: %s <max_rows/max_cols> <penalty> <num_threads>\\n\", argv[0]);\n    fprintf(stderr, \"\\t<dimension>      - x and y dimensions\\n\");\n    fprintf(stderr, \"\\t<penalty>        - penalty(positive integer)\\n\");\n    fprintf(stderr, \"\\t<num_threads>    - no. of threads\\n\");\n    exit(1);\n}\n\nvoid nw_optimized(int *input_itemsets, int *output_itemsets, int *referrence,\n        int max_rows, int max_cols, int penalty)\n{\n#ifdef OMP_OFFLOAD\n    int transfer_size = max_rows * max_cols;\n#pragma omp target data map(to: max_cols, penalty, referrence[0:transfer_size]) map(input_itemsets[0:transfer_size])\n    {\n\n#pragma omp target \n#endif\n        for( int blk = 1; blk <= (max_cols-1)/BLOCK_SIZE; blk++ )\n        {\n#ifdef OPENMP\n#pragma omp parallel for schedule(static) shared(input_itemsets, referrence) firstprivate(blk, max_rows, max_cols, penalty)\n#endif\n            for( int b_index_x = 0; b_index_x < blk; ++b_index_x)\n            {\n                int b_index_y = blk - 1 - b_index_x;\n                int input_itemsets_l[(BLOCK_SIZE + 1) *(BLOCK_SIZE+1)] __attribute__ ((aligned (64)));\n                int reference_l[BLOCK_SIZE * BLOCK_SIZE] __attribute__ ((aligned (64)));\n\n                // Copy referrence to local memory\n                for ( int i = 0; i < BLOCK_SIZE; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE; ++j)\n                    {\n                        reference_l[i*BLOCK_SIZE + j] = referrence[max_cols*(b_index_y*BLOCK_SIZE + i + 1) + b_index_x*BLOCK_SIZE +  j + 1];\n                    }\n                }\n\n                // Copy input_itemsets to local memory\n                for ( int i = 0; i < BLOCK_SIZE + 1; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE + 1; ++j)\n                    {\n                        input_itemsets_l[i*(BLOCK_SIZE + 1) + j] = input_itemsets[max_cols*(b_index_y*BLOCK_SIZE + i) + b_index_x*BLOCK_SIZE +  j];\n                    }\n                }\n\n                // Compute\n                for ( int i = 1; i < BLOCK_SIZE + 1; ++i )\n                {\n                    for ( int j = 1; j < BLOCK_SIZE + 1; ++j)\n                    {\n                        input_itemsets_l[i*(BLOCK_SIZE + 1) + j] = maximum( input_itemsets_l[(i - 1)*(BLOCK_SIZE + 1) + j - 1] + reference_l[(i - 1)*BLOCK_SIZE + j - 1],\n                                input_itemsets_l[i*(BLOCK_SIZE + 1) + j - 1] - penalty,\n                                input_itemsets_l[(i - 1)*(BLOCK_SIZE + 1) + j] - penalty);\n                    }\n                }\n\n                // Copy results to global memory\n                for ( int i = 0; i < BLOCK_SIZE; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE; ++j)\n                    {\n                        input_itemsets[max_cols*(b_index_y*BLOCK_SIZE + i + 1) + b_index_x*BLOCK_SIZE +  j + 1] = input_itemsets_l[(i + 1)*(BLOCK_SIZE+1) + j + 1];\n                    }\n                }\n\n            }\n        }    \n\n        printf(\"Processing bottom-right matrix\\n\");\n\n#ifdef OMP_OFFLOAD\n#pragma omp target\n#endif\n        for ( int blk = 2; blk <= (max_cols-1)/BLOCK_SIZE; blk++ )\n        {\n#ifdef OPENMP\n#pragma omp parallel for schedule(static) shared(input_itemsets, referrence) firstprivate(blk, max_rows, max_cols, penalty)\n#endif\n            for( int b_index_x = blk - 1; b_index_x < (max_cols-1)/BLOCK_SIZE; ++b_index_x)\n            {\n                int b_index_y = (max_cols-1)/BLOCK_SIZE + blk - 2 - b_index_x;\n\n                int input_itemsets_l[(BLOCK_SIZE + 1) *(BLOCK_SIZE+1)] __attribute__ ((aligned (64)));\n                int reference_l[BLOCK_SIZE * BLOCK_SIZE] __attribute__ ((aligned (64)));\n\n                // Copy referrence to local memory\n                for ( int i = 0; i < BLOCK_SIZE; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE; ++j)\n                    {\n                        reference_l[i*BLOCK_SIZE + j] = referrence[max_cols*(b_index_y*BLOCK_SIZE + i + 1) + b_index_x*BLOCK_SIZE +  j + 1];\n                    }\n                }\n\n                // Copy input_itemsets to local memory\n                for ( int i = 0; i < BLOCK_SIZE + 1; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE + 1; ++j)\n                    {\n                        input_itemsets_l[i*(BLOCK_SIZE + 1) + j] = input_itemsets[max_cols*(b_index_y*BLOCK_SIZE + i) + b_index_x*BLOCK_SIZE +  j];\n                    }\n                }\n\n                // Compute\n                for ( int i = 1; i < BLOCK_SIZE + 1; ++i )\n                {\n                    for ( int j = 1; j < BLOCK_SIZE + 1; ++j)\n                    {\n                        input_itemsets_l[i*(BLOCK_SIZE + 1) + j] = maximum( input_itemsets_l[(i - 1)*(BLOCK_SIZE + 1) + j - 1] + reference_l[(i - 1)*BLOCK_SIZE + j - 1],\n                                input_itemsets_l[i*(BLOCK_SIZE + 1) + j - 1] - penalty,\n                                input_itemsets_l[(i - 1)*(BLOCK_SIZE + 1) + j] - penalty);\n                    }\n                }\n\n                // Copy results to global memory\n                for ( int i = 0; i < BLOCK_SIZE; ++i )\n                {\n#pragma omp simd\n                    for ( int j = 0; j < BLOCK_SIZE; ++j)\n                    {\n                        input_itemsets[max_cols*(b_index_y*BLOCK_SIZE + i + 1) + b_index_x*BLOCK_SIZE +  j + 1] = input_itemsets_l[(i + 1)*(BLOCK_SIZE+1) + j +1];\n                    }\n                }\n            }\n        }\n\n#ifdef OMP_OFFLOAD\n    }\n#endif\n\n}\n\n////////////////////////////////////////////////////////////////////////////////\n//! Run a simple test for CUDA\n////////////////////////////////////////////////////////////////////////////////\n    void\nrunTest( int argc, char** argv) \n{\n    int max_rows, max_cols, penalty;\n    int *input_itemsets, *output_itemsets, *referrence;\n    //int *matrix_cuda, *matrix_cuda_out, *referrence_cuda;\n    //int size;\n    int omp_num_threads;\n\n\n    // the lengths of the two sequences should be able to divided by 16.\n    // And at current stage  max_rows needs to equal max_cols\n    if (argc == 4)\n    {\n        max_rows = atoi(argv[1]);\n        max_cols = atoi(argv[1]);\n        penalty = atoi(argv[2]);\n        omp_num_threads = atoi(argv[3]);\n    }\n    else{\n        usage(argc, argv);\n    }\n\n    max_rows = max_rows + 1;\n    max_cols = max_cols + 1;\n    referrence = (int *)malloc( max_rows * max_cols * sizeof(int) );\n    input_itemsets = (int *)malloc( max_rows * max_cols * sizeof(int) );\n    output_itemsets = (int *)malloc( max_rows * max_cols * sizeof(int) );\n\n\n    if (!input_itemsets)\n        fprintf(stderr, \"error: can not allocate memory\");\n\n    srand ( 7 );\n\n    for (int i = 0 ; i < max_cols; i++){\n        for (int j = 0 ; j < max_rows; j++){\n            input_itemsets[i*max_cols+j] = 0;\n        }\n    }\n\n    printf(\"Start Needleman-Wunsch\\n\");\n\n    for( int i=1; i< max_rows ; i++){    //please define your own sequence. \n        input_itemsets[i*max_cols] = rand() % 10 + 1;\n    }\n    for( int j=1; j< max_cols ; j++){    //please define your own sequence.\n        input_itemsets[j] = rand() % 10 + 1;\n    }\n\n\n    for (int i = 1 ; i < max_cols; i++){\n        for (int j = 1 ; j < max_rows; j++){\n            referrence[i*max_cols+j] = blosum62[input_itemsets[i*max_cols]][input_itemsets[j]];\n        }\n    }\n\n    for( int i = 1; i< max_rows ; i++)\n        input_itemsets[i*max_cols] = -i * penalty;\n    for( int j = 1; j< max_cols ; j++)\n        input_itemsets[j] = -j * penalty;\n\n\n\n    //Compute top-left matrix \n    printf(\"Num of threads: %d\\n\", omp_num_threads);\n    printf(\"Processing top-left matrix\\n\");\n\n    long long start_time = get_time();\n\n    nw_optimized( input_itemsets, output_itemsets, referrence,\n            max_rows, max_cols, penalty );\n\n    long long end_time = get_time();\n\n    printf(\"Total time: %.3f seconds\\n\", ((float) (end_time - start_time)) / (1000*1000));\n\n#define TRACEBACK\n#ifdef TRACEBACK\n\n    FILE *fpo = fopen(\"result.txt\",\"w\");\n    fprintf(fpo, \"print traceback value GPU:\\n\");\n\n    for (int i = max_rows - 2,  j = max_rows - 2; i>=0, j>=0;){\n        int nw, n, w, traceback;\n        if ( i == max_rows - 2 && j == max_rows - 2 )\n            fprintf(fpo, \"%d \", input_itemsets[ i * max_cols + j]); //print the first element\n        if ( i == 0 && j == 0 )\n            break;\n        if ( i > 0 && j > 0 ){\n            nw = input_itemsets[(i - 1) * max_cols + j - 1];\n            w  = input_itemsets[ i * max_cols + j - 1 ];\n            n  = input_itemsets[(i - 1) * max_cols + j];\n        }\n        else if ( i == 0 ){\n            nw = n = LIMIT;\n            w  = input_itemsets[ i * max_cols + j - 1 ];\n        }\n        else if ( j == 0 ){\n            nw = w = LIMIT;\n            n  = input_itemsets[(i - 1) * max_cols + j];\n        }\n        else{\n        }\n\n        //traceback = maximum(nw, w, n);\n        int new_nw, new_w, new_n;\n        new_nw = nw + referrence[i * max_cols + j];\n        new_w = w - penalty;\n        new_n = n - penalty;\n\n        traceback = maximum(new_nw, new_w, new_n);\n        if(traceback == new_nw)\n            traceback = nw;\n        if(traceback == new_w)\n            traceback = w;\n        if(traceback == new_n)\n            traceback = n;\n\n        fprintf(fpo, \"%d \", traceback);\n\n        if(traceback == nw )\n        {i--; j--; continue;}\n\n        else if(traceback == w )\n        {j--; continue;}\n\n        else if(traceback == n )\n        {i--; continue;}\n\n        else\n            ;\n    }\n\n    fclose(fpo);\n\n#endif\n\n    free(referrence);\n    free(input_itemsets);\n    free(output_itemsets);\n\n}\n\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/cpu/run",
    "content": "./needle 2048 10 2 \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/cpu/run_offload",
    "content": "./needle_offload 2048 10 2\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/Makefile",
    "content": "include ./common/make.config\n\nCC := $(CUDA_DIR)/bin/nvcc\n\nINCLUDE := $(CUDA_DIR)/include\n\nSRC = needle.cu\n\nEXE = needle\n\nrelease: $(SRC)\n\t$(CC) ${KERNEL_DIM} $(SRC) -o $(EXE) -I$(INCLUDE) -L$(CUDA_LIB_DIR) -DTIMING \n\nclang: $(SRC)\n\tclang++ $(SRC) -o $(EXE) -I../util --cuda-gpu-arch=sm_20 \\\n\t\t-L/usr/local/cuda/lib64 -lcudart_static -ldl -lrt -pthread -DTIMING\n\nenum: $(SRC)\n\t$(CC) ${KERNEL_DIM} -deviceemu $(SRC) -o $(EXE) -I$(INCLUDE) -L$(CUDA_LIB_DIR) \n\ndebug: $(SRC)\n\t$(CC) ${KERNEL_DIM} -g $(SRC) -o $(EXE) -I$(INCLUDE) -L$(CUDA_LIB_DIR) \n\ndebugenum: $(SRC)\n\t$(CC) ${KERNEL_DIM} -g -deviceemu $(SRC) -o $(EXE) -I$(INCLUDE) -L$(CUDA_LIB_DIR) \n\nclean: $(SRC)\n\trm -f $(EXE) $(EXE).linkinfo result.txt\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/Makefile_nvidia",
    "content": "################################################################################\n#\n# Copyright 1993-2006 NVIDIA Corporation.  All rights reserved.\n#\n# NOTICE TO USER:   \n#\n# This source code is subject to NVIDIA ownership rights under U.S. and \n# international Copyright laws.  \n#\n# NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE \n# CODE FOR ANY PURPOSE.  IT IS PROVIDED \"AS IS\" WITHOUT EXPRESS OR \n# IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH \n# REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF \n# MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.   \n# IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, \n# OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS \n# OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE \n# OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE \n# OR PERFORMANCE OF THIS SOURCE CODE.  \n#\n# U.S. Government End Users.  This source code is a \"commercial item\" as \n# that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting  of \n# \"commercial computer software\" and \"commercial computer software \n# documentation\" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) \n# and is provided to the U.S. Government only as a commercial end item.  \n# Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through \n# 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the \n# source code with only those rights set forth herein.\n#\n################################################################################\n#\n# Build script for project\n#\n################################################################################\n\n# Add source files here\nEXECUTABLE\t:= needle\n# CUDA source files (compiled with cudacc)\nCUFILES\t\t:= needle.cu\n# CUDA dependency files\nCU_DEPS\t\t:= needle_kernel.cu\n# C/C++ source files (compiled with gcc / c++)\n# CCFILES\t\t:= BlackScholes_gold.cpp\n\n\n\n################################################################################\n# Rules and targets\n\ninclude ./common/common.mk\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/README",
    "content": "Needleman-Wunsch (NW)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./needle 46080 10\n\n\nNote: This program generate two sequences randomly. Please specify your own sequences for different uses.\n      At the current stage, the program only supports two sequences with the same lengh, which can be divided by 16. \nUsage: needle 32 10 \n\t  32 //the length of both sequences\n\t  10 //penalty value\n\n******Adjustable work group size*****\nRD_WG_SIZE_0 or RD_WG_SIZE_0_0 \n\nUSAGE:\nmake clean\nmake KERNEL_DIM=\"-DRD_WG_SIZE_0=16\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/common/common.mk",
    "content": "################################################################################\n#\n# Copyright 1993-2006 NVIDIA Corporation.  All rights reserved.\n#\n# NOTICE TO USER:   \n#\n# This source code is subject to NVIDIA ownership rights under U.S. and \n# international Copyright laws.  \n#\n# NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE \n# CODE FOR ANY PURPOSE.  IT IS PROVIDED \"AS IS\" WITHOUT EXPRESS OR \n# IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH \n# REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF \n# MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.   \n# IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, \n# OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS \n# OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE \n# OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE \n# OR PERFORMANCE OF THIS SOURCE CODE.  \n#\n# U.S. Government End Users.  This source code is a \"commercial item\" as \n# that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting  of \n# \"commercial computer software\" and \"commercial computer software \n# documentation\" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) \n# and is provided to the U.S. Government only as a commercial end item.  \n# Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through \n# 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the \n# source code with only those rights set forth herein.\n#\n################################################################################\n#\n# Common build script\n#\n################################################################################\n\n.SUFFIXES : .cu .cu_dbg_o .c_dbg_o .cpp_dbg_o .cu_rel_o .c_rel_o .cpp_rel_o .cubin\n\n# Add new SM Versions here as devices with new Compute Capability are released\nSM_VERSIONS := sm_10 sm_11 sm_12 sm_13\n\nCUDA_INSTALL_PATH ?= /usr/local/cuda\n\nifdef cuda-install\n\tCUDA_INSTALL_PATH := $(cuda-install)\nendif\n\n# detect OS\nOSUPPER = $(shell uname -s 2>/dev/null | tr [:lower:] [:upper:])\nOSLOWER = $(shell uname -s 2>/dev/null | tr [:upper:] [:lower:])\n# 'linux' is output for Linux system, 'darwin' for OS X\nDARWIN = $(strip $(findstring DARWIN, $(OSUPPER)))\n\n# Basic directory setup for SDK\n# (override directories only if they are not already defined)\nSRCDIR     ?= \nROOTDIR    ?= ..\nROOTBINDIR ?= $(ROOTDIR)/../bin\nBINDIR     ?= $(ROOTBINDIR)/$(OSLOWER)\nROOTOBJDIR ?= obj\nLIBDIR     := $(ROOTDIR)/../lib\nCOMMONDIR  := $(ROOTDIR)/../common\n\n# Compilers\nNVCC       := $(CUDA_INSTALL_PATH)/bin/nvcc \nCXX        := g++\nCC         := gcc\nLINK       := g++ -fPIC\n\n# Includes\nINCLUDES  += -I. -I$(CUDA_INSTALL_PATH)/include -I$(COMMONDIR)/inc\n\n# architecture flag for cubin build\nCUBIN_ARCH_FLAG := -m32\n\n# Warning flags\nCXXWARN_FLAGS := \\\n\t-W -Wall \\\n\t-Wimplicit \\\n\t-Wswitch \\\n\t-Wformat \\\n\t-Wchar-subscripts \\\n\t-Wparentheses \\\n\t-Wmultichar \\\n\t-Wtrigraphs \\\n\t-Wpointer-arith \\\n\t-Wcast-align \\\n\t-Wreturn-type \\\n\t-Wno-unused-function \\\n\t$(SPACE)\n\nCWARN_FLAGS := $(CXXWARN_FLAGS) \\\n\t-Wstrict-prototypes \\\n\t-Wmissing-prototypes \\\n\t-Wmissing-declarations \\\n\t-Wnested-externs \\\n\t-Wmain \\\n\n# Compiler-specific flags\nNVCCFLAGS := \nCXXFLAGS  := $(CXXWARN_FLAGS)\nCFLAGS    := $(CWARN_FLAGS)\n\n# Common flags\nCOMMONFLAGS += $(INCLUDES) -DUNIX\n\n# Debug/release configuration\nifeq ($(dbg),1)\n\tCOMMONFLAGS += -g\n\tNVCCFLAGS   += -D_DEBUG\n\tBINSUBDIR   := debug\n\tLIBSUFFIX   := D\nelse \n\tCOMMONFLAGS += -O3 \n\tBINSUBDIR   := release\n\tLIBSUFFIX   :=\n\tNVCCFLAGS   += --compiler-options -fno-strict-aliasing\n\tCXXFLAGS    += -fno-strict-aliasing\n\tCFLAGS      += -fno-strict-aliasing\nendif\n\n# append optional arch/SM version flags (such as -arch sm_11)\n#NVCCFLAGS += $(SMVERSIONFLAGS)\n\n# architecture flag for cubin build\nCUBIN_ARCH_FLAG := -m32\n\n# detect if 32 bit or 64 bit system\nHP_64 =\t$(shell uname -m | grep 64)\n\n# OpenGL is used or not (if it is used, then it is necessary to include GLEW)\nifeq ($(USEGLLIB),1)\n\n\tifneq ($(DARWIN),)\n\t\tOPENGLLIB := -L/System/Library/Frameworks/OpenGL.framework/Libraries -lGL -lGLU $(COMMONDIR)/lib/$(OSLOWER)/libGLEW.a\n\telse\n\t\tOPENGLLIB := -lGL -lGLU\n\n\t\tifeq \"$(strip $(HP_64))\" \"\"\n\t\t\tOPENGLLIB += -lGLEW\n\t\telse\n\t\t\tOPENGLLIB += -lGLEW_x86_64\n\t\tendif\n\tendif\n\n\tCUBIN_ARCH_FLAG := -m64\nendif\n\nifeq ($(USEGLUT),1)\n\tifneq ($(DARWIN),)\n\t\tOPENGLLIB += -framework GLUT\n\telse\n\t\tOPENGLLIB += -lglut\n\tendif\nendif\n\nifeq ($(USEPARAMGL),1)\n\tPARAMGLLIB := -lparamgl$(LIBSUFFIX)\nendif\n\nifeq ($(USERENDERCHECKGL),1)\n\tRENDERCHECKGLLIB := -lrendercheckgl$(LIBSUFFIX)\nendif\n\nifeq ($(USECUDPP), 1)\n\tifeq \"$(strip $(HP_64))\" \"\"\n\t\tCUDPPLIB := -lcudpp\n\telse\n\t\tCUDPPLIB := -lcudpp64\n\tendif\n\n\tCUDPPLIB := $(CUDPPLIB)$(LIBSUFFIX)\n\n\tifeq ($(emu), 1)\n\t\tCUDPPLIB := $(CUDPPLIB)_emu\n\tendif\nendif\n\n# Libs\nLIB       := -L$(CUDA_INSTALL_PATH)/lib -L$(LIBDIR) -L$(COMMONDIR)/lib/$(OSLOWER)\nifeq ($(USEDRVAPI),1)\n   LIB += -lcuda ${OPENGLLIB} $(PARAMGLLIB) $(RENDERCHECKGLLIB) $(CUDPPLIB) ${LIB} \nelse\n   LIB += -lcudart ${OPENGLLIB} $(PARAMGLLIB) $(RENDERCHECKGLLIB) $(CUDPPLIB) ${LIB}\nendif\n\nifeq ($(USECUFFT),1)\n  ifeq ($(emu),1)\n    LIB += -lcufftemu\n  else\n    LIB += -lcufft\n  endif\nendif\n\nifeq ($(USECUBLAS),1)\n  ifeq ($(emu),1)\n    LIB += -lcublasemu\n  else\n    LIB += -lcublas\n  endif\nendif\n\n# Lib/exe configuration\nifneq ($(STATIC_LIB),)\n\tTARGETDIR := $(LIBDIR)\n\tTARGET   := $(subst .a,$(LIBSUFFIX).a,$(LIBDIR)/$(STATIC_LIB))\n\tLINKLINE  = ar qv $(TARGET) $(OBJS) \nelse\n\t# LIB += -lcutil$(LIBSUFFIX)\n\t# Device emulation configuration\n\tifeq ($(emu), 1)\n\t\tNVCCFLAGS   += -deviceemu\n\t\tCUDACCFLAGS += \n\t\tBINSUBDIR   := emu$(BINSUBDIR)\n\t\t# consistency, makes developing easier\n\t\tCXXFLAGS\t\t+= -D__DEVICE_EMULATION__\n\t\tCFLAGS\t\t\t+= -D__DEVICE_EMULATION__\n\tendif\n\tTARGETDIR := $(BINDIR)/$(BINSUBDIR)\n\tTARGET    := $(TARGETDIR)/$(EXECUTABLE)\n\tLINKLINE  = $(LINK) -o $(TARGET) $(OBJS) $(LIB)\nendif\n\n# check if verbose \nifeq ($(verbose), 1)\n\tVERBOSE :=\nelse\n\tVERBOSE := @\nendif\n\n################################################################################\n# Check for input flags and set compiler flags appropriately\n################################################################################\nifeq ($(fastmath), 1)\n\tNVCCFLAGS += -use_fast_math\nendif\n\nifeq ($(keep), 1)\n\tNVCCFLAGS += -keep\n\tNVCC_KEEP_CLEAN := *.i* *.cubin *.cu.c *.cudafe* *.fatbin.c *.ptx\nendif\n\nifdef maxregisters\n\tNVCCFLAGS += -maxrregcount $(maxregisters)\nendif\n\n# Add cudacc flags\nNVCCFLAGS += $(CUDACCFLAGS)\n\n# workaround for mac os x cuda 1.1 compiler issues\nifneq ($(DARWIN),)\n\tNVCCFLAGS += --host-compilation=C\nendif\n\n# Add common flags\nNVCCFLAGS += $(COMMONFLAGS)\nCXXFLAGS  += $(COMMONFLAGS)\nCFLAGS    += $(COMMONFLAGS)\n\nifeq ($(nvcc_warn_verbose),1)\n\tNVCCFLAGS += $(addprefix --compiler-options ,$(CXXWARN_FLAGS)) \n\tNVCCFLAGS += --compiler-options -fno-strict-aliasing\nendif\n\n################################################################################\n# Set up object files\n################################################################################\nOBJDIR := $(ROOTOBJDIR)/$(BINSUBDIR)\nOBJS +=  $(patsubst %.cpp,$(OBJDIR)/%.cpp_o,$(notdir $(CCFILES)))\nOBJS +=  $(patsubst %.c,$(OBJDIR)/%.c_o,$(notdir $(CFILES)))\nOBJS +=  $(patsubst %.cu,$(OBJDIR)/%.cu_o,$(notdir $(CUFILES)))\n\n################################################################################\n# Set up cubin files\n################################################################################\nCUBINDIR := $(SRCDIR)data\nCUBINS +=  $(patsubst %.cu,$(CUBINDIR)/%.cubin,$(notdir $(CUBINFILES)))\n\n################################################################################\n# Rules\n################################################################################\n$(OBJDIR)/%.c_o : $(SRCDIR)%.c $(C_DEPS)\n\t$(VERBOSE)$(CC) $(CFLAGS) -o $@ -c $<\n\n$(OBJDIR)/%.cpp_o : $(SRCDIR)%.cpp $(C_DEPS)\n\t$(VERBOSE)$(CXX) $(CXXFLAGS) -o $@ -c $<\n\n$(OBJDIR)/%.cu_o : $(SRCDIR)%.cu $(CU_DEPS)\n\t$(VERBOSE)$(NVCC) $(NVCCFLAGS) $(SMVERSIONFLAGS) -o $@ -c $<\n\n$(CUBINDIR)/%.cubin : $(SRCDIR)%.cu cubindirectory\n\t$(VERBOSE)$(NVCC) $(CUBIN_ARCH_FLAG) $(NVCCFLAGS) $(SMVERSIONFLAGS) -o $@ -cubin $<\n\n#\n# The following definition is a template that gets instantiated for each SM\n# version (sm_10, sm_13, etc.) stored in SMVERSIONS.  It does 2 things:\n# 1. It adds to OBJS a .cu_sm_XX_o for each .cu file it finds in CUFILES_sm_XX.\n# 2. It generates a rule for building .cu_sm_XX_o files from the corresponding \n#    .cu file.\n#\n# The intended use for this is to allow Makefiles that use common.mk to compile\n# files to different Compute Capability targets (aka SM arch version).  To do\n# so, in the Makefile, list files for each SM arch separately, like so:\n#\n# CUFILES_sm_10 := mycudakernel_sm10.cu app.cu\n# CUFILES_sm_12 := anothercudakernel_sm12.cu\n#\ndefine SMVERSION_template\nOBJS += $(patsubst %.cu,$(OBJDIR)/%.cu_$(1)_o,$(notdir $(CUFILES_$(1))))\n$(OBJDIR)/%.cu_$(1)_o : $(SRCDIR)%.cu $(CU_DEPS)\n\t$(VERBOSE)$(NVCC) -o $$@ -c $$< $(NVCCFLAGS) -arch $(1)\nendef\n\n# This line invokes the above template for each arch version stored in\n# SM_VERSIONS.  The call funtion invokes the template, and the eval\n# function interprets it as make commands.\n$(foreach smver,$(SM_VERSIONS),$(eval $(call SMVERSION_template,$(smver))))\n\n$(TARGET): makedirectories $(OBJS) $(CUBINS) Makefile\n\t$(VERBOSE)$(LINKLINE)\n\ncubindirectory:\n\t$(VERBOSE)mkdir -p $(CUBINDIR)\n\nmakedirectories:\n\t$(VERBOSE)mkdir -p $(LIBDIR)\n\t$(VERBOSE)mkdir -p $(OBJDIR)\n\t$(VERBOSE)mkdir -p $(TARGETDIR)\n\n\ntidy :\n\t$(VERBOSE)find . | egrep \"#\" | xargs rm -f\n\t$(VERBOSE)find . | egrep \"\\~\" | xargs rm -f\n\nclean : tidy\n\t$(VERBOSE)rm -f $(OBJS)\n\t$(VERBOSE)rm -f $(CUBINS)\n\t$(VERBOSE)rm -f $(TARGET)\n\t$(VERBOSE)rm -f $(NVCC_KEEP_CLEAN)\n\nclobber : clean\n\t$(VERBOSE)rm -rf $(ROOTOBJDIR)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/common/make.config",
    "content": "# CUDA toolkit installation path\nCUDA_DIR = /usr/local/cuda\n\n# CUDA toolkit libraries\nCUDA_LIB_DIR := $(CUDA_DIR)/lib\nifeq ($(shell uname -m), x86_64)\n     ifeq ($(shell if test -d $(CUDA_DIR)/lib64; then echo T; else echo F; fi), T)\n     \tCUDA_LIB_DIR := $(CUDA_DIR)/lib64\n     endif\nendif\n\n# CUDA SDK installation path\nSDK_DIR = /usr/local/cuda/samples/\n\n# OPENCL\n\n# NVIDIA_DIR\nNV_OPENCL_DIR =/usr/local/cuda\nNV_OPENCL_INC = $(NV_OPENCL_DIR)/include\nNV_OPENCL_LIB = $(NV_OPENCL_DIR)/lib64\n\n# INTEL_DIR\nINTEL_OPENCL_DIR = /opt/intel/opencl\nINTEL_OPENCL_INC = $(INTEL_OPENCL_DIR)/include\nINTEL_OPENCL_LIB = $(INTEL_OPENCL_DIR)\n\n# AMD_DIR\n# OPENCL_DIR = /usr/local/cuda\n# OPENCL_INC = $(OPENCL_DIR)/include/ \n# OPENCL_LIB = $(OPENCL_DIR)/lib/x86_64/ -lOpenCL\n#ifeq ($(shell uname -m), x86_64)\n#     ifeq ($(shell if test -d $(OPENCL_DIR)/lib/x86_64/; then echo T; else echo F; fi), T)\n#     \tOPENCL_LIB = $(OPENCL_DIR)/lib/x86_64/\n#     endif\n#endif\n\n# DEFAULT OCL\nOPENCL_DIR = $(NV_OPENCL_DIR)\nOPENCL_INC = $(NV_OPENCL_INC)\nOPENCL_LIB = $(NV_OPENCL_LIB)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/needle.cu",
    "content": "#define LIMIT -999\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <math.h>\n#include \"needle.h\"\n#include <cuda.h>\n#include <sys/time.h>\n\n// includes, kernels\n#include \"needle_kernel.cu\"\n\n#ifdef TIMING\n#include \"timing.h\"\n\nstruct timeval tv;\nstruct timeval tv_total_start, tv_total_end;\nstruct timeval tv_h2d_start, tv_h2d_end;\nstruct timeval tv_d2h_start, tv_d2h_end;\nstruct timeval tv_kernel_start, tv_kernel_end;\nstruct timeval tv_mem_alloc_start, tv_mem_alloc_end;\nstruct timeval tv_close_start, tv_close_end;\nfloat init_time = 0, mem_alloc_time = 0, h2d_time = 0, kernel_time = 0,\n      d2h_time = 0, close_time = 0, total_time = 0;\n#endif\n\n////////////////////////////////////////////////////////////////////////////////\n// declaration, forward\nvoid runTest( int argc, char** argv);\n\n\nint blosum62[24][24] = {\n    { 4, -1, -2, -2,  0, -1, -1,  0, -2, -1, -1, -1, -1, -2, -1,  1,  0, -3, -2,  0, -2, -1,  0, -4},\n    {-1,  5,  0, -2, -3,  1,  0, -2,  0, -3, -2,  2, -1, -3, -2, -1, -1, -3, -2, -3, -1,  0, -1, -4},\n    {-2,  0,  6,  1, -3,  0,  0,  0,  1, -3, -3,  0, -2, -3, -2,  1,  0, -4, -2, -3,  3,  0, -1, -4},\n    {-2, -2,  1,  6, -3,  0,  2, -1, -1, -3, -4, -1, -3, -3, -1,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    { 0, -3, -3, -3,  9, -3, -4, -3, -3, -1, -1, -3, -1, -2, -3, -1, -1, -2, -2, -1, -3, -3, -2, -4},\n    {-1,  1,  0,  0, -3,  5,  2, -2,  0, -3, -2,  1,  0, -3, -1,  0, -1, -2, -1, -2,  0,  3, -1, -4},\n    {-1,  0,  0,  2, -4,  2,  5, -2,  0, -3, -3,  1, -2, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -2,  0, -1, -3, -2, -2,  6, -2, -4, -4, -2, -3, -3, -2,  0, -2, -2, -3, -3, -1, -2, -1, -4},\n    {-2,  0,  1, -1, -3,  0,  0, -2,  8, -3, -3, -1, -2, -1, -2, -1, -2, -2,  2, -3,  0,  0, -1, -4},\n    {-1, -3, -3, -3, -1, -3, -3, -4, -3,  4,  2, -3,  1,  0, -3, -2, -1, -3, -1,  3, -3, -3, -1, -4},\n    {-1, -2, -3, -4, -1, -2, -3, -4, -3,  2,  4, -2,  2,  0, -3, -2, -1, -2, -1,  1, -4, -3, -1, -4},\n    {-1,  2,  0, -1, -3,  1,  1, -2, -1, -3, -2,  5, -1, -3, -1,  0, -1, -3, -2, -2,  0,  1, -1, -4},\n    {-1, -1, -2, -3, -1,  0, -2, -3, -2,  1,  2, -1,  5,  0, -2, -1, -1, -1, -1,  1, -3, -1, -1, -4},\n    {-2, -3, -3, -3, -2, -3, -3, -3, -1,  0,  0, -3,  0,  6, -4, -2, -2,  1,  3, -1, -3, -3, -1, -4},\n    {-1, -2, -2, -1, -3, -1, -1, -2, -2, -3, -3, -1, -2, -4,  7, -1, -1, -4, -3, -2, -2, -1, -2, -4},\n    { 1, -1,  1,  0, -1,  0,  0,  0, -1, -2, -2,  0, -1, -2, -1,  4,  1, -3, -2, -2,  0,  0,  0, -4},\n    { 0, -1,  0, -1, -1, -1, -1, -2, -2, -1, -1, -1, -1, -2, -1,  1,  5, -2, -2,  0, -1, -1,  0, -4},\n    {-3, -3, -4, -4, -2, -2, -3, -2, -2, -3, -2, -3, -1,  1, -4, -3, -2, 11,  2, -3, -4, -3, -2, -4},\n    {-2, -2, -2, -3, -2, -1, -2, -3,  2, -1, -1, -2, -1,  3, -3, -2, -2,  2,  7, -1, -3, -2, -1, -4},\n    { 0, -3, -3, -3, -1, -2, -2, -3, -3,  3,  1, -2,  1, -1, -2, -2,  0, -3, -1,  4, -3, -2, -1, -4},\n    {-2, -1,  3,  4, -3,  0,  1, -1,  0, -3, -4,  0, -3, -3, -2,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    {-1,  0,  0,  1, -3,  3,  4, -2,  0, -3, -3,  1, -1, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -1, -1, -1, -2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2,  0,  0, -2, -1, -1, -1, -1, -1, -4},\n    {-4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4,  1}\n};\n\ndouble gettime() {\n    struct timeval t;\n    gettimeofday(&t,NULL);\n    return t.tv_sec+t.tv_usec*1e-6;\n}\n\n////////////////////////////////////////////////////////////////////////////////\n// Program main\n////////////////////////////////////////////////////////////////////////////////\n    int\nmain( int argc, char** argv) \n{\n\n    printf(\"WG size of kernel = %d \\n\", BLOCK_SIZE);\n\n    runTest( argc, argv);\n\n    return EXIT_SUCCESS;\n}\n\nvoid usage(int argc, char **argv)\n{\n    fprintf(stderr, \"Usage: %s <max_rows/max_cols> <penalty> \\n\", argv[0]);\n    fprintf(stderr, \"\\t<dimension>  - x and y dimensions\\n\");\n    fprintf(stderr, \"\\t<penalty> - penalty(positive integer)\\n\");\n    exit(1);\n}\n\nvoid runTest( int argc, char** argv) \n{\n    int max_rows, max_cols, penalty;\n    int *input_itemsets, *output_itemsets, *referrence;\n    int *matrix_cuda,  *referrence_cuda;\n    int size;\n\n\n    // the lengths of the two sequences should be able to divided by 16.\n    // And at current stage  max_rows needs to equal max_cols\n    if (argc == 3)\n    {\n        max_rows = atoi(argv[1]);\n        max_cols = atoi(argv[1]);\n        penalty = atoi(argv[2]);\n    }\n    else{\n        usage(argc, argv);\n    }\n\n    if(atoi(argv[1])%16!=0){\n        fprintf(stderr,\"The dimension values must be a multiple of 16\\n\");\n        exit(1);\n    }\n\n\n    max_rows = max_rows + 1;\n    max_cols = max_cols + 1;\n    referrence = (int *)malloc( max_rows * max_cols * sizeof(int) );\n    input_itemsets = (int *)malloc( max_rows * max_cols * sizeof(int) );\n    output_itemsets = (int *)malloc( max_rows * max_cols * sizeof(int) );\n\n\n    if (!input_itemsets)\n        fprintf(stderr, \"error: can not allocate memory\");\n\n    srand ( 7 );\n\n\n    for (int i = 0 ; i < max_cols; i++){\n        for (int j = 0 ; j < max_rows; j++){\n            input_itemsets[i*max_cols+j] = 0;\n        }\n    }\n\n    printf(\"Start Needleman-Wunsch\\n\");\n\n    for( int i=1; i< max_rows ; i++){    //please define your own sequence. \n        input_itemsets[i*max_cols] = rand() % 10 + 1;\n    }\n    for( int j=1; j< max_cols ; j++){    //please define your own sequence.\n        input_itemsets[j] = rand() % 10 + 1;\n    }\n\n\n    for (int i = 1 ; i < max_cols; i++){\n        for (int j = 1 ; j < max_rows; j++){\n            referrence[i*max_cols+j] = blosum62[input_itemsets[i*max_cols]][input_itemsets[j]];\n        }\n    }\n\n    for( int i = 1; i< max_rows ; i++)\n        input_itemsets[i*max_cols] = -i * penalty;\n    for( int j = 1; j< max_cols ; j++)\n        input_itemsets[j] = -j * penalty;\n\n\n    size = max_cols * max_rows;\n    cudaMalloc((void**)& referrence_cuda, sizeof(int)*size);\n    cudaMalloc((void**)& matrix_cuda, sizeof(int)*size);\n\n    cudaMemcpy(referrence_cuda, referrence, sizeof(int) * size, cudaMemcpyHostToDevice);\n    cudaMemcpy(matrix_cuda, input_itemsets, sizeof(int) * size, cudaMemcpyHostToDevice);\n\n    dim3 dimGrid;\n    dim3 dimBlock(BLOCK_SIZE, 1);\n    int block_width = ( max_cols - 1 )/BLOCK_SIZE;\n\n#ifdef  TIMING\n    gettimeofday(&tv_kernel_start, NULL);\n#endif\n\n    printf(\"Processing top-left matrix\\n\");\n    //process top-left matrix\n    for( int i = 1 ; i <= block_width ; i++){\n        dimGrid.x = i;\n        dimGrid.y = 1;\n        needle_cuda_shared_1<<<dimGrid, dimBlock>>>(referrence_cuda, matrix_cuda\n                ,max_cols, penalty, i, block_width); \n    }\n    printf(\"Processing bottom-right matrix\\n\");\n    //process bottom-right matrix\n    for( int i = block_width - 1  ; i >= 1 ; i--){\n        dimGrid.x = i;\n        dimGrid.y = 1;\n        needle_cuda_shared_2<<<dimGrid, dimBlock>>>(referrence_cuda, matrix_cuda\n                ,max_cols, penalty, i, block_width); \n    }\n\n#ifdef  TIMING\n    gettimeofday(&tv_kernel_end, NULL);\n    tvsub(&tv_kernel_end, &tv_kernel_start, &tv);\n    kernel_time += tv.tv_sec * 1000.0 + (float) tv.tv_usec / 1000.0;\n#endif\n\n    cudaMemcpy(output_itemsets, matrix_cuda, sizeof(int) * size, cudaMemcpyDeviceToHost);\n\n    //#define TRACEBACK\n#ifdef TRACEBACK\n\n    FILE *fpo = fopen(\"result.txt\",\"w\");\n    fprintf(fpo, \"print traceback value GPU:\\n\");\n\n    for (int i = max_rows - 2,  j = max_rows - 2; i>=0, j>=0;){\n        int nw, n, w, traceback;\n        if ( i == max_rows - 2 && j == max_rows - 2 )\n            fprintf(fpo, \"%d \", output_itemsets[ i * max_cols + j]); //print the first element\n        if ( i == 0 && j == 0 )\n            break;\n        if ( i > 0 && j > 0 ){\n            nw = output_itemsets[(i - 1) * max_cols + j - 1];\n            w  = output_itemsets[ i * max_cols + j - 1 ];\n            n  = output_itemsets[(i - 1) * max_cols + j];\n        }\n        else if ( i == 0 ){\n            nw = n = LIMIT;\n            w  = output_itemsets[ i * max_cols + j - 1 ];\n        }\n        else if ( j == 0 ){\n            nw = w = LIMIT;\n            n  = output_itemsets[(i - 1) * max_cols + j];\n        }\n        else{\n        }\n\n        //traceback = maximum(nw, w, n);\n        int new_nw, new_w, new_n;\n        new_nw = nw + referrence[i * max_cols + j];\n        new_w = w - penalty;\n        new_n = n - penalty;\n\n        traceback = maximum(new_nw, new_w, new_n);\n        if(traceback == new_nw)\n            traceback = nw;\n        if(traceback == new_w)\n            traceback = w;\n        if(traceback == new_n)\n            traceback = n;\n\n        fprintf(fpo, \"%d \", traceback);\n\n        if(traceback == nw )\n        {i--; j--; continue;}\n\n        else if(traceback == w )\n        {j--; continue;}\n\n        else if(traceback == n )\n        {i--; continue;}\n\n        else\n            ;\n    }\n\n    fclose(fpo);\n\n#endif\n\n    cudaFree(referrence_cuda);\n    cudaFree(matrix_cuda);\n\n    free(referrence);\n    free(input_itemsets);\n    free(output_itemsets);\n\n#ifdef  TIMING\n    printf(\"Exec: %f\\n\", kernel_time);\n#endif\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/needle.h",
    "content": "#ifdef RD_WG_SIZE_0_0\n\t#define BLOCK_SIZE RD_WG_SIZE_0_0\n#elif defined(RD_WG_SIZE_0)\n\t#define BLOCK_SIZE RD_WG_SIZE_0\n#elif defined(RD_WG_SIZE)\n\t#define BLOCK_SIZE RD_WG_SIZE\n#else\n\t#define BLOCK_SIZE 16\n#endif\n//#define TRACE\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/needle_kernel.cu",
    "content": "#include \"needle.h\"\n#include <stdio.h>\n\n\n#define SDATA( index)      CUT_BANK_CHECKER(sdata, index)\n\n__device__ __host__ int \nmaximum( int a,\n        int b,\n        int c){\n\n    int k;\n    if( a <= b )\n        k = b;\n    else \n        k = a;\n\n    if( k <=c )\n        return(c);\n    else\n        return(k);\n\n}\n\n__global__ void\nneedle_cuda_shared_1(  int* referrence,\n        int* matrix_cuda, \n        int cols,\n        int penalty,\n        int i,\n        int block_width) \n{\n    int bx = blockIdx.x;\n    int tx = threadIdx.x;\n\n    int b_index_x = bx;\n    int b_index_y = i - 1 - bx;\n\n    int index   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + tx + ( cols + 1 );\n    int index_n   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + tx + ( 1 );\n    int index_w   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + ( cols );\n    int index_nw =  cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x;\n\n    __shared__  int temp[BLOCK_SIZE+1][BLOCK_SIZE+1];\n    __shared__  int ref[BLOCK_SIZE][BLOCK_SIZE];\n\n    if (tx == 0)\n        temp[tx][0] = matrix_cuda[index_nw];\n\n\n    for ( int ty = 0 ; ty < BLOCK_SIZE ; ty++)\n        ref[ty][tx] = referrence[index + cols * ty];\n\n    __syncthreads();\n\n    temp[tx + 1][0] = matrix_cuda[index_w + cols * tx];\n\n    __syncthreads();\n\n    temp[0][tx + 1] = matrix_cuda[index_n];\n\n    __syncthreads();\n\n\n    for( int m = 0 ; m < BLOCK_SIZE ; m++){\n\n        if ( tx <= m ){\n\n            int t_index_x =  tx + 1;\n            int t_index_y =  m - tx + 1;\n\n            temp[t_index_y][t_index_x] = maximum( temp[t_index_y-1][t_index_x-1] + ref[t_index_y-1][t_index_x-1],\n                    temp[t_index_y][t_index_x-1]  - penalty, \n                    temp[t_index_y-1][t_index_x]  - penalty);\n\n\n\n        }\n\n        __syncthreads();\n\n    }\n\n    for( int m = BLOCK_SIZE - 2 ; m >=0 ; m--){\n\n        if ( tx <= m){\n\n            int t_index_x =  tx + BLOCK_SIZE - m ;\n            int t_index_y =  BLOCK_SIZE - tx;\n\n            temp[t_index_y][t_index_x] = maximum( temp[t_index_y-1][t_index_x-1] + ref[t_index_y-1][t_index_x-1],\n                    temp[t_index_y][t_index_x-1]  - penalty, \n                    temp[t_index_y-1][t_index_x]  - penalty);\n\n        }\n\n        __syncthreads();\n    }\n\n    for ( int ty = 0 ; ty < BLOCK_SIZE ; ty++)\n        matrix_cuda[index + ty * cols] = temp[ty+1][tx+1];\n\n}\n\n\n__global__ void\nneedle_cuda_shared_2(  int* referrence,\n        int* matrix_cuda, \n\n        int cols,\n        int penalty,\n        int i,\n        int block_width) \n{\n\n    int bx = blockIdx.x;\n    int tx = threadIdx.x;\n\n    int b_index_x = bx + block_width - i  ;\n    int b_index_y = block_width - bx -1;\n\n    int index   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + tx + ( cols + 1 );\n    int index_n   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + tx + ( 1 );\n    int index_w   = cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x + ( cols );\n    int index_nw =  cols * BLOCK_SIZE * b_index_y + BLOCK_SIZE * b_index_x;\n\n    __shared__  int temp[BLOCK_SIZE+1][BLOCK_SIZE+1];\n    __shared__  int ref[BLOCK_SIZE][BLOCK_SIZE];\n\n    for ( int ty = 0 ; ty < BLOCK_SIZE ; ty++)\n        ref[ty][tx] = referrence[index + cols * ty];\n\n    __syncthreads();\n\n    if (tx == 0)\n        temp[tx][0] = matrix_cuda[index_nw];\n\n\n    temp[tx + 1][0] = matrix_cuda[index_w + cols * tx];\n\n    __syncthreads();\n\n    temp[0][tx + 1] = matrix_cuda[index_n];\n\n    __syncthreads();\n\n\n    for( int m = 0 ; m < BLOCK_SIZE ; m++){\n\n        if ( tx <= m ){\n\n            int t_index_x =  tx + 1;\n            int t_index_y =  m - tx + 1;\n\n            temp[t_index_y][t_index_x] = maximum( temp[t_index_y-1][t_index_x-1] + ref[t_index_y-1][t_index_x-1],\n                    temp[t_index_y][t_index_x-1]  - penalty, \n                    temp[t_index_y-1][t_index_x]  - penalty);\t  \n\n        }\n\n        __syncthreads();\n\n    }\n\n\n    for( int m = BLOCK_SIZE - 2 ; m >=0 ; m--){\n\n        if ( tx <= m){\n\n            int t_index_x =  tx + BLOCK_SIZE - m ;\n            int t_index_y =  BLOCK_SIZE - tx;\n\n            temp[t_index_y][t_index_x] = maximum( temp[t_index_y-1][t_index_x-1] + ref[t_index_y-1][t_index_x-1],\n                    temp[t_index_y][t_index_x-1]  - penalty, \n                    temp[t_index_y-1][t_index_x]  - penalty);\n\n\n        }\n\n        __syncthreads();\n    }\n\n\n    for ( int ty = 0 ; ty < BLOCK_SIZE ; ty++)\n        matrix_cuda[index + ty * cols] = temp[ty+1][tx+1];\n\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/run",
    "content": "./needle 2048 10\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/baselines/gpu/timing.h",
    "content": "#ifndef __TIMING_H__\n#define __TIMING_H__\n\n#include <sys/time.h>\n\nvoid time_measure_start(struct timeval *tv);\nvoid time_measure_end(struct timeval *tv);\n\n/* tvsub: ret = x - y. */\nstatic inline void tvsub(struct timeval *x,\n\t\t\t\t\t\t struct timeval *y,\n\t\t\t\t\t\t struct timeval *ret)\n{\n\tret->tv_sec = x->tv_sec - y->tv_sec;\n\tret->tv_usec = x->tv_usec - y->tv_usec;\n\tif (ret->tv_usec < 0) {\n\t\tret->tv_sec--;\n\t\tret->tv_usec += 1000000;\n\t}\n}\n\n#endif"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/dpu/task.c",
    "content": "/**\n* Needleman-Wunsch with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n    unsigned int tasklet_id = me();\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n    uint32_t nblocks = DPU_INPUT_ARGUMENTS.nblocks;\n    uint32_t active_blocks = DPU_INPUT_ARGUMENTS.active_blocks;\n    uint32_t penalty = DPU_INPUT_ARGUMENTS.penalty;\n#if PRINT\n    printf(\"tasklet_id = %d, nblocks = %d \\n\", tasklet_id, nblocks);\n#endif\n\t\n    uint32_t mram_base_addr_input_itemsets = (uint32_t) (DPU_MRAM_HEAP_POINTER);\n    uint32_t mram_base_addr_ref = (uint32_t) (DPU_MRAM_HEAP_POINTER + nblocks * (BL+1) * (BL+2) * sizeof(int32_t));\n    if (nblocks != active_blocks)\n        mram_base_addr_ref = (uint32_t) (DPU_MRAM_HEAP_POINTER + active_blocks * (BL+1) * (BL+2) * sizeof(int32_t));\n\n    int32_t *cache_input = mem_alloc((BL_IN+1) * (BL_IN+2) * sizeof(int32_t));\n    int32_t *cache_ref = mem_alloc(BL_IN * BL_IN * sizeof(int32_t));\n    uint32_t REP = BL/BL_IN;\n    uint32_t chunks;\n    uint32_t mod;\n    uint32_t start;\n    uint32_t addr_input;\n    uint32_t addr_ref;\n    uint32_t cache_input_offset;\n\n    for (uint32_t bl = 0; bl < nblocks; bl++) {\n\n        // Top-left computation\n        for(uint32_t blk = 0; blk <= REP; blk++) {\n            \n            // Partition chunks/subblocks of the diagonal to tasklets \n            chunks = blk / NR_TASKLETS; \n            mod = blk % NR_TASKLETS;\n            if (tasklet_id < mod)\n                chunks++;\n            if (mod > 0) {\n                if(tasklet_id < mod)\n                    start = tasklet_id * chunks;\n                else\n                    start = mod * (chunks + 1) + (tasklet_id - mod) * chunks;\n            } else\n                start = tasklet_id * chunks;\n            \n            // Compute all assigned chunks  \n            for (uint32_t bl_indx = 0; bl_indx < chunks; bl_indx++) {\n                int t_index_x = start + bl_indx;\n                int t_index_y = blk - 1 - t_index_x; \n                \n                // Move input from MRAM to WRAM\n                addr_input =  mram_base_addr_input_itemsets + (t_index_x * (BL+2) * BL_IN * sizeof(int32_t)) + (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = (BL_IN+2);\n                mram_read((__mram_ptr void const *) addr_input, (void *) cache_input, (BL_IN+2) * sizeof(int32_t)); \n                addr_input += ((BL+2) * sizeof(int32_t));\n                for (int i = 1; i < BL_IN + 1; i++) {\n                    mram_read((__mram_ptr void const *) addr_input, (void *) (cache_input + cache_input_offset), (2) * sizeof(int32_t)); \n                    cache_input_offset += (BL_IN+2); \n                    addr_input += ((BL+2) * sizeof(int32_t));\n                }\n\n                addr_ref = mram_base_addr_ref + (t_index_x * BL * BL_IN * sizeof(int32_t)) +  (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = 0;\n                for (int i = 0; i < BL_IN; i++) {\n                    mram_read((__mram_ptr void const *) addr_ref, (void *) (cache_ref + cache_input_offset), (BL_IN) * sizeof(int32_t)); \n                    cache_input_offset += BL_IN; \n                    addr_ref += (BL * sizeof(int32_t));\n                }\n\n                // Computation\n                for (uint32_t i = 1; i < BL_IN + 1; i++) {\n                    for (uint32_t j = 1; j < BL_IN + 1; j++) {\n                        cache_input[i*(BL_IN+2) + j] = maximum(cache_input[(i-1)*(BL_IN+2) + j - 1] + cache_ref[(i-1)*BL_IN + j-1],\n                                                cache_input[i*(BL_IN+2) + j - 1] - penalty,\n                                                cache_input[(i-1)*(BL_IN+2) + j] - penalty);\n                    }\n                }\n\n                // Move output from WRAM to MRAM\n                addr_input =  mram_base_addr_input_itemsets + (t_index_x * (BL+2) * BL_IN * sizeof(int32_t)) + (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = (BL_IN+2);\n                addr_input += ((BL+2) * sizeof(int32_t));\n                for (int i = 1; i < BL_IN + 1; i++) {\n                    mram_write((cache_input + cache_input_offset), (__mram_ptr void *)  addr_input, (BL_IN+2) * sizeof(int32_t)); \n                    cache_input_offset += (BL_IN+2); \n                    addr_input += ((BL+2) * sizeof(int32_t));\n                }\n\n            }\n            \n            barrier_wait(&my_barrier);\n        }\n       \n        // Bottom-right computation\n        for(uint32_t blk = 2; blk <= REP; blk++) {\n            // Partition chunks/subblocks of the diagonal to tasklets \n            chunks = (REP - blk + 1) / NR_TASKLETS; \n            mod = (REP - blk + 1) % NR_TASKLETS;\n            if (tasklet_id < mod)\n                chunks++;\n            if (mod > 0){\n                if(tasklet_id < mod)\n                    start = tasklet_id * chunks;\n                else\n                    start = mod * (chunks + 1) + (tasklet_id - mod) * chunks;\n            } else\n                start = tasklet_id * chunks;\n\n            // Compute all assigned chunks  \n            for (uint32_t bl_indx = 0; bl_indx < chunks; bl_indx++) {\n                int t_index_x = blk - 1 + start + bl_indx;\n                int t_index_y = REP + blk - 2 - t_index_x; \n\n                // Move input from MRAM to WRAM\n                addr_input =  mram_base_addr_input_itemsets + (t_index_x * (BL+2) * BL_IN * sizeof(int32_t)) + (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = (BL_IN+2);\n                mram_read((__mram_ptr void const *) addr_input, (void *) cache_input, (BL_IN+2) * sizeof(int32_t)); \n                addr_input += ((BL+2) * sizeof(int32_t));\n                for (int i = 1; i < BL_IN + 1; i++) {\n                    mram_read((__mram_ptr void const *) addr_input, (void *) (cache_input + cache_input_offset), (2) * sizeof(int32_t)); \n                    cache_input_offset += (BL_IN+2); \n                    addr_input += ((BL+2) * sizeof(int32_t));\n                }\n\n                addr_ref = mram_base_addr_ref + (t_index_x * BL * BL_IN * sizeof(int32_t)) +  (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = 0;\n                for (int i = 0; i < BL_IN; i++) {\n                    mram_read((__mram_ptr void const *) addr_ref, (void *) (cache_ref + cache_input_offset), (BL_IN) * sizeof(int32_t)); \n                    cache_input_offset += BL_IN; \n                    addr_ref += (BL * sizeof(int32_t));\n                }\n\n\n                // Computation\n                for (int i = 1; i < BL_IN + 1; i++) {\n                    for (int j = 1; j < BL_IN + 1; j++) {\n                        cache_input[i*(BL_IN+2) + j] = maximum(cache_input[(i-1)*(BL_IN+2) + j - 1] + cache_ref[(i-1)*BL_IN + j-1],\n                                                cache_input[i*(BL_IN+2) + j - 1] - penalty,\n                                                cache_input[(i-1)*(BL_IN+2) + j] - penalty);\n                    }\n                }\n\n                // Move output from WRAM to MRAM\n                addr_input =  mram_base_addr_input_itemsets + (t_index_x * (BL+2) * BL_IN * sizeof(int32_t)) + (t_index_y * BL_IN * sizeof(int32_t));\n                cache_input_offset = (BL_IN+2);\n                addr_input += ((BL+2) * sizeof(int32_t));\n                for (int i = 1; i < BL_IN + 1; i++) {\n                    mram_write(cache_input + cache_input_offset, (__mram_ptr void *)  addr_input, (BL_IN+2) * sizeof(int32_t)); \n                    cache_input_offset += (BL_IN+2); \n                    addr_input += ((BL+2) * sizeof(int32_t));\n                }\n\n            }\n            \n            barrier_wait(&my_barrier);\n\n        }\n\t\t\n        mram_base_addr_input_itemsets += ((BL+1) * (BL+2) * sizeof(int32_t));\n        mram_base_addr_ref += (BL * BL * sizeof(int32_t)); \n    }\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/host/app.c",
    "content": "/**\n* app.c\n* NW Host Application Source File \n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/nw_dpu\"\n#endif\n\n// Traceback in the host\n#if PRINT_FILE\nstatic void traceback(int* traceback_output, char *file, int32_t *input_itemsets, int32_t *reference, unsigned int max_rows, unsigned int max_cols, unsigned int penalty) {\n    FILE *fpo = fopen(file, \"w\"); // Use to print to an output file\n#else\nstatic void traceback(int* traceback_output, int32_t *input_itemsets, int32_t *reference, unsigned int max_rows, unsigned int max_cols, unsigned int penalty) {\n#endif\n\n    int k = 0;\n    for (int i = max_rows - 2,  j = max_rows - 2; i>=0 && j>=0;) {\n        int nw = 0, n = 0, w = 0, traceback = 0;\n#if PRINT_FILE\n        if ( i == (int)max_rows - 2 && j == (int)max_rows - 2 )\n            fprintf(fpo, \"%d \", input_itemsets[ i * max_cols + j]); //print the first element\n#endif\n\n        if (i == 0 && j == 0)\n            break;\n        if (i > 0 && j > 0) {\n            nw = input_itemsets[(i - 1) * max_cols + j - 1];\n            w  = input_itemsets[i * max_cols + j - 1];\n            n  = input_itemsets[(i - 1) * max_cols + j];\n        } else if (i == 0) {\n            nw = n = LIMIT;\n            w  = input_itemsets[ i * max_cols + j - 1 ];\n        } else if (j == 0) {\n            nw = w = LIMIT;\n            n  = input_itemsets[(i - 1) * max_cols + j];\n        } else {\n            ;\n        }\n\n        int new_nw, new_w, new_n;\n        new_nw = nw + reference[i * max_cols + j];\n        new_w = w - penalty;\n        new_n = n - penalty;\n\n        traceback = maximum(new_nw, new_w, new_n);\n        if (traceback == new_nw)\n            traceback = nw;\n        if (traceback == new_w)\n            traceback = w;\n        if (traceback == new_n)\n            traceback = n;\n\n#if PRINT_FILE\n\tfprintf(fpo, \"%d \", traceback);\n#endif \n \ttraceback_output[k++] = traceback;\n\n\tif (traceback == nw) { \n            i--; \n            j--; \n            continue;\n        } else if (traceback == w) {\n            j--; \n            continue;\n        } else if (traceback == n) {\n            i--; \n            continue;\n        } else {\n            ;\n        }\n    }\n\n    return;\n}\n\n// Compute output in the host\nstatic void nw_host(int32_t *input_itemsets, int32_t *reference, uint64_t max_cols, unsigned int penalty) {\n\n    int32_t *input_itemsets_l = (int32_t *) malloc((BL + 1) * (BL + 1) * sizeof(int32_t));\n    int32_t *reference_l = (int32_t *) malloc((BL * BL) * sizeof(int32_t));\n\n\n    // top-left\n    for (uint64_t blk = 1; blk <= (max_cols-1)/BL; blk++) {\n        for (uint64_t b_index_x = 0; b_index_x < blk; b_index_x++) {\n            uint64_t b_index_y = blk - 1 - b_index_x;\n\n            for (uint64_t i = 0; i < BL; i++){\n                for (uint64_t j = 0; j < BL; j++) {\n                    reference_l[i*BL + j] = reference[(max_cols-1) * (b_index_y*BL + i) + b_index_x*BL + j];\n                }\n            }\n\n            for (uint64_t i = 0; i < BL + 1; i++){\n                for (uint64_t j = 0; j < BL + 1; j++) {\n                    input_itemsets_l[i*(BL + 1) + j] = input_itemsets[max_cols*(b_index_y*BL + i) + b_index_x*BL + j];\n                }\n            }\n\n            // Computation\n            for (uint64_t i = 1; i < BL + 1; i++) {\n                for (uint64_t j = 1; j < BL + 1; j++) {\n                    input_itemsets_l[i*(BL + 1) + j] = maximum(input_itemsets_l[(i-1)*(BL+1) + j - 1] + reference_l[(i-1)*BL + j - 1],\n                            input_itemsets_l[i*(BL+1) + j - 1] - penalty,\n                            input_itemsets_l[(i-1)*(BL+1) + j] - penalty);\n                }\n            }\n\n            for (uint64_t i = 0; i < BL; i++) {\n                for (uint64_t j = 0; j < BL; j++) {\n                    input_itemsets[max_cols*(b_index_y*BL + i + 1) + b_index_x*BL + j + 1] = input_itemsets_l[(i+1)*(BL+1) + j + 1];\n                }\n            }\n\n        }\n\n    }\n\n    // bottom-right \n    for (uint64_t blk = 2; blk <= (max_cols-1)/BL; blk++) {\n        for (uint64_t b_index_x = blk - 1; b_index_x < (max_cols-1)/BL; b_index_x++) {\n            uint64_t b_index_y = (max_cols-1)/BL + blk - 2 - b_index_x;\n\n            for (uint64_t i = 0; i < BL; i++){\n                for (uint64_t j = 0; j < BL; j++) {\n                    reference_l[i*BL + j] = reference[(max_cols-1)*(b_index_y*BL + i) + b_index_x*BL + j];\n                }\n            }\n\n            for (uint64_t i = 0; i < BL + 1; i++){\n                for (uint64_t j = 0; j < BL + 1; j++) {\n                    input_itemsets_l[i*(BL + 1) + j] = input_itemsets[max_cols*(b_index_y*BL + i) + b_index_x*BL + j];\n                }\n            }\n\n            // Computation\n            for (uint64_t i = 1; i < BL + 1; i++) {\n                for (uint64_t j = 1; j < BL + 1; j++) {\n                    input_itemsets_l[i*(BL + 1) + j] = maximum(input_itemsets_l[(i-1)*(BL+1) + j - 1] + reference_l[(i-1)*BL + j - 1],\n                            input_itemsets_l[i*(BL+1) + j - 1] - penalty,\n                            input_itemsets_l[(i-1)*(BL+1) + j] - penalty);\n                }\n            }\n\n            for (uint64_t i = 0; i < BL; i++) {\n                for (uint64_t j = 0; j < BL; j++) {\n                    input_itemsets[max_cols*(b_index_y*BL + i + 1) + b_index_x*BL + j + 1] = input_itemsets_l[(i+1)*(BL+1) + j + 1];\n                }\n            }\n\n        }\n\n    }\n\n\n    free(input_itemsets_l);\n    free(reference_l);\n    return;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus, max_dpus;\n\n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n    printf(\"Allocated %d TASKLET(s) per DPU\\n\", NR_TASKLETS);\n#if DYNAMIC\n    max_dpus = nr_of_dpus;\n#endif\n\n    uint64_t max_rows = p.max_rows + 1;\n    uint64_t max_cols = p.max_rows + 1;\n    unsigned int penalty = p.penalty;\n    int32_t *reference = (int32_t *) malloc(max_rows * max_cols * sizeof(int32_t));\n    int32_t *input_itemsets_host = (int32_t *) malloc(max_rows * max_cols * sizeof(int32_t));\n    int32_t *input_itemsets = (int32_t *) malloc((max_rows+1) * (max_cols+1) * sizeof(int32_t));\n    dpu_arguments_t *input_args = (dpu_arguments_t *) malloc(nr_of_dpus * sizeof(dpu_arguments_t));\n    printf(\"Max size %d\\n\", p.max_rows);\n\n    // Traceback output\n    int32_t* traceback_output = (int32_t *) malloc((max_rows + max_cols) * sizeof(int32_t));\n    int32_t* traceback_output_host = (int32_t *) malloc((max_rows + max_cols) * sizeof(int32_t));\n    memset(traceback_output, 0, (max_rows + max_cols) * sizeof(int32_t));\n    memset(traceback_output_host, 0, (max_rows + max_cols) * sizeof(int32_t));\n\n    // This array is used for dummy/stale CPU-DPU transfers\n    int32_t *dummy = (int32_t *) malloc(nr_of_dpus * (BL+2) * sizeof(int32_t));\n    unsigned int blocks_per_dpu;\n    unsigned int mram_offset = 0;\n\n    // Timer\n    Timer timer; \n    Timer long_diagonal_timer; \n#if ENERGY\n    double tacc_energy, tacc_time, tavg_time;\n    double tavg_energy=0;\n#endif\n\n    for (unsigned int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Initializing inputs are needed at each iteration\n        // Initialize input itemsets\n        for(unsigned int i = 0; i < max_rows; i++) {\n            for (unsigned int j = 0; j < max_cols; j++) {\n                input_itemsets_host[i * max_cols + j] = 0; \n            }\n        }\n\n        for(unsigned int i = 0; i <= max_rows; i++) {\n            for (unsigned int j = 0; j <= max_cols; j++) {\n                input_itemsets[i * (max_cols+1) + j] = 0; \n            }\n        }\n\n        // Define random sequences\n        srand(7);\n        for (unsigned int i = 1; i < max_rows; i++) {\n            input_itemsets_host[i * max_cols] = rand() % 10 + 1;\n        }\n\n        for (unsigned int j = 1; j < max_cols; j++) {\n            input_itemsets_host[j] = rand() % 10 + 1;\n        }   \n\n        for (unsigned int i = 0; i < max_rows-1; i++) {\n            for (unsigned int j = 0; j < max_cols-1; j++) {\n                reference[i * (max_cols-1) + j] = blosum62[input_itemsets[(i+1) * max_cols]][input_itemsets[j+1]];\n            }\n        }\n\n        for (unsigned int i = 1; i < max_rows; i++) {\n            input_itemsets_host[i * max_cols] = -i * penalty;\n            input_itemsets[i * (max_cols+1)] = -i * penalty;\n        }\n\n        for (unsigned int j = 1; j < max_cols; j++) {\n            input_itemsets_host[j] = -j * penalty;\n            input_itemsets[j] = -j * penalty;\n        }\n\n        if (rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        // Computation on host CPU\n        nw_host(input_itemsets_host, reference, max_cols, penalty);\n\n        // Print host output\n#if PRINT_FILE\n        if (rep >= p.n_warmup) {\n            char *host_file = \"./bin/host_output.txt\";\n            traceback(traceback_output_host, host_file, input_itemsets_host, reference, max_rows, max_cols, penalty);\n        }\n#endif\n        if (rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        // Top-left computation on DPUs\n        for (unsigned int blk = 1; blk <= (max_cols-1)/BL; blk++) {\n#if DYNAMIC \n            // If nr_of_blocks are lower than max_dpus,\n            // set nr_of_dpus to be equal with nr_of_blocks\n            unsigned nr_of_blocks = blk;\n            if (nr_of_blocks < max_dpus) {\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(nr_of_blocks, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n            } else if (nr_of_dpus == max_dpus) {\n                ;\n            } else {\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(max_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n            }\n#if PRINT\n            printf(\"Allocated %d DPU(s) for %d (%d) blocks\\n\", nr_of_dpus, nr_of_blocks, blk);\n#endif\n#endif\n\n            // Copy data to DPUs\n            unsigned int i=0;\n            DPU_FOREACH(dpu_set, dpu, i) {\n                unsigned int blocks_per_dpu = blk / nr_of_dpus;\n                unsigned int active_blocks_per_dpu = blk / nr_of_dpus;\n                unsigned int rest_blocks = blk % nr_of_dpus;\n                if(i < rest_blocks)\n                    blocks_per_dpu++;\n\n                if(rest_blocks != 0)\n                    active_blocks_per_dpu++;\n\n                // Copy input arguments to dpu\n                input_args[i].nblocks = blocks_per_dpu;\n                input_args[i].active_blocks = active_blocks_per_dpu;\n                input_args[i].penalty = penalty;\n                DPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n            } \n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n            // Copy itemsets to DPUs\n            blocks_per_dpu = blk / nr_of_dpus;\n            if (blk % nr_of_dpus != 0)\n                blocks_per_dpu++;\n            mram_offset = 0;\n\n\n            if (rep >= p.n_warmup) {\n                if ((max_cols-1)/BL == 1) \n                    start(&timer, 2, rep - p.n_warmup + blk - 1);\n                else \n                    start(&timer, 1, rep - p.n_warmup + blk - 1);\n                \n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    if ((max_cols-1)/BL == 1) \n                        start(&long_diagonal_timer, 2, rep - p.n_warmup);\n                    else \n                        start(&long_diagonal_timer, 1, rep - p.n_warmup);\n                }\n            }\n\n#if PRINT\n            uint64_t total_dpu_memory = 0;\n            total_dpu_memory = (uint64_t) blocks_per_dpu * (BL+1) * (BL+2) * sizeof(int32_t) + (uint64_t) blocks_per_dpu * BL * BL * sizeof(int32_t);\n            printf(\"Total memory allocated in each DPU %u bytes\\n\", total_dpu_memory);\n#endif\n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL + 1; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = blk / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = blk % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t input_itemsets_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= blk) {\n                            dpu_pointer = dummy;\n                            input_itemsets_offset = 0;  \n                        } else {\n                            uint64_t b_index_x =  prev_block_index + bl_indx;\n                            uint64_t b_index_y = blk - 1 - b_index_x;\n                            dpu_pointer = input_itemsets;\n                            input_itemsets_offset = b_index_y * (max_cols+1) * BL + b_index_x * BL + bl * (max_cols + 1);  \n                        }\n\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + input_itemsets_offset));\n                    }\n\n                    if (bl == 0) \n                        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, (BL+2) * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    else\n                        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, 2 * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += ((BL+2) * sizeof(int32_t));\n\n                }\n            }\n            if (rep >= p.n_warmup) {\n                if ((max_cols-1)/BL == 1) \n                    stop(&timer, 2);\n                else\n                    stop(&timer, 1);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    if ((max_cols-1)/BL == 1) \n                        stop(&long_diagonal_timer, 2);\n                    else \n                        stop(&long_diagonal_timer, 1);\n                }\n            }\n\n\n            if (rep >= p.n_warmup) {\n                start(&timer, 2, rep - p.n_warmup + blk - 1);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    start(&long_diagonal_timer, 2, rep - p.n_warmup);\n                }\n            }\n            // Copy reference to DPUs\n            mram_offset = blocks_per_dpu * (BL+1) * (BL+2) * sizeof(int32_t); \n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = blk / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = blk % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t reference_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= blk) {\n                            dpu_pointer = dummy;\n                            reference_offset = 0;  \n                        } else {\n                            uint64_t b_index_x =  prev_block_index + bl_indx;\n                            uint64_t b_index_y = blk - 1 - b_index_x;\n                            dpu_pointer = reference;\n                            reference_offset = b_index_y * (max_cols - 1) * BL + b_index_x * BL + bl * (max_cols - 1);  \n                        }\n\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + reference_offset));\n                    }\n                    DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, BL * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += BL * sizeof(int32_t);\n\n                }\n            }\n            if (rep >= p.n_warmup) {\n                stop(&timer, 2);\n                if (blk == ((max_cols-1)/BL)) {\n                    stop(&long_diagonal_timer, 2);\n                }\n            }\n\n#if ENERGY\n            if (rep >= p.n_warmup) {\n                DPU_ASSERT(dpu_probe_start(&probe));\n            }\n#endif\n            if (rep >= p.n_warmup) {\n                start(&timer, 3, rep - p.n_warmup + blk - 1);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    start(&long_diagonal_timer, 3, rep - p.n_warmup);\n                }\n            }\n            // Launch kernel on DPUs\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if (rep >= p.n_warmup) {\n                stop(&timer, 3);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    stop(&long_diagonal_timer, 3);\n                }\n            }\n#if ENERGY\n            if (rep >= p.n_warmup) {\n                DPU_ASSERT(dpu_probe_stop(&probe));\n            }\n#endif\n\n#if ENERGY\n    \t    double acc_energy, avg_energy, acc_time, avg_time;\n\t        DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n    \t    tavg_energy += avg_energy;\n#endif\n\n#if PRINT\n            // Display DPU Logs\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n            }\n#endif\n\n            if (rep >= p.n_warmup) {\n                start(&timer, 4, rep - p.n_warmup + blk - 1);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    start(&long_diagonal_timer, 4, rep - p.n_warmup);\n                }\n            }\n            // Retrieve results\n            // Copy output result to Host CPU\n            mram_offset = 0;\n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL + 1; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = blk / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = blk % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t input_itemsets_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= blk) {\n                            dpu_pointer = dummy;\n                            input_itemsets_offset = 0;  \n                        } else {\n                            uint64_t b_index_x =  prev_block_index + bl_indx;\n                            uint64_t b_index_y = blk - 1 - b_index_x;\n                            dpu_pointer = input_itemsets;\n                            input_itemsets_offset = b_index_y * (max_cols+1) * BL + b_index_x * BL + bl * (max_cols + 1);  \n                        }\n\n                        if (bl == 0) // Skip the first row of the block\n                            continue;\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + input_itemsets_offset));\n\n                    }\n                    if (bl == 0) {\n                        mram_offset += (BL+2) * sizeof(int32_t);\n                        continue;\n                    }\n                    DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, (BL+2) * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += (BL+2) * sizeof(int32_t);\n\n                }\n            }\n            if (rep >= p.n_warmup) {\n                stop(&timer, 4);\n                // Timer for longest diagonal\n                if (blk == ((max_cols-1)/BL)) {\n                    stop(&long_diagonal_timer, 4);\n                }\n            }\n        }\n\n\n        // Bottom-right computation on DPUs\n        for (unsigned int blk = 2; blk <= (max_cols-1)/BL; blk++) {\n#if DYNAMIC\n            // If nr_of_blocks are lower than max_dpus,\n            // set nr_of_dpus to be equal with nr_of_blocks\n            unsigned nr_of_blocks = (((max_cols-1)/BL) - blk + 1);\n            if (nr_of_blocks < max_dpus) {\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(nr_of_blocks, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n            } else if (nr_of_dpus == max_dpus) {\n                ;\n            } else {\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(max_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n            }\n#if PRINT\n            printf(\"Allocated %d DPU(s) for %d (%d) blocks\\n\", nr_of_dpus, nr_of_blocks, (((max_cols-1)/BL) - blk + 1));\n#endif\n#endif\n\n            // Copy data to DPUs\n            unsigned int i=0;\n            DPU_FOREACH(dpu_set, dpu, i) {\n                unsigned int blocks_per_dpu = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n                unsigned int active_blocks_per_dpu = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n                unsigned int rest_blocks = (((max_cols-1)/BL) - blk + 1) % nr_of_dpus;\n                if(i < rest_blocks)\n                    blocks_per_dpu++;\n\n                if(rest_blocks != 0)\n                    active_blocks_per_dpu++;\n\n                // Copy input arguments to dpu\n                input_args[i].nblocks = blocks_per_dpu;\n                input_args[i].active_blocks = active_blocks_per_dpu;\n                input_args[i].penalty = penalty;\n                DPU_ASSERT(dpu_prepare_xfer(dpu, input_args + i));\n            } \n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(dpu_arguments_t), DPU_XFER_DEFAULT));\n\n            if (rep >= p.n_warmup)\n                start(&timer, 1, rep - p.n_warmup + blk - 1);\n            // Copy itemsets to DPUs\n            unsigned int blocks_per_dpu = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n            if ((((max_cols-1)/BL) - blk + 1) % nr_of_dpus != 0)\n                blocks_per_dpu++;\n#if PRINT\n            uint64_t total_dpu_memory = 0;\n            total_dpu_memory = (uint64_t) blocks_per_dpu * (BL+1) * (BL+2) * sizeof(int32_t) + (uint64_t) blocks_per_dpu * BL * BL * sizeof(int32_t);\n            printf(\"Total memory allocated in each DPU %u bytes\\n\", total_dpu_memory);\n#endif\n            unsigned int mram_offset = 0;\n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL + 1; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = (((max_cols-1)/BL) - blk + 1) % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t input_itemsets_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= (((max_cols-1)/BL) - blk + 1)) {\n                            dpu_pointer = dummy;\n                            input_itemsets_offset = 0;  \n                        } else {\n                            uint64_t b_index_x = blk - 1 + prev_block_index + bl_indx;\n                            uint64_t b_index_y = (max_cols-1)/BL + blk - 2 - b_index_x;\n                            dpu_pointer = input_itemsets;\n                            input_itemsets_offset = b_index_y * (max_cols+1) * BL + b_index_x * BL + bl * (max_cols + 1);  \n                        }\n\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + input_itemsets_offset));\n                    }\n\n                    if (bl == 0) \n                        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, (BL+2) * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    else\n                        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, 2 * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += (BL+2) * sizeof(int32_t);\n\n                }\n            }\n            if (rep >= p.n_warmup)\n                stop(&timer, 1);\n\n\n            if (rep >= p.n_warmup)\n                start(&timer, 2, rep - p.n_warmup + blk - 1);\n            // Copy reference to DPUs\n            mram_offset = blocks_per_dpu * (BL+1) * (BL+2) * sizeof(int32_t); \n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = (((max_cols-1)/BL) - blk + 1) % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t reference_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= (((max_cols-1)/BL) - blk + 1)) {\n                            dpu_pointer = dummy;\n                            reference_offset = 0;  \n                        } else {\n                            uint64_t b_index_x = blk - 1 + prev_block_index + bl_indx;\n                            uint64_t b_index_y = (max_cols-1)/BL + blk - 2 - b_index_x;\n                            dpu_pointer = reference;\n                            reference_offset = b_index_y * (max_cols - 1) * BL + b_index_x * BL + bl * (max_cols - 1);  \n                        }\n\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + reference_offset));\n                    }\n\n                    DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, BL * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += BL * sizeof(int32_t);\n\n                }\n            }\n            if (rep >= p.n_warmup)\n                stop(&timer, 2);\n\n#if ENERGY\n            if (rep >= p.n_warmup) {\n                DPU_ASSERT(dpu_probe_start(&probe));\n            }\n#endif\n            if (rep >= p.n_warmup)\n                start(&timer, 3, rep - p.n_warmup + blk - 1); // Do not re-initialize the counter\n            // Launch kernel on DPUs\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if (rep >= p.n_warmup)\n                stop(&timer, 3);\n#if ENERGY\n            if (rep >= p.n_warmup) {\n                DPU_ASSERT(dpu_probe_stop(&probe));\n            }\n#endif\n\n#if ENERGY\n    \t    double acc_energy, avg_energy, acc_time, avg_time;\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n    \t    DPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n    \t    tavg_energy += avg_energy;\n#endif\n\n#if PRINT\n            // Display DPU Logs\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n            }\n#endif\n\n\n            if (rep >= p.n_warmup)\n                start(&timer, 4, rep - p.n_warmup + blk - 1);\n            // Retrieve results\n            // Copy output result to Host CPU\n            mram_offset = 0;\n            for (unsigned int bl_indx = 0; bl_indx < blocks_per_dpu; bl_indx++) {\n                for (unsigned int bl = 0; bl < BL + 1; bl++) {\n\n                    i = 0;\n                    DPU_FOREACH(dpu_set, dpu, i) {\n                        unsigned int chunks = (((max_cols-1)/BL) - blk + 1) / nr_of_dpus;\n                        unsigned int prev_block_index = 0;\n                        unsigned int rest_blocks = (((max_cols-1)/BL) - blk + 1) % nr_of_dpus;\n                        if (rest_blocks > 0) {\n                            if (i >= rest_blocks) {\n                                prev_block_index = rest_blocks * (chunks + 1) + (i - rest_blocks) * chunks;\n                            } else {\n                                prev_block_index = i * (chunks + 1);\n                            }\n                        } else {\n                            prev_block_index = i * blocks_per_dpu; \n                        }\n\n                        uint64_t input_itemsets_offset = 0;  \n                        int32_t *dpu_pointer;  \n                        if (i + bl_indx * nr_of_dpus >= (((max_cols-1)/BL) - blk + 1)) {\n                            dpu_pointer = dummy;\n                            input_itemsets_offset = 0;  \n                        } else {\n                            uint64_t b_index_x = blk - 1 + prev_block_index + bl_indx;\n                            uint64_t b_index_y = (max_cols-1)/BL + blk - 2 - b_index_x;\n                            dpu_pointer = input_itemsets;\n                            input_itemsets_offset = b_index_y * (max_cols+1) * BL + b_index_x * BL + bl * (max_cols + 1);  \n                        }\n\n                        if (bl == 0) // Skip the first row of the block\n                            continue;\n                        DPU_ASSERT(dpu_prepare_xfer(dpu, dpu_pointer + input_itemsets_offset));\n\n                    }\n\n                    if (bl == 0) {\n                        mram_offset += (BL+2) * sizeof(int32_t);\n                        continue;\n                    }\n                    DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, mram_offset, (BL+2) * sizeof(int32_t), DPU_XFER_DEFAULT));\n                    mram_offset += (BL+2) * sizeof(int32_t);\n\n                }\n            }\n            if (rep >= p.n_warmup)\n                stop(&timer, 4);\n\n\n        }\n\n        // Traceback step\n        if (rep >= p.n_warmup)\n            start(&timer, 1, 1);\n#if PRINT_FILE\n        char *dpu_file = \"./bin/dpu_output.txt\";\n        traceback(traceback_output, dpu_file, input_itemsets, reference, max_rows+1, max_cols+1, penalty);\n#else\n        traceback(traceback_output, input_itemsets, reference, max_rows+1, max_cols+1, penalty);\n#endif\n        if (rep >= p.n_warmup)\n            stop(&timer, 1);\n\n    }\n\n    // Print timing results\n    printf(\"CPU version \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 3, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n    printf(\"\\n\");\n    printf(\"Longest Diagonal CPU-DPU \");\n    print(&long_diagonal_timer, 2, p.n_reps);\n    printf(\"Longest Diagonal DPU Kernel \");\n    print(&long_diagonal_timer, 3, p.n_reps);\n    printf(\"Longest Diagonal Inter-DPU \");\n    print(&long_diagonal_timer, 1, p.n_reps);\n    printf(\"Longest Diagonal DPU-CPU \");\n    print(&long_diagonal_timer, 4, p.n_reps);\n    printf(\"\\n\");\n    \n#if ENERGY\n    printf(\"DPU Energy (J): %f \\t \", tavg_energy / p.n_reps);\n#endif\n\n    // Check output\n    bool status = true;\n    for (uint64_t i = 1; i < max_rows; i++) {\n        for (uint64_t j = 1; j < max_cols; j++) {\n            if (input_itemsets_host[i*max_cols + j] != input_itemsets[i*(max_cols+1) + j]) {\n                status = false;\n#if PRINT\n                printf(\"%ld (%ld, %ld): %d %d\\n\", i*max_cols + j, i, j, input_itemsets_host[i*max_cols + j], input_itemsets[i*(max_cols+1) + j]); \n#endif\n            } \n        }\n    }\n    \n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    free(input_itemsets_host);\n    free(input_itemsets);\n    free(reference);\n    free(traceback_output);\n    free(traceback_output_host);\n    DPU_ASSERT(dpu_free(dpu_set));\n    return status ? 0 : -1;\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t nblocks;\n    uint32_t active_blocks;\n    uint32_t penalty;\n    uint32_t dummy;\n} dpu_arguments_t;\n\n#ifndef BL\n#define BL 16 \n#endif\n\n// Data type\n#define T int32_t\n\n// MAX\nint32_t maximum(int32_t a, int32_t b, int32_t c) {\n\n    int32_t k;\n    if (a <= b)\n        k = b;\n    else\n        k = a;\n\n    if (k <= c)\n        return c;\n    else\n        return k;\n        \n}\n\n#define DPU_CAPACITY (64 << 20) // A DPU's capacity is 64 MiB\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define LIMIT -999\n\nint blosum62[24][24] = {\n    { 4, -1, -2, -2,  0, -1, -1,  0, -2, -1, -1, -1, -1, -2, -1,  1,  0, -3, -2,  0, -2, -1,  0, -4},\n    {-1,  5,  0, -2, -3,  1,  0, -2,  0, -3, -2,  2, -1, -3, -2, -1, -1, -3, -2, -3, -1,  0, -1, -4},\n    {-2,  0,  6,  1, -3,  0,  0,  0,  1, -3, -3,  0, -2, -3, -2,  1,  0, -4, -2, -3,  3,  0, -1, -4},\n    {-2, -2,  1,  6, -3,  0,  2, -1, -1, -3, -4, -1, -3, -3, -1,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    { 0, -3, -3, -3,  9, -3, -4, -3, -3, -1, -1, -3, -1, -2, -3, -1, -1, -2, -2, -1, -3, -3, -2, -4},\n    {-1,  1,  0,  0, -3,  5,  2, -2,  0, -3, -2,  1,  0, -3, -1,  0, -1, -2, -1, -2,  0,  3, -1, -4},\n    {-1,  0,  0,  2, -4,  2,  5, -2,  0, -3, -3,  1, -2, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -2,  0, -1, -3, -2, -2,  6, -2, -4, -4, -2, -3, -3, -2,  0, -2, -2, -3, -3, -1, -2, -1, -4},\n    {-2,  0,  1, -1, -3,  0,  0, -2,  8, -3, -3, -1, -2, -1, -2, -1, -2, -2,  2, -3,  0,  0, -1, -4},\n    {-1, -3, -3, -3, -1, -3, -3, -4, -3,  4,  2, -3,  1,  0, -3, -2, -1, -3, -1,  3, -3, -3, -1, -4},\n    {-1, -2, -3, -4, -1, -2, -3, -4, -3,  2,  4, -2,  2,  0, -3, -2, -1, -2, -1,  1, -4, -3, -1, -4},\n    {-1,  2,  0, -1, -3,  1,  1, -2, -1, -3, -2,  5, -1, -3, -1,  0, -1, -3, -2, -2,  0,  1, -1, -4},\n    {-1, -1, -2, -3, -1,  0, -2, -3, -2,  1,  2, -1,  5,  0, -2, -1, -1, -1, -1,  1, -3, -1, -1, -4},\n    {-2, -3, -3, -3, -2, -3, -3, -3, -1,  0,  0, -3,  0,  6, -4, -2, -2,  1,  3, -1, -3, -3, -1, -4},\n    {-1, -2, -2, -1, -3, -1, -1, -2, -2, -3, -3, -1, -2, -4,  7, -1, -1, -4, -3, -2, -2, -1, -2, -4},\n    { 1, -1,  1,  0, -1,  0,  0,  0, -1, -2, -2,  0, -1, -2, -1,  4,  1, -3, -2, -2,  0,  0,  0, -4},\n    { 0, -1,  0, -1, -1, -1, -1, -2, -2, -1, -1, -1, -1, -2, -1,  1,  5, -2, -2,  0, -1, -1,  0, -4},\n    {-3, -3, -4, -4, -2, -2, -3, -2, -2, -3, -2, -3, -1,  1, -4, -3, -2, 11,  2, -3, -4, -3, -2, -4},\n    {-2, -2, -2, -3, -2, -1, -2, -3,  2, -1, -1, -2, -1,  3, -3, -2, -2,  2,  7, -1, -3, -2, -1, -4},\n    { 0, -3, -3, -3, -1, -2, -2, -3, -3,  3,  1, -2,  1, -1, -2, -2,  0, -3, -1,  4, -3, -2, -1, -4},\n    {-2, -1,  3,  4, -3,  0,  1, -1,  0, -3, -4,  0, -3, -3, -2,  0, -1, -4, -3, -3,  4,  1, -1, -4},\n    {-1,  0,  0,  1, -3,  3,  4, -2,  0, -3, -3,  1, -1, -3, -1,  0, -1, -3, -2, -2,  1,  4, -1, -4},\n    { 0, -1, -1, -1, -2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2,  0,  0, -2, -1, -1, -1, -1, -1, -4},\n    {-4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4, -4,  1}\n};\n\n#define DYNAMIC 1\n#define PRINT 0\n#define PRINT_FILE 0\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   max_rows;\n    unsigned int   penalty;\n    unsigned int   n_warmup;\n    unsigned int   n_reps;\n} Params;\n\nstatic void usage() {\n    fprintf(stderr,\n            \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -h        help\"\n            \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n            \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -n <N>    size of sequence: length of the sequence\"\n            \"\\n    -p <P>    penalty: a positive integer\"\n            \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.max_rows      = 256;\n    p.penalty       = 1;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:n:p:\")) >= 0) {\n        switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'w': p.n_warmup      = atoi(optarg); break;\n            case 'e': p.n_reps        = atoi(optarg); break;\n            case 'n': p.max_rows      = atoi(optarg); break;\n            case 'p': p.penalty       = atoi(optarg); break;\n            default:\n                      fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                      usage();\n                      exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/NW/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec); \r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nTYPE ?= INT32\nOP ?= ADD\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE},${OP})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -D${OP}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} -D${OP}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/dpu/task.c",
    "content": "/*\n* Arithmetic Throughtput versus Operational Intensity\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Update\nvoid update(T* bufferA, T scalar, uint32_t rep, uint32_t str) {\n    for (unsigned int r = 0; r < rep; r++){\n        for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i+=str){\n#ifdef ADD\n            bufferA[i] += scalar; // ADD \n#elif SUB\n            bufferA[i] -= scalar; // SUB\n#elif MUL\n            bufferA[i] *= scalar; // MUL \n#elif DIV\n            bufferA[i] /= scalar; // DIV\n#endif\n        }\n    }\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n    perfcounter_cycles cycles;\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    uint32_t rep = DPU_INPUT_ARGUMENTS.repetitions;\n    uint32_t str = DPU_INPUT_ARGUMENTS.stride;\n    T scalar = DPU_INPUT_ARGUMENTS.scalar; // Simply use this number as a scalar\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\n    barrier_wait(&my_barrier);\n    timer_start(&cycles); // START TIMER\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Update\n        update(cache_A, scalar, rep, str);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n    barrier_wait(&my_barrier);\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/host/app.c",
    "content": "/**\n* app.c\n* Operational Intensity Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void update_host(T* A, T scalar, unsigned int nr_elements, unsigned int rep, unsigned int str) {\n    for (unsigned int j = 0; j < nr_elements; j+=(BLOCK_SIZE / sizeof(T))) {\n        for (unsigned int r = 0; r < rep; r++){\n            for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i+=str){\n#ifdef ADD\n                A[j + i] += scalar; // ADD \n#elif SUB\n                A[j + i] -= scalar; // SUB\n#elif MUL\n                A[j + i] *= scalar; // MUL \n#elif DIV\n                A[j + i] /= scalar; // DIV\n#endif\n            }\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size);\n    memcpy(B, A, input_size * sizeof(T));\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\t\n    unsigned int repetitions = p.repetitions >= 1.0 ? (unsigned int)p.repetitions : 1;\n    unsigned int stride = p.repetitions >= 1.0 ? 1 : (unsigned int)(1 / p.repetitions);\n\n    printf(\"p.repetitions\\t%f\\trepetitions\\t%u\\tstride\\t%u\\n\", p.repetitions, repetitions, stride);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        update_host(B, (T)p.n_reps /*use as a scalar*/, input_size, repetitions, stride);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        T scalar = (T)p.n_reps; // Just a scalar\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel, repetitions, stride, scalar};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(B[i] != bufferA[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, B[i], bufferA[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/run.sh",
    "content": "#!/bin/bash\n\nfor i in ADD SUB MUL DIV\ndo\n\tfor j in CHAR SHORT INT32 FLOAT INT64 DOUBLE\n\tdo \t\n\t\tfor k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16\n\t\tdo\n\t\t\tfor l in 0.001953125 0.00390625 0.0078125 0.015625 0.03125 0.0625 0.125 0.25 0.5 1 2 4 8 16 32 64 128 256 512 \n\t\t\tdo\n\t\t\t\tNR_DPUS=1 NR_TASKLETS=$k BL=10 OP=$i TYPE=$j make all\n\t\t\t\twait\n\t\t\t\t./bin/host_code -w 0 -e 1 -i 1048576 -p ${l} >& profile/${i}_${j}_tl${k}_p${l}.txt\n\t\t\t\twait\n\t\t\t\tmake clean\n\t\t\t\twait\n\t\t\tdone\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#elif UINT64\n#define T uint64_t\n#elif INT32\n#define T int32_t\n#elif INT64\n#define T int64_t\n#elif FLOAT\n#define T float\n#elif DOUBLE\n#define T double\n#elif CHAR\n#define T char\n#elif SHORT\n#define T short\n#endif\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n    enum kernels {\n        kernel1 = 0,\n        nr_kernels = 1,\n    } kernel;\n    uint32_t repetitions;\n    uint32_t stride;\n    T scalar;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    float   repetitions;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=2)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=5)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n    -p <P>    # of compute repetitions (default=2)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.repetitions    = 1.0;\n    p.n_warmup      = 2;\n    p.n_reps        = 5;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:p:w:e:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'p': p.repetitions   = atof(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Operational-Intensity/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nVERSION ?= SINGLE\nSYNC ?= HAND\nTYPE ?= INT64\nENERGY ?= 0\nPERF ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_VERSION_$(4)_SYNC_$(5)_TYPE_$(6).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${VERSION},${SYNC},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DENERGY=${ENERGY} -DPERF=${PERF}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${VERSION} -D${SYNC} -D${TYPE} -DPERF=${PERF}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -w 0 -e 1 -i 6553600 -x 1\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/cpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000 -t 4\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 1;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\t\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        thrust::omp::vector<T> d_input(input_size);\n        memcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        count = thrust::reduce(thrust::omp::par, d_input.begin(), d_input.end());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n        h_output = d_input;\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o red -D${TYPE}\n\nclean:\n\trm red\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/gpu/README",
    "content": "Reduction (RED)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./red -i 1048576000\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 160 * 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        count = thrust::reduce(d_input.begin(),d_input.end());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n\tcudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    if(count_host != count){ \n        status = false;\n        printf(\"%lu -- %lu\\n\", count, count_host);\n    }\n\tif (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/dpu/task.c",
    "content": "/*\n* Reduction with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input, unsigned int l_size){\n    T output = 0;\n    for (unsigned int j = 0; j < l_size; j++){\n        output += input[j];\n    }\n    return output;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n#if PERF\n        perfcounter_config(COUNT_CYCLES, true);\n#endif\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n#if PERF && !PERF_SYNC\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n#if !PERF_SYNC // COMMENT OUT TO COMPARE SYNC PRIMITIVES (Experiment in Appendix)\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n\t\t\n        // Reduction in each tasklet\n        l_count += reduction(cache_A, l_size_bytes >> DIV);\n\n    }\n#endif\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = 0;\n    perfcounter_cycles cycles;\n    timer_start(&cycles); // START TIMER\n#endif\n#ifdef TREE // Tree-based reduction\n#ifdef BARRIER\n    // Barrier\n    barrier_wait(&my_barrier);\n#endif\n\n    #pragma unroll\n    for (unsigned int offset = 1; offset < NR_TASKLETS; offset <<= 1){\n\n        if((tasklet_id & (2*offset - 1)) == 0){\n#ifndef BARRIER\n            // Wait\n            handshake_wait_for(tasklet_id + offset);\n#endif\n            message[tasklet_id] += message[tasklet_id + offset];\n        }\n\n#ifdef BARRIER\n        // Barrier\n        barrier_wait(&my_barrier);\n#else\n        else if ((tasklet_id & (offset - 1)) == 0){ // Ensure that wait and notify are in pair\n            // Notify\n            handshake_notify();\n        }\n#endif\n\n    }\n\n#else  // Single-thread reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0)\n        #pragma unroll\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n#endif\n#if PERF && PERF_SYNC // TIMER FOR SYNC PRIMITIVES\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    // Total count in this DPU\n    if(tasklet_id == 0){\n        result->t_count = message[tasklet_id];\n    }\n\n#if PERF && !PERF_SYNC\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/host/app.c",
    "content": "/**\n* app.c\n* RED Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T)(rand());\n    }\n}\n\n// Compute output in the host\nstatic T reduction_host(T* A, unsigned int nr_elements) {\n    T count = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        count += A[i];\n    }\n    return count;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n#if PERF\n    double cc = 0;\n    double cc_min = 0;\n#endif\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T count = 0;\n    T count_host = 0;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        count_host = reduction_host(A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        count = 0;\n        // Input arguments\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments[NR_DPUS];\n        for(i=0; i<nr_of_dpus-1; i++) {\n            input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].kernel=kernel;\n        }\n        input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n        input_arguments[nr_of_dpus-1].kernel=kernel;\t\t\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_count = malloc(nr_of_dpus * sizeof(T));\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == 0)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n#if !PERF\n            free(results_retrieve[i]);\n#endif\n            // Sequential reduction\n            count += results[i].t_count;\n#if PRINT\n            printf(\"i=%d -- %lu\\n\", i, count);\n#endif\n        }\n\n#if PERF\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if (results_retrieve[i][each_tasklet].cycles > results[i].cycles)\n                    results[i].cycles = results_retrieve[i][each_tasklet].cycles;\n            }\n            free(results_retrieve[i]);\n        }\n#endif\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n        // Free memory\n        free(results_count);\n    }\n#if PERF\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n#endif\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(count != count_host) status = false;\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor j in BARRIER HAND\n\tdo \t\n\t\tfor k in 1 2 4 8 16\n\t\tdo\n\t\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=TREE SYNC=$j make all\n\t\t\twait\n            ./bin/host_code -w 2 -e 10 -i 2097152 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n            #./bin/host_code -w 2 -e 10 -i 2048 > profile/TREE_${j}_tl${k}_dpu${i}.txt\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\n\t\tdone\n\tdone\ndone\n\nfor i in 1 \ndo\n    for k in 1 2 4 8 16\n\tdo\n\t    PERF=1 NR_DPUS=$i NR_TASKLETS=$k BL=10 VERSION=SINGLE make all\n\t\twait\n        ./bin/host_code -w 2 -e 10 -i 2097152 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n        #./bin/host_code -w 2 -e 10 -i 2048 > profile/SINGLE_SINGLE_tl${k}_dpu${i}.txt\n\t\twait\n\t\tmake clean\n\t\twait\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n    T t_count;\n} dpu_results_t;\n\n#ifndef PERF\n#define PERF 0 // Use perfcounters?\n#endif\n#ifndef PERF_SYNC\n#define PERF_SYNC 0 // Use perfcounters to time sync primitives?\n#endif\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=6553600 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 6553600;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/RED/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/dpu/gups.c",
    "content": "/*\n* Random Access (GUPS) with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n\nT ran[128]; // Current random numbers\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n#if PERF\n        // perfcounter_config(COUNT_CYCLES, true);\n#endif\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n#if PERF\n    // perfcounter_cycles cycles;\n    // timer_start(&cycles); // START TIMER\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    // result->cycles = 0;\n#endif\t\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    // Number of updates to table (suggested: 16x number of table entries)\n    int NUPDATE = 16 * input_size_dpu;\n\n    for(int j = tasklet_id; j < 128; j += NR_TASKLETS){\n        ran[j] = HPCC_starts((NUPDATE/128) * j);\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(sizeof(T));\n\t\n    for (int i = 0; i < NUPDATE/128; i++){\n        for (int j = tasklet_id; j < 128; j += NR_TASKLETS){\n\n            ran[j] = (ran[j] << 1) ^ ((S) ran[j] < 0 ? POLY : 0);\n\n            // Table[ran[j] & (TableSize-1)] ^= ran[j]; is computed as follows (3 steps)\n            // 1. Load cache \n            mram_read((__mram_ptr void const*)(mram_base_addr_A + (ran[j] & (input_size_dpu - 1)) * sizeof(T)), cache_A, sizeof(T));\n\n            // 2. Update\n            //*cache_A ^= ran[j];\n            *cache_A = ran[j] & (input_size_dpu - 1);\n\n            // 3. Write cache \n            mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_A + (ran[j] & (input_size_dpu - 1)) * sizeof(T)), sizeof(T));\n        }\n    }\n\n#if PERF\n    // result->cycles += timer_stop(&cycles); // STOP TIMER\n#endif\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/host/app.c",
    "content": "/**\n* app.c\n* Random Access (GUPS) Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = A[i];\n    }\n}\n\n// Compute output in the host\nstatic void gups_host(T* B, unsigned int nr_elements) {\n\n    // Number of updates to table (suggested: 16x number of table entries)\n    unsigned int NUPDATE = 16 * (nr_elements / NR_DPUS);\n\n    for (unsigned int d = 0; d < NR_DPUS; d++){\n\n        T ran[128]; // Current random numbers\n        for(unsigned int j = 0; j < 128; j++){\n            ran[j] = HPCC_starts((NUPDATE/128) * j);\n        }\n\n        for (unsigned int i = 0; i < NUPDATE/128; i++){\n            for (unsigned int j = 0; j < NR_TASKLETS; j++){\n                for (unsigned int k = j; k < 128; k += NR_TASKLETS){\n                    ran[k] = (ran[k] << 1) ^ ((S) ran[k] < 0 ? POLY : 0);\n                    //B[((nr_elements / NR_DPUS) * d) + (ran[k] & ((nr_elements / NR_DPUS) - 1))] ^= ran[k];\n                    B[((nr_elements / NR_DPUS) * d) + (ran[k] & ((nr_elements / NR_DPUS) - 1))] = ran[k] & ((nr_elements / NR_DPUS) - 1);\n                }\n            }\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        gups_host(B, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(B[i] != bufferA[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, B[i], bufferA[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/run.sh",
    "content": "#!/bin/bash\n\nfor i in 1 \ndo\n\tfor j in 1 2 4 8 12 16 \n\tdo \t\n            NR_DPUS=$i NR_TASKLETS=$j BL=10 make all\n            wait\n            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/gups_${i}_tl${j}.txt\n            wait\n            make clean\n            wait\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n#define S int64_t\n\n// HPCC_starts function from HPCC benchmark (https://github.com/icl-utk-edu/hpcc/blob/main/RandomAccess/utility.c)\n#define POLY 7ULL\n#define PERIOD 1317624576693539401LL\n\nT HPCC_starts(S n) {\n    int i, j;\n    T m2[64];\n    T temp, ran;\n\n    while (n < 0) n += PERIOD;\n    while (n > PERIOD) n -= PERIOD;\n    if (n == 0) return 0x1;\n\n    temp = 0x1;\n    for (i=0; i<64; i++) {\n        m2[i] = temp;\n        temp = (temp << 1) ^ ((S) temp < 0 ? POLY : 0);\n        temp = (temp << 1) ^ ((S) temp < 0 ? POLY : 0);\n    }\n\n    for (i=62; i>=0; i--)\n        if ((n >> i) & 1)\n            break;\n\n    ran = 0x2;\n    while (i > 0) {\n        temp = 0;\n        for (j=0; j<64; j++)\n            if ((ran >> j) & 1)\n                temp ^= m2[j];\n        ran = temp;\n        i -= 1;\n        if ((n >> i) & 1)\n            ran = (ran << 1) ^ ((S) ran < 0 ? POLY : 0);\n    }\n\n    return ran;\n}\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/Random-GUPS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/cpu/Makefile",
    "content": "all:\n\tg++ -O2 app_baseline.cpp -fopenmp -DTHRUST_HOST_SYSTEM=THRUST_HOST_SYSTEM_CPP -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -lgomp -I/usr/local/cuda-8.0/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/cpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200 -t 4\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/cpu/app_baseline.cpp",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* CPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n#include <thrust/system/omp/execution_policy.h>\n#include <thrust/system/omp/vector.h>\n\n#include <omp.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size =  p.input_size;\n    assert(input_size % (p.n_threads) == 0 && \"Input size!\");\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::omp::vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        memcpy(thrust::raw_pointer_cast(&h_output[0]), A, input_size * sizeof(T));\n\n        omp_set_num_threads(p.n_threads);\n\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        thrust::exclusive_scan(thrust::omp::par, h_output.begin(),h_output.end(),h_output.begin());\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel \");\n    print(&timer, 1, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            //printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app_baseline.cu -I/usr/local/cuda/include -lm -o scan -D${TYPE}\n\nclean:\n\trm scan\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/gpu/README",
    "content": "Prefix sum (SCAN)\n\nCompilation instructions\n\n    TYPE=UINT64 make\n\nExecution instructions\n\n    ./scan -i 1258291200\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/baselines/gpu/app_baseline.cu",
    "content": "/*\n* JGL@SAFARI\n*/\n\n/**\n* GPU code with Thrust\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n\n#include <vector>\n#include <thrust/device_vector.h>\n#include <thrust/host_vector.h>\n#include <thrust/scan.h>\n#include <thrust/copy.h>\n\n#include \"../../support/common.h\"\n#include \"../../support/timer.h\"\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n/**\n* @brief creates input arrays\n* @param nr_elements how many elements in input arrays\n*/\nstatic void read_input(T* A, unsigned int nr_elements) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand()) % 2;\n        A[i] = i;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i - 1];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   exp;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=640 * 3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 1258291200;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of threads!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    cudaDeviceProp device_properties;\n    cudaGetDeviceProperties(&device_properties, 0);\n    cudaSetDevice(0);\n\n    struct Params p = input_params(argc, argv);\n\n    unsigned int nr_of_dpus = 1;\n    \n    unsigned int i = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = (T*)malloc(input_size * sizeof(T));\n    C = (T*)malloc(input_size * sizeof(T));\n    C2 = (T*)malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data.\n    read_input(A, input_size);\n\n    // Timer declaration\n    Timer timer;\n    float time_gpu = 0;\n\n    thrust::host_vector<T> h_output(input_size);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n\n        // Event creation\n        cudaEvent_t start, stop;\n        cudaEventCreate(&start);\n        cudaEventCreate(&stop);\n        float time1 = 0;\n\n        thrust::device_vector<T> d_input(input_size);\n        cudaMemcpy(thrust::raw_pointer_cast(&d_input[0]), A, input_size * sizeof(T), cudaMemcpyHostToDevice);\n\n        // Start timer\n        cudaEventRecord( start, 0 );\n        thrust::exclusive_scan(d_input.begin(),d_input.end(),d_input.begin());\n        // End timer\n        cudaEventRecord( stop, 0 );\n        cudaEventSynchronize( stop );\n        cudaEventElapsedTime( &time1, start, stop );\n        time_gpu += time1;\n\n        h_output = d_input;\n\n        cudaEventDestroy(start);\n        cudaEventDestroy(stop);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"Kernel (ms):\");\n    printf(\"%f\\n\", time_gpu / p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != h_output[i]){ \n            status = false;\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], h_output[i]);\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Reduce-scan-scan)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Reduction in each tasklet\nT __attribute__ ((noinline)) reduction(T *input){\n    T output = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output += input[j];\n    }\n    return output;\n}\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Reduction\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Local count\n    T l_count = 0;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Reduction in each tasklet\n        l_count += reduction(cache_A);\n\n    }\n\n    // Reduce local counts\n    message[tasklet_id] = l_count;\n\n    // Single-runtime reduction\n    // Barrier\n    barrier_wait(&my_barrier);\n    if(tasklet_id == 0){\n        for (unsigned int each_tasklet = 1; each_tasklet < NR_TASKLETS; each_tasklet++){\n            message[0] += message[each_tasklet];\n        }\n        // Total count in this DPU\n        result->t_count = message[0];\n    }\n\n    return 0;\n}\n\n// Scan\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\t\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/host/app.c",
    "content": "/**\n* app.c\n* SCAN-RSS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    T accum = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel, 0};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_scan = malloc(nr_of_dpus * sizeof(T));\n        i = 0;\n        accum = 0;\n\t\t\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == 0)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n            free(results_retrieve[i]);\n            // Sequential scan\n            T temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %lu,  %lu, %lu\\n\", i, results_scan[i], accum, temp);\n#endif\n        }\n\n        // Arguments for scan kernel (2nd kernel)\n        kernel = 1;\n        dpu_arguments_t input_arguments_2[NR_DPUS];\n        for(i=0; i<nr_of_dpus; i++) {\n            input_arguments_2[i].size=input_size_dpu * sizeof(T); \n            input_arguments_2[i].kernel=kernel;\n            input_arguments_2[i].t_count=results_scan[i];\n        }\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments_2[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments_2[0]), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 4, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 4);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 5, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 5);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel Reduction \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU (Scan) \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU Kernel Scan \");\n    print(&timer, 4, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 5, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 VERSION=SINGLE make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-RSS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nBL ?= 10\nTYPE ?= INT64\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/dpu/task.c",
    "content": "/*\n* Scan with multiple tasklets (Scan-scan-add)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nT message[NR_TASKLETS];\nT message_partial_count;\n\n// Scan in each tasklet\nT __attribute__ ((noinline)) scan(T *output, T *input){\n    output[0] = input[0];\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        output[j] = output[j - 1] + input[j];\n    }\n    return output[REGS - 1];\n}\n\n// Handshake with adjacent tasklets\nT __attribute__ ((noinline)) handshake_sync(T l_count, unsigned int tasklet_id){\n    T p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Add in each tasklet\nvoid __attribute__ ((noinline)) add_(T *output, T p_count){\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        output[j] += p_count;\n    }\n}\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Scan-(handshake)scan\nint main_kernel1() {\n#if 1 // Comment out for appendix experiment\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = DPU_INPUT_ARGUMENTS.t_count;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((const __mram_ptr void*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Scan in each tasklet\n        T l_count = scan(cache_B, cache_A); \n\n        // Sync with adjacent tasklets\n        T p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Add in each tasklet\n        add_(cache_B, message_partial_count + p_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\t}\n\n#endif\n    return 0;\n}\n\n// Add\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\t\n    T t_count = DPU_INPUT_ARGUMENTS.t_count;\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_A, BLOCK_SIZE);\n\n        // Add in each tasklet\n        add_(cache_A, t_count);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/host/app.c",
    "content": "/**\n* app.c\n* SCAN-SSA Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic void scan_host(T* C, T* A, unsigned int nr_elements) {\n    C[0] = A[0];\n    for (unsigned int i = 1; i < nr_elements; i++) {\n        C[i] = C[i - 1] + A[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    T accum = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        scan_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel, 0};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n \n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        T* results_scan = malloc(nr_of_dpus * sizeof(T));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                if(each_tasklet == NR_TASKLETS - 1)\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n            }\n            free(results_retrieve[i]);\n            // Sequential scan\n            T temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %lu,  %lu, %lu\\n\", i, results_scan[i], accum, temp);\n#endif\n        }\n\n        // Arguments for add kernel (2nd kernel)\n        kernel = 1;\n        dpu_arguments_t input_arguments_2[NR_DPUS];\n        for(i=0; i<nr_of_dpus; i++) {\n            input_arguments_2[i].size=input_size_dpu * sizeof(T); \n            input_arguments_2[i].kernel=kernel;\n            input_arguments_2[i].t_count=results_scan[i];\n        }\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments_2[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments_2[0]), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 4, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 4);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 5, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 5);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel Scan \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU (Scan) \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU Kernel Add \");\n    print(&timer, 4, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 5, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/run.sh",
    "content": "#!/bin/bash\n\nfor i in  2048 4096 8192 16384 65536 262144 1048576 3932160\ndo\n\t\t    NR_DPUS=1 NR_TASKLETS=16 BL=10 make all\n\t\t\twait\n            ./bin/host_code -w 10 -e 100 -i ${i} > profile/out${i}_tl16_bl10_dpu11\n\t\t\twait\n\t\t\tmake clean\n\t\t\twait\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#define REGS (BLOCK_SIZE >> DIV)\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n    T t_count;\n} dpu_arguments_t;\n\ntypedef struct {\n    T t_count;\n} dpu_results_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SCAN-SSA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o sel -fopenmp app_baseline.c \n\nclean:\n\trm sel\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/cpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./sel -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic uint64_t *A;\nstatic uint64_t *B;\nstatic uint64_t *C;\nstatic uint64_t *C2;\nstatic int pos;\n\nbool pred(const uint64_t x){\n  return (x % 2) == 0;\n}\n\n\nvoid  *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    B = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n    C = (uint64_t*) malloc(nr_elements * sizeof(uint64_t));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        A[i] = i+1;\n        B[i] = 0;\n    }\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic int select_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(!pred(A[my])) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n    return pos;\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    char* dpu_type;\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -d <D>    DPU type (default=fsim)\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=2)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=5)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = select_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n    \n    free(A);\n    free(B);\n    free(C);\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc select.cu -I/usr/local/cuda/include -lm -o select -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm select\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/gpu/README",
    "content": "Select (SEL)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./select 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays (Note: Sample predicate is only for INT)\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__global__ void select_remove_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(!pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n\n__global__ void select_copy_if(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags,\n    struct is_even pred)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(pred(reg[j]))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/baselines/gpu/select.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n\n// Sample predicate for partition (only for INT)\nstruct is_even{\n  __host__ __device__\n  bool operator()(const T &x){\n    return (x % 2) == 0;\n  }\n};\n\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_copy_if(T* output, T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(pred(input[i])){\n\t  output[pos] = input[i];\n      pos++;\n    }\n  }\n}\nvoid cpu_remove_if(T* input, int elements, struct is_even pred){\n  int pos = 0;\n  for (int i = 0; i < elements; i++){\n    if(!pred(input[i])){\n\t  input[pos] = input[i];\n      pos++;\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Select on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n  float time3 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n  T *h_D = (T*)malloc(size);\n\n  // Allocate the device input vector A and output vector B\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n  T *d_B = NULL;\n  cudaMalloc((void **)&d_B, size);\n\n#define WARMUP 2\n#define REP 10\n  unsigned int flagM1 = 0;\n  unsigned int flagM2 = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++)\n        h_A[i] = i % 2 != 0 ? i:i+1;\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x] % 2 != 0){\n            h_A[x] = x * 2;\n            m--;\n        }\n    }\n\n#if PRINT\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    const int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Copy_if)\n    select_copy_if<<<num_wg, ldim>>>(d_B, d_A, numElements, d_flags, is_even());\n\n    cudaMemcpy(&flagM1, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // Stop timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM1) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Copy_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Atomic flags\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch (Remove_if)\n    select_remove_if<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags, is_even()); \n\n    cudaMemcpy(&flagM2, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time3 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time3 / REP;\n      double bw = (double)((numElements + flagM2) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Remove_if - Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_B, size, cudaMemcpyDeviceToHost);\n  cudaMemcpy(h_C, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_copy_if(h_D, h_A, numElements, is_even());\n  cpu_remove_if(h_A, numElements, is_even());\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_D+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM1 - 1; ++i){\n      if (h_B[i] != h_D[i]){\n          fprintf(stderr, \"Copy_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  for (int i = 0; i < flagM2 - 1; ++i){\n      if (h_C[i] != h_A[i]){\n          fprintf(stderr, \"Remove_if - Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaFree(d_B);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n  free(h_D);\n\n  return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/dpu/task.c",
    "content": "/*\n* Select with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nuint32_t message_partial_count;\n\n// SEL in each tasklet\nunsigned int __attribute__ ((noinline)) select(T *output, T *input){\n    unsigned int pos = 0;\n    #pragma unroll\n    for(unsigned int j = 0; j < REGS; j++) {\n        if(!pred(input[j])) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nunsigned int __attribute__ ((noinline)) handshake_sync(unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n    }\n    else\n        p_count = 0;\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        handshake_notify();\n    }\n    return p_count;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size;\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1)\n        message_partial_count = 0;\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // SELECT in each tasklet\n        uint32_t l_count = select(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint32_t p_count = handshake_sync(l_count, tasklet_id);\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + p_count) * sizeof(T)), l_count * sizeof(T));\n\n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            result->t_count = message_partial_count + p_count + l_count;\n            message_partial_count = result->t_count;\n        }\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/host/app.c",
    "content": "/**\n* app.c\n* SEL Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand());\n        A[i] = i + 1;\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) { // Complete with removable elements\n        A[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic unsigned int select_host(T* C, T* A, unsigned int nr_elements) {\n    unsigned int pos = 0;\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        if(!pred(A[i])) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    uint32_t accum = 0;\n    uint32_t total_count = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        total_count = select_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        uint32_t* results_scan = malloc(nr_of_dpus * sizeof(uint32_t));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n\t\t    start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                // Count of this DPU\n                if(each_tasklet == NR_TASKLETS - 1){\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n                }\n            }\n            // Sequential scan\n            uint32_t temp = results[i].t_count;\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %u,  %u, %u\\n\", i, results_scan[i], accum, temp);\n#endif\n            free(results_retrieve[i]);\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 4, rep - p.n_warmup);\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferC + results_scan[i], results[i].t_count * sizeof(T)));\n\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 4);\n\n        // Free memory\n        free(results_scan);\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    if(accum != total_count) status = false;\n    for (i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Sample predicate\nbool pred(const T x){\n  return (x % 2) == 0;\n}\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SEL/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nOP ?= copy\nMEM ?= MRAM\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP},${MEM})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/${OP}.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP} -D${MEM}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP} -D${MEM}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/dpu/add.c",
    "content": "/*\n* STREAM Add\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Add\nvoid add_dpu(T *bufferC, T *bufferA, T *bufferB) {\n\n    #pragma unroll\n    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){\n        bufferC[i] = bufferA[i] + bufferB[i];\n    }\n\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n    uint32_t mram_base_addr_C = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + 2 * input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);\n\n#ifdef WRAM\n        // Barrier\n        barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n#endif\n\n        // Add\n        add_dpu(cache_B, cache_A, cache_B);\n\n#ifdef WRAM\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n\t    // Barrier\n        barrier_wait(&my_barrier);\n#endif\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE);\n\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/dpu/copy.c",
    "content": "/*\n* STREAM Copy\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/dpu/copyw.c",
    "content": "/*\n* STREAM Copy (WRAM)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Copy\nvoid copyw_dpu(T *bufferB, T *bufferA) {\n\n    #pragma unroll\n    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){\n        bufferB[i] = bufferA[i];\n    }\n\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n#ifdef WRAM\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n#endif\n\n        // Copy\n        copyw_dpu(cache_B, cache_A);\n\n#ifdef WRAM\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n#endif\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/dpu/scale.c",
    "content": "/*\n* STREAM Scale\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Scale\nvoid scale_dpu(T *bufferB, T *bufferA, T scalar) {\n\n    #pragma unroll\n    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){\n        bufferB[i] = scalar * bufferA[i];\n    }\n\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    T scalar = (T)input_size_dpu; // Simply use this number as a scalar\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n#ifdef WRAM\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n#endif\n\n        // Scale\n        scale_dpu(cache_B, cache_A, scalar);\n\n#ifdef WRAM\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n#endif\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/dpu/triad.c",
    "content": "/*\n* STREAM Triad\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Triad\nvoid triad_dpu(T *bufferC, T *bufferA, T *bufferB, T scalar) {\n\n    #pragma unroll\n    for (unsigned int i = 0; i < BLOCK_SIZE / sizeof(T); i++){\n        bufferC[i] = bufferA[i] + scalar * bufferB[i];\n    }\n\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n\n    T scalar = (T)input_size_dpu; // Simply use this number as a scalar\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(T));\n    uint32_t mram_base_addr_C = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + 2 * input_size_dpu * sizeof(T));\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);\n\n#ifdef WRAM\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n#endif\n\n        // Triad\n        triad_dpu(cache_B, cache_A, cache_B, scalar);\n\n#ifdef WRAM\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n\t    // Barrier\n\t    barrier_wait(&my_barrier);\n#endif\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE);\n\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/host/app.c",
    "content": "/**\n* app.c\n* STREAM Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\n#if defined(add) || defined(triad)\nstatic T* C;\n#endif\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\n#if defined(add) || defined(triad)\nstatic void stream_host(T* C, T* B, T* A, unsigned int nr_elements) {\n#else\nstatic void stream_host(T* C, T* A, unsigned int nr_elements) {\n#endif\n    for (unsigned int i = 0; i < nr_elements; i++) {\n#ifdef scale\n        C[i] = (nr_elements / NR_DPUS) * A[i];\n#elif add\n        C[i] = A[i] + B[i];\n#elif triad\n        C[i] = A[i] + (nr_elements / NR_DPUS) * B[i];\n#else // copy\n        C[i] = A[i];\n#endif\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n#if defined(add) || defined(triad)\n    C = malloc(input_size * sizeof(T));\n    T *bufferC = C;\n#endif\n    C2 = malloc(input_size * sizeof(T));\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n#if defined(add) || defined(triad)\n        stream_host(C2, B, A, input_size);\n#else\n        stream_host(C2, A, input_size);\n#endif\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#if defined(add) || defined(triad)\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n#if defined(add) || defined(triad)\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, 2 * input_size_dpu * sizeof(T), bufferC + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#else\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#endif\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n#if defined(add) || defined(triad)\n        if(C2[i] != bufferC[i]){ \n#else\n        if(C2[i] != bufferB[i]){ \n#endif\n            status = false;\n#if PRINT\n#if defined(add) || defined(triad)\n            printf(\"%d: %u -- %u\\n\", i, C2[i], bufferC[i]);\n#else\n            printf(\"%d: %u -- %u\\n\", i, C2[i], bufferB[i]);\n#endif\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n#if defined(add) || defined(triad)\n    free(C);\n#endif\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/run.sh",
    "content": "#!/bin/bash\n\n# MRAM\nfor i in copy copyw add scale triad\ndo\n\tfor j in 1 \n\tdo \t\n        for k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 \n        do \t\n            NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=MRAM OP=$i make all\n            wait\n            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/${i}_${j}_tl${k}_MRAM.txt\n            wait\n            make clean\n            wait\n        done\n\tdone\ndone\n\n# WRAM\nfor i in copyw add scale triad\ndo\n\tfor j in 1 \n\tdo \t\n        for k in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 \n        do \t\n            NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=WRAM OP=$i make all\n            wait\n            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/${i}_${j}_tl${k}_WRAM.txt\n            wait\n            make clean\n            wait\n        done\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STREAM/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 8\nNR_DPUS ?= 1\nOP ?= COARSECOARSE\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/dpu/strided.c",
    "content": "/*\n* Strided access with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n    timer_start(&cycles); // START TIMER\t\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size / sizeof(T);\n    uint32_t s = DPU_INPUT_ARGUMENTS.stride;\n\t\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id * (input_size_dpu * sizeof(T) / NR_TASKLETS)));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id * (input_size_dpu * sizeof(T) / NR_TASKLETS)) + input_size_dpu * sizeof(T));\n\n#ifdef COARSECOARSE\t\n    // BLOCK SIZE\n    uint32_t B_SIZE = BLOCK_SIZE / sizeof(T);\n    uint32_t ADDR = (input_size_dpu/NR_TASKLETS) * tasklet_id;\n    uint32_t j = 0;\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T) / NR_TASKLETS; byte_index += BLOCK_SIZE){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);\n\n        // Copy\n        if(((ADDR + j * B_SIZE) & (s - 1)) == 0){\n\n            for(unsigned int i = 0; i < B_SIZE; i += s){\n                cache_B[i] = cache_A[i];\n            }\n\n        }\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), BLOCK_SIZE);\n        j++;\n    }\n#else // FINEFINE\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(sizeof(T));\n    uint32_t stride = (uint32_t)(s * sizeof(T));\n\n    for(unsigned int byte_index = 0; byte_index < input_size_dpu * sizeof(T)  / NR_TASKLETS; byte_index += stride){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, sizeof(T));\n\n        // Write cache to current MRAM block\n        mram_write(cache_A, (__mram_ptr void*)(mram_base_addr_B + byte_index), sizeof(T));\n    }\t\n#endif\n\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n\t\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/host/app.c",
    "content": "/**\n* app.c\n* Strided Access Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Create input arrays\nstatic void read_input(T* A, T* B, T* C, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = A[i];\n        C[i] = A[i];\n    }\n}\n\n// Compute output in the host\nstatic void stride_host(T* B, T* A, unsigned int nr_elements, int s) {\n    for (unsigned int i = 0; i < nr_elements; i+=s){\n        B[i] = A[i];\n    }\n}\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C;\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(T));\n    B = malloc(input_size * sizeof(T));\n    C = malloc(input_size * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n\n    // Create an input file with arbitrary data\n    read_input(A, B, C, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        stride_host(C, A, input_size, p.stride);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), p.stride, kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#ifdef COARSECOARSE\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferB[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C[i], bufferB[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/run.sh",
    "content": "#!/bin/bash\n\nfor i in COARSECOARSE FINEFINE\ndo\n\tfor j in 1 \n\tdo \t\n        for k in 1 2 4 8 16\n        do \t\n            for l in 1 2 4 8 16 32 64 128 256 512 1024 2048 4096\n            do \t\n                NR_DPUS=$j NR_TASKLETS=$k BL=10 OP=$i make all\n                wait\n                ./bin/host_code -w 0 -e 1 -i 2097152 -s ${l} >& profile/${i}_${j}_tl${k}_s${l}.txt\n                wait\n                make clean\n                wait\n            done\n        done\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n    uint32_t stride;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T uint64_t\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   stride;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n    -s <S>    stride (default=2)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.stride        = 2;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:s:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 's': p.stride        = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/STRIDED/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nCPU_BASE_DIR := baselines/cpu\nGPU_BASE_DIR := baselines/gpu\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\nCPU_BASE_TARGET := ${BUILDDIR}/cpu_baseline\nGPU_BASE_TARGET := ${BUILDDIR}/gpu_baseline\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\nCPU_BASE_SOURCES := $(wildcard ${CPU_BASE_DIR}/*.c)\nGPU_BASE_SOURCES := $(wildcard ${GPU_BASE_DIR}/*.cu)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\nCPU_BASE_FLAGS := -O3 -fopenmp\nGPU_BASE_FLAGS := -O3\n\nall: ${HOST_TARGET} ${DPU_TARGET} ${CPU_BASE_TARGET}\n\ngpu: ${GPU_BASE_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\n${CPU_BASE_TARGET}: ${CPU_BASE_SOURCES}\n\t$(CC) -o $@ ${CPU_BASE_SOURCES} ${CPU_BASE_FLAGS}\n\n${GPU_BASE_TARGET}: ${GPU_BASE_SOURCES}\n\tnvcc -o $@ ${GPU_BASE_SOURCES} ${GPU_BASE_FLAGS}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/cpu/Makefile",
    "content": "all:\n\t\tgcc -o spmv -fopenmp app.c \n\nclean:\n\t\trm spmv\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/cpu/README",
    "content": "Sparse Matrix Vector Multiplication (SpMV)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./spmv -f ../../data/bcsstk30.mtx \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/cpu/app.c",
    "content": "\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdint.h>\n\n#include <omp.h>\n\n#include \"../../support/matrix.h\"\n#include \"../../support/params.h\"\n#include \"../../support/timer.h\"\n#include \"../../support/utils.h\"\n\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Initialize SpMV data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading matrix %s\", p.fileName);\n    struct COOMatrix cooMatrix = readCOOMatrix(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    %u rows, %u columns, %u nonzeros\", cooMatrix.numRows, cooMatrix.numCols, cooMatrix.numNonzeros);\n    struct CSRMatrix csrMatrix = coo2csr(cooMatrix);\n    float* inVector = malloc(csrMatrix.numCols*sizeof(float));\n    float* outVector = malloc(csrMatrix.numRows*sizeof(float));\n    initVector(inVector, csrMatrix.numCols);\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU\");\n    omp_set_num_threads(4);\n    Timer timer;\n    startTimer(&timer);\n    #pragma omp parallel for\n    for(uint32_t rowIdx = 0; rowIdx < csrMatrix.numRows; ++rowIdx) {\n        float sum = 0.0f;\n        for(uint32_t i = csrMatrix.rowPtrs[rowIdx]; i < csrMatrix.rowPtrs[rowIdx + 1]; ++i) {\n            uint32_t colIdx = csrMatrix.nonzeros[i].col;\n            float value = csrMatrix.nonzeros[i].value;\n            sum += inVector[colIdx]*value;\n        }\n        outVector[rowIdx] = sum;\n    }\n    stopTimer(&timer);\n    if(p.verbosity == 0) PRINT(\"%f\", getElapsedTime(timer)*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"    Elapsed time: %f ms\", getElapsedTime(timer)*1e3);\n\n    // Deallocate data structures\n    freeCOOMatrix(cooMatrix);\n    freeCSRMatrix(csrMatrix);\n    free(inVector);\n    free(outVector);\n\n    return 0;\n\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc app.cu -I/usr/local/cuda/include -lm -o spmv\n\nclean:\n\trm spmv\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/gpu/README",
    "content": "Sparse Matrix Vector Multiplication (SpMV)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./spmv -f ../../data/bcsstk30.mtx \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/baselines/gpu/app.cu",
    "content": "\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdint.h>\n\n#include \"../../support/matrix.h\"\n#include \"../../support/params.h\"\n#include \"../../support/timer.h\"\n#include \"../../support/utils.h\"\n\n__global__ void spmv_kernel(CSRMatrix csrMatrix, float* inVector, float* outVector) {\n    unsigned int row = blockIdx.x*blockDim.x + threadIdx.x;\n    if(row < csrMatrix.numRows) {\n        float sum = 0.0f;\n        for(unsigned int i = csrMatrix.rowPtrs[row]; i < csrMatrix.rowPtrs[row + 1]; ++i) {\n            struct Nonzero nonzero = csrMatrix.nonzeros[i];\n            sum += inVector[nonzero.col]*nonzero.value;\n        }\n        outVector[row] = sum;\n    }\n}\n\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Initialize SpMV data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading matrix %s\", p.fileName);\n    struct COOMatrix cooMatrix = readCOOMatrix(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    %u rows, %u columns, %u nonzeros\", cooMatrix.numRows, cooMatrix.numCols, cooMatrix.numNonzeros);\n    struct CSRMatrix csrMatrix = coo2csr(cooMatrix);\n    float* inVector = (float*) malloc(csrMatrix.numCols*sizeof(float));\n    float* outVector = (float*) malloc(csrMatrix.numRows*sizeof(float));\n    initVector(inVector, csrMatrix.numCols);\n\n    // Allocate data structures on GPU\n    CSRMatrix csrMatrix_d;\n    csrMatrix_d.numRows = csrMatrix.numRows;\n    csrMatrix_d.numCols = csrMatrix.numCols;\n    csrMatrix_d.numNonzeros = csrMatrix.numNonzeros;\n    cudaMalloc((void**) &csrMatrix_d.rowPtrs, (csrMatrix_d.numRows + 1)*sizeof(unsigned int));\n    cudaMalloc((void**) &csrMatrix_d.nonzeros, csrMatrix_d.numNonzeros*sizeof(struct Nonzero));\n    float* inVector_d;\n    cudaMalloc((void**) &inVector_d, csrMatrix_d.numCols*sizeof(float));\n    float* outVector_d;\n    cudaMalloc((void**) &outVector_d, csrMatrix_d.numRows*sizeof(float));\n\n    // Copy data to GPU\n    cudaMemcpy(csrMatrix_d.rowPtrs, csrMatrix.rowPtrs, (csrMatrix_d.numRows + 1)*sizeof(unsigned int), cudaMemcpyHostToDevice);\n    cudaMemcpy(csrMatrix_d.nonzeros, csrMatrix.nonzeros, csrMatrix_d.numNonzeros*sizeof(struct Nonzero), cudaMemcpyHostToDevice);\n    cudaMemcpy(inVector_d, inVector, csrMatrix_d.numCols*sizeof(float), cudaMemcpyHostToDevice);\n    cudaDeviceSynchronize();\n\n    // Calculating result on GPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on GPU\");\n    Timer timer;\n    startTimer(&timer);\n    unsigned int numThreadsPerBlock = 1024;\n    unsigned int numBlocks = (csrMatrix_d.numRows + numThreadsPerBlock - 1)/numThreadsPerBlock;\n    spmv_kernel <<< numBlocks, numThreadsPerBlock >>> (csrMatrix_d, inVector_d, outVector_d);\n    cudaDeviceSynchronize();\n    stopTimer(&timer);\n    if(p.verbosity == 0) PRINT(\"%f\", getElapsedTime(timer)*1e3);\n    PRINT_INFO(p.verbosity >= 1, \"    Elapsed time: %f ms\", getElapsedTime(timer)*1e3);\n\n    // Copy data from GPU\n    cudaMemcpy(outVector, outVector_d, csrMatrix_d.numRows*sizeof(float), cudaMemcpyDeviceToHost);\n    cudaDeviceSynchronize();\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU\");\n    float* outVectorReference = (float*) malloc(csrMatrix.numRows*sizeof(float));\n    for(uint32_t rowIdx = 0; rowIdx < csrMatrix.numRows; ++rowIdx) {\n        float sum = 0.0f;\n        for(uint32_t i = csrMatrix.rowPtrs[rowIdx]; i < csrMatrix.rowPtrs[rowIdx + 1]; ++i) {\n            uint32_t colIdx = csrMatrix.nonzeros[i].col;\n            float value = csrMatrix.nonzeros[i].value;\n            sum += inVector[colIdx]*value;\n        }\n        outVectorReference[rowIdx] = sum;\n    }\n\n    // Verify the result\n    PRINT_INFO(p.verbosity >= 1, \"Verifying the result\");\n    for(uint32_t rowIdx = 0; rowIdx < csrMatrix.numRows; ++rowIdx) {\n        float diff = (outVectorReference[rowIdx] - outVector[rowIdx])/outVectorReference[rowIdx];\n        const float tolerance = 0.00001;\n        if(diff > tolerance || diff < -tolerance) {\n            PRINT_ERROR(\"Mismatch at index %u (CPU result = %f, DPU result = %f)\", rowIdx, outVectorReference[rowIdx], outVector[rowIdx]);\n        }\n    }\n\n    // Deallocate data structures\n    freeCOOMatrix(cooMatrix);\n    freeCSRMatrix(csrMatrix);\n    free(inVector);\n    free(outVector);\n    free(outVectorReference);\n\n    return 0;\n\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/data/generate/Makefile",
    "content": "\ndefault:\n\tgcc replicate.c -o replicate\n\nclean:\n\trm -f replicate\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/data/generate/generate.sh",
    "content": "\nR=\"1 4 16 64 256\"\n\nmake\n\nfor r in $R; do\n    ./replicate ../bcsstk30.mtx $r ../bcsstk30.mtx.$r.mtx\ndone\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/data/generate/replicate.c",
    "content": "\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n\ntypedef unsigned int uint32_t;\n\nstruct COOMatrix {\n    uint32_t numRows;\n    uint32_t numCols;\n    uint32_t numNonzeros;\n    uint32_t* rowIdxs;\n    uint32_t* colIdxs;\n};\n\nstatic struct COOMatrix readCOOMatrix(const char* fileName) {\n\n    struct COOMatrix cooMatrix;\n\n    // Initialize fields\n    FILE* fp = fopen(fileName, \"r\");\n    assert(fscanf(fp, \"%u\", &cooMatrix.numRows));\n    assert(fscanf(fp, \"%u\", &cooMatrix.numCols));\n    assert(fscanf(fp, \"%u\", &cooMatrix.numNonzeros));\n    cooMatrix.rowIdxs = (uint32_t*) malloc(cooMatrix.numNonzeros*sizeof(uint32_t));\n    cooMatrix.colIdxs = (uint32_t*) malloc(cooMatrix.numNonzeros*sizeof(uint32_t));\n\n    // Read the nonzeros\n    for(uint32_t i = 0; i < cooMatrix.numNonzeros; ++i) {\n        uint32_t rowIdx;\n        assert(fscanf(fp, \"%u\", &rowIdx));\n        cooMatrix.rowIdxs[i] = rowIdx - 1; // File format indexes begin at 1\n        uint32_t colIdx;\n        assert(fscanf(fp, \"%u\", &colIdx));\n        cooMatrix.colIdxs[i] = colIdx - 1; // File format indexes begin at 1\n    }\n\n    fclose(fp);\n\n    return cooMatrix;\n\n}\n\nstatic void freeCOOMatrix(struct COOMatrix cooMatrix) {\n    free(cooMatrix.rowIdxs);\n    free(cooMatrix.colIdxs);\n}\n\nint main(int argc, char** argv) {\n\n    const char* fileName = (argc > 1)?argv[1]:\"bcsstk30.mtx\";\n    unsigned int replicationFactor = (argc > 2)?atoi(argv[2]):4;\n    const char* outFileName = (argc > 3)?argv[3]:\"out.mtx\";\n\n    struct COOMatrix cooMatrix = readCOOMatrix(fileName);\n\n    FILE* fp = fopen(outFileName, \"w\");\n    fprintf(fp, \"%u  %u  %u\\n\", cooMatrix.numRows*replicationFactor, cooMatrix.numCols, cooMatrix.numNonzeros*replicationFactor);\n    for(unsigned int i = 0; i < cooMatrix.numNonzeros; ++i) {\n        unsigned int row = cooMatrix.rowIdxs[i];\n        unsigned int col = cooMatrix.colIdxs[i];\n        for(unsigned int r = 0; r < replicationFactor; ++r) {\n            fprintf(fp, \"%u %u\\n\", row + 1 + r*cooMatrix.numRows, col + 1);\n        }\n    }\n    fclose(fp);\n\n    freeCOOMatrix(cooMatrix);\n\n    return 0;\n\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/dpu/task.c",
    "content": "/*\n* SpMV with multiple tasklets\n*\n*/\n#include <stdio.h>\n\n#include <alloc.h>\n#include <barrier.h>\n#include <defs.h>\n#include <mram.h>\n#include <perfcounter.h>\n#include <seqread.h>\n\n#include \"../support/common.h\"\n\n#define PRINT_ERROR(fmt, ...) printf(\"\\033[0;31mERROR:\\033[0m   \"fmt\"\\n\", ##__VA_ARGS__)\n\n#define MIN(x, y)   (((x) < (y))?(x):(y))\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// main\nint main() {\n\n    if(me() == 0) {\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    // Load parameters\n    uint32_t params_m = (uint32_t) DPU_MRAM_HEAP_POINTER;\n    struct DPUParams* params_w = (struct DPUParams*) mem_alloc(ROUND_UP_TO_MULTIPLE_OF_8(sizeof(struct DPUParams)));\n    mram_read((__mram_ptr void const*)params_m, params_w, ROUND_UP_TO_MULTIPLE_OF_8(sizeof(struct DPUParams)));\n    uint32_t numRows = params_w->dpuNumRows;\n\n    // Sanity check\n    if(me() == 0) {\n        if(numRows%2 != 0) {\n            // The number of rows assigned to the DPU must be a multiple of two to ensure that writes to the output vector are aligned to 8 bytes\n            PRINT_ERROR(\"The number of rows is not a multiple of two!\");\n        }\n    }\n\n    // Identify tasklet's rows\n    uint32_t numRowsPerTasklet = ROUND_UP_TO_MULTIPLE_OF_2((numRows - 1)/NR_TASKLETS + 1); // Multiple of two to ensure that access to rowPtrs and outVector is 8-byte aligned\n    uint32_t taskletRowsStart = me()*numRowsPerTasklet;\n    uint32_t taskletNumRows;\n    if(taskletRowsStart > numRows) {\n        taskletNumRows = 0;\n    } else if(taskletRowsStart + numRowsPerTasklet > numRows) {\n        taskletNumRows = numRows - taskletRowsStart;\n    } else {\n        taskletNumRows = numRowsPerTasklet;\n    }\n\n    // Only process tasklets with nonzero number of rows\n    if(taskletNumRows > 0) {\n\n        // Extract parameters\n        uint32_t rowPtrsOffset = params_w->dpuRowPtrsOffset;\n        uint32_t rowPtrs_m = ((uint32_t)DPU_MRAM_HEAP_POINTER) + params_w->dpuRowPtrs_m;\n        uint32_t nonzeros_m = ((uint32_t)DPU_MRAM_HEAP_POINTER) + params_w->dpuNonzeros_m;\n        uint32_t inVector_m = ((uint32_t)DPU_MRAM_HEAP_POINTER) + params_w->dpuInVector_m;\n        uint32_t outVector_m = ((uint32_t)DPU_MRAM_HEAP_POINTER) + params_w->dpuOutVector_m;\n\n        // Initialize row pointer sequential reader\n        uint32_t taskletRowPtrs_m = rowPtrs_m + taskletRowsStart*sizeof(uint32_t);\n        seqreader_t rowPtrReader;\n        uint32_t* taskletRowPtrs_w = seqread_init(seqread_alloc(), (__mram_ptr void*)taskletRowPtrs_m, &rowPtrReader);\n        uint32_t firstRowPtr = *taskletRowPtrs_w;\n\n        // Initialize nonzeros sequential reader\n        uint32_t taskletNonzerosStart = firstRowPtr - rowPtrsOffset;\n        uint32_t taskletNonzeros_m = nonzeros_m + taskletNonzerosStart*sizeof(struct Nonzero); // 8-byte aligned because Nonzero is 8 bytes\n        seqreader_t nonzerosReader;\n        struct Nonzero* taskletNonzeros_w = seqread_init(seqread_alloc(), (__mram_ptr void*)taskletNonzeros_m, &nonzerosReader);\n\n        // Initialize input vector cache\n        uint32_t inVectorTileSize = 64;\n        float* inVectorTile_w = mem_alloc(inVectorTileSize*sizeof(float));\n        mram_read((__mram_ptr void const*)inVector_m, inVectorTile_w, 256);\n        uint32_t currInVectorTileIdx = 0;\n\n        // Initialize output vector cache\n        uint32_t taskletOutVector_m = outVector_m + taskletRowsStart*sizeof(float);\n        uint32_t outVectorTileSize = 64;\n        float* outVectorTile_w = mem_alloc(outVectorTileSize*sizeof(float));\n\n        // SpMV\n        uint32_t nextRowPtr = firstRowPtr;\n        for(uint32_t row = 0; row < taskletNumRows; ++row) {\n\n            // Find row nonzeros\n            taskletRowPtrs_w = seqread_get(taskletRowPtrs_w, sizeof(uint32_t), &rowPtrReader);\n            uint32_t rowPtr = nextRowPtr;\n            nextRowPtr = *taskletRowPtrs_w;\n            uint32_t taskletNNZ = nextRowPtr - rowPtr;\n\n            // Multiply row with vector\n            float outValue = 0.0f;\n            for(uint32_t nzIdx = 0; nzIdx < taskletNNZ; ++nzIdx) {\n\n                // Get matrix value\n                float matValue = taskletNonzeros_w->value;\n\n                // Get input vector value\n                uint32_t col = taskletNonzeros_w->col;\n                uint32_t inVectorTileIdx = col/inVectorTileSize;\n                uint32_t inVectorTileOffset = col%inVectorTileSize;\n                if(inVectorTileIdx != currInVectorTileIdx) {\n                    mram_read((__mram_ptr void const*)(inVector_m + inVectorTileIdx*inVectorTileSize*sizeof(float)), inVectorTile_w, 256);\n                    currInVectorTileIdx = inVectorTileIdx;\n                }\n                float inValue = inVectorTile_w[inVectorTileOffset];\n\n                // Multiply and add\n                outValue += matValue*inValue;\n\n                // Read next nonzero\n                taskletNonzeros_w = seqread_get(taskletNonzeros_w, sizeof(struct Nonzero), &nonzerosReader); // Last read will be out of bounds and unused\n\n            }\n\n            // Store output\n            uint32_t outVectorTileIdx = row/outVectorTileSize;\n            uint32_t outVectorTileOffset = row%outVectorTileSize;\n            outVectorTile_w[outVectorTileOffset] = outValue;\n            if(outVectorTileOffset == outVectorTileSize - 1) { // Last element in tile\n                mram_write(outVectorTile_w, (__mram_ptr void*)(taskletOutVector_m + outVectorTileIdx*outVectorTileSize*sizeof(float)), 256);\n            } else if(row == taskletNumRows - 1) { // Last row for tasklet\n                mram_write(outVectorTile_w, (__mram_ptr void*)(taskletOutVector_m + outVectorTileIdx*outVectorTileSize*sizeof(float)), (taskletNumRows%outVectorTileSize)*sizeof(float));\n            }\n\n        }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/host/app.c",
    "content": "/**\n* app.c\n* SpMV Host Application Source File\n*\n*/\n#include <dpu.h>\n#include <dpu_log.h>\n\n#include <assert.h>\n#include <getopt.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n#include \"mram-management.h\"\n#include \"../support/common.h\"\n#include \"../support/matrix.h\"\n#include \"../support/params.h\"\n#include \"../support/timer.h\"\n#include \"../support/utils.h\"\n\n#define DPU_BINARY \"./bin/dpu_code\"\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Main of the Host Application\nint main(int argc, char** argv) {\n\n    // Process parameters\n    struct Params p = input_params(argc, argv);\n\n    // Timing and profiling\n    Timer timer;\n    float loadTime = 0.0f, dpuTime = 0.0f, retrieveTime = 0.0f;\n    #if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n    #endif\n\n    // Allocate DPUs and load binary\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t numDPUs;\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &numDPUs));\n    PRINT_INFO(p.verbosity >= 1, \"Allocated %d DPU(s)\", numDPUs);\n\n    // Initialize SpMV data structures\n    PRINT_INFO(p.verbosity >= 1, \"Reading matrix %s\", p.fileName);\n    struct COOMatrix cooMatrix = readCOOMatrix(p.fileName);\n    PRINT_INFO(p.verbosity >= 1, \"    %u rows, %u columns, %u nonzeros\", cooMatrix.numRows, cooMatrix.numCols, cooMatrix.numNonzeros);\n    struct CSRMatrix csrMatrix = coo2csr(cooMatrix);\n    uint32_t numRows = csrMatrix.numRows;\n    uint32_t numCols = csrMatrix.numCols;\n    uint32_t* rowPtrs = csrMatrix.rowPtrs;\n    struct Nonzero* nonzeros = csrMatrix.nonzeros;\n    float* inVector = malloc(ROUND_UP_TO_MULTIPLE_OF_8(numCols*sizeof(float)));\n    initVector(inVector, numCols);\n    float* outVector = malloc(ROUND_UP_TO_MULTIPLE_OF_8(numRows*sizeof(float)));\n\n    // Partition data structure across DPUs\n    uint32_t numRowsPerDPU = ROUND_UP_TO_MULTIPLE_OF_2((numRows - 1)/numDPUs + 1);\n    PRINT_INFO(p.verbosity >= 1, \"Assigning %u rows per DPU\", numRowsPerDPU);\n    struct DPUParams dpuParams[numDPUs];\n    unsigned int dpuIdx = 0;\n    PRINT_INFO(p.verbosity == 1, \"Copying data to DPUs\");\n    DPU_FOREACH (dpu_set, dpu) {\n\n        // Allocate parameters\n        struct mram_heap_allocator_t allocator;\n        init_allocator(&allocator);\n        uint32_t dpuParams_m = mram_heap_alloc(&allocator, sizeof(struct DPUParams));\n\n        // Find DPU's rows\n        uint32_t dpuStartRowIdx = dpuIdx*numRowsPerDPU;\n        uint32_t dpuNumRows;\n        if(dpuStartRowIdx > numRows) {\n            dpuNumRows = 0;\n        } else if(dpuStartRowIdx + numRowsPerDPU > numRows) {\n            dpuNumRows = numRows - dpuStartRowIdx;\n        } else {\n            dpuNumRows = numRowsPerDPU;\n        }\n        dpuParams[dpuIdx].dpuNumRows = dpuNumRows;\n        PRINT_INFO(p.verbosity >= 2, \"    DPU %u:\", dpuIdx);\n        PRINT_INFO(p.verbosity >= 2, \"        Receives %u rows\", dpuNumRows);\n\n        // Partition nonzeros and copy data\n        if(dpuNumRows > 0) {\n\n            // Find DPU's CSR matrix partition\n            uint32_t* dpuRowPtrs_h = &rowPtrs[dpuStartRowIdx];\n            uint32_t dpuRowPtrsOffset = dpuRowPtrs_h[0];\n            struct Nonzero* dpuNonzeros_h = &nonzeros[dpuRowPtrsOffset];\n            uint32_t dpuNumNonzeros = dpuRowPtrs_h[dpuNumRows] - dpuRowPtrsOffset;\n\n            // Allocate MRAM\n            uint32_t dpuRowPtrs_m = mram_heap_alloc(&allocator, (dpuNumRows + 1)*sizeof(uint32_t));\n            uint32_t dpuNonzeros_m = mram_heap_alloc(&allocator, dpuNumNonzeros*sizeof(struct Nonzero));\n            uint32_t dpuInVector_m = mram_heap_alloc(&allocator, numCols*sizeof(float));\n            uint32_t dpuOutVector_m = mram_heap_alloc(&allocator, dpuNumRows*sizeof(float));\n            assert((dpuNumRows*sizeof(float))%8 == 0 && \"Output sub-vector must be a multiple of 8 bytes!\");\n            PRINT_INFO(p.verbosity >= 2, \"        Total memory allocated is %d bytes\", allocator.totalAllocated);\n\n            // Set up DPU parameters\n            dpuParams[dpuIdx].dpuRowPtrsOffset = dpuRowPtrsOffset;\n            dpuParams[dpuIdx].dpuRowPtrs_m = dpuRowPtrs_m;\n            dpuParams[dpuIdx].dpuNonzeros_m = dpuNonzeros_m;\n            dpuParams[dpuIdx].dpuInVector_m = dpuInVector_m;\n            dpuParams[dpuIdx].dpuOutVector_m = dpuOutVector_m;\n\n            // Send data to DPU\n            PRINT_INFO(p.verbosity >= 2, \"        Copying data to DPU\");\n            startTimer(&timer);\n            copyToDPU(dpu, (uint8_t*)dpuRowPtrs_h, dpuRowPtrs_m, (dpuNumRows + 1)*sizeof(uint32_t));\n            copyToDPU(dpu, (uint8_t*)dpuNonzeros_h, dpuNonzeros_m, dpuNumNonzeros*sizeof(struct Nonzero));\n            copyToDPU(dpu, (uint8_t*)inVector, dpuInVector_m, numCols*sizeof(float));\n            stopTimer(&timer);\n            loadTime += getElapsedTime(timer);\n\n        }\n\n        // Send parameters to DPU\n        PRINT_INFO(p.verbosity >= 2, \"        Copying parameters to DPU\");\n        startTimer(&timer);\n        copyToDPU(dpu, (uint8_t*)&dpuParams[dpuIdx], dpuParams_m, sizeof(struct DPUParams));\n        stopTimer(&timer);\n        loadTime += getElapsedTime(timer);\n\n        ++dpuIdx;\n\n    }\n    PRINT_INFO(p.verbosity >= 1, \"    CPU-DPU Time: %f ms\", loadTime*1e3);\n\n    // Run all DPUs\n    PRINT_INFO(p.verbosity >= 1, \"Booting DPUs\");\n    startTimer(&timer);\n    #if ENERGY\n    DPU_ASSERT(dpu_probe_start(&probe));\n    #endif\n    DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n    #if ENERGY\n    DPU_ASSERT(dpu_probe_stop(&probe));\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    PRINT_INFO(p.verbosity >= 1, \"    DPU Energy: %f J\", energy);\n    #endif\n    stopTimer(&timer);\n    dpuTime += getElapsedTime(timer);\n    PRINT_INFO(p.verbosity >= 1, \"    DPU Time: %f ms\", dpuTime*1e3);\n\n    // Copy back result\n    PRINT_INFO(p.verbosity >= 1, \"Copying back the result\");\n    startTimer(&timer);\n    dpuIdx = 0;\n    DPU_FOREACH (dpu_set, dpu) {\n        unsigned int dpuNumRows = dpuParams[dpuIdx].dpuNumRows;\n        if(dpuNumRows > 0) {\n            uint32_t dpuStartRowIdx = dpuIdx*numRowsPerDPU;\n            copyFromDPU(dpu, dpuParams[dpuIdx].dpuOutVector_m, (uint8_t*)(outVector + dpuStartRowIdx), dpuNumRows*sizeof(float));\n        }\n        ++dpuIdx;\n    }\n    stopTimer(&timer);\n    retrieveTime += getElapsedTime(timer);\n    PRINT_INFO(p.verbosity >= 1, \"    DPU-CPU Time: %f ms\", retrieveTime*1e3);\n    if(p.verbosity == 0) PRINT(\"CPU-DPU Time(ms): %f    DPU Kernel Time (ms): %f    DPU-CPU Time (ms): %f\", loadTime*1e3, dpuTime*1e3, retrieveTime*1e3);\n\n    // Calculating result on CPU\n    PRINT_INFO(p.verbosity >= 1, \"Calculating result on CPU\");\n    float* outVectorReference = malloc(numRows*sizeof(float));\n    for(uint32_t rowIdx = 0; rowIdx < numRows; ++rowIdx) {\n        float sum = 0.0f;\n        for(uint32_t i = rowPtrs[rowIdx]; i < rowPtrs[rowIdx + 1]; ++i) {\n            uint32_t colIdx = nonzeros[i].col;\n            float value = nonzeros[i].value;\n            sum += inVector[colIdx]*value;\n        }\n        outVectorReference[rowIdx] = sum;\n    }\n\n    // Verify the result\n    PRINT_INFO(p.verbosity >= 1, \"Verifying the result\");\n    for(uint32_t rowIdx = 0; rowIdx < numRows; ++rowIdx) {\n        float diff = (outVectorReference[rowIdx] - outVector[rowIdx])/outVectorReference[rowIdx];\n        const float tolerance = 0.00001;\n        if(diff > tolerance || diff < -tolerance) {\n            PRINT_ERROR(\"Mismatch at index %u (CPU result = %f, DPU result = %f)\", rowIdx, outVectorReference[rowIdx], outVector[rowIdx]);\n        }\n    }\n\n    // Display DPU Logs\n    if(p.verbosity >= 2) {\n        PRINT_INFO(p.verbosity >= 2, \"Displaying DPU Logs:\");\n        dpuIdx = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            PRINT(\"DPU %u:\", dpuIdx);\n            DPU_ASSERT(dpu_log_read(dpu, stdout));\n            ++dpuIdx;\n        }\n    }\n\n    // Deallocate data structures\n    freeCOOMatrix(cooMatrix);\n    freeCSRMatrix(csrMatrix);\n    free(inVector);\n    free(outVector);\n    free(outVectorReference);\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/host/mram-management.h",
    "content": "\n#ifndef _MRAM_MANAGEMENT_H_\n#define _MRAM_MANAGEMENT_H_\n\n#include \"../support/common.h\"\n#include \"../support/utils.h\"\n\n#define DPU_CAPACITY (64 << 20) // A DPU's capacity is 64 MiB\n\nstruct mram_heap_allocator_t {\n    uint32_t totalAllocated;\n};\n\nstatic void init_allocator(struct mram_heap_allocator_t* allocator) {\n    allocator->totalAllocated = 0;\n}\n\nstatic uint32_t mram_heap_alloc(struct mram_heap_allocator_t* allocator, uint32_t size) {\n    uint32_t ret = allocator->totalAllocated;\n    allocator->totalAllocated += ROUND_UP_TO_MULTIPLE_OF_8(size);\n    if(allocator->totalAllocated > DPU_CAPACITY) {\n        PRINT_ERROR(\"        Total memory allocated is %d bytes which exceeds the DPU capacity (%d bytes)!\", allocator->totalAllocated, DPU_CAPACITY);\n        exit(0);\n    }\n    return ret;\n}\n\nstatic void copyToDPU(struct dpu_set_t dpu, uint8_t* hostPtr, uint32_t mramIdx, uint32_t size) {\n    DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, mramIdx, hostPtr, ROUND_UP_TO_MULTIPLE_OF_8(size)));\n}\n\nstatic void copyFromDPU(struct dpu_set_t dpu, uint32_t mramIdx, uint8_t* hostPtr, uint32_t size) {\n    DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, mramIdx, hostPtr, ROUND_UP_TO_MULTIPLE_OF_8(size)));\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/support/common.h",
    "content": "\n/* Common data structures between host and DPUs */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define ROUND_UP_TO_MULTIPLE_OF_2(x)    ((((x) + 1)/2)*2)\n#define ROUND_UP_TO_MULTIPLE_OF_8(x)    ((((x) + 7)/8)*8)\n\nstruct DPUParams {\n    uint32_t dpuNumRows; /* Number of rows assigned to the DPU */\n    uint32_t dpuRowPtrsOffset; /* Offset of the row pointers */\n    uint32_t dpuRowPtrs_m;\n    uint32_t dpuNonzeros_m;\n    uint32_t dpuInVector_m;\n    uint32_t dpuOutVector_m;\n};\n\nstruct Nonzero {\n    uint32_t col;\n    float value;\n};\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/support/matrix.h",
    "content": "\n#ifndef _MATRIX_H_\n#define _MATRIX_H_\n\n#include <assert.h>\n#include <stdio.h>\n\n#include \"common.h\"\n#include \"utils.h\"\n\nstruct COOMatrix {\n    uint32_t numRows;\n    uint32_t numCols;\n    uint32_t numNonzeros;\n    uint32_t* rowIdxs;\n    struct Nonzero* nonzeros;\n};\n\nstruct CSRMatrix {\n    uint32_t numRows;\n    uint32_t numCols;\n    uint32_t numNonzeros;\n    uint32_t* rowPtrs;\n    struct Nonzero* nonzeros;\n};\n\nstatic struct COOMatrix readCOOMatrix(const char* fileName) {\n\n    struct COOMatrix cooMatrix;\n\n    // Initialize fields\n    FILE* fp = fopen(fileName, \"r\");\n    assert(fscanf(fp, \"%u\", &cooMatrix.numRows));\n    if(cooMatrix.numRows%2 == 1) {\n        PRINT_WARNING(\"Reading matrix %s: number of rows must be even. Padding with an extra row.\", fileName);\n        cooMatrix.numRows++;\n    }\n    assert(fscanf(fp, \"%u\", &cooMatrix.numCols));\n    assert(fscanf(fp, \"%u\", &cooMatrix.numNonzeros));\n    cooMatrix.rowIdxs = (uint32_t*) malloc(ROUND_UP_TO_MULTIPLE_OF_8(cooMatrix.numNonzeros*sizeof(uint32_t)));\n    cooMatrix.nonzeros = (struct Nonzero*) malloc(ROUND_UP_TO_MULTIPLE_OF_8(cooMatrix.numNonzeros*sizeof(struct Nonzero)));\n\n    // Read the nonzeros\n    for(uint32_t i = 0; i < cooMatrix.numNonzeros; ++i) {\n        uint32_t rowIdx;\n        assert(fscanf(fp, \"%u\", &rowIdx));\n        cooMatrix.rowIdxs[i] = rowIdx - 1; // File format indexes begin at 1\n        uint32_t colIdx;\n        assert(fscanf(fp, \"%u\", &colIdx));\n        cooMatrix.nonzeros[i].col = colIdx - 1; // File format indexes begin at 1\n        cooMatrix.nonzeros[i].value = 1.0f;\n    }\n\n    return cooMatrix;\n\n}\n\nstatic void freeCOOMatrix(struct COOMatrix cooMatrix) {\n    free(cooMatrix.rowIdxs);\n    free(cooMatrix.nonzeros);\n}\n\nstatic struct CSRMatrix coo2csr(struct COOMatrix cooMatrix) {\n\n    struct CSRMatrix csrMatrix;\n\n    // Initialize fields\n    csrMatrix.numRows = cooMatrix.numRows;\n    csrMatrix.numCols = cooMatrix.numCols;\n    csrMatrix.numNonzeros = cooMatrix.numNonzeros;\n    csrMatrix.rowPtrs = (uint32_t*) malloc(ROUND_UP_TO_MULTIPLE_OF_8((csrMatrix.numRows + 1)*sizeof(uint32_t)));\n    csrMatrix.nonzeros = (struct Nonzero*) malloc(ROUND_UP_TO_MULTIPLE_OF_8(csrMatrix.numNonzeros*sizeof(struct Nonzero)));\n\n    // Histogram rowIdxs\n    memset(csrMatrix.rowPtrs, 0, (csrMatrix.numRows + 1)*sizeof(uint32_t));\n    for(uint32_t i = 0; i < cooMatrix.numNonzeros; ++i) {\n        uint32_t rowIdx = cooMatrix.rowIdxs[i];\n        csrMatrix.rowPtrs[rowIdx]++;\n    }\n\n    // Prefix sum rowPtrs\n    uint32_t sumBeforeNextRow = 0;\n    for(uint32_t rowIdx = 0; rowIdx < csrMatrix.numRows; ++rowIdx) {\n        uint32_t sumBeforeRow = sumBeforeNextRow;\n        sumBeforeNextRow += csrMatrix.rowPtrs[rowIdx];\n        csrMatrix.rowPtrs[rowIdx] = sumBeforeRow;\n    }\n    csrMatrix.rowPtrs[csrMatrix.numRows] = sumBeforeNextRow;\n\n    // Bin the nonzeros\n    for(uint32_t i = 0; i < cooMatrix.numNonzeros; ++i) {\n        uint32_t rowIdx = cooMatrix.rowIdxs[i];\n        uint32_t nnzIdx = csrMatrix.rowPtrs[rowIdx]++;\n        csrMatrix.nonzeros[nnzIdx] = cooMatrix.nonzeros[i];\n    }\n\n    // Restore rowPtrs\n    for(uint32_t rowIdx = csrMatrix.numRows - 1; rowIdx > 0; --rowIdx) {\n        csrMatrix.rowPtrs[rowIdx] = csrMatrix.rowPtrs[rowIdx - 1];\n    }\n    csrMatrix.rowPtrs[0] = 0;\n\n    return csrMatrix;\n\n}\n\nstatic void freeCSRMatrix(struct CSRMatrix csrMatrix) {\n    free(csrMatrix.rowPtrs);\n    free(csrMatrix.nonzeros);\n}\n\nstatic void initVector(float* vec, uint32_t size) {\n    for(uint32_t i = 0; i < size; ++i) {\n        vec[i] = 1.0f;\n    }\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/support/params.h",
    "content": "\n#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n#include \"utils.h\"\n\nstatic void usage() {\n    PRINT(  \"\\nUsage:  ./program [options]\"\n            \"\\n\"\n            \"\\nBenchmark-specific options:\"\n            \"\\n    -f <F>    input matrix file name (default=data/bcsstk30.mtx)\"\n            \"\\n\"\n            \"\\nGeneral options:\"\n            \"\\n    -v <V>    verbosity\"\n            \"\\n    -h        help\"\n            \"\\n\\n\");\n}\n\ntypedef struct Params {\n  const char* fileName;\n  unsigned int verbosity;\n} Params;\n\nstatic struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.fileName      = \"data/bcsstk30.mtx\";\n    p.verbosity     = 1;\n    int opt;\n    while((opt = getopt(argc, argv, \"f:v:h\")) >= 0) {\n        switch(opt) {\n            case 'f': p.fileName    = optarg;       break;\n            case 'v': p.verbosity   = atoi(optarg); break;\n            case 'h': usage(); exit(0);\n            default:\n                      PRINT_ERROR(\"Unrecognized option!\");\n                      usage();\n                      exit(0);\n        }\n    }\n\n    return p;\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/support/timer.h",
    "content": "\n#ifndef _TIMER_H_\n#define _TIMER_H_\n\n#include <stdio.h>\n#include <sys/time.h>\n\ntypedef struct Timer {\n    struct timeval startTime;\n    struct timeval endTime;\n} Timer;\n\nstatic void startTimer(Timer* timer) {\n    gettimeofday(&(timer->startTime), NULL);\n}\n\nstatic void stopTimer(Timer* timer) {\n    gettimeofday(&(timer->endTime), NULL);\n}\n\nstatic float getElapsedTime(Timer timer) {\n    return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec)\n                   + (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));\n}\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/SpMV/support/utils.h",
    "content": "\n#ifndef _UTILS_H_\n#define _UTILS_H_\n\n#define PRINT_ERROR(fmt, ...)       fprintf(stderr, \"\\033[0;31mERROR:\\033[0m   \" fmt \"\\n\", ##__VA_ARGS__)\n#define PRINT_WARNING(fmt, ...)     fprintf(stderr, \"\\033[0;35mWARNING:\\033[0m \" fmt \"\\n\", ##__VA_ARGS__)\n#define PRINT_INFO(cond, fmt, ...)  if(cond) printf(\"\\033[0;32mINFO:\\033[0m    \" fmt \"\\n\", ##__VA_ARGS__);\n#define PRINT(fmt, ...)             printf(fmt \"\\n\", ##__VA_ARGS__)\n\n#endif\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_DPUS ?= 1\nNR_TASKLETS ?= 16\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=g++\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -lm -pthread\n\nDEP=kernel.cpp kernel.h main.cpp support/common.h support/setup.h support/timer.h \nSRC=main.cpp kernel.cpp\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 \n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/kernel.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"kernel.h\"\n#include <math.h>\n#include <thread>\n#include <vector>\n#include <algorithm>\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   data[b];\n            T   backup[b];\n            int done;\n            int m = A * B - 1;\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < m) {\n                int next_in_cycle = (gid * A) - m * (gid / B);\n                if(next_in_cycle == gid) {\n                    // Dynamic fetch\n                    gid = (head)->fetch_add(1);\n                    continue;\n                }\n                for(int i = 0; i < b; i++) {\n                    data[i] = input[gid * b + i];\n                }\n                //make sure the read is not cached\n                done = (finished + gid)->load();\n                for(; done == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n                    for(int i = 0; i < b; i++) {\n                        backup[i] = input[next_in_cycle * b + i];\n                    }\n                    done = (finished + next_in_cycle)->exchange(1);\n                    if(!done) {\n                        for(int i = 0; i < b; i++) {\n                            input[next_in_cycle * b + i] = data[i];\n                        }\n                    }\n                    for(int i = 0; i < b; i++) {\n                        data[i] = backup[i];\n                    }\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n            }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n\n\n// CPU threads-----------------------------------------------------------------\nvoid run_cpu_threads_010(T *input, std::atomic_int* head, int a, int b, int tiles, int threads) {\n///////////////// Run CPU worker threads /////////////////////////////////\n#if PRINT\n    printf(\"Starting %d CPU threads\\n\", threads);\n#endif\n\n    std::vector<std::thread> cpu_threads;\n    for(int i = 0; i < threads; i++) {\n\n        cpu_threads.push_back(std::thread([=]() {\n\n            T   tile[a * b];\n            int m = a * b - 1;\n\n            // Dynamic fetch\n            int gid = (head)->fetch_add(1);\n\n            while(gid < tiles) {\n                T* input_array = input + a * b * gid;\n                for (int j = 0; j < a * b; j++) {\n                    int next = (j * a)-m*(j/b);\n                    tile[next] = input_array[j];\n                }\n                for (int j = 0; j < a * b; j++) {\n                    input_array[j] = tile[j];\n                }\n                // Dynamic fetch\n                gid = (head)->fetch_add(1);\n\t\t    }\n        }));\n    }\n\n    std::for_each(cpu_threads.begin(), cpu_threads.end(), [](std::thread &t) { t.join(); });\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\nvoid run_cpu_threads_100(T *input, std::atomic_int *finished, std::atomic_int *head, int A, int B, int b, int threads);\nvoid run_cpu_threads_010(T *input, std::atomic_int *head, int m, int n, int tiles, int threads);\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int M_;\n    int m;\n    int N_;\n    int n;\n\n    Params(int argc, char **argv) {\n        n_threads     = 4;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"ht:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -t <T>    # of host threads (default=4)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n                \"\\nBenchmark-specific options:\"\n\t\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    Timer        timer;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 1\");\n        // Launch CPU threads\n        std::thread main_thread_1(run_cpu_threads_100, h_in_out, h_finished, h_head, M_ * m, N_, n, p.n_threads); //M_ * m * N_);\n        main_thread_1.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 1\");\n\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 2\");\n        // Launch CPU threads\n        std::thread main_thread_2(run_cpu_threads_010, h_in_out, h_head, m, n, M_ * N_, p.n_threads);\n        main_thread_2.join();\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 2\");\n\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n        for(int i = 0; i < N_; i++)\n            h_head[i].store(0);\n\n        // start timer\n        if(rep >= p.n_warmup)\n            timer.start(\"Step 3\");\n        // Launch CPU threads\n        for(int i = 0; i < N_; i++){\n            std::thread main_thread_3(run_cpu_threads_100, h_in_out + i * M_ * n * m, h_finished + i * M_ * n, h_head + i, M_, n, m, p.n_threads); //M_ * n);\n            main_thread_3.join();\n\t\t}\n        // end timer\n        if(rep >= p.n_warmup)\n            timer.stop(\"Step 3\");\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Verify answer\n    //verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    free(h_in_backup);\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T double\n#else\n#define T float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/support/setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, struct timeval> startTime;\r\n    map<string, struct timeval> stopTime;\r\n    map<string, double>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            time[name] = 0.0;\r\n        }\r\n        gettimeofday(&startTime[name], NULL);\r\n    }\r\n\r\n    void stop(string name) {\r\n        gettimeofday(&stopTime[name], NULL);\r\n        time[name] += (stopTime[name].tv_sec - startTime[name].tv_sec) * 1000000.0 +\r\n                      (stopTime[name].tv_usec - startTime[name].tv_usec);\r\n    }\r\n\r\n\t\tvoid print(string name, int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / (1000 * REP)); }\r\n};\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/cpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/Makefile",
    "content": "# \n#  Copyright (c) 2016 University of Cordoba and University of Illinois\n#  All rights reserved.\n# \n#  Developed by:    IMPACT Research Group\n#                   University of Cordoba and University of Illinois\n#                   http://impact.crhc.illinois.edu/\n# \n#  Permission is hereby granted, free of charge, to any person obtaining a copy\n#  of this software and associated documentation files (the \"Software\"), to deal\n#  with the Software without restriction, including without limitation the \n#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n#  sell copies of the Software, and to permit persons to whom the Software is\n#  furnished to do so, subject to the following conditions:\n# \n#       > Redistributions of source code must retain the above copyright notice,\n#         this list of conditions and the following disclaimers.\n#       > Redistributions in binary form must reproduce the above copyright\n#         notice, this list of conditions and the following disclaimers in the\n#         documentation and/or other materials provided with the distribution.\n#       > Neither the names of IMPACT Research Group, University of Cordoba, \n#         University of Illinois nor the names of its contributors may be used \n#         to endorse or promote products derived from this Software without \n#         specific prior written permission.\n# \n#  THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n#  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n#  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n#  THE SOFTWARE.\n# \n\nCXX=/usr/local/cuda/bin/nvcc\nCXX_FLAGS=-std=c++11\n\nLIB=-L/usr/lib/ -L$/usr/local/cuda/lib64/ -lm\n\nINC=-I/usr/local/cuda/include/\n\nDEP=kernel.h main.cpp kernel.cu support/common.h support/cuda-setup.h support/timer.h support/verify.h\nSRC=main.cpp kernel.cu\nEXE=trns\n\nall:\n\t$(CXX) $(CXX_FLAGS) $(SRC) $(LIB) $(INC) -o $(EXE)\n\nclean:\n\trm -f $(EXE)\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/README",
    "content": "In-place matrix transposition (TRNS)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./trns -w 0 -r 1 -m 16 -n 8 -o 4096 -p 2556 -i 64\n\nFor more options\n\n    ./trns -h\n\nRead more\nJ. Gomez-Luna et al., “In-place Matrix Transposition on GPUs,” IEEE TPDS, 2016.\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/kernel.cu",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/common.h\"\n\nextern __shared__ int l_mem[];\n\n// GPU kernel ------------------------------------------------------------------------------------------\n__global__ void PTTWAC_soa_asta(int A, int B, int b, T *input, int *finished, int *head) {\n\n    int* done = l_mem;\n    int* gid_ = &done[1];\n\n    const int tid = threadIdx.x;\n    int       m   = A * B - 1;\n\n    if(tid == 0) // Dynamic fetch\n        gid_[0] = atomicAdd(&head[0], 1);\n    __syncthreads();\n\n    while(gid_[0] < m) {\n        int next_in_cycle = (gid_[0] * A) - m * (gid_[0] / B);\n        if(next_in_cycle == gid_[0]) {\n            if(tid == 0) // Dynamic fetch\n                gid_[0] = atomicAdd(&head[0], 1);\n            __syncthreads();\n            continue;\n        }\n        T   data1, data2, data3, data4;\n        int i = tid;\n        if(i < b)\n            data1 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data2 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data3 = input[gid_[0] * b + i];\n        i += blockDim.x;\n        if(i < b)\n            data4 = input[gid_[0] * b + i];\n\n        if(tid == 0) {\n            //make sure the read is not cached\n            done[0] = atomicAdd(&finished[gid_[0]], 0);\n        }\n        __syncthreads();\n\n        for(; done[0] == 0; next_in_cycle = (next_in_cycle * A) - m * (next_in_cycle / B)) {\n            T backup1, backup2, backup3, backup4;\n            i = tid;\n            if(i < b)\n                backup1 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup2 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup3 = input[next_in_cycle * b + i];\n            i += blockDim.x;\n            if(i < b)\n                backup4 = input[next_in_cycle * b + i];\n\n            if(tid == 0) {\n                done[0] = atomicExch(&finished[next_in_cycle], (int)1);\n            }\n            __syncthreads();\n\n            if(!done[0]) {\n                i = tid;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data1;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data2;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data3;\n                i += blockDim.x;\n                if(i < b)\n                    input[next_in_cycle * b + i] = data4;\n            }\n            i = tid;\n            if(i < b)\n                data1 = backup1;\n            i += blockDim.x;\n            if(i < b)\n                data2 = backup2;\n            i += blockDim.x;\n            if(i < b)\n                data3 = backup3;\n            i += blockDim.x;\n            if(i < b)\n                data4 = backup4;\n        }\n\n        if(tid == 0) // Dynamic fetch\n            gid_[0] = atomicAdd(&head[0], 1);\n        __syncthreads();\n    }\n}\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    PTTWAC_soa_asta<<<dimGrid, dimBlock, l_mem_size>>>(A, B, b, input, \n        finished, head);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n\n__global__ void BS_marshal(T *input, int tile_size, int width) {\n\n  T* tile = (T*)l_mem;\n\n  int tidx = threadIdx.x;\n  int m = width*tile_size-1;\n  int bid = blockIdx.x;\n\n  input += tile_size*width*bid;\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    int next = (i * tile_size)-m*(i/width);\n    tile[next] = input[i];\n  }\n  __syncthreads();\n  for (int i = tidx; i < tile_size*width; i+=blockDim.x) {\n    input[i] = tile[i];\n  }\n}\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size){\n    dim3 dimGrid(blocks);\n    dim3 dimBlock(threads);\n    BS_marshal<<<dimGrid, dimBlock, l_mem_size>>>(input, m, n);\n    cudaError_t err = cudaGetLastError();\n    return err;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/kernel.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"cuda_runtime.h\"\n#include <stdlib.h>\n#include <atomic>\n#include \"support/common.h\"\n\ncudaError_t call_PTTWAC_soa_asta(int blocks, int threads, int A, int B, int b, T *input, \n    int *finished, int *head, int l_mem_size);\n\ncudaError_t call_BS_marshal(int blocks, int threads, int m, int n, T *input, int l_mem_size);\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/main.cpp",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"support/cuda-setup.h\"\n#include \"kernel.h\"\n#include \"support/common.h\"\n#include \"support/timer.h\"\n#include \"support/verify.h\"\n\n#include <unistd.h>\n#include <thread>\n#include <string.h>\n#include <assert.h>\n\n// Params ---------------------------------------------------------------------\nstruct Params {\n\n    int device;\n    int n_gpu_threads;\n    int n_gpu_blocks;\n    int n_threads;\n    int n_warmup;\n    int n_reps;\n    int   M_;\n    int   m;\n    int   N_;\n    int   n;\n\n    Params(int argc, char **argv) {\n        device        = 0;\n        n_gpu_threads  = 64;\n        n_gpu_blocks = 16;\n        n_warmup      = 5;\n        n_reps        = 50;\n        M_            = 128;\n        m             = 16;\n        N_            = 128;\n        n             = 8;\n        int opt;\n        while((opt = getopt(argc, argv, \"hd:i:g:t:w:r:m:n:o:p:\")) >= 0) {\n            switch(opt) {\n            case 'h':\n                usage();\n                exit(0);\n                break;\n            case 'd': device        = atoi(optarg); break;\n            case 'i': n_gpu_threads  = atoi(optarg); break;\n            case 'g': n_gpu_blocks = atoi(optarg); break;\n            case 't': n_threads     = atoi(optarg); break;\n            case 'w': n_warmup      = atoi(optarg); break;\n            case 'r': n_reps        = atoi(optarg); break;\n            case 'm': m             = atoi(optarg); break;\n            case 'n': n             = atoi(optarg); break;\n            case 'o': M_            = atoi(optarg); break;\n            case 'p': N_            = atoi(optarg); break;\n            default:\n                fprintf(stderr, \"\\nUnrecognized option!\\n\");\n                usage();\n                exit(0);\n            }\n        }\n        assert((n_gpu_threads > 0 && n_gpu_blocks > 0)\n            && \"TRNS only runs on CPU-only or GPU-only: './trns -g 0' or './trns -t 0'\");\n    }\n\n    void usage() {\n        fprintf(stderr,\n                \"\\nUsage:  ./trns [options]\"\n                \"\\n\"\n                \"\\nGeneral options:\"\n                \"\\n    -h        help\"\n                \"\\n    -d <D>    CUDA device ID (default=0)\"\n                \"\\n    -i <I>    # of device threads per block (default=64)\"\n                \"\\n    -g <G>    # of device blocks (default=16)\"\n                \"\\n    -w <W>    # of untimed warmup iterations (default=5)\"\n                \"\\n    -r <R>    # of timed repetition iterations (default=50)\"\n                \"\\n\"\n                \"\\nData-partitioning-specific options:\"\n                \"\\n    TRNS only supports CPU-only or GPU-only execution\"\n                \"\\n\"\n\t\t        \"\\nBenchmark-specific options:\"\n\t\t        \"\\n    -m <I>    m (default=16 elements)\"\n\t\t        \"\\n    -n <I>    n (default=8 elements)\"\n\t\t        \"\\n    -o <I>    M_ (default=128 elements)\"\n\t\t        \"\\n    -p <I>    N_ (default=128 elements)\"\n                \"\\n\");\n    }\n};\n\n// Input Data -----------------------------------------------------------------\nvoid read_input(T *x_vector, const Params &p) {\n    int in_size = p.M_ * p.m * p.N_ * p.n;\n    srand(5432);\n    for(int i = 0; i < in_size; i++) {\n        x_vector[i] = ((T)(rand() % 100) / 100);\n    }\n}\n\n// Main ------------------------------------------------------------------------------------------\nint main(int argc, char **argv) {\n\n    const Params p(argc, argv);\n    CUDASetup    setcuda(p.device);\n    Timer        timer;\n    cudaError_t  cudaStatus;\n\n    // Allocate\n    timer.start(\"Allocation\");\n    int M_       = p.M_;\n    int m       = p.m;\n    int N_       = p.N_;\n    int n       = p.n;\n    int in_size       = M_ * m * N_ * n;\n    int finished_size = M_ * m * N_;\n    T *              h_in_out = (T *)malloc(in_size * sizeof(T));\n    std::atomic_int *h_finished =\n        (std::atomic_int *)malloc(sizeof(std::atomic_int) * finished_size);\n    std::atomic_int *h_head = (std::atomic_int *)malloc(N_ * sizeof(std::atomic_int));\n    ALLOC_ERR(h_in_out, h_finished, h_head);\n    T * d_in_out;\n    int * d_finished;\n    int * d_head;\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMalloc((void**)&d_in_out, in_size * sizeof(T));\n        cudaStatus = cudaMalloc((void**)&d_finished, (p.n_gpu_blocks != 0) ? sizeof(int) * finished_size : 0);\n        cudaStatus = cudaMalloc((void**)&d_head, (p.n_gpu_blocks != 0) ? N_ * sizeof(int) : 0);\n        CUDA_ERR();\n    }\n    T *h_in_backup = (T *)malloc(in_size * sizeof(T));\n    ALLOC_ERR(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Allocation\");\n    timer.print(\"Allocation\", 1);\n\n    // Initialize\n    timer.start(\"Initialization\");\n    const int max_gpu_threads = setcuda.max_gpu_threads();\n    read_input(h_in_out, p);\n    memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n    for(int i = 0; i < N_; i++)\n        h_head[i].store(0);\n    timer.stop(\"Initialization\");\n    timer.print(\"Initialization\", 1);\n    memcpy(h_in_backup, h_in_out, in_size * sizeof(T)); // Backup for reuse across iterations\n\n    // Copy to device\n    timer.start(\"Copy To Device\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n        cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n        CUDA_ERR();\n    }\n    cudaDeviceSynchronize();\n    timer.stop(\"Copy To Device\");\n    timer.print(\"Copy To Device\", 1);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Reset\n        memcpy(h_in_out, h_in_backup, in_size * sizeof(T));\n        memset((void *)h_finished, 0, sizeof(std::atomic_int) * finished_size);\n\t    for(int i = 0; i < N_; i++)\n\t        h_head[i].store(0);\n\t\tcudaDeviceSynchronize();\n\n        // Launch GPU threads\n        if(p.n_gpu_blocks > 0) {\n            // Kernel launch\n            assert(p.n_gpu_threads <= max_gpu_threads && \n                \"The runtime block size is greater than the maximum runtime block size that can be used on this device\");\n\n            cudaStatus = cudaMemcpy(d_in_out, h_in_backup, in_size * sizeof(T), cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 1\");\n            // Step 1\n            cudaStatus = call_PTTWAC_soa_asta(M_ * m * N_, p.n_gpu_threads, M_ * m, N_, n,\n                d_in_out, (int*)d_finished, (int*)d_head, sizeof(int) + sizeof(int));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 1\");\n\n\t        // start timer\n\t        if(rep >= p.n_warmup)\n\t            timer.start(\"Step 2\");\n            // Step 2\n            cudaStatus = call_BS_marshal(M_ * N_, p.n_gpu_threads, m, n, d_in_out, m * n * sizeof(T));\n            CUDA_ERR();\n\t        // end timer\n\t        if(rep >= p.n_warmup)\n\t            timer.stop(\"Step 2\");\n\n            cudaStatus = cudaMemcpy(d_finished, h_finished, sizeof(int) * finished_size, cudaMemcpyHostToDevice);\n            cudaStatus = cudaMemcpy(d_head, h_head, N_ * sizeof(int), cudaMemcpyHostToDevice);\n            CUDA_ERR();\n            // start timer\n            if(rep >= p.n_warmup)\n                timer.start(\"Step 3\");\n            // Step 3\n            for(int i = 0; i < N_; i++){\n                cudaStatus = call_PTTWAC_soa_asta(M_ * n, p.n_gpu_threads, M_, n, m,\n                    d_in_out + i * M_ * n * m, (int*)d_finished + i * M_ * n, (int*)d_head + i, sizeof(int) + sizeof(int));\n                CUDA_ERR();\n            }\n            // end timer\n            if(rep >= p.n_warmup)\n                timer.stop(\"Step 3\");\n\n        }\n\n        cudaDeviceSynchronize();\n\n    }\n    timer.print(\"Step 1\", p.n_reps);\n    timer.print(\"Step 2\", p.n_reps);\n    timer.print(\"Step 3\", p.n_reps);\n\n    // Copy back\n    timer.start(\"Copy Back and Merge\");\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaMemcpy(h_in_out, d_in_out, in_size * sizeof(T), cudaMemcpyDeviceToHost);\n        CUDA_ERR();\n        cudaDeviceSynchronize();\n    }\n    timer.stop(\"Copy Back and Merge\");\n    timer.print(\"Copy Back and Merge\", 1);\n\n    // Verify answer\n    verify(h_in_out, h_in_backup, M_ * m, N_ * n, 1);\n\n    // Free memory\n    timer.start(\"Deallocation\");\n    free(h_in_out);\n    free(h_finished);\n    free(h_head);\n    if(p.n_gpu_blocks != 0) {\n        cudaStatus = cudaFree(d_in_out);\n        cudaStatus = cudaFree(d_finished);\n        cudaStatus = cudaFree(d_head);\n        CUDA_ERR();\n    }\n    free(h_in_backup);\n    cudaDeviceSynchronize();\n    timer.stop(\"Deallocation\");\n    timer.print(\"Deallocation\", 1);\n\n    // Release timers\n    timer.release(\"Allocation\");\n    timer.release(\"Initialization\");\n    timer.release(\"Copy To Device\");\n    timer.release(\"Step 1\");\n    timer.release(\"Step 2\");\n    timer.release(\"Step 3\");\n    timer.release(\"Copy Back and Merge\");\n    timer.release(\"Deallocation\");\n\n    printf(\"Test Passed\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/support/common.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#ifndef DOUBLE_PRECISION\n#define DOUBLE_PRECISION 1\n#endif\n\n#if DOUBLE_PRECISION\n#define T long int // double\n#else\n#define T int // float\n#endif\n\n#define PRINT 0\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/support/cuda-setup.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include <cuda.h>\n#include <cuda_runtime.h>\n#include <fstream>\n\n// Allocation error checking\n#define ERR_1(v1)                                                                                                      \\\n    if(v1 == NULL) {                                                                                                   \\\n        fprintf(stderr, \"Allocation error at %s, %d\\n\", __FILE__, __LINE__);                                           \\\n        exit(-1);                                                                                                      \\\n    }\n#define ERR_2(v1,v2) ERR_1(v1) ERR_1(v2)\n#define ERR_3(v1,v2,v3) ERR_2(v1,v2) ERR_1(v3)\n#define ERR_4(v1,v2,v3,v4) ERR_3(v1,v2,v3) ERR_1(v4)\n#define ERR_5(v1,v2,v3,v4,v5) ERR_4(v1,v2,v3,v4) ERR_1(v5)\n#define ERR_6(v1,v2,v3,v4,v5,v6) ERR_5(v1,v2,v3,v4,v5) ERR_1(v6)\n#define GET_ERR_MACRO(_1,_2,_3,_4,_5,_6,NAME,...) NAME\n#define ALLOC_ERR(...) GET_ERR_MACRO(__VA_ARGS__,ERR_6,ERR_5,ERR_4,ERR_3,ERR_2,ERR_1)(__VA_ARGS__)\n\n#define CUDA_ERR()                                                                                                     \\\n    if(cudaStatus != cudaSuccess) {                                                                                    \\\n        fprintf(stderr, \"CUDA error: %s\\n at %s, %d\\n\", cudaGetErrorString(cudaStatus), __FILE__, __LINE__);           \\\n        exit(-1);                                                                                                      \\\n    }\n\nstruct CUDASetup {\n\n    cudaDeviceProp device_prop;\n\n    CUDASetup(int device) {\n        cudaError_t cudaStatus;\n        cudaStatus = cudaSetDevice(device);\n        CUDA_ERR();\n\n        cudaStatus = cudaGetDeviceProperties(&device_prop, device);\n        CUDA_ERR();\n        fprintf(stderr, \"%s\\t\", device_prop.name);\n\n    }\n\n    int max_gpu_threads() {\n        return device_prop.maxThreadsPerBlock;\n    }\n};\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <cuda_runtime.h>\r\n#include <sys/time.h>\r\n#include <iostream>\r\n#include <map>\r\n#include <string>\r\n\r\nusing namespace std;\r\n\r\nstruct Timer {\r\n\r\n    map<string, cudaEvent_t> startTime;\r\n    map<string, cudaEvent_t> stopTime;\r\n    map<string, float>         time;\r\n\r\n    void start(string name) {\r\n        if(!time.count(name)) {\r\n            cudaEventCreate(&startTime[name]); \r\n            cudaEventCreate(&stopTime[name]);\r\n            time[name] = 0.0;\r\n        }\r\n        cudaEventRecord(startTime[name], 0);\r\n    }\r\n\r\n    void stop(string name) {\r\n        cudaEventRecord(stopTime[name],0);\r\n        cudaEventSynchronize(stopTime[name]);\r\n        float part_time = 0.0;\r\n        cudaEventElapsedTime(&part_time, startTime[name], stopTime[name]);\r\n        time[name] += part_time;\r\n    }\r\n\r\n    void print(string name, unsigned int REP) { printf(\"%s Time (ms): %f\\n\", name.c_str(), time[name] / REP); }\r\n\r\n    void release(string name){\r\n        cudaEventDestroy(startTime[name]); \r\n        cudaEventDestroy(stopTime[name]);\r\n    }\r\n};\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/baselines/gpu/support/verify.h",
    "content": "/*\n * Copyright (c) 2016 University of Cordoba and University of Illinois\n * All rights reserved.\n *\n * Developed by:    IMPACT Research Group\n *                  University of Cordoba and University of Illinois\n *                  http://impact.crhc.illinois.edu/\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * with the Software without restriction, including without limitation the \n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\n * sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n *      > Redistributions of source code must retain the above copyright notice,\n *        this list of conditions and the following disclaimers.\n *      > Redistributions in binary form must reproduce the above copyright\n *        notice, this list of conditions and the following disclaimers in the\n *        documentation and/or other materials provided with the distribution.\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \n *        University of Illinois nor the names of its contributors may be used \n *        to endorse or promote products derived from this Software without \n *        specific prior written permission.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\n * THE SOFTWARE.\n *\n */\n\n#include \"common.h\"\n#include <math.h>\n\ninline int compare_output(T *output, T *ref, int dim) {\n    int i;\n    for(i = 0; i < dim; i++) {\n        T diff = fabs(ref[i] - output[i]);\n        if((diff - 0.0f) > 0.00001f && diff > 0.01 * fabs(ref[i])) {\n            printf(\"line: %d ref: %f actual: %f diff: %f\\n\", i, ref[i], output[i], diff);\n            exit(EXIT_FAILURE);\n        }\n    }\n    return 0;\n}\n\n// Sequential transposition for comparison purposes\n//[w][h/t][t] to [h/t][w][t]\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\ninline void verify(T *input2, T *input, int height, int width, int tile_size) {\n    trns_host(input, height, width, tile_size);\n    compare_output(input2, input, height * width);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/dpu/task.c",
    "content": "/*\n* 3-step matrix transposition with multiple tasklets\n* Acks: Stefano Ballarin (P&S PIM Fall 2020)\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <mutex.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\nuint32_t curr_tile = 0; // protected by MUTEX\nuint32_t get_tile();\nvoid read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n);\nvoid read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\nvoid write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m);\n_Bool get_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n_Bool get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done);\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\n// Mutexes\nMUTEX_INIT(tile_mutex);\nMUTEX_INIT(done_mutex);\n\nextern int main_kernel1(void);\nextern int main_kernel2(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1, main_kernel2};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// Step 2: 0010\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER; // A in MRAM\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n\n    T* data = (T*) mem_alloc(m * n * sizeof(T));\n    T* backup = (T*) mem_alloc(m * n * sizeof(T));\n\n    for(unsigned int tile = tasklet_id; tile < M_; tile += NR_TASKLETS){\n        read_tile_step2(A, tile * m * n, data, m, n);\n        for (unsigned int i = 0; i < m * n; i++){\n            backup[(i * m) - (m * n - 1) * (i / n)] = data[i];\n        }\n        write_tile_step2(A, tile * m * n, backup, m, n);\n    }\n\n    return 0;\n}\n\n// Step 3: 0100\nint main_kernel2() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t m = DPU_INPUT_ARGUMENTS.m;\n    uint32_t n = DPU_INPUT_ARGUMENTS.n;\n    uint32_t M_ = DPU_INPUT_ARGUMENTS.M_;\n    uint32_t done_array = (uint32_t)(DPU_MRAM_HEAP_POINTER + M_ * m * n * sizeof(T));\n\n    const uint32_t tile_max = M_ * n - 1; // Tile id upper bound\n\n    T* data = (T*)mem_alloc(sizeof(T) * m);\n    T* backup = (T*)mem_alloc(sizeof(T) * m);\n    T* read_done = (T*)mem_alloc(sizeof(T));\n\n    uint32_t tile;\n    _Bool done;\n\n    tile = get_tile();\n\n    while (tile < tile_max){\n        uint32_t next_in_cycle = ((tile * M_) - tile_max * (tile / n));\n        if (next_in_cycle == tile){\n            tile = get_tile();\n            continue;\n        }\n        read_tile_step3(A, tile * m, data, m);\n\n        done = get_done(done_array, tile, read_done);\n        for(; done == 0; next_in_cycle = ((next_in_cycle * M_) - tile_max * (next_in_cycle / n))){\n            read_tile_step3(A, next_in_cycle * m, backup, m);\n\n            done = get_and_set_done(done_array, next_in_cycle, read_done);\n\n            if(!done) {\n                write_tile_step3(A, next_in_cycle * m, data, m);\n            }\n            for(uint32_t i = 0; i < m; i++){\n                data[i] = backup[i];\n            }\n        }\n        tile = get_tile();\n    }\n\t\t\n    return 0;\n}\n\n// Auxiliary functions\nuint32_t __attribute__ ((noinline)) get_tile(){\n    mutex_lock(tile_mutex);\n    uint32_t value = curr_tile;\n    curr_tile++;\n    mutex_unlock(tile_mutex);\n    return value;\n}\n\nvoid __attribute__ ((noinline)) read_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_read((__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), variable + (m * n - rest) * sizeof(T), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) write_tile_step2(uint32_t A, uint32_t offset, T* variable, uint32_t m, uint32_t n){\n    int rest = m * n;\n    int transfer;\n    while(rest > 0){\n        if(rest * sizeof(T) > 2048){\n            transfer = 2048 / sizeof(T);\n      } else {\n            transfer = rest;\n      }\n      mram_write(variable + (m * n - rest) * sizeof(T), (__mram_ptr void*)(A + (offset + m * n - rest) * sizeof(T)), sizeof(T) * transfer);\n      rest -= transfer;\n    }\n}\n\nvoid __attribute__ ((noinline)) read_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_read((__mram_ptr void*)(A + offset * sizeof(T)), variable, sizeof(T) * m);\n}\n\nvoid __attribute__ ((noinline)) write_tile_step3(uint32_t A, uint32_t offset, T* variable, uint32_t m){\n    mram_write(variable, (__mram_ptr void*)(A + offset * sizeof(T)), sizeof(T) * m);\n}\n\n_Bool __attribute__ ((noinline)) get_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n\n_Bool __attribute__ ((noinline))get_and_set_done(uint32_t done_array_step3, uint32_t address, T* read_done){\n    uint32_t result;\n\n    mutex_lock(done_mutex);\n    mram_read((__mram_ptr void*)(done_array_step3 + address), read_done, sizeof(T));\n    result = ((*read_done & (0x01 << (address % sizeof(T)))) != 0);\n    *read_done |= (0x01 << (address % sizeof(T)));\n    mram_write(read_done, (__mram_ptr void*)(done_array_step3 + address), sizeof(T));\n    mutex_unlock(done_mutex);\n\n    return (_Bool)result;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/host/app.c",
    "content": "/**\n* app.c\n* TRNS Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A_host;\nstatic T* A_backup;\nstatic T* A_result;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void trns_host(T* input, unsigned int A, unsigned int B, unsigned int b){\n   T* output = (T*) malloc(sizeof(T) * A * B * b);\n   unsigned int next;\n   for (unsigned int j = 0; j < b; j++){\n      for (unsigned int i = 0; i < A * B; i++){\n         next = (i * A) - (A * B - 1) * (i / B);\n         output[next * b + j] = input[i*b+j];\n      }\n   }\n   for (unsigned int k = 0; k < A * B * b; k++){\n      input[k] = output[k];\n   }\n   free(output);\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    unsigned int i = 0;\n    unsigned int N_ = p.N_;\n    const unsigned int n = p.n;\n    const unsigned int M_ = p.M_;\n    const unsigned int m = p.m;\n    N_ = p.exp == 0 ? N_ * NR_DPUS : N_;\n\n    // Input/output allocation\n    A_host = malloc(M_ * m * N_ * n * sizeof(T));\n    A_backup = malloc(M_ * m * N_ * n * sizeof(T));\n    A_result = malloc(M_ * m * N_ * n * sizeof(T));\n    T* done_host = malloc(M_ * n); // Host array to reset done array of step 3\n    memset(done_host, 0, M_ * n);\n\n    // Create an input file with arbitrary data\n    read_input(A_host, M_ * m * N_ * n);\n    memcpy(A_backup, A_host, M_ * m * N_ * n * sizeof(T));\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\n\", NR_TASKLETS);\n    printf(\"M_\\t%u, m\\t%u, N_\\t%u, n\\t%u\\n\", M_, m, N_, n);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        int timer_fix = 0;\n        // Compute output on CPU (performance comparison and verification purposes)\n        memcpy(A_host, A_backup, M_ * m * N_ * n * sizeof(T));\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup + timer_fix);\n        trns_host(A_host, M_ * m, N_ * n, 1);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        unsigned int curr_dpu = 0;\n        unsigned int active_dpus;\n        unsigned int active_dpus_before = 0;\n        unsigned int first_round = 1;\n\n        while(curr_dpu < N_){\n            // Allocate DPUs and load binary\n            if((N_ - curr_dpu) > NR_DPUS){\n                active_dpus = NR_DPUS;\n            } else {\n                active_dpus = (N_ - curr_dpu);\n            }\n            if((active_dpus_before != active_dpus) && (!(first_round))){\n                DPU_ASSERT(dpu_free(dpu_set));\n                DPU_ASSERT(dpu_alloc(active_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n                printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n            } else if (first_round){\n                DPU_ASSERT(dpu_alloc(active_dpus, NULL, &dpu_set));\n                DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n                DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n                printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n            }\n\n            printf(\"Load input data (step 1)\\n\");\n            if(rep >= p.n_warmup)\n                start(&timer, 1, rep - p.n_warmup + timer_fix);\n            // Load input matrix (step 1)\n            for(unsigned int j = 0; j < M_ * m; j++){\n                unsigned int i = 0;\n                DPU_FOREACH(dpu_set, dpu) {\n                    DPU_ASSERT(dpu_prepare_xfer(dpu, &A_backup[j * N_ * n + n * (i + curr_dpu)]));\n                    i++;\n                }\n                DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, sizeof(T) * j * n, sizeof(T) * n, DPU_XFER_DEFAULT));\n            }\n            if(rep >= p.n_warmup)\n                stop(&timer, 1);\n            // Reset done array (for step 3)\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpu_prepare_xfer(dpu, done_host));\n            }\n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, M_ * m * n * sizeof(T), (M_ * n) / 8 == 0 ? 8 : M_ * n, DPU_XFER_DEFAULT));\n\n            unsigned int kernel = 0;\n            dpu_arguments_t input_arguments = {m, n, M_, kernel};\n\t        DPU_FOREACH(dpu_set, dpu, i) {\n\t            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n\t        }\n\t        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n            printf(\"Run step 2 on DPU(s) \\n\");\n            // Run DPU kernel\n            if(rep >= p.n_warmup){\n                start(&timer, 2, rep - p.n_warmup + timer_fix);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_start(&probe));\n#endif\n            }\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if(rep >= p.n_warmup){\n                stop(&timer, 2);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n            }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n            kernel = 1;\n            dpu_arguments_t input_arguments2 = {m, n, M_, kernel};\n\t        DPU_FOREACH(dpu_set, dpu, i) {\n\t            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments2));\n\t        }\n\t        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments2), DPU_XFER_DEFAULT));\n            printf(\"Run step 3 on DPU(s) \\n\");\n            // Run DPU kernel\n            if(rep >= p.n_warmup){\n                start(&timer, 3, rep - p.n_warmup + timer_fix);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_start(&probe));\n#endif\n            }\n            DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n            if(rep >= p.n_warmup){\n                stop(&timer, 3);\n#if ENERGY\n                DPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n            }\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n            printf(\"Retrieve results\\n\");\n            if(rep >= p.n_warmup)\n                start(&timer, 4, rep - p.n_warmup + timer_fix);\n            DPU_FOREACH(dpu_set, dpu) {\n                DPU_ASSERT(dpu_prepare_xfer(dpu, (T*)(&A_result[curr_dpu * m * n * M_])));\n                curr_dpu++;\n            }\n            DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, sizeof(T) * m * n * M_, DPU_XFER_DEFAULT));\n            if(rep >= p.n_warmup)\n                stop(&timer, 4);\n\n            if(first_round){\n                first_round = 0;\n            }\n            timer_fix++;\n        }\n        DPU_ASSERT(dpu_free(dpu_set));\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU (Step 1) \");\n    print(&timer, 1, p.n_reps);\n    printf(\"Step 2 \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Step 3 \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n    #if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n    #endif\t\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < M_ * m * N_ * n; i++) {\n        if(A_host[i] != A_result[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, A_host[i], A_result[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A_host);\n    free(A_backup);\n    free(A_result);\n    free(done_host);\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#define T int64_t\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t m;\n    uint32_t n;\n    uint32_t M_;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    kernel2 = 1,\n\t    nr_kernels = 2,\n\t} kernel;\n} dpu_arguments_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   M_;\n    unsigned int   m;\n    unsigned int   N_;\n    unsigned int   n;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -m <I>    m (default=16 elements)\"\n        \"\\n    -n <I>    n (default=8 elements)\"\n        \"\\n    -o <I>    M_ (default=12288 elements)\"\n        \"\\n    -p <I>    N_ (default=1 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.M_            = 12288;\n    p.m             = 16;\n    p.N_            = 1;\n    p.n             = 8;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:x:m:n:o:p:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 'm': p.m             = atoi(optarg); break;\n        case 'n': p.n             = atoi(optarg); break;\n        case 'o': p.M_            = atoi(optarg); break;\n        case 'p': p.N_            = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TRNS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nNR_DPUS ?= 1\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS})\n\nCOMMON_INCLUDES := support\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -lm\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET} -n 131072\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/Makefile",
    "content": "all:\n\tg++ streamp_openmp.cpp tools.cpp -o streamp_openmp -std=c++11 -fopenmp\nrun:\n\t./streamp_openmp SampleInput/randomlist5M.txt 256\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/README",
    "content": "Time Series Analysis (TS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./launch.sh\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/launch.sh",
    "content": "./streamp_openmp inputs/randomlist33M.txt 256\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/mprofile.h",
    "content": "\n#define PATH_TIME_SERIES \"./\"\n#define PATH_RESULTS \"./\"\n#define DTYPE double \n#define ARIT_FACT 32\n\n//#define HBM_ALOC\n//#define RANDOM_DIAGS\n\nint loadTimeSeriesFromFile (std::string infilename, std::vector<DTYPE> &A, int &timeSeriesLength);\nint saveProfileToFile(std::string outfilename, DTYPE * profile, int * profileIndex, int timeSeriesLength, int windowSize);\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/streamp_openmp.cpp",
    "content": "/*++++++++\r\nWritten by Yan Zhu, Jan 2018.\r\n\r\nThis is SCRIMP++.\r\n\r\nDetails of the SCRIMP++ algorithm can be found at:\r\nYan Zhu, Chin-Chia M.Yeh, Zachary Zimmerman, Kaveh Kamgar and Eamonn Keogh,\r\n\"Solving Time Series Data Mining Problems at Scale with SCRIMP++\", submitted to KDD 2018.\r\n\r\nUsage: >> scrimpplusplus InputFileName SubsequenceLength stepsize\r\nInputFileName: Name of the time series file\r\nSubsequenceLength: Subsequence length m\r\nstepsize: Step size ratio s/m. For all the experiments in the paper, stepsize is always set as 0.25.\r\n\r\nexample input:\r\n>> scrimpplusplus ts_1000.txt 50 0.25\r\n\r\nexample output:\r\nThe code will generate two outputs.\r\nSCRIMP_PLUS_PLUS_New_PreSCRIMP_MatrixProfile_and_Index_50_ts_1000.txt          This is the approximate matrix profile and matrix profile index generated after PreSCRIMP.\r\nSCRIMP_PLUS_PLUS_New_MatrixProfile_and_Index_50_ts_1000.txt                    This is the final/exact matrix profile and matrix profile index, generated when the whole algorithm (PreSCRIMP+SCRIMP) is completed.\r\n\r\nThe first column of the output file is the matrix profile value.\r\nThe second column of the output file is the matrix profile index.\r\n*/\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <signal.h>\r\n#include <stdlib.h>\r\n#include <math.h>\r\n#include <iostream>\r\n#include <fstream>\r\n#include <iomanip>\r\n#include <limits>\r\n#include <vector>\r\n#include <algorithm>\r\n#include <string.h>\r\n#include <sstream>\r\n#include <chrono>\r\n#include <omp.h>\r\n\r\n#include \"mprofile.h\"\r\n\r\nbool interrupt = false;\r\nint numThreads, exclusionZone;\r\nint windowSize, timeSeriesLength, ProfileLength;\r\nint* profileIndex, *profileIndex_tmp;\r\nDTYPE *AMean, *ASigma, *profile, *profile_tmp;\r\nstd::vector<int> idx;\r\nstd::vector<DTYPE> A;\r\n\r\n\r\nvoid intHandler(int) {\r\n    std::cout << '\\n' << \"[>>] Interrupt request by user...\" << '\\n';\r\n    interrupt = true;\r\n}\r\n\r\n\r\nvoid preprocess()\r\n{\r\n  DTYPE* ACumSum   = new DTYPE[timeSeriesLength];\r\n  DTYPE* ASqCumSum = new DTYPE[timeSeriesLength];\r\n  DTYPE* ASum      = new DTYPE[ProfileLength];\r\n  DTYPE* ASumSq    = new DTYPE[ProfileLength];\r\n  DTYPE* ASigmaSq  = new DTYPE[ProfileLength];\r\n\r\n  AMean  = new DTYPE[ProfileLength];\r\n  ASigma = new DTYPE[ProfileLength];\r\n\r\n  ACumSum[0]   = A[0];\r\n  ASqCumSum[0] = A[0] * A[0];\r\n\r\n  for (int i = 1; i < timeSeriesLength; i++)\r\n  {\r\n    ACumSum[i]   = A[i] + ACumSum[i - 1];\r\n    ASqCumSum[i] = A[i] * A[i] + ASqCumSum[i - 1];\r\n  }\r\n\r\n  ASum[0] = ACumSum[windowSize - 1];\r\n  ASumSq[0] = ASqCumSum[windowSize - 1];\r\n\r\n  for (int i = 0; i < timeSeriesLength - windowSize; i++)\r\n  {\r\n    ASum[i + 1]   = ACumSum[windowSize + i] - ACumSum[i];\r\n    ASumSq[i + 1] = ASqCumSum[windowSize + i] - ASqCumSum[i];\r\n  }\r\n\r\n  for (int i = 0; i < ProfileLength; i++)\r\n  {\r\n      AMean[i] = ASum[i]/ windowSize;\r\n      ASigmaSq[i] = ASumSq[i] / windowSize - AMean[i] * AMean[i];\r\n      ASigma[i] = sqrt(ASigmaSq[i]);\r\n  }\r\n\r\n  delete ACumSum;\r\n  delete ASqCumSum;\r\n  delete ASum;\r\n  delete ASumSq;\r\n  delete ASigmaSq;\r\n}\r\n\r\nvoid streamp()\r\n{\r\n\r\n  #pragma omp parallel\r\n  {\r\n    DTYPE  lastz, distance, windowSizeDTYPE;\r\n    DTYPE  * distances, * lastzs;\r\n    int diag, my_offset, i, j, ri;\r\n\r\n    distances = new DTYPE[ARIT_FACT];\r\n    lastzs    = new DTYPE[ARIT_FACT];\r\n\r\n    windowSizeDTYPE = (DTYPE) windowSize;\r\n\r\n    my_offset = omp_get_thread_num() * ProfileLength;\r\n\r\n    #pragma omp for schedule(dynamic)\r\n    for (ri = 0; ri < idx.size(); ri++)\r\n    {\r\n      //select a diagonal\r\n\r\n      if(!interrupt){\r\n\r\n      diag = idx[ri];\r\n\r\n      lastz = 0;\r\n\r\n      //calculate the dot product of every two time series values that ar diag away\r\n      #pragma omp simd\r\n      for (j = diag; j < windowSize + diag; j++)\r\n      {\r\n        lastz += A[j] * A[j-diag];\r\n      }\r\n\r\n      //j is the column index, i is the row index of the current distance value in the distance matrix\r\n      j = diag;\r\n      i = 0;\r\n\r\n      //evaluate the distance based on the dot product\r\n      distance = 2 * (windowSizeDTYPE - (lastz - windowSizeDTYPE* AMean[j] * AMean[i]) / (ASigma[j] * ASigma[i]));\r\n\r\n      //update matrix profile and matrix profile index if the current distance value is smaller\r\n      if (distance < profile_tmp[my_offset + j])\r\n      {\r\n        profile_tmp[my_offset + j] = distance;\r\n        profileIndex_tmp [my_offset+j] = i;\r\n      }\r\n\r\n      if (distance < profile_tmp[my_offset + i])\r\n      {\r\n        profile_tmp[my_offset + i] = distance;\r\n        profileIndex_tmp [my_offset + i] = j;\r\n      }\r\n      i = 1;\r\n      j = diag + 1;\r\n\r\n      /*while(j < (ProfileLength - ARIT_FACT))\r\n      {\r\n        #pragma omp simd\r\n        for(int k = 0; k < ARIT_FACT; k++)\r\n        {\r\n          lastzs[k] = (A[k + j + windowSize - 1] * A[k + i + windowSize - 1]) - (A[k + j - 1] * A[k + i - 1]);\r\n        }\r\n\r\n        lastzs[0] += lastz;\r\n        #pragma unroll (ARIT_FACT - 1)\r\n        for(int k = 1; k < ARIT_FACT; k++)\r\n        {\r\n          lastzs[k] += lastzs[k-1];\r\n        }\r\n        lastz = lastzs[ARIT_FACT - 1];\r\n\r\n        #pragma omp simd\r\n        for(int k = 0; k < ARIT_FACT; k++)\r\n        {\r\n          distances[k] =  2 * (windowSizeDTYPE - (lastzs[k] -  AMean[k+j]  * AMean[k+i] * windowSizeDTYPE) / (ASigma[k+j] * ASigma[k+i]));\r\n        }\r\n\r\n        #pragma omp simd\r\n        for(int k = 0; k < ARIT_FACT; k++)\r\n        {\r\n          if (distances[k] < profile_tmp[k + my_offset + j])\r\n          {\r\n            profile_tmp[k + my_offset + j] = distances[k];\r\n            profileIndex_tmp [k + my_offset+ j] = i + k;\r\n          }\r\n\r\n         if (distances[k] < profile_tmp[k + my_offset + i])\r\n          {\r\n            profile_tmp[k + my_offset + i] = distances[k];\r\n            profileIndex_tmp[k + my_offset + i] = j + k;\r\n          }\r\n        }\r\n        i+=ARIT_FACT;\r\n        j+=ARIT_FACT;\r\n      }\r\n\r\n      while(j < ProfileLength)\r\n      {\r\n        lastz   = lastz + (A[j + windowSize - 1] * A[i + windowSize - 1]) - (A[j - 1] * A[i - 1]);\r\n        distance = 2 * (windowSizeDTYPE - (lastz -  AMean[j]  * AMean[i] * windowSizeDTYPE) / (ASigma[j] * ASigma[i]));\r\n\r\n        if (distance < profile_tmp[my_offset + j])\r\n        {\r\n          profile_tmp[my_offset + j] = distance;\r\n          profileIndex_tmp [my_offset+ j] = i;\r\n        }\r\n\r\n        if (distance < profile_tmp[my_offset + i])\r\n        {\r\n          profile_tmp[my_offset + i] = distance;\r\n          profileIndex_tmp[my_offset + i] = j;\r\n        }\r\n        i++;\r\n        j++;\r\n      }*/\r\n    }\r\n    }\r\n\r\n    delete(lastzs);\r\n    delete(distances);\r\n\r\n    #pragma omp barrier\r\n\r\n    // Reduce the (partial) result\r\n    DTYPE min_distance;\r\n    int min_index;\r\n\r\n    #pragma omp for schedule(static)\r\n    for (int colum = 0; colum < ProfileLength; colum++)\r\n    {\r\n      min_distance = std::numeric_limits<DTYPE>::infinity();\r\n      min_index = 0;\r\n      #pragma unroll(256)\r\n      for(int row = 0; row < numThreads; row++)\r\n      {\r\n        if(profile_tmp[colum + (row*ProfileLength)] < min_distance)\r\n        {\r\n          min_distance = profile_tmp[colum + (row * ProfileLength)];\r\n          min_index    = profileIndex_tmp[colum + (row * ProfileLength)];\r\n        }\r\n      }\r\n      profile[colum]      = min_distance;\r\n      profileIndex[colum] = min_index;\r\n    }\r\n    #pragma omp barrier\r\n  }\r\n\r\n  delete(AMean);\r\n  delete(ASigma);\r\n  delete(profile_tmp);\r\n  delete(profileIndex_tmp);\r\n}\r\n\r\nint main(int argc, char* argv[])\r\n{\r\n  bool sequentialDiags = false;\r\n  // Creation of time meassure structures\r\n  std::chrono::high_resolution_clock::time_point tprogstart, tstart, tend;\r\n  std::chrono::duration<double> time_elapsed;\r\n\r\n  // Creation of interrupt handler\r\n  struct sigaction act;\r\n  act.sa_handler = intHandler;\r\n  sigaction(SIGINT, &act, NULL);\r\n\r\n  // Set window size\r\n  windowSize = atoi(argv[2]);\r\n\r\n  // Set the exclusion zone\r\n  exclusionZone = (int) (windowSize * 0.25);\r\n\r\n  // Set the runtime number\r\n  //numThreads = atoi(argv[3]);\r\n  //omp_set_num_threads(numThreads);\r\n\r\n  numThreads = omp_get_max_threads();\r\n\r\n  // Set computational order\r\n  if(argc > 4)\r\n  \tsequentialDiags = (strcmp(argv[4], \"-s\") == 0);\r\n\r\n  // Display info through console\r\n  std::cout << std::endl;\r\n  std::cout << \"############################################################\" << std::endl;\r\n  std::cout << \"///////////////////////// STREAMP //////////////////////////\" << std::endl;\r\n  std::cout << \"############################################################\" << std::endl;\r\n  std::cout << std::endl;\r\n  std::cout << \"[>>] Reading File...\" << std::endl;\r\n\r\n  /* Read time series file */\r\n  tstart = std::chrono::high_resolution_clock::now();\r\n//  tprogstart = tstart;\r\n\r\n  std::stringstream outfilename_num;\r\n  outfilename_num << windowSize;\r\n  std::string outfilenamenum = outfilename_num.str();\r\n  std::string inputfilename  = argv[1];\r\n  std::string outfilename = \"SCRIMP_PLUS_PLUS_New_MatrixProfile_and_Index_\" + outfilenamenum + \"_\" + inputfilename;\r\n\r\n  loadTimeSeriesFromFile(inputfilename, A, timeSeriesLength);\r\n\r\n  tend = std::chrono::high_resolution_clock::now();\r\n  time_elapsed = tend - tstart;\r\n  std::cout << \"[OK] Read File Time: \" << std::setprecision(std::numeric_limits<double>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n\r\n  // Set Matrix Profile Length\r\n  ProfileLength = timeSeriesLength - windowSize + 1;\r\n\r\n  // Display info through console\r\n  std::cout << std::endl;\r\n  std::cout << \"------------------------------------------------------------\" << std::endl;\r\n  std::cout << \"************************** INFO ****************************\" << std::endl;\r\n  std::cout << std::endl;\r\n  std::cout << \" Time series length: \" << timeSeriesLength << std::endl;\r\n  std::cout << \" Window size:        \" << windowSize       << std::endl;\r\n  std::cout << \" Exclusion zone:     \" << exclusionZone    << std::endl;\r\n  std::cout << \" Profile length:     \" << timeSeriesLength << std::endl;\r\n  std::cout << \" Max avail. threads: \" << numThreads       << std::endl;\r\n  std::cout << \" Sequential order:   \";\r\n  if(sequentialDiags) std::cout << \"true\" << std::endl;\r\n  else std::cout << \"false\" << std::endl;\r\n  std::cout << std::endl;\r\n  std::cout << \"------------------------------------------------------------\" << std::endl;\r\n  std::cout << std::endl;\r\n\r\n  // Preprocess, statistics, get the mean and standard deviation of every subsequence in the time series\r\n  std::cout << \"[>>] Preprocessing...\" << std::endl;\r\n  tstart = std::chrono::high_resolution_clock::now();\r\n\r\n  tprogstart = tstart;\r\n  preprocess();\r\n\r\n  tend = std::chrono::high_resolution_clock::now();\r\n  time_elapsed = tend - tstart;\r\n  std::cout << \"[OK] Preprocess Time:         \" << std::setprecision(std::numeric_limits<double>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n\r\n  //Initialize Matrix Profile and Matrix Profile Index\r\n  std::cout << \"[>>] Initializing Profile...\" << std::endl;\r\n  tstart = std::chrono::high_resolution_clock::now();\r\n\r\n  profile          = new DTYPE[ProfileLength];\r\n  profileIndex     = new int[ProfileLength];\r\n\r\n  profile_tmp      = new DTYPE[ProfileLength * numThreads];\r\n  profileIndex_tmp = new int[ProfileLength * numThreads];\r\n\r\n  for (int i=0; i<ProfileLength*numThreads; i++) profile_tmp[i] = std::numeric_limits<DTYPE>::infinity();\r\n\r\n  tend = std::chrono::high_resolution_clock::now();\r\n  time_elapsed = tend - tstart;\r\n  std::cout << \"[OK] Initialize Profile Time: \" << std::setprecision(std::numeric_limits<DTYPE>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n\r\n  // Random shuffle the diagonals\r\n  idx.clear();\r\n  for (int i = exclusionZone+1; i < ProfileLength; i++)\r\n    idx.push_back(i);\r\n\r\n  if(!sequentialDiags)\r\n    std::random_shuffle(idx.begin(), idx.end());\r\n\r\n  /******************** SCRIMP ********************/\r\n  std::cout << \"[>>] Performing STREAMP...\" << std::endl;\r\n  tstart = std::chrono::high_resolution_clock::now();\r\n\r\n  streamp();\r\n\r\n  tend = std::chrono::high_resolution_clock::now();\r\n  time_elapsed = tend - tstart;\r\n  std::cout << \"[OK] STREAMP Time:            \" << std::setprecision(std::numeric_limits<DTYPE>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n\r\n  // Save profile to file\r\n  //std::cout << \"[>>] Saving Profile...\" << std::endl;\r\n  //tstart = std::chrono::high_resolution_clock::now();\r\n\r\n  //aveProfileToFile(outfilename.c_str(), profile, profileIndex, timeSeriesLength, windowSize);\r\n\r\n  //tend = std::chrono::high_resolution_clock::now();\r\n  //time_elapsed = tend - tstart;\r\n // std::cout << \"[OK] Save Profile Time:       \" << std::setprecision(std::numeric_limits<DTYPE>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n\r\n  // Calculate total time\r\n  time_elapsed = tend - tprogstart;\r\n  std::cout << \"[OK] Total Time:              \" << std::setprecision(std::numeric_limits<DTYPE>::digits10 + 2) << time_elapsed.count() << \" seconds.\" << std::endl;\r\n  std::cout << std::endl;\r\n\r\n  delete profile;\r\n  delete profileIndex;\r\n}\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/cpu/tools.cpp",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <math.h>\n//#include <ctime>\n#include <iostream>\n#include <fstream>\n#include <iomanip>\n#include <limits>\n#include <vector>\n#include <algorithm>\n#include <string>\n#include <sstream>\n\n#include \"mprofile.h\"\n\n\nint loadTimeSeriesFromFile (std::string infilename, std::vector<DTYPE> &A, int &timeSeriesLength)\n{\n  std::fstream timeSeriesFile(std::string(PATH_TIME_SERIES) + infilename, std::ios_base::in);\n\tdouble tempval;\n\ttimeSeriesLength = 0;\n\twhile (timeSeriesFile >> tempval)\n\t{\n\t\tA.push_back(tempval);\n\t\ttimeSeriesLength++;\n\t}\n\ttimeSeriesFile.close();\n\n  return 0;\n}\n\n\nint saveProfileToFile(std::string outfilename, DTYPE * profile, int * profileIndex, int timeSeriesLength, int windowSize)\n{\n  std::string preoutfilename = std::string(PATH_RESULTS) + outfilename;\n\n  std::fstream preprofileOutFile(preoutfilename.c_str(), std::ios_base::out);\n\n  // Write PreSCRIMP Matrix Profile and Matrix Profile Index to file.\n  for (int i = 0; i < timeSeriesLength - windowSize + 1; i++)\n  {\n    preprofileOutFile << std::setprecision(std::numeric_limits<DTYPE>::digits10 + 2) << sqrt(abs(profile[i])) << \" \" << std::setprecision(std::numeric_limits<int>::digits10 + 1) << profileIndex[i] << std::endl;\n  }\n\n  preprofileOutFile.close();\n\n  return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/gpu/Makefile",
    "content": "CUDA_DIRECTORY=/usr/local/cuda\nCC=$(CUDA_DIRECTORY)/bin/nvcc\n#ARCH=-gencode=arch=compute_61,code=sm_61 -gencode=arch=compute_60,code=sm_60 -gencode=arch=compute_52,code=sm_52 -gencode=arch=compute_37,code=sm_37 -gencode=arch=compute_35,code=sm_35 -gencode=arch=compute_30,code=sm_30 -gencode=arch=compute_20,code=sm_20   -gencode=arch=compute_50,code=sm_50\nARCH=-gencode=arch=compute_70,code=sm_70\nCFLAGS=-c -std=c++11 $(ARCH) -O3 -I$(CUDA_DIRECTORY)/include \nLDFLAGS=-L$(CUDA_DIRECTORY)/lib64 -lcufft -lcuda\n#CFLAGS=-c -std=c++11 $(ARCH) -O3  \nSOURCES=STREAMP.cu\n#LDFLAGS= -lcufft -lcuda\nOBJECTS=STREAMP.o\nEXECUTABLE=STREAMP\n\nall: $(SOURCES) $(EXECUTABLE)\n\nmatlab:\n\tnvcc $(MATFLAGS) $(SOURCES)\n    \n$(EXECUTABLE): $(OBJECTS)  $(SOURCES)\n\t$(CC) $(LDFLAGS) $(OBJECTS) -o $@\n\t\n\nSTREAMP.o: $(SOURCES)\n\t$(CC) $(CFLAGS) STREAMP.cu -o $@\n\t\nclean:\n\trm -f *.o STREAMP\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/gpu/README",
    "content": "Time Series Analysis (TS)\n\nCompilation instructions:\n\n    make\n\nExecution instructions\n\n    ./launch.sh\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/gpu/STREAMP.cu",
    "content": "#include <cuComplex.h>\n#include <cufft.h>\n#include <vector>\n#include <stdio.h>\n#include <cuda.h>\n#include <thrust/functional.h>\n#include <thrust/device_ptr.h>\n#include <thrust/transform_scan.h>\n#include <thrust/sequence.h>\n#include <float.h>\n#include <chrono>\n\nusing std::vector;\n\nstatic const int THREADS_PER_BLOCK = 1024;\n\n// Holds matrix profile and index values together\ntypedef union  {\n  float floats[2];                 // floats[0] = lowest\n  unsigned int ints[2];                     // ints[1] = lowIdx\n  unsigned long long int ulong;    // for atomic update\n} mp_entry;\n\nstruct MPIDXCombine\n{\n\t__host__ __device__\n\tmp_entry operator()(double x, unsigned int idx){\n\t\tmp_entry item;\n\t\titem.floats[0] = (float) x;\n\t\titem.ints[1] = idx;\n\t\treturn item;\n\t}\n};\n\n//Atomically updates the MP/idxs using a single 64-bit integer. We lose a small amount of precision in the output, if we do not do this we are unable\n// to atomically update both the matrix profile and the indexes without using a critical section and dedicated locks.\n__device__ inline unsigned long long int MPatomicMin(volatile unsigned long long int* address, double val, unsigned int idx)\n{\n\tfloat fval = (float)val;\n\tmp_entry loc, loctest;\n\tloc.floats[0] = fval;\n\tloc.ints[1] = idx;\n\tloctest.ulong = *address;\n\twhile (loctest.floats[0] > fval){\n\t\tloctest.ulong = atomicCAS((unsigned long long int*) address, loctest.ulong,  loc.ulong);\n\t}\n\treturn loctest.ulong;\n}\n\n//This macro checks return value of the CUDA runtime call and exits\n//the application if the call failed.\n#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }\ninline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)\n{\n   if (code != cudaSuccess)\n   {\n      fprintf(stderr,\"GPUassert: %s %s %d\\n\", cudaGetErrorString(code), file, line);\n      if (abort) exit(code);\n   }\n}\n\n//This kernel computes a sliding mean with specified window size and a corresponding prefix sum array (A)\ntemplate<class DTYPE>\n__global__ void sliding_mean(DTYPE* pref_sum,  size_t window, size_t size, DTYPE* means)\n{\n\tconst DTYPE coeff = 1.0 / (DTYPE) window;\n\tsize_t a = blockIdx.x * blockDim.x + threadIdx.x;\n\tsize_t b = blockIdx.x * blockDim.x + threadIdx.x + window;\n\n\tif(a == 0){\n\t\tmeans[a] = pref_sum[window - 1] * coeff;\n\t}\n\tif(a < size - 1){\n\t\tmeans[a + 1] = (pref_sum[b] - pref_sum[a]) * coeff;\n\t}\n}\n\n//This kernel computes a sliding standard deviaiton with specified window size, the corresponding means of each element, and the prefix squared sum at each element\ntemplate<class DTYPE>\n__global__ void sliding_std(DTYPE* squares, size_t window, size_t size, DTYPE* means, DTYPE* stds){\n\tconst DTYPE coeff = 1 / (DTYPE) window;\n\tsize_t a = blockIdx.x * blockDim.x + threadIdx.x;\n\tsize_t b = blockIdx.x * blockDim.x + threadIdx.x + window;\n\tif(a == 0){\n\t\tstds[a] = sqrt((squares[window - 1] * coeff) - (means[a] * means[a]));\n\t}\n\telse if(b < size + window) {\n\t\tstds[a] = sqrt(((squares[b - 1] - squares[a - 1]) * coeff) - (means[a] * means[a]));\n    }\n}\n\n\ntemplate<class DTYPE>\n__global__ void elementwise_multiply_inplace(const DTYPE* A, DTYPE *B, const int size)\n{\n    int tid = blockIdx.x * blockDim.x + threadIdx.x;\n    if(tid < size) {\n       B[tid] *= A[tid];\n    }\n}\n\ntemplate<>\n__global__ void elementwise_multiply_inplace(const cuDoubleComplex* A, cuDoubleComplex* B, const int size)\n{\n    int tid = blockIdx.x * blockDim.x + threadIdx.x;\n    if(tid < size) {\n       B[tid] = cuCmul(A[tid], B[tid]);\n    }\n}\n\n\n// A is input unaligned sliding dot products produced by ifft\n// out is the computed vector of distances\ntemplate<class DTYPE>\n__global__ void normalized_aligned_distance(const DTYPE* A, DTYPE* out, DTYPE * lastzs,\n  const DTYPE * AMean, const DTYPE* ASigma,\n  const unsigned int windowSize, const int exclusionZone,\n  const unsigned int ProfileLength, DTYPE* profile,\n  unsigned int * profile_idx, const unsigned int scratch, mp_entry *profile_entry)\n  {\n\n    int thID = blockIdx.x * blockDim.x + threadIdx.x;\n    int i = 1;\n    int j = thID + i;\n\n    DTYPE lastz = lastzs[thID];\n\n    if(j > exclusionZone)\n    {\n//      while(j < ProfileLength)\n//      {\n        lastz  = lastz + (A[j + windowSize - 1] * A[i + windowSize - 1]) - (A[j - 1] * A[i - 1]);\n        DTYPE distance = max(2 * (windowSize - (lastz -  AMean[j] * AMean[i] * windowSize) / (ASigma[j] * ASigma[i])), 0.0);\n\n        if (distance < profile_entry[j].floats[0])\n        {\n          MPatomicMin((unsigned long long int*)&profile_entry[j], distance, i);\n        }\n        if (distance < profile_entry[i].floats[0])\n        {\n          MPatomicMin((unsigned long long int*)&profile_entry[i], distance, j);\n        }\n        i++;\n        j++;\n  //    }\n    }\n  }\n\n\ntemplate<class DTYPE>\n__global__ void initialize_lastzs(const DTYPE* A, DTYPE* out, DTYPE * lastzs_last,\n  const DTYPE * AMean, const DTYPE* ASigma,  const unsigned int windowSize, const unsigned int exclusionZone,\n  const unsigned int ProfileLength, DTYPE* profile,\n  unsigned int * profile_idx)\n{\n    int j = blockIdx.x * blockDim.x + threadIdx.x;\n\n    if((j > exclusionZone) && (j < ProfileLength)) {\n       DTYPE lastz = 0;\n       for (int index = j; index < windowSize + j; index++)\n       {\n         lastz += A[index] * A[index-j];\n       }\n\n       DTYPE distance = max(2 * (windowSize - (lastz -  AMean[j] * AMean[0] * windowSize) / (ASigma[j] * ASigma[0])), 0.0);\n       // Update the distance profile\n       out[j] = distance;\n       // Update the matrix profile if needed\n       if(profile[j] > distance) {\n         profile[j] = distance;\n         profile_idx[j] = 0;\n       }\n       if(j < ProfileLength) lastzs_last[j] = lastz;\n\n    }\n    else if (j < ProfileLength)\n    {\n      out[j] = DBL_MAX;\n    }\n}\n\n\ntemplate<class DTYPE>\n__host__ void distance_profile(const DTYPE* A, DTYPE* QT, DTYPE * lastzs,\n  DTYPE *profile, unsigned int *profile_idx, const DTYPE * AMean, const DTYPE * ASigma, const int timeSeriesLength,\n  const int windowSize,const int exclusionZone, const unsigned int i, mp_entry *profile_entry)\n  {\n    const int ProfileLength = timeSeriesLength - windowSize + 1;\n\n    dim3 grid(ceil(ProfileLength / (float) THREADS_PER_BLOCK), 1, 1);\n    dim3 block(THREADS_PER_BLOCK, 1, 1);\n\n    normalized_aligned_distance<DTYPE><<<grid, block>>>(A, QT, lastzs, AMean, ASigma,windowSize,\n      exclusionZone, ProfileLength,profile, profile_idx, i, profile_entry);\n    gpuErrchk(cudaPeekAtLastError());\n\n  }\n\n// Reduction kernel, upper layer\n// This reduction was adapted from the nvidia whitepaper:\n// http://developer.download.nvidia.com/compute/cuda/1.1-Beta/x86_website/projects/reduction/doc/reduction.pdf\ntemplate <class DTYPE, unsigned int blockSize>\n__global__ void reduce(const DTYPE *g_idata, DTYPE *g_odata, unsigned int *g_oloc,  unsigned int ProfileLength) {\n\t__shared__ DTYPE sdata[blockSize];\n\t__shared__ DTYPE sloc[blockSize];\n\tunsigned int tid = threadIdx.x;\n\tunsigned int i = blockIdx.x*(blockSize*2) + tid;\n\tunsigned int gridSize = blockSize*2*gridDim.x;\n\tDTYPE temp;\n\tunsigned int temploc;\n\tsdata[tid] = DBL_MAX;\n\twhile (i < ProfileLength) {\n\t\tif (i + blockSize < ProfileLength)\n\t\t{\n\t\t\tif (g_idata[i] < g_idata[i+blockSize])\n\t\t\t{\n\t\t\t\ttemp=g_idata[i];\n\t\t\t\ttemploc=i;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\ttemp=g_idata[i+blockSize];\n\t\t\t\ttemploc = i+blockSize;\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttemp = g_idata[i];\n\t\t\ttemploc = i;\n\t\t}\n\t\tif (sdata[tid] > temp)\n\t\t{\n\t\t\tsdata[tid] = temp;\n\t\t\tsloc[tid] = temploc;\n\t\t}\n\t\ti += gridSize;\n\t}\n\t__syncthreads();\n\tif (blockSize >= 1024) {\n\t\tif (tid < 512 && sdata[tid] > sdata[tid + 512])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 512];\n\t\t\tsloc[tid] = sloc[tid + 512];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 512 ) {\n\t\tif (tid < 256 && sdata[tid] > sdata[tid + 256])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 256];\n\t\t\tsloc[tid] = sloc[tid + 256];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 256) {\n\t\tif (tid < 128 && sdata[tid] > sdata[tid + 128])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 128];\n\t\t\tsloc[tid] = sloc[tid + 128];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 128) {\n\t\tif (tid < 64 && sdata[tid] > sdata[tid + 64])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 64];\n\t\t\tsloc[tid] = sloc[tid + 64];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 64) {\n\t\tif (tid < 32 && sdata[tid] > sdata[tid + 32])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 32];\n\t\t\tsloc[tid] = sloc[tid + 32];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 32) {\n\t\tif (tid < 16 && sdata[tid] > sdata[tid + 16])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 16];\n\t\t\tsloc[tid] = sloc[tid + 16];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 16) {\n\t\tif (tid < 8 && sdata[tid] > sdata[tid + 8])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 8];\n\t\t\tsloc[tid] = sloc[tid + 8];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 8) {\n\t\tif (tid < 4 && sdata[tid] > sdata[tid + 4])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 4];\n\t\t\tsloc[tid] = sloc[tid + 4];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 4) {\n\t\tif (tid < 2 && sdata[tid] > sdata[tid + 2])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 2];\n\t\t\tsloc[tid] = sloc[tid + 2];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 2) {\n\t\tif (tid == 0)\n\t\t{\n\t\t\tif (sdata[0] <= sdata[1])\n\t\t\t{\n\t\t\t\tg_odata[blockIdx.x] = sdata[0];\n\t\t\t\tg_oloc[blockIdx.x] = sloc[0];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tg_odata[blockIdx.x] = sdata[1];\n\t\t\t\tg_oloc[blockIdx.x] = sloc[1];\n\t\t\t}\n\t\t}\n\t}\n\telse\n\t{\n\t\tif (tid == 0)\n\t\t{\n\t\t\tg_odata[blockIdx.x] = sdata[0];\n\t\t\tg_oloc[blockIdx.x] = sloc[0];\n\t\t}\n\t}\n}\n\n//reduction kernel, lower layer\ntemplate <class DTYPE, unsigned int blockSize>\n__global__ void reducelast(DTYPE *g_idata, unsigned int *g_iloc,\n  unsigned int start_loc, DTYPE* profilei, unsigned int* profileidxi, unsigned int n) {\n\n\t__shared__ DTYPE sdata[blockSize];\n\t__shared__ DTYPE sloc[blockSize];\n\tunsigned int tid = threadIdx.x;\n\tunsigned int i = blockIdx.x*(blockSize*2) + tid;\n\tunsigned int gridSize = blockSize*2*gridDim.x;\n\tDTYPE temp;\n\tunsigned int temploc;\n\tsdata[tid] = DBL_MAX;\n\tDTYPE minval;\n\tunsigned int minloc;\n\twhile (i < n) {\n\t\tif (i + blockSize <n)\n\t\t{\n\t\t\tif (g_idata[i] < g_idata[i+blockSize])\n\t\t\t{\n\t\t\t\ttemp=g_idata[i];\n\t\t\t\ttemploc=g_iloc[i];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\ttemp=g_idata[i+blockSize];\n\t\t\t\ttemploc = g_iloc[i+blockSize];\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttemp = g_idata[i];\n\t\t\ttemploc = g_iloc[i];\n\t\t}\n\t\tif (sdata[tid] > temp)\n\t\t{\n\t\t\tsdata[tid] = temp;\n\t\t\tsloc[tid] = temploc;\n\t\t}\n\t\ti += gridSize;\n\t}\n\t__syncthreads();\n\tif (blockSize >= 1024) {\n\t\tif (tid < 512 && sdata[tid] > sdata[tid + 512])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 512];\n\t\t\tsloc[tid] = sloc[tid + 512];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 512 ) {\n\t\tif (tid < 256 && sdata[tid] > sdata[tid + 256])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 256];\n\t\t\tsloc[tid] = sloc[tid + 256];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 256) {\n\t\tif (tid < 128 && sdata[tid] > sdata[tid + 128])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 128];\n\t\t\tsloc[tid] = sloc[tid + 128];\n\t\t}\n\t\t__syncthreads();\n\t}\n\tif (blockSize >= 128) {\n\t\tif (tid < 64 && sdata[tid] > sdata[tid + 64])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 64];\n\t\t\tsloc[tid] = sloc[tid + 64];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 64) {\n\t\tif (tid < 32 && sdata[tid] > sdata[tid + 32])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 32];\n\t\t\tsloc[tid] = sloc[tid + 32];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 32) {\n\t\tif (tid < 16 && sdata[tid] > sdata[tid + 16])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 16];\n\t\t\tsloc[tid] = sloc[tid + 16];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 16) {\n\t\tif (tid < 8 && sdata[tid] > sdata[tid + 8])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 8];\n\t\t\tsloc[tid] = sloc[tid + 8];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 8) {\n\t\tif (tid < 4 && sdata[tid] > sdata[tid + 4])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 4];\n\t\t\tsloc[tid] = sloc[tid + 4];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 4) {\n\t\tif (tid < 2 && sdata[tid] > sdata[tid + 2])\n\t\t{\n\t\t\tsdata[tid] = sdata[tid + 2];\n\t\t\tsloc[tid] = sloc[tid + 2];\n\t\t}\n\t\t__syncthreads();\n\t}\n\n\tif (blockSize >= 2) {\n\t\tif (tid == 0)\n\t\t{\n\t\t\tif (sdata[0] <= sdata[1])\n\t\t\t{\n\t\t\t\tminval = sdata[0];\n\t\t\t\tminloc = sloc[0];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tminval = sdata[1];\n\t\t\t\tminloc = sloc[1];\n\t\t\t}\n\t\t}\n\t}\n\telse\n\t{\n\t\tif (tid == 0)\n\t\t{\n\t\t\tminval = sdata[0];\n\t\t\tminloc = sloc[0];\n\t\t}\n\t}\n\n\tif (tid==0)\n\t{\n\t\tif (minval<(*profilei))\n\t\t{\n\t\t\t(*profilei)=minval;\n\t\t\t(*profileidxi)=minloc+start_loc;\n\t\t}\n\t}\n\n}\n\ntemplate<class DTYPE>\nvoid reducemain(DTYPE* vd, unsigned int start_loc, unsigned int max_block_num, unsigned int max_thread_num, unsigned int n, DTYPE* profile, unsigned int* profileidx, unsigned int i, DTYPE* reduced_result, unsigned int* reduced_loc)\n{\n\n\tif (n==0) //if this happens, there's an error\n\t\treturn;\n\tif (max_thread_num>1024)\n\t\tmax_thread_num=1024;\n\n\tunsigned int * middle_loc_pointer=reduced_loc;\n\n\n\tunsigned int num_threads=max_thread_num;\n\n\tunsigned int num_blocks=n/(num_threads*2);\n\tif (n%(num_threads*2)!=0)\n\t\tnum_blocks++;\n\tif (num_blocks>=max_block_num)\n\t\tnum_blocks=max_block_num;\n\tDTYPE *middle_pointer = NULL;\n\tunsigned int curn;\n\tif (num_blocks>1) //upperlevel reduction\n\t{\n\t\tmiddle_pointer=reduced_result;\n\t\tcurn=num_blocks;\n\t\tswitch (num_threads)\n\t\t{\n\t\t\tcase 1024:\n\t\t\t\treduce<DTYPE, 1024><<<num_blocks,1024>>>(vd + start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 512:\n\t\t\t\treduce<DTYPE, 512><<<num_blocks,512>>>(vd + start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 256:\n\t\t\t\treduce<DTYPE, 256><<<num_blocks,256>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 128:\n\t\t\t\treduce<DTYPE, 128><<<num_blocks,128>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 64:\n\t\t\t\treduce<DTYPE, 64><<<num_blocks,64>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 32:\n\t\t\t\treduce<DTYPE, 32><<<num_blocks,32>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 16:\n\t\t\t\treduce<DTYPE, 16><<<num_blocks,16>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 8:\n\t\t\t\treduce<DTYPE, 8><<<num_blocks,8>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 4:\n\t\t\t\treduce<DTYPE, 4><<<num_blocks,4>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tcase 2:\n\t\t\t\treduce<DTYPE, 2><<<num_blocks,2>>>(vd+start_loc,reduced_result,reduced_loc,n); break;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t}\n\t        gpuErrchk( cudaPeekAtLastError() );\n\t}\n\telse\n\t{\n\t\tmiddle_pointer=vd+start_loc;\n\t\tcurn=n;\n        auto ptr = thrust::device_pointer_cast(reduced_loc);\n\t\tthrust::sequence(ptr,ptr+curn);\n\t}\n\n\n\tnum_threads=floor(pow(2,ceil(log(curn)/log(2))-1));\n\tif (num_threads>max_thread_num)\n\t\tnum_threads=max_thread_num;\n\tswitch (num_threads)\n\t{\n\t\tcase 1024:\n\t\t\treducelast<DTYPE,1024><<<1,1024>>>(middle_pointer, middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 512:\n\t\t\treducelast<DTYPE,512><<<1,512>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i,  curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 256:\n\t\t\treducelast<DTYPE,256><<<1,256>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 128:\n\t\t\treducelast<DTYPE,128><<<1,128>>>(middle_pointer,middle_loc_pointer, start_loc,  profile+i, profileidx+i,curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 64:\n\t\t\treducelast<DTYPE,64><<<1,64>>>(middle_pointer,middle_loc_pointer, start_loc,  profile+i, profileidx+i,curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 32:\n\t\t\treducelast<DTYPE,32><<<1,32>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 16:\n\t\t\treducelast<DTYPE,16><<<1,16>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i,curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\treducelast<DTYPE,8><<<1,8>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i,curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\treducelast<DTYPE,4><<<1,4>>>(middle_pointer,middle_loc_pointer, start_loc,  profile+i, profileidx+i,curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\treducelast<DTYPE,2><<<1,2>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\treducelast<DTYPE,1><<<1,1>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\treducelast<DTYPE,1><<<1,1>>>(middle_pointer,middle_loc_pointer, start_loc, profile+i, profileidx+i, curn);\n\t        \tgpuErrchk( cudaPeekAtLastError() );\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t}\n}\n\ntemplate<class DTYPE>\nstruct square_op : public thrust::unary_function<DTYPE,DTYPE>\n{\n  __host__ __device__\n  DTYPE operator()(DTYPE x) const\n  {\n    return x * x;\n  }\n};\n\ntemplate<class DTYPE>\nvoid compute_statistics(const DTYPE *T, DTYPE *means, DTYPE *stds, DTYPE *scratch, size_t n, size_t m)\n{\n    square_op<DTYPE> sqr;\n    dim3 grid(ceil(n / (double) THREADS_PER_BLOCK), 1,1);\n    dim3 block(THREADS_PER_BLOCK, 1, 1);\n    thrust::device_ptr<const DTYPE> dev_ptr_T = thrust::device_pointer_cast(T);\n    thrust::device_ptr<DTYPE> dev_ptr_scratch = thrust::device_pointer_cast(scratch);\n\n\tthrust::inclusive_scan(dev_ptr_T, dev_ptr_T + n + m - 1, dev_ptr_scratch, thrust::plus<DTYPE>());\n    sliding_mean<DTYPE><<<grid, block>>>(scratch, m, n, means);\n\tthrust::transform_inclusive_scan(dev_ptr_T, dev_ptr_T + n + m - 1, dev_ptr_scratch, sqr,thrust::plus<DTYPE>());\n    sliding_std<DTYPE><<<grid,block>>>(scratch, m, n, means, stds);\n}\n\n\n\ntemplate<class DTYPE>\nvoid STREAMP(DTYPE* T, const int timeSeriesLength, const int windowSize, DTYPE* profile, unsigned int* profile_idxs,  mp_entry *profile_with_idx)\n{\n\n  int exclusionZone = windowSize / 4;\n  size_t ProfileLength = timeSeriesLength - windowSize + 1;\n  DTYPE * AMean, * ASigma, *QT, *lastzs, *reduced_result;\n\n  dim3 block(THREADS_PER_BLOCK,1,1);\n  dim3 grid(ceil(ProfileLength / (float) THREADS_PER_BLOCK), 1, 1);\n\n  unsigned int *reduced_loc;\n\n  //clock_t start, now;\n  const unsigned int max_block_num=2048;\n  const unsigned int max_thread_num=1024;\n  unsigned int middle_loc_size=max_block_num>max_thread_num?max_block_num:max_thread_num;\n // printf(\"size = %d, window = %d, exclusion = %d\\n\", ProfileLength, windowSize, exclusionZone);\n\n  //start = clock();\n\n  cudaMalloc(&QT, ProfileLength * sizeof(DTYPE));\n  cudaMalloc(&AMean, ProfileLength * sizeof(DTYPE));\n  cudaMalloc(&ASigma, ProfileLength * sizeof(DTYPE));\n  cudaMalloc(&lastzs, ProfileLength * sizeof(DTYPE));\n\n  cudaMalloc(&reduced_result, max_block_num * sizeof(DTYPE));\n  cudaMalloc(&reduced_loc, middle_loc_size * sizeof(unsigned int));\n\n  //now = clock();\n  //printf(\"Allocate memory took %lf sec\\n\", (now - start) / (double) CLOCKS_PER_SEC);\n\n  // Precompute statistics\n  //start = clock();\n\n  //Use QT vector as scratch space as we don't need it yet\n  compute_statistics(T, AMean, ASigma, QT, ProfileLength, windowSize);\n  //now = clock();\n // printf(\"Precompute statistics took %lf sec\\n\", (now - start) / (double) CLOCKS_PER_SEC);\n\n  // Initialize profile and lastzs_last\n // start = clock();\n   auto begin = std::chrono::high_resolution_clock::now();\n\n  initialize_lastzs<DTYPE><<<grid, block>>>(T, QT, lastzs, AMean, ASigma,  windowSize, exclusionZone,\n    ProfileLength, profile, profile_idxs);\n\n  reducemain(QT, 0, 2048, 1024, ProfileLength, profile, profile_idxs, 0, reduced_result, reduced_loc);\n\n  MPIDXCombine combiner;\n  auto ptr_prof = thrust::device_pointer_cast(profile);\n  auto ptr_idx = thrust::device_pointer_cast(profile_idxs);\n  auto ptr_comb = thrust::device_pointer_cast(profile_with_idx);\n  thrust::transform(ptr_prof, ptr_prof + ProfileLength, ptr_idx, ptr_comb, combiner);\n\n  cudaDeviceSynchronize();\n\n  // compute the distance profile\n  distance_profile<DTYPE>(T, QT, lastzs, profile, profile_idxs, AMean, ASigma, timeSeriesLength,\n    windowSize, exclusionZone, 1, profile_with_idx);\n\n  cudaDeviceSynchronize();\n  //now = clock();\n  auto end = std::chrono::high_resolution_clock::now(); \n  std::cout << \"STREAMP time: \"<< (float) std::chrono::duration_cast<std::chrono::microseconds>(end-begin).count() / 1000 << \" ms.\" << std::endl;\n\n  cudaFree(QT);\n  cudaFree(AMean);\n  cudaFree(ASigma);\n  cudaFree(lastzs);\n}\n\n//Reads input time series from file\ntemplate<class DTYPE>\nvoid readFile(const char* filename, vector<DTYPE>& v, const char *format_str)\n{\n\tFILE* f = fopen( filename, \"r\");\n\tif(f == NULL){\n\t\tprintf(\"Unable to open %s for reading, please make sure it exists\\n\", filename);\n\t\texit(0);\n\t}\n\tDTYPE num;\n\twhile(!feof(f)){\n\t\t\tfscanf(f, format_str, &num);\n\t\t\tv.push_back(num);\n    }\n\tv.pop_back();\n\tfclose(f);\n}\n\nint main(int argc, char **argv)\n{\n  if (argc != 4) {\n    printf(\"Usage: <subseq length> <input file> <output file>\\n\");\n    exit(0);\n  }\n\n  int nDevices;\n  double *T, *profile;\n  unsigned int *idxs;\n  mp_entry *profile_with_idx;\n  int windowSize = atoi(argv[1]);\n  char *filename = argv[2];\n  //clock_t start, now;\n  vector<double> T_host;\n\n\n  cudaGetDeviceCount(&nDevices);\n  vector<cudaDeviceProp> device_info(nDevices);\n\n /* printf(\"Number of CUDA devices: %d\\n\",nDevices);\n\n  for (int i = 0; i < nDevices; ++i) {\n    cudaGetDeviceProperties(&device_info.at(i), i);\n    printf(\"Device Number: %d\\n\", i);\n    printf(\"  Device name: %s\\n\", device_info.at(i).name);\n    printf(\"  Memory Clock Rate (KHz): %d\\n\",\n    device_info.at(i).memoryClockRate);\n    printf(\"  Memory Bus Width (bits): %d\\n\",\n    device_info.at(i).memoryBusWidth);\n    printf(\"  Peak Memory Bandwidth (GB/s): %f\\n\\n\",\n      2.0*device_info.at(i).memoryClockRate*(device_info.at(i).memoryBusWidth/8)/1.0e6);\n  }*/\n\n // std::cout << \"Enter the device number to use: \" << '\\n';\n  //std::cin >> selectedDevice;\n\n  //cudaSetDevice(selectedDevice);\n  cudaSetDevice(0);\n  cudaFree(0);\n\n  //start = clock();\n  readFile<double>(filename, T_host, \"%lf\");\n  //now = clock();\n\n // printf(\"Time taken to read date from file: %lf seconds\\n\", (now - start) / (double) CLOCKS_PER_SEC);\n\n  vector<double> profile_host(T_host.size() - windowSize + 1, DBL_MAX);\n  vector<unsigned int> index_host(profile_host.size(), 0);\n  vector<mp_entry> profile_with_idx_h(profile_host.size());\n\n  //start = clock();\n  cudaMalloc(&T, T_host.size() * sizeof(double));\n  cudaMemcpy(T, T_host.data(), T_host.size() * sizeof(double), cudaMemcpyHostToDevice);\n  cudaMalloc(&profile, profile_host.size() * sizeof(double));\n  cudaMemcpy(profile, profile_host.data(), profile_host.size() * sizeof(double), cudaMemcpyHostToDevice);\n  cudaMalloc(&idxs, index_host.size() * sizeof(unsigned int));\n  cudaMalloc(&profile_with_idx, profile_host.size() * sizeof(mp_entry));\n  //now = clock();\n\n // printf(\"Time taken to allocate T and profile and transfer to device: %lf seconds\\n\", (now - start) / (double) CLOCKS_PER_SEC);\n\n  // Do SCRIMP\n  STREAMP<double>(T, T_host.size(), windowSize, profile, idxs, profile_with_idx);\n\n  //start = clock();\n  cudaMemcpy(&profile_with_idx_h[0], profile_with_idx, profile_host.size() * sizeof(mp_entry), cudaMemcpyDeviceToHost);\n  //now = clock();\n\n  //printf(\"Time taken to copy result to host: %lf seconds\\n\", (now - start) / (double) CLOCKS_PER_SEC);\n\n  //printf(\"writing result to files\\n\");\n  FILE* f1 = fopen( argv[3], \"w\");\n  for(int i = 0; i < profile_host.size(); ++i){\n    fprintf(f1, \"%.10f %u\\n\", sqrt(profile_with_idx_h[i].floats[0]) , profile_with_idx_h[i].ints[1]);\n  }\n\n  fclose(f1);\n  gpuErrchk(cudaDeviceSynchronize());\n  gpuErrchk(cudaDeviceReset());\n\n  cudaFree(T);\n  cudaFree(profile);\n  cudaFree(profile_with_idx);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/gpu/launch.sh",
    "content": "./STREAMP 256 inputs/randomlist33M.txt /dev/null \n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/baselines/gpu/randlist.py",
    "content": "import random\nimport sys\n\n# Generates a random list of floating point values between 0 and 10\nfd = open(sys.argv[2], \"w\")\n\nfor i in range(0, int(sys.argv[1])):\n    fd.write(str(random.randint(0, 1000000000) / float(100000000)) + \"\\n\")\n\nfd.close()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/dpu/task.c",
    "content": "/*\n * STREAMP implementation of Matrix Profile with multiple tasklets\n *\n */\n\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <mram.h>\n#include <barrier.h>\n#include \"common.h\"\n\n#define DOTPIP BLOCK_SIZE / sizeof(DTYPE)\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_result_t DPU_RESULTS[NR_TASKLETS];\n\n// Dot product\nvoid __attribute__ ((noinline)) dot_product(DTYPE *vectorA, DTYPE *vectorA_aux, DTYPE *vectorB, DTYPE * result) {\n\n\tfor(uint32_t i = 0; i <  BLOCK_SIZE / sizeof(DTYPE); i++)\n\t{\n\t\tfor(uint32_t j = 0; j < DOTPIP; j++)\n\t\t{\n\t\t\tif((j + i) > BLOCK_SIZE / sizeof(DTYPE) - 1)\n\t\t\t{\n\t\t\t\tresult[j] += vectorA_aux[(j + i) - BLOCK_SIZE / sizeof(DTYPE)]  * vectorB[i];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tresult[j] += vectorA[j + i] * vectorB[i];\n\t\t\t}\n\t\t}\n\t}\n}\n\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint(*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void){\n\t// Kernel\n\treturn kernels[DPU_INPUT_ARGUMENTS.kernel]();\n}\n\n// main_kernel1\nint main_kernel1() {\n\tunsigned int tasklet_id = me();\n#if PRINT\n\tprintf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n\tif(tasklet_id == 0){\n\t\tmem_reset(); // Reset the heap\n\t}\n\t// Barrier\n\tbarrier_wait(&my_barrier);\n\n\t// Input arguments\n\tuint32_t query_length  = DPU_INPUT_ARGUMENTS.query_length;\n\tDTYPE query_mean       = DPU_INPUT_ARGUMENTS.query_mean;\n\tDTYPE query_std        = DPU_INPUT_ARGUMENTS.query_std;\n\tuint32_t slice_per_dpu = DPU_INPUT_ARGUMENTS.slice_per_dpu;\n\n\t// Boundaries for current tasklet\n\tuint32_t myStartElem = tasklet_id  * (slice_per_dpu / (NR_TASKLETS));\n\tuint32_t myEndElem   = myStartElem + (slice_per_dpu / (NR_TASKLETS)) - 1;\n\n\t// Check time series limit\n\tif(myEndElem > slice_per_dpu - query_length) myEndElem = slice_per_dpu - query_length;\n\n\t// Starting address of the current processing block in MRAM\n\tuint32_t mem_offset = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t// Starting address of the query subsequence\n\tuint32_t current_mram_block_addr_query = (uint32_t)(mem_offset);\n\tmem_offset += query_length * sizeof(DTYPE);\n\n\t// Starting address of the time series slice\n\tmem_offset += myStartElem * sizeof(DTYPE);\n\tuint32_t starting_offset_ts = mem_offset;\n\tuint32_t current_mram_block_addr_TS = (uint32_t) mem_offset;\n\n\t// Starting address of the time series means\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSMean = (uint32_t)(mem_offset);\n\n\t// Starting address of the time series standard deviations\n\tmem_offset += (slice_per_dpu + query_length) * sizeof(DTYPE);\n\tuint32_t current_mram_block_addr_TSSigma = (uint32_t)(mem_offset);\n\n\t// Initialize local caches to store the MRAM blocks\n\tDTYPE *cache_TS       = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TS_aux   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_query    = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSMean   = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_TSSigma  = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\tDTYPE *cache_dotprods = (DTYPE *) mem_alloc(BLOCK_SIZE);\n\n\t// Create result structure pointer\n\tdpu_result_t *result = &DPU_RESULTS[tasklet_id];\n\n\t// Auxiliary variables\n\tDTYPE distance;\n\tDTYPE min_distance = DTYPE_MAX;\n\tuint32_t min_index = 0;\n\n\n\tfor(uint32_t i = myStartElem; i < myEndElem; i+= (BLOCK_SIZE / sizeof(DTYPE)))\n\t{\n\t\tfor(uint32_t d = 0; d < DOTPIP; d++)\n\t\t\tcache_dotprods[d] = 0;\n\n\t\tcurrent_mram_block_addr_TS    = (uint32_t) starting_offset_ts + (i - myStartElem) * sizeof(DTYPE);\n\t\tcurrent_mram_block_addr_query = (uint32_t) DPU_MRAM_HEAP_POINTER;\n\n\t\tfor(uint32_t j = 0; j < (query_length) / (BLOCK_SIZE / sizeof(DTYPE)); j++)\n\t\t{\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS, cache_TS, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TS + BLOCK_SIZE, cache_TS_aux, BLOCK_SIZE);\n\t\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_query, cache_query, BLOCK_SIZE);\n\n\t\t\tcurrent_mram_block_addr_TS    += BLOCK_SIZE;\n\t\t\tcurrent_mram_block_addr_query += BLOCK_SIZE;\n\t\t\tdot_product(cache_TS, cache_TS_aux, cache_query, cache_dotprods);\n\t\t}\n\n\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSMean, cache_TSMean, BLOCK_SIZE);\n\t\tmram_read((__mram_ptr void const *) current_mram_block_addr_TSSigma, cache_TSSigma, BLOCK_SIZE);\n\t\tcurrent_mram_block_addr_TSMean  += BLOCK_SIZE;\n\t\tcurrent_mram_block_addr_TSSigma += BLOCK_SIZE;\n\n\t\tfor (uint32_t k = 0; k < (BLOCK_SIZE / sizeof(DTYPE)); k++)\n\t\t{\n\t\t\tdistance = 2 * ((DTYPE) query_length - (cache_dotprods[k] - (DTYPE) query_length * cache_TSMean[k]\n\t\t\t\t\t\t* query_mean) / (cache_TSSigma[k] * query_std));\n\n\t\t\tif(distance < min_distance)\n\t\t\t{\n\t\t\t\tmin_distance =  distance;\n\t\t\t\tmin_index    =  i + k;\n\t\t\t}\n\t\t}\n\t}\n\n\t// Save the result\n\tresult->minValue = min_distance;\n\tresult->minIndex = min_index;\n\n\treturn 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/host/app.c",
    "content": "/**\n * app.c\n * TS Host Application Source File\n *\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <math.h>\n#include <time.h>\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n#include \"params.h\"\n#include \"timer.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#define DPU_BINARY \"./bin/ts_dpu\"\n\n#define MAX_DATA_VAL 127\n\nstatic DTYPE tSeries[1 << 26];\nstatic DTYPE query  [1 << 15];\nstatic DTYPE AMean  [1 << 26];\nstatic DTYPE ASigma [1 << 26];\nstatic DTYPE minHost;\nstatic DTYPE minHostIdx;\n\n// Create input arrays\nstatic DTYPE *create_test_file(unsigned int ts_elements, unsigned int query_elements) {\n\tsrand(0);\n\n\tfor (uint64_t i = 0; i < ts_elements; i++)\n\t{\n\t\ttSeries[i] = i % MAX_DATA_VAL;\n\t}\n\n\tfor (uint64_t i = 0; i < query_elements; i++)\n\t{\n\t\tquery[i] = i % MAX_DATA_VAL;\n\t}\n\n\treturn tSeries;\n}\n\n// Compute output in the host\nstatic void streamp(DTYPE* tSeries, DTYPE* AMean, DTYPE* ASigma, int ProfileLength,\n\t\tDTYPE* query, int queryLength, DTYPE queryMean, DTYPE queryStdDeviation)\n{\n\tDTYPE distance;\n\tDTYPE dotprod;\n\tminHost    = INT32_MAX;\n\tminHostIdx = 0;\n\n\tfor (int subseq = 0; subseq < ProfileLength; subseq++)\n\t{\n\t\tdotprod = 0;\n\t\tfor(int j = 0; j < queryLength; j++)\n\t\t{\n\t\t\tdotprod += tSeries[j + subseq] * query[j];\n\t\t}\n\n\t\tdistance = 2 * (queryLength - (dotprod - queryLength * AMean[subseq]\n\t\t\t\t\t* queryMean) / (ASigma[subseq] * queryStdDeviation));\n\n\t\tif(distance < minHost)\n\t\t{\n\t\t\tminHost = distance;\n\t\t\tminHostIdx = subseq;\n\t\t}\n\t}\n}\n\nstatic void compute_ts_statistics(unsigned int timeSeriesLength, unsigned int ProfileLength, unsigned int queryLength)\n{\n\tdouble* ACumSum = malloc(sizeof(double) * timeSeriesLength);\n\tACumSum[0] = tSeries[0];\n\tfor (uint64_t i = 1; i < timeSeriesLength; i++)\n\t\tACumSum[i] = tSeries[i] + ACumSum[i - 1];\n\tdouble* ASqCumSum = malloc(sizeof(double) * timeSeriesLength);\n\tASqCumSum[0] = tSeries[0] * tSeries[0];\n\tfor (uint64_t i = 1; i < timeSeriesLength; i++)\n\t\tASqCumSum[i] = tSeries[i] * tSeries[i] + ASqCumSum[i - 1];\n\tdouble* ASum = malloc(sizeof(double) * ProfileLength);\n\tASum[0] = ACumSum[queryLength - 1];\n\tfor (uint64_t i = 0; i < timeSeriesLength - queryLength; i++)\n\t\tASum[i + 1] = ACumSum[queryLength + i] - ACumSum[i];\n\tdouble* ASumSq = malloc(sizeof(double) * ProfileLength);\n\tASumSq[0] = ASqCumSum[queryLength - 1];\n\tfor (uint64_t i = 0; i < timeSeriesLength - queryLength; i++)\n\t\tASumSq[i + 1] = ASqCumSum[queryLength + i] - ASqCumSum[i];\n\tdouble * AMean_tmp = malloc(sizeof(double) * ProfileLength);\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t\tAMean_tmp[i] = ASum[i] / queryLength;\n\tdouble* ASigmaSq = malloc(sizeof(double) * ProfileLength);\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t\tASigmaSq[i] = ASumSq[i] / queryLength - AMean[i] * AMean[i];\n\tfor (uint64_t i = 0; i < ProfileLength; i++)\n\t{\n\t\tASigma[i] = sqrt(ASigmaSq[i]);\n\t\tAMean[i]  = (DTYPE) AMean_tmp[i];\n\t}\n\n\tfree(ACumSum);\n\tfree(ASqCumSum);\n\tfree(ASum);\n\tfree(ASumSq);\n\tfree(ASigmaSq);\n\tfree(AMean_tmp);\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n\t// Timer declaration\n\tTimer timer;\n\n\tstruct Params p = input_params(argc, argv);\n\tstruct dpu_set_t dpu_set, dpu;\n\tuint32_t nr_of_dpus;\n\n\t// Allocate DPUs and load binary\n\tDPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n\tDPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n\tDPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n\n#if ENERGY\n\tstruct dpu_probe_t probe;\n\tDPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n\tunsigned long int ts_size =  p.input_size_n;\n\tconst unsigned int query_length = p.input_size_m;\n\n\t// Size adjustment\n\tif(ts_size % (nr_of_dpus * NR_TASKLETS*query_length))\n\t\tts_size = ts_size +  (nr_of_dpus * NR_TASKLETS * query_length - ts_size % (nr_of_dpus * NR_TASKLETS*query_length));\n\n\t// Create an input file with arbitrary data\n\tcreate_test_file(ts_size, query_length);\n\tcompute_ts_statistics(ts_size, ts_size - query_length, query_length);\n\n\tDTYPE query_mean;\n\tdouble queryMean = 0;\n\tfor(unsigned i = 0; i < query_length; i++) queryMean += query[i];\n\tqueryMean /= (double) query_length;\n\tquery_mean = (DTYPE) queryMean;\n\n\tDTYPE query_std;\n\tdouble queryStdDeviation;\n\tdouble queryVariance = 0;\n\tfor(unsigned i = 0; i < query_length; i++)\n\t{\n\t\tqueryVariance += (query[i] - queryMean) * (query[i] - queryMean);\n\t}\n\tqueryVariance /= (double) query_length;\n\tqueryStdDeviation = sqrt(queryVariance);\n\tquery_std = (DTYPE) queryStdDeviation;\n\n\tDTYPE *bufferTS     = tSeries;\n\tDTYPE *bufferQ      = query;\n\tDTYPE *bufferAMean  = AMean;\n\tDTYPE *bufferASigma = ASigma;\n\n\tuint32_t slice_per_dpu = ts_size / nr_of_dpus;\n\n\tunsigned int kernel = 0;\n\tdpu_arguments_t input_arguments = {ts_size, query_length, query_mean, query_std, slice_per_dpu, 0, kernel};\n\tuint32_t mem_offset;\n\n\tdpu_result_t result;\n\tresult.minValue = INT32_MAX;\n\tresult.minIndex = 0;\n\tresult.maxValue = 0;\n\tresult.maxIndex = 0;\n\n\tfor (int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 1, rep - p.n_warmup);\n\t\tuint32_t i = 0;\n\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tinput_arguments.exclusion_zone = 0;\n\n\t\t\tDPU_ASSERT(dpu_copy_to(dpu, \"DPU_INPUT_ARGUMENTS\", 0, (const void *) &input_arguments, sizeof(input_arguments)));\n\t\t\ti++;\n\t\t}\n\n\t\ti = 0;\n\t\tmem_offset = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i)\n\t\t{\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferQ));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, query_length * sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tmem_offset += query_length * sizeof(DTYPE);\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferTS + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset,(slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tmem_offset += ((slice_per_dpu + query_length) * sizeof(DTYPE));\n\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferAMean + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\n\t\tmem_offset += ((slice_per_dpu + query_length) * sizeof(DTYPE));\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, bufferASigma + slice_per_dpu * i));\n\t\t}\n\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, mem_offset, (slice_per_dpu + query_length)*sizeof(DTYPE), DPU_XFER_DEFAULT));\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstop(&timer, 1);\n\n\t\t// Run kernel on DPUs\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstart(&timer, 2, rep - p.n_warmup);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_start(&probe));\n#endif\n\t\t}\n\n\t\tDPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n\n\t\tif (rep >= p.n_warmup)\n\t\t{\n\t\t\tstop(&timer, 2);\n#if ENERGY\n\t\t\tDPU_ASSERT(dpu_probe_stop(&probe));\n#endif\n\t\t}\n\n\t\tdpu_result_t* results_retrieve[nr_of_dpus];\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 3, rep - p.n_warmup);\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tresults_retrieve[i] = (dpu_result_t*)malloc(NR_TASKLETS * sizeof(dpu_result_t));\n\t\t}\n\n\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tDPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n\t\t}\n\t\tDPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_result_t), DPU_XFER_DEFAULT));\n\n\t\ti = 0;\n\t\tDPU_FOREACH(dpu_set, dpu, i) {\n\t\t\tfor (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n\t\t\t\tif(results_retrieve[i][each_tasklet].minValue < result.minValue && results_retrieve[i][each_tasklet].minValue > 0)\n\t\t\t\t{\n\t\t\t\t\tresult.minValue = results_retrieve[i][each_tasklet].minValue;\n\t\t\t\t\tresult.minIndex = (DTYPE)results_retrieve[i][each_tasklet].minIndex + (i * slice_per_dpu);\n\t\t\t\t}\n\n\t\t\t}\n\t\t\tfree(results_retrieve[i]);\n\t\t\ti++;\n\t\t}\n\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 3);\n\n\n#if PRINT\n\t\tprintf(\"LOGS\\n\");\n\t\tDPU_FOREACH(dpu_set, dpu) {\n\t\t\tDPU_ASSERT(dpu_log_read(dpu, stdout));\n\t\t}\n#endif\n\n\t\tif (rep >= p.n_warmup)\n\t\t\tstart(&timer, 4, rep - p.n_warmup);\n\t\tstreamp(tSeries, AMean, ASigma, ts_size - query_length - 1, query, query_length, query_mean, query_std);\n\t\tif(rep >= p.n_warmup)\n\t\t\tstop(&timer, 4);\n\t}\n\n#if ENERGY\n\tdouble acc_energy, avg_energy, acc_time, avg_time;\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_ACCUMULATE, &acc_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &avg_energy));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_ACCUMULATE, &acc_time));\n\tDPU_ASSERT(dpu_probe_get(&probe, DPU_TIME, DPU_AVERAGE, &avg_time));\n#endif\n\n\t// Print timing results\n\tprintf(\"CPU Version Time (ms): \");\n\tprint(&timer, 4, p.n_reps);\n\tprintf(\"Inter-DPU Time (ms): \");\n\tprint(&timer, 0, p.n_reps);\n\tprintf(\"CPU-DPU Time (ms): \");\n\tprint(&timer, 1, p.n_reps);\n\tprintf(\"DPU Kernel Time (ms): \");\n\tprint(&timer, 2, p.n_reps);\n\tprintf(\"DPU-CPU Time (ms): \");\n\tprint(&timer, 3, p.n_reps);\n\n#if ENERGY\n\tprintf(\"Energy (J): %f J\\t\", avg_energy);\n#endif\n\n\tint status = (minHost == result.minValue);\n\tif (status) {\n\t\tprintf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] results are equal\\n\");\n\t} else {\n\t\tprintf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] results differ!\\n\");\n\t}\n\n\tDPU_ASSERT(dpu_free(dpu_set));\n\n#if ENERGY\n\tDPU_ASSERT(dpu_probe_deinit(&probe));\n#endif\n\n\treturn 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#endif\n\n// Data type\n#define DTYPE int32_t\n#define DTYPE_MAX INT32_MAX\n\ntypedef struct  {\n\tuint32_t ts_length;\n    uint32_t query_length;\n    DTYPE query_mean;\n    DTYPE query_std;\n    uint32_t slice_per_dpu;\n    int32_t exclusion_zone;\n    enum kernels {\n\t\tkernel1 = 0,\n\t\tnr_kernels = 1,\n\t} kernel;\n}dpu_arguments_t;\n\ntypedef struct  {\n    DTYPE minValue;\n    uint32_t minIndex;\n    DTYPE maxValue;\n    uint32_t maxIndex;\n}dpu_result_t;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n  unsigned long  input_size_n;\n  unsigned long  input_size_m;\n  int  n_warmup;\n  int  n_reps;\n}Params;\n\nvoid usage() {\n  fprintf(stderr,\n    \"\\nUsage:  ./program [options]\"\n    \"\\n\"\n    \"\\nGeneral options:\"\n    \"\\n    -h        help\"\n    \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n    \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n    \"\\n\"\n    \"\\nBenchmark-specific options:\"\n    \"\\n    -n <n>    n (TS length. Default=64K elements)\"\n    \"\\n    -m <m>    m (Query length. Default=256 elements)\"\n    \"\\n\");\n  }\n\n  struct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size_n  = 1 << 16;\n    p.input_size_m  = 1 << 8;\n\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hw:e:n:m:\")) >= 0) {\n      switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'n': p.input_size_n  = atol(optarg); break;\n        case 'm': p.input_size_m  = atol(optarg); break;\n        default:\n        fprintf(stderr, \"\\nUnrecognized option!\\n\");\n        usage();\n        exit(0);\n      }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n  }\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/TS/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[5];\r\n    struct timeval stopTime[5];\r\n    double         time[5];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"%f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -DENERGY=${ENERGY} \nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} \n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o uni -fopenmp app_baseline.c \n\nclean:\n\trm uni\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/cpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./uni -i 1258291200 -t 4\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/cpu/app_baseline.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\n#define T int64_t\n\nstatic int pos;\n\nstatic T *A;\nstatic T *B;\nstatic T *C;\nstatic T *C2;\n\n// Create a \"test file\"\nstatic T *create_test_file(unsigned int nr_elements) {\n    //srand(0);\n\n    A = (T*) malloc(nr_elements * sizeof(T));\n    B = (T*) malloc(nr_elements * sizeof(T));\n    C = (T*) malloc(nr_elements * sizeof(T));\n\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (int i = 0; i < nr_elements; i++) {\n        //A[i] = (unsigned int) (rand());\n        //A[i] = i+1;\n        //A[i] = i%2==0?i+1:i;\n        A[i] = i%2==0?i:i+1;\n        B[i] = 0;\n    }\n\n    return A;\n}\n\n// Compute output in the host\nstatic int unique_host(int size, int t) {\n    pos = 0;\n    C[pos] = A[pos];\n\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for(int my = 1; my < size; my++) {\n        if(A[my] != A[my-1]) {\n            int p;\n            #pragma omp atomic update\n            pos++;\n            p = pos;\n            C[p] = A[my];\n        }\n    }\n\n    return pos;\n}\n\n// Params \ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16 << 20;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 8;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hd:i:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads     = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n// Main\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n    uint32_t accum = 0;\n    int total_count;\n\n    // Create an input file with arbitrary data\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    total_count = unique_host(file_size, p.n_threads);\n\n    stop(&timer, 0);\n\n    printf(\"Total count = %d\\t\", total_count);\n\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n    return 0;\n  }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc unique.cu -I/usr/local/cuda/include -lm -o unique -D COARSENING=32 -D THREADS=512 -D INT64 \n\nclean:\n\trm unique\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/gpu/README",
    "content": "Unique (UNI)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./unique 0 50 1258291200\n\nCompilation flags\n\n    FLOAT - For single precision arrays (Default: Double precision)\n    INT - For integer arrays\n    THREADS - Thread block size (Default: 1024)\n    COARSENING - Coarsening factor (Default: 16 (SP and INT); 8 (DP))\n    ATOMIC - Global atomics for synchronization (Default: No atomics)\n\nRead more\nJ. Gomez-Luna et al., “In-place Data Sliding Algorithms for Many-core Architectures,” ICPP 2015.\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/gpu/ds.h",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include <iostream>\n#include <fstream>\n#include <cstdlib>\n#include <ctime>\n#include <cstdio>\n#include <math.h>\n#include <sys/time.h>\n#include <vector>\n\n#ifdef FLOAT\n#define T float\n#elif INT\n#define T int\n#elif INT64\n#define T int64_t\n#else\n#define T double\n#endif\n\n#ifdef THREADS\n#define L_DIM THREADS\n#else \n#define L_DIM 1024\n#endif\n\n#ifdef COARSENING\n#define REGS COARSENING\n#else\n#ifdef FLOAT\n#define REGS 16\n#elif INT\n#define REGS 16\n#else\n#define REGS 8 \n#endif\n#endif\n\n#ifdef ATOMIC\n#define ATOM 1\n#else\n#define ATOM 0\n#endif\n\n#define WARP_SIZE 32\n\n#define PRINT 0\n\n// Dynamic allocation of runtime workgroup id\n__device__ int dynamic_wg_id(volatile unsigned int *flags, const int num_flags){\n  __shared__ int gid_;\n  if (threadIdx.x == 0) gid_ = atomicAdd((unsigned int*)&flags[num_flags + 1], 1);\n  __syncthreads();\n  int my_s = gid_;\n  return my_s;\n}\n\n// Set global synchronization (regular DS)\n__device__ void ds_sync(volatile unsigned int *flags, const int my_s){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    atomicOr((unsigned int*)&flags[my_s + 1], 1);\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    flags[my_s + 1] = 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS)\n__device__ void ds_sync_irregular(volatile unsigned int *flags, const int my_s, int *count){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags[my_s], 0) == 0){}\n    int flag = flags[my_s];\n    atomicAdd((unsigned int*)&flags[my_s + 1], flag + *count);\n    *count = flag - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags[my_s] == 0){}\n    int flag = flags[my_s];\n    flags[my_s + 1] = flag + *count;\n    *count = flag - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Set global synchronization (irregular DS Partition)\n__device__ void ds_sync_irregular_partition(volatile unsigned int *flags1, volatile unsigned int *flags2, const int my_s, int *count1, int *count2){\n#if ATOM\n  if (threadIdx.x == 0){\n    while (atomicOr((unsigned int*)&flags1[my_s], 0) == 0){}\n    int flag2 = flags2[my_s];\n    atomicAdd((unsigned int*)&flags2[my_s + 1], flag2 + *count);\n    int flag1 = flags1[my_s];\n    atomicAdd((unsigned int*)&flags1[my_s + 1], flag1 + *count);\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#else\n  if (threadIdx.x == 0){\n    while (flags1[my_s] == 0){}\n    int flag2 = flags2[my_s];\n    flags2[my_s + 1] = flag2 + *count2;\n    int flag1 = flags1[my_s];\n    flags1[my_s + 1] = flag1 + *count1;\n    *count1 = flag1 - 1;\n    *count2 = flag2 - 1;\n  }\n#endif\n  __syncthreads();\n}\n\n// Reduction kernel (CUDA SDK reduce6)\ntemplate <class S>\n__device__ void reduction(S *count, S local_cnt){\n    __shared__ S sdata[L_DIM];\n\n    unsigned int tid = threadIdx.x;\n    S mySum = local_cnt;\n\n    // each runtime puts its local sum into shared memory\n    sdata[tid] = local_cnt;\n    __syncthreads();\n\n    // do reduction in shared mem\n    if ((blockDim.x >= 1024) && (tid < 512)){\n        sdata[tid] = mySum = mySum + sdata[tid + 512];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 512) && (tid < 256)){\n        sdata[tid] = mySum = mySum + sdata[tid + 256];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >= 256) && (tid < 128)){\n            sdata[tid] = mySum = mySum + sdata[tid + 128];\n    }\n     __syncthreads();\n\n    if ((blockDim.x >= 128) && (tid <  64)){\n       sdata[tid] = mySum = mySum + sdata[tid +  64];\n    }\n    __syncthreads();\n\n#if (__CUDA_ARCH__ >= 300 )\n    if ( tid < 32 ){\n        // Fetch final intermediate sum from 2nd warp\n        if (blockDim.x >=  64) mySum += sdata[tid + 32];\n        // Reduce final warp using shuffle\n        #pragma unroll\n        for (int offset = WARP_SIZE/2; offset > 0; offset /= 2){\n            //mySum += __shfl_down(mySum, offset);\n            mySum += __shfl_xor(mySum, offset);\n        }\n    }\n#else\n    // fully unroll reduction within a single warp\n    if ((blockDim.x >=  64) && (tid < 32)){\n        sdata[tid] = mySum = mySum + sdata[tid + 32];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  32) && (tid < 16)){\n        sdata[tid] = mySum = mySum + sdata[tid + 16];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=  16) && (tid <  8)){\n        sdata[tid] = mySum = mySum + sdata[tid +  8];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   8) && (tid <  4)){\n        sdata[tid] = mySum = mySum + sdata[tid +  4];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   4) && (tid <  2)){\n        sdata[tid] = mySum = mySum + sdata[tid +  2];\n    }\n    __syncthreads();\n\n    if ((blockDim.x >=   2) && ( tid <  1)){\n        sdata[tid] = mySum = mySum + sdata[tid +  1];\n    }\n    __syncthreads();\n#endif\n\n    // write result for this block to global mem\n    if (tid == 0) *count = mySum;\n}\n\n// Binary prefix-sum (GPU Computing Gems)\n__device__ inline int lane_id(void) { return threadIdx.x % WARP_SIZE; }\n__device__ inline int warp_id(void) { return threadIdx.x / WARP_SIZE; }\n\n__device__ unsigned int warp_prefix_sums(bool p){\n  unsigned int b = __ballot(p);\n  return __popc(b & ((1 << lane_id()) - 1));\n}\n\n__device__ int warp_scan(int val, volatile int *s_data){\n#if (__CUDA_ARCH__ < 300 )\n  int idx = 2 * threadIdx.x - (threadIdx.x & (WARP_SIZE - 1));\n  s_data[idx] = 0;\n  idx += WARP_SIZE;\n  int t = s_data[idx] = val;\n  s_data[idx] = t = t + s_data[idx - 1];\n  s_data[idx] = t = t + s_data[idx - 2];\n  s_data[idx] = t = t + s_data[idx - 4];\n  s_data[idx] = t = t + s_data[idx - 8];\n  s_data[idx] = t = t + s_data[idx - 16];\n  return s_data[idx - 1];\n#else\n  int x = val;\n  #pragma unroll\n  for(int offset = 1; offset < 32; offset <<= 1){\n  // From GTC: Kepler shuffle tips and tricks:\n#if 0\n    int y = __shfl_up(x, offset);\n    if(lane_id() >= offset)\n      x += y;\n#else\n    asm volatile(\"{\"\n        \" .reg .s32 r0;\"\n        \" .reg .pred p;\"\n        \" shfl.up.b32 r0|p, %0, %1, 0x0;\"\n        \" @p add.s32 r0, r0, %0;\"\n        \" mov.s32 %0, r0;\"\n        \"}\" : \"+r\"(x) : \"r\"(offset));\n#endif\n  }\n  return x - val;\n#endif\n}\n\n__device__ int block_binary_prefix_sums(int* count, int x){\n\n  __shared__ int sdata[L_DIM];\n\n  // A. Exclusive scan within each warp\n  int warpPrefix = warp_prefix_sums(x);\n\n  // B. Store in shared memory\n  if(lane_id() == WARP_SIZE - 1)\n    sdata[warp_id()] = warpPrefix + x;\n  __syncthreads();\n\n  // C. One warp scans in shared memory\n  if(threadIdx.x < WARP_SIZE)\n    sdata[threadIdx.x] = warp_scan(sdata[threadIdx.x], sdata);\n  __syncthreads();\n\n  // D. Each runtime calculates it final value\n  int thread_out_element = warpPrefix + sdata[warp_id()];\n  int output = thread_out_element + *count;\n  __syncthreads();\n  if(threadIdx.x == blockDim.x - 1)\n    *count += (thread_out_element + x);\n\n  return output;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/gpu/kernel.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n__device__ T warp_up(T reg, int delta){\n  __shared__ volatile T R[L_DIM];\n\n  R[threadIdx.x] = reg;\n\n  return (lane_id() - delta >= 0 ? R[threadIdx.x - delta] : 0);\n}\n__device__ T __shuffle_up(T* matrix, int my_s, int pos, T regi, int i){\n#if (__CUDA_ARCH__ >= 300 )\n  T p = __shfl_up(regi, 1);\n#else\n  T p = warp_up(regi, 1);\n#endif\n  if(lane_id() == 0 && i > 0)\n    p = matrix[pos - 1]; \n  if(lane_id() == 0 && threadIdx.x != 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s > 0 && threadIdx.x == 0 && i == 0)\n    p = matrix[pos - 1];\n  if(my_s == 0 && threadIdx.x == 0 && i == 0)\n    p = -1;\n  return p;\n}\n\n__global__ void unique(T *matrix_out, T *matrix,\n    int size,\n    volatile unsigned int *flags)\n{\n  __shared__ int count; // Counter for number of non-zero elements per block\n  const int num_flags = size % (blockDim.x * REGS) == 0 ? size / (blockDim.x * REGS) : size / (blockDim.x * REGS) + 1;\n\n  // Dynamic allocation of runtime workgroup id\n  if (threadIdx.x == 0) count = 0;\n  const int my_s = dynamic_wg_id(flags, num_flags);\n\n  int local_cnt = 0;\n  // Declare on-chip memory\n  T reg[REGS];\n  int pos = my_s * REGS * blockDim.x + threadIdx.x;\n  // Load in on-chip memory\n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    if (pos < size){\n      reg[j] = matrix[pos];\n      if(reg[j] != __shuffle_up(matrix, my_s, pos, reg[j], j))\n        local_cnt++;\n      else\n        reg[j] = -1;\n    }\n    else\n      reg[j] = -1;\n    pos += blockDim.x;\n  }\n  reduction<int>(&count, local_cnt);\n\n  // Set global synch\n  ds_sync_irregular(flags, my_s, &count);\n\n  // Store to global memory \n  #pragma unroll\n  for (int j = 0; j < REGS; j++){\n    pos = block_binary_prefix_sums(&count, reg[j] >= 0);\n    if (reg[j] >= 0){\n      matrix_out[pos] = reg[j];\n    }\n  }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/baselines/gpu/unique.cu",
    "content": "/***************************************************************************\n *cr\n *cr            (C) Copyright 2015 The Board of Trustees of the\n *cr                        University of Illinois\n *cr                         All Rights Reserved\n *cr\n ***************************************************************************/\n/*\n  In-Place Data Sliding Algorithms for Many-Core Architectures, presented in ICPP’15\n\n  Copyright (c) 2015 University of Illinois at Urbana-Champaign. \n  All rights reserved.\n\n  Permission to use, copy, modify and distribute this software and its documentation for \n  educational purpose is hereby granted without fee, provided that the above copyright \n  notice and this permission notice appear in all copies of this software and that you do \n  not sell the software.\n\n  THE SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT WARRANTY OF ANY KIND,EXPRESS, IMPLIED OR \n  OTHERWISE.\n\n  Authors: Juan Gómez-Luna (el1goluj@uco.es, gomezlun@illinois.edu), Li-Wen Chang (lchang20@illinois.edu)\n*/\n\n#include \"ds.h\"\n#include \"kernel.cu\"\n\n// Sequential CPU version\nvoid cpu_unique(T* output, T* input, int elements){\n  int j = 0;\n  output[j] = input[j];\n  j++;\n  for (int i = 1; i < elements; i++){\n    if (input[i] != input[i-1]){\n      output[j] = input[i];\n      j++;\t\t\n    }\n  }\n}\n\nint main(int argc, char **argv){\n\n  // Syntax verification\n  if (argc != 4) {\n      printf(\"Wrong format\\n\");\n      printf(\"Syntax: %s <Device Input (%% elements) numElements>\\n\",argv[0]);\n      exit(1);\n  }\n  int device = atoi(argv[1]);\n  int input = atoi(argv[2]);\n  int numElements = atoi(argv[3]);\n  size_t size = numElements * sizeof(T);\n\n  // Set device\n  cudaDeviceProp device_properties;\n  cudaGetDeviceProperties(&device_properties,device);\n  cudaSetDevice(device);\n\n  printf(\"DS Unique on %s\\n\", device_properties.name);\n  printf(\"Thread block size = %d\\n\", L_DIM);\n  printf(\"Coarsening factor = %d\\n\", REGS);\n#ifdef FLOAT\n  printf(\"Single precision array: %d elements\\n\", numElements);\n#elif INT\n  printf(\"Integer array: %d elements\\n\", numElements);\n#else\n  printf(\"Double precision array: %d elements\\n\", numElements);\n#endif\n\n  // Event creation\n  cudaEvent_t start, stop;\n  cudaEventCreate(&start);\n  cudaEventCreate(&stop);\n\n  float time1 = 0;\n  float time2 = 0;\n\n  // Allocate the host input vector A\n  T *h_A = (T*)malloc(size);\n\n  // Allocate the host output vectors\n  T *h_B = (T*)malloc(size);\n  T *h_C = (T*)malloc(size);\n\n  // Allocate the device input vector A\n  T *d_A = NULL;\n  cudaMalloc((void **)&d_A, size);\n\n#define WARMUP 0\n#define REP 1\n  int value1 = 0;\n  int value2 = 1;\n  int value3 = 2;\n  int value4 = 3;\n  unsigned int flagM = 0;\n  for(int iteration = 0; iteration < REP+WARMUP; iteration++){\n    // Initialize the host input vectors\n    srand(2014);\n    for(int i = 0; i < numElements; i++){\n    \th_A[i] = value1;\n        if(i >= numElements/4 && i < numElements/2) h_A[i] = value2;\n        if(i >= numElements/2 && i < 3*numElements/4) h_A[i] = value3;\n        if(i >= 3*numElements/4 && i < numElements) h_A[i] = value4;\n    }\n    int M = (numElements * input)/100;\n    int m = M;\n    while(m>0){\n        int x = (int)(numElements*(((float)rand()/(float)RAND_MAX)));\n        if(h_A[x]==value1 || h_A[x]==value2 || h_A[x]==value3 || h_A[x]==value4){\n    \t    h_A[x] = x+2;\n            m--;\n        }\n    }\n\n#if PRINT\n    printf(\"\\n\");\n    for(int i = 0; i < numElements; ++i){\n        printf(\"%d \",*(h_A+i));\n    }\n    printf(\"\\n\");\n#endif\n\n    // Copy the host input vector A in host memory to the device input vector in device memory\n    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n\n    int ldim = L_DIM;\n    // Atomic flags\n    unsigned int* d_flags = NULL;\n    int num_flags = numElements % (ldim * REGS) == 0 ? numElements / (ldim * REGS) : numElements / (ldim * REGS) + 1;\n    unsigned int *flags = (unsigned int *)calloc(sizeof(unsigned int), num_flags + 2);\n    flags[0] = 1;\n    flags[num_flags + 1] = 0;\n    cudaMalloc((void **)&d_flags, (num_flags + 2) * sizeof(unsigned int));\n    cudaMemcpy(d_flags, flags, (num_flags + 2) * sizeof(unsigned int), cudaMemcpyHostToDevice);\n    free(flags);\n    // Number of work-groups/runtime blocks\n    int num_wg = num_flags;\n\n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    // Kernel launch\n    unique<<<num_wg, ldim>>>(d_A, d_A, numElements, d_flags);\n\n    cudaMemcpy(&flagM, d_flags + num_flags, sizeof(unsigned int), cudaMemcpyDeviceToHost);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n    if(iteration >= WARMUP) time2 += time1;\n\n    if(iteration == REP+WARMUP-1){\n      float timer = time2 / REP;\n      double bw = (double)((numElements + flagM) * sizeof(T)) / (double)(timer * 1000000.0);\n      printf(\"Execution time = %f ms, Throughput = %f GB/s\\n\", timer, bw);\n    }\n\n    // Free flags\n    cudaFree(d_flags);\n  }\n  // Copy to host memory\n  cudaMemcpy(h_B, d_A, size, cudaMemcpyDeviceToHost);\n\n  // CPU execution for comparison\n  cpu_unique(h_C, h_A, numElements);\n\n  // Verify that the result vector is correct\n#if PRINT\n  for(int i = 0; i < numElements; ++i){\n     printf(\"%d \",*(h_B+i));\n  }\n  printf(\"\\n\");\n  for(int i = 0; i < numElements; ++i){\n      printf(\"%d \",*(h_C+i));\n  }\n  printf(\"\\n\");\n#endif\n  for (int i = 0; i < flagM - 1; ++i){\n      if (h_B[i] != h_C[i]){\n          fprintf(stderr, \"Result verification failed at element %d!\\n\", i);\n          exit(EXIT_FAILURE);\n      }\n  }\n  printf(\"Test PASSED\\n\");\n\n  // Free device global memory\n  cudaFree(d_A);\n  cudaEventDestroy(start);\n  cudaEventDestroy(stop);\n  // Free host memory\n  free(h_A);\n  free(h_B);\n  free(h_C);\n\n  return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/dpu/task.c",
    "content": "/*\n* Unique with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <handshake.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Array for communication between adjacent tasklets\nuint32_t message[NR_TASKLETS];\nT        message_value[NR_TASKLETS];\nuint32_t message_offset[NR_TASKLETS];\nuint32_t message_partial_count;\nT        message_last_from_last;\n\n// UNI in each tasklet\nunsigned int __attribute__ ((noinline)) unique(T *output, T *input){\n    unsigned int pos = 0;\n    output[pos] = input[pos];\n    pos++;\n    #pragma unroll\n    for(unsigned int j = 1; j < REGS; j++) {\n        if(input[j] != input[j - 1]) {\n            output[pos] = input[j];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Handshake with adjacent tasklets\nuint3 __attribute__ ((noinline)) handshake_sync(T *output, unsigned int l_count, unsigned int tasklet_id){\n    unsigned int p_count, o_count, offset;\n    // Wait and read message\n    if(tasklet_id != 0){\n        handshake_wait_for(tasklet_id - 1);\n        p_count = message[tasklet_id];\n        offset = (message_value[tasklet_id] == output[0])?1:0;\n        o_count = message_offset[tasklet_id];\n    }\n    else{\n        p_count = 0;\n        offset = (message_last_from_last == output[0])?1:0;\n        o_count = 0;\n    }\n    // Write message and notify\n    if(tasklet_id < NR_TASKLETS - 1){\n        message[tasklet_id + 1] = p_count + l_count;\n        message_value[tasklet_id + 1] = output[l_count - 1];\n        message_offset[tasklet_id + 1] = o_count + offset;\n        handshake_notify();\n    }\n    uint3 result = {p_count, o_count, offset}; \n    return result;\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    // Initialize shared variable\n    if(tasklet_id == NR_TASKLETS - 1){\n        message_partial_count = 0;\n        message_last_from_last = 0xFFFFFFFF; // A value that is not in the input array\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    unsigned int i = 0; // Iteration count\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, BLOCK_SIZE);\n\n        // UNI in each tasklet\n        unsigned int l_count = unique(cache_B, cache_A); // In-place or out-of-place?\n\n        // Sync with adjacent tasklets\n        uint3 po_count = handshake_sync(cache_B, l_count, tasklet_id);\n\n        // Write cache to current MRAM block\n        mram_write(&cache_B[po_count.z], (__mram_ptr void*)(mram_base_addr_B + (message_partial_count + po_count.x - po_count.y) * sizeof(T)), l_count * sizeof(T));\n\n        // First\n        if(tasklet_id == 0 && i == 0){\n            result->first = cache_B[0];\n        }\n        \n        // Total count in this DPU\n        if(tasklet_id == NR_TASKLETS - 1){\n            message_last_from_last = cache_B[l_count - 1];\n            result->last = cache_B[l_count - 1];\n            result->t_count = message_partial_count + po_count.x + l_count - po_count.y - po_count.z;\n            message_partial_count = result->t_count;\n        }\n\n        // Barrier\n        barrier_wait(&my_barrier);\n\n        i++;\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/host/app.c",
    "content": "/**\n* app.c\n* UNI Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, unsigned int nr_elements, unsigned int nr_elements_round) {\n    //srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        //A[i] = (T) (rand());\n        A[i] = i%2==0?i:i+1;\n    }\n    for (unsigned int i = nr_elements; i < nr_elements_round; i++) {\n        A[i] = A[nr_elements - 1];\n    }\n}\n\n// Compute output in the host\nstatic unsigned int unique_host(T* C, T* A, unsigned int nr_elements) {\n    unsigned int pos = 0;\n    C[pos] = A[pos];\n    pos++;\n    for(unsigned int i = 1; i < nr_elements; i++) {\n        if(A[i] != A[i-1]) {\n            C[pos] = A[i];\n            pos++;\n        }\n    }\n    return pos;\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    uint32_t accum = 0;\n    uint32_t total_count = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_dpu_ = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_round = \n        (input_size_dpu_ % (NR_TASKLETS * REGS) != 0) ? roundup(input_size_dpu_, (NR_TASKLETS * REGS)) : input_size_dpu_; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_round * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, input_size, input_size_dpu_round * nr_of_dpus);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        total_count = unique_host(C, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size_dpu_round;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu * sizeof(T), kernel};\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments), DPU_XFER_DEFAULT));\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        dpu_results_t results[nr_of_dpus];\n        uint32_t* results_scan = malloc(nr_of_dpus * sizeof(uint32_t));\n        uint32_t* offset = calloc(nr_of_dpus, sizeof(uint32_t));\n        uint32_t* offset_scan = calloc(nr_of_dpus, sizeof(uint32_t));\n        i = 0;\n        accum = 0;\n\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        // PARALLEL RETRIEVE TRANSFER\n        dpu_results_t* results_retrieve[nr_of_dpus];\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            results_retrieve[i] = (dpu_results_t*)malloc(NR_TASKLETS * sizeof(dpu_results_t));\n            DPU_ASSERT(dpu_prepare_xfer(dpu, results_retrieve[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, \"DPU_RESULTS\", 0, NR_TASKLETS * sizeof(dpu_results_t), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                // First output element of this DPU\n                if(each_tasklet == 0){\n                    results[i].first = results_retrieve[i][each_tasklet].first;\n                }\n                // Last output element of this DPU and count\n                if(each_tasklet == NR_TASKLETS - 1){\n                    results[i].t_count = results_retrieve[i][each_tasklet].t_count;\n                    results[i].last = results_retrieve[i][each_tasklet].last;\n                }\n            }\n            // Check if first(i) == last(i-1) -- offset\n            if(i != 0){\n                if(results[i].first == results[i - 1].last)\n                    offset[i] = 1;\n                // Sequential scan - offset\n                offset_scan[i] += offset[i];\n            }\n            // Sequential scan\n            uint32_t temp = results[i].t_count - offset[i];\n            results_scan[i] = accum;\n            accum += temp;\n#if PRINT\n            printf(\"i=%d -- %u,  %u, %u -- %u\\n\", i, results_scan[i], accum, temp, offset_scan[i]);\n#endif\n            free(results_retrieve[i]);\n        }\n        if(rep >= p.n_warmup)\n\t\t    stop(&timer, 3);\n\n        i = 0;\n        if(rep >= p.n_warmup)\n            start(&timer, 4, rep - p.n_warmup);\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(T), bufferC + results_scan[i] - offset_scan[i], results[i].t_count * sizeof(T)));\n\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 4);\n\n        // Free memory\n        free(results_scan);\n        free(offset);\n        free(offset_scan);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"Inter-DPU \");\n    print(&timer, 3, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 4, p.n_reps);\n\n#if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n#endif\t\n\n    // Check output\n    bool status = true;\n    if(accum != total_count) status = false;\n#if PRINT\n    printf(\"accum %u, total_count %u\\n\", accum, total_count);\n#endif\n    for (i = 0; i < accum; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %lu -- %lu\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Data type\n#define T int64_t\n#define REGS (BLOCK_SIZE >> 3) // 64 bits\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint32_t t_count;\n    T first;\n    T last;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\ntypedef struct{unsigned int x; unsigned int y; unsigned int z;} uint3;\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=3932160 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 3932160;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/UNI/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[7];\r\n    struct timeval stopTime[7];\r\n    double         time[7];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nTYPE ?= INT32\nENERGY ?= 0\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_TYPE_$(4).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${TYPE})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${TYPE} -DENERGY=${ENERGY}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${TYPE}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o ${HOST_TARGET}.bin ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/cpu/Makefile",
    "content": "all:\n\tgcc -o va -fopenmp app_baseline.c \n\nclean:\n\trm va\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/cpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va -t 4\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/cpu/app_baseline.c",
    "content": "/**\n* @file app.c\n* @brief Template for a Host Application Source File.\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n#include <stdint.h>\n\n#include <omp.h>\n#include \"../../support/timer.h\"\n\nstatic int32_t *A;\nstatic int32_t *B;\nstatic int32_t *C;\nstatic int32_t *C2; \n\n/**\n* @brief creates a \"test file\" by filling a buffer of 64MB with pseudo-random values\n* @param nr_elements how many 32-bit elements we want the file to be\n* @return the buffer address\n*/\nvoid  *create_test_file(unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    A = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    B = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    C = (uint32_t*) malloc(nr_elements * sizeof(uint32_t));\n    \n    for (int i = 0; i < nr_elements; i++) {\n        A[i] = (int) (rand());\n        B[i] = (int) (rand());\n    }\n\n}\n\n/**\n* @brief compute output in the host\n*/\nstatic void vector_addition_host(unsigned int nr_elements, int t) {\n    omp_set_num_threads(t);\n    #pragma omp parallel for\n    for (int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\n// Params ---------------------------------------------------------------------\ntypedef struct Params {\n    int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int   n_threads;\n}Params;\n\nvoid usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -t <T>    # of threads (default=8)\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8M elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 16777216;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.n_threads     = 5;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:t:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 't': p.n_threads        = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(p.n_threads > 0 && \"Invalid # of ranks!\");\n\n    return p;\n}\n\n/**\n* @brief Main of the Host Application.\n*/\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    const unsigned int file_size = p.input_size;\n\n    // Create an input file with arbitrary data.\n    create_test_file(file_size);\n\n    Timer timer;\n    start(&timer, 0, 0);\n\n    vector_addition_host(file_size, p.n_threads);\n\t\n    stop(&timer, 0);\n    printf(\"Kernel \");\n    print(&timer, 0, 1);\n    printf(\"\\n\");\n\n    free(A);\n    free(B);\n    free(C);\n\n   return 0;\n }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/gpu/Makefile",
    "content": "all:\n\t/usr/local/cuda/bin/nvcc vec_add.cu -I/usr/local/cuda/include -lm -o va\n\nclean:\n\trm va\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/gpu/README",
    "content": "Vector addition (VA)\n\nCompilation instructions\n\n    make\n\nExecution instructions\n\n    ./va\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/baselines/gpu/vec_add.cu",
    "content": "/* File:     vec_add.cu\n * Purpose:  Implement vector addition on a gpu using cuda\n *\n * Compile:  nvcc [-g] [-G] -o vec_add vec_add.cu\n * Run:      ./vec_add\n */\n\n#include <stdio.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <math.h>\n\n__global__ void Vec_add(unsigned int x[], unsigned int y[], unsigned int z[], int n) {\n    int thread_id = blockIdx.x * blockDim.x + threadIdx.x;\n    if (thread_id < n){\n        z[thread_id] = x[thread_id] + y[thread_id];\n    }\n}\n\n\nint main(int argc, char* argv[]) {\n    int n, m;\n    unsigned int *h_x, *h_y, *h_z;\n    unsigned int *d_x, *d_y, *d_z;\n    size_t size;\n\n    /* Define vector length */\n    n = 2621440;\n    m = 320;\n    size = m * n * sizeof(unsigned int);\n\n    // Allocate memory for the vectors on host memory.\n    h_x = (unsigned int*) malloc(size);\n    h_y = (unsigned int*) malloc(size);\n    h_z = (unsigned int*) malloc(size);\n\n    for (int i = 0; i < n * m; i++) {\n        h_x[i] = i+1;\n        h_y[i] = n-i;\n    }\n\n    printf(\"Input size = %d\\n\", n * m);\n\n    // Print original vectors.\n    /*printf(\"h_x = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_x[i]);\n    }\n    printf(\"\\n\\n\");\n    printf(\"h_y = \");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_y[i]);\n    }\n    printf(\"\\n\\n\");*/\n\n    // Event creation\n    cudaEvent_t start, stop;\n    cudaEventCreate(&start);\n    cudaEventCreate(&stop);\n    float time1 = 0;\n\n    /* Allocate vectors in device memory */\n    cudaMalloc(&d_x, size);\n    cudaMalloc(&d_y, size);\n    cudaMalloc(&d_z, size);\n\n    /* Copy vectors from host memory to device memory */\n    cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);\n    cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);\n    \n    // Start timer\n    cudaEventRecord( start, 0 );\n\n    /* Kernel Call */\n    Vec_add<<<(n * m) / 256, 256>>>(d_x, d_y, d_z, n * m);\n\n    // End timer\n    cudaEventRecord( stop, 0 );\n    cudaEventSynchronize( stop );\n    cudaEventElapsedTime( &time1, start, stop );\n\n    cudaMemcpy(h_z, d_z, size, cudaMemcpyDeviceToHost);\n    /*printf(\"The sum is: \\n\");\n    for (int i = 0; i < m; i++){\n        printf(\"%u \", h_z[i]);\n    }\n    printf(\"\\n\");*/\n\n    printf(\"Execution time = %f ms\\n\", time1);\n\n    /* Free device memory */\n    cudaFree(d_x);\n    cudaFree(d_y);\n    cudaFree(d_z);\n    /* Free host memory */\n    free(h_x);\n    free(h_y);\n    free(h_z);\n\n    return 0;\n}  /* main */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/dpu/task.c",
    "content": "/*\n* Vector addition with multiple tasklets\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n\n// vector_addition: Computes the vector addition of a cached block \nvoid __attribute__ ((noinline)) vector_addition(T *bufferB, T *bufferA, unsigned int l_size) {\n    for (unsigned int i = 0; i < l_size; i++){\n        bufferB[i] += bufferA[i];\n    }\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n    }\n    // Barrier\n    barrier_wait(&my_barrier);\n\n    uint32_t input_size_dpu_bytes = DPU_INPUT_ARGUMENTS.size; // Input size per DPU in bytes\n    uint32_t input_size_dpu_bytes_transfer = DPU_INPUT_ARGUMENTS.transfer_size; // Transfer input size per DPU in bytes\n\n    // Address of the current processing block in MRAM\n    uint32_t base_tasklet = tasklet_id << BLOCK_SIZE_LOG2;\n    uint32_t mram_base_addr_A = (uint32_t)DPU_MRAM_HEAP_POINTER;\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + input_size_dpu_bytes_transfer);\n\n    // Initialize a local cache to store the MRAM block\n    T *cache_A = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n\n    for(unsigned int byte_index = base_tasklet; byte_index < input_size_dpu_bytes; byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Bound checking\n        uint32_t l_size_bytes = (byte_index + BLOCK_SIZE >= input_size_dpu_bytes) ? (input_size_dpu_bytes - byte_index) : BLOCK_SIZE;\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + byte_index), cache_A, l_size_bytes);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, l_size_bytes);\n\n        // Computer vector addition\n        vector_addition(cache_B, cache_A, l_size_bytes >> DIV);\n\n        // Write cache to current MRAM block\n        mram_write(cache_B, (__mram_ptr void*)(mram_base_addr_B + byte_index), l_size_bytes);\n\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/host/app.c",
    "content": "/**\n* app.c\n* VA Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n#if ENERGY\n#include <dpu_probe.h>\n#endif\n\n// Pointer declaration\nstatic T* A;\nstatic T* B;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\nstatic void read_input(T* A, T* B, unsigned int nr_elements) {\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        A[i] = (T) (rand());\n        B[i] = (T) (rand());\n    }\n}\n\n// Compute output in the host\nstatic void vector_addition_host(T* C, T* A, T* B, unsigned int nr_elements) {\n    for (unsigned int i = 0; i < nr_elements; i++) {\n        C[i] = A[i] + B[i];\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n\n#if ENERGY\n    struct dpu_probe_t probe;\n    DPU_ASSERT(dpu_probe_init(\"energy_probe\", &probe));\n#endif\n\n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n    unsigned int i = 0;\n\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size; // Total input size (weak or strong scaling)\n    const unsigned int input_size_8bytes = \n        ((input_size * sizeof(T)) % 8) != 0 ? roundup(input_size, 8) : input_size; // Input size per DPU (max.), 8-byte aligned\n    const unsigned int input_size_dpu = divceil(input_size, nr_of_dpus); // Input size per DPU (max.)\n    const unsigned int input_size_dpu_8bytes = \n        ((input_size_dpu * sizeof(T)) % 8) != 0 ? roundup(input_size_dpu, 8) : input_size_dpu; // Input size per DPU (max.), 8-byte aligned\n\n    // Input/output allocation\n    A = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    B = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    C = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    C2 = malloc(input_size_dpu_8bytes * nr_of_dpus * sizeof(T));\n    T *bufferA = A;\n    T *bufferB = B;\n    T *bufferC = C2;\n\n    // Create an input file with arbitrary data\n    read_input(A, B, input_size);\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        vector_addition_host(C, A, B, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments[NR_DPUS];\n        for(i=0; i<nr_of_dpus-1; i++) {\n            input_arguments[i].size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].transfer_size=input_size_dpu_8bytes * sizeof(T); \n            input_arguments[i].kernel=kernel;\n        }\n        input_arguments[nr_of_dpus-1].size=(input_size_8bytes - input_size_dpu_8bytes * (NR_DPUS-1)) * sizeof(T); \n        input_arguments[nr_of_dpus-1].transfer_size=input_size_dpu_8bytes * sizeof(T); \n        input_arguments[nr_of_dpus-1].kernel=kernel;\n\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, &input_arguments[i]));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, \"DPU_INPUT_ARGUMENTS\", 0, sizeof(input_arguments[0]), DPU_XFER_DEFAULT));\n\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferA + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, 0, input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n \n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferB + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_TO_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup) {\n            start(&timer, 2, rep - p.n_warmup);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_start(&probe));\n            #endif\n        }\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup) {\n            stop(&timer, 2);\n            #if ENERGY\n            DPU_ASSERT(dpu_probe_stop(&probe));\n            #endif\n        }\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        i = 0;\n        // PARALLEL RETRIEVE TRANSFER\n        DPU_FOREACH(dpu_set, dpu, i) {\n            DPU_ASSERT(dpu_prepare_xfer(dpu, bufferC + input_size_dpu_8bytes * i));\n        }\n        DPU_ASSERT(dpu_push_xfer(dpu_set, DPU_XFER_FROM_DPU, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu_8bytes * sizeof(T), input_size_dpu_8bytes * sizeof(T), DPU_XFER_DEFAULT));\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n    }\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n#if ENERGY\n    double energy;\n    DPU_ASSERT(dpu_probe_get(&probe, DPU_ENERGY, DPU_AVERAGE, &energy));\n    printf(\"DPU Energy (J): %f\\t\", energy);\n#endif\t\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information\ntypedef struct {\n    uint32_t size;\n    uint32_t transfer_size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef UINT32\n#define T uint32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif UINT64\n#define T uint64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif INT64\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif FLOAT\n#define T float\n#define DIV 2 // Shift right to divide by sizeof(T)\n#elif DOUBLE\n#define T double\n#define DIV 3 // Shift right to divide by sizeof(T)\n#elif CHAR\n#define T char\n#define DIV 0 // Shift right to divide by sizeof(T)\n#elif SHORT\n#define T short\n#define DIV 1 // Shift right to divide by sizeof(T)\n#endif\n\n#ifndef ENERGY\n#define ENERGY 0\n#endif\n#define PRINT 0 \n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#define divceil(n, m) (((n)-1) / (m) + 1)\n#define roundup(n, m) ((n / m) * m + m)\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=2621440 elements)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 2621440;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/VA/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/Makefile",
    "content": "DPU_DIR := dpu\nHOST_DIR := host\nBUILDDIR ?= bin\nNR_TASKLETS ?= 16\nBL ?= 10\nNR_DPUS ?= 1\nOP ?= streaming\nMEM ?= WRAM\nTYPE ?= INT64\n\ndefine conf_filename\n\t${BUILDDIR}/.NR_DPUS_$(1)_NR_TASKLETS_$(2)_BL_$(3)_$(4)_$(5).conf\nendef\nCONF := $(call conf_filename,${NR_DPUS},${NR_TASKLETS},${BL},${OP},${MEM})\n\nHOST_TARGET := ${BUILDDIR}/host_code\nDPU_TARGET := ${BUILDDIR}/dpu_code\n\nCOMMON_INCLUDES := support\nHOST_SOURCES := $(wildcard ${HOST_DIR}/*.c)\nDPU_SOURCES := $(wildcard ${DPU_DIR}/*.c)\n\n.PHONY: all clean test\n\n__dirs := $(shell mkdir -p ${BUILDDIR})\n\nCOMMON_FLAGS := -w -I${COMMON_INCLUDES}\nHOST_FLAGS := ${COMMON_FLAGS} -std=c11 -O3 `dpu-pkg-config --cflags --libs dpu` -DNR_TASKLETS=${NR_TASKLETS} -DNR_DPUS=${NR_DPUS} -DBL=${BL} -D${OP} -D${MEM} -D${TYPE}\nDPU_FLAGS := ${COMMON_FLAGS} -O2 -DNR_TASKLETS=${NR_TASKLETS} -DBL=${BL} -D${OP} -D${MEM} -D${TYPE}\n\nall: ${HOST_TARGET} ${DPU_TARGET}\n\n${CONF}:\n\t$(RM) $(call conf_filename,*,*)\n\ttouch ${CONF}\n\n${HOST_TARGET}: ${HOST_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\t$(CC) -o $@ ${HOST_SOURCES} ${HOST_FLAGS}\n\t$(CC) -S -o ${HOST_TARGET}.S ${HOST_SOURCES} ${HOST_FLAGS}\n\n${DPU_TARGET}: ${DPU_SOURCES} ${COMMON_INCLUDES} ${CONF}\n\tdpu-upmem-dpurte-clang ${DPU_FLAGS} -o $@ ${DPU_SOURCES}\n\tdpu-upmem-dpurte-clang -S ${DPU_FLAGS} -o ${DPU_TARGET}.S ${DPU_SOURCES}\n\nclean:\n\t$(RM) -r $(BUILDDIR)\n\ntest: all\n\t./${HOST_TARGET}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/dpu/task.c",
    "content": "/*\n* WRAM Access\n*\n*/\n#include <stdint.h>\n#include <stdio.h>\n#include <defs.h>\n#include <mram.h>\n#include <alloc.h>\n#include <perfcounter.h>\n#include <barrier.h>\n\n#include \"../support/common.h\"\n#include \"../support/cyclecount.h\"\n\n__host dpu_arguments_t DPU_INPUT_ARGUMENTS;\n__host dpu_results_t DPU_RESULTS[NR_TASKLETS];\n\n// Copy\nvoid copy_pattern_dpu(T *bufferC, T *bufferB, uint32_t *bufferA) {\n\n    #pragma unroll\n    for (unsigned int i = 0; i < (BLOCK_SIZE >> DIV); i++){\n\t\t\n        uint32_t address = bufferA[i];\n        bufferC[address] = bufferB[address];\n\n    }\n\n}\n\n// Barrier\nBARRIER_INIT(my_barrier, NR_TASKLETS);\n\nextern int main_kernel1(void);\n\nint (*kernels[nr_kernels])(void) = {main_kernel1};\n\nint main(void) { \n    // Kernel\n    return kernels[DPU_INPUT_ARGUMENTS.kernel](); \n}\n\n// main_kernel1\nint main_kernel1() {\n    unsigned int tasklet_id = me();\n#if PRINT\n    printf(\"tasklet_id = %u\\n\", tasklet_id);\n#endif\n    if (tasklet_id == 0){ // Initialize once the cycle counter\n        mem_reset(); // Reset the heap\n\n        perfcounter_config(COUNT_CYCLES, true);\n    }\n    perfcounter_cycles cycles;\n    // Barrier\n    barrier_wait(&my_barrier);\n#ifndef WRAM\n    timer_start(&cycles); // START TIMER\n#endif\n\n    uint32_t input_size_dpu = DPU_INPUT_ARGUMENTS.size;\n\n    dpu_results_t *result = &DPU_RESULTS[tasklet_id];\n    result->cycles = 0;\n\n    const uint32_t A_SIZE = (BLOCK_SIZE >> DIV) << 2;\n    // Address of the current processing block in MRAM\n    uint32_t mram_base_addr_A = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id * A_SIZE));\n    uint32_t mram_base_addr_B = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * sizeof(uint32_t));\n    uint32_t mram_base_addr_C = (uint32_t)(DPU_MRAM_HEAP_POINTER + (tasklet_id << BLOCK_SIZE_LOG2) + input_size_dpu * (sizeof(uint32_t) + sizeof(T)));\n\n    // Initialize a local cache to store the MRAM block\n    uint32_t *cache_A = (uint32_t *) mem_alloc(A_SIZE);\n    T *cache_B = (T *) mem_alloc(BLOCK_SIZE);\n    T *cache_C = (T *) mem_alloc(BLOCK_SIZE);\n\n    uint32_t A_byte_index = 0; \n    for(unsigned int byte_index = 0; byte_index < (input_size_dpu << DIV); byte_index += BLOCK_SIZE * NR_TASKLETS){\n\n        // Load cache with current MRAM block\n        mram_read((__mram_ptr void const*)(mram_base_addr_A + A_byte_index), cache_A, A_SIZE);\n        mram_read((__mram_ptr void const*)(mram_base_addr_B + byte_index), cache_B, BLOCK_SIZE);\n        mram_read((__mram_ptr void const*)(mram_base_addr_C + byte_index), cache_C, BLOCK_SIZE); // Clean cache_C\n\n#ifdef WRAM\n        // Barrier\n        barrier_wait(&my_barrier);\n        timer_start(&cycles); // START TIMER\n#endif\n\n        // Copy\n        copy_pattern_dpu(cache_C, cache_B, cache_A);\n\n#ifdef WRAM\n        result->cycles += timer_stop(&cycles); // STOP TIMER\n        // Barrier\n        barrier_wait(&my_barrier);\n#endif\n\n        // Write cache to current MRAM block\n        mram_write(cache_C, (__mram_ptr void*)(mram_base_addr_C + byte_index), BLOCK_SIZE);\n\n        A_byte_index += A_SIZE * NR_TASKLETS;\n    }\n\n#ifndef WRAM\n    result->cycles = timer_stop(&cycles); // STOP TIMER\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/host/app.c",
    "content": "/**\n* app.c\n* WRAM Access Host Application Source File\n*\n*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <dpu.h>\n#include <dpu_log.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <assert.h>\n\n#include \"../support/common.h\"\n#include \"../support/timer.h\"\n#include \"../support/params.h\"\n\n// Define the DPU Binary path as DPU_BINARY here\n#ifndef DPU_BINARY\n#define DPU_BINARY \"./bin/dpu_code\"\n#endif\n\n// Pointer declaration\nstatic unsigned int* A;\nstatic T* B;\nstatic T* C;\nstatic T* C2;\n\n// Create input arrays\n#ifdef strided\nstatic void read_input(unsigned int* A, T* B, unsigned int nr_elements, unsigned int stride) {\n#else\nstatic void read_input(unsigned int* A, T* B, unsigned int nr_elements) {\n#endif\n    srand(0);\n    printf(\"nr_elements\\t%u\\t\", nr_elements);\n    for (unsigned int i = 0; i < nr_elements; i++) {\n#ifdef streaming\n        A[i] = i % (BLOCK_SIZE >> DIV);\n#elif strided\n        A[i] = ((i>0 ? A[i-1]:0) + stride) % (BLOCK_SIZE >> DIV);\n#else\n        A[i] = ((unsigned int)rand()) % (BLOCK_SIZE >> DIV);\n#endif\n        B[i] = (T)(rand());\n        C[i] = 0;\n    }\n}\n\n// Compute output in the host\nstatic void copy_host(T* C, T* B, unsigned int* A, unsigned int nr_elements) {\n    unsigned int wram_size = BLOCK_SIZE >> DIV;\n    for (unsigned int i = 0; i < nr_elements / wram_size; i++) {\n        for (unsigned int j = 0; j < wram_size; j++) {\n            unsigned int address = A[i * wram_size + j];\n            C[i * wram_size + address] = B[i * wram_size + address];\n        }\n    }\n}\n\n// Main of the Host Application\nint main(int argc, char **argv) {\n\n    struct Params p = input_params(argc, argv);\n\n    struct dpu_set_t dpu_set, dpu;\n    uint32_t nr_of_dpus;\n    \n    // Allocate DPUs and load binary\n    DPU_ASSERT(dpu_alloc(NR_DPUS, NULL, &dpu_set));\n    DPU_ASSERT(dpu_load(dpu_set, DPU_BINARY, NULL));\n    DPU_ASSERT(dpu_get_nr_dpus(dpu_set, &nr_of_dpus));\n    printf(\"Allocated %d DPU(s)\\n\", nr_of_dpus);\n\n    unsigned int i = 0;\n    double cc = 0;\n    double cc_min = 0;\n    const unsigned int input_size = p.exp == 0 ? p.input_size * nr_of_dpus : p.input_size;\n\n    // Input/output allocation\n    A = malloc(input_size * sizeof(unsigned int));\n    unsigned int *bufferA = A;\n    B = malloc(input_size * sizeof(T));\n    T *bufferB = B;\n    C = malloc(input_size * sizeof(T));\n    T *bufferC = C;\n    C2 = malloc(input_size * sizeof(T));\n\n    // Create an input file with arbitrary data\n#ifdef strided\n    read_input(A, B, input_size, p.stride);\n#else\n    read_input(A, B, input_size);\n#endif\n\n    // Timer declaration\n    Timer timer;\n\n    printf(\"NR_TASKLETS\\t%d\\tBL\\t%d\\n\", NR_TASKLETS, BL);\n\n    // Loop over main kernel\n    for(int rep = 0; rep < p.n_warmup + p.n_reps; rep++) {\n\n        // Compute output on CPU (performance comparison and verification purposes)\n        if(rep >= p.n_warmup)\n            start(&timer, 0, rep - p.n_warmup);\n        copy_host(C2, B, A, input_size);\n        if(rep >= p.n_warmup)\n            stop(&timer, 0);\n\n        printf(\"Load input data\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 1, rep - p.n_warmup);\n        // Input arguments\n        const unsigned int input_size_dpu = input_size / nr_of_dpus;\n        unsigned int kernel = 0;\n        dpu_arguments_t input_arguments = {input_size_dpu, kernel};\n        DPU_ASSERT(dpu_copy_to(dpu_set, \"DPU_INPUT_ARGUMENTS\", 0, (const void *)&input_arguments, sizeof(input_arguments)));\n        // Copy input arrays\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, 0, bufferA + input_size_dpu * i, input_size_dpu * sizeof(unsigned int)));\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * sizeof(unsigned int), bufferB + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            DPU_ASSERT(dpu_copy_to(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * (sizeof(unsigned int) + sizeof(T)), bufferC + input_size_dpu * i, input_size_dpu * sizeof(T)));\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 1);\n\n        printf(\"Run program on DPU(s) \\n\");\n        // Run DPU kernel\n        if(rep >= p.n_warmup)\n            start(&timer, 2, rep - p.n_warmup);\n        DPU_ASSERT(dpu_launch(dpu_set, DPU_SYNCHRONOUS));\n        if(rep >= p.n_warmup)\n            stop(&timer, 2);\n\n#if PRINT\n        {\n            unsigned int each_dpu = 0;\n            printf(\"Display DPU Logs\\n\");\n            DPU_FOREACH (dpu_set, dpu) {\n                printf(\"DPU#%d:\\n\", each_dpu);\n                DPU_ASSERT(dpulog_read_for_dpu(dpu.dpu, stdout));\n                each_dpu++;\n            }\n        }\n#endif\n\n        printf(\"Retrieve results\\n\");\n        if(rep >= p.n_warmup)\n            start(&timer, 3, rep - p.n_warmup);\n        dpu_results_t results[nr_of_dpus];\n        i = 0;\n        DPU_FOREACH (dpu_set, dpu) {\n            // Copy output array\n            DPU_ASSERT(dpu_copy_from(dpu, DPU_MRAM_HEAP_POINTER_NAME, input_size_dpu * (sizeof(unsigned int) + sizeof(T)), bufferC + input_size_dpu * i, input_size_dpu * sizeof(T)));\n\t\t\t\n#if PERF\n            results[i].cycles = 0;\n            // Retrieve tasklet timings\n            for (unsigned int each_tasklet = 0; each_tasklet < NR_TASKLETS; each_tasklet++) {\n                dpu_results_t result;\n                result.cycles = 0;\n                DPU_ASSERT(dpu_copy_from(dpu, \"DPU_RESULTS\", each_tasklet * sizeof(dpu_results_t), &result, sizeof(dpu_results_t)));\n                if (result.cycles > results[i].cycles)\n                    results[i].cycles = result.cycles;\n            }\n#endif\n            i++;\n        }\n        if(rep >= p.n_warmup)\n            stop(&timer, 3);\n\n#if PERF\n        uint64_t max_cycles = 0;\n        uint64_t min_cycles = 0xFFFFFFFFFFFFFFFF;\n        // Print performance results\n        if(rep >= p.n_warmup){\n            i = 0;\n            DPU_FOREACH(dpu_set, dpu) {\n                if(results[i].cycles > max_cycles)\n                    max_cycles = results[i].cycles;\n                if(results[i].cycles < min_cycles)\n                    min_cycles = results[i].cycles;\n                i++;\n            }\n            cc += (double)max_cycles;\n            cc_min += (double)min_cycles;\n        }\n#endif\n\n    }\n    printf(\"DPU cycles  = %g cc\\n\", cc / p.n_reps);\n\n    // Print timing results\n    printf(\"CPU \");\n    print(&timer, 0, p.n_reps);\n    printf(\"CPU-DPU \");\n    print(&timer, 1, p.n_reps);\n    printf(\"DPU Kernel \");\n    print(&timer, 2, p.n_reps);\n    printf(\"DPU-CPU \");\n    print(&timer, 3, p.n_reps);\n\n    // Check output\n    bool status = true;\n    for (i = 0; i < input_size; i++) {\n        if(C2[i] != bufferC[i]){ \n            status = false;\n#if PRINT\n            printf(\"%d: %u -- %u\\n\", i, C2[i], bufferC[i]);\n#endif\n        }\n    }\n    if (status) {\n        printf(\"[\" ANSI_COLOR_GREEN \"OK\" ANSI_COLOR_RESET \"] Outputs are equal\\n\");\n    } else {\n        printf(\"[\" ANSI_COLOR_RED \"ERROR\" ANSI_COLOR_RESET \"] Outputs differ!\\n\");\n    }\n\n    // Deallocation\n    free(A);\n    free(B);\n    free(C);\n    free(C2);\n    DPU_ASSERT(dpu_free(dpu_set));\n\t\n    return status ? 0 : -1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/run.sh",
    "content": "#!/bin/bash\n\n# WRAM\nfor i in streaming random\ndo\n\tfor j in 1 \n\tdo \t\n        for k in 1 2 4 8 16  \n        do \t\n            NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=WRAM OP=$i make all\n            wait\n            ./bin/host_code -w 0 -e 1 -i 2097152 >& profile/${i}_${j}_tl${k}_s1_WRAM.txt\n            wait\n            make clean\n            wait\n        done\n\tdone\ndone\n\nfor i in strided \ndo\n\tfor j in 1 \n\tdo \t\n        for k in 1 2 4 8 16  \n        do \t\n            for l in 1 2 4 8 16 32 64\n            do \t\n                NR_DPUS=$j NR_TASKLETS=$k BL=10 MEM=WRAM OP=$i make all\n                wait\n                ./bin/host_code -w 0 -e 1 -i 2097152 -s ${l} >& profile/${i}_${j}_tl${k}_s${l}_WRAM.txt\n                wait\n                make clean\n                wait\n\t        done\n        done\n\tdone\ndone\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/support/common.h",
    "content": "#ifndef _COMMON_H_\n#define _COMMON_H_\n\n// Structures used by both the host and the dpu to communicate information \ntypedef struct {\n    uint32_t size;\n\tenum kernels {\n\t    kernel1 = 0,\n\t    nr_kernels = 1,\n\t} kernel;\n} dpu_arguments_t;\n\ntypedef struct {\n    uint64_t cycles;\n} dpu_results_t;\n\n// Transfer size between MRAM and WRAM\n#ifdef BL\n#define BLOCK_SIZE_LOG2 BL\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#else\n#define BLOCK_SIZE_LOG2 8\n#define BLOCK_SIZE (1 << BLOCK_SIZE_LOG2)\n#define BL BLOCK_SIZE_LOG2\n#endif\n\n// Data type\n#ifdef INT32\n#define T int32_t\n#define DIV 2 // Shift right to divide by sizeof(T)\n#else\n#define T int64_t\n#define DIV 3 // Shift right to divide by sizeof(T)\n#endif\n\n#define PERF 1 // Use perfcounters?\n#define PRINT 0\n\n#define ANSI_COLOR_RED     \"\\x1b[31m\"\n#define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n#define ANSI_COLOR_RESET   \"\\x1b[0m\"\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/support/cyclecount.h",
    "content": "#include <perfcounter.h>\n\n// Timer\ntypedef struct perfcounter_cycles{\n    perfcounter_t start;\n    perfcounter_t end;\n    perfcounter_t end2;\n\n}perfcounter_cycles;\n\nvoid timer_start(perfcounter_cycles *cycles){\n    cycles->start = perfcounter_get(); // START TIMER\n}\n\nuint64_t timer_stop(perfcounter_cycles *cycles){\n    cycles->end = perfcounter_get(); // STOP TIMER\n    cycles->end2 = perfcounter_get(); // STOP TIMER\n    return(((uint64_t)((uint32_t)(((cycles->end >> 4) - (cycles->start >> 4)) - ((cycles->end2 >> 4) - (cycles->end >> 4))))) << 4);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/support/params.h",
    "content": "#ifndef _PARAMS_H_\n#define _PARAMS_H_\n\n#include \"common.h\"\n\ntypedef struct Params {\n    unsigned int   input_size;\n    unsigned int   stride;\n    int   n_warmup;\n    int   n_reps;\n    int  exp;\n}Params;\n\nstatic void usage() {\n    fprintf(stderr,\n        \"\\nUsage:  ./program [options]\"\n        \"\\n\"\n        \"\\nGeneral options:\"\n        \"\\n    -h        help\"\n        \"\\n    -w <W>    # of untimed warmup iterations (default=1)\"\n        \"\\n    -e <E>    # of timed repetition iterations (default=3)\"\n        \"\\n    -x <X>    Weak (0) or strong (1) scaling (default=0)\"\n        \"\\n\"\n        \"\\nBenchmark-specific options:\"\n        \"\\n    -i <I>    input size (default=8K elements)\"\n        \"\\n    -s <S>    stride (default=2)\"\n        \"\\n\");\n}\n\nstruct Params input_params(int argc, char **argv) {\n    struct Params p;\n    p.input_size    = 8 << 10;\n    p.stride        = 2;\n    p.n_warmup      = 1;\n    p.n_reps        = 3;\n    p.exp           = 0;\n\n    int opt;\n    while((opt = getopt(argc, argv, \"hi:w:e:x:s:\")) >= 0) {\n        switch(opt) {\n        case 'h':\n        usage();\n        exit(0);\n        break;\n        case 'i': p.input_size    = atoi(optarg); break;\n        case 'w': p.n_warmup      = atoi(optarg); break;\n        case 'e': p.n_reps        = atoi(optarg); break;\n        case 'x': p.exp           = atoi(optarg); break;\n        case 's': p.stride        = atoi(optarg); break;\n        default:\n            fprintf(stderr, \"\\nUnrecognized option!\\n\");\n            usage();\n            exit(0);\n        }\n    }\n    assert(NR_DPUS > 0 && \"Invalid # of dpus!\");\n    assert((NR_TASKLETS & (NR_TASKLETS - 1)) == 0 && \"Use a power-of-two number of tasklets!\");\n\n    return p;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/benchmark/WRAM/support/timer.h",
    "content": "/*\r\n * Copyright (c) 2016 University of Cordoba and University of Illinois\r\n * All rights reserved.\r\n *\r\n * Developed by:    IMPACT Research Group\r\n *                  University of Cordoba and University of Illinois\r\n *                  http://impact.crhc.illinois.edu/\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * with the Software without restriction, including without limitation the \r\n * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r\n * sell copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n *      > Redistributions of source code must retain the above copyright notice,\r\n *        this list of conditions and the following disclaimers.\r\n *      > Redistributions in binary form must reproduce the above copyright\r\n *        notice, this list of conditions and the following disclaimers in the\r\n *        documentation and/or other materials provided with the distribution.\r\n *      > Neither the names of IMPACT Research Group, University of Cordoba, \r\n *        University of Illinois nor the names of its contributors may be used \r\n *        to endorse or promote products derived from this Software without \r\n *        specific prior written permission.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \r\n * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH\r\n * THE SOFTWARE.\r\n *\r\n */\r\n\r\n#include <sys/time.h>\r\n\r\ntypedef struct Timer{\r\n\r\n    struct timeval startTime[4];\r\n    struct timeval stopTime[4];\r\n    double         time[4];\r\n\r\n}Timer;\r\n\r\nvoid start(Timer *timer, int i, int rep) {\r\n    if(rep == 0) {\r\n        timer->time[i] = 0.0;\r\n    }\r\n    gettimeofday(&timer->startTime[i], NULL);\r\n}\r\n\r\nvoid stop(Timer *timer, int i) {\r\n    gettimeofday(&timer->stopTime[i], NULL);\r\n    timer->time[i] += (timer->stopTime[i].tv_sec - timer->startTime[i].tv_sec) * 1000000.0 +\r\n                      (timer->stopTime[i].tv_usec - timer->startTime[i].tv_usec);\r\n}\r\n\r\nvoid print(Timer *timer, int i, int REP) { printf(\"Time (ms): %f\\t\", timer->time[i] / (1000 * REP)); }\r\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/docker/compiler.dockerfile",
    "content": "FROM ubuntu:20.04\n\nENV DEBIAN_FRONTEND=noninteractive\nENV PYTHONPATH=\"/root/upmem_linker/src:$PYTHONPATH\"\n\nRUN chmod 1777 /tmp\n\nRUN apt update\nRUN apt install -y git\nRUN apt install -y wget\nRUN apt install -y vim\nRUN apt install -y tmux\nRUN apt install -y mlocate\nRUN apt install -y cmake\nRUN apt install -y ninja-build\nRUN apt install -y pkg-config\nRUN apt install -y libnuma-dev\nRUN apt install -y libelf-dev\nRUN apt install -y flex\n\n# Python 3.10\nRUN apt update\nRUN apt upgrade -y\nRUN apt install -y software-properties-common\nRUN add-apt-repository ppa:deadsnakes/ppa\nRUN apt install -y python3.10\nRUN apt install -y python3-pip\n\n# UPMEM LLVM\nWORKDIR /root\nRUN git clone https://github.com/upmem/llvm-project.git\nRUN mkdir -p /root/llvm-project/build\nWORKDIR /root/llvm-project/build\nRUN cmake -G Ninja /root/llvm-project/llvm -DLLVM_ENABLE_PROJECTS=\"clang\"\nRUN cmake build .\n\n# UPMEM SDK\nWORKDIR /root\nRUN wget sdk-releases.upmem.com/2021.3.0/ubuntu_20.04/upmem-2021.3.0-Linux-x86_64.tar.gz\nRUN tar -zxvf upmem-2021.3.0-Linux-x86_64.tar.gz\nRUN echo \"source /root/upmem-2021.3.0-Linux-x86_64/upmem_env.sh\" > /root/.bashrc\n\nWORKDIR /root/upmem_compiler"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/docker/parser.dockerfile",
    "content": "FROM ubuntu:latest\n\nENV DEBIAN_FRONTEND=noninteractive\nENV PYTHONPATH=\"/root/upmem_linker/src:$PYTHONPATH\"\n\nRUN chmod 1777 /tmp\n\nRUN apt update\nRUN apt install -y git\nRUN apt install -y wget\nRUN apt install -y vim\nRUN apt install -y tmux\nRUN apt install -y default-jre\nRUN apt install -y default-jdk\n\n# Python 3.10\nRUN apt update\nRUN apt upgrade -y\nRUN apt install -y software-properties-common\nRUN add-apt-repository ppa:deadsnakes/ppa\nRUN apt install -y python3.10\nRUN apt install -y python3-pip\n\n# ANTLR4\nWORKDIR /root\nRUN wget https://www.antlr.org/download/antlr-4.9.2-complete.jar\nENV CLASSPATH=\"/root/antlr-4.9.2-complete.jar:$CLASSPATH\"\nRUN echo \"alias antlr4='java -Xmx500M -cp \\\"/root/antlr-4.9.2-complete.jar:$CLASSPATH\\\" org.antlr.v4.Tool'\" >> /root/.bashrc\nRUN echo \"alias grun='java -Xmx500M -cp \\\"/root/antlr-4.9.2-complete.jar:$CLASSPATH\\\" org.antlr.v4.gui.TestRig'\" >> /root/.bashrc\n\nWORKDIR /root/upmem_compiler"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/pyproject.toml",
    "content": "[tool.black]\nline-length = 120"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/requirements.txt",
    "content": "antlr4-python3-runtime==4.9.3\nastroid==2.9.3\nattrs==21.4.0\nautoflake==1.4\nblack==22.1.0\ncertifi==2020.6.20\nclick==8.0.4\niniconfig==1.1.1\nisort==5.10.1\nlazy-object-proxy==1.7.1\nmypy-extensions==0.4.3\nnumpy==1.22.3\npackaging==21.3\npathspec==0.9.0\nplatformdirs==2.5.1\npluggy==1.0.0\npy==1.11.0\npyflakes==2.4.0\npyparsing==3.0.7\npytest==7.0.1\ntomli==2.0.1\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/accessMramFromDpu.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    // Preconditions:\n    //  - MRAM offset is a multiple of 8\n    //  - Buffer size is a multiple of 8\n\n    __asm__ volatile(\"  sd zero, 0, d0\\n\" // Saving context\n                     \"  sd zero, 8, d2\\n\"\n                     \"  or r0, zero, 0, ?xnz, . + 2\\n\"\n                     \"  or r0, r0, 0x2\\n\"\n                     \"  addc r0, r0, 0\\n\"\n                     \"  sw zero, 16, r0\\n\"\n                     \"  lw r0, zero, 20\\n\" // MRAM offset, must be patched by the Host\n                     \"resume_start:\\n\"\n                     \"  lw r1, zero, 24\\n\" // Buffer size, must be patched by the Host\n                     \"  move r2, 32\\n\" // Wram offset\n                     \"  move r3, 2048\\n\" // Transfer size\n                     \"  transfer_loop:\\n\"\n                     \"  jltu r1, r3, last_transfer\\n\"\n                     \"  ldma r2, r0, 255\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r3\\n\"\n                     \"  add r2, r2, r3\\n\"\n                     \"  sub r1, r1, r3, true, transfer_loop\\n\"\n                     \"last_transfer:\\n\"\n                     \"  jz r1, end\\n\"\n                     \"  lsr r3, r1, 3\\n\"\n                     \"  add r3, r3, -1\\n\"\n                     \"  lsl_add r2, r2, r3, 24\\n\"\n                     \"  ldma r2, r0, 0\\n\" // Can be patched by the Host into a SDMA to write MRAM\n                     \"  add r0, r0, r1\\n\"\n                     \"end:\\n\"\n                     \"  lw r2, zero, 28\\n\" // Restoring context if needed\n                     \"  jnz r2, . + 2\\n\"\n                     \"  stop true, resume_start\\n\"\n                     \"  ld d2, zero, 8\\n\"\n                     \"  lw r0, zero, 16\\n\"\n                     \"  add r1, r0, r0\\n\"\n                     \"  add r0, r0, r1\\n\"\n                     \"  call zero, r0, . + 1\\n\"\n                     \"  add r0, zero, 0x00000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 0\n                     \"  add r0, mneg, 0x80000001; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 0, C = 1\n                     \"  add r0, zero, 0x00000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 0\n                     \"  add r0, mneg, 0x80000000; ld d0, zero, 0; stop true, 0\\n\" // ... restore Z = 1, C = 1\n    );\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/coreDump.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"core dump\" program, used by debugging processes to fetch each\n * runtime register and the atomic bits.\n * The program should be booted once on runtime 0.\n *\n * The output in WRAM has the following form:\n *  - byte 0..255 = atomic bits : each bit is stored into an individual byte\n *  - byte 256..2559 = work registers\n *  - byte 2560..2555 = flags\n *\n * Only the runtime 0 fills in the atomic bits part of the output.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0), d0\\n\"\n        \"  or r0, zero, 0, ?xnz, no_z_flag\\n\"\n        \"  or r0, r0, 0x2\\n\"\n        \"  no_z_flag:\\n\"\n        \"  addc r0, r0, 0\\n\"\n        \"  sw id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12), r0\\n\"\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1), d2\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2), d4\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3), d6\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4), d8\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5), d10\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6), d12\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7), d14\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8), d16\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9), d18\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10), d20\\n\"\n        \"  sd id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11), d22\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  sb r0, 0, 0xFF\\n\"\n        \"  acquire r0, 0, nz, atomic_next\\n\"\n        \"  sb r0, 0, 0x00\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/crt0.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <macro_utils.h>\n#include <attributes.h>\n#include <stdint.h>\n#include <dpuruntime.h>\n\n__mram_noinit uint8_t __sys_used_mram_end[0];\n\nuint64_t __sys_null_pointer __attribute__((used, section(\".data.__sys_zero\"))) = 0ULL;\n\nuint32_t __lower_data(\"thread_profiling\") thread_profiling[NR_THREADS];\nuint32_t perfcounter_end_value;\n\n#define DECLARE_STACK(x)                                                                                                         \\\n    extern uint32_t __sys_stack_thread_##x;                                                                                      \\\n    extern uint32_t STACK_SIZE_TASKLET_##x;\n#define SET_STACK_TABLE_PTR(x)                                                                                                   \\\n    [x] = { .stack_ptr = (uint32_t)&__sys_stack_thread_##x, .stack_size = (uint32_t)&STACK_SIZE_TASKLET_##x },\n\n__FOR_EACH_THREAD(DECLARE_STACK);\n\nthread_stack_t __keep __dma_aligned __SP_TABLE__[NR_THREADS] = { __FOR_EACH_THREAD(SET_STACK_TABLE_PTR) };\n\n__host const volatile uint32_t CLOCKS_PER_SEC;\n\n__host const volatile uint32_t error_storage;\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"), no_instrument_function)) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jnz id, __sys_start_thread\\n\"\n        __CONFIG_PERFCOUNTER_ENTRY__\n        \"  sd zero, \" __STR(__STDOUT_BUFFER_STATE) \", 0\\n\"\n        \"  move r23, \" __STR(__atomic_end_addr) \"\\n\"\n        \"__sys_atomic_bit_clear:\\n\"\n        \"  jeq r23, \" __STR(__atomic_used_addr) \", __sys_start_thread\\n\"\n        \"  release r23, 0, nz, . + 1\\n\"\n        \"  add r23, r23, -1, true, __sys_atomic_bit_clear\\n\"\n        \"__sys_start_thread:\\n\"\n        \"  jeq id, NR_TASKLETS - 1, . + 2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d22, id8, \" __STR(__SP_TABLE__) \"\\n\"\n        \"  call r23, main\\n\"\n        \".globl __sys_end\\n\"\n        \"__sys_end:\\n\"\n        __SAVE_PERFCOUNTER_ENTRY__\n        \"  stop true, __sys_end\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/dpu.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Default linker script for DPU programs.\n * The bootstrap sequence is generated by the studio as __bootstrap.\n * The two DPU memories (IRAM and WRAM) are mapped on two different\n * \"virtual\" spaces:\n *  - IRAM: starts at address 0x80000000, which may imply fixups\n *    when loading and debugging of programs\n *  - WRAM: exposed as is at address 0x00000000\n *\n * In addition, the run-time environment information is stored into\n * a virtual physical space at 0x40000000.\n */\nENTRY(__bootstrap)\nMEMORY {\n    iram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n    mram (wa) : ORIGIN = 0x08000000, LENGTH = 64M\n    wram (wa) : ORIGIN = 0x00000000, LENGTH = 64K\n    atomic (r) : ORIGIN = 0xF0000000, LENGTH = 256\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text.__bootstrap)\n    *(.text)\n    *(.text.*) \n  } > iram\n\n  /*\n   * Atomic bits 'allocator'\n   */\n  .atomic (NOLOAD) : {\n    __atomic_start_addr = .;\n    . = . + 200;\n    __atomic_used_addr = .;\n    *(.atomic)\n    __atomic_end_addr = .;\n  } > atomic\n\n  /*\n   * Locate every other section as data.\n   */\n  .data : {\n    KEEP(*(.data.__sys_zero))\n    . += MAX(8, .);\n    /* WRAM accessible using loads and stores with immediate 11-bit offsets */\n    *(.data.immediate_memory .data.immediate_memory.*)\n    HIDDEN(__imm_mem_end = .);\n    ASSERT(__imm_mem_end < 2048, \"immediate memory not accessible with 11-bit address\")\n    __rodata_start_addr = .;\n    *(.rodata .rodata.*)\n    __rodata_end_addr = .;\n    *(.bss .bss.*)\n    *(COMMON)\n    /* Data that we want to keep even there seems to be no use,\n     * usually because host may need it.\n     */\n    KEEP(*(.data.__sys_keep))\n    *(.data .data.*)\n    . = ALIGN(8);\n  } > wram\n\n  .data.__sys_host : {\n    . = ALIGN(8);\n    KEEP(*(.dpu_host))\n  } > wram\n\n  .data.__sys_profiling : {\n    . = ALIGN(4);\n    KEEP(*(.dpu_profiling))\n  } > wram\n\n  .data.stacks (NOLOAD) : {\n    ASSERT(NR_TASKLETS >= 0 && NR_TASKLETS <= 24, \"NR_TASKLETS should be in the range: [0; 24]\")\n    ASSERT(((STACK_SIZE_TASKLET_0  % 8 == 0) && (STACK_SIZE_TASKLET_0  > 0)) || (NR_TASKLETS <= 0 ), \"STACK_SIZE_TASKLET_0  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_1  % 8 == 0) && (STACK_SIZE_TASKLET_1  > 0)) || (NR_TASKLETS <= 1 ), \"STACK_SIZE_TASKLET_1  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_2  % 8 == 0) && (STACK_SIZE_TASKLET_2  > 0)) || (NR_TASKLETS <= 2 ), \"STACK_SIZE_TASKLET_2  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_3  % 8 == 0) && (STACK_SIZE_TASKLET_3  > 0)) || (NR_TASKLETS <= 3 ), \"STACK_SIZE_TASKLET_3  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_4  % 8 == 0) && (STACK_SIZE_TASKLET_4  > 0)) || (NR_TASKLETS <= 4 ), \"STACK_SIZE_TASKLET_4  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_5  % 8 == 0) && (STACK_SIZE_TASKLET_5  > 0)) || (NR_TASKLETS <= 5 ), \"STACK_SIZE_TASKLET_5  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_6  % 8 == 0) && (STACK_SIZE_TASKLET_6  > 0)) || (NR_TASKLETS <= 6 ), \"STACK_SIZE_TASKLET_6  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_7  % 8 == 0) && (STACK_SIZE_TASKLET_7  > 0)) || (NR_TASKLETS <= 7 ), \"STACK_SIZE_TASKLET_7  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_8  % 8 == 0) && (STACK_SIZE_TASKLET_8  > 0)) || (NR_TASKLETS <= 8 ), \"STACK_SIZE_TASKLET_8  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_9  % 8 == 0) && (STACK_SIZE_TASKLET_9  > 0)) || (NR_TASKLETS <= 9 ), \"STACK_SIZE_TASKLET_9  should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_10 % 8 == 0) && (STACK_SIZE_TASKLET_10 > 0)) || (NR_TASKLETS <= 10), \"STACK_SIZE_TASKLET_10 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_11 % 8 == 0) && (STACK_SIZE_TASKLET_11 > 0)) || (NR_TASKLETS <= 11), \"STACK_SIZE_TASKLET_11 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_12 % 8 == 0) && (STACK_SIZE_TASKLET_12 > 0)) || (NR_TASKLETS <= 12), \"STACK_SIZE_TASKLET_12 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_13 % 8 == 0) && (STACK_SIZE_TASKLET_13 > 0)) || (NR_TASKLETS <= 13), \"STACK_SIZE_TASKLET_13 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_14 % 8 == 0) && (STACK_SIZE_TASKLET_14 > 0)) || (NR_TASKLETS <= 14), \"STACK_SIZE_TASKLET_14 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_15 % 8 == 0) && (STACK_SIZE_TASKLET_15 > 0)) || (NR_TASKLETS <= 15), \"STACK_SIZE_TASKLET_15 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_16 % 8 == 0) && (STACK_SIZE_TASKLET_16 > 0)) || (NR_TASKLETS <= 16), \"STACK_SIZE_TASKLET_16 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_17 % 8 == 0) && (STACK_SIZE_TASKLET_17 > 0)) || (NR_TASKLETS <= 17), \"STACK_SIZE_TASKLET_17 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_18 % 8 == 0) && (STACK_SIZE_TASKLET_18 > 0)) || (NR_TASKLETS <= 18), \"STACK_SIZE_TASKLET_18 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_19 % 8 == 0) && (STACK_SIZE_TASKLET_19 > 0)) || (NR_TASKLETS <= 19), \"STACK_SIZE_TASKLET_19 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_20 % 8 == 0) && (STACK_SIZE_TASKLET_20 > 0)) || (NR_TASKLETS <= 20), \"STACK_SIZE_TASKLET_20 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_21 % 8 == 0) && (STACK_SIZE_TASKLET_21 > 0)) || (NR_TASKLETS <= 21), \"STACK_SIZE_TASKLET_21 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_22 % 8 == 0) && (STACK_SIZE_TASKLET_22 > 0)) || (NR_TASKLETS <= 22), \"STACK_SIZE_TASKLET_22 should be a multiple of 8 and > 0\")\n    ASSERT(((STACK_SIZE_TASKLET_23 % 8 == 0) && (STACK_SIZE_TASKLET_23 > 0)) || (NR_TASKLETS <= 23), \"STACK_SIZE_TASKLET_23 should be a multiple of 8 and > 0\")\n    ASSERT((NR_TASKLETS > 0 ) || (STACK_SIZE_TASKLET_0  == 0) , \"STACK_SIZE_TASKLET_0  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 1 ) || (STACK_SIZE_TASKLET_1  == 0) , \"STACK_SIZE_TASKLET_1  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 2 ) || (STACK_SIZE_TASKLET_2  == 0) , \"STACK_SIZE_TASKLET_2  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 3 ) || (STACK_SIZE_TASKLET_3  == 0) , \"STACK_SIZE_TASKLET_3  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 4 ) || (STACK_SIZE_TASKLET_4  == 0) , \"STACK_SIZE_TASKLET_4  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 5 ) || (STACK_SIZE_TASKLET_5  == 0) , \"STACK_SIZE_TASKLET_5  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 6 ) || (STACK_SIZE_TASKLET_6  == 0) , \"STACK_SIZE_TASKLET_6  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 7 ) || (STACK_SIZE_TASKLET_7  == 0) , \"STACK_SIZE_TASKLET_7  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 8 ) || (STACK_SIZE_TASKLET_8  == 0) , \"STACK_SIZE_TASKLET_8  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 9 ) || (STACK_SIZE_TASKLET_9  == 0) , \"STACK_SIZE_TASKLET_9  should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 10) || (STACK_SIZE_TASKLET_10 == 0) , \"STACK_SIZE_TASKLET_10 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 11) || (STACK_SIZE_TASKLET_11 == 0) , \"STACK_SIZE_TASKLET_11 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 12) || (STACK_SIZE_TASKLET_12 == 0) , \"STACK_SIZE_TASKLET_12 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 13) || (STACK_SIZE_TASKLET_13 == 0) , \"STACK_SIZE_TASKLET_13 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 14) || (STACK_SIZE_TASKLET_14 == 0) , \"STACK_SIZE_TASKLET_14 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 15) || (STACK_SIZE_TASKLET_15 == 0) , \"STACK_SIZE_TASKLET_15 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 16) || (STACK_SIZE_TASKLET_16 == 0) , \"STACK_SIZE_TASKLET_16 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 17) || (STACK_SIZE_TASKLET_17 == 0) , \"STACK_SIZE_TASKLET_17 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 18) || (STACK_SIZE_TASKLET_18 == 0) , \"STACK_SIZE_TASKLET_18 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 19) || (STACK_SIZE_TASKLET_19 == 0) , \"STACK_SIZE_TASKLET_19 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 20) || (STACK_SIZE_TASKLET_20 == 0) , \"STACK_SIZE_TASKLET_20 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 21) || (STACK_SIZE_TASKLET_21 == 0) , \"STACK_SIZE_TASKLET_21 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 22) || (STACK_SIZE_TASKLET_22 == 0) , \"STACK_SIZE_TASKLET_22 should be equal to 0 as the tasklet is not active\")\n    ASSERT((NR_TASKLETS > 23) || (STACK_SIZE_TASKLET_23 == 0) , \"STACK_SIZE_TASKLET_23 should be equal to 0 as the tasklet is not active\")\n    . = ALIGN(8);\n    __sys_stack_thread_0  = .;\n    . += STACK_SIZE_TASKLET_0;\n    __sys_stack_thread_1  = .;\n    . += STACK_SIZE_TASKLET_1;\n    __sys_stack_thread_2  = .;\n    . += STACK_SIZE_TASKLET_2;\n    __sys_stack_thread_3  = .;\n    . += STACK_SIZE_TASKLET_3;\n    __sys_stack_thread_4  = .;\n    . += STACK_SIZE_TASKLET_4;\n    __sys_stack_thread_5  = .;\n    . += STACK_SIZE_TASKLET_5;\n    __sys_stack_thread_6  = .;\n    . += STACK_SIZE_TASKLET_6;\n    __sys_stack_thread_7  = .;\n    . += STACK_SIZE_TASKLET_7;\n    __sys_stack_thread_8  = .;\n    . += STACK_SIZE_TASKLET_8;\n    __sys_stack_thread_9  = .;\n    . += STACK_SIZE_TASKLET_9;\n    __sys_stack_thread_10 = .;\n    . += STACK_SIZE_TASKLET_10;\n    __sys_stack_thread_11 = .;\n    . += STACK_SIZE_TASKLET_11;\n    __sys_stack_thread_12 = .;\n    . += STACK_SIZE_TASKLET_12;\n    __sys_stack_thread_13 = .;\n    . += STACK_SIZE_TASKLET_13;\n    __sys_stack_thread_14 = .;\n    . += STACK_SIZE_TASKLET_14;\n    __sys_stack_thread_15 = .;\n    . += STACK_SIZE_TASKLET_15;\n    __sys_stack_thread_16 = .;\n    . += STACK_SIZE_TASKLET_16;\n    __sys_stack_thread_17 = .;\n    . += STACK_SIZE_TASKLET_17;\n    __sys_stack_thread_18 = .;\n    . += STACK_SIZE_TASKLET_18;\n    __sys_stack_thread_19 = .;\n    . += STACK_SIZE_TASKLET_19;\n    __sys_stack_thread_20 = .;\n    . += STACK_SIZE_TASKLET_20;\n    __sys_stack_thread_21 = .;\n    . += STACK_SIZE_TASKLET_21;\n    __sys_stack_thread_22 = .;\n    . += STACK_SIZE_TASKLET_22;\n    __sys_stack_thread_23 = .;\n    . += STACK_SIZE_TASKLET_23;\n    . = ALIGN(8);\n  } > wram\n\n\n  .data.sw_cache (NOLOAD): {\n    . = ALIGN(8);\n    __sw_cache_buffer = .;\n    . += 8 * NR_TASKLETS;\n  } > wram\n\n  .data.heap_pointer_reset (NOLOAD) : {\n    /* Start of heap: must be aligned on DMA size.\n     * Stored as a symbol \"__reset_heap_pointer\", so that\n     * the bootstrap just moves the value into a register to\n     * initialize heap pointer at each reboot.\n     */\n    . = ALIGN(8);\n    PROVIDE(__sys_heap_pointer_reset = .);\n  } > wram\n\n  .mram.noinit (NOLOAD) : {\n    *(.mram.noinit .mram.noinit.*)\n    KEEP(*(.mram.noinit.keep .mram.noinit.keep.*))\n  } > mram\n\n  .mram : {\n    *(.mram .mram.*)\n    KEEP(*(.mram.keep .mram.keep.*))\n    . = ALIGN(8);\n    __sys_used_mram_end = .;\n  } > mram\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/internalStateReset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The strict minimum to reset the internal state of the DPU (that can only be changed by a DPU program).\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  sub r0, \" __STR(NR_ATOMIC_BITS) \" - 1, id\\n\"\n        \"before_release:\\n\"\n        // Resetting Atomic bits\n        \"  release r0, 0, nz, after_release\\n\"\n        \"after_release:\\n\"\n        \"  sub r0, r0, \" __STR(NR_THREADS) \", pl, before_release\\n\"\n        // Resetting Zero and Carry flags + Preparing configuration for perfcounter register\n        \"  add r0, zero, 7\\n\"\n        // Resetting Performance Counter\n        \"  time_cfg zero, r0\\n\"\n        // Resetting Pc\n        \"  stop true, 0\\n\");\n    /* clang-format on */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/linkerScript.lds",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Simple linker script for embedded programs.\n */\nENTRY(__bootstrap)\nMEMORY {\n\tiram (rx) : ORIGIN = 0x80000000, LENGTH = 32K\n}\nSECTIONS\n{\n  /*\n   * Merge every text section into .text.\n   */\n  .text : {\n    *(.text)\n  } > iram\n}\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/restoreRegisters.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * The \"restore registers\" program, is used by debugging processes to restore every registers of every runtime.\n * The program should be booted once on runtime 0.\n */\n\n#include \"restore_carry_and_zero_flag.h\"\n\nvoid __attribute__((naked, used, section(\".text.__bootstrap\"))) __bootstrap()\n{\n    /* clang-format off */\n    __asm__ volatile(\n        \"  jeq id, \" __STR(NR_THREADS) \" - 1, .+2\\n\"\n        \"  boot id, 1\\n\"\n        \"  ld d2,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  1)\\n\"\n        \"  ld d4,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  2)\\n\"\n        \"  ld d6,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  3)\\n\"\n        \"  ld d8,  id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  4)\\n\"\n        \"  ld d10, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  5)\\n\"\n        \"  ld d12, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  6)\\n\"\n        \"  ld d14, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  7)\\n\"\n        \"  ld d16, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  8)\\n\"\n        \"  ld d18, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 *  9)\\n\"\n        \"  ld d20, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 10)\\n\"\n        \"  ld d22, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 11)\\n\"\n        \"  jnz id, atomic_done\\n\"\n        \"  move r0, \" __STR(NR_ATOMIC_BITS) \" - 1\\n\"\n        \"atomic_loop:\\n\"\n        \"  lbu r1, r0, 0\\n\"\n        \"  jz r1, atomic_release\\n\"\n        \"  acquire r0, 0, true, atomic_next\\n\"\n        \"atomic_release:\\n\"\n        \"  release r0, 0, nz, atomic_next\\n\"\n        \"atomic_next:\\n\"\n        \"  add r0, r0, -1, pl, atomic_loop\\n\"\n        \"atomic_done:\\n\"\n        RESTORE_CARRY_AND_ZERO_FLAG\n    );\n    /* clang-format on */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/misc/restore_carry_and_zero_flag.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"macro_utils.h\"\n\n/* clang-format off */\n#define __RESTORE_CARRY_AND_ZERO_FLAG(x) \\\n        \"add r0, zero, 0x00000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 0 */ \\\n        \"add r0, mneg, 0x80000001; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 0, C = 1 */ \\\n        \"add r0, zero, 0x00000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" /* ... restore Z = 1, C = 0 */ \\\n        \"add r0, mneg, 0x80000000; ld d0, id8, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 0); stop true, 0\\n\" // ... restore Z = 1, C = 1 */\n\n#define RESTORE_CARRY_AND_ZERO_FLAG \\\n        \"  lw r0,  id4, \" __STR(NR_ATOMIC_BITS) \" + (\" __STR(NR_THREADS) \" * 8 * 12)\\n\" \\\n        \"  add r1, r0,  r0\\n\" \\\n        \"  add r0, r0,  r1\\n\" /* r0 =  3 * r0 (each line of ending_routines is 3 instructions) */ \\\n        \"  or  r1, id8, 0 \\n\" \\\n        \"  add r1, id4, r1\\n\" /* r1 = 12 * id (there are 12 instructions per runtime in ending_routines) */ \\\n        \"  add r0, r0,  r1\\n\" /* r0 = r0 + r1 (compute the offset (in number of instructions) to jump to) */ \\\n        \"  call zero, r0, ending_routines\\n\" \\\n        \"ending_routines:\\n\" \\\n        __FOR_EACH_THREAD(__RESTORE_CARRY_AND_ZERO_FLAG)\n\n/* clang-format on */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/abort.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n\nvoid\nabort()\n{\n    halt();\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/assert.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ASSERT_H_\n#define _DPUSYSCORE_ASSERT_H_\n\n/**\n * @file assert.h\n * @brief Provides a way to verify assumptions with <code>assert</code>.\n */\n\n#define static_assert _Static_assert\n\n#ifdef NDEBUG\n\n/**\n * @def assert\n * @hideinitializer\n * @brief When NDEBUG is defined, <code>assert</code> is not available and calling it will do nothing.\n */\n#define assert(ignore) ((void)0)\n\n#else\n\n#include <dpufault.h>\n#include <macro_utils.h>\n\n/**\n * @def assert\n * @hideinitializer\n * @brief Verify the assumption of the specified expression, resulting in a fault if it fails.\n *\n * @param expression the assumption to verify\n * @throws FAULT_ASSERT_FAILED when the assertion failed\n * @todo add a diagnostic message to the log, if it exists, when the assertion fails\n */\n#define assert(expression)                                                                                                       \\\n    do {                                                                                                                         \\\n        if (!(expression)) {                                                                                                     \\\n            __asm__ volatile(\"fault \" __STR(__FAULT_ASSERT_FAILED__));                                                           \\\n        }                                                                                                                        \\\n    } while (0)\n\n#endif /* NDEBUG */\n\n#endif /* _DPUSYSCORE_ASSERT_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/atoi.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nint\natoi(const char *nptr)\n{\n    int result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/atol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <ctype.h>\n\nlong\natol(const char *nptr)\n{\n    long result = 0;\n    bool is_positive = true;\n\n    if (nptr == NULL) {\n        return result;\n    }\n\n    while (isspace(*nptr)) {\n        nptr++;\n    }\n\n    if (*nptr == '-') {\n        is_positive = false;\n        nptr++;\n    } else if (*nptr == '+') {\n        nptr++;\n    }\n\n    for (;; nptr++) {\n        unsigned int digit = *nptr - '0';\n\n        if (digit > 9) {\n            break;\n        }\n\n        result = (10 * result) + digit;\n    }\n\n    return is_positive ? result : -result;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/ctype.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_CTYPE_H_\n#define _DPUSYSCORE_CTYPE_H_\n\n/**\n * @file ctype.h\n * @brief Provides useful functions for testing and mapping characters.\n */\n\n/**\n * @brief Checks whether the specified character is a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisdigit(int c)\n{\n    return (c >= '0') && (c <= '9');\n}\n\n/**\n * @brief Checks whether the specified character is a lowercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a digit (using 0 as false and anything else as true).\n */\nstatic inline int islower(c) { return (c >= 'a') && (c <= 'z'); }\n\n/**\n * @brief Checks whether the specified character is an uppercase letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is an uppercase letter (using 0 as false and anything else as true).\n */\nstatic inline int isupper(c) { return (c >= 'A') && (c <= 'Z'); }\n\n/**\n * @brief Checks whether the specified character is a letter.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter (using 0 as false and anything else as true).\n */\nstatic inline int\nisalpha(int c)\n{\n    return islower(c) || isupper(c);\n}\n\n/**\n * @brief Checks whether the specified character is a letter or a digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a letter or a digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisalnum(int c)\n{\n    return isalpha(c) || isdigit(c);\n}\n\n/**\n * @brief Checks whether the specified character is a control character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a control character (using 0 as false and anything else as true).\n */\nstatic inline int\niscntrl(int c)\n{\n    return (c <= 0x1f) || (c == 0x7f);\n}\n\n/**\n * @brief Checks whether the specified character is printable.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is printable (using 0 as false and anything else as true).\n */\nstatic inline int\nisprint(int c)\n{\n    return !iscntrl(c);\n}\n\n/**\n * @brief Checks whether the specified character has graphical representation using locale.\n\n * @param c an unsigned char or EOF\n * @return Whether the character has graphical representation using locale (using 0 as false and anything else as true).\n */\nstatic inline int\nisgraph(int c)\n{\n    return isprint(c) && (c != ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a punctuation character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a punctuation character (using 0 as false and anything else as true).\n */\nstatic inline int\nispunct(int c)\n{\n    return (c >= '!' && c <= '/') || (c >= ':' && c <= '@') || (c >= '[' && c <= '`') || (c >= '{' && c <= '~');\n}\n\n/**\n * @brief Checks whether the specified character is a white-space.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a white-space (using 0 as false and anything else as true).\n */\nstatic inline int\nisspace(int c)\n{\n    return (c >= 0x9 && c <= 0xd) || (c == ' ');\n}\n\n/**\n * @brief Checks whether the specified character is a hexadecimal digit.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a hexadecimal digit (using 0 as false and anything else as true).\n */\nstatic inline int\nisxdigit(int c)\n{\n    return isdigit(c) || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f');\n}\n\n/**\n * @brief Checks whether the specified character is a blank character.\n\n * @param c an unsigned char or EOF\n * @return Whether the character is a blank character (using 0 as false and anything else as true).\n */\nstatic inline int\nisblank(int c)\n{\n    return c == ' ' || c == '\\t';\n}\n\n/**\n * @brief Converts the specified character to a lowercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The lowercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntolower(int c)\n{\n    return isupper(c) ? (c + 0x20) : c;\n}\n\n/**\n * @brief Converts the specified character to a uppercase letter if it is a letter;\n\n * @param c an unsigned char or EOF\n * @return The uppercase letter corresponding to the character, if it is a letter. The initial character otherwise.\n */\nstatic inline int\ntoupper(int c)\n{\n    return islower(c) ? (c - 0x20) : c;\n}\n\n#endif /* _DPUSYSCORE_CTYPE_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/errno.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nint __errno[NR_THREADS];\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/errno.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ERRNO_H_\n#define _DPUSYSCORE_ERRNO_H_\n\n#include <defs.h>\n\n/**\n * @file errno.h\n * @brief Defines the system error numbers.\n */\n\n// errno is an array indexed on the tasklet id rather than\n// a single integer.\nextern int __errno[];\n\n// Mimic errno variable as an index to __errno.\n// Defined in such a way that users can't override errno.\n#define errno (*(__errno + me()))\n\n/**\n * @def E2BIG\n * @brief  Argument list too long.\n */\n#define E2BIG 1\n/**\n * @def EACCES\n * @brief  Permission denied.\n */\n#define EACCES 2\n/**\n * @def EADDRINUSE\n * @brief  Address in use.\n */\n#define EADDRINUSE 3\n/**\n * @def EADDRNOTAVAIL\n * @brief  Address not available.\n */\n#define EADDRNOTAVAIL 4\n/**\n * @def EAFNOSUPPORT\n * @brief  Address family not supported.\n */\n#define EAFNOSUPPORT 5\n/**\n * @def EAGAIN\n * @brief  Resource unavailable, try again.\n */\n#define EAGAIN 6\n/**\n * @def EALREADY\n * @brief  Connection already in progress.\n */\n#define EALREADY 7\n/**\n * @def EBADF\n * @brief  Bad file descriptor.\n */\n#define EBADF 8\n/**\n * @def EBADMSG\n * @brief  Bad message.\n */\n#define EBADMSG 9\n/**\n * @def EBUSY\n * @brief  Device or resource busy.\n */\n#define EBUSY 10\n/**\n * @def ECANCELED\n * @brief  Operation canceled.\n */\n#define ECANCELED 11\n/**\n * @def ECHILD\n * @brief  No child processes.\n */\n#define ECHILD 12\n/**\n * @def ECONNABORTED\n * @brief  Connection aborted.\n */\n#define ECONNABORTED 13\n/**\n * @def ECONNREFUSED\n * @brief  Connection refused.\n */\n#define ECONNREFUSED 14\n/**\n * @def ECONNRESET\n * @brief  Connection reset.\n */\n#define ECONNRESET 15\n/**\n * @def EDEADLK\n * @brief  Resource deadlock would occur.\n */\n#define EDEADLK 16\n/**\n * @def EDESTADDRREQ\n * @brief  Destination address required.\n */\n#define EDESTADDRREQ 17\n/**\n * @def EDOM\n * @brief  Mathematics argument out of domain of function.\n */\n#define EDOM 18\n/**\n * @def EDQUOT\n * @brief  Reserved.\n */\n#define EDQUOT 19\n/**\n * @def EEXIST\n * @brief  File exists.\n */\n#define EEXIST 20\n/**\n * @def EFAULT\n * @brief  Bad address.\n */\n#define EFAULT 21\n/**\n * @def EFBIG\n * @brief  File too large.\n */\n#define EFBIG 22\n/**\n * @def EHOSTUNREACH\n * @brief  Host is unreachable.\n */\n#define EHOSTUNREACH 23\n/**\n * @def EIDRM\n * @brief  Identifier removed.\n */\n#define EIDRM 24\n/**\n * @def EILSEQ\n * @brief  Illegal byte sequence.\n */\n#define EILSEQ 25\n/**\n * @def EINPROGRESS\n * @brief  Operation in progress.\n */\n#define EINPROGRESS 26\n/**\n * @def EINTR\n * @brief  Interrupted function.\n */\n#define EINTR 27\n/**\n * @def EINVAL\n * @brief  Invalid argument.\n */\n#define EINVAL 28\n/**\n * @def EIO\n * @brief  I/O error.\n */\n#define EIO 29\n/**\n * @def EISCONN\n * @brief  Socket is connected.\n */\n#define EISCONN 30\n/**\n * @def EISDIR\n * @brief  Is a directory.\n */\n#define EISDIR 31\n/**\n * @def ELOOP\n * @brief  Too many levels of symbolic links.\n */\n#define ELOOP 32\n/**\n * @def EMFILE\n * @brief  File descriptor value too large.\n */\n#define EMFILE 33\n/**\n * @def EMLINK\n * @brief  Too many links.\n */\n#define EMLINK 34\n/**\n * @def EMSGSIZE\n * @brief  Message too large.\n */\n#define EMSGSIZE 35\n/**\n * @def EMULTIHOP\n * @brief  Reserved.\n */\n#define EMULTIHOP 36\n/**\n * @def ENAMETOOLONG\n * @brief  Filename too long.\n */\n#define ENAMETOOLONG 37\n/**\n * @def ENETDOWN\n * @brief  Network is down.\n */\n#define ENETDOWN 38\n/**\n * @def ENETRESET\n * @brief  Connection aborted by network.\n */\n#define ENETRESET 39\n/**\n * @def ENETUNREACH\n * @brief  Network unreachable.\n */\n#define ENETUNREACH 40\n/**\n * @def ENFILE\n * @brief  Too many files open in system.\n */\n#define ENFILE 41\n/**\n * @def ENOBUFS\n * @brief  No buffer space available.\n */\n#define ENOBUFS 42\n/**\n * @def ENODATA\n * @brief  No message is available on the STREAM head read queue.\n */\n#define ENODATA 43\n/**\n * @def ENODEV\n * @brief  No such device.\n */\n#define ENODEV 44\n/**\n * @def ENOENT\n * @brief  No such file or directory.\n */\n#define ENOENT 45\n/**\n * @def ENOEXEC\n * @brief  Executable file format error.\n */\n#define ENOEXEC 46\n/**\n * @def ENOLCK\n * @brief  No locks available.\n */\n#define ENOLCK 47\n/**\n * @def ENOLINK\n * @brief  Reserved.\n */\n#define ENOLINK 48\n/**\n * @def ENOMEM\n * @brief  Not enough space.\n */\n#define ENOMEM 49\n/**\n * @def ENOMSG\n * @brief  No message of the desired type.\n */\n#define ENOMSG 50\n/**\n * @def ENOPROTOOPT\n * @brief  Protocol not available.\n */\n#define ENOPROTOOPT 51\n/**\n * @def ENOSPC\n * @brief  No space left on device.\n */\n#define ENOSPC 52\n/**\n * @def ENOSR\n * @brief  No STREAM resources.\n */\n#define ENOSR 53\n/**\n * @def ENOSTR\n * @brief  Not a STREAM.\n */\n#define ENOSTR 54\n/**\n * @def ENOSYS\n * @brief  Function not supported.\n */\n#define ENOSYS 55\n/**\n * @def ENOTCONN\n * @brief  The socket is not connected.\n */\n#define ENOTCONN 56\n/**\n * @def ENOTDIR\n * @brief  Not a directory or a symbolic link to a directory.\n */\n#define ENOTDIR 57\n/**\n * @def ENOTEMPTY\n * @brief  Directory not empty.\n */\n#define ENOTEMPTY 58\n/**\n * @def ENOTRECOVERABLE\n * @brief  State not recoverable.\n */\n#define ENOTRECOVERABLE 59\n/**\n * @def ENOTSOCK\n * @brief  Not a socket.\n */\n#define ENOTSOCK 60\n/**\n * @def ENOTSUP\n * @brief  Not supported.\n */\n#define ENOTSUP 61\n/**\n * @def ENOTTY\n * @brief  Inappropriate I/O control operation.\n */\n#define ENOTTY 62\n/**\n * @def ENXIO\n * @brief  No such device or address.\n */\n#define ENXIO 63\n/**\n * @def EOPNOTSUPP\n * @brief  Operation not supported on socket.\n */\n#define EOPNOTSUPP ENOTSUP\n/**\n * @def EOVERFLOW\n * @brief  Value too large to be stored in data type.\n */\n#define EOVERFLOW 65\n/**\n * @def EOWNERDEAD\n * @brief  Previous owner died.\n */\n#define EOWNERDEAD 66\n/**\n * @def EPERM\n * @brief  Operation not permitted.\n */\n#define EPERM 67\n/**\n * @def EPIPE\n * @brief  Broken pipe.\n */\n#define EPIPE 68\n/**\n * @def EPROTO\n * @brief  Protocol error.\n */\n#define EPROTO 69\n/**\n * @def EPROTONOSUPPORT\n * @brief  Protocol not supported.\n */\n#define EPROTONOSUPPORT 70\n/**\n * @def EPROTOTYPE\n * @brief  Protocol wrong type for socket.\n */\n#define EPROTOTYPE 71\n/**\n * @def ERANGE\n * @brief  Result too large.\n */\n#define ERANGE 72\n/**\n * @def EROFS\n * @brief  Read-only file system.\n */\n#define EROFS 73\n/**\n * @def ESPIPE\n * @brief  Invalid seek.\n */\n#define ESPIPE 74\n/**\n * @def ESRCH\n * @brief  No such process.\n */\n#define ESRCH 75\n/**\n * @def ESTALE\n * @brief  Reserved.\n */\n#define ESTALE 76\n/**\n * @def ETIME\n * @brief  Stream ioctl() timeout.\n */\n#define ETIME 77\n/**\n * @def ETIMEDOUT\n * @brief  Connection timed out.\n */\n#define ETIMEDOUT 78\n/**\n * @def ETXTBSY\n * @brief  Text file busy.\n */\n#define ETXTBSY 79\n/**\n * @def EWOULDBLOCK\n * @brief  Operation would block.\n */\n#define EWOULDBLOCK ENOTSUP\n/**\n * @def EXDEV\n * @brief  Cross-device link.\n */\n#define EXDEV 81\n\n#endif /* _DPUSYSCORE_ERRNO_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/exit.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include \"defs.h\"\n#include \"stdlib.h\"\n\n#define unreachable() __builtin_unreachable()\n\nvoid\nexit(int __attribute__((unused)) status)\n{\n    __asm__ volatile(\"stop true, __sys_end\");\n    unreachable();\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/inttypes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_INTTYPES_H_\n#define _DPUSYSCORE_INTTYPES_H_\n\n/**\n * @file inttypes.h\n * @brief Extends stdint.h.\n */\n\n#include <stdint.h>\n\ntypedef struct {\n    intmax_t quot;\n    intmax_t rem;\n} imaxdiv_t;\n\nstatic inline intmax_t\nimaxabs(intmax_t x)\n{\n    return (x < 0) ? -x : x;\n}\n\nstatic inline imaxdiv_t\nimaxdiv(intmax_t numer, intmax_t denom)\n{\n    imaxdiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/* Macros for printing format specifiers.  */\n\n/* Decimal notation.  */\n#define PRId8 \"d\"\n#define PRId16 \"d\"\n#define PRId32 \"d\"\n#define PRId64 \"ld\"\n\n#define PRIdLEAST8 \"d\"\n#define PRIdLEAST16 \"d\"\n#define PRIdLEAST32 \"d\"\n#define PRIdLEAST64 \"ld\"\n\n#define PRIdFAST8 \"d\"\n#define PRIdFAST16 \"d\"\n#define PRIdFAST32 \"d\"\n#define PRIdFAST64 \"ld\"\n\n#define PRIi8 \"i\"\n#define PRIi16 \"i\"\n#define PRIi32 \"i\"\n#define PRIi64 \"li\"\n\n#define PRIiLEAST8 \"i\"\n#define PRIiLEAST16 \"i\"\n#define PRIiLEAST32 \"i\"\n#define PRIiLEAST64 \"li\"\n\n#define PRIiFAST8 \"i\"\n#define PRIiFAST16 \"i\"\n#define PRIiFAST32 \"i\"\n#define PRIiFAST64 \"li\"\n\n/* Octal notation.  */\n#define PRIo8 \"o\"\n#define PRIo16 \"o\"\n#define PRIo32 \"o\"\n#define PRIo64 \"lo\"\n\n#define PRIoLEAST8 \"o\"\n#define PRIoLEAST16 \"o\"\n#define PRIoLEAST32 \"o\"\n#define PRIoLEAST64 \"lo\"\n\n#define PRIoFAST8 \"o\"\n#define PRIoFAST16 \"o\"\n#define PRIoFAST32 \"o\"\n#define PRIoFAST64 \"lo\"\n\n/* Unsigned integers.  */\n#define PRIu8 \"u\"\n#define PRIu16 \"u\"\n#define PRIu32 \"u\"\n#define PRIu64 \"lu\"\n\n#define PRIuLEAST8 \"u\"\n#define PRIuLEAST16 \"u\"\n#define PRIuLEAST32 \"u\"\n#define PRIuLEAST64 \"lu\"\n\n#define PRIuFAST8 \"u\"\n#define PRIuFAST16 \"u\"\n#define PRIuFAST32 \"u\"\n#define PRIuFAST64 \"lu\"\n\n/* lowercase hexadecimal notation.  */\n#define PRIx8 \"x\"\n#define PRIx16 \"x\"\n#define PRIx32 \"x\"\n#define PRIx64 \"lx\"\n\n#define PRIxLEAST8 \"x\"\n#define PRIxLEAST16 \"x\"\n#define PRIxLEAST32 \"x\"\n#define PRIxLEAST64 \"lx\"\n\n#define PRIxFAST8 \"x\"\n#define PRIxFAST16 \"x\"\n#define PRIxFAST32 \"x\"\n#define PRIxFAST64 \"lx\"\n\n/* UPPERCASE hexadecimal notation.  */\n#define PRIX8 \"X\"\n#define PRIX16 \"X\"\n#define PRIX32 \"X\"\n#define PRIX64 \"lX\"\n\n#define PRIXLEAST8 \"X\"\n#define PRIXLEAST16 \"X\"\n#define PRIXLEAST32 \"X\"\n#define PRIXLEAST64 \"lX\"\n\n#define PRIXFAST8 \"X\"\n#define PRIXFAST16 \"X\"\n#define PRIXFAST32 \"X\"\n#define PRIXFAST64 \"lX\"\n\n/* Macros for printing `intmax_t' and `uintmax_t'.  */\n#define PRIdMAX \"ld\"\n#define PRIiMAX \"li\"\n#define PRIoMAX \"lo\"\n#define PRIuMAX \"lu\"\n#define PRIxMAX \"lx\"\n#define PRIXMAX \"lX\"\n\n/* Macros for printing `intptr_t' and `uintptr_t'.  */\n#define PRIdPTR \"d\"\n#define PRIiPTR \"i\"\n#define PRIoPTR \"o\"\n#define PRIuPTR \"u\"\n#define PRIxPTR \"x\"\n#define PRIXPTR \"X\"\n\n#endif /* _DPUSYSCORE_INTTYPES_H_ */"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/iso646.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_ISO646_H_\n#define _DPUSYSCORE_ISO646_H_\n\n/**\n * @file iso646.h\n * @brief Alternative spellings for operators not supported by the ISO646 standard character set.\n */\n\n/**\n * @def and\n * @brief Logical AND.\n */\n#define and &&\n/**\n * @def and_eq\n * @brief Bitwise AND accumulation.\n */\n#define and_eq &=\n/**\n * @def bitand\n * @brief Bitwise AND.\n */\n#define bitand &\n/**\n * @def bitor\n * @brief Bitwise OR.\n */\n#define bitor |\n/**\n * @def compl\n * @brief Bitwise NOT.\n */\n#define compl ~\n/**\n * @def not\n * @brief Logical NOT.\n */\n#define not !\n/**\n * @def not_eq\n * @brief Difference.\n */\n#define not_eq !=\n/**\n * @def or\n * @brief Logical OR.\n */\n#define or ||\n/**\n * @def or_eq\n * @brief Bitwise OR accumulation.\n */\n#define or_eq |=\n/**\n * @def xor\n * @brief Bitwise XOR.\n */\n#define xor ^\n/**\n * @def xor_eq\n * @brief Bitwise XOR accumulation.\n */\n#define xor_eq ^=\n\n#endif /* _DPUSYSCORE_ISO646_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/limits.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_LIMITS_H_\n#define _DPUSYSCORE_LIMITS_H_\n\n#define SCHAR_MAX (0x0000007f)\n#define SHRT_MAX (0x00007fff)\n#define INT_MAX (0x7fffffff)\n#define LONG_MAX (0x7fffffffffffffffl)\n#define LLONG_MAX (0x7fffffffffffffffl)\n\n#define SCHAR_MIN (-SCHAR_MAX - 1)\n#define SHRT_MIN (-SHRT_MAX - 1)\n#define INT_MIN (-INT_MAX - 1)\n#define LONG_MIN (-LONG_MAX - 1)\n#define LLONG_MIN (-LLONG_MAX - 1)\n\n#define UCHAR_MAX (SCHAR_MAX * 2 + 1)\n#define USHRT_MAX (SHRT_MAX * 2 + 1)\n#define UINT_MAX (INT_MAX * 2U + 1U)\n#define ULONG_MAX (LONG_MAX * 2UL + 1UL)\n#define ULLONG_MAX (LLONG_MAX * 2UL + 1UL)\n\n#ifdef __CHAR_UNSIGNED__ /* -funsigned-char */\n#define CHAR_MIN 0\n#define CHAR_MAX UCHAR_MAX\n#else\n#define CHAR_MIN SCHAR_MIN\n#define CHAR_MAX SCHAR_MAX\n#endif\n\n/* The maximum number of bytes in a multi-byte character.  */\n#define MB_LEN_MAX 16\n\n/* Limits of integral types */\n\n/**\n * @def CHAR_BIT\n * @hideinitializer\n * @brief The number of bits in a char type.\n */\n#define CHAR_BIT (8)\n\n/**\n * @def WORD_BIT\n * @hideinitializer\n * @brief The number of bits in a word type.\n */\n#define WORD_BIT (32)\n\n/**\n * @def LONG_BIT\n * @hideinitializer\n * @brief The number of bits in a pseudo-long type.\n */\n#define LONG_BIT (32)\n\n/* Minimum of signed integral types */\n\n/**\n * @def INT8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MIN (-0x7f - 1)\n\n/**\n * @def INT16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MIN (-0x7fff - 1)\n\n/**\n * @def INT32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MIN (-0x7fffffff - 1)\n\n/**\n * @def INT64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types */\n\n/**\n * @def INT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int8_t</code>.\n */\n#define INT8_MAX (0x7f)\n/**\n * @def INT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int16_t</code>.\n */\n#define INT16_MAX (0x7fff)\n/**\n * @def INT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int32_t</code>.\n */\n#define INT32_MAX (0x7fffffff)\n/**\n * @def INT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int64_t</code>.\n */\n#define INT64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types */\n\n/**\n * @def UINT8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint8_t</code>.\n */\n#define UINT8_MAX (0xff)\n/**\n * @def UINT16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint16_t</code>.\n */\n#define UINT16_MAX (0xffff)\n/**\n * @def UINT32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint32_t</code>.\n */\n#define UINT32_MAX (0xffffffff)\n/**\n * @def UINT64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint64_t</code>.\n */\n#define UINT64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MIN (-0x7f - 1)\n/**\n * @def INT_LEAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MIN (-0x7fff - 1)\n/**\n * @def INT_LEAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_LEAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of signed integral types having a minimum size */\n\n/**\n * @def INT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least8_t</code>.\n */\n#define INT_LEAST8_MAX (0x7f)\n/**\n * @def INT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least16_t</code>.\n */\n#define INT_LEAST16_MAX (0x7fff)\n/**\n * @def INT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least32_t</code>.\n */\n#define INT_LEAST32_MAX (0x7fffffff)\n/**\n * @def INT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_least64_t</code>.\n */\n#define INT_LEAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of unsigned integral types having a minimum size */\n\n/**\n * @def UINT_LEAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least8_t</code>.\n */\n#define UINT_LEAST8_MAX (0xff)\n/**\n * @def UINT_LEAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least16_t</code>.\n */\n#define UINT_LEAST16_MAX (0xffff)\n/**\n * @def UINT_LEAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least32_t</code>.\n */\n#define UINT_LEAST32_MAX (0xffffffff)\n/**\n * @def UINT_LEAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_least64_t</code>.\n */\n#define UINT_LEAST64_MAX (0xffffffffffffffffUL)\n\n/* Minimum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MIN (-0x7f - 1)\n/**\n * @def INT_FAST16_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST32_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MIN (-0x7fffffff - 1)\n/**\n * @def INT_FAST64_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MIN (-0x7fffffffffffffffL - 1L)\n\n/* Maximum of fast signed integral types having a minimum size */\n\n/**\n * @def INT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast8_t</code>.\n */\n#define INT_FAST8_MAX (0x7f)\n/**\n * @def INT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast16_t</code>.\n */\n#define INT_FAST16_MAX (0x7fffffff)\n/**\n * @def INT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast32_t</code>.\n */\n#define INT_FAST32_MAX (0x7fffffff)\n/**\n * @def INT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>int_fast64_t</code>.\n */\n#define INT_FAST64_MAX (0x7fffffffffffffffL)\n\n/* Maximum of fast unsigned integral types having a minimum size */\n\n/**\n * @def UINT_FAST8_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast8_t</code>.\n */\n#define UINT_FAST8_MAX (0xff)\n/**\n * @def UINT_FAST16_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast16_t</code>.\n */\n#define UINT_FAST16_MAX (0xffffffffU)\n/**\n * @def UINT_FAST32_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast32_t</code>.\n */\n#define UINT_FAST32_MAX (0xffffffffU)\n/**\n * @def UINT_FAST64_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uint_fast64_t</code>.\n */\n#define UINT_FAST64_MAX (0xffffffffffffffffUL)\n\n/* Limits for integral types holding void* pointers */\n\n/**\n * @def INTPTR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MIN (-0x7fffffff - 1)\n/**\n * @def INTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intptr_t</code>.\n */\n#define INTPTR_MAX (0x7fffffff)\n/**\n * @def UINTPTR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintptr_t</code>.\n */\n#define UINTPTR_MAX (0xffffffffU)\n\n/* Limits of greatest-width integer types */\n\n/**\n * @def INTMAX_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MIN (-0x7fffffffffffffffLL - 1)\n/**\n * @def INTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>intmax_t</code>.\n */\n#define INTMAX_MAX (0x7fffffffffffffffLL)\n/**\n * @def UINTMAX_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>uintmax_t</code>.\n */\n#define UINTMAX_MAX (0xffffffffffffffffULL)\n\n/* Limits of others integer types */\n\n/**\n * @def PTRDIFF_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MIN (-0x7fffffff - 1)\n/**\n * @def PTRDIFF_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>ptrdiff_t</code>.\n * @see ptrdiff_t\n */\n#define PTRDIFF_MAX (0x7fffffff)\n\n/**\n * @def SIZE_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>size_t</code>.\n * @see size_t\n */\n#define SIZE_MAX (0xffffffffU)\n\n/**\n * @def WCHAR_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MIN (-0x7fffffff - 1)\n/**\n * @def WCHAR_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wchar_t</code>.\n * @see wchar_t\n */\n#define WCHAR_MAX (0x7fffffff)\n\n/**\n * @def WINT_MIN\n * @hideinitializer\n * @brief The minimum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MIN (0u)\n/**\n * @def WINT_MAX\n * @hideinitializer\n * @brief The maximum value for a value of type <code>wint_t</code>.\n */\n#define WINT_MAX (0xffffffffu)\n\n/* Macros for integer constant expressions */\n\n/* Signed */\n\n/**\n * @def INT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least8_t</code>\n */\n#define INT8_C(value) value\n/**\n * @def INT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least16_t</code>\n */\n#define INT16_C(value) value\n/**\n * @def INT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least32_t</code>\n */\n#define INT32_C(value) value\n/**\n * @def INT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>int_least64_t</code>\n */\n#define INT64_C(value) value##LL\n\n/* Unsigned */\n\n/**\n * @def UINT8_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least8_t</code>\n */\n#define UINT8_C(value) value##U\n/**\n * @def UINT16_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least16_t</code>\n */\n#define UINT16_C(value) value##U\n/**\n * @def UINT32_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least32_t</code>\n */\n#define UINT32_C(value) value##U\n/**\n * @def UINT64_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uint_least64_t</code>\n */\n#define UINT64_C(value) value##ULL\n\n/* Maximum types */\n\n/**\n * @def INTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>intmax_t</code>\n */\n#define INTMAX_C(value) value##LL\n/**\n * @def UINTMAX_C\n * @hideinitializer\n * @brief Expands the value to an expression corresponding to the type <code>uintmax_t</code>\n */\n#define UINTMAX_C(value) value##ULL\n\n#endif /* _DPUSYSCORE_LIMITS_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nvoid *\nmemchr(const void *area, int character, size_t size)\n{\n    const char *ptr = (const char *)area;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        if (ptr[each_byte] == character) {\n            return (void *)(ptr + each_byte);\n        }\n    }\n\n    return NULL;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nint\nmemcmp(const void *area1, const void *area2, size_t size)\n{\n    const unsigned char *ptr1 = (const unsigned char *)area1;\n    const unsigned char *ptr2 = (const unsigned char *)area2;\n\n    for (size_t each_byte = 0; each_byte < size; ++each_byte) {\n        int diff = ptr1[each_byte] - ptr2[each_byte];\n        if (diff != 0) {\n            return diff;\n        }\n    }\n\n    return 0;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\n__attribute__((used)) void *\n__memcpy_wram_4align(void *dest, const void *src, size_t len)\n{\n    uint32_t *dw = (uint32_t *)dest;\n    uint32_t *sw = (uint32_t *)src;\n\n    for (uint32_t i = 0; i < (len / sizeof(uint32_t)); ++i) {\n        dw[i] = sw[i];\n    }\n    return dest;\n}\n\nvoid *\nmemcpy(void *dest, const void *src, size_t len)\n{\n    uint8_t *d = (uint8_t *)dest;\n    const uint8_t *s = (const uint8_t *)src;\n    uint32_t *dw;\n    const uint32_t *sw;\n    uint8_t *head;\n    uint8_t *const tail = (uint8_t *)dest + len;\n    /* Set 'body' to the last word boundary */\n    uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);\n\n    if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n        /* Misaligned. no body, no tail. */\n        head = tail;\n    } else {\n        /* Aligned */\n        if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))\n            /* len is shorter than the first word boundary */\n            head = tail;\n        else\n            /* Set 'head' to the first word boundary */\n            head = (uint8_t *)(((uintptr_t)d + 3) & ~3);\n    }\n\n    /* Copy head */\n    uint32_t head_len = head - d;\n    if (head_len != 0) {\n        for (uint32_t i = 0; i < head_len; ++i)\n            d[i] = s[i];\n    }\n\n    /* Copy body */\n    dw = (uint32_t *)(d + head_len);\n    sw = (uint32_t *)(s + head_len);\n\n    uint32_t body_len = (body < dw) ? 0 : body - dw;\n    if (body_len != 0) {\n        __memcpy_wram_4align(dw, sw, body_len * sizeof(uint32_t));\n    }\n\n    /* Copy tail */\n    d = (uint8_t *)(dw + body_len);\n    s = (const uint8_t *)(sw + body_len);\n    uint32_t tail_len = tail - d;\n    if (tail_len != 0) {\n        for (uint32_t i = 0; i < tail_len; ++i)\n            d[i] = s[i];\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mw(__mram_ptr void *dest, const void *src, size_t len)\n{\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n\n    if (destOff != 0) {\n        size_t part = MIN(remaining, MRAM_CACHE_SIZE - destOff);\n        mram_read(dest, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache + destOff, src, part);\n        mram_write(destCache, dest, MRAM_CACHE_SIZE);\n        remaining -= part;\n        idx += part;\n    }\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_write(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            memcpy(destCache, src + idx, MRAM_CACHE_SIZE);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n        memcpy(destCache, src + idx, remaining);\n        mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) void *\n__memcpy_wm(void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    uint32_t idx = 0;\n    size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n\n    mram_read(src, srcCache, MRAM_CACHE_SIZE);\n    memcpy(dest, srcCache + srcOff, part);\n    remaining -= part;\n    idx += part;\n\n    if (srcOff == destOff) {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    } else {\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(dest + idx, srcCache, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n    }\n\n    if (remaining != 0) {\n        mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n        memcpy(dest + idx, srcCache, remaining);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memcpy_mm(__mram_ptr void *dest, const __mram_ptr void *src, size_t len)\n{\n    uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n    void *srcCache = (void *)srcCache64;\n    void *destCache = (void *)destCache64;\n\n    uint32_t srcOff = ((uintptr_t)src) & DMA_OFF_MASK;\n    uint32_t destOff = ((uintptr_t)dest) & DMA_OFF_MASK;\n    size_t remaining = len;\n\n    if (srcOff == destOff) {\n        uint32_t idx = 0;\n\n        if (destOff != 0) {\n            size_t part = MIN(remaining, MRAM_CACHE_SIZE - srcOff);\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, part);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            remaining -= part;\n            idx += part;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            mram_write(srcCache, dest + idx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            idx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + idx, destCache, MRAM_CACHE_SIZE);\n            mram_read(src + idx, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache, srcCache, remaining);\n            mram_write(destCache, dest + idx, MRAM_CACHE_SIZE);\n        }\n    } else {\n        uint32_t srcIdx = 0;\n        uint32_t destIdx = 0;\n        size_t initLen = MIN(remaining, MRAM_CACHE_SIZE - MIN(destOff, srcOff));\n\n        if (initLen == remaining) {\n            mram_read(dest, destCache, MRAM_CACHE_SIZE);\n            mram_read(src, srcCache, MRAM_CACHE_SIZE);\n            memcpy(destCache + destOff, srcCache + srcOff, remaining);\n            mram_write(destCache, dest, MRAM_CACHE_SIZE);\n            return dest;\n        }\n\n        mram_read(src, srcCache, MRAM_CACHE_SIZE);\n        srcIdx += MRAM_CACHE_SIZE;\n\n        if (destOff != 0) {\n            mram_read(dest, destCache, DMA_ALIGNED(destOff));\n\n            if (destOff > srcOff) {\n                size_t part = MRAM_CACHE_SIZE - destOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n\n                srcOff += part;\n            } else {\n                size_t part = MRAM_CACHE_SIZE - srcOff;\n                memcpy(destCache + destOff, srcCache + srcOff, part);\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx += MRAM_CACHE_SIZE;\n\n                size_t part2 = srcOff - destOff;\n                memcpy(destCache + destOff + part, srcCache, part2);\n\n                srcOff = part2;\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            destIdx += MRAM_CACHE_SIZE;\n            remaining -= MRAM_CACHE_SIZE - destOff;\n        }\n\n        while (remaining >= MRAM_CACHE_SIZE) {\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n            mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx += MRAM_CACHE_SIZE;\n\n            size_t part2 = srcOff;\n            memcpy(destCache + part, srcCache, part2);\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n            remaining -= MRAM_CACHE_SIZE;\n            destIdx += MRAM_CACHE_SIZE;\n        }\n\n        if (remaining != 0) {\n            mram_read(dest + destIdx, destCache, MRAM_CACHE_SIZE);\n\n            size_t part = MRAM_CACHE_SIZE - srcOff;\n            memcpy(destCache, srcCache + srcOff, part);\n\n            if (remaining > part) {\n                size_t part2 = remaining - part;\n                mram_read(src + srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + part, srcCache, part2);\n            }\n\n            mram_write(destCache, dest + destIdx, MRAM_CACHE_SIZE);\n        }\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memmove.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <string.h>\n#include <stdint.h>\n\nvoid *\nmemmove(void *dest, const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return memcpy(dest, src, len);\n    } else {\n        /* Need to copy from tail because there is overlap. */\n        char *d = (char *)dest + len;\n        const char *s = (const char *)src + len;\n        uint32_t *dw;\n        const uint32_t *sw;\n        char *head;\n        char *const tail = (char *)dest;\n        /* Set 'body' to the last word boundary */\n        uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3);\n\n        if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {\n            /* Misaligned. no body, no tail. */\n            head = tail;\n        } else {\n            /* Aligned */\n            if ((uintptr_t)tail > ((uintptr_t)d & ~3))\n                /* Shorter than the first word boundary */\n                head = tail;\n            else\n                /* Set 'head' to the first word boundary */\n                head = (char *)((uintptr_t)d & ~3);\n        }\n\n        /* Copy head */\n        uint32_t head_len = d - head;\n        for (int32_t i = head_len - 1; i >= 0; --i)\n            d[i - head_len] = s[i - head_len];\n\n        /* Copy body */\n        dw = (uint32_t *)(d - head_len);\n        sw = (uint32_t *)(s - head_len);\n\n        uint32_t body_len = (dw < body) ? 0 : dw - body;\n        for (int32_t i = body_len - 1; i >= 0; --i)\n            dw[i - body_len] = sw[i - body_len];\n\n        /* Copy tail */\n        d = (char *)(dw - body_len);\n        s = (const char *)(sw - body_len);\n\n        uint32_t tail_len = d - tail;\n        for (int32_t i = tail_len - 1; i >= 0; --i)\n            d[i - tail_len] = s[i - tail_len];\n\n        return dest;\n    }\n}\n\n__mram_ptr void *\n__memmove_mm(__mram_ptr void *dest, __mram_ptr const void *src, size_t len)\n{\n    if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) {\n        /* Start of destination doesn't overlap source, so just use\n         * memcpy(). */\n        return (__mram_ptr void *)memcpy(dest, src, len);\n    } else {\n        uint64_t srcCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        uint64_t destCache64[MRAM_CACHE_SIZE / sizeof(uint64_t)];\n        void *srcCache = (void *)srcCache64;\n        void *destCache = (void *)destCache64;\n\n        __mram_ptr const void *srcIdx = src + len;\n        __mram_ptr void *dstIdx = dest + len;\n        uint32_t remaining = len;\n\n        uint32_t srcOff = ((uintptr_t)srcIdx) & DMA_OFF_MASK;\n        uint32_t dstOff = ((uintptr_t)dstIdx) & DMA_OFF_MASK;\n\n        if (srcOff == dstOff) {\n            size_t part = MIN(remaining, srcOff);\n            uint32_t off = srcOff - part;\n\n            if (dstOff != 0) {\n                srcIdx -= srcOff;\n                dstIdx -= dstOff;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, part);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= part;\n            }\n\n            srcIdx -= MRAM_CACHE_SIZE;\n            dstIdx -= MRAM_CACHE_SIZE;\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                mram_write(srcCache, dstIdx, MRAM_CACHE_SIZE);\n                remaining -= MRAM_CACHE_SIZE;\n                srcIdx -= MRAM_CACHE_SIZE;\n                dstIdx -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                uint32_t off = MRAM_CACHE_SIZE - remaining;\n\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + off, srcCache + off, remaining);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        } else {\n            size_t initLen = MIN(remaining, MIN(dstOff, srcOff));\n\n            if (initLen == remaining) {\n                mram_read(dest, destCache, MRAM_CACHE_SIZE);\n                mram_read(src, srcCache, MRAM_CACHE_SIZE);\n                memcpy(destCache + dstOff - remaining, srcCache + srcOff - remaining, remaining);\n                mram_write(destCache, dest, MRAM_CACHE_SIZE);\n                return dest;\n            }\n\n            mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n            srcIdx -= MRAM_CACHE_SIZE;\n\n            if (dstOff != 0) {\n                size_t part = DMA_ALIGNED(dstOff);\n                mram_read(dstIdx, destCache + MRAM_CACHE_SIZE - part, part);\n\n                if (srcOff > dstOff) {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n                    memcpy(destCache, srcCache + srcOff - part, part);\n                    srcOff -= part;\n                } else {\n                    part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                    memcpy(destCache + dstOff - part, srcCache, part);\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    srcIdx -= MRAM_CACHE_SIZE;\n\n                    size_t part2 = dstOff - part;\n                    memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n\n                    srcOff = MRAM_CACHE_SIZE - part2;\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE - (DMA_ALIGNMENT - dstOff);\n            }\n\n            while (remaining >= MRAM_CACHE_SIZE) {\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n                mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                srcIdx -= MRAM_CACHE_SIZE;\n\n                size_t part2 = MRAM_CACHE_SIZE - part;\n                memcpy(destCache, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n                dstIdx -= MRAM_CACHE_SIZE;\n                remaining -= MRAM_CACHE_SIZE;\n            }\n\n            if (remaining != 0) {\n                mram_read(dstIdx, destCache, MRAM_CACHE_SIZE);\n\n                size_t part = MRAM_CACHE_SIZE - (DMA_ALIGNMENT - srcOff);\n                memcpy(destCache + MRAM_CACHE_SIZE - part, srcCache, part);\n\n                if (remaining > part) {\n                    size_t part2 = remaining - part;\n                    mram_read(srcIdx, srcCache, MRAM_CACHE_SIZE);\n                    memcpy(destCache + MRAM_CACHE_SIZE - remaining, srcCache + MRAM_CACHE_SIZE - part2, part2);\n                }\n\n                mram_write(destCache, dstIdx, MRAM_CACHE_SIZE);\n            }\n        }\n\n        return dest;\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memmram_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_MEMMRAM_UTILS_H_\n#define _DPUSYSCORE_MEMMRAM_UTILS_H_\n\n#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))\n#define ALIGN(x, a) ALIGN_MASK((x), (a)-1)\n#define DMA_ALIGNMENT 8\n#define DMA_OFF_MASK (DMA_ALIGNMENT - 1)\n#define DMA_ALIGNED(x) ALIGN(x, DMA_ALIGNMENT)\n\n#define MIN(a, b) ((a) < (b) ? (a) : (b))\n\n#define MRAM_CACHE_SIZE 8\n\n#endif /* _DPUSYSCORE_MEMMRAM_UTILS_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/memset.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <memmram_utils.h>\n#include <mram.h>\n#include <stddef.h>\n#include <stdint.h>\n\nstatic void *\n__memset_wram_1align(void *dest, int c, size_t len)\n{\n    uint8_t *dest8 = (uint8_t *)(dest);\n    for (uint32_t i = 0; i < (len); ++i) {\n        dest8[i] = (c);\n    }\n    return dest;\n}\n\ntypedef uint32_t memset_wram_t;\n/* Requisite:\n *  - dest: align on 4 bytes\n *  - len: mutiple of 4 bytes\n */\nvoid *__attribute__((used)) __memset_wram_4align(void *dest, int c, size_t len)\n{\n    uint32_t cccc;\n    memset_wram_t *dest32 = (memset_wram_t *)dest;\n\n    c &= 0xff; /* Clear upper bits before ORing below */\n    cccc = c | (c << 8) | (c << 16) | (c << 24);\n\n    for (uint32_t i = 0; i < len / sizeof(memset_wram_t); ++i) {\n        dest32[i] = cccc;\n    }\n\n    return dest;\n}\n\nvoid *\nmemset(void *dest, int c, size_t len)\n{\n    const uint32_t align = sizeof(memset_wram_t);\n    const uint32_t align_off_mask = (align - 1);\n    uint32_t align_offset = ((uintptr_t)dest) & align_off_mask;\n    uint8_t *d = (uint8_t *)dest;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = align - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        __memset_wram_1align(d, c, head_len);\n\n        len -= head_len;\n        d += head_len;\n    }\n\n    /* memset body */\n    if (len >= align) {\n        size_t body_len = len & (~align_off_mask);\n\n        __memset_wram_4align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        __memset_wram_1align(d, c, len);\n    }\n\n    return dest;\n}\n\n#define MEMSET_MRAM_CACHE_SIZE (8)\n/* Requisite:\n *  - dest: align on 8 bytes\n *  - len: mutiple of 8 bytes\n */\n__attribute__((used)) __mram_ptr void *\n__memset_mram_8align(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n\n    __memset_wram_4align(cache, c, MEMSET_MRAM_CACHE_SIZE);\n\n    for (uint32_t idx = 0; idx < len; idx += MEMSET_MRAM_CACHE_SIZE) {\n        mram_write(cache, dest + idx, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n\n__attribute__((used)) __mram_ptr void *\n__memset_mram(__mram_ptr void *dest, int c, size_t len)\n{\n    __dma_aligned uint8_t cache64[MEMSET_MRAM_CACHE_SIZE];\n    void *cache = (void *)cache64;\n    __mram_ptr uint8_t *d = (__mram_ptr uint8_t *)((uintptr_t)dest & (~DMA_OFF_MASK));\n    uint32_t align_offset = ((uintptr_t)dest) & DMA_OFF_MASK;\n\n    /* memset head */\n    if (align_offset != 0) {\n        size_t head_len = MEMSET_MRAM_CACHE_SIZE - align_offset;\n        if (head_len > len) {\n            head_len = len;\n        }\n\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache + align_offset, c, head_len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n\n        len -= head_len;\n        d += MEMSET_MRAM_CACHE_SIZE;\n    }\n\n    /* memset body */\n    if (len >= MRAM_CACHE_SIZE) {\n        size_t body_len = len & (~(MEMSET_MRAM_CACHE_SIZE - 1));\n\n        __memset_mram_8align(d, c, body_len);\n\n        len -= body_len;\n        d += body_len;\n    }\n\n    /* memset tail */\n    if (len > 0) {\n        mram_read(d, cache, MEMSET_MRAM_CACHE_SIZE);\n        __memset_wram_1align(cache, c, len);\n        mram_write(cache, d, MEMSET_MRAM_CACHE_SIZE);\n    }\n\n    return dest;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdalign.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDALIGN_H_\n#define _DPUSYSCORE_STDALIGN_H_\n\n/**\n * @file stdalign.h\n * @brief Defines align macros.\n */\n\n/**\n * @def alignas\n * @brief _Alignas specifier.\n */\n#define alignas _Alignas\n\n/**\n * @def alignof\n * @brief _Alignof operator.\n */\n#define alignof _Alignof\n\n/**\n * @def __alignas_is_defined\n * @brief Whether the alignas macro is defined.\n */\n#define __alignas_is_defined 1\n\n/**\n * @def __alignof_is_defined\n * @brief Whether the alignof macro is defined.\n */\n#define __alignof_is_defined 1\n\n#endif /* _DPUSYSCORE_STDALIGN_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdarg.h",
    "content": "/*===---- stdarg.h - Variable argument handling ----------------------------===\n *\n * Copyright (c) 2008 Eli Friedman\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __STDARG_H\n#define __STDARG_H\n\n#ifndef _VA_LIST\ntypedef __builtin_va_list va_list;\n#define _VA_LIST\n#endif\n#define va_start(ap, param) __builtin_va_start(ap, param)\n#define va_end(ap) __builtin_va_end(ap)\n#define va_arg(ap, type) __builtin_va_arg(ap, type)\n\n/* GCC always defines __va_copy, but does not define va_copy unless in c99 mode\n * or -ansi is not specified, since it was not part of C90.\n */\n#define __va_copy(d, s) __builtin_va_copy(d, s)\n\n#if __STDC_VERSION__ >= 199901L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__)\n#define va_copy(dest, src) __builtin_va_copy(dest, src)\n#endif\n\n#ifndef __GNUC_VA_LIST\n#define __GNUC_VA_LIST 1\ntypedef __builtin_va_list __gnuc_va_list;\n#endif\n\n#endif /* __STDARG_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdbool.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDBOOL_H_\n#define _DPUSYSCORE_STDBOOL_H_\n\n/**\n * @file stdbool.h\n * @brief Defines the boolean type.\n */\n\n/**\n * @def __bool_true_false_are_defined\n * @brief Whether the boolean type and values are defined.\n */\n#define __bool_true_false_are_defined 1\n\n/**\n * @def bool\n * @brief The boolean type.\n */\n#define bool _Bool\n\n/**\n * @def true\n * @brief The <code>true</code> constant, represented by <code>1</code>\n */\n#define true 1\n/**\n * @def false\n * @brief The <code>false</code> constant, represented by <code>0</code>\n */\n#define false 0\n\n#endif /* _DPUSYSCORE_STDBOOL_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stddef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDDEF_H_\n#define _DPUSYSCORE_STDDEF_H_\n\n/**\n * @file stddef.h\n * @brief Defines some standard types.\n */\n\n/**\n * @brief The type for the result of subtracting two pointers.\n */\ntypedef int ptrdiff_t;\n\n/**\n * @brief The type for the result of the <code>sizeof</code> operator.\n *\n * @internal No memory or object in the DPU can be more than megabytes of data.\n *           As a consequence, we can restrict the sizes to 32 bits, which is\n *           already a lot.\n */\ntypedef unsigned int size_t;\n\n/**\n * @brief Value whose alignment requirement is at least as strict (as large) as that of every scalar type.\n */\ntypedef unsigned long int max_align_t;\n\n/**\n * @brief The type for wide-character codes.\n */\ntypedef unsigned int wchar_t;\n\n/**\n * @def NULL\n * @brief The null pointer constant.\n */\n#define NULL ((void *)0)\n\n/**\n * @def offsetof\n * @hideinitializer\n * @brief Offset in bytes to the structure member, from the beginning of its structure.\n *\n * @param st the structure\n * @param m the member name\n *\n * @internal Raw version of offsetof, should be enough in our context, with all the underlying risks.\n */\n#define offsetof(st, m) ((size_t)(&((st *)0)->m))\n\n#endif /* _DPUSYSCORE_STDDEF_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdint.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDINT_H_\n#define _DPUSYSCORE_STDINT_H_\n\n/**\n * @file stdint.h\n * @brief Provides abstraction over machine types.\n */\n\n/* Exact integer types */\n\n/* Signed */\n\n/**\n * @brief A signed 8-bit value.\n */\ntypedef signed char int8_t;\n/**\n * @brief A signed 16-bit value.\n */\ntypedef short int int16_t;\n/**\n * @brief A signed 32-bit value.\n */\ntypedef int int32_t;\n/**\n * @brief A signed 64-bit value.\n */\ntypedef long long int int64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned 8-bit value.\n */\ntypedef unsigned char uint8_t;\n/**\n * @brief An unsigned 16-bit value.\n */\ntypedef unsigned short int uint16_t;\n/**\n * @brief An unsigned 32-bit value.\n */\ntypedef unsigned int uint32_t;\n\n/**\n * @brief An unsigned 64-bit value.\n */\ntypedef unsigned long int uint64_t;\n\n/* Small types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits.\n */\ntypedef signed char int_least8_t;\n/**\n * @brief A signed value on at least 16 bits.\n */\ntypedef short int int_least16_t;\n/**\n * @brief A signed value on at least 32 bits.\n */\ntypedef int int_least32_t;\n/**\n * @brief A signed value on at least 64 bits.\n */\ntypedef long int int_least64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits.\n */\ntypedef unsigned char uint_least8_t;\n/**\n * @brief An unsigned value on at least 16 bits.\n */\ntypedef unsigned short int uint_least16_t;\n/**\n * @brief An unsigned value on at least 32 bits.\n */\ntypedef unsigned int uint_least32_t;\n/**\n * @brief An unsigned value on at least 64 bits.\n */\ntypedef unsigned long int uint_least64_t;\n\n/* Fast types */\n\n/* Signed */\n\n/**\n * @brief A signed value on at least 8 bits, optimized for that length.\n */\ntypedef signed char int_fast8_t;\n/**\n * @brief A signed value on at least 16 bits, optimized for that length.\n */\ntypedef int int_fast16_t;\n/**\n * @brief A signed value on at least 32 bits, optimized for that length.\n */\ntypedef int int_fast32_t;\n/**\n * @brief A signed value on at least 64 bits, optimized for that length.\n */\ntypedef long int int_fast64_t;\n\n/* Unsigned */\n\n/**\n * @brief An unsigned value on at least 8 bits, optimized for that length.\n */\ntypedef unsigned char uint_fast8_t;\n/**\n * @brief An unsigned value on at least 16 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast16_t;\n/**\n * @brief An unsigned value on at least 32 bits, optimized for that length.\n */\ntypedef unsigned int uint_fast32_t;\n/**\n * @brief An unsigned value on at least 64 bits, optimized for that length.\n */\ntypedef unsigned long int uint_fast64_t;\n\n/* Types for void* pointers */\n\n/**\n * @brief A signed value which can contain a pointer value.\n */\ntypedef int intptr_t;\n/**\n * @brief An unsigned value which can contain a pointer value.\n */\ntypedef unsigned int uintptr_t;\n\n/* Greatest-width integer types */\n\n/**\n * @brief A signed value which can contain all signed values.\n */\ntypedef long long int intmax_t;\n/**\n * @brief An unsigned value which can contain all unsigned values.\n */\ntypedef unsigned long long int uintmax_t;\n\n#include <limits.h>\n\n#endif /* _DPUSYSCORE_STDINT_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdio.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdarg.h>\n#include <string.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n#include <mram.h>\n#include <dpuruntime.h>\n\n#define DEFAULT_STDOUT_BUFFER_SIZE (1 << 20)\n\nunsigned char __weak __mram_noinit __stdout_buffer[DEFAULT_STDOUT_BUFFER_SIZE];\nunsigned int __weak __stdout_buffer_size = DEFAULT_STDOUT_BUFFER_SIZE;\n\n/* __lower_data: needed to make sure that the structure address will be less that a signed12\n *               (sd endian:e ra off:s12 imm:s16 used in bootstrap).\n *\n * __dma_aligned: needed to make sure that the structure address will be aligned on 8 bytes (for sd in bootstrap as well).\n *\n * This structure is initialize at zero in the bootsrap\n */\n__lower_data(__STR(__STDOUT_BUFFER_STATE)) __dma_aligned struct {\n    uint32_t wp;\n    uint32_t has_wrapped;\n} __STDOUT_BUFFER_STATE;\n\nstatic uint32_t __stdout_buffer_write_pointer_initial;\nstatic uint32_t __stdout_nr_of_wrapping;\n\n#define STDOUT_CACHE_BUFFER_SIZE 8\n_Static_assert((STDOUT_CACHE_BUFFER_SIZE >= 8) && (STDOUT_CACHE_BUFFER_SIZE <= 2048) && (STDOUT_CACHE_BUFFER_SIZE % 8 == 0),\n    \"STDOUT_CACHE_BUFFER_SIZE needs to be a multiple of 8 in ]0; 2048]\");\n\nstatic char __stdout_cache_buffer[STDOUT_CACHE_BUFFER_SIZE] __dma_aligned;\nstatic unsigned int __stdout_cache_write_index;\n\nATOMIC_BIT_INIT(__stdout_buffer_lock);\n\n__attribute__((noinline)) static void\n__transfer_cache_to_mram()\n{\n    __mram_ptr void *offset_in_mram = (__mram_ptr void *)(__STDOUT_BUFFER_STATE.wp + (uintptr_t)__stdout_buffer);\n\n    __STDOUT_BUFFER_STATE.wp += STDOUT_CACHE_BUFFER_SIZE;\n    if (__STDOUT_BUFFER_STATE.wp >= __stdout_buffer_size) {\n        __STDOUT_BUFFER_STATE.wp = 0;\n        __STDOUT_BUFFER_STATE.has_wrapped = true;\n        __stdout_nr_of_wrapping++;\n    }\n\n    mram_write(__stdout_cache_buffer, offset_in_mram, STDOUT_CACHE_BUFFER_SIZE);\n}\n\n// Generic template that will be used everywhere: cache a byte and flush to MRAM\n// when the cache is full.\n__attribute__((noinline)) static void\n__write_byte_and_flush_if_needed(uint8_t byte)\n{\n    __stdout_cache_buffer[__stdout_cache_write_index++] = byte;\n    if (__stdout_cache_write_index == STDOUT_CACHE_BUFFER_SIZE) {\n        __transfer_cache_to_mram();\n        __stdout_cache_write_index = 0;\n    }\n}\n\n__attribute__((noinline)) static void\n__finalized_print_sequence()\n{\n    memset(__stdout_cache_buffer + __stdout_cache_write_index, 0, STDOUT_CACHE_BUFFER_SIZE - __stdout_cache_write_index);\n    __transfer_cache_to_mram();\n\n    if (__stdout_nr_of_wrapping > 1\n        || (__stdout_nr_of_wrapping == 1 && __STDOUT_BUFFER_STATE.wp > __stdout_buffer_write_pointer_initial))\n        __asm__(\"fault \" __STR(__FAULT_PRINTF_OVERFLOW__)); // need to throw fault because we will not be able to print the buffer\n}\n\n__attribute__((noinline)) static void\n__open_print_sequence()\n{\n    ATOMIC_BIT_ACQUIRE(__stdout_buffer_lock);\n    __stdout_cache_write_index = 0;\n    __stdout_nr_of_wrapping = 0;\n    __stdout_buffer_write_pointer_initial = __STDOUT_BUFFER_STATE.wp;\n}\n\n/* Nothing else that the release instruction should be in this function in order to make sure that the print routine in complete\n * at this point*/\n__attribute__((noinline)) static void\n__close_print_sequence()\n{\n    ATOMIC_BIT_RELEASE(__stdout_buffer_lock);\n}\n\nvoid\nprintf(const char *restrict format, ...)\n{\n    bool insert_string_arg = true;\n    bool insert_string_arg_end_character = false;\n    char *current_format_char_ptr = (char *)format;\n\n    __open_print_sequence();\n\n    va_list args;\n    va_start(args, format);\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_format_process;\n\n            __write_byte_and_flush_if_needed('%');\n\n            while (*current_format_char_ptr != '\\0') {\n                if (*current_format_char_ptr == 'l') {\n                    __write_byte_and_flush_if_needed(*current_format_char_ptr);\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if ((*current_format_char_ptr == 'L') || (*current_format_char_ptr == 'z')) {\n                    ++current_format_char_ptr;\n                    continue;\n                }\n                if (*current_format_char_ptr == 'i') {\n                    __write_byte_and_flush_if_needed('d');\n                    break;\n                }\n                __write_byte_and_flush_if_needed(*current_format_char_ptr);\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            insert_string_arg = true;\n\n        } else {\n        standard_character_format_process:\n            if (insert_string_arg) {\n                __write_byte_and_flush_if_needed('%');\n                __write_byte_and_flush_if_needed('s');\n                insert_string_arg = false;\n            }\n        }\n    }\n\n    __write_byte_and_flush_if_needed('\\0');\n    current_format_char_ptr = (char *)format;\n\n    for (; *current_format_char_ptr != '\\0'; ++current_format_char_ptr) {\n        if (*current_format_char_ptr == '%') {\n            ++current_format_char_ptr;\n\n            if (*current_format_char_ptr == '\\0')\n                break;\n            if (*current_format_char_ptr == '%')\n                goto standard_character_process;\n\n            if (insert_string_arg_end_character) {\n                insert_string_arg_end_character = false;\n                __write_byte_and_flush_if_needed('\\0');\n            }\n\n            bool arg_is_64_bits = false;\n\n            while (*current_format_char_ptr != '\\0') {\n                if ((*current_format_char_ptr == 'l') || (*current_format_char_ptr == 'L')) {\n                    arg_is_64_bits = true;\n                    current_format_char_ptr++;\n                    continue;\n                } else if (*current_format_char_ptr == 'z') {\n                    current_format_char_ptr++;\n                    continue;\n                }\n\n                if (((*current_format_char_ptr >= 'A') && (*current_format_char_ptr <= 'Z'))\n                    || ((*current_format_char_ptr >= 'a') && (*current_format_char_ptr <= 'z')))\n                    break;\n\n                ++current_format_char_ptr;\n            }\n\n            switch (*current_format_char_ptr) {\n                case 's': {\n                    char *arg = (char *)va_arg(args, int);\n                    while (*arg != '\\0') {\n                        __write_byte_and_flush_if_needed(*arg);\n                        arg++;\n                    }\n                    __write_byte_and_flush_if_needed('\\0');\n                    break;\n                }\n                case 'c': {\n                    char arg_as_char = (char)va_arg(args, int);\n                    __write_byte_and_flush_if_needed(arg_as_char);\n                    break;\n                }\n                case 'f':\n                case 'e':\n                case 'E':\n                case 'g':\n                case 'G': {\n                    __asm__ volatile(\"nop\");\n                    double val = va_arg(args, double);\n                    char *arg = (char *)&val;\n                    for (int i = 0; i < 8; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                    break;\n                }\n                default: {\n                    unsigned int arg_size_in_bytes;\n                    long val;\n\n                    if (arg_is_64_bits) {\n                        val = va_arg(args, long);\n                        arg_size_in_bytes = 8;\n                    } else {\n                        val = (long)va_arg(args, int);\n                        arg_size_in_bytes = 4;\n                    }\n\n                    char *arg = (char *)&val;\n                    for (unsigned int i = 0; i < arg_size_in_bytes; i++) {\n                        char arg_byte = arg[i];\n                        __write_byte_and_flush_if_needed(arg_byte);\n                    }\n                }\n            }\n        } else {\n        standard_character_process:\n            __write_byte_and_flush_if_needed(*current_format_char_ptr);\n            insert_string_arg_end_character = true;\n        }\n    }\n\n    if (insert_string_arg_end_character) {\n        __write_byte_and_flush_if_needed('\\0');\n    }\n\n    va_end(args);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputs(const char *str)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('s');\n    __write_byte_and_flush_if_needed('\\0');\n\n    for (char *current_char_ptr = (char *)str; *current_char_ptr != '\\0'; current_char_ptr++) {\n        __write_byte_and_flush_if_needed(*current_char_ptr);\n    }\n\n    __write_byte_and_flush_if_needed('\\n');\n    __write_byte_and_flush_if_needed('\\0');\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n\nvoid\nputchar(int c)\n{\n    __open_print_sequence();\n\n    __write_byte_and_flush_if_needed('%');\n    __write_byte_and_flush_if_needed('c');\n    __write_byte_and_flush_if_needed('\\0');\n\n    char arg_as_char = (char)c;\n    __write_byte_and_flush_if_needed(arg_as_char);\n\n    __finalized_print_sequence();\n    __close_print_sequence();\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdio.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDIO_H_\n#define _DPUSYSCORE_STDIO_H_\n\n#include <attributes.h>\n#include <stddef.h>\n\n/**\n * @file stdio.h\n * @brief Standard input/output library functions.\n */\n\n/**\n * @def STDOUT_BUFFER_INIT\n * @hideinitializer\n * @brief Declares the stdout buffer. Should be used as when declaring a global variable.\n * @param size the size of the stdout buffer. Must be a multiple of 8, and greater than 0.\n */\n#define STDOUT_BUFFER_INIT(size)                                                                                                 \\\n    _Static_assert((size >= 8) && (((size)&7) == 0), \"stdout buffer size must be a multiple of 8 and > 0\");                      \\\n    unsigned char __dma_aligned __mram_noinit __stdout_buffer[(size)];                                                           \\\n    const unsigned int __stdout_buffer_size = (size);\n\n/**\n * @fn printf\n * @brief Writes the formatted data in the stdout buffer.\n *\n * This function has a prototype close to the one of the standard printf function.\n * However, the format string comply to the java.util.Formatter format, which is\n * similar to the printf format, but not quit exactly the same. Date formatter may\n * produce interpreted results, but they will probably be incorrect. Every format\n * specifier should reference one and only one of the variadic argument (eg. \"%n\"\n * is not supported).\n *\n * There is no compile-time check to verify that the format is correct: any other\n * character in the format string will not be interpreted.\n *\n * @param format how the logged data should be formatted\n * @param ... the different data to be printed\n */\nvoid __attribute__((format(printf, 1, 2))) printf(const char *restrict format, ...);\n\n/**\n * @fn puts\n * @brief Writes the string in the stdout buffer. A newline character is appended to the output.\n * @param str the null-terminated string to be written\n */\nvoid\nputs(const char *str);\n\n/**\n * @fn putchar\n * @brief Writes the character in the stdout buffer.\n * @param c the character to be written\n */\nvoid\nputchar(int c);\n\n#endif /* _DPUSYSCORE_STDIO_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdlib.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STDLIB_H\n#define DPUSYSCORE_STDLIB_H\n\n/**\n * @file stdlib.h\n * @brief Elementary standard C functions: calls the system function halt.\n */\n\n#include <stddef.h>\n#include <attributes.h>\n\n/**\n * @def EXIT_FAILURE\n * @hideinitializer\n * @brief Unsuccessful termination for exit().\n */\n#define EXIT_FAILURE 1\n\n/**\n * @def EXIT_SUCCESS\n * @hideinitializer\n * @brief Successful termination for exit().\n */\n#define EXIT_SUCCESS 0\n\n/**\n * @brief Aborts the DPU execution triggering a processor fault.\n */\n__NO_RETURN void\nabort(void);\n\n/**\n * @brief Terminates the invoking tasklet, returning the specified status.\n */\n__NO_RETURN void\nexit(int status);\n\n/**\n * @brief Get an environment variable, or NULL. In the DPU case, always NULL.\n */\nstatic inline char *\ngetenv(__attribute__((unused)) const char *name)\n{\n    return NULL;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline int\nabs(int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long int\nlabs(long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\n/**\n * @brief Returns the absolute value of the argument.\n */\nstatic inline long long int\nllabs(long long int x)\n{\n    return (x < 0) ? -x : x;\n}\n\ntypedef struct {\n    int quot;\n    int rem;\n} div_t;\n\ntypedef struct {\n    long int quot;\n    long int rem;\n} ldiv_t;\n\ntypedef struct {\n    long long int quot;\n    long long int rem;\n} lldiv_t;\n\nstatic inline div_t\ndiv(int numer, int denom)\n{\n    div_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline ldiv_t\nldiv(long int numer, long int denom)\n{\n    ldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\nstatic inline lldiv_t\nlldiv(long long int numer, long long int denom)\n{\n    lldiv_t result = { numer / denom, numer % denom };\n    return result;\n}\n\n/**\n * @brief Converts a string to an integer\n *\n * Function converts the initial part of the string in nptr to an integer value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atoi()\n * returns INT_MIN. If an overflow occurs, atoi() returns INT_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nint\natoi(const char *nptr);\n\n/**\n * @brief Converts a string to a long integer (64 bits)\n *\n * Function converts the initial part of the string in nptr to a long value. The string may begin\n * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n *\n * Conversion stops at the first character not representing a digit. If an underflow occurs, atol()\n * returns LONG_MIN. If an overflow occurs, atol() returns LONG_MAX. In both cases errno is set to ERANGE.\n *\n *\n * @param nptr string that contains an integer in a string format\n * @return the result of conversion unless the value would overflow or underflow.\n */\nlong\natol(const char *nptr);\n\n///**\n// * @brief Converts a string to a long integer (64 bits) according to the given base\n// * between 2 and 36 inclusive, or be the special value 0\n// *\n// * TODO : If the given base is oustide of the range [2...36], then errno is set to EINVAL\n// *\n// * Function converts the initial part of the string in nptr to a long value. The string may begin\n// * with an arbitrary amount of white space followed by a single optional '+' or '-' sign.\n// *\n// * If base is zero or 16, the string may then include a \"0x\" prefix, and the number will be read\n// * in base 16; otherwise, a zero base is taken as 10 (decimal) unless the next character is '0',\n// * in which case it is taken as 8 (octal).\n// *\n// * Conversion stops at the first character not representing a digit in the given base.\n// * Accepted digits are : in bases above 10, the letter 'A' in either uppercase or lowercase\n// * represents 10, 'B' represents 11, and so forth, with 'Z' representing 35.\n// *\n// * If endptr is not NULL, strtol() stores the address of the first invalid character in *endptr.\n// * If there were no digits at all, strtol() stores the original value of nptr in *endptr (and\n// * returns 0). In particular, if *nptr is not '\\0' but **endptr is '\\0' on return, the entire\n// * string is valid.\n// *\n// * If an underflow occurs, atol() returns LONG_MIN. If an overflow occurs, atol()\n// * returns LONG_MAX. TODO!!! In both cases errno is set to ERANGE.\n// *\n// * @param nptr string that contains an integer in a string format\n// * @param endptr\n// * @param base\n//\n// * @return the result of conversion unless the value would overflow or underflow.\n//*/\n// long int strtol(const char *nptr, char **endptr, int base);\n// TODO : strtol() doesn't work : has to be written in assembly\n\n#endif /* DPUSYSCORE_STDLIB_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stdnoreturn.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef _DPUSYSCORE_STDNORETURN_H_\n#define _DPUSYSCORE_STDNORETURN_H_\n\n/**\n * @file stdnoreturn.h\n * @brief Defines the noreturn macro.\n */\n\n/**\n * @def noreturn\n * @brief _Noreturn attribute.\n */\n#define noreturn _Noreturn\n\n#endif /* _DPUSYSCORE_STDNORETURN_H_ */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stpcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nchar *\nstpcpy(char *destination, const char *source)\n{\n    char c = *source;\n\n    while (c != '\\0') {\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    *destination = c;\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/stpncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstpncpy(char *destination, const char *source, size_t size)\n{\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            char *null_char_ptr = destination;\n\n            for (; each_byte < size; ++each_byte) {\n                *destination = '\\0';\n                destination++;\n            }\n\n            return null_char_ptr;\n        }\n\n        *destination = c;\n        destination++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strcat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcat(char *destination, const char *source)\n{\n    size_t length = strlen(destination);\n    unsigned int i;\n\n    for (i = 0; source[i] != '\\0'; i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrchr(const char *string, int character)\n{\n    char *str = (char *)string;\n    unsigned char c = *str;\n\n    while (1) {\n        if (c == character) {\n            return str;\n        }\n        if (c == '\\0') {\n            return NULL;\n        }\n\n        str++;\n        c = *str;\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strcmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrcmp(const char *string1, const char *string2)\n{\n    unsigned char c1 = *string1;\n    unsigned char c2 = *string2;\n\n    while (c1 != '\\0') {\n        if (c1 - c2 != 0) {\n            return c1 - c2;\n        }\n\n        string1++;\n        string2++;\n        c1 = *string1;\n        c2 = *string2;\n    }\n\n    return c1 - c2;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strcpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrcpy(char *destination, const char *source)\n{\n    char *ptr = destination;\n    char c = *source;\n\n    while (c != '\\0') {\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    *ptr = c;\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strcspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrcspn(const char *string, const char *reject)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        for (unsigned int reject_index = 0; reject[reject_index] != '\\0'; ++reject_index) {\n            if (reject[reject_index] == c) {\n                return prefix_length;\n            }\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strdup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrdup(const char *string)\n{\n    size_t length = strlen(string) + 1; // we get the length of the string for memory allocation\n\n    char *result = buddy_alloc(length); // we allocate length+1 bytes for the duplicate\n\n    if (result != NULL) {\n        memcpy(result, string, length); // we copy length bytes from string to the duplicate\n    }\n\n    return result;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strerror.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <defs.h>\n#include \"errno.h\"\n\n// http://www.delorie.com/gnu/docs/glibc/libc_17.html\n\n// static char* strerror_errors[] = { \"Success\",\n//\"E2BIG\", \"EACCES\", \"EADDRINUSE\", \"EADDRNOTAVAIL\", \"EAFNOSUPPORT\", \"EAGAIN\", \"EALREADY\", \"EBADF\",\n//\"EBADMSG\", \"EBUSY\", \"ECANCELED\", \"ECHILD\", \"ECONNABORTED\", \"ECONNREFUSED\", \"ECONNRESET\", \"EDEADLK\",\n//\"EDESTADDRREQ\", \"EDOM\", \"EDQUOT\", \"EEXIST\", \"EFAULT\", \"EFBIG\", \"EHOSTUNREACH\", \"EIDRM\",\n//\"EILSEQ\", \"EINPROGRESS\", \"EINTR\", \"EINVAL\", \"EIO\", \"EISCONN\", \"EISDIR\", \"ELOOP\",\n//\"EMFILE\", \"EMLINK\", \"EMSGSIZE\", \"EMULTIHOP\", \"ENAMETOOLONG\", \"ENETDOWN\", \"ENETRESET\", \"ENETUNREACH\",\n//\"ENFILE\", \"ENOBUFS\", \"ENODATA\", \"ENODEV\", \"ENOENT\", \"ENOEXEC\", \"ENOLCK\", \"ENOLINK\",\n//\"ENOMEM\", \"ENOMSG\", \"ENOPROTOOPT\", \"ENOSPC\", \"ENOSR\", \"ENOSTR\", \"ENOSYS\", \"ENOTCONN\",\n//\"ENOTDIR\", \"ENOTEMPTY\", \"ENOTRECOVERABLE\", \"ENOTSOCK\", \"ENOTSUP\", \"ENOTTY\", \"ENXIO\", \"EOPNOTSUPP\",\n//\"EOVERFLOW\", \"EOWNERDEAD\", \"EPERM\", \"EPIPE\", \"EPROTO\", \"EPROTONOSUPPORT\", \"EPROTOTYPE\", \"ERANGE\",\n//\"EROFS\", \"ESPIPE\", \"ESRCH\", \"ESTALE\", \"ETIME\", \"ETIMEDOUT\", \"ETXTBSY\", \"EWOULDBLOCK\",\n//\"EXDEV\"\n//};\n\n// 81 errors in total including 2 not supported ones.\n\nconst static char *strerror_errors_complete[] = { \"Success\",\n    \"Argument list too long\",\n    \"Permission denied\",\n    \"Address in use\",\n    \"Address not available\",\n    \"Address family not supported\",\n    \"Resource unavailable, try again\",\n    \"Connection already in progress\",\n    \"Bad file descriptor\",\n\n    \"Bad message\",\n    \"Device or resource busy\",\n    \"Operation canceled\",\n    \"No child processes\",\n    \"Connection aborted\",\n    \"Connection refused\",\n    \"Connection reset\",\n    \"Resource deadlock would occur\",\n\n    \"Destination address required\",\n    \"Mathematics argument out of domain of function\",\n    \"Disk quota exceeded\",\n    \"File exists\",\n    \"Bad address\",\n    \"File too big\",\n    \"Host unreachable\",\n    \"Identifier removed\",\n\n    \"Illegal byte sequence\",\n    \"Operation in progress\",\n    \"Interrupted function\",\n    \"Invalid argument\",\n    \"I/O error\",\n    \"Socket is connected\",\n    \"File is a directory\",\n    \"Too many levels of symbolic links\",\n\n    \"File descriptor value too large\",\n    \"Too many links\",\n    \"Message too large\",\n    \"EMULTIHOP\",\n    \"Filename too long\",\n    \"Network is down\",\n    \"Connection aborted by network\",\n    \"Network unreachable\",\n\n    \"Too many files open in system\",\n    \"No buffer space available\",\n    \"No message is available on the STREAM head read queue\",\n    \"No such device\",\n    \"No such file or directory\",\n    \"Executable file format error\",\n    \"No locks available\",\n    \"ENOLINK\",\n\n    \"Not enough space\",\n    \"No message of the desired type\",\n    \"Protocol unavailable\",\n    \"No space left on device\",\n    \"No STREAM resources\",\n    \"Not a STREAM\",\n    \"Function not supported\",\n    \"The socket is not connected\",\n\n    \"Not a directory or a symbolic link to a directory\",\n    \"Directory not empty\",\n    \"State not recoverable\",\n    \"Not a socket\",\n    \"Not supported\",\n    \"Inappropriate I/O control operation\",\n    \"No such device or address\",\n    \"Operation not supported on socket\",\n\n    \"Value too large to be stored in data type\",\n    \"Previous owner died\",\n    \"Operation not permitted\",\n    \"Broken pipe\",\n    \"Protocol error\",\n    \"Protocol not supported\",\n    \"Protocol wrong type for socket\",\n    \"Result too large\",\n\n    \"Read-only file system\",\n    \"Invalid seek\",\n    \"No such process\",\n    \"ESTALE\",\n    \"Stream ioctl() timeout\",\n    \"Connection timed out\",\n    \"Text file busy\",\n    \"Operation would block\",\n\n    \"Cross-device link\",\n    \"Unknown error\" };\n\nchar *\nstrerror(int errnum)\n{\n    unsigned int length = sizeof(strerror_errors_complete) / sizeof(strerror_errors_complete[0]) - 1; //-1 for \"Unknown error\"\n    if (((unsigned int)errnum) >= length) {\n        errno = EINVAL;\n        return (char *)strerror_errors_complete[length];\n    }\n    return (char *)strerror_errors_complete[errnum];\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/string.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_STRING_H\n#define DPUSYSCORE_STRING_H\n\n/**\n * @file string.h\n * @brief Provides functions to manipulate arrays of characters.\n */\n\n#include <stddef.h>\n\n/**\n * @brief Computes the length of the given null-terminated string.\n *\n * @param string the string for which we want the length.\n * @return The length of the string, not including the null character.\n */\nsize_t\nstrlen(const char *string);\n\n/**\n * @brief Computes the length of the given null-terminated string if this length is less than <code>max_len</code>.\n * strnlen checks at most <code>max_len</code> bytes and returns <code>max_len</code> if it has read as many bytes.\n *\n * @param string the string for which we want to find the length.\n * @param max_len maximum number of bytes to check\n * @return The length of the string, not including the null character or <code>max_len</code> if null character\n * wasn't found.\n */\nsize_t\nstrnlen(const char *string, size_t max_len);\n\n/**\n * @brief Compares the first <code>size</code> bytes of <code>area1</code> and <code>area2</code>.\n *\n * @param area1 the pointer to the start of the first area of the comparison\n * @param area2 the pointer to the start of the second area of the comparison\n * @param size the number of bytes to compare between each area.\n * @return <code>0</code> if the areas are the same, a non-zero value otherwise.\n */\nint\nmemcmp(const void *area1, const void *area2, size_t size);\n\n/**\n * @brief Compares the two null-terminated strings <code>string1</code> and <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrcmp(const char *string1, const char *string2);\n\n/**\n * @brief Compares the first <code>size</code> bytes of the two null-terminated strings <code>string1</code> and\n * <code>string2</code>.\n *\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @param size the maximum number of bytes to compare between each string.\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\nint\nstrncmp(const char *string1, const char *string2, size_t size);\n\n/**\n * @brief Set the first <code>size</code> bytes of <code>area</code> at <code>value</code>.\n *\n * @param area the pointer to the start of the area to set\n * @param value the value at which the area is set\n * @param size the number of bytes being set\n * @return A pointer to the start of the set area.\n */\nvoid *\nmemset(void *area, int value, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the first <code>size</code> bytes of <code>area</code>.\n *\n * @param area the pointer to the start of the area to search\n * @param character the value to search for\n * @param size the number of bytes to search\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nvoid *\nmemchr(const void *area, int character, size_t size);\n\n/**\n * @brief Concatenate the string <code>source</code> after the string <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrcat(char *destination, const char *source);\n\n/**\n * @brief Concatenate the first <code>size</code> bytes of the string <code>source</code> after the string\n * <code>destination</code>.\n *\n * @param destination the pointer to the start of the first string\n * @param source the pointer to the start of the second string\n * @param size the maximum number of bytes to concatenate\n * @return A pointer to the start of the concatenated string.\n */\nchar *\nstrncat(char *destination, const char *source, size_t size);\n\n/**\n * @brief Search for the first occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the first occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrchr(const char *string, int character);\n\n/**\n * @brief Search for the last occurrence of <code>character</code> in the <code>string</code>.\n *\n * @param string the pointer to the start of the string to search\n * @param character the value to search for\n * @return A pointer to the last occurrence, if it exists, <code>NULL</code> otherwise.\n */\nchar *\nstrrchr(const char *string, int character);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * @warning This function is not safe for overlapping memory blocks.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemcpy(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy <code>size</code> bytes from <code>source</code> into <code>destination</code>.\n *\n * This is a safer method than <code>memcpy</code> for overlapping memory blocks.\n *\n * @see memcpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the area to copy\n * @param size the number of bytes to copy\n * @return A pointer to the start of the copied area.\n */\nvoid *\nmemmove(void *destination, const void *source, size_t size);\n\n/**\n * @brief Copy the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\nchar *\nstrncpy(char *destination, const char *source, size_t size);\n\n/**\n * @def strxfrm\n * @hideinitializer\n * @brief Transform the first <code>size</code> bytes of the string <code>source</code> into current locale and place them in the\n * string <code>destination</code>.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strncpy</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @see strncpy\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the start of the copied string.\n */\n#define strxfrm strncpy\n\n/**\n * @def strcoll\n * @hideinitializer\n * @brief Compare two null-terminated strings using the current locale.\n *\n * There is no concept of \"locale\" in the DPU, implying that the related functions behave as native, \"locale-less\", functions.\n * This function is just a synonym of <code>strcmp</code>.\n *\n * @see strcmp\n * @param string1 the pointer to the start of the first string of the comparison\n * @param string2 the pointer to the start of the second string of the comparison\n * @return <code>0</code> if the strings are the same, a non-zero value otherwise.\n */\n#define strcoll strcmp\n\n/**\n * @brief Copy the string <code>source</code> into the string <code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpcpy(char *destination, const char *source);\n\n/**\n * @brief Copy <code>size</code> bytes from the string <code>source</code> into the string<code>destination</code>.\n *\n * @warning This function is not safe for overlapping strings.\n * If <code>size</code> is less than the length of the <code>source</code>, then\n * the remaining characters in <code>destination</code> will be filled with '\\0'\n *\n * @param destination the pointer to the start of the destination of the copy\n * @param source the pointer to the start of the string to copy\n * @param size the maximum number of bytes to copy\n * @return A pointer to the end (the address of the terminating null byte)\n * of the copied string.\n */\nchar *\nstpncpy(char *destination, const char *source, size_t size);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrlwr(char *string);\n\n/**\n * @brief Converts every character of a null-terminated string into lowercase\n *\n * Convertion is done in place. Only uppercase latin characters\n * will become lowercase, all other characters will remain\n * the same.\n *\n * @param string the string we want to convert to lowercase.\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrupr(char *string);\n\n/**\n * @brief Reverses the order of characters in the string\n *\n * For example, a string \"Hello\" becomes \"olleH\". The NULL character at the end\n * of the string remains at the end.\n *\n * @param string the string we want to reverse\n * @return The same pointer as the one passed in parameters\n */\nchar *\nstrrev(char *string);\n\n/**\n * @brief Returns a string corresponding to the error number\n *\n * Warning : the returned pointer should be duplicated if the user ever needs to modify it\n *\n * @param errnum number of error\n * @return the pointer to the message corresponding to the errnum or NULL if none was found\n */\nchar *\nstrerror(int errnum);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strdup(const char *string);\n\n/**\n * @brief Returns a pointer to a new string which is a duplicate of the argument (copies at most n bytes)\n *\n * Warning : Memory for the new string is obtained with buddy_alloc() //TODO buddy_alloc/malloc for now?\n * and should be freed with buddy_free().\n * buddy_init() should be called before calling strerror().\n *\n * @param string string to duplicate\n * @param n max number of characters to duplicate\n * @return the pointer to the duplicate of the argument string or NULL if couldn't allocate enough memory space\n */\n// char *strndup(const char *string, size_t n);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes in accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters that the longest prefix consists of\n * @return the index of the first character in string that is not in accept\n */\nsize_t\nstrspn(const char *string, const char *accept);\n\n/**\n * @brief Calculates the length of the longest prefix of string which consists entirely of bytes not in reject.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param reject key characters that must not be in the longest prefix\n * @return the index of the first character in string that is the same as any of the ones in reject\n */\nsize_t\nstrcspn(const char *string, const char *reject);\n\n/**\n * @brief Locates the first occurrence in the target string of any of the bytes in the string accept.\n *\n *  The function does not sort the characters and does not delete the double occurrences in accept.\n *  If the user wishes to accelerate the function, she/he needs to do this separately.\n *  This decision was made, because the usefulness of such operations highly depends on the parameters.\n *\n * @param string the target of the function\n * @param accept key characters\n * @return a pointer to the byte in string that matches one of the bytes in accept, or NULL if no such byte is found.\n */\nchar *\nstrpbrk(const char *string, const char *accept);\n\n/**\n * @brief Finds the first occurrence of the substring needle in the string haystack.\n *\n * If needle is an empty string, the result will be the same pointer as the one passed to haystack\n * This function uses KMP algorithm, and thereby uses more memory space\n *\n * @param haystack the target string where we look for a pattern\n * @param needle pattern to look for\n * @return a pointer to the beginning of the located substring, or NULL if the substring is not found\n */\nchar *\nstrstr(const char *haystack, const char *needle);\n\n/**\n * @brief Extracts a token from a string\n *\n * The strtok_r() function breaks a string into a sequence of zero or more nonempty tokens.\n *\n * On the first call to strtok_r(), str should point to the string to be parsed, and the value of saveptr is ignored (modified\n * internally). In each subsequent call that should parse the same string, str must be NULL and saveptr should be unchanged since\n * the previous call.\n *\n * The caller may specify different strings in delim in successive calls that parse the same string. For instance, if string is\n * \"a,b,c d e f,g\", by calling strtok_r() only with \",\" delimiter will create 4 tokens, but if the user calls it 2 times with \",\"\n * delimiter and then the rest with \" \" delimiter, 6 tokens wil be created : \"a\",\"b\",\"c\",\"d\",\"e\",\"f,g\" (\"f,g\" is indeed one token\n * as strtok_r() was called with \" \" delimiter).\n *\n * Each call to strtok_r() returns a pointer to a null-terminated string containing the next token. This string does not include\n * the delimiting byte. If no more tokens are found, strtok_r() returns NULL.\n *\n * A sequence of calls to strtok_r() that operate on the same string maintains a pointer that determines the point from which to\n * start searching for the next token. The first call to strtok_r() sets this pointer to point to the first byte of the string.\n * The start of the next token is determined by scanning forward for the next nondelimiter byte in str. If such a byte is found,\n * it is taken as the start of the next token. If no such byte is found, then there are no more tokens, and strtok_r() returns\n * NULL. (A string that is empty or that contains only delimiters will thus cause strtok() to return NULL on the first call.)\n *\n * The end of each token is found by scanning forward until either the next delimiter byte is found or until the terminating null\n * byte ('\\0') is encountered. If a delimiter byte is found, it is OVERWRITTEN with a null byte to terminate the current token,\n * and strtok_r() saves a pointer to the following byte; that pointer will be used as the starting point when searching for the\n * next token. In this case, strtok_r() returns a pointer to the start of the found token.\n *\n * From the above description, it follows that a sequence of two or more contiguous delimiter bytes in the parsed string is\n * considered to be a single delimiter, and that delimiter bytes at the start or end of the string are ignored. Put another way:\n * the tokens returned by strtok() are always nonempty strings.\n *\n * Different strings may be parsed concurrently using sequences of calls to strtok_r() that specify different saveptr arguments.\n *\n * Warning :\n *      strtok_r modifies str\n *      identity of delimiter bytes is lost (i.e. most of them will be replaced by '\\0' in str)\n *      if NULL is passed as the first argument for the FIRST call, *saveptr (not saveptr) should also be NULL\n *\n * @param str string to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @param saveptr pointer used internally by strtok_r in order to maintain context between successive calls that parse the same\n * string\n * @return a pointer to the beginning of the next token terminated by '\\0' or NULL if there are no more tokens\n */\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr);\n\n/**\n * @brief Extracts a token from a string\n *\n * If *stringp is NULL, the strsep() function returns NULL and does nothing else. Otherwise, this function finds the first token\n * in the string *stringp, that is delimited by one of the bytes in the string delim. This token is terminated by overwriting the\n * delimiter with a null byte ('\\0'), and *stringp is updated to point past the token. In case no delimiter was found, the token\n * is taken to be the entire string *stringp, and *stringp is made NULL.\n *\n * Warning:\n *      strsep() modifies its first parameter\n *      identity of delimiter bytes is lost (they will be replaced by '\\0' in *stringp)\n *\n * @param stringp pointer to a string (because string will be modified) to extract tokens from\n * @param delim string that contains bytes that would serve as delimiters\n * @return a pointer to the found null-terminated token, that is, it returns the original value of *stringp\n */\nchar *\nstrsep(char **stringp, const char *delim);\n\n#endif /* DPUSYSCORE_STRING_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrlen(const char *string)\n{\n    const char *ptr = string;\n\n    while (*ptr != '\\0') {\n        ptr++;\n    }\n\n    return ptr - string;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strlwr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrlwr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = tolower(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strncat.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrncat(char *destination, const char *source, size_t size)\n{\n    size_t length = strlen(destination);\n    size_t i;\n\n    for (i = 0; (i < size) && (source[i] != '\\0'); i++) {\n        destination[length + i] = source[i];\n    }\n\n    destination[length + i] = '\\0';\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strncmp.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nint\nstrncmp(const char *string1, const char *string2, size_t size)\n{\n    for (size_t len = 0; len < size; ++len) {\n        unsigned char c1 = string1[len];\n        unsigned char c2 = string2[len];\n\n        if (((c1 - c2) != 0) || (c1 == '\\0')) {\n            return c1 - c2;\n        }\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strncpy.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrncpy(char *destination, const char *source, size_t size)\n{\n    char *ptr = destination;\n    char c = *source;\n    size_t each_byte;\n\n    for (each_byte = 0; each_byte < size; ++each_byte) {\n        if (c == '\\0') {\n            for (; each_byte < size; ++each_byte) {\n                *ptr = '\\0';\n                ptr++;\n            }\n\n            return destination;\n        }\n\n        *ptr = c;\n        ptr++;\n        source++;\n        c = *source;\n    }\n\n    return destination;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strndup.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrndup(const char *string, size_t n)\n{\n    size_t length = strnlen(string, n);\n    char *result = buddy_alloc(length + 1);\n\n    if (result != NULL) {\n        memcpy(result, string, length);\n        ((char *)result)[length + 1] = '\\0';\n    }\n\n    return result;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strnlen.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nsize_t\nstrnlen(const char *string, size_t max_len)\n{\n    size_t len = 0;\n\n    while ((string[len] != '\\0') && len < max_len) {\n        len++;\n    }\n\n    return len;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strpbrk.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\nchar *\nstrpbrk(const char *string, const char *accept)\n{\n    string += strcspn(string, accept);\n    return *string ? (char *)string : NULL;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strrchr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n\nchar *\nstrrchr(char *string, int character)\n{\n    char *pos = NULL;\n    char *ptr = string;\n    unsigned char c;\n\n    do {\n        c = *ptr;\n        if (c == character) {\n            pos = ptr;\n        }\n        ptr++;\n    } while (c != '\\0');\n\n    return pos;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strrev.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrrev(char *string)\n{\n    size_t length = strlen(string);\n\n    for (size_t each_char = 0; each_char < length / 2; ++each_char) {\n        char c = string[each_char];\n        string[each_char] = string[length - each_char - 1];\n        string[length - each_char - 1] = c;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strsep.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n\nchar *\nstrsep(char **stringp, const char *delim)\n{\n    if (*stringp == NULL) {\n        return NULL;\n    }\n\n    char *original = *stringp;\n    char *delim_ptr = strpbrk(*stringp, delim);\n\n    if (delim_ptr == NULL) {\n        *stringp = NULL;\n    } else {\n        *delim_ptr = '\\0';\n        *stringp = delim_ptr + 1;\n    }\n\n    return original;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strspn.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <string.h>\n#include <stdbool.h>\n\n// TODO Possible optimization:\n//  use of the table of indexation that indicates if the character should or should not be accepted/rejected\n//  in this case we will need 128 bits (as there are 128 ascii characters) ( = 16 bytes = 4 words ) per runtime\n// => 4x24 = 96 words of 32 bits.\n//\n//  TODO Another solution would be to stock this table only temporarily with the allocation function, but, currently, it's not an\n//  option.\n\nsize_t\nstrspn(const char *string, const char *accept)\n{\n    size_t prefix_length;\n\n    for (prefix_length = 0; string[prefix_length] != '\\0'; ++prefix_length) {\n        char c = string[prefix_length];\n\n        unsigned int accept_index = 0;\n        while (true) {\n            char a = accept[accept_index];\n\n            if (c == a) {\n                break;\n            }\n\n            if (a == '\\0') {\n                return prefix_length;\n            }\n\n            accept_index++;\n        }\n    }\n\n    return prefix_length;\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strstr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"stdbool.h\"\n#include \"string.h\"\n#include \"buddy_alloc.h\"\n\nchar *\nstrstr(const char *haystack, const char *needle)\n{\n    char *current_needle = (char *)needle;\n    char *start_haystack = (char *)haystack;\n    char *current_haystack = start_haystack;\n\n    while (true) {\n        char needle_char = *current_needle;\n\n        if (needle_char == '\\0') {\n            return start_haystack;\n        }\n\n        char haystack_char = *current_haystack;\n\n        if (haystack_char == needle_char) {\n            current_haystack++;\n            current_needle++;\n        } else if (haystack_char == '\\0') {\n            return NULL;\n        } else {\n            current_needle = (char *)needle;\n            current_haystack = ++start_haystack;\n        }\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strtok_r.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include \"string.h\"\n\nchar *\nstrtok_r(char *str, const char *delim, char **saveptr)\n{\n    char *end;\n\n    if (str == NULL) {\n        str = *saveptr;\n    }\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    str += strspn(str, delim);\n\n    if (*str == '\\0') {\n        *saveptr = str;\n        return NULL;\n    }\n\n    end = str + strcspn(str, delim);\n    if (*end == '\\0') {\n        *saveptr = end;\n        return str;\n    }\n\n    *end = '\\0';\n    *saveptr = end + 1;\n    return str;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strtol.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n////\n//////TODO : **endptr\n////\n////#include <stddef.h>\n////#include \"ctype.h\"\n////#include \"limits.h\"\n////\n////static long overflow(int sign)\n////{\n////    if(sign)\n////        return INT64_MAX;\n////    else\n////        return INT64_MIN;\n////\n////\n////}\n////\n////long strtol(const char *nptr, char **endptr, int base)\n////{\n////    if(nptr == NULL)\n////        return 0;\n////    unsigned long result = 0;\n////    int sign = 1;\n////    int i = 0;\n//////    while(isspace(nptr[i]))\n//////        i++;\n////\n//////    switch(nptr[i]){\n//////        case '-' :\n//////            sign = 0;       //we change sign only when '-' was encountered\n//////        case '+' :\n//////            i++;            //we increment i in both cases\n//////    }\n////\n//////\n//////    if((base == 16 ) && (nptr[i] == '0') && (nptr[i+1] == 'x'))\n//////        i+=2;\n//////    else if(base == 0){\n//////        if(nptr[i] == '0'){\n//////            base = 8;\n//////            i++;\n//////            if(nptr[i+1] == 'x'){\n//////                base = 16;\n//////                i++;\n//////            }\n//////        }\n//////        else\n//////            base = 10;\n//////    }\n////\n//////    switch(base) {\n//////        case 10 :\n////            while(((nptr[i]>>4) == 0x3) && ((nptr[i] & 0xf)<=9)){\n////                if((unsigned long)result>>60){\n////                    return overflow(sign);\n////                }\n////\n////                result = (unsigned long)(result<<1) + (unsigned long)(result<<3) + (unsigned long) nptr[i] - (unsigned long)\n///'0';\n//////                if((unsigned long)result>>63){\n//////                    return overflow(sign);\n//////                }\n////                i++;\n////            }\n//////            break;\n//////        case 2 :\n//////            while((nptr[i] & 0xfe) == 0x30){\n//////                result = (result<<1) + (unsigned long)(nptr[i] & 0x1);\n//////                i++;\n//////            }\n//////            break;\n//////        case 4 :\n//////            while((nptr[i] & 0xfc) == 0x30){\n//////                result = (result<<2) + (unsigned long)(nptr[i] & 0x3);\n//////                i++;\n//////            }\n//////            break;\n//////        case 8 :\n//////            while((nptr[i] & 0xf8) == 0x30){\n//////                result = (result<<3) + (unsigned long)(nptr[i] & 0x7);\n//////                i++;\n//////            }\n//////            break;\n//////        case 16 :\n//////            while(((nptr[i]>='0') && (nptr[i]<='9')) || ((nptr[i]>='a') && (nptr[i]<='f')) || ((nptr[i]>='A') &&\n///(nptr[i]<='F')) ){\n//////                unsigned long digit = ((nptr[i]>='0') && (nptr[i]<='9')) ? (unsigned long)(nptr[i] - '0') : (unsigned\n/// long)((nptr[i] & 0xf) + 10);\n//////                result = result<<4;\n//////                result = result + digit;\n//////                i++;\n//////            }\n//////            break;\n//////        default :\n//////            if(base < 2 || base > 36){ //base 0 has already been replaced by 8,10 or 16\n//////                //TODO!!!\n//////                break;\n//////            }\n//////    }\n////\n//////    if(sign == 0)\n//////        return (long)0 - (long)result;\n//////    else\n////        return (long) result;\n////\n////}\n////\n//\n//\n//\n////\n//\n//// Copyright (c) 2014-2019 - UPMEM\n//\n////\n//\n//#include <stddef.h>\n//\n//#include \"limits.h\"\n//\n//#include \"ctype.h\"\n//\n// static long overflow(int sign)\n//\n//{\n//\n//    if(sign)\n//\n//        return INT64_MAX;\n//\n//    else\n//\n//        return INT64_MIN;\n//\n//}\n//\n// long int strtol(const char *nptr, char **endptr, int base)\n//\n//{\n//\n//    if(nptr == NULL)\n//\n//        return 0;\n//\n//    int sign = 1;\n//\n//    int i=0;\n//\n//    long result = 0;\n//\n//\n//\n//    while((nptr[i]>='0') && (nptr[i]<='9')){\n//\n//        if(result>>60){\n//\n//                    return overflow(sign);\n//\n//                }\n//\n//        result = (result<<1) + (result<<3)+ nptr[i] - '0';\n//\n//        i++;\n//\n//    }\n//\n//    return result;\n//\n//}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/stdlib/strupr.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <ctype.h>\n\nchar *\nstrupr(char *string)\n{\n    char *ptr = string;\n    char c;\n\n    while ((c = *ptr) != '\\0') {\n        *ptr = toupper(c);\n        ptr++;\n    }\n\n    return string;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/absvdi2.c",
    "content": "/*===-- absvdi2.c - Implement __absvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __absvdi2 for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI di_int\n__absvdi2(di_int a)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    if (a == ((di_int)1 << (N - 1)))\n        compilerrt_abort();\n    const di_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/absvsi2.c",
    "content": "/* ===-- absvsi2.c - Implement __absvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __absvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: absolute value */\n\n/* Effects: aborts if abs(x) < 0 */\n\nCOMPILER_RT_ABI si_int\n__absvsi2(si_int a)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    if (a == (1 << (N - 1)))\n        compilerrt_abort();\n    const si_int t = a >> (N - 1);\n    return (a ^ t) - t;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/adddf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI double\n__adddf3(double a, double b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_dadd(double a, double b)\n{\n    return __adddf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/addsf3.c",
    "content": "//===-- lib/addsf3.c - Single-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI float\n__addsf3(float a, float b)\n{\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_fadd(float a, float b)\n{\n    return __addsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/addvdi3.c",
    "content": "/* ===-- addvdi3.c - Implement __addvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI di_int\n__addvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a + (du_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/addvsi3.c",
    "content": "/* ===-- addvsi3.c - Implement __addvsi3 -----------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __addvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a + b */\n\n/* Effects: aborts if a + b overflows */\n\nCOMPILER_RT_ABI si_int\n__addvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a + (su_int)b;\n    if (b >= 0) {\n        if (s < a)\n            compilerrt_abort();\n    } else {\n        if (s >= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nvolatile unsigned int __sys_heap_pointer = (unsigned int)(&__sys_heap_pointer_reset);\n\nATOMIC_BIT_INIT(__heap_pointer);\n\n/* noinline, because part of grind tracked functions\n * Also used by seqread.inc\n */\nvoid *__noinline\nmem_alloc_nolock(size_t size)\n{\n    unsigned int pointer = __HEAP_POINTER;\n\n    if (size != 0) {\n        pointer = (pointer + 7) & ~7;\n\n        unsigned int new_heap_pointer, dummy;\n\n        __asm__ volatile(\"\\tadd %[nhp], %[ptr], %[sz], nc, . + 2\\n\"\n                         \"\\tfault \" __STR(__FAULT_ALLOC_HEAP_FULL__) \"\\n\"\n                                                                     \"\\tlbu %[dumb], %[nhp], -1\\n\"\n                         : [nhp] \"=r\"(new_heap_pointer), [dumb] \"=r\"(dummy)\n                         : [ptr] \"r\"(pointer), [sz] \"r\"(size));\n\n        __HEAP_POINTER = new_heap_pointer;\n    }\n    return (void *)pointer;\n}\n\nvoid *\nmem_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n    void *pointer = mem_alloc_nolock(size);\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n    return pointer;\n}\n\nvoid *\nmem_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    void *initial = &__sys_heap_pointer_reset;\n\n    __sys_heap_pointer = (unsigned int)initial;\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return (void *)initial;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ALLOC_H\n#define DPUSYSCORE_ALLOC_H\n\n/**\n * @file alloc.h\n * @brief Provides a way to manage heap allocation.\n *\n * @internal The heap is situated after the different kernel structures, local and global variables.\n *           It can grow until reaching the end of the WRAM. A reboot of the DPU reset the Heap.\n *           The current heap pointer can be accessed at the address defined by __HEAP_POINTER__.\n */\n\n#include <stddef.h>\n\n#include <fsb_allocator.h>\n#include <buddy_alloc.h>\n\n#include <attributes.h>\n\n/**\n * @fn mem_alloc\n * @brief Allocates a buffer of the given size in the heap.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * @param size the allocated buffer's size, in bytes\n * @throws a fault if there is no memory left\n * @return The allocated buffer address.\n */\nvoid *\nmem_alloc(size_t size);\n\n/**\n * @fn mem_reset\n * @brief Resets the heap.\n *\n * Every allocated buffer becomes invalid, since subsequent allocations restart from the beginning\n * of the heap.\n *\n * @return The heap initial address.\n */\nvoid *\nmem_reset(void);\n\n#endif /* DPUSYSCORE_ALLOC_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ashldi3.c",
    "content": "/* ====-- ashldi3.c - Implement __ashldi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashldi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a << b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashldi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.low = 0;\n        result.s.high = input.s.low << (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.low = input.s.low << b;\n        result.s.high = (input.s.high << b) | (input.s.low >> (bits_in_word - b));\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsl(di_int a, si_int b)\n{\n    return __ashldi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ashrdi3.c",
    "content": "/*===-- ashrdi3.c - Implement __ashrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: arithmetic a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        /* result.s.high = input.s.high < 0 ? -1 : 0 */\n        result.s.high = input.s.high >> (bits_in_word - 1);\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_lasr(di_int a, si_int b)\n{\n    return __ashrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/atomic_bit.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATOMIC_BIT_H\n#define DPUSYSCORE_ATOMIC_BIT_H\n\n/**\n * @file atomic_bit.h\n * @brief Provides direct access to the atomic bits.\n */\n\n#include <stdint.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n#define ATOMIC_BIT_GET(_name) __CONCAT(__atomic_bit_, _name)\n#define ATOMIC_BIT_INIT(_name) uint8_t __atomic_bit ATOMIC_BIT_GET(_name)\n#define ATOMIC_BIT_EXTERN(_name) extern ATOMIC_BIT_INIT(_name)\n\nextern uint8_t __atomic_start_addr;\n#define ATOMIC_BIT_INDEX(_name) (&ATOMIC_BIT_GET(_name) - &__atomic_start_addr)\n\n#define __ATOMIC_BIT_ACQUIRE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"acquire %[areg], %[abit], nz, .\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define __ATOMIC_BIT_RELEASE(_reg, _bit)                                                                                         \\\n    __asm__ volatile(\"release %[areg], %[abit], nz, .+1\" : : [areg] \"r\"(_reg), [abit] \"i\"(_bit))\n\n#define ATOMIC_BIT_ACQUIRE(_name) __asm__ volatile(\"acquire zero, %[abit], nz, .\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#define ATOMIC_BIT_RELEASE(_name) __asm__ volatile(\"release zero, %[abit], nz, .+1\" : : [abit] \"i\"(&ATOMIC_BIT_GET(_name)))\n\n#endif /* DPUSYSCORE_ATOMIC_BIT_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/atomics.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * Prototype of function can be found here: https://llvm.org/docs/Atomics.html\n */\n\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\n#define ATOMIC_BIT llvm_atomic_functions\nATOMIC_BIT_INIT(ATOMIC_BIT);\n\n#define FOR_ALL_TYPES(fct) fct(1, char) fct(2, short) fct(4, int) fct(8, long long)\n\n#define PROLOGUE(ptr, load, n_type)                                                                                              \\\n    n_type load;                                                                                                                 \\\n    ATOMIC_BIT_ACQUIRE(ATOMIC_BIT);                                                                                              \\\n    load = *ptr;\n\n#define EPILOGUE(load)                                                                                                           \\\n    ATOMIC_BIT_RELEASE(ATOMIC_BIT);                                                                                              \\\n    return load;\n\n#define __SYNC_VAL_COMPARE_AND_SWAP_N(n_val, n_type)                                                                             \\\n    n_type __dpu_sync_val_compare_and_swap_##n_val(volatile n_type *ptr, n_type expected, n_type desired)                        \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        if (load == expected)                                                                                                    \\\n            *ptr = desired;                                                                                                      \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_VAL_COMPARE_AND_SWAP_N)\n\n#define __SYNC_LOCK_TEST_AND_SET_N(n_val, n_type)                                                                                \\\n    n_type __dpu_sync_lock_test_and_set_##n_val(volatile n_type *ptr, n_type val)                                                \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = val;                                                                                                              \\\n        EPILOGUE(load);                                                                                                          \\\n    }\nFOR_ALL_TYPES(__SYNC_LOCK_TEST_AND_SET_N)\n\n#define __SYNC_FETCH_AND_DO_N(fct, fct_name, n_val, n_type)                                                                      \\\n    n_type __dpu_sync_fetch_and_##fct_name##_##n_val(volatile n_type *ptr, n_type val)                                           \\\n    {                                                                                                                            \\\n        PROLOGUE(ptr, load, n_type);                                                                                             \\\n        *ptr = fct(load, val, n_type);                                                                                           \\\n        EPILOGUE(load);                                                                                                          \\\n    }\n\n#define DO_ADD(a, b, n_type) ((a) + (b))\n#define __SYNC_FETCH_AND_ADD_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_ADD, add, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_ADD_N)\n\n#define DO_SUB(a, b, n_type) ((a) - (b))\n#define __SYNC_FETCH_AND_SUB_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_SUB, sub, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_SUB_N)\n\n#define DO_AND(a, b, n_type) ((a) & (b))\n#define __SYNC_FETCH_AND_AND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_AND, and, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_AND_N)\n\n#define DO_OR(a, b, n_type) ((a) | (b))\n#define __SYNC_FETCH_AND_OR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_OR, or, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_OR_N)\n\n#define DO_XOR(a, b, n_type) ((a) ^ (b))\n#define __SYNC_FETCH_AND_XOR_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_XOR, xor, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_XOR_N)\n\n#define DO_NAND(a, b, n_type) (~((a) & (b)))\n#define __SYNC_FETCH_AND_NAND_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_NAND, nand, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_NAND_N)\n\n#define DO_MAX(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MAX, max, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MAX_N)\n\n#define DO_UMAX(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMAX_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMAX, umax, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMAX_N)\n\n#define DO_MIN(a, b, n_type) ((a) > (b) ? (a) : (b))\n#define __SYNC_FETCH_AND_MIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_MIN, min, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_MIN_N)\n\n#define DO_UMIN(a, b, n_type) (((unsigned n_type)(a)) > ((unsigned n_type)(b)) ? (a) : (b))\n#define __SYNC_FETCH_AND_UMIN_N(n_val, n_type) __SYNC_FETCH_AND_DO_N(DO_UMIN, umin, n_val, n_type)\nFOR_ALL_TYPES(__SYNC_FETCH_AND_UMIN_N)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/attributes.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_ATTRIBUTES_H\n#define DPUSYSCORE_ATTRIBUTES_H\n\n/**\n * @file attributes.h\n * @brief Provides common useful compiler attributes.\n */\n\n#define DEPRECATED __attribute__((deprecated))\n\n#if __STDC_VERSION__ >= 201112L\n#define __NO_RETURN _Noreturn\n#else\n#define __NO_RETURN\n#endif /* __STDC_VERSION__ */\n\n#define __weak __attribute__((weak))\n\n#define __section(s) __attribute__((section(s)))\n\n#define __aligned(a) __attribute__((aligned(a)))\n\n#define __used __attribute__((used))\n\n#define __noinline __attribute__((noinline))\n\n#define __atomic_bit __section(\".atomic\")\n\n#define __dma_aligned __aligned(8)\n\n#define __keep __used __section(\".data.__sys_keep\")\n\n#define __host __aligned(8) __used __section(\".dpu_host\")\n\n// Use this macro at variable definition to place this variable into the section\n// .data.immediate_memory and then makes it possible to use this variable\n// directly as an immediate into load store instructions (and then avoids the need\n// to move the address into a register before): immediate values are 12 signed bits\n// large.\n#define __lower_data(name) __attribute__((used, section(\".data.immediate_memory.\" name)))\n\n/**\n * @def __mram_ptr\n * @brief An attribute declaring that a pointer is an address in MRAM.\n *\n * A typical usage is: ``unsigned int __mram_ptr * array32 = (unsigned int __mram_ptr *) 0xf000;``\n *\n * Performing a cast between a pointer in MRAM and a pointer in WRAM is not allowed by the compiler.\n *\n */\n#define __mram_ptr __attribute__((address_space(255)))\n\n#define __mram __mram_ptr __section(\".mram\") __dma_aligned __used\n\n#define __mram_noinit __mram_ptr __section(\".mram.noinit\") __dma_aligned __used\n\n#define __mram_keep __mram_ptr __section(\".mram.keep\") __dma_aligned __used\n\n#define __mram_noinit_keep __mram_ptr __section(\".mram.noinit.keep\") __dma_aligned __used\n\n#endif /* DPUSYSCORE_ATTRIBUTES_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/barrier.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <barrier.h>\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nvoid\nbarrier_wait(struct barrier_t *barrier)\n{\n    unsigned char lock = barrier->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = barrier->count;\n    unsigned char last = barrier->wait_queue;\n    unsigned char first;\n    thread_id_t tid = me();\n\n    /* Count = 1 means that I am the last to enter the barrier.\n     * Need to wake up everybody.*/\n    if (unlikely(count == 1)) {\n        if (likely(last != __EMPTY_WAIT_QUEUE)) {\n            first = __WAIT_QUEUE_TABLE[last];\n            while (first != last) {\n                __resume(first, \"0\");\n                first = __WAIT_QUEUE_TABLE[first];\n            }\n            __resume(first, \"0\");\n            barrier->wait_queue = __EMPTY_WAIT_QUEUE;\n            barrier->count = barrier->initial_count;\n        }\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    } else {\n        if (unlikely(last == __EMPTY_WAIT_QUEUE)) {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        } else {\n            first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        }\n\n        barrier->wait_queue = tid;\n        barrier->count = --count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/barrier.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BARRIER_H\n#define DPUSYSCORE_BARRIER_H\n\n/**\n * @file barrier.h\n * @brief Synchronization with barriers.\n *\n * This synchronization mechanism allows to suspend a fixed number of tasklets until the expected number of subscribers is\n * present. When the required number of tasklets reached the barrier, the counter of the barrier will be reinitialised to the\n * original value.\n *\n * @internal The barriers are represented by a static value, defining the number of expected tasklets, a counter for the\n *           current number of tasklets suspended by this barrier and a wait queue entry.\n *           Whenever a new tasklet reaches the barrier (barrier_wait), the counter is  decremented and the tasklet\n *           is put into the wait queue.\n *           If the counter is reduced to 0, all the tasklets that were suspended by this barrier will be resumed and\n *           the counter will be reinitialised to its initial value.\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef barrier_t\n * @brief A barrier object, as declared by BARRIER_INIT.\n */\ntypedef struct barrier_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} barrier_t;\n\n/**\n * @def BARRIER_INIT\n * @hideinitializer\n * @brief Declare and initialize a barrier associated to the given name.\n */\n/* clang-format off */\n#define BARRIER_INIT(_name, _counter)                                                                                            \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"barrier counter must be encoded on a byte\");                         \\\n    ATOMIC_BIT_INIT(__CONCAT(barrier_, _name));                                                                                  \\\n    extern barrier_t _name;                                                                                                      \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR( _name) \",@object\\n\"                                                                                  \\\n            \".globl \" __STR( _name) \"\\n\"                                                                                         \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(barrier_,_name))) \"\\n\"                                                        \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn barrier_wait\n * @brief Decrements the counter associated to the barrier and suspends the invoking tasklet.\n *\n * The counter of the barrier is decremented and the invoking tasklet is suspended until\n * the counter associated to the barrier is reduced to 0.\n *\n * @param barrier the barrier the tasklet will be associated to.\n */\nvoid\nbarrier_wait(barrier_t *barrier);\n\n#endif /* DPUSYSCORE_BARRIER_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/bswapdi2.c",
    "content": "/* ===-- bswapdi2.c - Implement __bswapdi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint64_t\n__bswapdi2(uint64_t u)\n{\n    return ((((u)&0xff00000000000000ULL) >> 56) | (((u)&0x00ff000000000000ULL) >> 40) | (((u)&0x0000ff0000000000ULL) >> 24)\n        | (((u)&0x000000ff00000000ULL) >> 8) | (((u)&0x00000000ff000000ULL) << 8) | (((u)&0x0000000000ff0000ULL) << 24)\n        | (((u)&0x000000000000ff00ULL) << 40) | (((u)&0x00000000000000ffULL) << 56));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/bswapsi2.c",
    "content": "/* ===-- bswapsi2.c - Implement __bswapsi2 ---------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __bswapsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI uint32_t\n__bswapsi2(uint32_t u)\n{\n    return ((((u)&0xff000000) >> 24) | (((u)&0x00ff0000) >> 8) | (((u)&0x0000ff00) << 8) | (((u)&0x000000ff) << 24));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/buddy_alloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <buddy_alloc.h>\n#include <alloc.h> //for mem_alloc\n#include <stddef.h> //for size_t\n#include <string.h> //for memset\n#include <dpuruntime.h>\n#include <errno.h>\n#include <defs.h>\n#include <stdbool.h>\n#include <built_ins.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nstatic unsigned char __buddy_init_done = 0;\nstatic int *__buddy_blocks = 0;\nstatic void *__buddy_heap_start = 0;\nstatic unsigned int __BUDDY_SIZE_OF_HEAP__ = 0;\nstatic unsigned char __BUDDY_MAX_POWER__ = 0;\nstatic unsigned char __BUDDY_NUMBER_OF_LEVELS__ = 0;\n\nATOMIC_BIT_INIT(__buddy_lock);\n\n#define __BUDDY_DEPTH_LEVELS__ 3\n#define __BUDDY_SHIFT_ADDRESS_TO_INDEX__ 4\n\nstatic inline unsigned int\nnext_power_of_2(int x)\n{\n    // in order to find the size of the block to allocate we\n    // count the number of leading zeros to get the correct\n    // log2(size)\n    // if size has only one \"1\" bit then we keep this power of 2\n    // otherwise, we add 1\n\n    unsigned int power_of_2 = 31 - count_leading_zeros(x);\n\n    if (count_population(x) != 1) {\n        power_of_2++;\n    }\n\n    return power_of_2;\n}\n\n/*\n * Note 1:\n *   each bit represents the state of a block. It can equal either 0 or 1 and can represent 4 different states of a block :\n *   target = 1 & buddy = 0                                      -> free                     : target block is [free] and can be\n * allocated without the need to cut the bigger block in half target = 1 & buddy = 1                                      -> not\n * in use               : neither target nor its buddy are in use and bigger blocks must be checked\n *\n *   target = 0 & both successors = 1 [not in use]               -> allocated                : this block is completely allocated\n *   target = 0 & one or both of the successors = 0 [allocated]  -> partially allocated      : block is partially allocated i.e.\n * at least one of the sub-blocks is [allocated]\n *\n * Note 2:\n *  Indexes of __buddy_blocks are indeed quite bizarre, which was a mistake during the conception stage. It doesn't change much.\n *  Indexe_in_level start from 0 from left to right, but not for the 5 least significant bits where they still start from 0 but\n * from right to left\n */\nvoid *\nsafe_buddy_alloc(size_t size)\n{\n    if ((size == 0) || (size > __BUDDY_SIZE_OF_HEAP__)) {\n        errno = EINVAL;\n        return NULL;\n    }\n\n    // we replace the size by the smallest 2 to the power of X such as it is greater than or equals the size\n    // afterwards, we take X as power_of_2 and thereby find the correct level to search for free blocks:\n    // blocks_level = __BUDDY_MAX_POWER__ - power_of_2\n    // for example if we try to allocate a block of 64 bytes (64=2^6), blocks_level = __BUDDY_MAX_POWER__ - 6\n\n    unsigned int power_of_2 = next_power_of_2(size);\n    int blocks_level = __BUDDY_MAX_POWER__ - power_of_2;\n\n    // if the size is smaller than the minimal size of\n    // block divided by 2, then we can't allocate a block\n    // so small and we have to allocate the block of the\n    // minimal allowed size\n    if (blocks_level >= __BUDDY_NUMBER_OF_LEVELS__) {\n        blocks_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n    }\n\n    // we browse all levels until we find the smallest free block that is big enough to contain \"size\" bytes\n    for (int blocks_level_current = blocks_level; blocks_level_current >= 0; --blocks_level_current) {\n        // we initialise index_in_level as the biggest index permitted in level\n        unsigned int index_in_level = 1 << blocks_level_current;\n\n        // levels 0-4 are in the same bitfield,\n        // level 5 consists of a single bitfield\n        // all other levels consist of 1<<(#level - 5)\n        // bitfields\n        unsigned int initial_number_of_current_bitfield = 0;\n        unsigned int loaded_case_mask;\n\n        switch (blocks_level_current) {\n            default:\n                initial_number_of_current_bitfield = ((1 << blocks_level_current) >> 5) - 1;\n                loaded_case_mask = 0xFFFFFFFF;\n                break;\n            case 0:\n                loaded_case_mask = 0x40000000;\n                break;\n            case 1:\n                loaded_case_mask = 0x30000000;\n                break;\n            case 2:\n                loaded_case_mask = 0x0F000000;\n                break;\n            case 3:\n                loaded_case_mask = 0x00FF0000;\n                break;\n            case 4:\n                loaded_case_mask = 0x0000FFFF;\n                break;\n        }\n\n        for (int number_of_current_bitfield = initial_number_of_current_bitfield; number_of_current_bitfield >= 0;\n             --number_of_current_bitfield, index_in_level -= 32) {\n            // sizes of levels in __buddy_blocks is a geometric\n            // series and thereby we can easily calculate the\n            // number of bitfields that precede the current level\n            unsigned int real_index = (1 << blocks_level_current) >> 5;\n            // we load the bitfield\n            unsigned int *initial_loaded_case_address\n                = (unsigned int *)(__buddy_blocks + number_of_current_bitfield + real_index);\n            // if we are in the very first bitfield\n            // that contains first 5 levels, then we\n            // need to make sure that buddy_free will\n            // ignore the bits that represent blocks\n            // that don't belong to blocks_level_current\n            unsigned int loaded_case = *initial_loaded_case_address & loaded_case_mask;\n\n            // this formula gives the number of zeros\n            // before the first pair of free/allocated blocks\n            // present in the current bitfield. If it equals\n            // 32, then no such pair is present.\n            unsigned int lz_before_first_pair_tmp = ((loaded_case << 1) ^ loaded_case) & 0xAAAAAAAA;\n\n            if (lz_before_first_pair_tmp != 0) {\n                unsigned int lz_before_first_pair = count_leading_zeros(lz_before_first_pair_tmp);\n                index_in_level = index_in_level - lz_before_first_pair - 1;\n\n                // if we are in the very first bitfield,\n                // then we need to take into account the special\n                // positioning of the 5 levels of blocks\n                // inside this bitfield\n                if (blocks_level_current < 5) {\n                    index_in_level += 1 << blocks_level_current;\n                }\n\n                unsigned int highlight_target_bit = 1 << index_in_level;\n\n                // if current level is among first 4\n                //(5th is unnecessary to consider)\n                // then we need to shift the mask\n                if (blocks_level_current < 4) {\n                    // we want to find the value of the offset to shift the mask for target and its buddy\n                    // offset = 32 - 2^(current_lvl+1)\n                    highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                }\n\n                // we have the position of a pair of\n                // free/allocated blocks, but we might\n                // need to shift this position by 1\n                // if the target's buddy is the potential\n                // block to allocate\n                loaded_case = loaded_case & highlight_target_bit;\n\n                if (loaded_case == 0) {\n                    highlight_target_bit = highlight_target_bit >> 1;\n                    index_in_level--;\n                }\n\n                // loaded_case have been modified if the first bitfield is handled\n                loaded_case = *initial_loaded_case_address;\n\n                // we mark the target bit as allocated\n                loaded_case -= highlight_target_bit;\n                *initial_loaded_case_address = loaded_case;\n\n                // if we have already had a free block of the necessary size,\n                // we return its address, otherwise we jump to\n                //__buddy_alloc_break_loop and start cutting the blocks\n                // in half until we get a block of the required size\n                if (blocks_level == blocks_level_current) {\n                    return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n                }\n\n                // we have already set the block to 0 [partially allocated]\n                // so we descend and start with the next one\n                blocks_level_current++;\n\n                while (blocks_level_current <= blocks_level) {\n                    index_in_level = index_in_level << 1;\n                    highlight_target_bit = 1 << index_in_level;\n\n                    // first 5 levels are stored in the same\n                    // bitfield. We need to handle this\n                    // special case and shift the mask\n                    int blocks_level_clamped = blocks_level_current - 4;\n\n                    if (blocks_level_clamped < 0) {\n                        highlight_target_bit = highlight_target_bit << (32 - (2 << blocks_level_current));\n                    }\n\n                    // we load the bitfield\n\n                    // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n                    unsigned int real_index = 0;\n                    blocks_level_clamped--;\n                    if (blocks_level_clamped >= 0) {\n                        real_index = 1 << blocks_level_clamped;\n                        blocks_level_clamped = index_in_level >> 5;\n                        real_index += blocks_level_clamped;\n                    }\n                    loaded_case = __buddy_blocks[real_index];\n\n                    // we mark the bit as allocated\n                    __buddy_blocks[real_index] = loaded_case - highlight_target_bit;\n\n                    // we continue to descend\n                    blocks_level_current++;\n                }\n\n                return __buddy_heap_start + (index_in_level << (__BUDDY_MAX_POWER__ - blocks_level));\n            }\n        }\n    }\n\n    // if no level contains a big enough block, we return NULL\n    errno = ENOMEM;\n    return NULL;\n}\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nint\nbuddy_search_for_pointer(void *pointer, buddy_search_context_t context)\n{\n    // if the pointer is not aligned to 64 bits, then it is corrupted\n    // if the pointer is outside of the heap, we can do nothing\n    if (((((unsigned int)pointer) & 7) != 0) || (pointer < __buddy_heap_start)\n        || (pointer > (__buddy_heap_start + __BUDDY_SIZE_OF_HEAP__ - 1))) {\n        errno = EINVAL;\n        return -1;\n    }\n\n    // we transform the real address into an index for __buddy_blocks\n    // index_in_level = (pointer - START_OF_HEAP)>>__BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    unsigned int index_in_level = (pointer - __buddy_heap_start) >> __BUDDY_SHIFT_ADDRESS_TO_INDEX__;\n    // we start to search for the pointer from the lowest level\n    unsigned int target_level = __BUDDY_NUMBER_OF_LEVELS__ - 1;\n\n    while (true) {\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        unsigned int highlight_target_bit = 1 << index_in_level;\n        unsigned int highlight_buddy_bit;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the\n        // same bitfield. We need to handle\n        // this special case and shift\n        // the masks\n        int target_level_clamped = target_level - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << target_level);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding to the index\n        // in __buddy_blocks\n        // real_index is the offset in 32-bit words from the first bitfield in __buddy_blocks\n        unsigned int real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index_in_level >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        unsigned int loaded_case = __buddy_blocks[real_index];\n\n        // We search for an allocated block\n        // if we are on the highest level, we quit.\n        if (((loaded_case & highlight_target_bit) == 0) || (target_level <= 0)) {\n            context->target_level = target_level;\n            context->real_index = real_index;\n            context->highlight_target_bit = highlight_target_bit;\n            context->highlight_buddy_bit = highlight_buddy_bit;\n            return index_in_level;\n        }\n\n        // Condition required to avoid unwanted release\n        if ((loaded_case & highlight_buddy_bit) == 0) {\n            errno = EINVAL;\n            return -1;\n        }\n\n        // we rise to the higher level\n        index_in_level = index_in_level >> 1;\n        target_level--;\n    }\n}\n\nstatic void\nbuddy_free_fusion_of_blocks(unsigned int index, buddy_search_context_t context)\n{\n    unsigned int real_index = context->real_index;\n    unsigned int current_level_freeing = context->target_level;\n    unsigned int highlight_target_bit = context->highlight_target_bit;\n    unsigned int highlight_buddy_bit = context->highlight_buddy_bit;\n    unsigned int loaded_case = __buddy_blocks[real_index];\n    // if we are at the highest level, there is nothing to fuse\n    while (current_level_freeing > 0) {\n        // fusion occurs only when both blocks are free\n        if (((loaded_case & highlight_target_bit) == 0) | ((loaded_case & highlight_buddy_bit) == 0)) {\n            return;\n        }\n\n        // index of predecessor = index of successor >> 1\n        index = index >> 1;\n        // we rise to the higher level\n        current_level_freeing--;\n\n        // knowing the index_in_level we can calculate\n        // highlight_target_bit and highlight_buddy_bit\n        highlight_target_bit = 1 << index;\n\n        if ((count_leading_zeros(highlight_target_bit) & 1) == 0) {\n            highlight_buddy_bit = highlight_target_bit >> 1;\n        } else {\n            highlight_buddy_bit = highlight_target_bit << 1;\n        }\n\n        // first 5 levels are stored in the same bitfield.\n        // We need to handle this special case and shift\n        // the masks\n        int target_level_clamped = current_level_freeing - 4;\n\n        if (target_level_clamped < 0) {\n            // we want to find the value of the offset to shift the mask for target and its buddy\n            // offset = 32 - 2^(current_lvl+1)\n            unsigned int offset = 32 - (2 << current_level_freeing);\n\n            highlight_buddy_bit = highlight_buddy_bit << offset;\n            highlight_target_bit = highlight_target_bit << offset;\n        }\n\n        // we load a bitfield corresponding\n        // to the index in __buddy_blocks\n        //\n        // As both sub-blocks were freed, their \"father\"\n        // must be marked as free.\n        real_index = 0;\n        target_level_clamped--;\n\n        if (target_level_clamped >= 0) {\n            real_index = (1 << target_level_clamped);\n            target_level_clamped = index >> 5;\n            real_index = real_index + target_level_clamped;\n        }\n\n        loaded_case = __buddy_blocks[real_index] | highlight_target_bit;\n        __buddy_blocks[real_index] = loaded_case;\n    }\n}\n\nvoid\nsafe_buddy_free(void *pointer)\n{\n    struct _buddy_search_context_t context;\n\n    int index = buddy_search_for_pointer(pointer, &context);\n\n    if (index != -1) {\n        __buddy_blocks[context.real_index] |= context.highlight_target_bit;\n        buddy_free_fusion_of_blocks(index, &context);\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline *\nbuddy_alloc(size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = safe_buddy_alloc(size);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_free(void *pointer)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    safe_buddy_free(pointer);\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n\n/*if the size of the smallest block needs to be changed, then only 2 things need to change :\n *  __BUDDY_DEPTH_LEVELS__ here in buddy_init.c\n *  __BUDDY_SHIFT_ADDRESS_TO_INDEX__ in buddy_defs.s\n *\n *  When the minimal size of a block needs to be 32 bytes, then these two constants must equal 4 and 5 correspondingly\n *  If minimal size needs to be 16 bytes, then these two constants must equal 3 and 4 correspondingly\n *  If minimal size needs to be 8 bytes, then these two constants must equal 2 and 3 correspondingly\n *\n *  Also, certain tests (Global, Reset, LevelByLevel) should also be changed.\n */\n\n// TODO: Right now the size must be of power of 2 : 2048, 4096, 8192 and it won't work with other sizes.\n// TODO: There is no point in accepting other sizes, as the whole idea of having buddy allocation is based on it.\n// TODO: Right now the possibility of failure of mem_alloc is not taken into account of.\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_init(size_t size_of_heap)\n{\n    if (__buddy_init_done == 0) {\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n\n        __BUDDY_SIZE_OF_HEAP__ = size_of_heap;\n\n        unsigned int power_of_2 = count_leading_zeros(size_of_heap);\n        __BUDDY_MAX_POWER__ = (31 - power_of_2);\n\n        __BUDDY_NUMBER_OF_LEVELS__ = __BUDDY_MAX_POWER__ - __BUDDY_DEPTH_LEVELS__;\n\n        unsigned int blocks_in_buddy_blocks = (1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2;\n        __buddy_blocks = mem_alloc(size_of_heap + blocks_in_buddy_blocks);\n\n        __buddy_heap_start = __buddy_blocks + (blocks_in_buddy_blocks >> 2);\n\n        __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n        memset(&__buddy_blocks[1], 0xff, blocks_in_buddy_blocks - 4); // in order to initialize the __buddy_blocks structure\n        __buddy_init_done = 1;\n    }\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nbuddy_reset()\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n\n    __buddy_blocks[0] = 0x7fffffff; // all bits except for the very first one must be set to 1\n    memset(&__buddy_blocks[1],\n        0xff,\n        ((1 << (__BUDDY_NUMBER_OF_LEVELS__ - 5)) << 2) - 4); // in order to initialize the __buddy_blocks structure\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/buddy_alloc.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_BUDDY_ALLOC_H\n#define DPUSYSCORE_BUDDY_ALLOC_H\n\n/**\n * @file buddy_alloc.h\n * @brief Dynamic memory allocation and freeing.\n *\n * This library allows to create unique memory space in the heap to allocate and free\n * blocks of data.\n *\n * The memory space is initialized with <code>buddy_init</code>, which must be invoked only once during\n * the program's lifecycle.\n *\n * Functions can then dynamically get and free buffers, using <code>buddy_alloc</code> and <code>buddy_free</code>\n * respectively.\n *\n * In this implementation, the allocatable buffer size is chosen during the first call to <code>buddy_init</code>.\n * Tested sizes : 2048, 4096, 8192, 16384 and 32768 bytes\n * The allocated buffers are properly aligned on DMA transfer constraints, so that they can be\n * used as is in MRAM/WRAM transfer operations.\n */\n\n/*\n * @internal The algorithm used in this implementation is Buddy memory allocation.\n *\n * A particularity of this implementation is that no headers are created and thereby\n * the memory consumption of the heap is reduced. The drawback is a slight slow-down\n * in speed of memory freeing.\n *\n * Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free. If the pointer given in the parameter\n *   is not currently allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>, <code>buddy_free</code>\n *   will do nothing.\n *\n */\n\n#include <stddef.h>\n\n/**\n * @fn buddy_init\n * @brief Allocates size_of_heap bytes for a heap that <code>buddy_alloc</code> can access to.\n *\n * Reserves memory space in the heap used to perform dynamic allocation and release of buffers.\n *\n * @param size_of_heap the size of heap in bytes that <code>buddy_alloc</code> can access to\n */\nvoid\nbuddy_init(size_t size_of_heap);\n\n/**\n * @fn buddy_reset\n * @brief Resets the heap.\n *\n * Quickly frees all pointers allocated by <code>buddy_alloc</code> or <code>buddy_realloc</code>.\n * Warning : currently buddy_reset() doesn't reset the size of the allocated heap.\n */\nvoid\nbuddy_reset(void);\n\n/**\n * @fn buddy_alloc\n * @brief Allocates a buffer of the given size in the heap, in a runtime-safe way.\n *\n * The allocated buffer is aligned on 64 bits, in order to ensure compatibility\n * with the maximum buffer alignment constraint. As a consequence, a buffer\n * allocated with this function is also compatible with data transfers to/from MRAM.\n *\n * Due to the idea of the buddy algorithm (to decrease external fragmentation),\n * the allocated blocks will be of size equal to a power of 2. In other words,\n * if the user allocates 33 bytes, 64 bytes will be allocated and when 2049 bytes\n * are requested, 4096 will be allocated. The user might want to take this into\n * account if she/he wishes to minimise the memory consumption.\n *\n * The minimal size of the allocated block is 16 bytes, but can easily be changed in\n * future implementations, so <code>buddy_alloc</code> is mostly adapted to allocating medium and\n * big structures, such as arrays containing more than 8 bytes (in order to make sure\n * that not too much memory space is wasted), binary trees or linked lists.\n *\n * If the <code>size</code> passed in parameter is less or equal to 0 or greater than the size of heap,\n * errno will be set to EINVAL and <code>buddy_alloc</code> will do nothing.\n * If <code>buddy_alloc</code> fails to find enough free memory space to allocate, errno will be\n * set to ENOMEM.\n *\n * @param size the allocated buffer's size, in bytes\n * @return A pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_alloc(size_t size);\n\n/**\n * @fn buddy_free\n * @brief Frees a specified pointer, in a runtime-safe way.\n *\n *  Warning :\n *   Due to the particularities of the implementation (lack of headers), <code>buddy_free</code>\n *   will always try to find a pointer to free and will see a pointer to the beginning of the\n *   block in the same way as the pointer to anywhere inside the block. For example, if we have\n *   allocated an int array[10], <code>buddy_free</code> will treat &array[0] the same way as &array[1]\n *   or as the address of any other element inside this array and will free the whole block.\n *\n * If the pointer given in the parameter is not currently allocated by <code>buddy_alloc</code> or\n * <code>buddy_realloc</code>, <code>buddy_free</code> will do nothing.\n *\n * This function frees the memory space pointed to by pointer, which\n * must have been returned by a previous call to <code>buddy_alloc</code> or <code>buddy_realloc</code>\n * If it wasn't or if <code>buddy_free</code> has already been called for this pointer before,\n * then <code>buddy_free</code> will do nothing. If pointer is NULL, no operation is performed.\n * If the pointer passed as a parameter is not aligned to 64 bits or if it is outside\n * of the allocated heap errno will be set to EINVAL.\n * If <code>buddy_free</code> detects the attempt to free a non-allocated pointer, it will equally\n * set errno to EINVAL.\n *\n * @param pointer the pointer to the block to free\n */\nvoid\nbuddy_free(void *pointer);\n\n/**\n * @fn buddy_realloc\n * @brief Changes the size of the memory block pointed to by <code>ptr</code> to <code>size</code> bytes in a runtime-safe way.\n *\n * The contents will be unchanged in the range from the start of the region up to the minimum of the old and new sizes.\n * If the new <code>size</code> is larger than the old size, the added memory will not be initialized.\n * If <code>ptr</code> is NULL, then the call is equivalent to <code>buddy_alloc(size)</code> for all values of <code>size</code>.\n * If <code>size</code> is equal to zero, and <code>ptr</code> is not NULL, then the call is equivalent to\n * <code>buddy_free(ptr)</code> and the return value will be equal to the pointer passed as the parameter. Unless <code>ptr</code>\n * is NULL, it should have been returned by an earlier call to <code>buddy_alloc()</code> or <code>buddy_realloc()</code>. If it\n * wasn't, then <code>buddy_realloc()</code> will try to find this pointer among the allocated ones, but undefined behavior might\n * occur.\n *\n * If new <code>size</code> is smaller than the old size, then the remaining memory will potentially be released (depends\n * on the size of block).\n *\n * <code>buddy_realloc()</code> internally calls <code>buddy_alloc</code> and <code>buddy_free</code> and thereby will set errno\n * to ENOMEM or EINVAL on failure.\n *\n * @param ptr original pointer\n * @param size the new allocated buffer's size, in bytes\n * @return A new (or the same) pointer to the allocated buffer if one was available, NULL otherwise.\n */\nvoid *\nbuddy_realloc(void *ptr, size_t size);\n\n#endif /* DPUSYSCORE_BUDDY_ALLOC_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/buddy_realloc.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n// todo integrate in buddy_alloc.c, when we have reduced the buddy_alloc object file size\n\n#include <buddy_alloc.h>\n#include <stddef.h>\n#include <alloc.h>\n#include <string.h> //for memcpy\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <attributes.h>\n\nATOMIC_BIT_EXTERN(__buddy_lock);\n\ntypedef struct _buddy_search_context_t {\n    unsigned int target_level;\n    unsigned int real_index;\n    unsigned int highlight_target_bit;\n    unsigned int highlight_buddy_bit;\n} * buddy_search_context_t;\n\nextern void *\nsafe_buddy_alloc(size_t size);\nextern void\nsafe_buddy_free(void *ptr);\nextern int\nbuddy_search_for_pointer(void *ptr, buddy_search_context_t context);\n\nstatic int\nbuddy_sizeofblock(void *pointer)\n{\n    // We get the pointer (address) as the parameter and look for any allocated block that starts at this address.\n    // If it is allocated, it will be found and its size will be returned.\n    // If it is currently non allocated, buddy_sizeofblock will do nothing.\n    struct _buddy_search_context_t dummy;\n    int index = buddy_search_for_pointer(pointer, &dummy);\n\n    if (index == -1) {\n        return -1;\n    }\n\n    return 1 << (12 - index);\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nbuddy_realloc(void *ptr, size_t size)\n{\n    ATOMIC_BIT_ACQUIRE(__buddy_lock);\n    void *result = ptr;\n    if (ptr == NULL) { // if ptr == NULL, then buddy_realloc must behave as buddy_alloc\n        result = safe_buddy_alloc(size);\n        ATOMIC_BIT_RELEASE(__buddy_lock);\n        return result; //\n    }\n\n    if (size == 0) { // if size == 0 and ptr != NULL, then buddy_realloc behaves as buddy_free\n        safe_buddy_free(ptr); //\n        ATOMIC_BIT_RELEASE(__buddy_lock); //\n        return ptr; //\n    }\n\n    size_t size_block = buddy_sizeofblock(ptr);\n\n    if (size_block == ((size_t)-1)) { // size_block is set to -1 if ptr was not found among\n        ATOMIC_BIT_RELEASE(__buddy_lock); // allocated pointers and that there is nothing to do\n        return NULL;\n    }\n\n    if (size <= (size_block >> 1)) { // if newly allocated block is smaller than the currently allocated block\n        size_block = size; // we will only copy \"size\" bytes\n    } else if (size <= size_block) { // if newly allocated block is of the same size as the currently allocated block\n        ATOMIC_BIT_RELEASE(__buddy_lock); // then there is no reason to do anything\n        return ptr;\n    }\n\n    safe_buddy_free(ptr); // newly allocated block is either bigger or smaller than the currently allocated\n    result = safe_buddy_alloc(size); // block and we need to call buddy_alloc to be sure that external fragmentation\n    memcpy(result, ptr, size_block); // is avoided.\n\n    ATOMIC_BIT_RELEASE(__buddy_lock);\n    return result;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/built_ins.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef BUILT_INS_H\n#define BUILT_INS_H\n\n/**\n * @file built_ins.h\n * @brief Provides access to the built-in functions\n *\n * Automatically generated by the DPU assembler\n */\n\n#define __builtin_nor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rri(rc, ra, shift) __asm__(\"lsr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_zri(zero, ra, shift) __asm__(\"lsr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_zrr(zero, ra, rb) __asm__(\"lsr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_boot_rici(ra, imm, boot_cc, pc) __asm__(\"boot %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_erii(endian, ra, off, imm) __asm__(\"sb \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sb \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sb_esii(endian, sa, off, imm) __asm__(\"sb \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsl_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rri(rc, ra, shift) __asm__(\"lsl %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_zri(zero, ra, shift) __asm__(\"lsl %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"lsl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_zrr(zero, ra, rb) __asm__(\"lsl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sw_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_erii(endian, ra, off, imm) __asm__(\"sw \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sw \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sw_esii(endian, sa, off, imm) __asm__(\"sw \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_asr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rri(rc, ra, imm) __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zri(zero, rb, imm) __asm__(\"addc %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrici(rc, ra, imm, add_nz_cc, pc)                                                                         \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrici(zero, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                          \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"addc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_addc_zrr(zero, ra, rb) __asm__(\"addc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_u_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_u_rr(dc, rb) __asm__(\"time_cfg.u %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_s_rci(dc, true_cc, pc) __asm__(\"time.s %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_s_r(dc) __asm__(\"time.s %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_call_rri(rc, ra, off) __asm__(\"call %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_zri(zero, ra, off) __asm__(\"call %[zero], %[ra_r32], \" off \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_call_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"call %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_call_zrr(zero, ra, rb) __asm__(\"call %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_zri(zero, ra, shift) __asm__(\"lsl1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsl1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_zrr(zero, ra, rb) __asm__(\"lsl1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_stop_ci(boot_cc, pc) __asm__(\"stop \" boot_cc \", \" pc \"\" :::)\n\n#define __builtin_ldmai_rri(ra, rb, immDma)                                                                                      \\\n    __asm__(\"ldmai %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_cfg_rrci(rc, rb, true_cc, pc)                                                                             \\\n    __asm__(\"time_cfg %[rc_wr32], %[rb_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zrci(zero, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg %[zero], %[rb_wr32], \" true_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_rr(rc, rb) __asm__(\"time_cfg %[rc_wr32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_zr(zero, rb) __asm__(\"time_cfg %[zero], %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rri(rc, ra, imm) __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zri(zero, rb, imm) __asm__(\"or %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrici(rc, ra, imm, log_nz_cc, pc)                                                                           \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrici(zero, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rric(rc, ra, imm, log_set_cc)                                                                               \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zric(zero, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrif(rc, ra, imm, false_cc)                                                                                 \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_zrif(zero, ra, imm, false_cc) __asm__(\"or %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                            \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrrc(rc, ra, rb, log_set_cc)                                                                                \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrrc(zero, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_rrr(rc, ra, rb)                                                                                             \\\n    __asm__(\"or %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_zrr(zero, ra, rb) __asm__(\"or %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cao_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_u_rr(dc, ra) __asm__(\"cao.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_zri(zero, ra, shift) __asm__(\"lsrx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsrx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_zrr(zero, ra, rb) __asm__(\"lsrx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_u_rr(dc, ra) __asm__(\"cls.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_sl_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sl %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sd_erir(endian, ra, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[ra_r32], \" off \", %[db_wr64]\" ::[ra_r32] \"r\"(ra), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_erii(endian, ra, off, imm) __asm__(\"sd \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sd_esir(endian, sa, off, db)                                                                                   \\\n    __asm__(\"sd \" endian \", %[sa_r32], \" off \", %[db_wr64]\" ::[sa_r32] \"r\"(sa), [db_wr64] \"r\"(db) :)\n\n#define __builtin_sd_esii(endian, sa, off, imm) __asm__(\"sd \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lsrx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sdma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"sdma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lhs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_zri(zero, ra, shift) __asm__(\"lsr1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsr1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1x_zrr(zero, ra, rb) __asm__(\"lsr1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_ul_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_ul_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_ul.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbu_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbu_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbu \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_time_u_rci(dc, true_cc, pc) __asm__(\"time.u %[dc_wr64], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_time_u_r(dc) __asm__(\"time.u %[dc_wr64]\" : [dc_wr64] \"=r\"(dc)::)\n\n#define __builtin_subc_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_s_rr(dc, ra) __asm__(\"clo.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_ul_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_ul_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_ul_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"cmpb4 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_zrr(zero, ra, rb) __asm__(\"cmpb4 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"hash %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_hash_zrr(zero, ra, rb) __asm__(\"hash %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rir(rc, imm, ra) __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zir(zero, imm, rb) __asm__(\"sub %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirc(rc, imm, ra, sub_set_cc)                                                                              \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirc(zero, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rirf(rc, imm, ra, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zirf(zero, imm, ra, false_cc) __asm__(\"sub %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rric(rc, ra, imm, ext_sub_set_cc)                                                                          \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zric(zero, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_zrif(zero, ra, imm, false_cc) __asm__(\"sub %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_ssi(sc, sa, imm) __asm__(\"sub %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_sub_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"sub %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_sub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                           \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                          \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"sub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sub_zrr(zero, ra, rb) __asm__(\"sub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsb_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsb %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zrc(zero, ra, log_set_cc) __asm__(\"extsb %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_rr(rc, ra) __asm__(\"extsb %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_zr(zero, ra) __asm__(\"extsb %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_movd_rrci(dc, db, true_false_cc, pc)                                                                           \\\n    __asm__(\"movd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_lsl1x_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rric(rc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zric(zero, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rri(rc, ra, shift)                                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_zri(zero, ra, shift) __asm__(\"lsl1x %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrrc(rc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_zrrc(zero, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"lsl1x %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_zrr(zero, ra, rb) __asm__(\"lsl1x %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_s_rr(dc, ra) __asm__(\"sats.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_s_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rri(rc, ra, imm) __asm__(\"and %[rc_wr32], %[ra_wr32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_wr32] \"r\"(ra) :)\n\n#define __builtin_and_zri(zero, rb, imm) __asm__(\"and %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_zrif(zero, ra, imm, false_cc) __asm__(\"and %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"and %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_zrr(zero, ra, rb) __asm__(\"and %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cls_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cls %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zrc(zero, ra, log_set_cc) __asm__(\"cls %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_rr(rc, ra) __asm__(\"cls %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_zr(zero, ra) __asm__(\"cls %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrrc(rc, ra, rb, sub_set_cc)                                                                              \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrrc(zero, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"rsub %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsub_zrr(zero, ra, rb) __asm__(\"rsub %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_div_step_rrrici(dc, ra, db, shift, div_cc, pc)                                                                 \\\n    __asm__(\"div_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" div_cc \", \" pc \"\"                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_rol_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rri(rc, ra, shift) __asm__(\"rol %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_zri(zero, ra, shift) __asm__(\"rol %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"rol %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_zrr(zero, ra, rb) __asm__(\"rol %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_swapd_rrci(dc, db, true_false_cc, pc)                                                                          \\\n    __asm__(\"swapd %[dc_wr64], %[db_wr64], \" true_false_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [db_wr64] \"r\"(db) :)\n\n#define __builtin_add_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nand %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_zrr(zero, ra, rb) __asm__(\"nand %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_s_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbs.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"lsl.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_s_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.s \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sb_id_erii(endian, ra, off, imm) __asm__(\"sb_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rki(dc, ra, imm) __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nop_() __asm__(\"nop \" :::)\n\n#define __builtin_sd_id_erii(endian, ra, off, imm) __asm__(\"sd_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_id_erii(endian, ra, off, imm) __asm__(\"sh_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsr1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extsh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zrc(zero, ra, log_set_cc) __asm__(\"extsh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_rr(rc, ra) __asm__(\"extsh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_zr(zero, ra) __asm__(\"extsh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_acquire_rici(ra, imm, acquire_cc, pc)                                                                          \\\n    __asm__(\"acquire %[ra_r32], \" imm \", \" acquire_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rri(rc, ra, imm) __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zri(zero, rb, imm) __asm__(\"xor %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_zrif(zero, ra, imm, false_cc) __asm__(\"xor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"xor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_zrr(zero, ra, rb) __asm__(\"xor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsrx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsrx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsrx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsrx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_zri(zero, ra, shift) __asm__(\"lslx %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lslx %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_zrr(zero, ra, rb) __asm__(\"lslx %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"asr.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"nor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirc(dc, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rirf(dc, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                       \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"subc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"nxor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_zrr(zero, ra, rb) __asm__(\"nxor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_xor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_xor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_xor_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"xor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clo.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_u_rr(dc, ra) __asm__(\"clo.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_s_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extsh_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsh.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsh_s_rr(dc, ra) __asm__(\"extsh.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_cmpb4_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                       \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_cmpb4_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"cmpb4.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1x_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_s_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsl_sub %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl_sub_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rri(rc, ra, shift) __asm__(\"ror %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_zri(zero, ra, shift) __asm__(\"ror %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"ror %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ror_zrr(zero, ra, rb) __asm__(\"ror %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_fault_i(imm) __asm__(\"fault \" imm \"\" :::)\n\n#define __builtin_clz_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_s_rr(dc, ra) __asm__(\"clz.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirci(dc, imm, ra, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirc(dc, imm, ra, sub_set_cc)                                                                            \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rirf(dc, imm, ra, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], \" imm \", %[ra_r32], \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrici(dc, ra, imm, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rric(dc, ra, imm, ext_sub_set_cc)                                                                        \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrrc(dc, ra, rb, ext_sub_set_cc)                                                                         \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                        \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_sub_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"sub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_uh_uh_u_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_uh_uh_u_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_uh_uh.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sl_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sl_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sl.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rri(dc, rb, imm) __asm__(\"or.s %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_s_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_s_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sats_rrci(rc, ra, log_nz_cc, pc)                                                                               \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrci(zero, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rrc(rc, ra, log_set_cc)                                                                                   \\\n    __asm__(\"sats %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zrc(zero, ra, log_set_cc) __asm__(\"sats %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_rr(rc, ra) __asm__(\"sats %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_zr(zero, ra) __asm__(\"sats %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rsub_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrrc(dc, ra, rb, sub_set_cc)                                                                            \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsub_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"rsub.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_erri(endian, rc, ra, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lw_ersi(endian, rc, sa, off)                                                                                   \\\n    __asm__(\"lw \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extsb_s_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extsb.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extsb_s_rr(dc, ra) __asm__(\"extsb.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ror_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_ror_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"ror.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_ul_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_ul_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_ul %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rrci(dc, rb, true_cc, pc)                                                                           \\\n    __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32], \" true_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_time_cfg_s_rr(dc, rb) __asm__(\"time_cfg.s %[dc_wr64], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_ul_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_ul_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_ul.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_u_rrrci(dc, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrrc(dc, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"rsubc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"rol_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"cao %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zrc(zero, ra, log_set_cc) __asm__(\"cao %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_rr(rc, ra) __asm__(\"cao %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_zr(zero, ra) __asm__(\"cao %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extuh %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zrc(zero, ra, log_set_cc) __asm__(\"extuh %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_rr(rc, ra) __asm__(\"extuh %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_zr(zero, ra) __asm__(\"extuh %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsl1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"orn.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lw_u_erri(endian, dc, ra, off)                                                                                 \\\n    __asm__(\"lw.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sl_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lslx_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lslx_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lslx_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lslx.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nand_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rric(dc, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rri(dc, ra, shift)                                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                  \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"lsr1.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rki(dc, ra, imm) __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_and_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_and_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_and_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"and.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_zrif(zero, ra, imm, false_cc) __asm__(\"orn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_orn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_orn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"orn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_orn_zrr(zero, ra, rb) __asm__(\"orn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clo_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clo %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clo %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zrc(zero, ra, log_set_cc) __asm__(\"clo %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_rr(rc, ra) __asm__(\"clo %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clo_zr(zero, ra) __asm__(\"clo %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rric(dc, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rri(dc, ra, shift)                                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_rol_s_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                   \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rol_s_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"rol.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_sh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rol_add_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_rol_add_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"rol_add.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrrici(rc, rb, ra, shift, div_nz_cc, pc)                                                               \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_zrrici(zero, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_rrri(rc, rb, ra, shift)                                                                                \\\n    __asm__(\"lsr_add %[rc_wr32], %[rb_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr_add_zrri(zero, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add %[zero], %[rb_wr32], %[ra_r32], \" shift \"\" ::[rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_hash_s_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_hash_s_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"hash.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_extub_rrci(rc, ra, log_nz_cc, pc)                                                                              \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrci(zero, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub %[zero], %[ra_r32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rrc(rc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"extub %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zrc(zero, ra, log_set_cc) __asm__(\"extub %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_rr(rc, ra) __asm__(\"extub %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_zr(zero, ra) __asm__(\"extub %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sw_id_erii(endian, ra, off, imm) __asm__(\"sw_id \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_time_rci(rc, true_cc, pc) __asm__(\"time %[rc_wr32], \" true_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_zci(zero, true_cc, pc) __asm__(\"time %[zero], \" true_cc \", \" pc \"\" :::)\n\n#define __builtin_time_r(rc) __asm__(\"time %[rc_wr32]\" : [rc_wr32] \"=r\"(rc)::)\n\n#define __builtin_time_z(zero) __asm__(\"time %[zero]\" :::)\n\n#define __builtin_asr_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                  \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                                \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rric(rc, ra, shift, log_set_cc)                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zric(zero, ra, shift, log_set_cc)                                                                          \\\n    __asm__(\"asr %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rri(rc, ra, shift) __asm__(\"asr %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_zri(zero, ra, shift) __asm__(\"asr %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_asr_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                         \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_asr_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                       \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"asr %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_asr_zrr(zero, ra, rb) __asm__(\"asr %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ldma_rri(ra, rb, immDma)                                                                                       \\\n    __asm__(\"ldma %[ra_r32], %[rb_wr32], \" immDma \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_ld_erri(endian, dc, ra, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_ld_ersi(endian, dc, sa, off)                                                                                   \\\n    __asm__(\"ld \" endian \", %[dc_wr64], %[sa_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cls_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cls.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cls_s_rr(dc, ra) __asm__(\"cls.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extuh.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extuh_u_rr(dc, ra) __asm__(\"extuh.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrci(dc, ra, log_nz_cc, pc)                                                                             \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rrc(dc, ra, log_set_cc)                                                                                 \\\n    __asm__(\"sats.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_sats_u_rr(dc, ra) __asm__(\"sats.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                       \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_addc_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                        \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_addc_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"addc.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"andn.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nxor_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nxor_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nxor_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nxor.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsl_sub_u_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsl_sub_u_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsl_sub.u %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrici(dc, ra, shift, imm_shift_nz_cc, pc)                                                              \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rric(dc, ra, shift, log_set_cc)                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rri(dc, ra, shift)                                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsl1x_u_rrrci(dc, ra, rb, shift_nz_cc, pc)                                                                     \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                 \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrrc(dc, ra, rb, log_set_cc)                                                                           \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                          \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsl1x_u_rrr(dc, ra, rb)                                                                                        \\\n    __asm__(\"lsl1x.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_resume_rici(ra, imm, boot_cc, pc) __asm__(\"resume %[ra_r32], \" imm \", \" boot_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lhs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_cao_s_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"cao.s %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_cao_s_rr(dc, ra) __asm__(\"cao.s %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrci(dc, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rrc(dc, ra, log_set_cc)                                                                                  \\\n    __asm__(\"clz.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_u_rr(dc, ra) __asm__(\"clz.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrici(rc, ra, shift, imm_shift_nz_cc, pc)                                                                 \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zrici(zero, ra, shift, imm_shift_nz_cc, pc)                                                               \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" imm_shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rric(rc, ra, shift, log_set_cc)                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zric(zero, ra, shift, log_set_cc)                                                                         \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rri(rc, ra, shift)                                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], \" shift \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_zri(zero, ra, shift) __asm__(\"lsr1 %[zero], %[ra_r32], \" shift \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_lsr1_rrrci(rc, ra, rb, shift_nz_cc, pc)                                                                        \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\"                                                    \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_lsr1_zrrci(zero, ra, rb, shift_nz_cc, pc)                                                                      \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" shift_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"lsr1 %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr1_zrr(zero, ra, rb) __asm__(\"lsr1 %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rri(dc, rb, imm)                                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_u_rrici(dc, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rric(dc, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrif(dc, ra, imm, false_cc)                                                                              \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_u_rrrci(dc, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                     \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrrc(dc, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                            \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_u_rrr(dc, ra, rb)                                                                                          \\\n    __asm__(\"add.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                     \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrrc(rc, ra, rb, sub_set_cc)                                                                             \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\"                                                            \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_rsubc_zrrc(zero, ra, rb, sub_set_cc)                                                                           \\\n    __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_rrr(rc, ra, rb)                                                                                          \\\n    __asm__(\"rsubc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_rsubc_zrr(zero, ra, rb) __asm__(\"rsubc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rri(rc, ra, imm) __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zri(zero, rb, imm) __asm__(\"add %[zero], %[rb_wr32], \" imm \"\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrici(rc, ra, imm, add_nz_cc, pc)                                                                          \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrici(zero, ra, imm, add_nz_cc, pc)                                                                        \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"add %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_zrif(zero, ra, imm, false_cc) __asm__(\"add %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_add_ssi(sc, sa, imm) __asm__(\"add %[sc_wr32], %[sa_r32], \" imm \"\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa) :)\n\n#define __builtin_add_rrrci(rc, ra, rb, add_nz_cc, pc)                                                                           \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_add_zrrci(zero, ra, rb, add_nz_cc, pc)                                                                         \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" add_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"add %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"add %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_zrr(zero, ra, rb) __asm__(\"add %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_add_sss(sc, sa, sb)                                                                                            \\\n    __asm__(\"add %[sc_wr32], %[sa_r32], %[sb_wr32]\" ::[sc_wr32] \"r\"(sc), [sa_r32] \"r\"(sa), [sb_wr32] \"r\"(sb) :)\n\n#define __builtin_nor_rrici(rc, ra, imm, log_nz_cc, pc)                                                                          \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrici(zero, ra, imm, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rric(rc, ra, imm, log_set_cc)                                                                              \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zric(zero, ra, imm, log_set_cc)                                                                            \\\n    __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrif(rc, ra, imm, false_cc)                                                                                \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_zrif(zero, ra, imm, false_cc) __asm__(\"nor %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_nor_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                           \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                       \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nor_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                         \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrrc(rc, ra, rb, log_set_cc)                                                                               \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrrc(zero, ra, rb, log_set_cc)                                                                             \\\n    __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_rrr(rc, ra, rb)                                                                                            \\\n    __asm__(\"nor %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_nor_zrr(zero, ra, rb) __asm__(\"nor %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rri(dc, rb, imm) __asm__(\"or.u %[dc_wr64], %[rb_wr32], \" imm \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rric(dc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrif(dc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_or_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_or_u_rrrc(dc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_or_u_rrr(dc, ra, rb)                                                                                           \\\n    __asm__(\"or.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rir(rc, imm, ra) __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zir(zero, imm, rb) __asm__(\"subc %[zero], \" imm \", %[rb_wr32]\" ::[rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rirci(rc, imm, ra, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirci(zero, imm, ra, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirc(rc, imm, ra, sub_set_cc)                                                                             \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirc(zero, imm, ra, sub_set_cc)                                                                           \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rirf(rc, imm, ra, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], \" imm \", %[ra_r32], \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zirf(zero, imm, ra, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], \" imm \", %[ra_r32], \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrici(rc, ra, imm, sub_nz_cc, pc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrici(zero, ra, imm, sub_nz_cc, pc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rric(rc, ra, imm, ext_sub_set_cc)                                                                         \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zric(zero, ra, imm, ext_sub_set_cc)                                                                       \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"subc %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_subc_rrrci(rc, ra, rb, sub_nz_cc, pc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrci(zero, ra, rb, sub_nz_cc, pc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" sub_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrrc(rc, ra, rb, ext_sub_set_cc)                                                                          \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\"                                                         \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_subc_zrrc(zero, ra, rb, ext_sub_set_cc)                                                                        \\\n    __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32], \" ext_sub_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"subc %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_subc_zrr(zero, ra, rb) __asm__(\"subc %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lbs_erri(endian, rc, ra, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[ra_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lbs_ersi(endian, rc, sa, off)                                                                                  \\\n    __asm__(\"lbs \" endian \", %[rc_wr32], %[sa_r32], \" off \"\" : [rc_wr32] \"=r\"(rc) : [sa_r32] \"r\"(sa) :)\n\n#define __builtin_extub_u_rrci(dc, ra, log_nz_cc, pc)                                                                            \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rrc(dc, ra, log_set_cc)                                                                                \\\n    __asm__(\"extub.u %[dc_wr64], %[ra_r32], \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_extub_u_rr(dc, ra) __asm__(\"extub.u %[dc_wr64], %[ra_r32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrici(dc, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rric(dc, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" log_set_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrif(dc, ra, imm, false_cc)                                                                             \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], \" imm \", \" false_cc \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_nand_u_rrrci(dc, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                    \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrrc(dc, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                           \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_nand_u_rrr(dc, ra, rb)                                                                                         \\\n    __asm__(\"nand.u %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrici(rc, ra, imm, log_nz_cc, pc)                                                                         \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrici(zero, ra, imm, log_nz_cc, pc)                                                                       \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rric(rc, ra, imm, log_set_cc)                                                                             \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zric(zero, ra, imm, log_set_cc)                                                                           \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrif(rc, ra, imm, false_cc)                                                                               \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], \" imm \", \" false_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_zrif(zero, ra, imm, false_cc)                                                                             \\\n    __asm__(\"andn %[zero], %[ra_r32], \" imm \", \" false_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_andn_rrrci(rc, ra, rb, log_nz_cc, pc)                                                                          \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\"                                                      \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_andn_zrrci(zero, ra, rb, log_nz_cc, pc)                                                                        \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrrc(rc, ra, rb, log_set_cc)                                                                              \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrrc(zero, ra, rb, log_set_cc)                                                                            \\\n    __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_rrr(rc, ra, rb)                                                                                           \\\n    __asm__(\"andn %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_andn_zrr(zero, ra, rb) __asm__(\"andn %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_release_rici(ra, imm, release_cc, pc)                                                                          \\\n    __asm__(\"release %[ra_r32], \" imm \", \" release_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_lsr_add_s_rrrici(dc, rb, ra, shift, div_nz_cc, pc)                                                             \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \", \" div_nz_cc \", \" pc \"\"                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra)                                                                                \\\n            :)\n\n#define __builtin_lsr_add_s_rrri(dc, rb, ra, shift)                                                                              \\\n    __asm__(\"lsr_add.s %[dc_wr64], %[rb_wr32], %[ra_r32], \" shift \"\" : [dc_wr64] \"=r\"(dc) : [rb_wr32] \"r\"(rb), [ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_sh_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrci(rc, ra, rb, mul_nz_cc, pc)                                                                     \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                                 \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrci(zero, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrrc(rc, ra, rb, log_set_cc)                                                                         \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                        \\\n            : [rc_wr32] \"=r\"(rc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sl_uh_zrrc(zero, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_rrr(rc, ra, rb)                                                                                      \\\n    __asm__(\"mul_sl_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sl_uh_zrr(zero, ra, rb)                                                                                    \\\n    __asm__(\"mul_sl_uh %[zero], %[ra_r32], %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_mul_sh_sh_s_rrrci(dc, ra, rb, mul_nz_cc, pc)                                                                   \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" mul_nz_cc \", \" pc \"\"                                               \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrrc(dc, ra, rb, log_set_cc)                                                                       \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32], \" log_set_cc \"\"                                                      \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb)                                                                                \\\n            :)\n\n#define __builtin_mul_sh_sh_s_rrr(dc, ra, rb)                                                                                    \\\n    __asm__(\"mul_sh_sh.s %[dc_wr64], %[ra_r32], %[rb_wr32]\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_clz_rrci(rc, ra, count_nz_cc, pc)                                                                              \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" count_nz_cc \", \" pc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrci(zero, ra, count_nz_cc, pc)                                                                            \\\n    __asm__(\"clz %[zero], %[ra_r32], \" count_nz_cc \", \" pc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rrc(rc, ra, log_set_cc)                                                                                    \\\n    __asm__(\"clz %[rc_wr32], %[ra_r32], \" log_set_cc \"\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zrc(zero, ra, log_set_cc) __asm__(\"clz %[zero], %[ra_r32], \" log_set_cc \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_rr(rc, ra) __asm__(\"clz %[rc_wr32], %[ra_r32]\" : [rc_wr32] \"=r\"(rc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_clz_zr(zero, ra) __asm__(\"clz %[zero], %[ra_r32]\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_mul_step_rrrici(dc, ra, db, shift, boot_cc, pc)                                                                \\\n    __asm__(\"mul_step %[dc_wr64], %[ra_r32], %[db_wr64], \" shift \", \" boot_cc \", \" pc \"\"                                         \\\n            : [dc_wr64] \"=r\"(dc)                                                                                                 \\\n            : [ra_r32] \"r\"(ra), [db_wr64] \"r\"(db)                                                                                \\\n            :)\n\n#define __builtin_sh_erir(endian, ra, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[ra_r32], \" off \", %[rb_wr32]\" ::[ra_r32] \"r\"(ra), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_erii(endian, ra, off, imm) __asm__(\"sh \" endian \", %[ra_r32], \" off \", \" imm \"\" ::[ra_r32] \"r\"(ra) :)\n\n#define __builtin_sh_esir(endian, sa, off, rb)                                                                                   \\\n    __asm__(\"sh \" endian \", %[sa_r32], \" off \", %[rb_wr32]\" ::[sa_r32] \"r\"(sa), [rb_wr32] \"r\"(rb) :)\n\n#define __builtin_sh_esii(endian, sa, off, imm) __asm__(\"sh \" endian \", %[sa_r32], \" off \", \" imm \"\" ::[sa_r32] \"r\"(sa) :)\n\n#define __builtin_lbu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lbu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#define __builtin_lhu_u_erri(endian, dc, ra, off)                                                                                \\\n    __asm__(\"lhu.u \" endian \", %[dc_wr64], %[ra_r32], \" off \"\" : [dc_wr64] \"=r\"(dc) : [ra_r32] \"r\"(ra) :)\n\n#endif /* BUILT_INS_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/clzdi2.c",
    "content": "/* ===-- clzdi2.c - Implement __clzdi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.high == 0);\n    return __builtin_clz((x.s.high & ~f) | (x.s.low & f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/clzsi2.c",
    "content": "/* ===-- clzsi2.c - Implement __clzsi2 -------------------------------------===\n *\n *               The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __clzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of leading 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__clzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0xFFFF0000) == 0) << 4; /* if (x is small) t = 16 else 0 */\n    x >>= 16 - t; /* x = [0 - 0xFFFF] */\n    su_int r = t; /* r = [0, 16] */\n    /* return r + clz(x) */\n    t = ((x & 0xFF00) == 0) << 3;\n    x >>= 8 - t; /* x = [0 - 0xFF] */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + clz(x) */\n    t = ((x & 0xF0) == 0) << 2;\n    x >>= 4 - t; /* x = [0 - 0xF] */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + clz(x) */\n    t = ((x & 0xC) == 0) << 1;\n    x >>= 2 - t; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + clz(x) */\n    /*     switch (x)\n     *     {\n     *     case 0:\n     *         return r + 2;\n     *     case 1:\n     *         return r + 1;\n     *     case 2:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - x) & -((x & 2) == 0));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/cmpdi2.c",
    "content": "/* ===-- cmpdi2.c - Implement __cmpdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __cmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__cmpdi2(di_int a, di_int b)\n{\n    dwords x;\n    x.all = a;\n    dwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_lcmp(di_int a, di_int b)\n{\n    return __cmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/comparedf2.c",
    "content": "//===-- lib/comparedf2.c - Double-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// // This file implements the following soft-float comparison routines:\n//\n//   __eqdf2   __gedf2   __unorddf2\n//   __ledf2   __gtdf2\n//   __ltdf2\n//   __nedf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __ledf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gedf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unorddf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __ledf2( ) and __gedf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ledf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a floating-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpdf2, __ledf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gedf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unorddf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltdf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nedf2(fp_t a, fp_t b)\n{\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtdf2(fp_t a, fp_t b)\n{\n    return __gedf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_dcmpun(fp_t a, fp_t b)\n{\n    return __unorddf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/comparesf2.c",
    "content": "//===-- lib/comparesf2.c - Single-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements the following soft-fp_t comparison routines:\n//\n//   __eqsf2   __gesf2   __unordsf2\n//   __lesf2   __gtsf2\n//   __ltsf2\n//   __nesf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __lesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unordsf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT { LE_LESS = -1, LE_EQUAL = 0, LE_GREATER = 1, LE_UNORDERED = 1 };\n\nCOMPILER_RT_ABI enum LE_RESULT\n__lesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep)\n        return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0)\n        return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a fp_ting-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt)\n            return LE_LESS;\n        else if (aInt == bInt)\n            return LE_EQUAL;\n        else\n            return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpsf2, __lesf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS = -1,\n    GE_EQUAL = 0,\n    GE_GREATER = 1,\n    GE_UNORDERED = -1 // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gesf2(fp_t a, fp_t b)\n{\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep)\n        return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0)\n        return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    } else {\n        if (aInt > bInt)\n            return GE_LESS;\n        else if (aInt == bInt)\n            return GE_EQUAL;\n        else\n            return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unordsf2(fp_t a, fp_t b)\n{\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltsf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nesf2(fp_t a, fp_t b)\n{\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtsf2(fp_t a, fp_t b)\n{\n    return __gesf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI int\n__aeabi_fcmpun(fp_t a, fp_t b)\n{\n    return __unordsf2(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ctzdi2.c",
    "content": "/* ===-- ctzdi2.c - Implement __ctzdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits  */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    const si_int f = -(x.s.low == 0);\n    return __builtin_ctz((x.s.high & f) | (x.s.low & ~f)) + (f & ((si_int)(sizeof(si_int) * CHAR_BIT)));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ctzsi2.c",
    "content": "/* ===-- ctzsi2.c - Implement __ctzsi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ctzsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the number of trailing 0-bits */\n\n/* Precondition: a != 0 */\n\nCOMPILER_RT_ABI si_int\n__ctzsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    si_int t = ((x & 0x0000FFFF) == 0) << 4; /* if (x has no small bits) t = 16 else 0 */\n    x >>= t; /* x = [0 - 0xFFFF] + higher garbage bits */\n    su_int r = t; /* r = [0, 16]  */\n    /* return r + ctz(x) */\n    t = ((x & 0x00FF) == 0) << 3;\n    x >>= t; /* x = [0 - 0xFF] + higher garbage bits */\n    r += t; /* r = [0, 8, 16, 24] */\n    /* return r + ctz(x) */\n    t = ((x & 0x0F) == 0) << 2;\n    x >>= t; /* x = [0 - 0xF] + higher garbage bits */\n    r += t; /* r = [0, 4, 8, 12, 16, 20, 24, 28] */\n    /* return r + ctz(x) */\n    t = ((x & 0x3) == 0) << 1;\n    x >>= t;\n    x &= 3; /* x = [0 - 3] */\n    r += t; /* r = [0 - 30] and is even */\n    /* return r + ctz(x) */\n\n    /*  The branch-less return statement below is equivalent\n     *  to the following switch statement:\n     *     switch (x)\n     *    {\n     *     case 0:\n     *         return r + 2;\n     *     case 2:\n     *         return r + 1;\n     *     case 1:\n     *     case 3:\n     *         return r;\n     *     }\n     */\n    return r + ((2 - (x >> 1)) & -((x & 1) == 0));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/defs.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <sysdef.h>\n#include <dpuruntime.h>\n\nint\ncheck_stack()\n{\n    unsigned int stack_base, stack_size;\n    int stack_limit, remaining;\n    thread_id_t tid = me();\n\n    stack_base = __SP_TABLE__[tid].stack_ptr;\n    stack_size = __SP_TABLE__[tid].stack_size;\n    stack_limit = (int)(stack_base + stack_size);\n    __asm__ volatile(\"sub %[r], %[l], r22\" : [r] \"=r\"(remaining) : [l] \"r\"(stack_limit));\n\n    return remaining;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/defs.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEFS_H\n#define DPUSYSCORE_DEFS_H\n\n#include <sysdef.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <attributes.h>\n\n/**\n * @file defs.h\n * @brief Miscellaneous system functions.\n *\n * General purpose definitions.\n */\n\n#if __STDC_VERSION__ >= 201112L\n#define __ATTRIBUTE_NO_RETURN__ _Noreturn\n#else\n#define __ATTRIBUTE_NO_RETURN__\n#endif /* __STDC_VERSION__ */\n\n/**\n * @fn me\n * @internal This just returns the value of the special register id.\n * @return The current tasklet's sysname.\n */\nstatic inline sysname_t\nme()\n{\n    return __builtin_dpu_tid();\n}\n\n/**\n * @fn halt\n * @brief Halts the DPU.\n * @throws FAULT_HALT always\n */\n__ATTRIBUTE_NO_RETURN__ static inline void\nhalt()\n{\n    __builtin_trap();\n    __builtin_unreachable();\n}\n\n/**\n * @fn check_stack\n * @return the number of unused 32-bits words in the current runtime's stack.\n *         If the number is negative, it indicates by how much 32-bits words the stack overflowed.\n *\n * @internal This fetches the position of the next stack in memory from the Stack Pointer Table (cf. tasklet.h)\n *           and compute the remaining bytes.\n */\nint\ncheck_stack();\n\n#endif /* DPUSYSCORE_DEFS_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/devprivate.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DEVPRIVATE_H\n#define DPUSYSCORE_DEVPRIVATE_H\n\n/**\n * @file devprivate.h\n * @brief Reserved for internal use ... please do not use those functions unless you know exactly what you do.\n */\n\n/**\n * @def tell\n * @brief On a simulator, injects a tell instruction to print out developer debug info.\n * @nolink\n *\n * @warning This function will not work on a target different from simulator.\n *\n * @param reg a register\n * @param val a constant value\n */\n#define tell(reg, val) __asm__(\"tell %[r], \" val : : [r] \"r\"(reg) :)\n\n#endif /* DPUSYSCORE_DEVPRIVATE_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/div32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __udiv32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"  clz r3, r1, max, __udiv32_division_by_zero\\n\" // r3 = by how many the divider can be shifted on 32-bit\n                     \"  clz r4, r0\\n\" // r4 = number of useless bits of the dividend\n                     \"  sub r3, r4, r3, gtu, __udiv32_result_0\\n\" // r3 = the maximal shift to be done\n                     \"  move r4, r1\\n\"\n                     \"  move.u d0, r0\\n\"\n                     \"  jump r3, __udiv32_base\\n\" // As we will jump backward relatively to __udiv32_base\n                     \"  div_step d0, r4, d0, 31\\n\"\n                     \"  div_step d0, r4, d0, 30\\n\"\n                     \"  div_step d0, r4, d0, 29\\n\"\n                     \"  div_step d0, r4, d0, 28\\n\"\n                     \"  div_step d0, r4, d0, 27\\n\"\n                     \"  div_step d0, r4, d0, 26\\n\"\n                     \"  div_step d0, r4, d0, 25\\n\"\n                     \"  div_step d0, r4, d0, 24\\n\"\n                     \"  div_step d0, r4, d0, 23\\n\"\n                     \"  div_step d0, r4, d0, 22\\n\"\n                     \"  div_step d0, r4, d0, 21\\n\"\n                     \"  div_step d0, r4, d0, 20\\n\"\n                     \"  div_step d0, r4, d0, 19\\n\"\n                     \"  div_step d0, r4, d0, 18\\n\"\n                     \"  div_step d0, r4, d0, 17\\n\"\n                     \"  div_step d0, r4, d0, 16\\n\"\n                     \"  div_step d0, r4, d0, 15\\n\"\n                     \"  div_step d0, r4, d0, 14\\n\"\n                     \"  div_step d0, r4, d0, 13\\n\"\n                     \"  div_step d0, r4, d0, 12\\n\"\n                     \"  div_step d0, r4, d0, 11\\n\"\n                     \"  div_step d0, r4, d0, 10\\n\"\n                     \"  div_step d0, r4, d0, 9\\n\"\n                     \"  div_step d0, r4, d0, 8\\n\"\n                     \"  div_step d0, r4, d0, 7\\n\"\n                     \"  div_step d0, r4, d0, 6\\n\"\n                     \"  div_step d0, r4, d0, 5\\n\"\n                     \"  div_step d0, r4, d0, 4\\n\"\n                     \"  div_step d0, r4, d0, 3\\n\"\n                     \"  div_step d0, r4, d0, 2\\n\"\n                     \"  div_step d0, r4, d0, 1\\n\"\n                     \"__udiv32_base:\\n\"\n                     \"  div_step d0, r4, d0, 0\\n\"\n                     \"__udiv32_exit:\\n\"\n                     \"  jump r23\\n\"\n                     \"__udiv32_result_0:\\n\"\n                     \"  move.u d0, r0, true, __udiv32_exit\\n\"\n                     \"__udiv32_division_by_zero:\\n\"\n                     \"  fault \"__STR(__FAULT_DIVISION_BY_ZERO__));\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) __div32(void)\n{\n    __asm__ volatile(\"  \"__ADD_PROFILING_ENTRY__\n                     \"sd r22, 0, d22\\n\"\n                     \"add r22, r22, 8\\n\"\n                     // The quotient's sign depends on the sign of the dividend and divider... After few tries it sounds\n                     // like the quickest way to select the operators is to branch according to the cases.\n                     \"  clo r3, r0, z, __div32_pos_dividend\\n\"\n                     \"  clo r3, r1, z, __div32_neg_dividend_pos_divider\\n\"\n                     \"__div32_neg_dividend_neg_divider:\\n\" // As a result, the quotient is positive and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1, true, __div32_exit\\n\"\n                     \"__div32_neg_dividend_pos_divider:\\n\" // As a result, the quotient is negative and the remainder negative\n                     \"  neg r0, r0\\n\"\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r1, r1\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend:\\n\"\n                     \"  clo r3, r1, z, __div32_pos_dividend_pos_divider\\n\"\n                     \"  neg r1, r1\\n\" // As a result, the quotient is negative and the remainder positive\n                     \"  call r23, __udiv32\\n\"\n                     \"  neg r0, r0, true, __div32_exit\\n\"\n                     \"__div32_pos_dividend_pos_divider:\\n\" // The dividend and divider are both positive\n                     \"  call r23, __udiv32\\n\"\n                     \"__div32_exit:\\n\"\n                     \"  ld d22, r22, -8\\n\"\n                     \"  jump r23\\n\");\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/divdf3.c",
    "content": "//===-- lib/divdf3.c - Double-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divdf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    const uint32_t q31b = bSignificand >> 21;\n    uint32_t recip32 = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction32;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n\n    // recip32 might have overflowed to exactly zero in the preceding\n    // computation if the high word of b is exactly 1.0.  This would sabotage\n    // the full-width final stage of the computation that follows, so we adjust\n    // recip32 downward by one bit.\n    recip32--;\n\n    // We need to perform one more iteration to get us to 56 binary digits;\n    // The last iteration needs to happen with extra precision.\n    const uint32_t q63blo = bSignificand << 11;\n    uint64_t correction, reciprocal;\n    correction = -((uint64_t)recip32 * q31b + ((uint64_t)recip32 * q63blo >> 32));\n    uint32_t cHi = correction >> 32;\n    uint32_t cLo = correction;\n    reciprocal = (uint64_t)recip32 * cHi + ((uint64_t)recip32 * cLo >> 32);\n\n    // We already adjusted the 32-bit estimate, now we need to adjust the final\n    // 64-bit reciprocal estimate downward to ensure that it is strictly smaller\n    // than the infinitely precise exact reciprocal.  Because the computation\n    // of the Newton-Raphson step is truncating at every step, this adjustment\n    // is small; most of the work is already done.\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-56, lies in the\n    // interval [0.5, 1.0), and is strictly smaller than the true reciprocal\n    // of b.  Multiplying a by this reciprocal thus gives a numerical q = a/b\n    // in Q53 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0.5, 2.0)\n    //    3. the error in q is bounded away from 2^-53 (actually, we have a\n    //       couple of bits to spare, but this is all we need).\n\n    // We need a 64 x 64 multiply high to compute q, which isn't a basic\n    // operation in C, so we need to be a little bit fussy.\n    rep_t quotient, quotientLo;\n    wideMultiply(aSignificand << 2, reciprocal, &quotient, &quotientLo);\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 53) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 52) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        const double result = fromRep(absResult | quotientSign);\n        return result;\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ddiv(fp_t a, fp_t b)\n{\n    return __divdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/divdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__divdi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 0);\n        } else {\n            return -__udiv64(dividend, -divider, 0);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 0);\n    } else {\n        // Negative dividend, negative divider\n        return __udiv64(-dividend, -divider, 0);\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/divmodsi4.c",
    "content": "/*===-- divmodsi4.c - Implement __divmodsi4 --------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__divmodsi4(si_int a, si_int b, si_int *rem)\n{\n    long res = __div32(a, b);\n    *rem = (int)res;\n    return (int)(res >> 32);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/divsf3.c",
    "content": "//===-- lib/divsf3.c - Single-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divsf3(fp_t a, fp_t b)\n{\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent - 1U >= maxExponent - 1U || bExponent - 1U >= maxExponent - 1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep)\n            return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep)\n            return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep)\n                return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else\n                return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep)\n            return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs)\n                return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else\n                return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs)\n            return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit)\n            scale += normalize(&aSignificand);\n        if (bAbs < implicitBit)\n            scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    uint32_t q31b = bSignificand << 8;\n    uint32_t reciprocal = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n\n    // Exhaustive testing shows that the error in reciprocal after three steps\n    // is in the interval [-0x1.f58108p-31, 0x1.d0e48cp-29], in line with our\n    // expectations.  We bump the reciprocal by a tiny value to force the error\n    // to be strictly positive (in the range [0x1.4fdfp-37,0x1.287246p-29], to\n    // be specific).  This also causes 1/1 to give a sensible approximation\n    // instead of zero (due to overflow).\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-28, lies in the\n    // interval [0x1.000000eep-1, 0x1.fffffffcp-1], and is strictly smaller\n    // than the true reciprocal of b.  Multiplying a by this reciprocal thus\n    // gives a numerical q = a/b in Q24 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0x1.000000eep-1, 0x1.fffffffcp0)\n    //    3. the error in q is at most 2^-24 + 2^-27 -- the 2^24 term comes\n    //       from the fact that we truncate the product, and the 2^27 term\n    //       is the error in the reciprocal of b scaled by the maximum\n    //       possible value of a.  As a consequence of this error bound,\n    //       either q or nextafter(q) is the correctly rounded\n    rep_t quotient = (uint64_t)reciprocal * (aSignificand << 1) >> 32;\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 24) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 23) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        return fromRep(absResult | quotientSign);\n    }\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fdiv(fp_t a, fp_t b)\n{\n    return __divsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/divsi3.c",
    "content": "/* ===-- divsi3.c - Implement __divsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __divsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b)\n{\n    const int bits_in_word_m1 = (int)(sizeof(si_int) * CHAR_BIT) - 1;\n    si_int s_a = a >> bits_in_word_m1; /* s_a = a < 0 ? -1 : 0 */\n    si_int s_b = b >> bits_in_word_m1; /* s_b = b < 0 ? -1 : 0 */\n    a = (a ^ s_a) - s_a; /* negate if s_a == -1 */\n    b = (b ^ s_b) - s_b; /* negate if s_b == -1 */\n    s_a ^= s_b; /* sign of quotient */\n    /*\n     * On CPUs without unsigned hardware division support,\n     *  this calls __udivsi3 (notice the cast to su_int).\n     * On CPUs with unsigned hardware division support,\n     *  this uses the unsigned division instruction.\n     */\n    return ((su_int)a / (su_int)b ^ s_a) - s_a; /* negate if s_a == -1 */\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_idiv(si_int a, si_int b)\n{\n    return __divsi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/dpuconst.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUCONST_H\n#define DPUSYSCORE_DPUCONST_H\n\n#define __DPU_NUMBER_OF_THREADS 24\n#define __DPU_MRAM_SIZE_LOG2 26\n\n#endif /* DPUSYSCORE_DPUCONST_H */"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/dpufault.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPUFAULT_H\n#define DPUSYSCORE_DPUFAULT_H\n\n// A list of \"fault codes\"\n#define __FAULT_ALLOC_HEAP_FULL__ 1\n#define __FAULT_DIVISION_BY_ZERO__ 2\n#define __FAULT_ASSERT_FAILED__ 3\n// Used in the compiler to implement a trap\n#define __FAULT_HALT__ 4\n#define __FAULT_PRINTF_OVERFLOW__ 5\n#define __FAULT_ALREADY_PROFILING__ 6\n#define __FAULT_NOT_PROFILING__ 7\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/dpuruntime.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_DPURUNTIME_H\n#define DPUSYSCORE_DPURUNTIME_H\n\n#include <built_ins.h>\n#include <dpuconst.h>\n#include <dpufault.h>\n#include <macro_utils.h>\n#include <stdint.h>\n\n// todo fix: This file should not be included by another syslib header file, only by source files (conflicting definitions).\n\n#define __INITIAL_HEAP_POINTER __sys_heap_pointer_reset\n#define __HEAP_POINTER __sys_heap_pointer\n#define __WAIT_QUEUE_TABLE __sys_wq_table\n#define __SP_TABLE__ __sys_thread_stack_table_ptr\n#define __STDOUT_BUFFER_STATE __stdout_buffer_state\n\n/* The order needs to match the __bootstrap function expectation */\ntypedef struct {\n    uint32_t stack_size;\n    uint32_t stack_ptr;\n} thread_stack_t;\n\nextern unsigned int __INITIAL_HEAP_POINTER;\nextern volatile unsigned int __HEAP_POINTER;\nextern unsigned char __WAIT_QUEUE_TABLE[];\nextern thread_stack_t __SP_TABLE__[];\n\n#define __acquire(base, off) __builtin_acquire_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __release(base, off, at) __builtin_release_rici(base, off, \"nz\", at)\n\n#define __resume(base, off) __builtin_resume_rici(base, off, \"nz\", __AT_THIS_INSTRUCTION)\n#define __stop() __builtin_stop_ci(\"false\", \"0\")\n#define __stop_at(label) __builtin_stop_ci(\"true\", label)\n\n#define likely(x) __builtin_expect((x), 1)\n#define unlikely(x) __builtin_expect((x), 0)\n#define unreachable() __builtin_unreachable()\n\n#define count_leading_zeros(x) __builtin_clz(x)\n#define count_population(x) __builtin_popcount(x)\n\n#define __EMPTY_WAIT_QUEUE 0xFF\n\n#define __AT_THIS_INSTRUCTION \".+0\"\n#define __AT_NEXT_INSTRUCTION \".+1\"\n\n// Use this macro at the beginning of an assembly function in order to get profiled.\n#ifdef DPU_PROFILING\n#define __ADD_PROFILING_ENTRY__ \"call r23, mcount\\n\"\n#else\n#define __ADD_PROFILING_ENTRY__ \"\\n\"\n#endif\n\n#ifdef DPU_PROFILING\n/* Reset counter + count cycles */\n#define __CONFIG_PERFCOUNTER_ENTRY__                                                                                             \\\n    \"  move r23, 3\\n\"                                                                                                            \\\n    \"  time_cfg zero, r23\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__                                                                                               \\\n    \"  time r23\\n\"                                                                                                               \\\n    \"  sw zero, perfcounter_end_value, r23\\n\"\n#else\n#define __CONFIG_PERFCOUNTER_ENTRY__ \"\\n\"\n#define __SAVE_PERFCOUNTER_ENTRY__ \"\\n\"\n#endif\n\n#endif /* DPUSYSCORE_DPURUNTIME_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/extendhfsf2.c",
    "content": "//===-- lib/extendhfsf2.c - half -> single conversion -------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_HALF\n#define DST_SINGLE\n#include \"fp_extend_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE float\n__extendhfsf2(uint16_t a)\n{\n    return __extendXfYf2__(a);\n}\n\nCOMPILER_RT_ABI float\n__gnu_h2f_ieee(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_h2f(uint16_t a)\n{\n    return __extendhfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/extendsfdf2.c",
    "content": "//===-- lib/extendsfdf2.c - single -> double conversion -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n\n#define SRC_SINGLE\n#define DST_DOUBLE\n#include \"fp_extend_impl.inc\"\n\nCOMPILER_RT_ABI double\n__extendsfdf2(float a)\n{\n    return __extendXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_f2d(float a)\n{\n    return __extendsfdf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ffsdi2.c",
    "content": "/* ===-- ffsdi2.c - Implement __ffsdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsdi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctz(x.s.high) + (1 + sizeof(si_int) * CHAR_BIT);\n    }\n    return __builtin_ctz(x.s.low) + 1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ffssi2.c",
    "content": "/* ===-- ffssi2.c - Implement __ffssi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffssi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffssi2(si_int a)\n{\n    if (a == 0) {\n        return 0;\n    }\n    return __builtin_ctz(a) + 1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ffsti2.c",
    "content": "/* ===-- ffsti2.c - Implement __ffsti2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ffsti2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n#ifdef CRT_HAS_128BIT\n\n/* Returns: the index of the least significant 1-bit in a, or\n * the value zero if a is zero. The least significant bit is index one.\n */\n\nCOMPILER_RT_ABI si_int\n__ffsti2(ti_int a)\n{\n    twords x;\n    x.all = a;\n    if (x.s.low == 0) {\n        if (x.s.high == 0)\n            return 0;\n        return __builtin_ctzll(x.s.high) + (1 + sizeof(di_int) * CHAR_BIT);\n    }\n    return __builtin_ctzll(x.s.low) + 1;\n}\n\n#endif /* CRT_HAS_128BIT */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixdfdi.c",
    "content": "/* ===-- fixdfdi.c - Implement __fixdfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a);\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(double a)\n{\n    if (a < 0.0) {\n        return -__fixunsdfdi(-a);\n    }\n    return __fixunsdfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixdfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_d2lz(fp_t a)\n{\n#else\n__aeabi_d2lz(double a)\n{\n#endif\n    return __fixdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixdfsi.c",
    "content": "/* ===-- fixdfsi.c - Implement __fixdfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixdfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_d2iz(fp_t a)\n{\n    return __fixdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixsfdi.c",
    "content": "/* ===-- fixsfdi.c - Implement __fixsfdi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a);\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(float a)\n{\n    if (a < 0.0f) {\n        return -__fixunssfdi(-a);\n    }\n    return __fixunssfdi(a);\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef di_int fixint_t;\ntypedef du_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI di_int\n__fixsfdi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n#if defined(__SOFT_FP__)\n__aeabi_f2lz(fp_t a)\n{\n#else\n__aeabi_f2lz(float a)\n{\n#endif\n    return __fixsfdi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixsfsi.c",
    "content": "/* ===-- fixsfsi.c - Implement __fixsfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixsfsi(fp_t a)\n{\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI si_int\n__aeabi_f2iz(fp_t a)\n{\n    return __fixsfsi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixunsdfdi.c",
    "content": "/* ===-- fixunsdfdi.c - Implement __fixunsdfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(double a)\n{\n    if (a <= 0.0)\n        return 0;\n    su_int high = a / 4294967296.f; /* a / 0x1p32f; */\n    su_int low = a - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunsdfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_d2ulz(fp_t a)\n{\n#else\n__aeabi_d2ulz(double a)\n{\n#endif\n    return __fixunsdfdi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixunsdfsi.c",
    "content": "/* ===-- fixunsdfsi.c - Implement __fixunsdfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunsdfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_d2uiz(fp_t a)\n{\n    return __fixunsdfsi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixunssfdi.c",
    "content": "/* ===-- fixunssfdi.c - Implement __fixunssfdi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; can set the invalid\n * flag as a side-effect of computation.\n */\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(float a)\n{\n    if (a <= 0.0f)\n        return 0;\n    double da = a;\n    su_int high = da / 4294967296.f; /* da / 0x1p32f; */\n    su_int low = da - (double)high * 4294967296.f; /* high * 0x1p32f; */\n    return ((du_int)high << 32) | low;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no\n * flags to set, and we don't want to code-gen to an unknown soft-float\n * implementation.\n */\n\ntypedef du_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI du_int\n__fixunssfdi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI du_int\n#if defined(__SOFT_FP__)\n__aeabi_f2ulz(fp_t a)\n{\n#else\n__aeabi_f2ulz(float a)\n{\n#endif\n    return __fixunssfdi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fixunssfsi.c",
    "content": "/* ===-- fixunssfsi.c - Implement __fixunssfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __fixunssfsi for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunssfsi(fp_t a)\n{\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_f2uiz(fp_t a)\n{\n    return __fixunssfsi(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/float.h",
    "content": "/*===---- float.h - Characteristics of floating point types ----------------===\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n *===-----------------------------------------------------------------------===\n */\n\n#ifndef __FLOAT_H\n#define __FLOAT_H\n\n/**\n * @file float.h\n */\n\n/* Characteristics of floating point types, C99 5.2.4.2.2 */\n\n#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__\n#define FLT_ROUNDS (__builtin_flt_rounds())\n#define FLT_RADIX __FLT_RADIX__\n\n#define FLT_MANT_DIG __FLT_MANT_DIG__\n#define DBL_MANT_DIG __DBL_MANT_DIG__\n#define LDBL_MANT_DIG __LDBL_MANT_DIG__\n\n#if __STDC_VERSION__ >= 199901L || !defined(__STRICT_ANSI__)\n#define DECIMAL_DIG __DECIMAL_DIG__\n#endif\n\n#define FLT_DIG __FLT_DIG__\n#define DBL_DIG __DBL_DIG__\n#define LDBL_DIG __LDBL_DIG__\n\n#define FLT_MIN_EXP __FLT_MIN_EXP__\n#define DBL_MIN_EXP __DBL_MIN_EXP__\n#define LDBL_MIN_EXP __LDBL_MIN_EXP__\n\n#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__\n#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__\n#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__\n\n#define FLT_MAX_EXP __FLT_MAX_EXP__\n#define DBL_MAX_EXP __DBL_MAX_EXP__\n#define LDBL_MAX_EXP __LDBL_MAX_EXP__\n\n#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__\n#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__\n#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__\n\n#define FLT_MAX __FLT_MAX__\n#define DBL_MAX __DBL_MAX__\n#define LDBL_MAX __LDBL_MAX__\n\n#define FLT_EPSILON __FLT_EPSILON__\n#define DBL_EPSILON __DBL_EPSILON__\n#define LDBL_EPSILON __LDBL_EPSILON__\n\n#define FLT_MIN __FLT_MIN__\n#define DBL_MIN __DBL_MIN__\n#define LDBL_MIN __LDBL_MIN__\n\n#define FLT_HAS_SUBNORM (-1)\n#define DBL_HAS_SUBNORM (-1)\n#define LDBL_HAS_SUBNORM (-1)\n#define DBL_FLT_HAS_SUBNORM (-1)\n#define LDBL_FLT_HAS_SUBNORM (-1)\n\n#if __STDC_VERSION__ >= 201112L || !defined(__STRICT_ANSI__)\n#define FLT_TRUE_MIN __FLT_DENORM_MIN__\n#define DBL_TRUE_MIN __DBL_DENORM_MIN__\n#define LDBL_TRUE_MIN __LDBL_DENORM_MIN__\n#define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__\n#define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__\n#define LDBL_DECIMAL_DIG __LDBL_DECIMAL_DIG__\n#endif\n\n#endif /* __FLOAT_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatdidf.c",
    "content": "/*===-- floatdidf.c - Implement __floatdidf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdidf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop32 = 4294967296.0; // 0x1.0p32\n\n    union {\n        int64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    const double high = (int32_t)(a >> 32) * twop32;\n    low.x |= a & INT64_C(0x00000000ffffffff);\n\n    const double result = (high - twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatdidf(di_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         * Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_l2d(di_int a)\n{\n    return __floatdidf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatdisf.c",
    "content": "/*===-- floatdisf.c - Implement __floatdisf -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n *===----------------------------------------------------------------------===\n *\n * This file implements __floatdisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even.*/\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *             di_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatdisf(di_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(di_int) * CHAR_BIT;\n    const di_int s = a >> (N - 1);\n    a = (a ^ s) - s;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = ((du_int)a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((su_int)s & 0x80000000) | /* sign */\n        ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_l2f(di_int a)\n{\n    return __floatdisf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatsidf.c",
    "content": "//===-- lib/floatsidf.c - integer -> double-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsidf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.  Extra\n    // cast to unsigned int is necessary to get the correct behavior for\n    // the input INT_MIN.\n    const int shift = significandBits - exponent;\n    result = (rep_t)(unsigned int)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2d(int a)\n{\n    return __floatsidf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatsisf.c",
    "content": "//===-- lib/floatsisf.c - integer -> single-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsisf(int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_i2f(int a)\n{\n    return __floatsisf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatundidf.c",
    "content": "/* ===-- floatundidf.c - Implement __floatundidf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundidf for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a double, rounding toward even. */\n\n/* Assumption: double is a IEEE 64 bit floating point type\n *             du_int is a 64 bit integral type\n */\n\n/* seee eeee eeee mmmm mmmm mmmm mmmm mmmm | mmmm mmmm mmmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\n#ifndef __SOFT_FP__\n/* Support for systems that have hardware floating-point; we'll set the inexact flag\n * as a side-effect of this computation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    static const double twop52 = 4503599627370496.0; // 0x1.0p52\n    static const double twop84 = 19342813113834066795298816.0; // 0x1.0p84\n    static const double twop84_plus_twop52 = 19342813118337666422669312.0; // 0x1.00000001p84\n\n    union {\n        uint64_t x;\n        double d;\n    } high = { .d = twop84 };\n    union {\n        uint64_t x;\n        double d;\n    } low = { .d = twop52 };\n\n    high.x |= a >> 32;\n    low.x |= a & UINT64_C(0x00000000ffffffff);\n\n    const double result = (high.d - twop84_plus_twop52) + low.d;\n    return result;\n}\n\n#else\n/* Support for systems that don't have hardware floating-point; there are no flags to\n * set, and we don't want to code-gen to an unknown soft-float implementation.\n */\n\nCOMPILER_RT_ABI double\n__floatundidf(du_int a)\n{\n    if (a == 0)\n        return 0.0;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* exponent */\n    if (sd > DBL_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit DBL_MANT_DIG-1 bits to the right of 1\n         *  Q = bit DBL_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case DBL_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case DBL_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (DBL_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + DBL_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to DBL_MANT_DIG or DBL_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << DBL_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to DBL_MANT_DIG bits */\n    } else {\n        a <<= (DBL_MANT_DIG - sd);\n        /* a is now rounded to DBL_MANT_DIG bits */\n    }\n    double_bits fb;\n    fb.u.s.high = ((e + 1023) << 20) | /* exponent */\n        ((su_int)(a >> 32) & 0x000FFFFF); /* mantissa-high */\n    fb.u.s.low = (su_int)a; /* mantissa-low  */\n    return fb.f;\n}\n#endif\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI double\n__aeabi_ul2d(du_int a)\n{\n    return __floatundidf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatundisf.c",
    "content": "/*===-- floatundisf.c - Implement __floatundisf ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __floatundisf for the compiler_rt library.\n *\n *===----------------------------------------------------------------------===\n */\n\n/* Returns: convert a to a float, rounding toward even. */\n\n/* Assumption: float is a IEEE 32 bit floating point type\n *            du_int is a 64 bit integral type\n */\n\n/* seee eeee emmm mmmm mmmm mmmm mmmm mmmm */\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI float\n__floatundisf(du_int a)\n{\n    if (a == 0)\n        return 0.0F;\n    const unsigned N = sizeof(du_int) * CHAR_BIT;\n    int sd = N - __builtin_clzll(a); /* number of significant digits */\n    int e = sd - 1; /* 8 exponent */\n    if (sd > FLT_MANT_DIG) {\n        /*  start:  0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx\n         *  finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR\n         *                                                12345678901234567890123456\n         *  1 = msb 1 bit\n         *  P = bit FLT_MANT_DIG-1 bits to the right of 1\n         *  Q = bit FLT_MANT_DIG bits to the right of 1\n         *  R = \"or\" of all bits to the right of Q\n         */\n        switch (sd) {\n            case FLT_MANT_DIG + 1:\n                a <<= 1;\n                break;\n            case FLT_MANT_DIG + 2:\n                break;\n            default:\n                a = (a >> (sd - (FLT_MANT_DIG + 2))) | ((a & ((du_int)(-1) >> ((N + FLT_MANT_DIG + 2) - sd))) != 0);\n        };\n        /* finish: */\n        a |= (a & 4) != 0; /* Or P into R */\n        ++a; /* round - this step may add a significant bit */\n        a >>= 2; /* dump Q and R */\n        /* a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits */\n        if (a & ((du_int)1 << FLT_MANT_DIG)) {\n            a >>= 1;\n            ++e;\n        }\n        /* a is now rounded to FLT_MANT_DIG bits */\n    } else {\n        a <<= (FLT_MANT_DIG - sd);\n        /* a is now rounded to FLT_MANT_DIG bits */\n    }\n    float_bits fb;\n    fb.u = ((e + 127) << 23) | /* exponent */\n        ((su_int)a & 0x007FFFFF); /* mantissa */\n    return fb.f;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_ul2f(du_int a)\n{\n    return __floatundisf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatunsidf.c",
    "content": "//===-- lib/floatunsidf.c - uint -> double-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsidf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.\n    const int shift = significandBits - exponent;\n    result = (rep_t)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2d(unsigned int a)\n{\n    return __floatunsidf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/floatunsisf.c",
    "content": "//===-- lib/floatunsisf.c - uint -> single-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsisf(unsigned int a)\n{\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit)\n            result++;\n        if (round == signBit)\n            result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_ui2f(unsigned int a)\n{\n    return __floatunsisf(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_add_impl.inc",
    "content": "//===----- lib/fp_add_impl.inc - floaing point addition -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float addition with the IEEE-754 default rounding\n// (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __addXf3__(fp_t a, fp_t b) {\n    rep_t aRep = toRep(a);\n    rep_t bRep = toRep(b);\n    const rep_t aAbs = aRep & absMask;\n    const rep_t bAbs = bRep & absMask;\n\n    // Detect if a or b is zero, infinity, or NaN.\n    if (aAbs - REP_C(1) >= infRep - REP_C(1) ||\n        bAbs - REP_C(1) >= infRep - REP_C(1)) {\n        // NaN + anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything + NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // +/-infinity + -/+infinity = qNaN\n            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);\n            // +/-infinity + anything remaining = +/- infinity\n            else return a;\n        }\n\n        // anything remaining + +/-infinity = +/-infinity\n        if (bAbs == infRep) return b;\n\n        // zero + anything = anything\n        if (!aAbs) {\n            // but we need to get the sign right for zero + zero\n            if (!bAbs) return fromRep(toRep(a) & toRep(b));\n            else return b;\n        }\n\n        // anything + zero = anything\n        if (!bAbs) return a;\n    }\n\n    // Swap a and b if necessary so that a has the larger absolute value.\n    if (bAbs > aAbs) {\n        const rep_t temp = aRep;\n        aRep = bRep;\n        bRep = temp;\n    }\n\n    // Extract the exponent and significand from the (possibly swapped) a and b.\n    int aExponent = aRep >> significandBits & maxExponent;\n    int bExponent = bRep >> significandBits & maxExponent;\n    rep_t aSignificand = aRep & significandMask;\n    rep_t bSignificand = bRep & significandMask;\n\n    // Normalize any denormals, and adjust the exponent accordingly.\n    if (aExponent == 0) aExponent = normalize(&aSignificand);\n    if (bExponent == 0) bExponent = normalize(&bSignificand);\n\n    // The sign of the result is the sign of the larger operand, a.  If they\n    // have opposite signs, we are performing a subtraction; otherwise addition.\n    const rep_t resultSign = aRep & signBit;\n    const bool subtraction = (aRep ^ bRep) & signBit;\n\n    // Shift the significands to give us round, guard and sticky, and or in the\n    // implicit significand bit.  (If we fell through from the denormal path it\n    // was already set by normalize( ), but setting it twice won't hurt\n    // anything.)\n    aSignificand = (aSignificand | implicitBit) << 3;\n    bSignificand = (bSignificand | implicitBit) << 3;\n\n    // Shift the significand of b by the difference in exponents, with a sticky\n    // bottom bit to get rounding correct.\n    const unsigned int align = aExponent - bExponent;\n    if (align) {\n        if (align < typeWidth) {\n            const bool sticky = bSignificand << (typeWidth - align);\n            bSignificand = bSignificand >> align | sticky;\n        } else {\n            bSignificand = 1; // sticky; b is known to be non-zero.\n        }\n    }\n    if (subtraction) {\n        aSignificand -= bSignificand;\n        // If a == -b, return +zero.\n        if (aSignificand == 0) return fromRep(0);\n\n        // If partial cancellation occured, we need to left-shift the result\n        // and adjust the exponent:\n        if (aSignificand < implicitBit << 3) {\n            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);\n            aSignificand <<= shift;\n            aExponent -= shift;\n        }\n    }\n    else /* addition */ {\n        aSignificand += bSignificand;\n\n        // If the addition carried up, we need to right-shift the result and\n        // adjust the exponent:\n        if (aSignificand & implicitBit << 4) {\n            const bool sticky = aSignificand & 1;\n            aSignificand = aSignificand >> 1 | sticky;\n            aExponent += 1;\n        }\n    }\n\n    // If we have overflowed the type, return +/- infinity:\n    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);\n\n    if (aExponent <= 0) {\n        // Result is denormal before rounding; the exponent is zero and we\n        // need to shift the significand.\n        const int shift = 1 - aExponent;\n        const bool sticky = aSignificand << (typeWidth - shift);\n        aSignificand = aSignificand >> shift | sticky;\n        aExponent = 0;\n    }\n\n    // Low three bits are round, guard, and sticky.\n    const int roundGuardSticky = aSignificand & 0x7;\n\n    // Shift the significand into place, and mask off the implicit bit.\n    rep_t result = aSignificand >> 3 & significandMask;\n\n    // Insert the exponent and sign.\n    result |= (rep_t)aExponent << significandBits;\n    result |= resultSign;\n\n    // Final rounding.  The result may overflow to infinity, but that is the\n    // correct result in that case.\n    if (roundGuardSticky > 0x4) result++;\n    if (roundGuardSticky == 0x4) result += result & 1;\n    return fromRep(result);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_extend.h",
    "content": "//===-lib/fp_extend.h - low precision -> high precision conversion -*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_EXTEND_HEADER\n#define FP_EXTEND_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n#define src_rep_t_clz __builtin_clz\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\nstatic __inline int\nsrc_rep_t_clz(src_rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#elif defined SRC_HALF\ntypedef uint16_t src_t;\ntypedef uint16_t src_rep_t;\n#define SRC_REP_C UINT16_C\nstatic const int srcSigBits = 10;\n#define src_rep_t_clz __builtin_clz\n\n#else\n#error Source should be half, single, or double precision!\n#endif // end source precision\n\n#if defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_QUAD\ntypedef long double dst_t;\ntypedef __uint128_t dst_rep_t;\n#define DST_REP_C (__uint128_t)\nstatic const int dstSigBits = 112;\n\n#else\n#error Destination should be single, double, or quad precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n// End helper routines.  Conversion implementation follows.\n\n#endif // FP_EXTEND_HEADER\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_extend_impl.inc",
    "content": "//=-lib/fp_extend_impl.inc - low precision -> high precision conversion -*-- -//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a narrower to a wider\n// IEEE-754 floating-point type.  The constants and types defined following the\n// includes below parameterize the conversion.\n//\n// It does not support types that don't use the usual IEEE-754 interchange\n// formats; specifically, some work would be needed to adapt it to\n// (for example) the Intel 80-bit format or PowerPC double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *widening* operations; if you need to convert to a *narrower* floating-point\n// type (e.g. double -> float), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.  You also may\n// run into trouble finding an appropriate CLZ function for wide source types;\n// you will likely need to roll your own on some platforms.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_extend.h\"\n\nstatic __inline dst_t __extendXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const dst_rep_t dstMinNormal = DST_REP_C(1) << dstSigBits;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    // If sizeof(src_rep_t) < sizeof(int), the subtraction result is promoted\n    // to (signed) int.  To avoid that, explicitly cast to src_rep_t.\n    if ((src_rep_t)(aAbs - srcMinNormal) < srcInfinity - srcMinNormal) {\n        // a is a normal number.\n        // Extend to the destination type by shifting the significand and\n        // exponent into the proper position and rebiasing the exponent.\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits);\n        absResult += (dst_rep_t)(dstExpBias - srcExpBias) << dstSigBits;\n    }\n\n    else if (aAbs >= srcInfinity) {\n        // a is NaN or infinity.\n        // Conjure the result by beginning with infinity, then setting the qNaN\n        // bit (if needed) and right-aligning the rest of the trailing NaN\n        // payload field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= (dst_rep_t)(aAbs & srcQNaN) << (dstSigBits - srcSigBits);\n        absResult |= (dst_rep_t)(aAbs & srcNaNCode) << (dstSigBits - srcSigBits);\n    }\n\n    else if (aAbs) {\n        // a is denormal.\n        // renormalize the significand and clear the leading bit, then insert\n        // the correct adjusted exponent in the destination type.\n        const int scale = src_rep_t_clz(aAbs) - src_rep_t_clz(srcMinNormal);\n        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits + scale);\n        absResult ^= dstMinNormal;\n        const int resultExponent = dstExpBias - srcExpBias - scale + 1;\n        absResult |= (dst_rep_t)resultExponent << dstSigBits;\n    }\n\n    else {\n        // a is zero.\n        absResult = 0;\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_fixint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixint_t __fixint(fp_t a) {\n    const fixint_t fixint_max = (fixint_t)((~(fixuint_t)0) / 2);\n    const fixint_t fixint_min = -fixint_max - 1;\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const fixint_t sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If exponent is negative, the result is zero.\n    if (exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixint_t) * CHAR_BIT)\n        return sign == 1 ? fixint_max : fixint_min;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return sign * (significand >> (significandBits - exponent));\n    else\n        return sign * ((fixint_t)significand << (exponent - significandBits));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_fixuint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to unsigned integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixuint_t __fixuint(fp_t a) {\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const int sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If either the value or the exponent is negative, the result is zero.\n    if (sign == -1 || exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixuint_t) * CHAR_BIT)\n        return ~(fixuint_t)0;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return significand >> (significandBits - exponent);\n    else\n        return (fixuint_t)significand << (exponent - significandBits);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_lib.h",
    "content": "//===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file is a configuration header for soft-float routines in compiler-rt.\n// This file does not provide any part of the compiler-rt interface, but defines\n// many useful constants and utility routines that are used in the\n// implementation of the soft-float routines in compiler-rt.\n//\n// Assumes that float, double and long double correspond to the IEEE-754\n// binary32, binary64 and binary 128 types, respectively, and that integer\n// endianness matches floating point endianness on the target platform.\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_LIB_HEADER\n#define FP_LIB_HEADER\n\n#include <stdint.h>\n#include <stdbool.h>\n#include <limits.h>\n#include \"int_lib.h\"\n\n// x86_64 FreeBSD prior v9.3 define fixed-width types incorrectly in\n// 32-bit mode.\n#if defined(__FreeBSD__) && defined(__i386__)\n#include <sys/param.h>\n#if __FreeBSD_version < 903000 // v9.3\n#define uint64_t unsigned long long\n#define int64_t long long\n#undef UINT64_C\n#define UINT64_C(c) (c##ULL)\n#endif\n#endif\n\n#if defined SINGLE_PRECISION\n\ntypedef uint32_t rep_t;\ntypedef int32_t srep_t;\ntypedef float fp_t;\n#define REP_C UINT32_C\n#define significandBits 23\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    return __builtin_clz(a);\n}\n\n// 32x32 --> 64 bit multiply\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    const uint64_t product = (uint64_t)a * b;\n    *hi = product >> 32;\n    *lo = product;\n}\nCOMPILER_RT_ABI fp_t\n__addsf3(fp_t a, fp_t b);\n\n#elif defined DOUBLE_PRECISION\n\ntypedef uint64_t rep_t;\ntypedef int64_t srep_t;\ntypedef double fp_t;\n#define REP_C UINT64_C\n#define significandBits 52\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#define loWord(a) (a & 0xffffffffU)\n#define hiWord(a) (a >> 32)\n\n// 64x64 -> 128 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n    // Each of the component 32x32 -> 64 products\n    const uint64_t plolo = loWord(a) * loWord(b);\n    const uint64_t plohi = loWord(a) * hiWord(b);\n    const uint64_t philo = hiWord(a) * loWord(b);\n    const uint64_t phihi = hiWord(a) * hiWord(b);\n    // Sum terms that contribute to lo in a way that allows us to get the carry\n    const uint64_t r0 = loWord(plolo);\n    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);\n    *lo = r0 + (r1 << 32);\n    // Sum terms contributing to hi with the carry from lo\n    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;\n}\n#undef loWord\n#undef hiWord\n\nCOMPILER_RT_ABI fp_t\n__adddf3(fp_t a, fp_t b);\n\n#elif defined QUAD_PRECISION\n#if __LDBL_MANT_DIG__ == 113\n#define CRT_LDBL_128BIT\ntypedef __uint128_t rep_t;\ntypedef __int128_t srep_t;\ntypedef long double fp_t;\n#define REP_C (__uint128_t)\n// Note: Since there is no explicit way to tell compiler the constant is a\n// 128-bit integer, we let the constant be casted to 128-bit integer\n#define significandBits 112\n\nstatic __inline int\nrep_clz(rep_t a)\n{\n    const union {\n        __uint128_t ll;\n#if _YUGA_BIG_ENDIAN\n        struct {\n            uint64_t high, low;\n        } s;\n#else\n        struct {\n            uint64_t low, high;\n        } s;\n#endif\n    } uu = { .ll = a };\n\n    uint64_t word;\n    uint64_t add;\n\n    if (uu.s.high) {\n        word = uu.s.high;\n        add = 0;\n    } else {\n        word = uu.s.low;\n        add = 64;\n    }\n    return __builtin_clzll(word) + add;\n}\n\n#define Word_LoMask UINT64_C(0x00000000ffffffff)\n#define Word_HiMask UINT64_C(0xffffffff00000000)\n#define Word_FullMask UINT64_C(0xffffffffffffffff)\n#define Word_1(a) (uint64_t)((a >> 96) & Word_LoMask)\n#define Word_2(a) (uint64_t)((a >> 64) & Word_LoMask)\n#define Word_3(a) (uint64_t)((a >> 32) & Word_LoMask)\n#define Word_4(a) (uint64_t)(a & Word_LoMask)\n\n// 128x128 -> 256 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void\nwideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo)\n{\n\n    const uint64_t product11 = Word_1(a) * Word_1(b);\n    const uint64_t product12 = Word_1(a) * Word_2(b);\n    const uint64_t product13 = Word_1(a) * Word_3(b);\n    const uint64_t product14 = Word_1(a) * Word_4(b);\n    const uint64_t product21 = Word_2(a) * Word_1(b);\n    const uint64_t product22 = Word_2(a) * Word_2(b);\n    const uint64_t product23 = Word_2(a) * Word_3(b);\n    const uint64_t product24 = Word_2(a) * Word_4(b);\n    const uint64_t product31 = Word_3(a) * Word_1(b);\n    const uint64_t product32 = Word_3(a) * Word_2(b);\n    const uint64_t product33 = Word_3(a) * Word_3(b);\n    const uint64_t product34 = Word_3(a) * Word_4(b);\n    const uint64_t product41 = Word_4(a) * Word_1(b);\n    const uint64_t product42 = Word_4(a) * Word_2(b);\n    const uint64_t product43 = Word_4(a) * Word_3(b);\n    const uint64_t product44 = Word_4(a) * Word_4(b);\n\n    const __uint128_t sum0 = (__uint128_t)product44;\n    const __uint128_t sum1 = (__uint128_t)product34 + (__uint128_t)product43;\n    const __uint128_t sum2 = (__uint128_t)product24 + (__uint128_t)product33 + (__uint128_t)product42;\n    const __uint128_t sum3 = (__uint128_t)product14 + (__uint128_t)product23 + (__uint128_t)product32 + (__uint128_t)product41;\n    const __uint128_t sum4 = (__uint128_t)product13 + (__uint128_t)product22 + (__uint128_t)product31;\n    const __uint128_t sum5 = (__uint128_t)product12 + (__uint128_t)product21;\n    const __uint128_t sum6 = (__uint128_t)product11;\n\n    const __uint128_t r0 = (sum0 & Word_FullMask) + ((sum1 & Word_LoMask) << 32);\n    const __uint128_t r1 = (sum0 >> 64) + ((sum1 >> 32) & Word_FullMask) + (sum2 & Word_FullMask) + ((sum3 << 32) & Word_HiMask);\n\n    *lo = r0 + (r1 << 64);\n    *hi = (r1 >> 64) + (sum1 >> 96) + (sum2 >> 64) + (sum3 >> 32) + sum4 + (sum5 << 32) + (sum6 << 64);\n}\n#undef Word_1\n#undef Word_2\n#undef Word_3\n#undef Word_4\n#undef Word_HiMask\n#undef Word_LoMask\n#undef Word_FullMask\n#endif // __LDBL_MANT_DIG__ == 113\n#else\n#error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.\n#endif\n\n#if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) || defined(CRT_LDBL_128BIT)\n#define typeWidth (sizeof(rep_t) * CHAR_BIT)\n#define exponentBits (typeWidth - significandBits - 1)\n#define maxExponent ((1 << exponentBits) - 1)\n#define exponentBias (maxExponent >> 1)\n\n#define implicitBit (REP_C(1) << significandBits)\n#define significandMask (implicitBit - 1U)\n#define signBit (REP_C(1) << (significandBits + exponentBits))\n#define absMask (signBit - 1U)\n#define exponentMask (absMask ^ significandMask)\n#define oneRep ((rep_t)exponentBias << significandBits)\n#define infRep exponentMask\n#define quietBit (implicitBit >> 1)\n#define qnanRep (exponentMask | quietBit)\n\nstatic __inline rep_t\ntoRep(fp_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline fp_t\nfromRep(rep_t x)\n{\n    const union {\n        fp_t f;\n        rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\nstatic __inline int\nnormalize(rep_t *significand)\n{\n    const int shift = rep_clz(*significand) - rep_clz(implicitBit);\n    *significand <<= shift;\n    return 1 - shift;\n}\n\nstatic __inline void\nwideLeftShift(rep_t *hi, rep_t *lo, int count)\n{\n    *hi = *hi << count | *lo >> (typeWidth - count);\n    *lo = *lo << count;\n}\n\nstatic __inline void\nwideRightShiftWithSticky(rep_t *hi, rep_t *lo, unsigned int count)\n{\n    if (count < typeWidth) {\n        const bool sticky = *lo << (typeWidth - count);\n        *lo = *hi << (typeWidth - count) | *lo >> count | sticky;\n        *hi = *hi >> count;\n    } else if (count < 2 * typeWidth) {\n        const bool sticky = *hi << (2 * typeWidth - count) | *lo;\n        *lo = *hi >> (count - typeWidth) | sticky;\n        *hi = 0;\n    } else {\n        const bool sticky = *hi | *lo;\n        *lo = sticky;\n        *hi = 0;\n    }\n}\n#endif\n\n#endif // FP_LIB_HEADER\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_mul_impl.inc",
    "content": "//===---- lib/fp_mul_impl.inc - floating point multiplication -----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float multiplication with the IEEE-754 default\n// rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __mulXf3__(fp_t a, fp_t b) {\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN * anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything * NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity * non-zero = +/- infinity\n            if (bAbs) return fromRep(aAbs | productSign);\n            // infinity * zero = NaN\n            else return fromRep(qnanRep);\n        }\n\n        if (bAbs == infRep) {\n            //? non-zero * infinity = +/- infinity\n            if (aAbs) return fromRep(bAbs | productSign);\n            // zero * infinity = NaN\n            else return fromRep(qnanRep);\n        }\n\n        // zero * anything = +/- zero\n        if (!aAbs) return fromRep(productSign);\n        // anything * zero = +/- zero\n        if (!bAbs) return fromRep(productSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale += normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n\n    // Get the significand of a*b.  Before multiplying the significands, shift\n    // one of them left to left-align it in the field.  Thus, the product will\n    // have (exponentBits + 2) integral digits, all but two of which must be\n    // zero.  Normalizing this result is just a conditional left-shift by one\n    // and bumping the exponent accordingly.\n    rep_t productHi, productLo;\n    wideMultiply(aSignificand, bSignificand << exponentBits,\n                 &productHi, &productLo);\n\n    int productExponent = aExponent + bExponent - exponentBias + scale;\n\n    // Normalize the significand, adjust exponent if needed.\n    if (productHi & implicitBit) productExponent++;\n    else wideLeftShift(&productHi, &productLo, 1);\n\n    // If we have overflowed the type, return +/- infinity.\n    if (productExponent >= maxExponent) return fromRep(infRep | productSign);\n\n    if (productExponent <= 0) {\n        // Result is denormal before rounding\n        //\n        // If the result is so small that it just underflows to zero, return\n        // a zero of the appropriate sign.  Mathematically there is no need to\n        // handle this case separately, but we make it a special case to\n        // simplify the shift logic.\n        const unsigned int shift = REP_C(1) - (unsigned int)productExponent;\n        if (shift >= typeWidth) return fromRep(productSign);\n\n        // Otherwise, shift the significand of the result so that the round\n        // bit is the high bit of productLo.\n        wideRightShiftWithSticky(&productHi, &productLo, shift);\n    }\n    else {\n        // Result is normal before rounding; insert the exponent.\n        productHi &= significandMask;\n        productHi |= (rep_t)productExponent << significandBits;\n    }\n\n    // Insert the sign of the result:\n    productHi |= productSign;\n\n    // Final rounding.  The final result may overflow to infinity, or underflow\n    // to zero, but those are the correct results in those cases.  We use the\n    // default IEEE-754 round-to-nearest, ties-to-even rounding mode.\n    if (productLo > signBit) productHi++;\n    if (productLo == signBit) productHi += productHi & 1;\n    return fromRep(productHi);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_trunc.h",
    "content": "//=== lib/fp_trunc.h - high precision -> low precision conversion *- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// Set source and destination precision setting\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_TRUNC_HEADER\n#define FP_TRUNC_HEADER\n\n#include \"int_lib.h\"\n\n#if defined SRC_SINGLE\ntypedef float src_t;\ntypedef uint32_t src_rep_t;\n#define SRC_REP_C UINT32_C\nstatic const int srcSigBits = 23;\n\n#elif defined SRC_DOUBLE\ntypedef double src_t;\ntypedef uint64_t src_rep_t;\n#define SRC_REP_C UINT64_C\nstatic const int srcSigBits = 52;\n\n#elif defined SRC_QUAD\ntypedef long double src_t;\ntypedef __uint128_t src_rep_t;\n#define SRC_REP_C (__uint128_t)\nstatic const int srcSigBits = 112;\n\n#else\n#error Source should be double precision or quad precision!\n#endif // end source precision\n\n#if defined DST_DOUBLE\ntypedef double dst_t;\ntypedef uint64_t dst_rep_t;\n#define DST_REP_C UINT64_C\nstatic const int dstSigBits = 52;\n\n#elif defined DST_SINGLE\ntypedef float dst_t;\ntypedef uint32_t dst_rep_t;\n#define DST_REP_C UINT32_C\nstatic const int dstSigBits = 23;\n\n#elif defined DST_HALF\ntypedef uint16_t dst_t;\ntypedef uint16_t dst_rep_t;\n#define DST_REP_C UINT16_C\nstatic const int dstSigBits = 10;\n\n#else\n#error Destination should be single precision or double precision!\n#endif // end destination precision\n\n// End of specialization parameters.  Two helper routines for conversion to and\n// from the representation of floating-point data as integer values follow.\n\nstatic __inline src_rep_t\nsrcToRep(src_t x)\n{\n    const union {\n        src_t f;\n        src_rep_t i;\n    } rep = { .f = x };\n    return rep.i;\n}\n\nstatic __inline dst_t\ndstFromRep(dst_rep_t x)\n{\n    const union {\n        dst_t f;\n        dst_rep_t i;\n    } rep = { .i = x };\n    return rep.f;\n}\n\n#endif // FP_TRUNC_HEADER\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fp_trunc_impl.inc",
    "content": "//= lib/fp_trunc_impl.inc - high precision -> low precision conversion *-*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements a fairly generic conversion from a wider to a narrower\n// IEEE-754 floating-point type in the default (round to nearest, ties to even)\n// rounding mode.  The constants and types defined following the includes below\n// parameterize the conversion.\n//\n// This routine can be trivially adapted to support conversions to\n// half-precision or from quad-precision. It does not support types that don't\n// use the usual IEEE-754 interchange formats; specifically, some work would be\n// needed to adapt it to (for example) the Intel 80-bit format or PowerPC\n// double-double format.\n//\n// Note please, however, that this implementation is only intended to support\n// *narrowing* operations; if you need to convert to a *wider* floating-point\n// type (e.g. float -> double), then this routine will not do what you want it\n// to.\n//\n// It also requires that integer types at least as large as both formats\n// are available on the target platform; this may pose a problem when trying\n// to add support for quad on some 32-bit systems, for example.\n//\n// Finally, the following assumptions are made:\n//\n// 1. floating-point types and integer types have the same endianness on the\n//    target platform\n//\n// 2. quiet NaNs, if supported, are indicated by the leading bit of the\n//    significand field being set\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_trunc.h\"\n\nstatic __inline dst_t __truncXfYf2__(src_t a) {\n    // Various constants whose values follow from the type parameters.\n    // Any reasonable optimizer will fold and propagate all of these.\n    const int srcBits = sizeof(src_t)*CHAR_BIT;\n    const int srcExpBits = srcBits - srcSigBits - 1;\n    const int srcInfExp = (1 << srcExpBits) - 1;\n    const int srcExpBias = srcInfExp >> 1;\n\n    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;\n    const src_rep_t srcSignificandMask = srcMinNormal - 1;\n    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;\n    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);\n    const src_rep_t srcAbsMask = srcSignMask - 1;\n    const src_rep_t roundMask = (SRC_REP_C(1) << (srcSigBits - dstSigBits)) - 1;\n    const src_rep_t halfway = SRC_REP_C(1) << (srcSigBits - dstSigBits - 1);\n    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);\n    const src_rep_t srcNaNCode = srcQNaN - 1;\n\n    const int dstBits = sizeof(dst_t)*CHAR_BIT;\n    const int dstExpBits = dstBits - dstSigBits - 1;\n    const int dstInfExp = (1 << dstExpBits) - 1;\n    const int dstExpBias = dstInfExp >> 1;\n\n    const int underflowExponent = srcExpBias + 1 - dstExpBias;\n    const int overflowExponent = srcExpBias + dstInfExp - dstExpBias;\n    const src_rep_t underflow = (src_rep_t)underflowExponent << srcSigBits;\n    const src_rep_t overflow = (src_rep_t)overflowExponent << srcSigBits;\n\n    const dst_rep_t dstQNaN = DST_REP_C(1) << (dstSigBits - 1);\n    const dst_rep_t dstNaNCode = dstQNaN - 1;\n\n    // Break a into a sign and representation of the absolute value\n    const src_rep_t aRep = srcToRep(a);\n    const src_rep_t aAbs = aRep & srcAbsMask;\n    const src_rep_t sign = aRep & srcSignMask;\n    dst_rep_t absResult;\n\n    if (aAbs - underflow < aAbs - overflow) {\n        // The exponent of a is within the range of normal numbers in the\n        // destination format.  We can convert by simply right-shifting with\n        // rounding and adjusting the exponent.\n        absResult = aAbs >> (srcSigBits - dstSigBits);\n        absResult -= (dst_rep_t)(srcExpBias - dstExpBias) << dstSigBits;\n\n        const src_rep_t roundBits = aAbs & roundMask;\n        // Round to nearest\n        if (roundBits > halfway)\n            absResult++;\n        // Ties to even\n        else if (roundBits == halfway)\n            absResult += absResult & 1;\n    }\n    else if (aAbs > srcInfinity) {\n        // a is NaN.\n        // Conjure the result by beginning with infinity, setting the qNaN\n        // bit and inserting the (truncated) trailing NaN field.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n        absResult |= dstQNaN;\n        absResult |= ((aAbs & srcNaNCode) >> (srcSigBits - dstSigBits)) & dstNaNCode;\n    }\n    else if (aAbs >= overflow) {\n        // a overflows to infinity.\n        absResult = (dst_rep_t)dstInfExp << dstSigBits;\n    }\n    else {\n        // a underflows on conversion to the destination type or is an exact\n        // zero.  The result may be a denormal or zero.  Extract the exponent\n        // to get the shift amount for the denormalization.\n        const int aExp = aAbs >> srcSigBits;\n        const int shift = srcExpBias - dstExpBias - aExp + 1;\n\n        const src_rep_t significand = (aRep & srcSignificandMask) | srcMinNormal;\n\n        // Right shift by the denormalization amount with sticky.\n        if (shift > srcSigBits) {\n            absResult = 0;\n        } else {\n            const bool sticky = significand << (srcBits - shift);\n            src_rep_t denormalizedSignificand = significand >> shift | sticky;\n            absResult = denormalizedSignificand >> (srcSigBits - dstSigBits);\n            const src_rep_t roundBits = denormalizedSignificand & roundMask;\n            // Round to nearest\n            if (roundBits > halfway)\n                absResult++;\n            // Ties to even\n            else if (roundBits == halfway)\n                absResult += absResult & 1;\n        }\n    }\n\n    // Apply the signbit to (dst_t)abs(a).\n    const dst_rep_t result = absResult | sign >> (srcBits - dstBits);\n    return dstFromRep(result);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fsb_allocator.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <fsb_allocator.h>\n#include <alloc.h>\n#include <stddef.h>\n#include <dpuruntime.h>\n#include <attributes.h>\n#include <atomic_bit.h>\n\nATOMIC_BIT_INIT(__fsb_lock);\n\n// noinline, because part of grind tracked functions\nfsb_allocator_t __noinline\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks)\n{\n    if (block_size > 0xFFFFFFF8) {\n        __asm__ volatile(\"fault \" __STR(__FAULT_ALLOC_HEAP_FULL__));\n        unreachable();\n    }\n\n    block_size = (block_size == 0) ? 8 : (block_size + 7) & ~7;\n\n    unsigned int memory_space_to_allocate = block_size * nb_of_blocks + 4;\n    void *memory = mem_alloc(memory_space_to_allocate);\n\n    unsigned int first_block = (unsigned int)memory;\n\n    for (unsigned int each_block = 0; each_block < nb_of_blocks - 1; ++each_block) {\n        unsigned int next_block_address = (unsigned int)(memory + block_size);\n        *((unsigned int *)memory) = next_block_address;\n        memory = (void *)next_block_address;\n    }\n\n    *((unsigned int *)memory) = 0;\n    memory += block_size;\n\n    void *free_ptr = memory;\n    *((unsigned int *)free_ptr) = first_block;\n\n    return (fsb_allocator_t)free_ptr;\n}\n\n// noinline, because part of grind tracked functions\nvoid *__noinline\nfsb_get(fsb_allocator_t allocator)\n{\n    void **result;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(result) : [alloc] \"r\"(allocator));\n\n    if (result == NULL) {\n        ATOMIC_BIT_RELEASE(__fsb_lock);\n        return NULL;\n    }\n\n    void *next = *result;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(next), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n\n    return (void *)result;\n}\n\n// noinline, because part of grind tracked functions\nvoid __noinline\nfsb_free(fsb_allocator_t allocator, void *ptr)\n{\n    void *next_free;\n    ATOMIC_BIT_ACQUIRE(__fsb_lock);\n    __asm__ volatile(\"lw %[res], %[alloc], 0\" : [res] \"=r\"(next_free) : [alloc] \"r\"(allocator));\n\n    *((void **)ptr) = next_free;\n\n    __asm__ volatile(\"sw %[alloc], 0, %[res]\" : : [res] \"r\"(ptr), [alloc] \"r\"(allocator));\n    ATOMIC_BIT_RELEASE(__fsb_lock);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/fsb_allocator.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_FBS_ALLOC_H\n#define DPUSYSCORE_FBS_ALLOC_H\n\n/**\n * @file fsb_allocator.h\n * @brief Provides a fixed-size block memory allocator.\n *\n * @internal When defining an allocator, the total memory needed will be allocated, using mem_alloc.\n *           The allocator structure is a pointer to the next available block. In each free block, the first four bytes\n *           store a pointer to the following free block, creating a linked list. To allocate a block, we just check\n *           the free pointer, check the next free pointer and update the free pointer accordingly. To free a block, we\n *           just check the free pointer, update it with the newly free block, and update the next pointer of this block\n *           with the previous free pointer.\n *           There is no protection to prevent invalid block to be added to the list. Moreover, the list being in the free\n *           blocks, if there is some memory overflow from a block, the list might be corrupted and totally invalid.\n */\n\n/**\n * @fn fsb_allocator_t\n * @brief A fixed-size block allocator.\n */\ntypedef void **fsb_allocator_t;\n\n/**\n * @fn fsb_alloc\n * @brief Allocate and initialize a fixed-size block allocator.\n *\n * @param block_size the size of the blocks allocated (will be realigned on 8 bytes, with a minimum of 8 bytes)\n * @param nb_of_blocks the number of blocks allocated\n * @throws a fault if there is no memory left\n * @return The newly allocated and ready-to-use fixed-size block allocator.\n */\nfsb_allocator_t\nfsb_alloc(unsigned int block_size, unsigned int nb_of_blocks);\n\n/**\n * @fn fsb_get\n * @brief Own a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator from which we take the block\n * @return A pointer to the owned block if one was available, NULL otherwise.\n */\nvoid *\nfsb_get(fsb_allocator_t allocator);\n\n/**\n * @fn fsb_free\n * @brief Free a block of the specified fixed-size block allocator, in a runtime-safe way.\n *\n * @param allocator the allocator in which we put the block back in\n * @param ptr the pointer to the block to free\n */\nvoid\nfsb_free(fsb_allocator_t allocator, void *ptr);\n\n#endif /* DPUSYSCORE_FBS_ALLOC_H */"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/handshake.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <defs.h>\n#include <errno.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n\nunsigned char __handshake_array[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };\n\nATOMIC_BIT_INIT(__handshake)[NR_THREADS];\n\n#define __acquire_handshake(off) __ATOMIC_BIT_ACQUIRE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n#define __release_handshake(off) __ATOMIC_BIT_RELEASE(off + (ATOMIC_BIT_GET(__handshake) - &__atomic_start_addr), 0)\n\nvoid\nhandshake_notify(void)\n{\n    thread_id_t tid = me();\n    unsigned char info;\n    __acquire_handshake(tid);\n    info = __handshake_array[tid];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[tid] = tid;\n        __release_handshake(tid);\n        __stop();\n    } else {\n        __resume(info, \"0\");\n        __handshake_array[tid] = __EMPTY_WAIT_QUEUE;\n        __release_handshake(tid);\n    }\n}\n\nint\nhandshake_wait_for(unsigned int notifier)\n{\n    thread_id_t tid = me();\n\n    unsigned char thread = (unsigned char)notifier;\n\n    __acquire_handshake(thread);\n    unsigned char info = __handshake_array[thread];\n\n    if (unlikely(info == __EMPTY_WAIT_QUEUE)) {\n        __handshake_array[thread] = tid;\n        __release_handshake(thread);\n        __stop();\n    } else {\n        if (unlikely(info != thread)) {\n            errno = EALREADY;\n            __release_handshake(thread);\n            return EALREADY;\n        } else {\n            __resume(info, \"0\");\n            __handshake_array[thread] = __EMPTY_WAIT_QUEUE;\n        }\n\n        __release_handshake(thread);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/handshake.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_HANDSHAKE_H\n#define DPUSYSCORE_HANDSHAKE_H\n\n/**\n * @file handshake.h\n * @brief Synchronization with handshakes.\n *\n * This synchronization mechanism allows to synchronize 2 tasklets. One tasklet will serve as a notifier\n * and will call handshake_notify() and the other as a customer and will call handshake_wait_for(notifier).\n *\n * @internal    If the notifier called handshake_notify() before the customer, it will stop until some tasklet\n *              calls handshake_wait_for(notifier).\n *              If a tasklet called handshake_wait_for(notifier) before the notifier, it will stop until\n *              the notifier calls handshake_notify(). If afterwards (still before the notifier calls\n *              handshake_notify()) another tasklet attempts to call handshake_wait_for(notifier) with\n *              the same tasklet in the parameter, the function will do nothing and will return the number\n *              of error and set the errno to the corresponding error number.\n */\n\n#include <sysdef.h>\n\n/**\n * @fn handshake_notify\n * @brief Notifies a tasklet waiting for the notifier.\n *\n * The invoking tasklet is suspended until another tasklet calls handshake_wait_for(notifier).\n * When this condition is reached, the function resumes the waiting tasklet.\n */\nvoid\nhandshake_notify(void);\n\n/**\n * @fn handshake_wait_for\n * @brief Waits for the notifier tasklet\n *\n * The invoking tasklet is suspended until the notifier tasklet (indicated in the parameter) sends a\n * notification to tell the invoking tasklet that it can go ahead.\n *\n * Beware that if the notifier tasklet and the invoking tasklet are the same, the tasklet will be suspended with no\n * easy way to wake it up. The user should check this case itself if it is something that their program allows.\n *\n * If the number of the notifier is not a defined tasklet, the function behavior is undefined. If some other tasklet has\n * already called handshake_wait_for() with the same notifier in the parameter and that the notifier has not yet called\n * handshake_notify(), the function will do nothing and simply return EALREADY.\n *\n * In both cases the errno will be set to the corresponding error number.\n *\n * @param notifier a number to wait the notification from. It must be a defined tasklet.\n * @return 0 if no error was detected, EALREADY if a corresponding error was detected.\n */\nint\nhandshake_wait_for(sysname_t notifier);\n\n#endif /* DPUSYSCORE_HANDSHAKE_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_endianness.h",
    "content": "/* ===-- int_endianness.h - configuration header for compiler-rt ------------===\n *\n *\t\t       The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_ENDIANNESS_H\n#define INT_ENDIANNESS_H\n\n#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && defined(__ORDER_LITTLE_ENDIAN__)\n\n/* Clang and GCC provide built-in endianness definitions. */\n#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* __BYTE_ORDER__ */\n\n#else /* Compilers other than Clang or GCC. */\n\n#if defined(__SVR4) && defined(__sun)\n#include <sys/byteorder.h>\n\n#if defined(_BIG_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif defined(_LITTLE_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#else /* !_LITTLE_ENDIAN */\n#error \"unknown endianness\"\n#endif /* !_LITTLE_ENDIAN */\n\n#endif /* Solaris and AuroraUX. */\n\n/* .. */\n\n#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__minix)\n#include <sys/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* *BSD */\n\n#if defined(__OpenBSD__) || defined(__Bitrig__)\n#include <machine/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif /* _BYTE_ORDER */\n\n#endif /* OpenBSD and Bitrig. */\n\n/* .. */\n\n/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the\n * compiler (at least with GCC) */\n#if defined(__APPLE__) || defined(__ellcc__)\n\n#ifdef __BIG_ENDIAN__\n#if __BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN 1\n#endif\n#endif /* __BIG_ENDIAN__ */\n\n#ifdef __LITTLE_ENDIAN__\n#if __LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n#endif\n#endif /* __LITTLE_ENDIAN__ */\n\n#endif /* Mac OSX */\n\n/* .. */\n\n#if defined(_WIN32)\n\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN 0\n\n#endif /* Windows */\n\n#endif /* Clang or GCC. */\n\n/* . */\n\n#if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN)\n#error Unable to determine endian\n#endif /* Check we found an endianness correctly. */\n\n#endif /* INT_ENDIANNESS_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_lib.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_LIB_H\n#define INT_LIB_H\n\n/* Assumption: Signed integral is 2's complement. */\n/* Assumption: Right shift of signed negative is arithmetic shift. */\n/* Assumption: Endianness is little or big (not mixed). */\n\n#if defined(__ELF__)\n#define FNALIAS(alias_name, original_name) void alias_name() __attribute__((alias(#original_name)))\n#else\n#define FNALIAS(alias, name) _Pragma(\"GCC error(\\\"alias unsupported on this file format\\\")\")\n#endif\n\n/* ABI macro definitions */\n\n#if __ARM_EABI__\n#ifdef COMPILER_RT_ARMHF_TARGET\n#define COMPILER_RT_ABI\n#else\n#define COMPILER_RT_ABI __attribute__((__pcs__(\"aapcs\")))\n#endif\n#else\n#define COMPILER_RT_ABI\n#endif\n\n#define AEABI_RTABI __attribute__((__pcs__(\"aapcs\")))\n\n#ifdef _MSC_VER\n#define ALWAYS_INLINE __forceinline\n#define NOINLINE __declspec(noinline)\n#define NORETURN __declspec(noreturn)\n#define UNUSED\n#else\n#define ALWAYS_INLINE __attribute__((always_inline))\n#define NOINLINE __attribute__((noinline))\n#define NORETURN __attribute__((noreturn))\n#define UNUSED __attribute__((unused))\n#endif\n\n#if defined(__NetBSD__) && (defined(_KERNEL) || defined(_STANDALONE))\n/*\n * Kernel and boot environment can't use normal headers,\n * so use the equivalent system headers.\n */\n#include <machine/limits.h>\n#include <sys/stdint.h>\n#include <sys/types.h>\n#else\n/* Include the standard compiler builtin headers we use functionality from. */\n#include <limits.h>\n#include <stdint.h>\n#include <stdbool.h>\n#include <float.h>\n#endif\n\n/* Include the commonly used internal type definitions. */\n#include \"int_types.h\"\n\n/* Include internal utility function declarations. */\n#include \"int_util.h\"\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a);\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a);\n\nCOMPILER_RT_ABI di_int\n__divdi3(di_int a, di_int b);\nCOMPILER_RT_ABI si_int\n__divsi3(si_int a, si_int b);\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem);\nCOMPILER_RT_ABI du_int\n__udivmoddi4(du_int a, du_int b, du_int *rem);\n#ifdef CRT_HAS_128BIT\nCOMPILER_RT_ABI si_int\n__clzti2(ti_int a);\nCOMPILER_RT_ABI tu_int\n__udivmodti4(tu_int a, tu_int b, tu_int *rem);\n#endif\n\n/* Definitions for builtins unavailable on MSVC */\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <intrin.h>\n\nuint32_t __inline __builtin_ctz(uint32_t value)\n{\n    unsigned long trailing_zero = 0;\n    if (_BitScanForward(&trailing_zero, value))\n        return trailing_zero;\n    return 32;\n}\n\nuint32_t __inline __builtin_clz(uint32_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse(&leading_zero, value))\n        return 31 - leading_zero;\n    return 32;\n}\n\n#if defined(_M_ARM) || defined(_M_X64)\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    unsigned long leading_zero = 0;\n    if (_BitScanReverse64(&leading_zero, value))\n        return 63 - leading_zero;\n    return 64;\n}\n#else\nuint32_t __inline __builtin_clzll(uint64_t value)\n{\n    if (value == 0)\n        return 64;\n    uint32_t msh = (uint32_t)(value >> 32);\n    uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF);\n    if (msh != 0)\n        return __builtin_clz(msh);\n    return 32 + __builtin_clz(lsh);\n}\n#endif\n\n#define __builtin_clzl __builtin_clzll\n#endif /* defined(_MSC_VER) && !defined(__clang__) */\n\n#endif /* INT_LIB_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_math.h",
    "content": "/* ===-- int_math.h - internal math inlines ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines substitutes for the libm functions used in some of the\n * compiler-rt implementations, defined in such a way that there is not a direct\n * dependency on libm or math.h. Instead, we use the compiler builtin versions\n * where available. This reduces our dependencies on the system SDK by foisting\n * the responsibility onto the compiler.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_MATH_H\n#define INT_MATH_H\n\n#ifndef __has_builtin\n#define __has_builtin(x) 0\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <math.h>\n#include <stdlib.h>\n#include <ymath.h>\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define CRT_INFINITY INFINITY\n#else\n#define CRT_INFINITY __builtin_huge_valf()\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_isfinite(x) _finite((x))\n#define crt_isinf(x) !_finite((x))\n#define crt_isnan(x) _isnan((x))\n#else\n/* Define crt_isfinite in terms of the builtin if available, otherwise provide\n * an alternate version in terms of our other functions. This supports some\n * versions of GCC which didn't have __builtin_isfinite.\n */\n#if __has_builtin(__builtin_isfinite)\n#define crt_isfinite(x) __builtin_isfinite((x))\n#elif defined(__GNUC__)\n#define crt_isfinite(x)                                                                                                          \\\n    __extension__(({                                                                                                             \\\n        __typeof((x)) x_ = (x);                                                                                                  \\\n        crt_isinf(x_) && crt_isnan(x_);                                                                                          \\\n    }))\n#else\n#error \"Do not know how to check for infinity\"\n#endif /* __has_builtin(__builtin_isfinite) */\n#define crt_isinf(x) __builtin_isinf((x))\n#define crt_isnan(x) __builtin_isnan((x))\n#endif /* _MSC_VER */\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_copysign(x, y) copysign((x), (y))\n#define crt_copysignf(x, y) copysignf((x), (y))\n#define crt_copysignl(x, y) copysignl((x), (y))\n#else\n#define crt_copysign(x, y) __builtin_copysign((x), (y))\n#define crt_copysignf(x, y) __builtin_copysignf((x), (y))\n#define crt_copysignl(x, y) __builtin_copysignl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fabs(x) fabs((x))\n#define crt_fabsf(x) fabsf((x))\n#define crt_fabsl(x) fabs((x))\n#else\n#define crt_fabs(x) __builtin_fabs((x))\n#define crt_fabsf(x) __builtin_fabsf((x))\n#define crt_fabsl(x) __builtin_fabsl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_fmax(x, y) __max((x), (y))\n#define crt_fmaxf(x, y) __max((x), (y))\n#define crt_fmaxl(x, y) __max((x), (y))\n#else\n#define crt_fmax(x, y) __builtin_fmax((x), (y))\n#define crt_fmaxf(x, y) __builtin_fmaxf((x), (y))\n#define crt_fmaxl(x, y) __builtin_fmaxl((x), (y))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_logb(x) logb((x))\n#define crt_logbf(x) logbf((x))\n#define crt_logbl(x) logbl((x))\n#else\n#define crt_logb(x) __builtin_logb((x))\n#define crt_logbf(x) __builtin_logbf((x))\n#define crt_logbl(x) __builtin_logbl((x))\n#endif\n\n#if defined(_MSC_VER) && !defined(__clang__)\n#define crt_scalbn(x, y) scalbn((x), (y))\n#define crt_scalbnf(x, y) scalbnf((x), (y))\n#define crt_scalbnl(x, y) scalbnl((x), (y))\n#else\n#define crt_scalbn(x, y) __builtin_scalbn((x), (y))\n#define crt_scalbnf(x, y) __builtin_scalbnf((x), (y))\n#define crt_scalbnl(x, y) __builtin_scalbnl((x), (y))\n#endif\n\n#endif /* INT_MATH_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_types.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines various standard types, most importantly a number of unions\n * used to access parts of larger types.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_TYPES_H\n#define INT_TYPES_H\n\n#include \"int_endianness.h\"\n\n/* si_int is defined in Linux sysroot's asm-generic/siginfo.h */\n#ifdef si_int\n#undef si_int\n#endif\ntypedef int si_int;\ntypedef unsigned su_int;\n\ntypedef long long di_int;\ntypedef unsigned long long du_int;\n\ntypedef union {\n    di_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        si_int high;\n#else\n        si_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} dwords;\n\ntypedef union {\n    du_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        su_int high;\n#else\n        su_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} udwords;\n\n#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64))\n#define CRT_HAS_128BIT\n#endif\n\n#ifdef CRT_HAS_128BIT\ntypedef int ti_int __attribute__((mode(TI)));\ntypedef unsigned tu_int __attribute__((mode(TI)));\n\ntypedef union {\n    ti_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        di_int high;\n#else\n        di_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} twords;\n\ntypedef union {\n    tu_int all;\n    struct {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        du_int high;\n#else\n        du_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    } s;\n} utwords;\n\nstatic __inline ti_int\nmake_ti(di_int h, di_int l)\n{\n    twords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\nstatic __inline tu_int\nmake_tu(du_int h, du_int l)\n{\n    utwords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\n#endif /* CRT_HAS_128BIT */\n\ntypedef union {\n    su_int u;\n    float f;\n} float_bits;\n\ntypedef union {\n    udwords u;\n    double f;\n} double_bits;\n\ntypedef struct {\n#if _YUGA_LITTLE_ENDIAN\n    udwords low;\n    udwords high;\n#else\n    udwords high;\n    udwords low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n} uqwords;\n\ntypedef union {\n    uqwords u;\n    long double f;\n} long_double_bits;\n\n#if __STDC_VERSION__ >= 199901L\ntypedef float _Complex Fcomplex;\ntypedef double _Complex Dcomplex;\ntypedef long double _Complex Lcomplex;\n\n#define COMPLEX_REAL(x) __real__(x)\n#define COMPLEX_IMAGINARY(x) __imag__(x)\n#else\ntypedef struct {\n    float real, imaginary;\n} Fcomplex;\n\ntypedef struct {\n    double real, imaginary;\n} Dcomplex;\n\ntypedef struct {\n    long double real, imaginary;\n} Lcomplex;\n\n#define COMPLEX_REAL(x) (x).real\n#define COMPLEX_IMAGINARY(x) (x).imaginary\n#endif\n#endif /* INT_TYPES_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_util.c",
    "content": "/* ===-- int_util.c - Implement internal utilities --------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_util.h\"\n\n/* NOTE: The definitions in this file are declared weak because we clients to be\n * able to arbitrarily package individual functions into separate .a files. If\n * we did not declare these weak, some link situations might end up seeing\n * duplicate strong definitions of the same symbol.\n *\n * We can't use this solution for kernel use (which may not support weak), but\n * currently expect that when built for kernel use all the functionality is\n * packaged into a single library.\n */\n\n#ifdef KERNEL_USE\n\nNORETURN extern void\npanic(const char *, ...);\n#ifndef _WIN32\n__attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    panic(\"%s:%d: abort in %s\", file, line, function);\n}\n\n#elif __APPLE__\n\n/* from libSystem.dylib */\nNORETURN extern void\n__assert_rtn(const char *func, const char *file, int line, const char *message);\n\n#ifndef _WIN32\n__attribute__((weak)) __attribute__((visibility(\"hidden\")))\n#endif\nvoid\ncompilerrt_abort_impl(const char *file, int line, const char *function)\n{\n    __assert_rtn(function, file, line, \"libcompiler_rt abort\");\n}\n\n#else\n\n/* Get the system definition of abort() */\n#include <stdlib.h>\n\n#ifndef _WIN32\n// JFR dirty patch\n// DPUCC doesn't like it either __attribute__((weak))\n// DPUCC doesn't like it either __attribute__((visibility(\"hidden\")))\n// End of patch\n#endif\nvoid\ncompilerrt_abort_impl(const char *file __attribute__((unused)),\n    int line __attribute__((unused)),\n    const char *function __attribute__((unused)))\n{\n    abort();\n}\n\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/int_util.h",
    "content": "/* ===-- int_util.h - internal utility functions ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines non-inline utilities which are available for use in the\n * library. The function definitions themselves are all contained in int_util.c\n * which will always be compiled into any compiler-rt library.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_UTIL_H\n#define INT_UTIL_H\n\n/** \\brief Trigger a program abort (or panic for kernel code). */\n#define compilerrt_abort() compilerrt_abort_impl(__FILE__, __LINE__, __func__)\n\nNORETURN void\ncompilerrt_abort_impl(const char *file, int line, const char *function);\n\n#define COMPILE_TIME_ASSERT(expr) COMPILE_TIME_ASSERT1(expr, __COUNTER__)\n#define COMPILE_TIME_ASSERT1(expr, cnt) COMPILE_TIME_ASSERT2(expr, cnt)\n#define COMPILE_TIME_ASSERT2(expr, cnt) typedef char ct_assert_##cnt[(expr) ? 1 : -1] UNUSED\n\n#endif /* INT_UTIL_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/listener.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#include <sysdef.h>\n#include <defs.h>\n\nextern bool\nfetch_request(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\nextern bool\nfifo_is_full(uint32_t fifo_info, uint32_t request_size);\nextern void\nfifo_produce(uint32_t fifo_info, uint32_t *request, uint32_t request_size);\n\nstatic inline uint32_t\nfifo_sys_fetch_info(uint32_t fid)\n{\n    extern uint32_t __sys_fifo_sys_table;\n    return (&__sys_fifo_sys_table)[fid];\n}\n\nstatic inline uint32_t\nfifo_fetch_info(sysname_t recipient)\n{\n    extern uint32_t __sys_fifo_table_ptr;\n    return *((uint32_t *)((&__sys_fifo_table_ptr)[recipient] & 0xFFFF));\n}\n\nstatic inline sysname_t\nfetch_recipient(uint32_t id)\n{\n    return id >> 24;\n}\n\nstatic inline sysname_t\nfetch_request_id(uint32_t id)\n{\n    return id & 0x00FFFFFF;\n}\n\nvoid\n__sys_internal_listener_loop(uint32_t *request, uint32_t request_size)\n{\n    sysname_t id = me();\n    uint32_t self_fifo_info;\n    uint32_t from_host_fifo_info;\n    uint32_t to_host_fifo_info;\n\n    self_fifo_info = fifo_fetch_info(id);\n    from_host_fifo_info = fifo_sys_fetch_info(0);\n    to_host_fifo_info = fifo_sys_fetch_info(1);\n\n    while (true) {\n        if (fetch_request(self_fifo_info, request, request_size)) {\n            while (fifo_is_full(to_host_fifo_info, request_size)) {\n                // Waiting for the recipient to read some of its pending requests...\n                // Do we want to add some \"sleep\" here?\n            }\n\n            fifo_produce(to_host_fifo_info, request, request_size);\n        }\n        if (fetch_request(from_host_fifo_info, request, request_size)) {\n            sysname_t recipient = fetch_recipient(request[0]);\n\n            /* If a message is sent to the listener from the host, we interpret it as a shutdown order. */\n            if (recipient == id)\n                break;\n\n            request[0] = fetch_request_id(request[0]);\n\n            extern void internal_actor_send(uint32_t recipient, uint32_t * request, uint32_t request_size);\n            internal_actor_send(recipient, request, request_size);\n        }\n\n        // Waiting for some request...\n        // Do we want to add some \"sleep\" here?\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/lshrdi3.c",
    "content": "/* ===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __lshrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: logical a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__lshrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    udwords input;\n    udwords result;\n    input.all = a;\n    if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.high = 0;\n        result.s.low = input.s.high >> (b - bits_in_word);\n    } else /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int\n__aeabi_llsr(di_int a, si_int b)\n{\n    return __lshrdi3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/macro_utils.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MACRO_UTILS_H\n#define DPUSYSCORE_MACRO_UTILS_H\n\n/**\n * @file macro_utils.h\n * @brief Provide utility macros.\n */\n\n#define __STR(x) __STR_AGAIN(x)\n#define __STR_AGAIN(x) #x\n\n#define __CONCAT(x, y) __CONCAT_AGAIN(x, y)\n#define __CONCAT_AGAIN(x, y) x##y\n\n#define __REPEAT_0(x)\n#define __REPEAT_1(x) x(0) __REPEAT_0(x)\n#define __REPEAT_2(x) x(1) __REPEAT_1(x)\n#define __REPEAT_3(x) x(2) __REPEAT_2(x)\n#define __REPEAT_4(x) x(3) __REPEAT_3(x)\n#define __REPEAT_5(x) x(4) __REPEAT_4(x)\n#define __REPEAT_6(x) x(5) __REPEAT_5(x)\n#define __REPEAT_7(x) x(6) __REPEAT_6(x)\n#define __REPEAT_8(x) x(7) __REPEAT_7(x)\n#define __REPEAT_9(x) x(8) __REPEAT_8(x)\n#define __REPEAT_10(x) x(9) __REPEAT_9(x)\n#define __REPEAT_11(x) x(10) __REPEAT_10(x)\n#define __REPEAT_12(x) x(11) __REPEAT_11(x)\n#define __REPEAT_13(x) x(12) __REPEAT_12(x)\n#define __REPEAT_14(x) x(13) __REPEAT_13(x)\n#define __REPEAT_15(x) x(14) __REPEAT_14(x)\n#define __REPEAT_16(x) x(15) __REPEAT_15(x)\n#define __REPEAT_17(x) x(16) __REPEAT_16(x)\n#define __REPEAT_18(x) x(17) __REPEAT_17(x)\n#define __REPEAT_19(x) x(18) __REPEAT_18(x)\n#define __REPEAT_20(x) x(19) __REPEAT_19(x)\n#define __REPEAT_21(x) x(20) __REPEAT_20(x)\n#define __REPEAT_22(x) x(21) __REPEAT_21(x)\n#define __REPEAT_23(x) x(22) __REPEAT_22(x)\n#define __REPEAT_24(x) x(23) __REPEAT_23(x)\n#define __FOR_EACH_THREAD(x) __CONCAT(__REPEAT_, NR_THREADS)(x)\n\n#endif /* DPUSYSCORE_MACRO_UTILS_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mcount.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\nvoid __attribute__((naked, noinline, no_instrument_function)) mcount(void)\n{\n    // Please see ret_mcount comment regarding why mcount references ret_mcount.\n    __asm__ volatile(\"jump ret_mcount\");\n}\n\nvoid __attribute__((naked, noinline, no_instrument_function)) ret_mcount(void)\n{\n    // ret_mcount is used in statistics mode, mcount *must* reference ret_mcount\n    // so that ret_mcount symbol is not gc (remember that we patch the binary\n    // when copying it to iram).\n    __asm__ volatile(\"sh id4, thread_profiling, r23\\n\"\n                     \"jump r23\");\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/moddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 signed division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nint64_t\n__moddi3(int64_t dividend, int64_t divider)\n{\n    if (dividend >= 0) {\n        if (divider >= 0) {\n            return __udiv64(dividend, divider, 1);\n        } else {\n            return __udiv64(dividend, -divider, 1);\n        }\n    } else if (divider >= 0) {\n        // Negative dividend, positive divider\n        return -__udiv64(-dividend, divider, 1);\n    } else {\n        // Negative dividend, negative divider\n        return -__udiv64(-dividend, -divider, 1);\n    }\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/modsi3.c",
    "content": "/* ===-- modsi3.c - Implement __modsi3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __modsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern long\n__div32(int, int);\n\nCOMPILER_RT_ABI si_int\n__modsi3(si_int a, si_int b)\n{\n    long res = __div32(a, b);\n    return (int)res;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mram.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MRAM_H\n#define DPUSYSCORE_MRAM_H\n\n#include <stdint.h>\n#include <attributes.h>\n\n/**\n * @file mram.h\n * @brief MRAM Transfer Management.\n */\n\n#define DPU_MRAM_HEAP_POINTER ((__mram_ptr void *)(&__sys_used_mram_end))\nextern __mram_ptr __dma_aligned uint8_t __sys_used_mram_end[0];\n\n/**\n * @fn mram_read\n * @brief Stores the specified number of bytes from MRAM to WRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in MRAM\n * @param to destination address in WRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_read(const __mram_ptr void *from, void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_ldma(to, from, nb_of_bytes);\n}\n\n/**\n * @fn mram_write\n * @brief Stores the specified number of bytes from WRAM to MRAM.\n * The number of bytes must be:\n *  - at least 8\n *  - at most 2048\n *  - a multiple of 8\n *\n * @param from source address in WRAM\n * @param to destination address in MRAM\n * @param nb_of_bytes number of bytes to transfer\n */\nstatic inline void\nmram_write(const void *from, __mram_ptr void *to, unsigned int nb_of_bytes)\n{\n    __builtin_dpu_sdma(from, to, nb_of_bytes);\n}\n\n#endif /* DPUSYSCORE_MRAM_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mul32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nint __attribute__((noinline)) __mulsi3(int a, int b)\n{\n    int dest;\n    __asm__ volatile(\"  jgtu %2, %1, __mulsi3_swap\\n\"\n                     \"  move r2, %1\\n\"\n                     \"  move r0, %2, true, __mulsi3_start\\n\"\n                     \"__mulsi3_swap:\\n\"\n                     \"  move r2, %2\\n\"\n                     \"  move r0, %1\\n\"\n                     \"__mulsi3_start:\\n\"\n                     \"  move r1, zero\\n\"\n                     \"  mul_step d0, r2, d0, 0 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 1 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 2 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 3 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 4 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 5 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 6 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 7 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 8 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 9 , z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 10, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 11, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 12, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 13, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 14, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 15, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 16, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 17, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 18, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 19, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 20, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 21, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 22, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 23, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 24, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 25, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 26, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 27, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 28, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 29, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 30, z, __mulsi3_exit\\n\"\n                     \"  mul_step d0, r2, d0, 31, z, __mulsi3_exit\\n\"\n                     \"__mulsi3_exit:\\n\"\n                     \"  move %0, r1\\n\"\n                     : \"=r\"(dest)\n                     : \"r\"(a), \"r\"(b));\n    return dest;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mul64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication emulation.\n *\n * A relatively fast emulation of 64x64 multiplication using byte multipliers.\n * Basically, the two operands X and Y are seen as byte polynomials:\n *  - X = X0.2^0 + X1.2^8 + X2.2^16 + X3.2^24 + X4.2^32 + X5.2^40 + X6.2^48 + X7.2^56\n *  - Y = Y0.2^0 + Y1.2^8 + Y2.2^16 + Y3.2^24 + Y4.2^32 + Y5.2^40 + Y6.2^48 + Y7.2^56\n *\n * The product Z is expressed as a similar polynomial. Since the result is 64 bits,\n * the function drops any coefficient for a power greater than 56, hence the following\n * formula:\n *  Z = (X0.Y0).2^0\n *      + (X0.Y1 + X1.Y0).2^8\n *      + (X0.Y2 + X2.Y0 + X1.Y1).2^16\n *      + (X0.Y3 + X1.Y2 + X2.Y1 + X3.Y0).2^24\n *      + (X0.Y4 + X1.Y3 + X2.Y2 + X3.Y1 + X4.Y0).2^32\n *      etc.\n *\n * Each individual produce is computed with the native built-in 8x8 instructions.\n * Resulting processing time is in the magnitude of 150 instructions.\n *\n * The two operands are found in __D0 and the first kernel nano-stack entry.\n * The result goes into __R0 (lsbits) and __R1 (msbits).\n * Also, __R2 contains the return address register, instead of __RET__.\n */\n#include <stdint.h>\n\nstatic uint16_t\n_mul00(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * (b & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul01(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return (a & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_ul_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\n#define _mul02(a, b) _mul00(a, (b >> 16))\n#define _mul03(a, b) _mul01(a, (b >> 16))\n\nstatic uint16_t\n_mul11(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 8) & 0xff);\n#else\n    uint32_t r;\n    __asm__ volatile(\"mul_uh_uh %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(b) :);\n    return r;\n#endif\n}\n\nstatic uint16_t\n_mul12(uint32_t a, uint32_t b)\n{\n#ifndef DPU\n    return ((a >> 8) & 0xff) * ((b >> 16) & 0xff);\n#else\n    uint32_t r = (b >> 16);\n    __asm__ volatile(\"mul_uh_ul %[rc_wr32], %[ra_r32], %[rb_wr32]\" : [rc_wr32] \"=r\"(r) : [ra_r32] \"r\"(a), [rb_wr32] \"r\"(r) :);\n    return r;\n#endif\n}\n\n#define _mul13(a, b) _mul11(a, (b >> 16))\n#define _mul22(a, b) _mul00((a >> 16), (b >> 16))\n#define _mul23(a, b) _mul01((a >> 16), (b >> 16))\n#define _mul33(a, b) _mul11((a >> 16), (b >> 16))\n\n#define mulx0y0(xl, yl) _mul00(xl, yl)\n#define mulx0y1(xl, yl) _mul01(xl, yl)\n#define mulx0y2(xl, yl) _mul02(xl, yl)\n#define mulx0y3(xl, yl) _mul03(xl, yl)\n#define mulx0y4(xl, yh) _mul00(xl, yh)\n#define mulx0y5(xl, yh) _mul01(xl, yh)\n#define mulx0y6(xl, yh) _mul02(xl, yh)\n#define mulx0y7(xl, yh) _mul03(xl, yh)\n\n#define mulx1y1(xl, yl) _mul11(xl, yl)\n#define mulx1y2(xl, yl) _mul12(xl, yl)\n#define mulx1y3(xl, yl) _mul13(xl, yl)\n#define mulx1y4(xl, yh) _mul01(yh, xl)\n#define mulx1y5(xl, yh) _mul11(xl, yh)\n#define mulx1y6(xl, yh) _mul12(xl, yh)\n\n#define mulx2y2(xl, yl) _mul22(xl, yl)\n#define mulx2y3(xl, yl) _mul23(xl, yl)\n#define mulx2y4(xl, yh) _mul02(yh, xl)\n#define mulx2y5(xl, yh) _mul12(yh, xl)\n\n#define mulx3y3(xl, yl) _mul33(xl, yl)\n#define mulx3y4(xl, yh) _mul03(yh, xl)\n\n// Symmetry...\n#define mulx1y0(xl, yl) mulx0y1(yl, xl)\n#define mulx2y0(xl, yl) mulx0y2(yl, xl)\n#define mulx2y1(xl, yl) mulx1y2(yl, xl)\n#define mulx3y0(xl, yl) mulx0y3(yl, xl)\n#define mulx3y1(xl, yl) mulx1y3(yl, xl)\n#define mulx3y2(xl, yl) mulx2y3(yl, xl)\n#define mulx4y0(xh, yl) mulx0y4(yl, xh)\n#define mulx4y1(xh, yl) mulx1y4(yl, xh)\n#define mulx4y2(xh, yl) mulx2y4(yl, xh)\n#define mulx4y3(xh, yl) mulx3y4(yl, xh)\n#define mulx5y0(xh, yl) mulx0y5(yl, xh)\n#define mulx5y1(xh, yl) mulx1y5(yl, xh)\n#define mulx5y2(xh, yl) mulx2y5(yl, xh)\n#define mulx6y0(xh, yl) mulx0y6(yl, xh)\n#define mulx6y1(xh, yl) mulx1y6(yl, xh)\n#define mulx7y0(xh, yl) mulx0y7(yl, xh)\n\nuint64_t\n__muldi3(uint64_t x, uint64_t y)\n{\n    uint32_t xl = x;\n    uint32_t xh = ((uint64_t)x >> 32);\n    uint32_t yl = y;\n    uint32_t yh = ((uint64_t)y >> 32);\n\n    // Each fragment of the product.\n    uint32_t p0, p1, p2, p3, p4, p5, p6, p7, rh;\n    uint64_t rl;\n\n    p0 = mulx0y0(xl, yl);\n    rl = (uint64_t)p0;\n    p1 = mulx0y1(xl, yl) + mulx1y0(xl, yl);\n    rl += ((uint64_t)p1 << 8);\n    p2 = mulx0y2(xl, yl) + mulx2y0(xl, yl) + mulx1y1(xl, yl);\n    rl += ((uint64_t)p2 << 16);\n    p3 = mulx0y3(xl, yl) + mulx3y0(xl, yl) + mulx1y2(xl, yl) + mulx2y1(xl, yl);\n    rl += ((uint64_t)p3 << 24);\n    p4 = mulx0y4(xl, yh) + mulx4y0(xh, yl) + mulx1y3(xl, yl) + mulx3y1(xl, yl) + mulx2y2(xl, yl);\n    rh = p4;\n    p5 = mulx0y5(xl, yh) + mulx5y0(xh, yl) + mulx1y4(xl, yh) + mulx4y1(xh, yl) + mulx2y3(xl, yl) + mulx3y2(xl, yl);\n    rh += p5 << 8;\n    p6 = mulx0y6(xl, yh) + mulx6y0(xh, yl) + mulx1y5(xl, yh) + mulx5y1(xh, yl) + mulx2y4(xl, yh) + mulx4y2(xh, yl)\n        + mulx3y3(xl, yl);\n    rh += p6 << 16;\n    p7 = mulx0y7(xl, yh) + mulx7y0(xh, yl) + mulx1y6(xl, yh) + mulx6y1(xh, yl) + mulx2y5(xl, yh) + mulx5y2(xh, yl)\n        + mulx3y4(xl, yh) + mulx4y3(xh, yl);\n    rh += p7 << 24;\n\n    return rl + (((uint64_t)rh) << 32);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/muldc3.c",
    "content": "/* ===-- muldc3.c - Implement __muldc3 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __muldc3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n#include \"int_math.h\"\n\n/* Returns: the product of a + ib and c + id */\n\nCOMPILER_RT_ABI Dcomplex\n__muldc3(double __a, double __b, double __c, double __d)\n{\n    double __ac = __a * __c;\n    double __bd = __b * __d;\n    double __ad = __a * __d;\n    double __bc = __b * __c;\n    Dcomplex z;\n    COMPLEX_REAL(z) = __ac - __bd;\n    COMPLEX_IMAGINARY(z) = __ad + __bc;\n    if (crt_isnan(COMPLEX_REAL(z)) && crt_isnan(COMPLEX_IMAGINARY(z))) {\n        int __recalc = 0;\n        if (crt_isinf(__a) || crt_isinf(__b)) {\n            __a = crt_copysign(crt_isinf(__a) ? 1 : 0, __a);\n            __b = crt_copysign(crt_isinf(__b) ? 1 : 0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (crt_isinf(__c) || crt_isinf(__d)) {\n            __c = crt_copysign(crt_isinf(__c) ? 1 : 0, __c);\n            __d = crt_copysign(crt_isinf(__d) ? 1 : 0, __d);\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            __recalc = 1;\n        }\n        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) || crt_isinf(__ad) || crt_isinf(__bc))) {\n            if (crt_isnan(__a))\n                __a = crt_copysign(0, __a);\n            if (crt_isnan(__b))\n                __b = crt_copysign(0, __b);\n            if (crt_isnan(__c))\n                __c = crt_copysign(0, __c);\n            if (crt_isnan(__d))\n                __d = crt_copysign(0, __d);\n            __recalc = 1;\n        }\n        if (__recalc) {\n            COMPLEX_REAL(z) = CRT_INFINITY * (__a * __c - __b * __d);\n            COMPLEX_IMAGINARY(z) = CRT_INFINITY * (__a * __d + __b * __c);\n        }\n    }\n    return z;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/muldf3.c",
    "content": "//===-- lib/muldf3.c - Double-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__muldf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dmul(fp_t a, fp_t b)\n{\n    return __muldf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mulodi4.c",
    "content": "/*===-- mulodi4.c - Implement __mulodi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulodi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulodi4(di_int a, di_int b, int *overflow)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    *overflow = 0;\n    di_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mulosi4.c",
    "content": "/*===-- mulosi4.c - Implement __mulosi4 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulosi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: sets *overflow to 1  if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulosi4(si_int a, si_int b, int *overflow)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    *overflow = 0;\n    si_int result = a * b;\n    if (a == MIN) {\n        if (b != 0 && b != 1)\n            *overflow = 1;\n        return result;\n    }\n    if (b == MIN) {\n        if (a != 0 && a != 1)\n            *overflow = 1;\n        return result;\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return result;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            *overflow = 1;\n    } else {\n        if (abs_a > MIN / -abs_b)\n            *overflow = 1;\n    }\n    return result;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mulsf3.c",
    "content": "//===-- lib/mulsf3.c - Single-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t\n__mulsf3(fp_t a, fp_t b)\n{\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fmul(fp_t a, fp_t b)\n{\n    return __mulsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mulvdi3.c",
    "content": "/*===-- mulvdi3.c - Implement __mulvdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI di_int\n__mulvdi3(di_int a, di_int b)\n{\n    const int N = (int)(sizeof(di_int) * CHAR_BIT);\n    const di_int MIN = (di_int)1 << (N - 1);\n    const di_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    di_int sa = a >> (N - 1);\n    di_int abs_a = (a ^ sa) - sa;\n    di_int sb = b >> (N - 1);\n    di_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mulvsi3.c",
    "content": "/* ===-- mulvsi3.c - Implement __mulvsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __mulvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a * b */\n\n/* Effects: aborts if a * b overflows */\n\nCOMPILER_RT_ABI si_int\n__mulvsi3(si_int a, si_int b)\n{\n    const int N = (int)(sizeof(si_int) * CHAR_BIT);\n    const si_int MIN = (si_int)1 << (N - 1);\n    const si_int MAX = ~MIN;\n    if (a == MIN) {\n        if (b == 0 || b == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    if (b == MIN) {\n        if (a == 0 || a == 1)\n            return a * b;\n        compilerrt_abort();\n    }\n    si_int sa = a >> (N - 1);\n    si_int abs_a = (a ^ sa) - sa;\n    si_int sb = b >> (N - 1);\n    si_int abs_b = (b ^ sb) - sb;\n    if (abs_a < 2 || abs_b < 2)\n        return a * b;\n    if (sa == sb) {\n        if (abs_a > MAX / abs_b)\n            compilerrt_abort();\n    } else {\n        if (abs_a > MIN / -abs_b)\n            compilerrt_abort();\n    }\n    return a * b;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/mutex.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_MUTEX_H\n#define DPUSYSCORE_MUTEX_H\n\n/**\n * @file mutex.h\n * @brief Mutual exclusions.\n *\n * A mutex ensures mutual exclusion between threads: only one runtime can have the mutex at a time, blocking all the\n * other threads trying to take the mutex.\n *\n * @internal All the mutexes are stored in a table in WRAM. In this table, each byte represents a mutex,\n *           and can be accessed directly by taking the base address of the table and adding it the sysname of the mutex\n *           we want (thus, the sysname should be an integer in the range [0; NB_MUTEX -1]). The result of\n *           this addition is what a mutex_get will return.\n *           A lock is made by using an lb_a instruction on the address of the mutex given as a parameter.\n *           An unlock is made by using an sb_r instruction on the address of the mutex given as a parameter.\n *           The id of the runtime doing the unlock is what is currently stored at the address of the mutex.\n *           The base address of this table is associated with the pointer defined by __MUTEX_TABLE__.\n */\n\n#include <stdint.h>\n#include <sysdef.h>\n#include <stdbool.h>\n#include <atomic_bit.h>\n\n/**\n * @typedef mutex_id_t\n * @brief A mutex object reference, as declared by MUTEX_INIT.\n */\ntypedef uint8_t *mutex_id_t;\n\n/**\n * @def MUTEX_GET\n * @hideinitializer\n * @brief Return the symbol to use when using the mutex associated to the given name.\n */\n#define MUTEX_GET(_name) _name\n\n/**\n * @def MUTEX_INIT\n * @hideinitializer\n * @brief Declare and initialize a mutex associated to the given name.\n */\n#define MUTEX_INIT(_name)                                                                                                        \\\n    ATOMIC_BIT_INIT(__CONCAT(mutex_, _name));                                                                                    \\\n    const mutex_id_t MUTEX_GET(_name) = &ATOMIC_BIT_GET(__CONCAT(mutex_, _name))\n\n/**\n * @fn mutex_lock\n * @brief Takes the lock on the given mutex.\n * @param mutex the mutex we want to lock\n */\nstatic inline void\nmutex_lock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"acquire %[mtx], 0, nz, .\" : : [mtx] \"r\"(mutex) :);\n}\n\n/**\n * @fn mutex_trylock\n * @brief Tries to take the lock on the given mutex. If the lock is already taken, returns immediately.\n * @param mutex the mutex we want to lock\n * @return Whether the mutex has been successfully locked.\n */\nstatic inline bool\nmutex_trylock(mutex_id_t mutex)\n{\n    bool result = true;\n    __asm__ volatile(\"acquire %[mtx], 0, z, .+2; move %[res], 0\" : [res] \"+r\"(result) : [mtx] \"r\"(mutex) :);\n    return result;\n}\n\n/**\n * @fn mutex_unlock\n * @brief Releases the lock on the given mutex.\n * @param mutex the mutex we want to unlock\n */\nstatic inline void\nmutex_unlock(mutex_id_t mutex)\n{\n    __asm__ volatile(\"release %[mtx], 0, nz, .+1\" : : [mtx] \"r\"(mutex) :);\n}\n\n#endif /* DPUSYSCORE_MUTEX_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/negdf2.c",
    "content": "//===-- lib/negdf2.c - double-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negdf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dneg(fp_t a)\n{\n    return __negdf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/negdi2.c",
    "content": "/* ===-- negdi2.c - Implement __negdi2 -------------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\nCOMPILER_RT_ABI di_int\n__negdi2(di_int a)\n{\n    /* Note: this routine is here for API compatibility; any sane compiler\n     * should expand it inline.\n     */\n    return -a;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/negsf2.c",
    "content": "//===-- lib/negsf2.c - single-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negsf2(fp_t a)\n{\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fneg(fp_t a)\n{\n    return __negsf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/negvdi2.c",
    "content": "/* ===-- negvdi2.c - Implement __negvdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI di_int\n__negvdi2(di_int a)\n{\n    const di_int MIN = (di_int)1 << ((int)(sizeof(di_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/negvsi2.c",
    "content": "/* ===-- negvsi2.c - Implement __negvsi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __negvsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: -a */\n\n/* Effects: aborts if -a overflows */\n\nCOMPILER_RT_ABI si_int\n__negvsi2(si_int a)\n{\n    const si_int MIN = (si_int)1 << ((int)(sizeof(si_int) * CHAR_BIT) - 1);\n    if (a == MIN)\n        compilerrt_abort();\n    return -a;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/paritydi2.c",
    "content": "/* ===-- paritydi2.c - Implement __paritydi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritydi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritydi2(di_int a)\n{\n    dwords x;\n    x.all = a;\n    return __paritysi2(x.s.high ^ x.s.low);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/paritysi2.c",
    "content": "/* ===-- paritysi2.c - Implement __paritysi2 -------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __paritysi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: 1 if number of bits is odd else returns 0 */\n\nCOMPILER_RT_ABI si_int\n__paritysi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x ^= x >> 16;\n    x ^= x >> 8;\n    x ^= x >> 4;\n    return (0x6996 >> (x & 0xF)) & 1;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/perfcounter.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <perfcounter.h>\n#include <attributes.h>\n\n#define BIT_IMPRECISION 4\n\nperfcounter_t\nperfcounter_get(void)\n{\n    uint32_t reg_value;\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(reg_value));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n\n#ifndef DPU_PROFILING\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value)\n{\n    uint32_t reg_value;\n    uint32_t reg_config = (reset_value ? 1 : 0) | (config << 1);\n    __asm__ volatile(\"time_cfg %[r], %[c]\" : [r] \"=r\"(reg_value) : [c] \"r\"(reg_config));\n    return ((perfcounter_t)reg_value) << BIT_IMPRECISION;\n}\n#endif /* !DPU_PROFILING */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/perfcounter.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PERFCOUNTER_H\n#define DPUSYSCORE_PERFCOUNTER_H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n/**\n * @file perfcounter.h\n * @brief Utilities concerning the performance counter register.\n *\n */\n\n/**\n * @typedef perfcounter_t\n * @brief A value which can be stored by the performance counter.\n */\ntypedef uint64_t perfcounter_t;\n\n/**\n * @enum perfcounter_config_t\n * @brief A configuration for the performance counter, defining what should be counted.\n *\n * @var COUNT_SAME          keep the previous configuration\n * @var COUNT_CYCLES        switch to counting clock cycles\n * @var COUNT_INSTRUCTIONS  switch to counting executed instructions\n * @var COUNT_NOTHING       does not count anything\n */\ntypedef enum _perfcounter_config_t {\n    COUNT_SAME = 0,\n    COUNT_CYCLES = 1,\n    COUNT_INSTRUCTIONS = 2,\n    COUNT_NOTHING = 3,\n} perfcounter_config_t;\n\n/**\n * @def CLOCKS_PER_SEC\n * @hideinitializer\n * @brief A number used to convert the value returned by the perfcounter_get and perfcounter_config functions into seconds,\n *        when counting clock cycles.\n */\nextern const volatile uint32_t CLOCKS_PER_SEC;\n\n/**\n * @fn perfcounter_get\n * @brief Fetch the value of the performance counter register.\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_get(void);\n\n#ifndef DPU_PROFILING\n/**\n * @fn perfcounter_config\n * @brief Configure the performance counter behavior.\n *\n * This function cannot be used when profiling an application.\n *\n * @param config        The new behavior for the performance counter register\n * @param reset_value   Whether the performance counter register should be set to 0\n *\n * @return The current value of the performance counter register, or undefined if perfcounter_config has not been called before.\n */\nperfcounter_t\nperfcounter_config(perfcounter_config_t config, bool reset_value);\n#else\n#define perfcounter_config(config, reset_value)                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* !DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PERFCOUNTER_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/popcountdi2.c",
    "content": "/* ===-- popcountdi2.c - Implement __popcountdi2 ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountdi2(di_int a)\n{\n    du_int x2 = (du_int)a;\n    x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL);\n    /* Every 2 bits holds the sum of every pair of bits (32) */\n    x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) */\n    x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) */\n    su_int x = (su_int)(x2 + (x2 >> 32));\n    /* The lower 32 bits hold four 16 bit sums (5 significant bits). */\n    /*   Upper 32 bits are garbage */\n    x = x + (x >> 16);\n    /* The lower 16 bits hold two 32 bit sums (6 significant bits). */\n    /*   Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000007F; /* (7 significant bits) */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/popcountsi2.c",
    "content": "/* ===-- popcountsi2.c - Implement __popcountsi2 ---------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __popcountsi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: count of 1 bits */\n\nCOMPILER_RT_ABI si_int\n__popcountsi2(si_int a)\n{\n    su_int x = (su_int)a;\n    x = x - ((x >> 1) & 0x55555555);\n    /* Every 2 bits holds the sum of every pair of bits */\n    x = ((x >> 2) & 0x33333333) + (x & 0x33333333);\n    /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) */\n    x = (x + (x >> 4)) & 0x0F0F0F0F;\n    /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) */\n    x = (x + (x >> 16));\n    /* The lower 16 bits hold two 8 bit sums (5 significant bits).*/\n    /*    Upper 16 bits are garbage */\n    return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/powidf2.c",
    "content": "/* ===-- powidf2.cpp - Implement __powidf2 ---------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powidf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI double\n__powidf2(double a, si_int b)\n{\n    const int recip = b < 0;\n    double r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/powisf2.c",
    "content": "/*===-- powisf2.cpp - Implement __powisf2 ---------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __powisf2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a ^ b */\n\nCOMPILER_RT_ABI float\n__powisf2(float a, si_int b)\n{\n    const int recip = b < 0;\n    float r = 1;\n    while (1) {\n        if (b & 1)\n            r *= a;\n        b /= 2;\n        if (b == 0)\n            break;\n        a *= a;\n    }\n    return recip ? 1 / r : r;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/profiling.c",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n#include <profiling.h>\n#include <defs.h>\n#include <dpufault.h>\n#include <dpuruntime.h>\n#include <macro_utils.h>\n#include <stdint.h>\n#include <sysdef.h>\n\n#ifdef DPU_PROFILING\nvoid __attribute__((no_instrument_function)) profiling_start(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] != PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_ALREADY_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->start[tid] = perfcounter_value;\n}\n\nvoid __attribute__((no_instrument_function)) profiling_stop(dpu_profiling_t *context)\n{\n    thread_id_t tid = me();\n    uint32_t perfcounter_value;\n\n    if (unlikely(context->start[tid] == PROFILING_RESET_VALUE)) {\n        __asm__(\"fault \" __STR(__FAULT_NOT_PROFILING__));\n        unreachable();\n    }\n\n    __asm__ volatile(\"time %[r]\" : [r] \"=r\"(perfcounter_value));\n    context->count[tid] += perfcounter_value - context->start[tid];\n    context->start[tid] = PROFILING_RESET_VALUE;\n}\n#endif /* DPU_PROFILING */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/profiling.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_PROFILING_H\n#define DPUSYSCORE_PROFILING_H\n\n/**\n * @file profiling.h\n * @brief Code section profiling management.\n */\n\n#include <attributes.h>\n#include <limits.h>\n#include <profiling_internals.h>\n\n#define PROFILING_RESET_VALUE (UINT32_MAX)\n\n/**\n * @def PROFILING_INIT\n * @hideinitializer\n * @brief Declare and initialize a profiling context associated to the given name.\n */\n#define PROFILING_INIT(_name)                                                                                                    \\\n    __section(\".dpu_profiling\") dpu_profiling_t _name = {                                                                        \\\n        .start = { [0 ...(NR_THREADS - 1)] = PROFILING_RESET_VALUE },                                                            \\\n        .count = { [0 ...(NR_THREADS - 1)] = 0 },                                                                                \\\n    }\n\n#ifdef DPU_PROFILING\n/**\n * @fn profiling_start\n * @brief Start profiling a code section.\n *\n * This function saves the perfcounter current value in the profiling context.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_start(dpu_profiling_t *context);\n\n/**\n * @fn profiling_stop\n * @brief Stop profiling a code section.\n *\n * This function gets the perfcounter current value and computes the number of cyles spent in the code section.\n * The profiling_start function must be called beforehand.\n *\n * @param context the profiling context to use.\n */\nvoid\nprofiling_stop(dpu_profiling_t *context);\n#else\n#define profiling_start(context)                                                                                                 \\\n    do {                                                                                                                         \\\n    } while (0)\n#define profiling_stop(context)                                                                                                  \\\n    do {                                                                                                                         \\\n    } while (0)\n#endif /* DPU_PROFILING */\n\n#endif /* DPUSYSCORE_PROFILING_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/profiling_internals.h",
    "content": "/* Copyright 2021 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/* Shared with backends */\n\n#ifndef DPUSYSCORE_PROFILING_INTERNALS_H\n#define DPUSYSCORE_PROFILING_INTERNALS_H\n\n/**\n * @file profiling_internals.h\n * @brief Code section profiling internals.\n */\n\n#include <stdint.h>\n\n#ifndef NR_THREADS\n#ifdef DPU_NR_THREADS\n#define NR_THREADS DPU_NR_THREADS\n#else\n#error \"DPU_NR_THREADS and NR_THREADS are undefined\"\n#endif /* DPU_NR_THREADS */\n#endif /* !NR_THREADS */\n\n/**\n * @typedef dpu_profiling_t\n * @brief A profiling context.\n */\ntypedef struct {\n    uint32_t start[NR_THREADS];\n    uint32_t count[NR_THREADS];\n} dpu_profiling_t;\n\n#endif /* DPUSYSCORE_PROFILING_INTERNALS_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/sem.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <sem.h>\n\n#include <defs.h>\n#include <dpuruntime.h>\n\nvoid\nsem_take(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    char count = sem->count - 1;\n    thread_id_t tid = me();\n\n    if (count < 0) {\n        unsigned char last = sem->wait_queue;\n\n        if (last != __EMPTY_WAIT_QUEUE) {\n            unsigned char first = __WAIT_QUEUE_TABLE[last];\n            __WAIT_QUEUE_TABLE[tid] = first;\n            __WAIT_QUEUE_TABLE[last] = tid;\n        } else {\n            __WAIT_QUEUE_TABLE[tid] = tid;\n        }\n\n        sem->wait_queue = tid;\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n        __stop();\n    } else {\n        sem->count = count;\n        __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n    }\n}\n\nvoid\nsem_give(struct sem_t *sem)\n{\n    unsigned char lock = sem->lock;\n    __acquire(lock, \"0\");\n    unsigned char count = sem->count + 1;\n    unsigned char last = sem->wait_queue;\n\n    if (last != __EMPTY_WAIT_QUEUE) {\n        unsigned char first = __WAIT_QUEUE_TABLE[last];\n\n        if (first == last) {\n            sem->wait_queue = __EMPTY_WAIT_QUEUE;\n        } else {\n            __WAIT_QUEUE_TABLE[last] = __WAIT_QUEUE_TABLE[first];\n        }\n\n        __resume(first, \"0\");\n    }\n\n    sem->count = count;\n    __release(lock, \"0\", __AT_NEXT_INSTRUCTION);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/sem.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEM_H\n#define DPUSYSCORE_SEM_H\n\n/**\n * @file sem.h\n * @brief Synchronization with semaphores.\n *\n * A semaphore is characterized by a counter and a wait queue. It provides two functions:\n *\n *   - Take: the counter is decremented by 1. If the counter is negative, the runtime is blocked (stop) and placed in the\n *     semaphore's wait queue, waiting to be resume by another runtime.\n *   - Give: the counter is incremented by 1. If the counter was negative before the increment, the runtime resumes the execution\n *     of the first runtime waiting in the waiting queue. In all the cases, the runtime continues its own execution.\n *\n */\n\n#include <attributes.h>\n#include <atomic_bit.h>\n#include <stdint.h>\n\n/**\n * @typedef sem_t\n * @brief A semaphore object, as declared by SEMAPHORE_INIT.\n */\ntypedef struct sem_t {\n    uint8_t wait_queue;\n    uint8_t count;\n    uint8_t initial_count;\n    uint8_t lock;\n} sem_t;\n\n/**\n * @def SEMAPHORE_INIT\n * @hideinitializer\n * @brief Declare and initialize a semaphore associated to the given name.\n */\n/* clang-format off */\n#define SEMAPHORE_INIT(_name, _counter)                                                                                          \\\n    _Static_assert((_counter < 128) && (_counter >= -127), \"semaphore counter must be encoded on a byte\");                       \\\n    ATOMIC_BIT_INIT(__CONCAT(semaphore_, _name));                                                                                \\\n    extern sem_t (_name);                                                                                                        \\\n    __asm__(\".section .data.\" __STR(_name) \"\\n\"                                                                                  \\\n            \".type \" __STR(_name) \",@object\\n\"                                                                                   \\\n            \".globl \" __STR(_name) \"\\n\"                                                                                          \\\n            \".p2align 2\\n\" __STR(_name) \":\\n\"                                                                                    \\\n            \".byte 0xFF\\n\"                                                                                                       \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(_counter) \"\\n\"                                                                                        \\\n            \".byte \" __STR(ATOMIC_BIT_GET(__CONCAT(semaphore_, _name))) \"\\n\"                                                     \\\n            \".size \" __STR(_name) \", 4\\n\"                                                                                        \\\n            \".text\");\n/* clang-format on */\n\n/**\n * @fn sem_take\n * @brief Takes one unit in the given semaphore (cf Take definition).\n * @param sem the semaphore we want to take\n */\nvoid\nsem_take(sem_t *sem);\n\n/**\n * @fn sem_give\n * @brief Gives on unit in the given semaphore (cf Give definition).\n * @param sem the semaphore we want to give\n */\nvoid\nsem_give(sem_t *sem);\n\n#endif /* DPUSYSCORE_SEM_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SEQREAD_H\n#define DPUSYSCORE_SEQREAD_H\n\n/**\n * @file seqread.h\n * @brief Sequential reading of items in MRAM.\n *\n * A sequential reader allows to parse a contiguous area in MRAM in sequence.\n * For example, if the MRAM contains an array of N structures, a sequential\n * reader on this array will automatically fetch the data into WRAM, thus\n * simplify the iterative loop on the elements.\n *\n * The size of cached area is defined by default but can be overriden by\n * defining this value in SEQREAD_CACHE_SIZE.\n *\n * The use of a sequential reader implies:\n *\n *  - first, to allocate some storage in WRAM to cache the items, using seqread_alloc.\n *  - then to initialize a reader on the MRAM area, via seqread_init\n *  - finally to iterate on the elements, invoking seqread_get whenever a new item is accessed.\n *\n */\n\n#include <stdint.h>\n#include <mram.h>\n#include <macro_utils.h>\n\n#ifndef SEQREAD_CACHE_SIZE\n/**\n * @def SEQREAD_CACHE_SIZE\n * @hideinitializer\n * @brief Size of caches used by seqread.\n */\n#define SEQREAD_CACHE_SIZE 256\n#endif\n\n_Static_assert(SEQREAD_CACHE_SIZE == 32 || SEQREAD_CACHE_SIZE == 64 || SEQREAD_CACHE_SIZE == 128 || SEQREAD_CACHE_SIZE == 256\n        || SEQREAD_CACHE_SIZE == 512 || SEQREAD_CACHE_SIZE == 1024,\n    \"seqread error: invalid cache size defined\");\n\n#define __SEQREAD_FCT(suffix) __CONCAT(__CONCAT(seqread, SEQREAD_CACHE_SIZE), suffix)\n#define __SEQREAD_ALLOC __SEQREAD_FCT(_alloc)\n#define __SEQREAD_INIT __SEQREAD_FCT(_init)\n#define __SEQREAD_GET __SEQREAD_FCT(_get)\n#define __SEQREAD_TELL __SEQREAD_FCT(_tell)\n#define __SEQREAD_SEEK __SEQREAD_FCT(_seek)\n\n/**\n * @typedef seqreader_buffer_t\n * @brief An buffer to use to initial a sequential reader.\n */\ntypedef uintptr_t seqreader_buffer_t;\n\n/**\n * @typedef seqreader_t\n * @brief An object used to perform sequential reading of MRAM.\n */\ntypedef struct {\n    seqreader_buffer_t wram_cache;\n    uintptr_t mram_addr;\n} seqreader_t;\n\nseqreader_buffer_t\n__SEQREAD_ALLOC();\n\n/**\n * @fn seqread_alloc\n * @brief Initializes an area in WRAM to cache the read buffers.\n *\n * Notice that this buffer can be re-used for different sequential reads,\n * as long as it is initialized each time to a new buffer in MRAM.\n *\n * @return A pointer to the allocated cache base address.\n */\n#define seqread_alloc __SEQREAD_ALLOC\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_init\n * @brief Creates a sequential reader.\n *\n * The reader is associated to an existing cache in WRAM, created with\n * seqread_alloc and a contiguous area of data in MRAM. The function\n * loads the first pages of data into the cache and provides a pointer\n * to the first byte in cache actually mapping the expected data.\n *\n * Notice that the provided MRAM address does not need to be aligned on\n * any constraint: the routine does the alignment automatically.\n *\n * @param cache the reader's cache in WRAM\n * @param mram_addr the buffer address in MRAM\n * @param reader the sequential reader to init to the supplied MRAM address\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_init __SEQREAD_INIT\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader);\n\n/**\n * @fn seqread_get\n * @brief Fetches the next item in a sequence.\n *\n * This operation basically consists in incrementing the pointer that goes\n * through the mapped area of memory. The function automatically reloads\n * data from cache if necessary.\n *\n * As a result, the provided pointer to the cache area is set to its new value.\n *\n * The provided increment must be less than SEQREAD_CACHE_SIZE. The reader's\n * behavior is undefined if the increment exceeds this value.\n *\n * @param ptr the incremented pointer\n * @param inc the number of bytes added to this pointer\n * @param reader a pointer to the sequential reader\n * @return The updated pointer value.\n */\n#define seqread_get __SEQREAD_GET\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader);\n\n/**\n * @fn seqread_seek\n * @brief Set the position of the cache to the supplied MRAM address\n *\n * Update automatically the cache if necessary.\n *\n * @param mram_addr the new buffer address in MRAM\n * @param reader a pointer to the sequential reader\n * @return A ptr to the first byte in cache corresponding to the MRAM address\n */\n#define seqread_seek __SEQREAD_SEEK\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader);\n\n/**\n * @fn seqread_tell\n * @brief Get the MRAM address corresponding to the supplied ptr in the cache\n *\n * @param ptr a pointer in the cache\n * @param reader a pointer to the sequential reader\n * @return A ptr to the MRAM address corresponding to the supplied pointer in the cache\n */\n#define seqread_tell __SEQREAD_TELL\n\n#endif /* DPUSYSCORE_SEQREAD_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread.inc",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <seqread.h>\n#include <mram.h>\n#include <dpuconst.h>\n#include <dpuruntime.h>\n#include <atomic_bit.h>\n#include <stddef.h>\n\n#define PAGE_SIZE (SEQREAD_CACHE_SIZE)\n#define PAGE_ALLOC_SIZE (2 * PAGE_SIZE)\n#define PAGE_OFF_MASK (PAGE_SIZE - 1)\n#define PAGE_IDX_MASK (~PAGE_OFF_MASK)\n\n#define MRAM_READ_PAGE(from, to) mram_read((__mram_ptr void *)(from), (void *)(to), PAGE_ALLOC_SIZE)\n\nextern void *\nmem_alloc_nolock(size_t size);\nATOMIC_BIT_EXTERN(__heap_pointer);\n\nseqreader_buffer_t\n__SEQREAD_ALLOC(void)\n{\n    ATOMIC_BIT_ACQUIRE(__heap_pointer);\n\n    unsigned int heap_pointer = __HEAP_POINTER;\n    seqreader_buffer_t pointer = (seqreader_buffer_t)((heap_pointer + PAGE_OFF_MASK) & PAGE_IDX_MASK);\n    size_t size = pointer + PAGE_ALLOC_SIZE - heap_pointer;\n    /* We already compute the return pointer\n     * mem_alloc_nolock is only used to really reserve the memory area in the heap */\n    mem_alloc_nolock(size);\n\n    ATOMIC_BIT_RELEASE(__heap_pointer);\n\n    return pointer;\n}\n\nvoid *\n__SEQREAD_INIT(seqreader_buffer_t cache, __mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    reader->wram_cache = cache;\n    reader->mram_addr = (uintptr_t)(1 << __DPU_MRAM_SIZE_LOG2);\n\n    return __SEQREAD_SEEK(mram_addr, reader);\n}\n\nvoid *\n__SEQREAD_GET(void *ptr, uint32_t inc, seqreader_t *reader)\n{\n    return (void *)__builtin_dpu_seqread_get((uintptr_t)ptr, inc, reader, PAGE_SIZE);\n}\n\nvoid *\n__SEQREAD_SEEK(__mram_ptr void *mram_addr, seqreader_t *reader)\n{\n    uintptr_t target_addr = (uintptr_t)mram_addr;\n    uintptr_t current_addr = (uintptr_t)reader->mram_addr;\n    uintptr_t wram_cache = (uintptr_t)reader->wram_cache;\n    uintptr_t mram_offset = target_addr - current_addr;\n    if ((mram_offset & PAGE_IDX_MASK) != 0) {\n        uintptr_t target_addr_idx_page = target_addr & PAGE_IDX_MASK;\n        MRAM_READ_PAGE(target_addr_idx_page, wram_cache);\n        mram_offset = target_addr & PAGE_OFF_MASK;\n        reader->mram_addr = target_addr_idx_page;\n    }\n    return (void *)(mram_offset + wram_cache);\n}\n\n__mram_ptr void *\n__SEQREAD_TELL(void *ptr, seqreader_t *reader)\n{\n    return (__mram_ptr void *)((uintptr_t)reader->mram_addr + ((uintptr_t)ptr & PAGE_OFF_MASK));\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread1024.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 1024\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread128.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 128\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread256.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 256\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread32.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 32\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread512.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 512\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/seqread64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#define SEQREAD_CACHE_SIZE 64\n#include <seqread.inc>\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/soft_cache.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <attributes.h>\n\nunsigned long __sw_cache_buffer[NR_THREADS] __dma_aligned __used;\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/soft_cache.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SOFT_CACHE_H\n#define DPUSYSCORE_SOFT_CACHE_H\n\n/**\n * @file soft_cache.h\n * @brief Software cache\n *\n * The software cache mechanism emulates a hardware cache to transparently load and store data from and to the\n * MRAM.\n *\n * This mechanism is quite slow, thus would only be used during the development process, to simplify the code.\n *\n * This module defines:\n *\n *  - A procedure to start the software cache, by creating a \"virtual TLB\" in the system, along with an area in WRAM to contain\n *    the cached MRAM pages\n *  - A procedure to flush the cache at the end of an execution, ensuring that the data in MRAM are consistent with the cached\n *    data\n *  - The special C directive \"__mram\", used to declare a pointer directly representing a buffer in MRAM.\n *\n * An MRAM pointer is mapped by the caching system. As a consequence, any access to data within this buffer is trapped\n * by a cache load or store procedure, transparently performing the required memory transactions to fetch and write back\n * the data.\n *\n */\n\n#include <attributes.h>\n\n#endif /* DPUSYSCORE_SOFT_CACHE_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/subdf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subdf3(fp_t a, fp_t b)\n{\n    return __adddf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_dsub(fp_t a, fp_t b)\n{\n    return __subdf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/subsf3.c",
    "content": "//===-- lib/subsf3.c - Single-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subsf3(fp_t a, fp_t b)\n{\n    return __addsf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI fp_t\n__aeabi_fsub(fp_t a, fp_t b)\n{\n    return __subsf3(a, b);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/subvdi3.c",
    "content": "/* ===-- subvdi3.c - Implement __subvdi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI di_int\n__subvdi3(di_int a, di_int b)\n{\n    di_int s = (du_int)a - (du_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/subvsi3.c",
    "content": "/* ===-- subvsi3.c - Implement __subvsi3 -----------------------------------===\n *\n *                The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __subvsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a - b */\n\n/* Effects: aborts if a - b overflows */\n\nCOMPILER_RT_ABI si_int\n__subvsi3(si_int a, si_int b)\n{\n    si_int s = (su_int)a - (su_int)b;\n    if (b >= 0) {\n        if (s > a)\n            compilerrt_abort();\n    } else {\n        if (s <= a)\n            compilerrt_abort();\n    }\n    return s;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/sysdef.h",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#ifndef DPUSYSCORE_SYSDEF_H\n#define DPUSYSCORE_SYSDEF_H\n\n/**\n * @file sysdef.h\n * @brief Provides useful system abstractions.\n */\n\n/**\n * @typedef thread_id_t\n * @brief A unique runtime number.\n */\ntypedef unsigned int thread_id_t;\n\n/**\n * @typedef sysname_t\n * @brief A system name.\n *\n * Used to name system structures, like mutexes, semaphores, meetpoints, etc... In practice, system names\n * are integers, representing a unique identifier for the given type of structure.\n */\ntypedef unsigned int sysname_t;\n\n#endif /* DPUSYSCORE_SYSDEF_H */\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/truncdfhf2.c",
    "content": "//===-- lib/truncdfhf2.c - double -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI uint16_t\n__truncdfhf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_d2h(double a)\n{\n    return __truncdfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/truncdfsf2.c",
    "content": "//===-- lib/truncdfsf2.c - double -> single conversion ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_DOUBLE\n#define DST_SINGLE\n#include \"fp_trunc_impl.inc\"\n\nCOMPILER_RT_ABI float\n__truncdfsf2(double a)\n{\n    return __truncXfYf2__(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI float\n__aeabi_d2f(double a)\n{\n    return __truncdfsf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/truncsfhf2.c",
    "content": "//===-- lib/truncsfhf2.c - single -> half conversion --------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE_LLVM.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n\n#define SRC_SINGLE\n#define DST_HALF\n#include \"fp_trunc_impl.inc\"\n\n// Use a forwarding definition and noinline to implement a poor man's alias,\n// as there isn't a good cross-platform way of defining one.\nCOMPILER_RT_ABI NOINLINE uint16_t\n__truncsfhf2(float a)\n{\n    return __truncXfYf2__(a);\n}\n\nCOMPILER_RT_ABI uint16_t\n__gnu_f2h_ieee(float a)\n{\n    return __truncsfhf2(a);\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI uint16_t\n__aeabi_f2h(float a)\n{\n    return __truncsfhf2(a);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/ucmpdi2.c",
    "content": "/* ===-- ucmpdi2.c - Implement __ucmpdi2 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ucmpdi2 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns:  if (a <  b) returns 0\n *           if (a == b) returns 1\n *           if (a >  b) returns 2\n */\n\nCOMPILER_RT_ABI si_int\n__ucmpdi2(du_int a, du_int b)\n{\n    udwords x;\n    x.all = a;\n    udwords y;\n    y.all = b;\n    if (x.s.high < y.s.high)\n        return 0;\n    if (x.s.high > y.s.high)\n        return 2;\n    if (x.s.low < y.s.low)\n        return 0;\n    if (x.s.low > y.s.low)\n        return 2;\n    return 1;\n}\n\n#ifdef __ARM_EABI__\n/* Returns: if (a <  b) returns -1\n *           if (a == b) returns  0\n *           if (a >  b) returns  1\n */\nCOMPILER_RT_ABI si_int\n__aeabi_ulcmp(di_int a, di_int b)\n{\n    return __ucmpdi2(a, b) - 1;\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/udiv64.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 multiplication unsigned division.\n */\n#include <stdint.h>\n#include <dpuruntime.h>\n\nstatic unsigned int\n__clz__(uint64_t x)\n{\n    return __builtin_clzl(x);\n}\n\nuint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder)\n{\n    uint64_t dxo = dividend, dxe = 0;\n\n    if (divider == 0)\n        goto division_by_zero;\n    if (divider > dividend) {\n        if (ask_remainder == 0)\n            return 0;\n        else\n            return dividend;\n    }\n\n    // Mimic the div_step.\n    /// div_step functionality:\n    //   if (Dxo >= (Ra<< #u5)) {\n    //     Dxo = Dxo - (Ra<< #u5);\n    //     Dxe = (Dxe << 1) | 1;\n    //   } else {\n    //     Dxe =  Dxe << 1;\n    //   }\n    int dividerl0 = __clz__(divider), dividendl0 = __clz__(dividend);\n\n    int i = dividerl0 - dividendl0;\n\n    for (; i >= 0; i--) {\n        uint64_t pivot = ((uint64_t)divider << i);\n        if (dxo >= pivot) {\n            dxo = dxo - pivot;\n            dxe = ((uint64_t)dxe << 1) | 1L;\n        } else {\n            dxe = (uint64_t)dxe << 1;\n        }\n    }\n    if (ask_remainder == 1)\n        return dxo;\n    else\n        return dxe;\n\ndivision_by_zero:\n    __asm__ volatile(\"fault \" __STR(__FAULT_DIVISION_BY_ZERO__));\n    unreachable();\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/udivdi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned division.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__udivdi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 0);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/udivmodsi4.c",
    "content": "/*===-- udivmodsi4.c - Implement __udivmodsi4 ------------------------------===\n *\n *                    The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivmodsi4 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b, *rem = a % b  */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__udivmodsi4(su_int a, su_int b, su_int *rem)\n{\n    unsigned long res = __udiv32(a, b);\n    *rem = (unsigned int)res;\n    return (unsigned int)(res >> 32);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/udivsi3.c",
    "content": "/* ===-- udivsi3.c - Implement __udivsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __udivsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a / b */\n\n/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */\n\n/* This function should not call __divsi3! */\nCOMPILER_RT_ABI su_int\n__udivsi3(su_int n, su_int d)\n{\n    const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT;\n    su_int q;\n    su_int r;\n    unsigned sr;\n    /* special cases */\n    if (d == 0)\n        return 0; /* ?! */\n    if (n == 0)\n        return 0;\n    sr = __builtin_clz(d) - __builtin_clz(n);\n    /* 0 <= sr <= n_uword_bits - 1 or sr large */\n    if (sr > n_uword_bits - 1) /* d > r */\n        return 0;\n    if (sr == n_uword_bits - 1) /* d == 1 */\n        return n;\n    ++sr;\n    /* 1 <= sr <= n_uword_bits - 1 */\n    /* Not a special case */\n    q = n << (n_uword_bits - sr);\n    r = n >> sr;\n    su_int carry = 0;\n    for (; sr > 0; --sr) {\n        /* r:q = ((r:q)  << 1) | carry */\n        r = (r << 1) | (q >> (n_uword_bits - 1));\n        q = (q << 1) | carry;\n        /* carry = 0;\n         * if (r.all >= d.all)\n         * {\n         *      r.all -= d.all;\n         *      carry = 1;\n         * }\n         */\n        const si_int s = (si_int)(d - r - 1) >> (n_uword_bits - 1);\n        carry = s & 1;\n        r -= d & s;\n    }\n    q = (q << 1) | carry;\n    return q;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI su_int\n__aeabi_uidiv(su_int n, su_int d)\n{\n    return __udivsi3(n, d);\n}\n#endif\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/umoddi3.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n/*\n * 64x64 unsigned remainder.\n *\n * This is the actual libcall implementation, as requested by the compiler.\n */\n#include <stdint.h>\nextern uint64_t\n__udiv64(uint64_t dividend, uint64_t divider, int ask_remainder);\n\nuint64_t\n__umoddi3(uint64_t dividend, uint64_t divider)\n{\n    return __udiv64(dividend, divider, 1);\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/umodsi3.c",
    "content": "/* ===-- umodsi3.c - Implement __umodsi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE_LLVM.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __umodsi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a % b */\n\nextern unsigned long\n__udiv32(unsigned int, unsigned int);\n\nCOMPILER_RT_ABI su_int\n__umodsi3(su_int a, su_int b)\n{\n    unsigned long res = __udiv32(a, b);\n    return (unsigned int)res;\n}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/sdk/syslib/waitqueue.c",
    "content": "/* Copyright 2020 UPMEM. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n */\n\n#include <dpuruntime.h>\n\nunsigned char __attribute__((used)) __sys_wq_table[NR_THREADS] = { [0 ...(NR_THREADS - 1)] = __EMPTY_WAIT_QUEUE };"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/binary/executable.py",
    "content": "import os\nfrom typing import List, Optional, Set, Union\n\nfrom abi.binary.liveness import Liveness\nfrom abi.binary.relocatable import Relocatable\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.label.label import Label\nfrom abi.section.section import Section\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom parser_.parser import Parser\n\n\nclass Executable:\n    def __init__(self, filepath: str, relocatable: Set[Relocatable]):\n        self._filepath: str = filepath\n        self._relocatables: Set[Relocatable] = relocatable\n        self._lines: str = self._init_lines()\n        self._liveness: Liveness = Liveness()\n        self._sections: Set[Section] = set()\n        self._cur_section: Optional[Section] = None\n\n    def filepath(self) -> str:\n        return self._filepath\n\n    def lines(self) -> str:\n        return self._lines\n\n    def liveness(self) -> Liveness:\n        return self._liveness\n\n    def sections(self, section_name: SectionName) -> Set[Section]:\n        sections: Set[Section] = set()\n        for section in self._sections:\n            if section.section_name() == section_name:\n                sections.add(section)\n        return sections\n\n    def section(self, section_name: SectionName, name: str) -> Optional[Section]:\n        for section in self._sections:\n            if section_name == section.section_name() and name == section.name():\n                return section\n        return None\n\n    def cur_section(self) -> Section:\n        assert self._cur_section is not None\n        return self._cur_section\n\n    def checkout_section(\n        self, section_name: SectionName, name: str, section_flags: Set[SectionFlag], section_type: SectionType,\n    ) -> None:\n        if self.section(section_name, name) is None:\n            self._sections.add(Section(section_name, name, section_flags, section_type))\n\n        section = self.section(section_name, name)\n        assert section is not None\n        self._cur_section = section\n        section.checkout_hidden_label()\n\n    def label(self, label_name: str) -> Optional[Label]:\n        for section in self._sections:\n            label = section.label(label_name)\n            if label is not None:\n                return label\n        return None\n\n    def labels(self) -> List[Label]:\n        labels: List[Label] = []\n        for section in self._sections:\n            labels += section.labels()\n        return labels\n\n    def cur_label(self) -> Label:\n        assert self._cur_section is not None\n        return self._cur_section.cur_label()\n\n    def append_label(self, label_name: str) -> None:\n        assert self._cur_section is not None\n        self._cur_section.append_label(label_name)\n\n    def append_assembler_instruction(\n        self,\n        assembler_instruction: Union[\n            AsciiDirective,\n            AscizDirective,\n            ByteDirective,\n            LongDirective,\n            QuadDirective,\n            ShortDirective,\n            ZeroDirective,\n            Instruction,\n        ],\n    ) -> None:\n        assert self._cur_section is not None\n        self._cur_section.append_assembler_instruction(assembler_instruction)\n\n    def _init_lines(self) -> str:\n        lines = \"\"\n        for relocatable in self._relocatables:\n            prefix = f\"{relocatable.filepath().split(os.path.sep)[-1].split('.')[0]}\"\n\n            with open(relocatable.filepath(), encoding=\"ISO-8859-1\") as file:\n                relocatable_lines = Parser.preprocess(\"\".join(file.readlines()))\n\n                if prefix != \"main\":\n                    for relocatable_local_symbols in relocatable.liveness().local_symbols():\n                        relocatable_lines = relocatable_lines.replace(\n                            f\"{relocatable_local_symbols},\", f\"{prefix}.{relocatable_local_symbols},\",\n                        )\n                        relocatable_lines = relocatable_lines.replace(\n                            f\"{relocatable_local_symbols} \", f\"{prefix}.{relocatable_local_symbols} \",\n                        )\n                        relocatable_lines = relocatable_lines.replace(\n                            f\"{relocatable_local_symbols}\\t\", f\"{prefix}.{relocatable_local_symbols}\\t\",\n                        )\n                        relocatable_lines = relocatable_lines.replace(\n                            f\"{relocatable_local_symbols}\\n\", f\"{prefix}.{relocatable_local_symbols}\\n\",\n                        )\n                        relocatable_lines = relocatable_lines.replace(\n                            f\"{relocatable_local_symbols}:\", f\"{prefix}.{relocatable_local_symbols}:\",\n                        )\n\n                lines += relocatable_lines\n        return lines\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/binary/liveness.py",
    "content": "from typing import Dict, Optional, Set\n\nfrom abi.label.symbol import Symbol\n\n\nclass Liveness:\n    def __init__(self):\n        self._def_uses: Dict[str, Set[str]] = {}\n        self._global_symbols: Set[str] = set()\n        self._symbols: Dict[str, Symbol] = {}\n        self._unresolved_symbols: Set[str] = set()\n\n        self._cur_def: Optional[str] = None\n\n    def defs(self) -> Set[str]:\n        return set(self._def_uses.keys())\n\n    def checkout_def(self, label_name: str) -> None:\n        self.add_def(label_name)\n        self._cur_def = label_name\n\n    def add_def(self, label_name: str) -> None:\n        if label_name not in self._def_uses:\n            self._def_uses[label_name] = set()\n\n            if label_name in self._unresolved_symbols:\n                self._unresolved_symbols.remove(label_name)\n\n    def uses(self, def_: str) -> Set[str]:\n        if def_ in self._def_uses:\n            return self._def_uses[def_].copy()\n        else:\n            return set()\n\n    def add_use(self, label_name: str) -> None:\n        assert self._cur_def is not None\n        self._def_uses[self._cur_def].add(label_name)\n\n        if label_name not in self._def_uses:\n            self._unresolved_symbols.add(label_name)\n\n    def global_symbols(self) -> Set[str]:\n        return self._global_symbols.copy()\n\n    def local_symbols(self) -> Set[str]:\n        local_symbols = self.defs()\n        for global_symbol in self.global_symbols():\n            local_symbols.remove(global_symbol)\n        return local_symbols\n\n    def symbol(self, symbol_name: str) -> Optional[Symbol]:\n        return self._symbols.get(symbol_name)\n\n    def add_global_symbol(self, symbol_name: str) -> None:\n        self._global_symbols.add(symbol_name)\n\n    def add_symbol(self, symbol_name: str, symbol: Symbol) -> None:\n        assert symbol_name not in self._symbols\n        self._symbols[symbol_name] = symbol\n\n    def unresolved_symbols(self) -> Set[str]:\n        return self._unresolved_symbols.copy()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/binary/relocatable.py",
    "content": "from abi.binary.liveness import Liveness\nfrom parser_.parser import Parser\n\n\nclass Relocatable:\n    def __init__(self, filepath: str):\n        self._filepath: str = filepath\n        self._lines: str = self._init_lines()\n        self._liveness: Liveness = Liveness()\n\n    def filepath(self) -> str:\n        return self._filepath\n\n    def lines(self) -> str:\n        return self._lines\n\n    def liveness(self) -> Liveness:\n        return self._liveness\n\n    def _init_lines(self) -> str:\n        with open(self._filepath, encoding=\"ISO-8859-1\") as file:\n            return Parser.preprocess(\"\".join(file.readlines()))\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/ascii_directive.py",
    "content": "class AsciiDirective:\n    def __init__(self, characters: str):\n        self._characters: str = characters\n\n    def characters(self) -> str:\n        return self._characters\n\n    def size(self) -> int:\n        return len(self._characters)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/asciz_directive.py",
    "content": "class AscizDirective:\n    def __init__(self, characters: str):\n        self._characters: str = characters\n\n    def characters(self) -> str:\n        return self._characters\n\n    def size(self) -> int:\n        return len(self._characters) + 1\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/byte_directive.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\n\n\nclass ByteDirective:\n    def __init__(self, value: int):\n        self._value: Immediate = Immediate(Representation.UNSIGNED, 8 * ByteDirective.size(), value)\n\n    def value(self) -> int:\n        return self._value.value()\n\n    @staticmethod\n    def size() -> int:\n        return 1\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/long_directive.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\n\n\nclass LongDirective:\n    def __init__(self, value: int):\n        self._value: Immediate = Immediate(Representation.UNSIGNED, 8 * LongDirective.size(), value)\n\n    def value(self) -> int:\n        return self._value.value()\n\n    @staticmethod\n    def size() -> int:\n        return 4\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/quad_directive.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\n\n\nclass QuadDirective:\n    def __init__(self, value: int):\n        self._value: Immediate = Immediate(Representation.UNSIGNED, 8 * QuadDirective.size(), value)\n\n    def value(self) -> int:\n        return self._value.value()\n\n    @staticmethod\n    def size() -> int:\n        return 8\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/short_directive.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\n\n\nclass ShortDirective:\n    def __init__(self, value: int):\n        self._value: Immediate = Immediate(Representation.UNSIGNED, 8 * ShortDirective.size(), value)\n\n    def value(self) -> int:\n        return self._value.value()\n\n    @staticmethod\n    def size() -> int:\n        return 2\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/directive/zero_directive.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\n\n\nclass ZeroDirective:\n    def __init__(self, size: int, value: int):\n        self._size: int = size\n        self._value: Immediate = Immediate(Representation.UNSIGNED, 8, value)\n\n    def size(self) -> int:\n        return self._size\n\n    def value(self) -> int:\n        return self._value.value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/_base_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.instruction.condition import Condition\n\n\nclass BaseCC:\n    def __init__(self, conditions: Set[Condition], condition: Condition):\n        assert condition in conditions\n        self._condition: Condition = condition\n\n    def condition(self):\n        return self._condition\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/acquire_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass AcquireCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(AcquireCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.Z, Condition.NZ, Condition.TRUE}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/add_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass AddNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            AddNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.C,\n            Condition.NC,\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.OV,\n            Condition.NOV,\n            Condition.PL,\n            Condition.MI,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.NC5,\n            Condition.NC6,\n            Condition.NC7,\n            Condition.NC8,\n            Condition.NC9,\n            Condition.NC10,\n            Condition.NC11,\n            Condition.NC12,\n            Condition.NC13,\n            Condition.NC14,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/boot_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass BootCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            BootCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.TRUE,\n            Condition.FALSE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/const_cc_ge0.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ConstCCGE0(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(ConstCCGE0.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.PL}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/const_cc_geu.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ConstCCGEU(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(ConstCCGEU.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.GEU}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/const_cc_zero.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ConstCCZero(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(ConstCCZero.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.Z}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/count_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass CountNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            CountNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.MAX,\n            Condition.NMAX,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/div_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass DivCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            DivCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.TRUE,\n            Condition.FALSE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/div_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass DivNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            DivNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/ext_sub_set_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ExtSubSetCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            ExtSubSetCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.C,\n            Condition.NC,\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.OV,\n            Condition.NOV,\n            Condition.EQ,\n            Condition.NEQ,\n            Condition.PL,\n            Condition.MI,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.GES,\n            Condition.GEU,\n            Condition.GTS,\n            Condition.GTU,\n            Condition.LES,\n            Condition.LEU,\n            Condition.LTS,\n            Condition.LTU,\n            Condition.XGTS,\n            Condition.XGTU,\n            Condition.XLES,\n            Condition.XLEU,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/false_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass FalseCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(FalseCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.FALSE}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/imm_shift_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ImmShiftNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            ImmShiftNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.E,\n            Condition.O,\n            Condition.PL,\n            Condition.MI,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.SE,\n            Condition.SO,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/log_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass LogNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            LogNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.PL,\n            Condition.MI,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/log_set_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass LogSetCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(LogSetCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.Z, Condition.NZ, Condition.XZ, Condition.XNZ}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/mul_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass MulNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            MulNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.LARGE,\n            Condition.SMALL,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/no_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass NoCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(NoCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return set()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/release_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ReleaseCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(ReleaseCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.NZ}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/shift_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass ShiftNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            ShiftNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.E,\n            Condition.O,\n            Condition.PL,\n            Condition.MI,\n            Condition.SZ,\n            Condition.SNZ,\n            Condition.SE,\n            Condition.SO,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.SH32,\n            Condition.NSH32,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/sub_nz_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass SubNZCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            SubNZCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.C,\n            Condition.NC,\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.OV,\n            Condition.NOV,\n            Condition.MI,\n            Condition.PL,\n            Condition.EQ,\n            Condition.NEQ,\n            Condition.SPL,\n            Condition.SMI,\n            Condition.GES,\n            Condition.GEU,\n            Condition.GTS,\n            Condition.GTU,\n            Condition.LES,\n            Condition.LEU,\n            Condition.LTS,\n            Condition.LTU,\n            Condition.XGTS,\n            Condition.XGTU,\n            Condition.XLES,\n            Condition.XLEU,\n            Condition.TRUE,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/sub_set_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass SubSetCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(\n            SubSetCC.conditions(), condition,\n        )\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {\n            Condition.Z,\n            Condition.NZ,\n            Condition.XZ,\n            Condition.XNZ,\n            Condition.EQ,\n            Condition.NEQ,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/true_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass TrueCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(TrueCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.TRUE}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/cc/true_false_cc.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc._base_cc import BaseCC\nfrom abi.isa.instruction.condition import Condition\n\n\nclass TrueFalseCC(BaseCC):\n    def __init__(self, condition: Condition):\n        super().__init__(TrueFalseCC.conditions(), condition)\n\n    @staticmethod\n    def conditions() -> Set[Condition]:\n        return {Condition.TRUE, Condition.FALSE}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/exception.py",
    "content": "from enum import Enum, auto\n\n\nclass Exception_(Enum):\n    MEMORY_FAULT = 0\n    DMA_FAULT = auto()\n    HEAP_FULL = auto()\n    DIVISION_BY_ZERO = auto()\n    ASSERT = auto()\n    HALT = auto()\n    PRINT_OVERFLOW = auto()\n    ALREADY_PROFILING = auto()\n    NOT_PROFILING = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/flag.py",
    "content": "from enum import Enum, auto\n\n\nclass Flag(Enum):\n    ZERO = 0\n    CARRY = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/instruction/condition.py",
    "content": "from enum import Enum, auto\n\n\nclass Condition(Enum):\n    # condition is always true, whatever the operation result is\n    TRUE = 0\n\n    # condition is always false, whatever the operation result is\n    FALSE = auto()\n\n    # operation result equals zero\n    Z = auto()\n\n    # operation result does not equal zero\n    NZ = auto()\n\n    # operation result is even\n    E = auto()\n\n    # operation result is odd\n    # trunk-ignore(flake8/E741)\n    O = auto()\n\n    # operation result is greater or equal to zero\n    PL = auto()\n\n    # operation result is strictly lower than zero\n    MI = auto()\n\n    # operation result has overflow set\n    OV = auto()\n\n    # operation result does not have overflow set\n    NOV = auto()\n\n    # operation result has carry set\n    C = auto()\n\n    # operation result does not have carry set\n    NC = auto()\n\n    # source register operand is equal to zero\n    SZ = auto()\n\n    # source register operand is not equal to zero\n    SNZ = auto()\n\n    # source register operand is positive or null\n    SPL = auto()\n\n    # source register operand is strictly negative\n    SMI = auto()\n\n    # source register operand is odd\n    SO = auto()\n\n    # source register operand is even\n    SE = auto()\n\n    # NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 operation result set the\n    # carry flag number 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 respectively.\n    # these conditions may come in handy to quickly detect buffer overflows.\n    NC5 = auto()\n    NC6 = auto()\n    NC7 = auto()\n    NC8 = auto()\n    NC9 = auto()\n    NC10 = auto()\n    NC11 = auto()\n    NC12 = auto()\n    NC13 = auto()\n    NC14 = auto()\n\n    # operation is a bit count and the result is the maximum count value\n    MAX = auto()\n\n    # operation is a bit count and the result is not the maximum count value\n    NMAX = auto()\n\n    # second operand is a register with a value having bit number 5 equal to one\n    SH32 = auto()\n\n    # second operand is a register with a value having bit number 5 equal to zero\n    NSH32 = auto()\n\n    # first operand is equal to the second operand\n    EQ = auto()\n\n    # first operand is different from the second operand\n    NEQ = auto()\n\n    # first operand is respectively lower than, lower or equal to, greater than,\n    # greater or equal to the second operand when performing an unsigned comparison\n    LTU = auto()\n    LEU = auto()\n    GTU = auto()\n    GEU = auto()\n\n    # first operand of is respectively lower than, lower or equal to, greater\n    # than, greater or equal to the second operand when performing a signed\n    # comparison\n    LTS = auto()\n    LES = auto()\n    GTS = auto()\n    GES = auto()\n\n    # operation result is null and ZeroFlag is set\n    XZ = auto()\n\n    # operation result is not null or ZeroFlag is not set\n    XNZ = auto()\n\n    # either operation result holds carry flag or ZeroFlag is set\n    XLEU = auto()\n\n    # operation result holds carry flag and ZeroFlag is not set\n    XGTU = auto()\n\n    # ZeroFLag is set and either operation result is negative or overflows\n    XLES = auto()\n\n    # ZeroFlag is not set and either operation result is positive or null or overflows\n    XGTS = auto()\n\n    # operation is an 8x8 multiplication and the result is a less than 256\n    SMALL = auto()\n\n    # operation is an 8x8 multiplication and the result is greater than 255\n    LARGE = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/instruction/endian.py",
    "content": "from enum import Enum, auto\n\n\nclass Endian(Enum):\n    LITTLE = 0\n    BIG = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/instruction/instruction.py",
    "content": "from typing import Optional, Union\n\nfrom abi.isa.cc.acquire_cc import AcquireCC\nfrom abi.isa.cc.add_nz_cc import AddNZCC\nfrom abi.isa.cc.boot_cc import BootCC\nfrom abi.isa.cc.count_nz_cc import CountNZCC\nfrom abi.isa.cc.div_cc import DivCC\nfrom abi.isa.cc.div_nz_cc import DivNZCC\nfrom abi.isa.cc.ext_sub_set_cc import ExtSubSetCC\nfrom abi.isa.cc.false_cc import FalseCC\nfrom abi.isa.cc.imm_shift_nz_cc import ImmShiftNZCC\nfrom abi.isa.cc.log_nz_cc import LogNZCC\nfrom abi.isa.cc.log_set_cc import LogSetCC\nfrom abi.isa.cc.mul_nz_cc import MulNZCC\nfrom abi.isa.cc.release_cc import ReleaseCC\nfrom abi.isa.cc.shift_nz_cc import ShiftNZCC\nfrom abi.isa.cc.sub_nz_cc import SubNZCC\nfrom abi.isa.cc.sub_set_cc import SubSetCC\nfrom abi.isa.cc.true_cc import TrueCC\nfrom abi.isa.cc.true_false_cc import TrueFalseCC\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.endian import Endian\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.isa.register.pair_register import PairRegister\nfrom abi.isa.register.sp_register import SPRegister\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass Instruction:\n    DestinationRegister = Union[GPRegister, SPRegister]\n    SourceRegister = Union[GPRegister, SPRegister]\n\n    AcquireRICIOpCodes = {OpCode.ACQUIRE}\n    ReleaseRICIOpCodes = {OpCode.RELEASE}\n    BootRICIOpCodes = {OpCode.BOOT, OpCode.RESUME}\n    RICIOpCodes = {*AcquireRICIOpCodes, *ReleaseRICIOpCodes, *BootRICIOpCodes}\n\n    AddRRIOpCodes = {OpCode.ADD, OpCode.ADDC, OpCode.AND, OpCode.OR, OpCode.XOR}\n    AsrRRIOpCodes = {\n        OpCode.ASR,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.ROL,\n        OpCode.ROR,\n    }\n    CallRRIOpCodes = {OpCode.CALL}\n    RRIOpCodes = {*AddRRIOpCodes, *AsrRRIOpCodes, *CallRRIOpCodes}\n\n    AddRRICOpCodes = {\n        OpCode.ADD,\n        OpCode.ADDC,\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.XOR,\n        OpCode.HASH,\n    }\n    AsrRRICOpCodes = {\n        OpCode.ASR,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.ROL,\n        OpCode.ROR,\n    }\n    SubRRICOpCodes = {OpCode.SUB, OpCode.SUBC}\n    RRICOpCodes = {*AddRRICOpCodes, *AsrRRICOpCodes, *SubRRICOpCodes}\n\n    AddRRICIOpCodes = {OpCode.ADD, OpCode.ADDC}\n    AndRRICIOpCodes = {\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.XOR,\n        OpCode.HASH,\n    }\n    AsrRRICIOpCodes = {\n        OpCode.ASR,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.ROL,\n        OpCode.ROR,\n    }\n    SubRRICIOpCodes = {OpCode.SUB, OpCode.SUBC}\n    RRICIOpCodes = {\n        *AddRRICIOpCodes,\n        *AndRRICIOpCodes,\n        *AsrRRICIOpCodes,\n        *SubRRICIOpCodes,\n    }\n\n    RRIFOpCodes = {\n        OpCode.ADD,\n        OpCode.ADDC,\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.SUB,\n        OpCode.SUBC,\n        OpCode.XOR,\n        OpCode.HASH,\n    }\n\n    RRROpCodes = {\n        OpCode.ADD,\n        OpCode.ADDC,\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.ASR,\n        OpCode.CMPB4,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.MUL_SH_SH,\n        OpCode.MUL_SH_SL,\n        OpCode.MUL_SH_UH,\n        OpCode.MUL_SH_UL,\n        OpCode.MUL_SL_SH,\n        OpCode.MUL_SL_SL,\n        OpCode.MUL_SL_UH,\n        OpCode.MUL_SL_UL,\n        OpCode.MUL_UH_UH,\n        OpCode.MUL_UH_UL,\n        OpCode.MUL_UL_UH,\n        OpCode.MUL_UL_UL,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.ROL,\n        OpCode.ROR,\n        OpCode.RSUB,\n        OpCode.RSUBC,\n        OpCode.SUB,\n        OpCode.SUBC,\n        OpCode.XOR,\n        OpCode.HASH,\n        OpCode.CALL,\n    }\n\n    AddRRRCOpCodes = {\n        OpCode.ADD,\n        OpCode.ADDC,\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.ASR,\n        OpCode.CMPB4,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.MUL_SH_SH,\n        OpCode.MUL_SH_SL,\n        OpCode.MUL_SH_UH,\n        OpCode.MUL_SH_UL,\n        OpCode.MUL_SL_SH,\n        OpCode.MUL_SL_SL,\n        OpCode.MUL_SL_UH,\n        OpCode.MUL_SL_UL,\n        OpCode.MUL_UH_UH,\n        OpCode.MUL_UH_UL,\n        OpCode.MUL_UL_UH,\n        OpCode.MUL_UL_UL,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.ROL,\n        OpCode.ROR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.XOR,\n        OpCode.HASH,\n        OpCode.CALL,\n    }\n    RsubRRRCOpCodes = {OpCode.RSUB, OpCode.RSUBC}\n    SubRRRCOpCodes = {OpCode.SUB, OpCode.SUBC}\n    RRRCOpCodes = {*AddRRRCOpCodes, *RsubRRRCOpCodes, *SubRRRCOpCodes}\n\n    AddRRRCIOpCodes = {OpCode.ADD, OpCode.ADDC}\n    AndRRRCIOpCodes = {\n        OpCode.AND,\n        OpCode.ANDN,\n        OpCode.NAND,\n        OpCode.NOR,\n        OpCode.NXOR,\n        OpCode.OR,\n        OpCode.ORN,\n        OpCode.XOR,\n        OpCode.HASH,\n    }\n    AsrRRRCIOpCodes = {\n        OpCode.ASR,\n        OpCode.CMPB4,\n        OpCode.LSL,\n        OpCode.LSL1,\n        OpCode.LSL1X,\n        OpCode.LSLX,\n        OpCode.LSR,\n        OpCode.LSR1,\n        OpCode.LSR1X,\n        OpCode.LSRX,\n        OpCode.ROL,\n        OpCode.ROR,\n    }\n    MulRRRCIOpCodes = {\n        OpCode.MUL_SH_SH,\n        OpCode.MUL_SH_SL,\n        OpCode.MUL_SH_UH,\n        OpCode.MUL_SH_UL,\n        OpCode.MUL_SL_SH,\n        OpCode.MUL_SL_SL,\n        OpCode.MUL_SL_UH,\n        OpCode.MUL_SL_UL,\n        OpCode.MUL_UH_UH,\n        OpCode.MUL_UH_UL,\n        OpCode.MUL_UL_UH,\n        OpCode.MUL_UL_UL,\n    }\n    RsubRRRCIOpCodes = {OpCode.RSUB, OpCode.RSUBC, OpCode.SUB, OpCode.SUBC}\n    RRRCIOpCodes = {\n        *AddRRRCIOpCodes,\n        *AndRRRCIOpCodes,\n        *AsrRRRCIOpCodes,\n        *RsubRRRCIOpCodes,\n    }\n\n    RROpCodes = {\n        OpCode.CAO,\n        OpCode.CLO,\n        OpCode.CLS,\n        OpCode.CLZ,\n        OpCode.EXTSB,\n        OpCode.EXTSH,\n        OpCode.EXTUB,\n        OpCode.EXTUH,\n        OpCode.SATS,\n        OpCode.TIME_CFG,\n    }\n\n    RRCOpCodes = {\n        OpCode.CAO,\n        OpCode.CLO,\n        OpCode.CLS,\n        OpCode.CLZ,\n        OpCode.EXTSB,\n        OpCode.EXTSH,\n        OpCode.EXTUB,\n        OpCode.EXTUH,\n        OpCode.SATS,\n    }\n\n    CaoRRCIOpCodes = {OpCode.CAO, OpCode.CLO, OpCode.CLS, OpCode.CLZ}\n    ExtsbRRCIOpCodes = {\n        OpCode.EXTSB,\n        OpCode.EXTSH,\n        OpCode.EXTUB,\n        OpCode.EXTUH,\n        OpCode.SATS,\n    }\n    TimeCfgRRCIOpCodes = {OpCode.TIME_CFG}\n    RRCIOpCodes = {*CaoRRCIOpCodes, *ExtsbRRCIOpCodes, *TimeCfgRRCIOpCodes}\n\n    DivStepDRDICIOpCodes = {OpCode.DIV_STEP}\n    MulStepDRDICIOpCodes = {OpCode.MUL_STEP}\n    DRDICIOpCodes = {*DivStepDRDICIOpCodes, *MulStepDRDICIOpCodes}\n\n    RRRIOpCodes = {OpCode.LSL_ADD, OpCode.LSL_SUB, OpCode.LSR_ADD, OpCode.ROL_ADD}\n    RRRICIOpCodes = {OpCode.LSL_ADD, OpCode.LSL_SUB, OpCode.LSR_ADD, OpCode.ROL_ADD}\n\n    RIROpCodes = {OpCode.SUB, OpCode.SUBC}\n    RIRCOpCodes = {OpCode.SUB, OpCode.SUBC}\n    RIRCIOpCodes = {OpCode.SUB, OpCode.SUBC}\n\n    ROpCodes = {OpCode.TIME}\n    RCIOpCodes = {OpCode.TIME}\n\n    CIOpCodes = {OpCode.STOP}\n    IOpCodes = {OpCode.FAULT}\n    DDCIOpCodes = {OpCode.MOVD, OpCode.SWAPD}\n\n    ERRIOpCodes = {OpCode.LBS, OpCode.LBU, OpCode.LHS, OpCode.LHU, OpCode.LW}\n    EDRIOpCodes = {OpCode.LD}\n\n    ERIIOpCodes = {\n        OpCode.SB,\n        OpCode.SB_ID,\n        OpCode.SD,\n        OpCode.SD_ID,\n        OpCode.SH,\n        OpCode.SH_ID,\n        OpCode.SW,\n        OpCode.SW_ID,\n        OpCode.SD,\n        OpCode.SD_ID,\n    }\n    ERIROpCodes = {OpCode.SB, OpCode.SH, OpCode.SW}\n    ERIDOpCodes = {OpCode.SD}\n\n    DMARRIOpCodes = {OpCode.LDMA, OpCode.LDMAI, OpCode.SDMA}\n\n    def __init__(\n        self,\n        op_code: OpCode,\n        suffix: Suffix,\n        rc: Optional[DestinationRegister] = None,\n        ra: Optional[SourceRegister] = None,\n        rb: Optional[SourceRegister] = None,\n        dc: Optional[PairRegister] = None,\n        db: Optional[PairRegister] = None,\n        condition: Optional[Condition] = None,\n        imm: Optional[int] = None,\n        off: Optional[int] = None,\n        pc: Optional[int] = None,\n        endian: Optional[Endian] = None,\n    ):\n        self._op_code: OpCode = op_code\n        self._suffix: Suffix = suffix\n        self._rc: Union[GPRegister, SPRegister, None] = None\n        self._ra: Union[GPRegister, SPRegister, None] = None\n        self._rb: Union[GPRegister, SPRegister, None] = None\n        self._dc: Optional[PairRegister] = None\n        self._db: Optional[PairRegister] = None\n        self._condition: Optional[Condition] = None\n        self._imm: Optional[Immediate] = None\n        self._pc: Optional[Immediate] = None\n        self._off: Optional[Immediate] = None\n        self._endian: Optional[Endian] = None\n\n        self._init_instruction(rc, ra, rb, dc, db, condition, imm, off, pc, endian)\n\n    def op_code(self) -> OpCode:\n        return self._op_code\n\n    def suffix(self) -> Suffix:\n        return self._suffix\n\n    def rc(self) -> Union[GPRegister, SPRegister]:\n        assert self._rc is not None\n        return self._rc\n\n    def ra(self) -> Union[GPRegister, SPRegister]:\n        assert self._ra is not None\n        return self._ra\n\n    def rb(self) -> Union[GPRegister, SPRegister]:\n        assert self._rb is not None\n        return self._rb\n\n    def dc(self) -> PairRegister:\n        assert self._dc is not None\n        return self._dc\n\n    def db(self) -> PairRegister:\n        assert self._db is not None\n        return self._db\n\n    def condition(self) -> Condition:\n        assert self._condition is not None\n        return self._condition\n\n    def imm(self) -> Immediate:\n        assert self._imm is not None\n        return self._imm\n\n    def off(self) -> Immediate:\n        assert self._off is not None\n        return self._off\n\n    def pc(self) -> Immediate:\n        assert self._pc is not None\n        return self._pc\n\n    def endian(self) -> Endian:\n        assert self._endian is not None\n        return self._endian\n\n    def _init_instruction(\n        self,\n        rc: Optional[DestinationRegister],\n        ra: Optional[SourceRegister],\n        rb: Optional[SourceRegister],\n        dc: Optional[PairRegister],\n        db: Optional[PairRegister],\n        condition: Optional[Condition],\n        imm: Optional[int],\n        off: Optional[int],\n        pc: Optional[int],\n        endian: Optional[Endian],\n    ) -> None:\n        if self._suffix == Suffix.RICI:\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rici(ra, imm, condition, pc)\n        elif self._suffix == Suffix.RRI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert imm is not None\n\n            self._init_rri(rc, ra, imm)\n        elif self._suffix == Suffix.RRIC:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_rric(rc, ra, imm, condition)\n        elif self._suffix == Suffix.RRICI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rrici(rc, ra, imm, condition, pc)\n        elif self._suffix == Suffix.RRIF:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_rrif(rc, ra, imm, condition)\n        elif self._suffix == Suffix.RRR:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert rb is not None\n\n            self._init_rrr(rc, ra, rb)\n        elif self._suffix == Suffix.RRRC:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n\n            self._init_rrrc(rc, ra, rb, condition)\n        elif self._suffix == Suffix.RRRCI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rrrci(rc, ra, rb, condition, pc)\n        elif self._suffix == Suffix.ZRI:\n            assert ra is not None\n            assert imm is not None\n\n            self._init_zri(ra, imm)\n        elif self._suffix == Suffix.ZRIC:\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_zric(ra, imm, condition)\n        elif self._suffix == Suffix.ZRICI:\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zrici(ra, imm, condition, pc)\n        elif self._suffix == Suffix.ZRIF:\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_zrif(ra, imm, condition)\n        elif self._suffix == Suffix.ZRR:\n            assert ra is not None\n            assert rb is not None\n\n            self._init_zrr(ra, rb)\n        elif self._suffix == Suffix.ZRRC:\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n\n            self._init_zrrc(ra, rb, condition)\n        elif self._suffix == Suffix.ZRRCI:\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zrrci(ra, rb, condition, pc)\n        elif self._suffix == Suffix.S_RRI or self._suffix == Suffix.U_RRI:\n            assert dc is not None\n            assert ra is not None\n            assert imm is not None\n\n            self._init_s_rri(dc, ra, imm)\n        elif self._suffix == Suffix.S_RRIC or self._suffix == Suffix.U_RRIC:\n            assert dc is not None\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_s_rric(dc, ra, imm, condition)\n        elif self._suffix == Suffix.S_RRICI or self._suffix == Suffix.U_RRICI:\n            assert dc is not None\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rrici(dc, ra, imm, condition, pc)\n        elif self._suffix == Suffix.S_RRIF or self._suffix == Suffix.U_RRIF:\n            assert dc is not None\n            assert ra is not None\n            assert imm is not None\n            assert condition is not None\n\n            self._init_s_rrif(dc, ra, imm, condition)\n        elif self._suffix == Suffix.S_RRR or self._suffix == Suffix.U_RRR:\n            assert dc is not None\n            assert ra is not None\n            assert rb is not None\n\n            self._init_s_rrr(dc, ra, rb)\n        elif self._suffix == Suffix.S_RRRC or self._suffix == Suffix.U_RRRC:\n            assert dc is not None\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n\n            self._init_s_rrrc(dc, ra, rb, condition)\n        elif self._suffix == Suffix.S_RRRCI or self._suffix == Suffix.U_RRRCI:\n            assert dc is not None\n            assert ra is not None\n            assert rb is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rrrci(dc, ra, rb, condition, pc)\n        elif self._suffix == Suffix.RR:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n\n            self._init_rr(rc, ra)\n        elif self._suffix == Suffix.RRC:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert condition is not None\n\n            self._init_rrc(rc, ra, condition)\n        elif self._suffix == Suffix.RRCI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rrci(rc, ra, condition, pc)\n        elif self._suffix == Suffix.ZR:\n            assert ra is not None\n\n            self._init_zr(ra)\n        elif self._suffix == Suffix.ZRC:\n            assert ra is not None\n            assert condition is not None\n\n            self._init_zrc(ra, condition)\n        elif self._suffix == Suffix.ZRCI:\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zrci(ra, condition, pc)\n        elif self._suffix == Suffix.S_RR or self._suffix == Suffix.U_RR:\n            assert dc is not None\n            assert ra is not None\n\n            self._init_s_rr(dc, ra)\n        elif self._suffix == Suffix.S_RRC or self._suffix == Suffix.U_RRC:\n            assert dc is not None\n            assert ra is not None\n            assert condition is not None\n\n            self._init_s_rrc(dc, ra, condition)\n        elif self._suffix == Suffix.S_RRCI or self._suffix == Suffix.U_RRCI:\n            assert dc is not None\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rrci(dc, ra, condition, pc)\n        elif self._suffix == Suffix.DRDICI:\n            assert dc is not None\n            assert ra is not None\n            assert db is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_drdici(dc, ra, db, imm, condition, pc)\n        elif self._suffix == Suffix.RRRI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n\n            self._init_rrri(rc, ra, rb, imm)\n        elif self._suffix == Suffix.RRRICI:\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rrrici(rc, ra, rb, imm, condition, pc)\n        elif self._suffix == Suffix.ZRRI:\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n\n            self._init_zrri(ra, rb, imm)\n        elif self._suffix == Suffix.ZRRICI:\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zrrici(ra, rb, imm, condition, pc)\n        elif self._suffix == Suffix.S_RRRI or self._suffix == Suffix.U_RRRI:\n            assert dc is not None\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n\n            self._init_s_rrri(dc, ra, rb, imm)\n        elif self._suffix == Suffix.S_RRRICI or self._suffix == Suffix.U_RRRICI:\n            assert dc is not None\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rrrici(dc, ra, rb, imm, condition, pc)\n        elif self._suffix == Suffix.RIR:\n            assert isinstance(rc, GPRegister)\n            assert imm is not None\n            assert ra is not None\n\n            self._init_rir(rc, imm, ra)\n        elif self._suffix == Suffix.RIRC:\n            assert isinstance(rc, GPRegister)\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n\n            self._init_rirc(rc, imm, ra, condition)\n        elif self._suffix == Suffix.RIRCI:\n            assert isinstance(rc, GPRegister)\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rirci(rc, imm, ra, condition, pc)\n        elif self._suffix == Suffix.ZIR:\n            assert imm is not None\n            assert ra is not None\n\n            self._init_zir(imm, ra)\n        elif self._suffix == Suffix.ZIRC:\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n\n            self._init_zirc(imm, ra, condition)\n        elif self._suffix == Suffix.ZIRCI:\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zirci(imm, ra, condition, pc)\n        elif self._suffix == Suffix.S_RIRC or self._suffix == Suffix.U_RIRC:\n            assert dc is not None\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n\n            self._init_s_rirc(dc, imm, ra, condition)\n        elif self._suffix == Suffix.S_RIRCI or self._suffix == Suffix.U_RIRCI:\n            assert dc is not None\n            assert imm is not None\n            assert ra is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rirci(dc, imm, ra, condition, pc)\n        elif self._suffix == Suffix.R:\n            assert isinstance(rc, GPRegister)\n\n            self._init_r(rc)\n        elif self._suffix == Suffix.RCI:\n            assert isinstance(rc, GPRegister)\n            assert condition is not None\n            assert pc is not None\n\n            self._init_rci(rc, condition, pc)\n        elif self._suffix == Suffix.Z:\n            self._init_z()\n        elif self._suffix == Suffix.ZCI:\n            assert condition is not None\n            assert pc is not None\n\n            self._init_zci(condition, pc)\n        elif self._suffix == Suffix.S_R or self._suffix == Suffix.U_R:\n            assert dc is not None\n\n            self._init_s_r(dc)\n        elif self._suffix == Suffix.S_RCI or self._suffix == Suffix.U_RCI:\n            assert dc is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_s_rci(dc, condition, pc)\n        elif self._suffix == Suffix.CI:\n            assert condition is not None\n            assert pc is not None\n\n            self._init_ci(condition, pc)\n        elif self._suffix == Suffix.I:\n            assert imm is not None\n\n            self._init_i(imm)\n        elif self._suffix == Suffix.DDCI:\n            assert dc is not None\n            assert db is not None\n            assert condition is not None\n            assert pc is not None\n\n            self._init_ddci(dc, db, condition, pc)\n        elif self._suffix == Suffix.ERRI:\n            assert endian is not None\n            assert isinstance(rc, GPRegister)\n            assert ra is not None\n            assert off is not None\n\n            self._init_erri(endian, rc, ra, off)\n        elif self._suffix == Suffix.S_ERRI or self._suffix == Suffix.U_ERRI:\n            assert endian is not None\n            assert dc is not None\n            assert ra is not None\n            assert off is not None\n\n            self._init_s_erri(endian, dc, ra, off)\n        elif self._suffix == Suffix.EDRI:\n            assert endian is not None\n            assert dc is not None\n            assert ra is not None\n            assert off is not None\n\n            self._init_edri(endian, dc, ra, off)\n        elif self._suffix == Suffix.ERII:\n            assert endian is not None\n            assert ra is not None\n            assert off is not None\n            assert imm is not None\n\n            self._init_erii(endian, ra, off, imm)\n        elif self._suffix == Suffix.ERIR:\n            assert endian is not None\n            assert ra is not None\n            assert off is not None\n            assert rb is not None\n\n            self._init_erir(endian, ra, off, rb)\n        elif self._suffix == Suffix.ERID:\n            assert endian is not None\n            assert ra is not None\n            assert off is not None\n            assert db is not None\n\n            self._init_erid(endian, ra, off, db)\n        elif self._suffix == Suffix.DMA_RRI:\n            assert ra is not None\n            assert rb is not None\n            assert imm is not None\n\n            self._init_dma_rri(ra, rb, imm)\n        else:\n            raise ValueError\n\n    def _init_rici(self, ra: SourceRegister, imm: int, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RICIOpCodes\n        assert self._suffix == Suffix.RICI\n\n        self._ra = ra\n        self._imm = Immediate(Representation.SIGNED, 16, imm)\n\n        if self._op_code in Instruction.AcquireRICIOpCodes:\n            self._condition = AcquireCC(condition).condition()\n        elif self._op_code in Instruction.ReleaseRICIOpCodes:\n            self._condition = ReleaseCC(condition).condition()\n        elif self._op_code in Instruction.BootRICIOpCodes:\n            self._condition = BootCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_rri(self, rc: GPRegister, ra: SourceRegister, imm: int) -> None:\n        assert self._op_code in Instruction.RRIOpCodes\n        assert self._suffix == Suffix.RRI\n\n        self._rc = rc\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 32, imm)\n        elif self._op_code in Instruction.AsrRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        elif self._op_code in Instruction.CallRRIOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 24, imm)\n        else:\n            raise ValueError\n\n    def _init_rric(self, rc: GPRegister, ra: SourceRegister, imm: int, condition: Condition,) -> None:\n        assert self._op_code in Instruction.RRICOpCodes\n        assert self._suffix == Suffix.RRIC\n\n        self._rc = rc\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.SubRRICOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 24, imm)\n        elif self._op_code in Instruction.AsrRRICOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.AsrRRICOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_rrici(self, rc: GPRegister, ra: SourceRegister, imm: int, condition: Condition, pc: int,) -> None:\n        assert self._op_code in Instruction.RRICIOpCodes\n        assert self._suffix == Suffix.RRICI\n\n        self._rc = rc\n        self._ra = ra\n\n        if (\n            self._op_code in Instruction.AddRRICIOpCodes\n            or self._op_code in Instruction.AndRRICIOpCodes\n            or self._op_code in Instruction.SubRRICIOpCodes\n        ):\n            self._imm = Immediate(Representation.SIGNED, 8, imm)\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRICIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._condition = ImmShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_rrif(self, rc: GPRegister, ra: SourceRegister, imm: int, condition: Condition,) -> None:\n        assert self._op_code in Instruction.RRIFOpCodes\n        assert self._suffix == Suffix.RRIF\n\n        self._rc = rc\n        self._ra = ra\n        self._imm = Immediate(Representation.SIGNED, 24, imm)\n        self._condition = FalseCC(condition).condition()\n\n    def _init_rrr(self, rc: GPRegister, ra: SourceRegister, rb: SourceRegister) -> None:\n        assert self._op_code in Instruction.RRROpCodes\n        assert self._suffix == Suffix.RRR\n\n        self._rc = rc\n        self._ra = ra\n        self._rb = rb\n\n    def _init_rrrc(self, rc: GPRegister, ra: SourceRegister, rb: SourceRegister, condition: Condition,) -> None:\n        assert self._op_code in Instruction.RRRCOpCodes\n        assert self._suffix == Suffix.RRRC\n\n        self._rc = rc\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCOpCodes:\n            self._condition = SubSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_rrrci(\n        self, rc: GPRegister, ra: SourceRegister, rb: SourceRegister, condition: Condition, pc: int,\n    ) -> None:\n        assert self._op_code in Instruction.RRRCIOpCodes\n        assert self._suffix == Suffix.RRRCI\n\n        self._rc = rc\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRRCIOpCodes:\n            self._condition = ShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.MulRRRCIOpCodes:\n            self._condition = MulNZCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_zri(self, ra: SourceRegister, imm: int):\n        assert self._op_code in Instruction.RRIOpCodes\n        assert self._suffix == Suffix.ZRI\n\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 32, imm)\n        elif self._op_code in Instruction.AsrRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        elif self._op_code in Instruction.CallRRIOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 28, imm)\n        else:\n            raise ValueError\n\n    def _init_zric(self, ra: SourceRegister, imm: int, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRICOpCodes\n        assert self._suffix == Suffix.ZRIC\n\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.SubRRICOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 27, imm)\n        elif self._op_code in Instruction.AsrRRICOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.AsrRRICOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_zrici(self, ra: SourceRegister, imm: int, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RRICIOpCodes\n        assert self._suffix == Suffix.ZRICI\n\n        self._ra = ra\n\n        if (\n            self._op_code in Instruction.AddRRICIOpCodes\n            or self._op_code in Instruction.AndRRICIOpCodes\n            or self._op_code in Instruction.SubRRICIOpCodes\n        ):\n            self._imm = Immediate(Representation.SIGNED, 11, imm)\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRICIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._condition = ImmShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_zrif(self, ra: SourceRegister, imm: int, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRIFOpCodes\n        assert self._suffix == Suffix.ZRIF\n\n        self._ra = ra\n        self._imm = Immediate(Representation.SIGNED, 27, imm)\n        self._condition = FalseCC(condition).condition()\n\n    def _init_zrr(self, ra: SourceRegister, rb: SourceRegister) -> None:\n        assert self._op_code in Instruction.RRROpCodes\n        assert self._suffix == Suffix.ZRR\n\n        self._ra = ra\n        self._rb = rb\n\n    def _init_zrrc(self, ra: SourceRegister, rb: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRRCOpCodes\n        assert self._suffix == Suffix.ZRRC\n\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCOpCodes:\n            self._condition = SubSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_zrrci(self, ra: SourceRegister, rb: SourceRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RRRCIOpCodes\n        assert self._suffix == Suffix.ZRRCI\n\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRRCIOpCodes:\n            self._condition = ShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.MulRRRCIOpCodes:\n            self._condition = MulNZCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_rri(self, dc: PairRegister, ra: SourceRegister, imm: int):\n        assert self._op_code in Instruction.RRIOpCodes\n        assert self._suffix == Suffix.S_RRI or self._suffix == Suffix.U_RRI\n\n        self._dc = dc\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 32, imm)\n        elif self._op_code in Instruction.AsrRRIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        elif self._op_code in Instruction.CallRRIOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 24, imm)\n        else:\n            raise ValueError\n\n    def _init_s_rric(self, dc: PairRegister, ra: SourceRegister, imm: int, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRICOpCodes\n        assert self._suffix == Suffix.S_RRIC or self._suffix == Suffix.U_RRIC\n\n        self._dc = dc\n        self._ra = ra\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.SubRRICOpCodes:\n            self._imm = Immediate(Representation.SIGNED, 24, imm)\n        elif self._op_code in Instruction.AsrRRICOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICOpCodes or self._op_code in Instruction.AsrRRICOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_s_rrici(self, dc: PairRegister, ra: SourceRegister, imm: int, condition: Condition, pc: int,) -> None:\n        assert self._op_code in Instruction.RRICIOpCodes\n        assert self._suffix == Suffix.S_RRICI or self._suffix == Suffix.U_RRICI\n\n        self._dc = dc\n        self._ra = ra\n\n        if (\n            self._op_code in Instruction.AddRRICIOpCodes\n            or self._op_code in Instruction.AndRRICIOpCodes\n            or self._op_code in Instruction.SubRRICIOpCodes\n        ):\n            self._imm = Immediate(Representation.SIGNED, 8, imm)\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        else:\n            raise ValueError\n\n        if self._op_code in Instruction.AddRRICIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRICIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRICIOpCodes:\n            self._condition = ImmShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_rrif(self, dc: PairRegister, ra: SourceRegister, imm: int, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRIFOpCodes\n        assert self._suffix == Suffix.S_RRIF or self._suffix == Suffix.U_RRIF\n\n        self._dc = dc\n        self._ra = ra\n        self._imm = Immediate(Representation.SIGNED, 24, imm)\n        self._condition = FalseCC(condition).condition()\n\n    def _init_s_rrr(self, dc: PairRegister, ra: SourceRegister, rb: SourceRegister) -> None:\n        assert self._op_code in Instruction.RRROpCodes\n        assert self._suffix == Suffix.S_RRR or self._suffix == Suffix.U_RRR\n\n        self._dc = dc\n        self._ra = ra\n        self._rb = rb\n\n    def _init_s_rrrc(self, dc: PairRegister, ra: SourceRegister, rb: SourceRegister, condition: Condition,) -> None:\n        assert self._op_code in Instruction.RRRCOpCodes\n        assert self._suffix == Suffix.S_RRRC or self._suffix == Suffix.U_RRRC\n\n        self._dc = dc\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCOpCodes:\n            self._condition = LogSetCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCOpCodes:\n            self._condition = SubSetCC(condition).condition()\n        elif self._op_code in Instruction.SubRRICIOpCodes:\n            self._condition = ExtSubSetCC(condition).condition()\n        else:\n            raise ValueError\n\n    def _init_s_rrrci(\n        self, dc: PairRegister, ra: SourceRegister, rb: SourceRegister, condition: Condition, pc: int,\n    ) -> None:\n        assert self._op_code in Instruction.RRRCIOpCodes\n        assert self._suffix == Suffix.S_RRRCI or self._suffix == Suffix.U_RRRCI\n\n        self._dc = dc\n        self._ra = ra\n        self._rb = rb\n\n        if self._op_code in Instruction.AddRRRCIOpCodes:\n            self._condition = AddNZCC(condition).condition()\n        elif self._op_code in Instruction.AndRRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.AsrRRRCIOpCodes:\n            self._condition = ShiftNZCC(condition).condition()\n        elif self._op_code in Instruction.MulRRRCIOpCodes:\n            self._condition = MulNZCC(condition).condition()\n        elif self._op_code in Instruction.RsubRRRCIOpCodes:\n            self._condition = SubNZCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_rr(self, rc: GPRegister, ra: SourceRegister) -> None:\n        assert self._op_code in Instruction.RROpCodes\n        assert self._suffix == Suffix.RR\n\n        self._rc = rc\n        self._ra = ra\n\n    def _init_rrc(self, rc: GPRegister, ra: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRCOpCodes\n        assert self._suffix == Suffix.RRC\n\n        self._rc = rc\n        self._ra = ra\n        self._condition = LogSetCC(condition).condition()\n\n    def _init_rrci(self, rc: GPRegister, ra: SourceRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RRCIOpCodes\n        assert self._suffix == Suffix.RRCI\n\n        self._rc = rc\n        self._ra = ra\n\n        if self._op_code in Instruction.CaoRRCIOpCodes:\n            self._condition = CountNZCC(condition).condition()\n        elif self._op_code in Instruction.ExtsbRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.TimeCfgRRCIOpCodes:\n            self._condition = TrueCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_zr(self, ra: SourceRegister) -> None:\n        assert self._op_code in Instruction.RROpCodes\n        assert self._suffix == Suffix.ZR\n\n        self._ra = ra\n\n    def _init_zrc(self, ra: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRCOpCodes\n        assert self._suffix == Suffix.ZRC\n\n        self._ra = ra\n        self._condition = LogSetCC(condition).condition()\n\n    def _init_zrci(self, ra: SourceRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RRCIOpCodes\n        assert self._suffix == Suffix.ZRCI\n\n        self._ra = ra\n\n        if self._op_code in Instruction.CaoRRCIOpCodes:\n            self._condition = CountNZCC(condition).condition()\n        elif self._op_code in Instruction.ExtsbRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.TimeCfgRRCIOpCodes:\n            self._condition = TrueCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_rr(self, dc: PairRegister, ra: SourceRegister) -> None:\n        assert self._op_code in Instruction.RROpCodes\n        assert self._suffix == Suffix.S_RR or self._suffix == Suffix.U_RR\n\n        self._dc = dc\n        self._ra = ra\n\n    def _init_s_rrc(self, dc: PairRegister, ra: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RRCOpCodes\n        assert self._suffix == Suffix.S_RRC or self._suffix == Suffix.U_RRC\n\n        self._dc = dc\n        self._ra = ra\n        self._condition = LogSetCC(condition).condition()\n\n    def _init_s_rrci(self, dc: PairRegister, ra: SourceRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RRCIOpCodes\n        assert self._suffix == Suffix.S_RRCI or self._suffix == Suffix.U_RRCI\n\n        self._dc = dc\n        self._ra = ra\n\n        if self._op_code in Instruction.CaoRRCIOpCodes:\n            self._condition = CountNZCC(condition).condition()\n        elif self._op_code in Instruction.ExtsbRRCIOpCodes:\n            self._condition = LogNZCC(condition).condition()\n        elif self._op_code in Instruction.TimeCfgRRCIOpCodes:\n            self._condition = TrueCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_drdici(\n        self, dc: PairRegister, ra: SourceRegister, db: PairRegister, imm: int, condition: Condition, pc: int,\n    ) -> None:\n        assert self._op_code in Instruction.DRDICIOpCodes\n        assert self._suffix == Suffix.DRDICI\n\n        self._dc = dc\n        self._ra = ra\n        self._db = db\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n\n        if self._op_code in Instruction.DivStepDRDICIOpCodes:\n            self._condition = DivCC(condition).condition()\n        elif self._op_code in Instruction.MulStepDRDICIOpCodes:\n            self._condition = BootCC(condition).condition()\n        else:\n            raise ValueError\n\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_rrri(self, rc: GPRegister, ra: SourceRegister, rb: SourceRegister, imm: int) -> None:\n        assert self._op_code in Instruction.RRRIOpCodes\n        assert self._suffix == Suffix.RRRI\n\n        self._rc = rc\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n\n    def _init_rrrici(\n        self, rc: GPRegister, ra: SourceRegister, rb: SourceRegister, imm: int, condition: Condition, pc: int,\n    ) -> None:\n        assert self._op_code in Instruction.RRRICIOpCodes\n        assert self._suffix == Suffix.RRRICI\n\n        self._rc = rc\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        self._condition = DivNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_zrri(self, ra: SourceRegister, rb: SourceRegister, imm: int) -> None:\n        assert self._op_code in Instruction.RRRIOpCodes\n        assert self._suffix == Suffix.ZRRI\n\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n\n    def _init_zrrici(self, ra: SourceRegister, rb: SourceRegister, imm: int, condition: Condition, pc: int,) -> None:\n        assert self._op_code in Instruction.RRRICIOpCodes\n        assert self._suffix == Suffix.ZRRICI\n\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        self._condition = DivNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_rrri(self, dc: PairRegister, ra: SourceRegister, rb: SourceRegister, imm: int) -> None:\n        assert self._op_code in Instruction.RRRIOpCodes\n        assert self._suffix == Suffix.S_RRRI or self._suffix == Suffix.U_RRRI\n\n        self._dc = dc\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n\n    def _init_s_rrrici(\n        self, dc: PairRegister, ra: SourceRegister, rb: SourceRegister, imm: int, condition: Condition, pc: int,\n    ) -> None:\n        assert self._op_code in Instruction.RRRICIOpCodes\n        assert self._suffix == Suffix.S_RRRICI or self._suffix == Suffix.U_RRRICI\n\n        self._dc = dc\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 5, imm)\n        self._condition = DivNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_rir(self, rc: GPRegister, imm: int, ra: SourceRegister) -> None:\n        assert self._op_code in Instruction.RIROpCodes\n        assert self._suffix == Suffix.RIR\n\n        self._rc = rc\n        self._imm = Immediate(Representation.UNSIGNED, 32, imm)\n        self._ra = ra\n\n    def _init_rirc(self, rc: GPRegister, imm: int, ra: SourceRegister, condition: Condition):\n        assert self._op_code in Instruction.RIRCOpCodes\n        assert self._suffix == Suffix.RIRC\n\n        self._rc = rc\n        self._imm = Immediate(Representation.SIGNED, 24, imm)\n        self._ra = ra\n        self._condition = SubSetCC(condition).condition()\n\n    def _init_rirci(self, rc: GPRegister, imm: int, ra: SourceRegister, condition: Condition, pc: int,) -> None:\n        assert self._op_code in Instruction.RIRCIOpCodes\n        assert self._suffix == Suffix.RIRCI\n\n        self._rc = rc\n        self._imm = Immediate(Representation.SIGNED, 8, imm)\n        self._ra = ra\n        self._condition = SubNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_zir(self, imm: int, ra: SourceRegister) -> None:\n        assert self._op_code in Instruction.RIROpCodes\n        assert self._suffix == Suffix.ZIR\n\n        self._imm = Immediate(Representation.UNSIGNED, 32, imm)\n        self._ra = ra\n\n    def _init_zirc(self, imm: int, ra: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RIRCOpCodes\n        assert self._suffix == Suffix.ZIRC\n\n        self._imm = Immediate(Representation.SIGNED, 27, imm)\n        self._ra = ra\n        self._condition = SubSetCC(condition).condition()\n\n    def _init_zirci(self, imm: int, ra: SourceRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RIRCIOpCodes\n        assert self._suffix == Suffix.ZIRCI\n\n        self._imm = Immediate(Representation.SIGNED, 11, imm)\n        self._ra = ra\n        self._condition = SubNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_rirc(self, dc: PairRegister, imm: int, ra: SourceRegister, condition: Condition) -> None:\n        assert self._op_code in Instruction.RIRCOpCodes\n        assert self._suffix == Suffix.S_RIRC or self._suffix == Suffix.U_RIRC\n\n        self._dc = dc\n        self._imm = Immediate(Representation.SIGNED, 24, imm)\n        self._ra = ra\n        self._condition = SubSetCC(condition).condition()\n\n    def _init_s_rirci(self, dc: PairRegister, imm: int, ra: SourceRegister, condition: Condition, pc: int,) -> None:\n        assert self._op_code in Instruction.RIRCIOpCodes\n        assert self._suffix == Suffix.S_RIRCI or self._suffix == Suffix.U_RIRCI\n\n        self._dc = dc\n        self._imm = Immediate(Representation.SIGNED, 8, imm)\n        self._ra = ra\n        self._condition = SubNZCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_r(self, rc: GPRegister) -> None:\n        assert self._op_code in Instruction.ROpCodes\n        assert self._suffix == Suffix.R\n\n        self._rc = rc\n\n    def _init_rci(self, rc: GPRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RCIOpCodes\n        assert self._suffix == Suffix.RCI\n\n        self._rc = rc\n        self._condition = TrueCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_z(self) -> None:\n        assert self._op_code in Instruction.ROpCodes or self._op_code == OpCode.NOP\n        assert self._suffix == Suffix.Z\n\n    def _init_zci(self, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RCIOpCodes\n        assert self._suffix == Suffix.ZCI\n\n        self._condition = TrueCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_s_r(self, dc: PairRegister) -> None:\n        assert self._op_code in Instruction.ROpCodes\n        assert self._suffix == Suffix.S_R or self._suffix == Suffix.U_R\n\n        self._dc = dc\n\n    def _init_s_rci(self, dc: PairRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.RCIOpCodes\n        assert self._suffix == Suffix.S_RCI or self._suffix == Suffix.U_RCI\n\n        self._dc = dc\n        self._condition = TrueCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_ci(self, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.CIOpCodes\n        assert self._suffix == Suffix.CI\n\n        self._condition = BootCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_i(self, imm: int) -> None:\n        assert self._op_code in Instruction.IOpCodes\n        assert self._suffix == Suffix.I\n\n        self._imm = Immediate(Representation.SIGNED, 24, imm)\n\n    def _init_ddci(self, dc: PairRegister, db: PairRegister, condition: Condition, pc: int) -> None:\n        assert self._op_code in Instruction.DDCIOpCodes\n        assert self._suffix == Suffix.DDCI\n\n        self._dc = dc\n        self._db = db\n        self._condition = TrueFalseCC(condition).condition()\n        self._pc = Immediate(Representation.UNSIGNED, ConfigLoader.iram_address_width(), pc)\n\n    def _init_erri(self, endian: Endian, rc: GPRegister, ra: SourceRegister, off: int) -> None:\n        assert self._op_code in Instruction.ERRIOpCodes\n        assert self._suffix == Suffix.ERRI\n\n        self._endian = endian\n        self._rc = rc\n        self._ra = ra\n        self._off = Immediate(Representation.SIGNED, 24, off)\n\n    def _init_s_erri(self, endian: Endian, dc: PairRegister, ra: SourceRegister, off: int) -> None:\n        assert self._op_code in Instruction.ERRIOpCodes\n        assert self._suffix == Suffix.S_ERRI or self._suffix == Suffix.U_ERRI\n\n        self._endian = endian\n        self._dc = dc\n        self._ra = ra\n        self._off = Immediate(Representation.SIGNED, 24, off)\n\n    def _init_edri(self, endian: Endian, dc: PairRegister, ra: SourceRegister, off: int) -> None:\n        assert self._op_code in Instruction.EDRIOpCodes\n        assert self._suffix == Suffix.EDRI\n\n        self._endian = endian\n        self._dc = dc\n        self._ra = ra\n        self._off = Immediate(Representation.SIGNED, 24, off)\n\n    def _init_erii(self, endian: Endian, ra: SourceRegister, off: int, imm: int) -> None:\n        assert self._op_code in Instruction.ERIIOpCodes\n        assert self._suffix == Suffix.ERII\n\n        self._endian = endian\n        self._ra = ra\n        # NOTE(bongjoon.hyun@gmail.com): original width is 12\n        self._off = Immediate(Representation.SIGNED, 24, off)\n        # NOTE(bongjoon.hyun@gmail.com): original width is 8\n        self._imm = Immediate(Representation.SIGNED, 16, imm)\n\n    def _init_erir(self, endian: Endian, ra: SourceRegister, off: int, rb: SourceRegister):\n        assert self._op_code in Instruction.ERIROpCodes\n        assert self._suffix == Suffix.ERIR\n\n        self._endian = endian\n        self._ra = ra\n        self._off = Immediate(Representation.SIGNED, 24, off)\n        self._rb = rb\n\n    def _init_erid(self, endian: Endian, ra: SourceRegister, off: int, db: PairRegister):\n        assert self._op_code in Instruction.ERIDOpCodes\n        assert self._suffix == Suffix.ERID\n\n        self._endian = endian\n        self._ra = ra\n        self._off = Immediate(Representation.SIGNED, 24, off)\n        self._db = db\n\n    def _init_dma_rri(self, ra: SourceRegister, rb: SourceRegister, imm: int):\n        assert self._op_code in Instruction.DMARRIOpCodes\n        assert self._suffix == Suffix.DMA_RRI\n\n        self._ra = ra\n        self._rb = rb\n        self._imm = Immediate(Representation.UNSIGNED, 8, imm)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/instruction/op_code.py",
    "content": "from enum import Enum, auto\n\n\nclass OpCode(Enum):\n    ACQUIRE = 0\n    RELEASE = auto()\n\n    ADD = auto()\n    ADDC = auto()\n    AND = auto()\n    ANDN = auto()\n    ASR = auto()\n    CAO = auto()\n    CLO = auto()\n    CLS = auto()\n    CLZ = auto()\n    CMPB4 = auto()\n    DIV_STEP = auto()\n    EXTSB = auto()\n    EXTSH = auto()\n    EXTUB = auto()\n    EXTUH = auto()\n    LSL = auto()\n    LSL_ADD = auto()\n    LSL_SUB = auto()\n    LSL1 = auto()\n    LSL1X = auto()\n    LSLX = auto()\n    LSR = auto()\n    LSR_ADD = auto()\n    LSR1 = auto()\n    LSR1X = auto()\n    LSRX = auto()\n    MUL_SH_SH = auto()\n    MUL_SH_SL = auto()\n    MUL_SH_UH = auto()\n    MUL_SH_UL = auto()\n    MUL_SL_SH = auto()\n    MUL_SL_SL = auto()\n    MUL_SL_UH = auto()\n    MUL_SL_UL = auto()\n    MUL_STEP = auto()\n    MUL_UH_UH = auto()\n    MUL_UH_UL = auto()\n    MUL_UL_UH = auto()\n    MUL_UL_UL = auto()\n    NAND = auto()\n    NOR = auto()\n    NXOR = auto()\n    OR = auto()\n    ORN = auto()\n    ROL = auto()\n    ROL_ADD = auto()\n    ROR = auto()\n    RSUB = auto()\n    RSUBC = auto()\n    SUB = auto()\n    SUBC = auto()\n    XOR = auto()\n\n    BOOT = auto()\n    RESUME = auto()\n    STOP = auto()\n\n    CALL = auto()\n\n    FAULT = auto()\n    NOP = auto()\n    SATS = auto()\n    MOVD = auto()\n    SWAPD = auto()\n\n    HASH = auto()\n    TIME = auto()\n    TIME_CFG = auto()\n\n    LBS = auto()\n    LBU = auto()\n    LD = auto()\n    LHS = auto()\n    LHU = auto()\n    LW = auto()\n\n    SB = auto()\n    SB_ID = auto()\n    SD = auto()\n    SD_ID = auto()\n    SH = auto()\n    SH_ID = auto()\n    SW = auto()\n    SW_ID = auto()\n\n    LDMA = auto()\n    LDMAI = auto()\n    SDMA = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/instruction/suffix.py",
    "content": "from enum import Enum, auto\n\n\nclass Suffix(Enum):\n    RICI = 0\n\n    RRI = auto()\n    RRIC = auto()\n    RRICI = auto()\n    RRIF = auto()\n    RRR = auto()\n    RRRC = auto()\n    RRRCI = auto()\n\n    ZRI = auto()\n    ZRIC = auto()\n    ZRICI = auto()\n    ZRIF = auto()\n    ZRR = auto()\n    ZRRC = auto()\n    ZRRCI = auto()\n\n    S_RRI = auto()\n    S_RRIC = auto()\n    S_RRICI = auto()\n    S_RRIF = auto()\n    S_RRR = auto()\n    S_RRRC = auto()\n    S_RRRCI = auto()\n\n    U_RRI = auto()\n    U_RRIC = auto()\n    U_RRICI = auto()\n    U_RRIF = auto()\n    U_RRR = auto()\n    U_RRRC = auto()\n    U_RRRCI = auto()\n\n    RR = auto()\n    RRC = auto()\n    RRCI = auto()\n\n    ZR = auto()\n    ZRC = auto()\n    ZRCI = auto()\n\n    S_RR = auto()\n    S_RRC = auto()\n    S_RRCI = auto()\n\n    U_RR = auto()\n    U_RRC = auto()\n    U_RRCI = auto()\n\n    DRDICI = auto()\n\n    RRRI = auto()\n    RRRICI = auto()\n\n    ZRRI = auto()\n    ZRRICI = auto()\n\n    S_RRRI = auto()\n    S_RRRICI = auto()\n\n    U_RRRI = auto()\n    U_RRRICI = auto()\n\n    RIR = auto()\n    RIRC = auto()\n    RIRCI = auto()\n\n    ZIR = auto()\n    ZIRC = auto()\n    ZIRCI = auto()\n\n    S_RIRC = auto()\n    S_RIRCI = auto()\n\n    U_RIRC = auto()\n    U_RIRCI = auto()\n\n    R = auto()\n    RCI = auto()\n\n    Z = auto()\n    ZCI = auto()\n\n    S_R = auto()\n    S_RCI = auto()\n\n    U_R = auto()\n    U_RCI = auto()\n\n    CI = auto()\n    # trunk-ignore(flake8/E741)\n    I = auto()\n\n    DDCI = auto()\n\n    ERRI = auto()\n\n    S_ERRI = auto()\n    U_ERRI = auto()\n\n    EDRI = auto()\n\n    ERII = auto()\n    ERIR = auto()\n    ERID = auto()\n\n    DMA_RRI = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/register/gp_register.py",
    "content": "from __future__ import annotations\n\nfrom util.config_loader import ConfigLoader\n\n\nclass GPRegister:\n    def __init__(self, index: int):\n        assert 0 <= index < ConfigLoader.num_gp_registers()\n\n        self._index: int = index\n\n    def __eq__(self, other: GPRegister) -> bool:\n        return self._index == other.index()\n\n    def index(self) -> int:\n        return self._index\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/register/pair_register.py",
    "content": "from __future__ import annotations\n\nfrom abi.isa.register.gp_register import GPRegister\nfrom util.config_loader import ConfigLoader\n\n\nclass PairRegister:\n    def __init__(self, index: int):\n        assert 0 <= index < ConfigLoader.num_gp_registers()\n        assert index % 2 == 0\n\n        self._index: int = index\n\n    def __eq__(self, other: PairRegister) -> bool:\n        return self._index == other.index()\n\n    def index(self) -> int:\n        return self._index\n\n    def even_register(self) -> GPRegister:\n        return GPRegister(self._index)\n\n    def odd_register(self) -> GPRegister:\n        return GPRegister(self._index + 1)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/isa/register/sp_register.py",
    "content": "from enum import Enum, auto\n\n\nclass SPRegister(Enum):\n    ZERO = 0\n    ONE = auto()\n    LNEG = auto()\n    MNEG = auto()\n    ID = auto()\n    ID2 = auto()\n    ID4 = auto()\n    ID8 = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/label/label.py",
    "content": "from typing import List, Optional, Union\n\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\nfrom encoder.directive_encoder import DirectiveEncoder\nfrom encoder.instruction_encoder import InstructionEncoder\nfrom util.config_loader import ConfigLoader\n\n\nclass Label:\n    def __init__(self, name: str):\n        self._name = name\n        self._address: Optional[DataAddressWord] = None\n        self._size: int = 0\n        self._assembler_instructions: List[\n            Union[\n                AsciiDirective,\n                AscizDirective,\n                ByteDirective,\n                LongDirective,\n                QuadDirective,\n                ShortDirective,\n                ZeroDirective,\n                Instruction,\n            ]\n        ] = []\n\n    def name(self) -> str:\n        return self._name\n\n    def address(self) -> Optional[int]:\n        if self._address is not None:\n            return self._address.value(Representation.UNSIGNED)\n        else:\n            return None\n\n    def begin_address(self) -> int:\n        address = self.address()\n        assert address is not None\n        return address\n\n    def end_address(self) -> int:\n        return self.begin_address() + self.size()\n\n    def set_address(self, address: int) -> None:\n        assert self._address is None\n        self._address = DataAddressWord()\n\n        assert address >= 0\n        self._address.set_value(address)\n\n    def size(self) -> int:\n        return max(self._size, self._assembler_instructions_size())\n\n    def set_size(self, size: int) -> None:\n        assert size >= self._assembler_instructions_size()\n        self._size = size\n\n    def append_assembler_instruction(\n        self,\n        assembler_instruction: Union[\n            AsciiDirective,\n            AscizDirective,\n            ByteDirective,\n            LongDirective,\n            QuadDirective,\n            ShortDirective,\n            ZeroDirective,\n            Instruction,\n        ],\n    ) -> None:\n        self._assembler_instructions.append(assembler_instruction)\n\n    def to_bytes(self) -> List[Byte]:\n        bytes_: List[Byte] = []\n        for assembler_instruction in self._assembler_instructions:\n            if isinstance(\n                assembler_instruction,\n                (\n                    AsciiDirective,\n                    AscizDirective,\n                    ByteDirective,\n                    LongDirective,\n                    QuadDirective,\n                    ShortDirective,\n                    ZeroDirective,\n                ),\n            ):\n                bytes_ += DirectiveEncoder.encode(assembler_instruction)\n            elif isinstance(assembler_instruction, Instruction):\n                bytes_ += InstructionEncoder.encode(assembler_instruction)\n            else:\n                raise ValueError\n        return bytes_\n\n    def _assembler_instructions_size(self) -> int:\n        size = 0\n        for assembler_instruction in self._assembler_instructions:\n            if isinstance(\n                assembler_instruction,\n                (\n                    AsciiDirective,\n                    AscizDirective,\n                    ByteDirective,\n                    LongDirective,\n                    QuadDirective,\n                    ShortDirective,\n                    ZeroDirective,\n                ),\n            ):\n                size += assembler_instruction.size()\n            elif isinstance(assembler_instruction, Instruction):\n                size += ConfigLoader.iram_data_width() // 8\n            else:\n                raise ValueError\n        return size\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/label/symbol.py",
    "content": "from enum import Enum, auto\n\n\nclass Symbol(Enum):\n    FUNCTION = 1\n    OBJECT = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/section/section.py",
    "content": "from typing import List, Optional, Set, Union\n\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.label.label import Label\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom abi.word.instruction_word import InstructionWord\nfrom converter.section_name_converter import SectionNameConverter\nfrom encoder.byte import Byte\n\n\nclass Section:\n    def __init__(\n        self, section_name: SectionName, name: str, section_flags: Set[SectionFlag], section_type: SectionType,\n    ):\n        self._section_name: SectionName = section_name\n        self._name = name\n        self._section_flags: Set[SectionFlag] = section_flags\n        self._section_type: SectionType = section_type\n\n        self._hidden_label = Label(self._hidden_label_name())\n        self._labels: List[Label] = [self._hidden_label]\n        self._cur_label: Label = self._hidden_label\n\n    def section_name(self) -> SectionName:\n        return self._section_name\n\n    def name(self) -> str:\n        return self._name\n\n    def address(self) -> Optional[int]:\n        return self._labels[0].address()\n\n    def set_address(self, address: int) -> None:\n        assert self.address() is None\n        assert address >= 0\n\n        offset = 0\n        for label in self._labels:\n            label.set_address(address + offset)\n            offset += label.size()\n\n            if self._section_name == SectionName.TEXT:\n                label_address = label.address()\n                label_size = label.size()\n\n                assert label_address is not None\n                assert label_address % InstructionWord().size() == 0\n                assert label_size % InstructionWord().size() == 0\n\n    def size(self) -> int:\n        return sum([label.size() for label in self._labels])\n\n    def labels(self) -> List[Label]:\n        return self._labels\n\n    def label(self, label_name: str) -> Optional[Label]:\n        for label in self._labels:\n            if label_name == label.name():\n                return label\n        return None\n\n    def checkout_hidden_label(self) -> None:\n        self._cur_label = self._hidden_label\n\n    def cur_label(self) -> Label:\n        return self._cur_label\n\n    def append_label(self, label_name: str):\n        if self.label(label_name) is None:\n            self._labels.append(Label(label_name))\n\n        label = self.label(label_name)\n        assert label is not None\n        self._cur_label = label\n\n    def append_assembler_instruction(\n        self,\n        assembler_instruction: Union[\n            AsciiDirective,\n            AscizDirective,\n            ByteDirective,\n            LongDirective,\n            QuadDirective,\n            ShortDirective,\n            ZeroDirective,\n            Instruction,\n        ],\n    ) -> None:\n        if self._section_name == SectionName.TEXT:\n            assert isinstance(assembler_instruction, Instruction)\n        else:\n            assert isinstance(\n                assembler_instruction,\n                (\n                    AsciiDirective,\n                    AscizDirective,\n                    ByteDirective,\n                    LongDirective,\n                    QuadDirective,\n                    ShortDirective,\n                    ZeroDirective,\n                ),\n            )\n\n        self._cur_label.append_assembler_instruction(assembler_instruction)\n\n    def to_bytes(self) -> List[Byte]:\n        bytes_: List[Byte] = []\n        for label in self._labels:\n            bytes_ += label.to_bytes()\n        return bytes_\n\n    def _hidden_label_name(self) -> str:\n        return f\"{SectionNameConverter.convert_to_str(self._section_name)}.{self._name}\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/section/section_flag.py",
    "content": "from enum import Enum, auto\n\n\nclass SectionFlag(Enum):\n    # the section is allocatable\n    ALLOC = 1\n\n    # the section is writable\n    WRITE = auto()\n\n    # the section is executable\n    EXECINSTR = auto()\n\n    # the section has a link-order restriction\n    LINK_ORDER = auto()\n\n    # the section can be merged\n    MERGE = auto()\n\n    # the section contains null-terminated string\n    STRINGS = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/section/section_name.py",
    "content": "from enum import Enum, auto\n\n\nclass SectionName(Enum):\n    ATOMIC = 1\n    BSS = auto()\n    DATA = auto()\n    DEBUG_ABBREV = auto()\n    DEBUG_FRAME = auto()\n    DEBUG_INFO = auto()\n    DEBUG_LINE = auto()\n    DEBUG_LOC = auto()\n    DEBUG_RANGES = auto()\n    DEBUG_STR = auto()\n    DPU_HOST = auto()\n    MRAM = auto()\n    RODATA = auto()\n    STACK_SIZES = auto()\n    TEXT = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/section/section_type.py",
    "content": "from enum import Enum, auto\n\n\nclass SectionType(Enum):\n    # section contains either initialized data and instructions or instructions only\n    PROG_BITS = 1\n\n    # section contains only zero-initialized data\n    NO_BITS = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/_base_word.py",
    "content": "import math\nfrom typing import List\n\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\n\n\nclass BaseWord:\n    def __init__(self, width: int):\n        assert width > 0\n\n        self._bits: List[bool] = [False for _ in range(width)]\n\n    def width(self) -> int:\n        return len(self._bits)\n\n    def size(self) -> int:\n        return self.width() // 8\n\n    def sign_bit(self) -> bool:\n        return self._bits[-1]\n\n    def bit(self, i: int) -> bool:\n        return self._bits[i]\n\n    def set_bit(self, i: int) -> None:\n        self._bits[i] = True\n\n    def clear_bit(self, i: int) -> None:\n        self._bits[i] = False\n\n    def bit_slice(self, representation: Representation, begin: int, end: int) -> int:\n        assert 0 <= begin < end <= self.width()\n\n        slice_width = end - begin\n\n        value = 0\n        for i in range(slice_width):\n            if self.bit(i + begin):\n                if representation == Representation.SIGNED and i == slice_width - 1:\n                    value -= 2 ** i\n                else:\n                    value += 2 ** i\n        return value\n\n    def set_bit_slice(self, begin: int, end: int, value: int) -> None:\n        assert 0 <= begin < end <= self.width()\n\n        if value >= 0:\n            self._set_positive_bit_slice(begin, end, value)\n        else:\n            self._set_negative_bit_slice(begin, end, value)\n\n    def value(self, representation: Representation) -> int:\n        return self.bit_slice(representation, 0, self.width())\n\n    def set_value(self, value: int) -> None:\n        self.set_bit_slice(0, self.width(), value)\n\n    def to_bytes(self) -> List[Byte]:\n        num_bytes = math.ceil(self.width() / 8.0)\n\n        bytes_: List[Byte] = []\n        for i in range(num_bytes):\n            begin = 8 * i\n            end = min(8 * (i + 1), self.width())\n\n            bytes_.append(Byte(self.bit_slice(Representation.UNSIGNED, begin, end)))\n        return bytes_\n\n    def from_bytes(self, bytes_: List[Byte]) -> None:\n        for i, byte in enumerate(bytes_):\n            begin = 8 * i\n            end = min(8 * (i + 1), self.width())\n\n            self.set_bit_slice(begin, end, byte.value())\n\n    def _set_positive_bit_slice(self, begin: int, end: int, value: int) -> None:\n        assert value >= 0\n\n        slice_width = end - begin\n        for i in range(slice_width):\n            if value % 2:\n                self.set_bit(i + begin)\n            else:\n                self.clear_bit(i + begin)\n\n            value //= 2\n\n        assert value == 0\n\n    def _set_negative_bit_slice(self, begin: int, end: int, value: int) -> None:\n        assert value < 0\n\n        slice_width = end - begin\n\n        self.set_bit(end - 1)\n        value += 2 ** (slice_width - 1)\n\n        if begin + 1 < end:\n            self._set_positive_bit_slice(begin, end - 1, value)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/data_address_word.py",
    "content": "from abi.word._base_word import BaseWord\nfrom util.config_loader import ConfigLoader\n\n\nclass DataAddressWord(BaseWord):\n    def __init__(self):\n        assert (\n            ConfigLoader.atomic_address_width()\n            == ConfigLoader.iram_address_width()\n            == ConfigLoader.wram_address_width()\n            == ConfigLoader.mram_address_width()\n        )\n\n        super().__init__(ConfigLoader.mram_address_width())\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/data_word.py",
    "content": "from abi.word._base_word import BaseWord\nfrom util.config_loader import ConfigLoader\n\n\nclass DataWord(BaseWord):\n    def __init__(self):\n        assert ConfigLoader.atomic_data_width() == ConfigLoader.wram_data_width() == ConfigLoader.mram_data_width()\n\n        super().__init__(ConfigLoader().atomic_data_width())\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/double_data_word.py",
    "content": "from abi.word._base_word import BaseWord\nfrom util.config_loader import ConfigLoader\n\n\nclass DoubleDataWord(BaseWord):\n    def __init__(self):\n        assert ConfigLoader.atomic_data_width() == ConfigLoader.wram_data_width() == ConfigLoader.mram_data_width()\n\n        super().__init__(2 * ConfigLoader().atomic_data_width())\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/immediate.py",
    "content": "import math\nfrom typing import List\n\nfrom abi.word.data_word import BaseWord\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\n\n\nclass Immediate:\n    def __init__(self, representation: Representation, width: int, value: int):\n        assert width > 0\n\n        self._representation: Representation = representation\n        self._width: int = width\n\n        self._word: BaseWord = BaseWord(width)\n        self._word.set_bit_slice(0, width, value)\n\n    def representation(self) -> Representation:\n        return self._representation\n\n    def width(self) -> int:\n        return self._width\n\n    def bit(self, i: int) -> bool:\n        return self._word.bit(i)\n\n    def bit_slice(self, representation: Representation, begin: int, end: int) -> int:\n        return self._word.bit_slice(representation, begin, end)\n\n    def value(self) -> int:\n        return self._word.bit_slice(self._representation, 0, self._width)\n\n    def to_bytes(self) -> List[Byte]:\n        num_bytes = math.ceil(self.width() / 8.0)\n        return self._word.to_bytes()[:num_bytes]\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/instruction_address_word.py",
    "content": "from abi.word._base_word import BaseWord\nfrom util.config_loader import ConfigLoader\n\n\nclass InstructionAddressWord(BaseWord):\n    def __init__(self):\n        super().__init__(ConfigLoader.iram_address_width())\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/instruction_word.py",
    "content": "from abi.word._base_word import BaseWord\nfrom util.config_loader import ConfigLoader\n\n\nclass InstructionWord(BaseWord):\n    def __init__(self):\n        super().__init__(ConfigLoader.iram_data_width())\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/abi/word/representation.py",
    "content": "from enum import Enum, auto\n\n\nclass Representation(Enum):\n    UNSIGNED = auto()\n    SIGNED = auto()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/assembler.py",
    "content": "import os\nfrom typing import List, Set, Union\n\nfrom abi.binary.executable import Executable\nfrom abi.label.symbol import Symbol\nfrom abi.section.section import Section\nfrom abi.section.section_name import SectionName\nfrom assembler.data_prep.bin import Bin\nfrom assembler.data_prep.bs_data_prep import BSDataPrep\nfrom assembler.data_prep.gemv_data_prep import GEMVDataPrep\nfrom assembler.data_prep.hst_data_prep import HSTDataPrep\nfrom assembler.data_prep.mlp_data_prep import MLPDataPrep\nfrom assembler.data_prep.red_data_prep import REDDataPrep\nfrom assembler.data_prep.scan_rss_data_prep import SCANRSSDataPrep\nfrom assembler.data_prep.scan_ssa_data_prep import SCANSSADataPrep\nfrom assembler.data_prep.sel_data_prep import SELDataPrep\nfrom assembler.data_prep.trns_data_prep import TRNSDataPrep\nfrom assembler.data_prep.ts_data_prep import TSDataPrep\nfrom assembler.data_prep.uni_data_prep import UNIDataPrep\nfrom assembler.data_prep.va_data_prep import VADataPrep\nfrom encoder.byte import Byte\nfrom linker_.linker_script import LinkerScript\nfrom util.path_collector import PathCollector\n\n\nclass Assembler:\n    DataPrep = Union[\n        BSDataPrep,\n        GEMVDataPrep,\n        HSTDataPrep,\n        MLPDataPrep,\n        REDDataPrep,\n        SCANRSSDataPrep,\n        SCANSSADataPrep,\n        SELDataPrep,\n        TRNSDataPrep,\n        TSDataPrep,\n        UNIDataPrep,\n        VADataPrep,\n    ]\n\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def assemble(\n        executable: Executable, linker_script: LinkerScript, data_prep_param: List[int], num_dpus: int\n    ) -> None:\n        Assembler._assemble_atomic(executable, num_dpus)\n        Assembler._assemble_iram(executable, num_dpus)\n        Assembler._assemble_wram(executable, num_dpus)\n        Assembler._assemble_mram(executable, num_dpus)\n\n        Assembler._assemble_global_object_symbols(executable, num_dpus)\n        Assembler._assemble_labels(executable, num_dpus)\n\n        Assembler._assemble_dpu_transfer_pointer(executable, linker_script, num_dpus)\n\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        data_prep = Assembler.data_prep(benchmark, num_tasklets, data_prep_param, num_dpus)\n\n        Assembler._assemble_input_dpu_mram_heap_pointer_name(executable, data_prep)\n        Assembler._assemble_output_dpu_mram_heap_pointer_name(executable, data_prep)\n        Assembler._assemble_dpu_input_arguments(executable, data_prep)\n        Assembler._assemble_dpu_results(executable, data_prep)\n        Assembler._assemble_num_executions(executable, data_prep)\n\n    @staticmethod\n    def _assemble_atomic(executable: Executable, num_dpus: int) -> None:\n        atomic_sections = Assembler._sort(executable.sections(SectionName.ATOMIC))\n\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        atomic_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{num_dpus}_dpus\",\n            f\"{benchmark}.{num_tasklets}\",\n            \"atomic.bin\",\n        )\n\n        bytes_: List[Byte] = []\n        for atomic_section in atomic_sections:\n            bytes_ += atomic_section.to_bytes()\n        atomic_bin = Bin(bytes_)\n        atomic_bin.dump(atomic_filepath)\n\n    @staticmethod\n    def _assemble_iram(executable: Executable, num_dpus: int) -> None:\n        text_sections = Assembler._sort(executable.sections(SectionName.TEXT))\n\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        iram_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{num_dpus}_dpus\", f\"{benchmark}.{num_tasklets}\", \"iram.bin\"\n        )\n\n        bytes_: List[Byte] = []\n        for text_section in text_sections:\n            bytes_ += text_section.to_bytes()\n        iram_bin = Bin(bytes_)\n        iram_bin.dump(iram_filepath)\n\n    @staticmethod\n    def _assemble_wram(executable: Executable, num_dpus: int) -> None:\n        sections = Assembler._sort(\n            {\n                *executable.sections(SectionName.DATA),\n                *executable.sections(SectionName.RODATA),\n                *executable.sections(SectionName.BSS),\n                *executable.sections(SectionName.DPU_HOST),\n            }\n        )\n\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        wram_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{num_dpus}_dpus\", f\"{benchmark}.{num_tasklets}\", \"wram.bin\"\n        )\n\n        bytes_: List[Byte] = []\n        for section in sections:\n            bytes_ += section.to_bytes()\n        wram_bin = Bin(bytes_)\n        wram_bin.dump(wram_filepath)\n\n    @staticmethod\n    def _assemble_mram(executable: Executable, num_dpus: int) -> None:\n        sections = Assembler._sort(\n            {\n                *executable.sections(SectionName.DEBUG_ABBREV),\n                *executable.sections(SectionName.DEBUG_FRAME),\n                *executable.sections(SectionName.DEBUG_INFO),\n                *executable.sections(SectionName.DEBUG_LINE),\n                *executable.sections(SectionName.DEBUG_LOC),\n                *executable.sections(SectionName.DEBUG_RANGES),\n                *executable.sections(SectionName.DEBUG_STR),\n                *executable.sections(SectionName.STACK_SIZES),\n                *executable.sections(SectionName.MRAM),\n            }\n        )\n\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        mram_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{num_dpus}_dpus\", f\"{benchmark}.{num_tasklets}\", \"mram.bin\"\n        )\n\n        bytes_: List[Byte] = []\n        for section in sections:\n            bytes_ += section.to_bytes()\n        mram_bin = Bin(bytes_)\n        mram_bin.dump(mram_filepath)\n\n    @staticmethod\n    def _assemble_global_object_symbols(executable: Executable, num_dpus: int) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        global_object_symbols_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{num_dpus}_dpus\",\n            f\"{benchmark}.{num_tasklets}\",\n            \"global_object_symbols.bin\",\n        )\n        with open(global_object_symbols_filepath, \"w\") as file:\n            lines = \"\"\n            for global_symbol in executable.liveness().global_symbols():\n                if executable.liveness().symbol(global_symbol) == Symbol.OBJECT:\n                    label = executable.label(global_symbol)\n                    assert label is not None\n                    symbol_address = label.address()\n                    symbol_size = label.size()\n                    lines += f\"{symbol_address}: {symbol_size}\\n\"\n            file.writelines(lines)\n\n    @staticmethod\n    def _assemble_dpu_transfer_pointer(executable: Executable, linker_script: LinkerScript, num_dpus: int) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n\n        dpu_transfer_pointer_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{num_dpus}_dpus\",\n            f\"{benchmark}.{num_tasklets}\",\n            \"dpu_transfer_pointer.bin\",\n        )\n        with open(dpu_transfer_pointer_filepath, \"w\") as file:\n            lines = \"\"\n\n            sys_used_mram_end = linker_script.symbol(\"__sys_used_mram_end\")\n            assert sys_used_mram_end.address() is not None\n            lines += f\"{sys_used_mram_end.address()}\\n\"\n\n            dpu_input_arguments = executable.label(\"DPU_INPUT_ARGUMENTS\")\n            if dpu_input_arguments is not None:\n                assert dpu_input_arguments.address() is not None\n                lines += f\"{dpu_input_arguments.address()}\\n\"\n            else:\n                lines += \"-1\\n\"\n\n            dpu_results = executable.label(\"DPU_RESULTS\")\n            if dpu_results is not None:\n                assert dpu_results is not None\n                lines += f\"{dpu_results.address()}\\n\"\n            else:\n                lines += \"-1\\n\"\n\n            sys_end = executable.label(\"__sys_end\")\n            assert sys_end is not None\n            assert sys_end.address() is not None\n            lines += f\"{sys_end.address()}\\n\"\n\n            file.writelines(lines)\n\n    @staticmethod\n    def _assemble_input_dpu_mram_heap_pointer_name(executable: Executable, data_prep: DataPrep) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n\n        for execution in range(data_prep.num_executions()):\n            for dpu_id in range(data_prep.num_dpus()):\n                input_dpu_mram_heap_pointer_name = data_prep.input_dpu_mram_heap_pointer_name(execution, dpu_id)\n                if input_dpu_mram_heap_pointer_name is not None:\n                    input_dpu_mram_heap_pointer_name_filepath = os.path.join(\n                        PathCollector.bin_path_in_local(),\n                        f\"{data_prep.num_dpus()}_dpus\",\n                        f\"{benchmark}.{num_tasklets}\",\n                        f\"input_dpu_mram_heap_pointer_name.dpu_id{dpu_id}.{execution}.bin\",\n                    )\n                    input_dpu_mram_heap_pointer_name.dump(input_dpu_mram_heap_pointer_name_filepath)\n\n    @staticmethod\n    def _assemble_output_dpu_mram_heap_pointer_name(executable: Executable, data_prep: DataPrep) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n\n        for execution in range(data_prep.num_executions()):\n            for dpu_id in range(data_prep.num_dpus()):\n                output_dpu_mram_heap_pointer_name = data_prep.output_dpu_mram_heap_pointer_name(execution, dpu_id)\n                if output_dpu_mram_heap_pointer_name is not None:\n                    output_dpu_mram_heap_pointer_name_filepath = os.path.join(\n                        PathCollector.bin_path_in_local(),\n                        f\"{data_prep.num_dpus()}_dpus\",\n                        f\"{benchmark}.{num_tasklets}\",\n                        f\"output_dpu_mram_heap_pointer_name.dpu_id{dpu_id}.{execution}.bin\",\n                    )\n                    output_dpu_mram_heap_pointer_name.dump(output_dpu_mram_heap_pointer_name_filepath)\n\n    @staticmethod\n    def _assemble_dpu_input_arguments(executable: Executable, data_prep: DataPrep) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n\n        for execution in range(data_prep.num_executions()):\n            for dpu_id in range(data_prep.num_dpus()):\n                dpu_input_arguments = data_prep.dpu_input_arguments(execution, dpu_id)\n                if dpu_input_arguments is not None:\n                    dpu_input_arguments_filepath = os.path.join(\n                        PathCollector.bin_path_in_local(),\n                        f\"{data_prep.num_dpus()}_dpus\",\n                        f\"{benchmark}.{num_tasklets}\",\n                        f\"dpu_input_arguments.dpu_id{dpu_id}.{execution}.bin\",\n                    )\n\n                    dpu_input_arguments.dump(dpu_input_arguments_filepath)\n\n    @staticmethod\n    def _assemble_dpu_results(executable: Executable, data_prep: DataPrep) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n\n        for execution in range(data_prep.num_executions()):\n            for dpu_id in range(data_prep.num_dpus()):\n                dpu_results = data_prep.dpu_results(execution, dpu_id)\n                if dpu_results is not None:\n                    dpu_results_filepath = os.path.join(\n                        PathCollector.bin_path_in_local(),\n                        f\"{data_prep.num_dpus()}_dpus\",\n                        f\"{benchmark}.{num_tasklets}\",\n                        f\"dpu_results.dpu_id{dpu_id}.{execution}.bin\",\n                    )\n\n                    dpu_results.dump(dpu_results_filepath)\n\n    @staticmethod\n    def _assemble_labels(executable: Executable, num_dpus: int) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        labels_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{num_dpus}_dpus\",\n            f\"{benchmark}.{num_tasklets}\",\n            \"labels.bin\",\n        )\n        with open(labels_filepath, \"w\") as file:\n            lines = \"\"\n            for label in executable.labels():\n                lines += f\"{label.name()}: {label.address()}\\n\"\n            file.writelines(lines)\n\n    @staticmethod\n    def _assemble_num_executions(executable: Executable, data_prep: DataPrep) -> None:\n        benchmark = Assembler._benchmark(executable)\n        num_tasklets = Assembler._num_tasklets(executable)\n        num_executions_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{data_prep.num_dpus()}_dpus\",\n            f\"{benchmark}.{num_tasklets}\",\n            \"num_executions.bin\",\n        )\n        with open(num_executions_filepath, \"w\") as file:\n            lines = f\"{data_prep.num_executions()}\\n\"\n            file.writelines(lines)\n\n    @staticmethod\n    def data_prep(benchmark: str, num_tasklets: int, data_prep_param: List[int], num_dpus: int) -> DataPrep:\n        if benchmark == \"BS\":\n            return BSDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"GEMV\":\n            return GEMVDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"HST-L\" or benchmark == \"HST-S\":\n            return HSTDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"MLP\":\n            return MLPDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"RED\":\n            return REDDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"SCAN-RSS\":\n            return SCANRSSDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"SCAN-SSA\":\n            return SCANSSADataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"SEL\":\n            return SELDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"TRNS\":\n            return TRNSDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"TS\":\n            return TSDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"UNI\":\n            return UNIDataPrep(num_tasklets, data_prep_param, num_dpus)\n        elif benchmark == \"VA\":\n            return VADataPrep(num_tasklets, data_prep_param, num_dpus)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _benchmark(executable: Executable) -> str:\n        return executable.filepath().split(os.path.sep)[-2].split(\".\")[0]\n\n    @staticmethod\n    def _num_tasklets(executable: Executable) -> int:\n        return int(executable.filepath().split(os.path.sep)[-2].split(\".\")[-1])\n\n    @staticmethod\n    def _sort(sections: Set[Section]) -> List[Section]:\n        def _address(section: Section) -> int:\n            address = section.address()\n            assert address is not None\n            return address\n\n        return sorted(sections, key=_address)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/bin.py",
    "content": "from typing import List\n\nfrom encoder.byte import Byte\n\n\nclass Bin:\n    def __init__(self, bytes_: List[Byte]):\n        self._bytes: List[Byte] = bytes_\n\n    def dump(self, filepath: str):\n        with open(filepath, \"w\") as file:\n            lines = \"\"\n            for byte in self._bytes:\n                lines += f\"{byte.value()}\\n\"\n            file.writelines(lines)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/bs_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass BSDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n        self._num_querys = int(data_prep_param[0] // 8)\n\n        self._num_executions: int = 1\n\n        if self._num_querys % (self._num_dpus * self._num_tasklets) != 0:\n            self._num_querys = self._num_querys + (\n                self._num_dpus * self._num_tasklets - self._num_querys % (self._num_dpus * self._num_tasklets)\n            )\n\n        assert self._num_querys % (self._num_dpus * self._num_tasklets) == 0\n\n        self._input_buffer: List[int] = [i + 1 for i in range(self._size)]\n        self._query_buffer: List[int] = [i for i in range(self._num_querys)]\n        self._result: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n\n        self._slice_per_dpu = self._num_querys // self._num_dpus\n        self._query_per_tasklet = self._slice_per_dpu // self._num_tasklets\n\n        for dpu_id in range(self._num_dpus):\n            for tasklet in range(self._num_tasklets):\n                for query in range(self._query_per_tasklet):\n                    is_found = False\n                    l = 0\n                    r = self._size - 1\n                    while l <= r:\n                        m = l + (r - l) // 2\n                        if (\n                            self._input_buffer[m]\n                            == self._query_buffer[\n                                query + tasklet * self._query_per_tasklet + dpu_id * self._slice_per_dpu\n                            ]\n                        ):\n                            self._result[dpu_id][tasklet] = m\n                            is_found = True\n                            break\n                        if (\n                            self._input_buffer[m]\n                            < self._query_buffer[\n                                query + tasklet * self._query_per_tasklet + dpu_id * self._slice_per_dpu\n                            ]\n                        ):\n                            l = m + 1\n                        else:\n                            r = m - 1\n                    if is_found == False:\n                        self._result[dpu_id][tasklet] = -1\n\n        self._kernel: int = 0\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._slice_per_dpu * dpu_id\n        end_elem = self._slice_per_dpu * (dpu_id + 1)\n\n        for element in self._input_buffer:\n            element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._query_buffer[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        size_immediate = Immediate(Representation.UNSIGNED, 64, self._size)\n        bytes_ += size_immediate.to_bytes()\n\n        slice_per_dpu_immediate = Immediate(Representation.UNSIGNED, 64, self._slice_per_dpu)\n        bytes_ += slice_per_dpu_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel)\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n        for element in self._result[dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n            bytes_ += element_immediate.to_bytes()\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/gemv_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass GEMVDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._m_size: int = data_prep_param[0]\n        self._n_size: int = 64\n\n        self._num_executions: int = 1\n\n        assert self._m_size % self._num_dpus == 0\n\n        self._n_size_pad: List[int] = [\n            (self._n_size if self._n_size % 2 == 0 else self._n_size + 1) for _ in range(self._num_dpus)\n        ]\n        self._nr_rows: List[int] = [self._m_size // self._num_dpus for _ in range(self._num_dpus)]\n        self._max_rows: List[int] = [\n            (self._nr_rows[i] if self._nr_rows[i] % 2 == 0 else self._nr_rows[i] + 1) for i in range(self._num_dpus)\n        ]\n\n        self._buffer_a: List[List[int]] = [\n            [IntInitializer.value_by_range(0, 50) for _ in range(self._n_size)] for _ in range(self._m_size)\n        ]\n\n        self._buffer_b: List[int] = [IntInitializer.value_by_range(0, 50) for _ in range(self._n_size)]\n\n        self._buffer_c: List[List[int]] = [[] for _ in range(self._num_dpus)]\n\n        for dpu_id in range(self._num_dpus):\n            start_row: int = self._nr_rows[dpu_id] * dpu_id\n            end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n            self._buffer_c[dpu_id] = np.matmul(self._buffer_a[start_row:end_row], self._buffer_b).tolist()\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_row: int = self._nr_rows[dpu_id] * dpu_id\n        end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n\n        for row in self._buffer_a[start_row:end_row]:\n            for element in row:\n                element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n                bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_b:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_row: int = self._nr_rows[dpu_id] * dpu_id\n        end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n\n        for row in self._buffer_a[start_row:end_row]:\n            for element in row:\n                element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n                bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_b:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_c[dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        n_size_immediate = Immediate(Representation.UNSIGNED, 32, self._n_size)\n        bytes_ += n_size_immediate.to_bytes()\n\n        n_size_pad_immediate = Immediate(Representation.UNSIGNED, 32, self._n_size_pad[dpu_id])\n        bytes_ += n_size_pad_immediate.to_bytes()\n\n        nr_rows_immediate = Immediate(Representation.UNSIGNED, 32, self._nr_rows[dpu_id])\n        bytes_ += nr_rows_immediate.to_bytes()\n\n        max_rows_immediate = Immediate(Representation.UNSIGNED, 32, self._max_rows[dpu_id])\n        bytes_ += max_rows_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/hst_data_prep.py",
    "content": "from typing import List, Optional\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass HSTDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]  \n        self._num_bins: int = 256\n\n        self._num_executions: int = 1\n\n        elem_size = 4\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        if (input_size * elem_size) % 8 != 0:\n            input_size_8bytes = (input_size // 8) * 8 + 8\n        else:\n            input_size_8bytes = input_size\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if (input_size_dpu * elem_size) % 8 != 0:\n            self._input_size_dpu_8bytes = (input_size_dpu // 8) * 8 + 8\n        else:\n            self._input_size_dpu_8bytes = input_size_dpu\n\n        self._buffer_a: List[int] = [IntInitializer.value_by_range(0, 4096) for _ in range(input_size)]\n\n        depth = 12\n\n        self._buffer_c: List[List[int]] = [[0 for _ in range(self._num_bins)] for _ in range(self._num_dpus)]\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_8bytes * dpu_id\n            end_elem = self._input_size_dpu_8bytes * (dpu_id + 1)\n            for elem in self._buffer_a[start_elem:end_elem]:\n                self._buffer_c[dpu_id][(elem * self._num_bins) >> depth] += 1\n\n        elem_size = 4\n\n        input_size = self._size\n        if (input_size * elem_size) % 8 != 0:\n            input_size_8bytes = (self._size // 8) * 8 + 8\n        else:\n            input_size_8bytes = self._size\n\n        self._dpu_arg_size: List[int] = [0 for _ in range(self._num_dpus)]\n        for dpu_id in range(self._num_dpus):\n            if dpu_id != self._num_dpus - 1:\n                self._dpu_arg_size[dpu_id] = self._input_size_dpu_8bytes * elem_size\n            else:\n                self._dpu_arg_size[dpu_id] = (\n                    input_size_8bytes - (self._input_size_dpu_8bytes * (self._num_dpus - 1))\n                ) * elem_size\n        self._transfer_size: int = self._input_size_dpu_8bytes * elem_size\n        self._kernel: int = 0\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_8bytes * dpu_id\n        end_elem = self._input_size_dpu_8bytes * (dpu_id + 1)\n\n        for element in self._buffer_a[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_8bytes * dpu_id\n        end_elem = self._input_size_dpu_8bytes * (dpu_id + 1)\n\n        for element in self._buffer_a[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_c[dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        dpu_arg_size_immediate = Immediate(Representation.UNSIGNED, 32, self._dpu_arg_size[dpu_id])\n        bytes_ += dpu_arg_size_immediate.to_bytes()\n\n        transfer_immediate = Immediate(Representation.UNSIGNED, 32, self._transfer_size)\n        bytes_ += transfer_immediate.to_bytes()\n\n        num_bins_immediate = Immediate(Representation.UNSIGNED, 32, self._num_bins)\n        bytes_ += num_bins_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel)\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/mlp_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass MLPDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._m_size: int = data_prep_param[0]\n        self._n_size: int = data_prep_param[0]\n\n        self._num_layers: int = 3\n\n        self._num_executions: int = self._num_layers\n\n        assert self._m_size % self._num_dpus == 0\n\n        self._n_size_pad: List[int] = [\n            (self._n_size if self._n_size % 2 == 0 else self._n_size + 1) for _ in range(self._num_dpus)\n        ]\n        self._nr_rows: List[int] = [self._m_size // self._num_dpus for _ in range(self._num_dpus)]\n        self._max_rows: List[int] = [\n            (self._nr_rows[i] if self._nr_rows[i] % 2 == 0 else self._nr_rows[i] + 1) for i in range(self._num_dpus)\n        ]\n\n        # weights\n        self._buffer_a: List[List[List[int]]] = [\n            [[0 if i % 100 < 98 else (layer + i) % 2 for i in range(self._n_size)] for _ in range(self._m_size)]\n            for layer in range(self._num_layers)\n        ]\n\n        # input activations\n        self._buffer_b: List[List[int]] = [\n            [0 if i % 50 < 48 else i % 2 for i in range(self._n_size)] for _ in range(self._num_layers)\n        ]\n\n        # output activations\n        self._buffer_c: List[List[List[int]]] = [\n            [[0 for _ in range(self._m_size)] for _ in range(self._num_dpus)] for _ in range(self._num_layers)\n        ]\n        for layer in range(self._num_layers):\n            for dpu_id in range(self._num_dpus):\n                start_row: int = self._nr_rows[dpu_id] * dpu_id\n                end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n\n                self._buffer_c[layer][dpu_id] = np.matmul(\n                    self._buffer_a[layer][start_row:end_row], self._buffer_b[layer]\n                ).tolist()\n                for i in range(len(self._buffer_c[layer][dpu_id])):\n                    if self._buffer_c[layer][dpu_id][i] < 0:\n                        self._buffer_c[layer][dpu_id][i] = 0\n\n                if layer < self._num_layers - 1:\n                    self._buffer_b[layer + 1][start_row:end_row] = self._buffer_c[layer][dpu_id]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_row: int = self._nr_rows[dpu_id] * dpu_id\n        end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n\n        for row in self._buffer_a[execution][start_row:end_row]:\n            for element in row:\n                element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n                bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_b[execution]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_row: int = self._nr_rows[dpu_id] * dpu_id\n        end_row: int = self._nr_rows[dpu_id] * (dpu_id + 1)\n\n        for row in self._buffer_a[execution][start_row:end_row]:\n            for element in row:\n                element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n                bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_b[execution]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_c[execution][dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        n_size_immediate = Immediate(Representation.UNSIGNED, 32, self._n_size)\n        bytes_ += n_size_immediate.to_bytes()\n\n        n_size_pad_immediate = Immediate(Representation.UNSIGNED, 32, self._n_size_pad[dpu_id])\n        bytes_ += n_size_pad_immediate.to_bytes()\n\n        nr_rows_immediate = Immediate(Representation.UNSIGNED, 32, self._nr_rows[dpu_id])\n        bytes_ += nr_rows_immediate.to_bytes()\n\n        max_rows_immediate = Immediate(Representation.UNSIGNED, 32, self._max_rows[dpu_id])\n        bytes_ += max_rows_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/red_data_prep.py",
    "content": "from typing import List, Optional\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass Result:\n    def __init__(self, cycle=0, t_count=0):\n        self._cycle: int = cycle\n        self._t_count: int = t_count\n\n\nclass REDDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n\n        self._num_executions: int = 1\n\n        elem_size = 8\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        if (input_size * elem_size) % 8 != 0:\n            input_size_8bytes = (input_size // 8) * 8 + 8\n        else:\n            input_size_8bytes = input_size\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if (input_size_dpu * elem_size) % 8 != 0:\n            self._input_size_dpu_8bytes = (input_size_dpu // 8) * 8 + 8\n        else:\n            self._input_size_dpu_8bytes = input_size_dpu\n\n        self._buffer_a: List[int] = [\n            IntInitializer.value_by_range(0, 100) for _ in range(self._input_size_dpu_8bytes * self._num_dpus)\n        ]\n\n        self._count: List[int] = [0 for _ in range(self._num_dpus)]\n        self._dpu_arg_size: List[int] = [0 for _ in range(self._num_dpus)]\n\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_8bytes * dpu_id\n            if dpu_id != self._num_dpus - 1:\n                end_elem = self._input_size_dpu_8bytes * (dpu_id + 1)\n            else:\n                end_elem = input_size\n\n            self._count[dpu_id] = sum(self._buffer_a[start_elem:end_elem])\n\n            if dpu_id != self._num_dpus - 1:\n                self._dpu_arg_size[dpu_id] = self._input_size_dpu_8bytes * elem_size\n            else:\n                self._dpu_arg_size[dpu_id] = (\n                    input_size_8bytes - (self._input_size_dpu_8bytes * (self._num_dpus - 1))\n                ) * elem_size\n\n        self._kernel: List[int] = [0 for _ in range(self._num_dpus)]\n        self._input_t_count: List[int] = [0 for _ in range(self._num_dpus)]\n\n        self._result: List[List[Result]] = [\n            [Result(0, self._count[j]) if i == 0 else Result() for i in range(self._num_tasklets)]\n            for j in range(self._num_dpus)\n        ]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_8bytes * dpu_id\n\n        for i in range(self._input_size_dpu_8bytes):\n            element_immediate = Immediate(Representation.UNSIGNED, 64, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n        return None\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n        dpu_arg_size_immediate = Immediate(Representation.UNSIGNED, 32, self._dpu_arg_size[dpu_id])\n        bytes_ += dpu_arg_size_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[dpu_id])\n        bytes_ += kernel_immediate.to_bytes()\n\n        input_t_count_immediate = Immediate(Representation.UNSIGNED, 64, self._input_t_count[dpu_id])\n        bytes_ += input_t_count_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n        for element in self._result[dpu_id]:\n            cycle_immediate = Immediate(Representation.UNSIGNED, 64, element._cycle)\n            bytes_ += cycle_immediate.to_bytes()\n\n            t_count_immediate = Immediate(Representation.UNSIGNED, 64, element._t_count)\n            bytes_ += t_count_immediate.to_bytes()\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/scan_rss_data_prep.py",
    "content": "import math\nfrom typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass SCANRSSDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n\n        self._num_executions: int = 2\n\n        elem_size = 8\n\n        regs = 128\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if input_size_dpu % (num_tasklets * regs) != 0:\n            self._input_size_dpu_round = math.ceil(input_size_dpu / (num_tasklets * regs)) * (num_tasklets * regs)\n        else:\n            self._input_size_dpu_round = input_size_dpu\n\n        self._buffer_a: List[int] = [\n            IntInitializer.value_by_range(0, 100) if i < input_size else 0\n            for i in range(self._input_size_dpu_round * self._num_dpus)\n        ]\n\n        self._buffer_c: List[int] = []\n        for i in range(self._input_size_dpu_round * self._num_dpus):\n            if i == 0:\n                self._buffer_c.append(self._buffer_a[i])\n            else:\n                self._buffer_c.append(self._buffer_c[i - 1] + self._buffer_a[i])\n\n        self._last_result_value: List[int] = [0 for _ in range(self._num_dpus)]\n        self._result_t_count: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n            self._last_result_value[dpu_id] = np.sum(self._buffer_a[start_elem:end_elem])\n            self._result_t_count[dpu_id][0] = self._last_result_value[dpu_id]\n\n        self._dpu_arg_size: int = self._input_size_dpu_round * elem_size\n        self._kernel: List[int] = [0, 1]\n        self._tcount: List[List[int]] = [\n            [0, 0 if dpu_id == 0 else np.sum(self._result_t_count[0:dpu_id])] for dpu_id in range(self._num_dpus)\n        ]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != 0:\n            return None\n        else:\n            bytes_: List[Byte] = []\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n            for element in self._buffer_a[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != self._num_executions - 1:\n            return None\n        else:\n            bytes_: List[Byte] = []\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n\n            for element in self._buffer_a[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n            for element in self._buffer_c[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n            return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        dpu_arg_size_immediate = Immediate(Representation.UNSIGNED, 32, self._dpu_arg_size)\n        bytes_ += dpu_arg_size_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[execution])\n        bytes_ += kernel_immediate.to_bytes()\n\n        tcount_immediate = Immediate(Representation.UNSIGNED, 64, self._tcount[dpu_id][execution])\n        bytes_ += tcount_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != 0:\n            return None\n        else:\n            bytes_: List[Byte] = []\n\n            for element in self._result_t_count[dpu_id]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/scan_ssa_data_prep.py",
    "content": "import math\nfrom typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass SCANSSADataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n\n        self._num_executions: int = 2\n\n        elem_size = 8\n\n        regs = 128\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if input_size_dpu % (num_tasklets * regs) != 0:\n            self._input_size_dpu_round = math.ceil(input_size_dpu / (num_tasklets * regs)) * (num_tasklets * regs)\n        else:\n            self._input_size_dpu_round = input_size_dpu\n\n        self._buffer_a: List[int] = [\n            IntInitializer.value_by_range(0, 100) if i < input_size else 0\n            for i in range(self._input_size_dpu_round * self._num_dpus)\n        ]\n\n        self._buffer_c: List[int] = []\n        for i in range(self._input_size_dpu_round * self._num_dpus):\n            if i == 0:\n                self._buffer_c.append(self._buffer_a[i])\n            else:\n                self._buffer_c.append(self._buffer_c[i - 1] + self._buffer_a[i])\n\n        self._last_result_value: List[int] = [0 for _ in range(self._num_dpus)]\n        self._result_t_count: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n            self._last_result_value[dpu_id] = np.sum(self._buffer_a[start_elem:end_elem])\n            self._result_t_count[dpu_id][self._num_tasklets - 1] = self._last_result_value[dpu_id]\n\n        self._dpu_arg_size: int = self._input_size_dpu_round * elem_size\n        self._kernel: List[int] = [0, 1]\n        self._tcount: List[List[int]] = [\n            [0, 0 if dpu_id == 0 else np.sum(self._result_t_count[0:dpu_id])] for dpu_id in range(self._num_dpus)\n        ]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != 0:\n            return None\n        else:\n            bytes_: List[Byte] = []\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n            for element in self._buffer_a[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != self._num_executions - 1:\n            return None\n        else:\n            bytes_: List[Byte] = []\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n\n            for element in self._buffer_a[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n            for element in self._buffer_c[start_elem:end_elem]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n            return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        dpu_arg_size_immediate = Immediate(Representation.UNSIGNED, 32, self._dpu_arg_size)\n        bytes_ += dpu_arg_size_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[execution])\n        bytes_ += kernel_immediate.to_bytes()\n\n        tcount_immediate = Immediate(Representation.UNSIGNED, 64, self._tcount[dpu_id][execution])\n        bytes_ += tcount_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if execution != 0:\n            return None\n        else:\n            bytes_: List[Byte] = []\n\n            for element in self._result_t_count[dpu_id]:\n                element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/sel_data_prep.py",
    "content": "import math\nfrom typing import List, Optional\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass Result:\n    def __init__(self, t_count=0, first=0, last=0):\n        self._t_count: int = t_count\n        self._first: int = first\n        self._last: int = last\n\n\nclass SELDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n\n        self._num_executions: int = 1\n\n        elem_size = 8\n\n        regs = 128\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if input_size_dpu % (num_tasklets * regs) != 0:\n            self._input_size_dpu_round = math.ceil(input_size_dpu / (num_tasklets * regs)) * (num_tasklets * regs)\n        else:\n            self._input_size_dpu_round = input_size_dpu\n\n        self._buffer_a: List[int] = [\n            i + 1 if i < input_size else 0 for i in range(self._input_size_dpu_round * self._num_dpus)\n        ]\n\n        self._buffer_c: List[List[int]] = [[] for _ in range(self._num_dpus)]\n        self._pos: List[int] = [0 for _ in range(self._num_dpus)]\n\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_round * dpu_id\n            end_elem = self._input_size_dpu_round * (dpu_id + 1)\n\n            self._buffer_c[dpu_id] = list(filter(lambda e: e % 2 != 0, self._buffer_a[start_elem:end_elem]))\n            self._pos[dpu_id] = len(self._buffer_c[dpu_id])\n\n            while len(self._buffer_c[dpu_id]) < self._input_size_dpu_round:\n                self._buffer_c[dpu_id].append(0)\n\n        self._dpu_arg_size: List[int] = [self._input_size_dpu_round * elem_size for _ in range(self._num_dpus)]\n        self._kernel: List[int] = [0 for _ in range(self._num_dpus)]\n\n        self._result: List[List[int]] = [\n            [0 if i != self._num_tasklets - 1 else self._pos[dpu_id] for i in range(self._num_tasklets)]\n            for dpu_id in range(self._num_dpus)\n        ]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_round * dpu_id\n\n        for i in range(self._input_size_dpu_round):\n            element_immediate = Immediate(Representation.UNSIGNED, 64, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_round * dpu_id\n\n        for i in range(self._input_size_dpu_round):\n            element_immediate = Immediate(Representation.UNSIGNED, 64, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        iter = 0\n        for element in self._buffer_c[dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n            bytes_ += element_immediate.to_bytes()\n            iter += 1\n            if iter >= self._pos[dpu_id]:\n                break\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        dpu_arg_size_immediate = Immediate(Representation.UNSIGNED, 32, self._dpu_arg_size[dpu_id])\n        bytes_ += dpu_arg_size_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[dpu_id])\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        for element in self._result[dpu_id]:\n            t_count_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += t_count_immediate.to_bytes()\n\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/trns_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass TRNSDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        if self._num_dpus > 1:\n            self._N_: int = 64  # Should be greater than or equal to \"self._num_dpus\" for strong scaling to fully utilize all DPUs.\n            self._n: int = 8\n            self._M_: int = data_prep_param[0]\n            self._m: int = 4\n        else:\n            self._N_: int = 1\n            self._n: int = 4\n            self._M_: int = data_prep_param[0]\n            self._m: int = 16\n        \n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        self._N_ = self._N_ if self._is_strong_scaling else self._N_ * self._num_dpus\n\n        self._num_active_dpus_at_begining: int = self._num_dpus if self._N_ > self._num_dpus else self._N_\n\n        self._num_executions: int = (\n            2 * (self._N_ // self._num_active_dpus_at_begining) if self._is_strong_scaling else 2 * self._N_\n        )\n\n        self._buffer_a: List[List[List[int]]] = [\n            [[IntInitializer.value_by_range(0, 100) for _ in range(self._n)] for _ in range(self._M_ * self._m)]\n            for _ in range(self._N_)\n        ]\n\n        self._done: List[int] = []\n        if (self._M_ * self._n) // 8 == 0:\n            for _ in range(8):\n                self._done.append(0)\n        else:\n            for _ in range(self._M_ * self._n):\n                self._done.append(0)\n\n        self._buffer_c: List[List[List[int]]] = [[] for _ in range(self._N_)]\n        for n in range(self._N_):\n            self._buffer_c[n] = np.transpose(self._buffer_a[n]).tolist()\n\n        self._kernel: List[int] = [0, 1]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if (execution % 2) != 0:\n            return None\n        else:\n            bytes_: List[Byte] = []\n\n            for row in self._buffer_a[(self._num_active_dpus_at_begining * (execution // 2)) + dpu_id]:\n                for element in row:\n                    element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                    bytes_ += element_immediate.to_bytes()\n            for element in self._done:\n                element_immediate = Immediate(Representation.UNSIGNED, 8, element)\n                bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        if (execution % 2) != 1:\n            return None\n        else:\n            bytes_: List[Byte] = []\n\n            for row in self._buffer_c[(self._num_active_dpus_at_begining * (execution // 2)) + dpu_id]:\n                for element in row:\n                    element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n                    bytes_ += element_immediate.to_bytes()\n\n            return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        m_immediate = Immediate(Representation.UNSIGNED, 32, self._m)\n        bytes_ += m_immediate.to_bytes()\n\n        n_immediate = Immediate(Representation.UNSIGNED, 32, self._n)\n        bytes_ += n_immediate.to_bytes()\n\n        M_immediate = Immediate(Representation.UNSIGNED, 32, self._M_)\n        bytes_ += M_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[execution % 2])\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/ts_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass TSDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._ts_size: int = data_prep_param[0]\n        self._query_length: int = 64  \n\n        if self._ts_size % (self._num_dpus * self._num_tasklets * self._query_length):\n            self._ts_size = self._ts_size + (\n                (self._num_dpus * self._num_tasklets * self._query_length)\n                - (self._ts_size % (self._num_dpus * self._num_tasklets * self._query_length))\n            )\n\n        self._num_executions: int = 1\n        self._t_series_buffer: List[int] = [i % 127 for i in range(self._ts_size)]\n        self._query_buffer: List[int] = [i % 127 for i in range(self._query_length)]\n\n        self._asigma_buffer: List[int] = [0 for _ in range(self._ts_size)]\n        self._amean_buffer: List[int] = [0 for _ in range(self._ts_size)]\n\n        acum_sum_buffer: List[int] = []\n        for i in range(self._ts_size):\n            if i == 0:\n                acum_sum_buffer.append(self._t_series_buffer[0])\n            else:\n                acum_sum_buffer.append(self._t_series_buffer[i] + acum_sum_buffer[i - 1])\n\n        asqcum_sum_buffer: List[int] = []\n        for i in range(self._ts_size):\n            if i == 0:\n                asqcum_sum_buffer.append(self._t_series_buffer[0] * self._t_series_buffer[0])\n            else:\n                asqcum_sum_buffer.append(self._t_series_buffer[i] * self._t_series_buffer[i] + asqcum_sum_buffer[i - 1])\n\n        asum_buffer: List[int] = []\n        for i in range(self._ts_size - self._query_length + 1):\n            if i == 0:\n                asum_buffer.append(acum_sum_buffer[self._query_length - 1])\n            else:\n                asum_buffer.append(acum_sum_buffer[self._query_length + i - 1] - acum_sum_buffer[i - 1])\n\n        asum_sq_buffer: List[int] = []\n        for i in range(self._ts_size - self._query_length + 1):\n            if i == 0:\n                asum_sq_buffer.append(asqcum_sum_buffer[self._query_length - 1])\n            else:\n                asum_sq_buffer.append(asqcum_sum_buffer[self._query_length + i - 1] - asqcum_sum_buffer[i - 1])\n\n        amean_temp_buffer: List[int] = [\n            asum_buffer[i] // self._query_length for i in range(self._ts_size - self._query_length)\n        ]\n        asigma_sq_buffer: List[int] = [\n            asum_sq_buffer[i] // self._query_length - self._amean_buffer[i] * self._amean_buffer[i]\n            for i in range(self._ts_size - self._query_length)\n        ]\n\n        self._asigma_buffer = [int(np.sqrt(asigma_sq_buffer[i])) for i in range(self._ts_size - self._query_length)]\n        self._amean_buffer = [amean_temp_buffer[i] for i in range(self._ts_size - self._query_length)]\n\n        for i in range(self._query_length):\n            self._t_series_buffer.append(0)\n        for i in range(self._query_length * 2):\n            self._asigma_buffer.append(0)\n            self._amean_buffer.append(0)\n\n        assert len(self._t_series_buffer) == len(self._amean_buffer)\n\n        queryMean = 0\n        for i in range(self._query_length):\n            queryMean += self._query_buffer[i]\n\n        queryMean = queryMean / self._query_length\n        self._query_mean = int(queryMean)\n\n        queryVariance = 0\n        for i in range(self._query_length):\n            queryVariance += (self._query_buffer[i] - queryMean) * (self._query_buffer[i] - queryMean)\n\n        queryVariance = queryVariance / self._query_length\n        queryStdDev = np.sqrt(queryVariance)\n        self._query_std = int(queryStdDev)\n\n        self._slice_per_dpu = self._ts_size // self._num_dpus\n\n        self._min_val: List[List[int]] = [\n            [0x7FFFFFFF for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)\n        ]\n        self._min_idx: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n        self._max_val: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n        self._max_idx: List[List[int]] = [[0 for _ in range(self._num_tasklets)] for _ in range(self._num_dpus)]\n\n        my_start_elem: List[List[int]] = [\n            [\n                self._slice_per_dpu * dpu_id + i * (self._slice_per_dpu // self._num_tasklets)\n                for i in range(self._num_tasklets)\n            ]\n            for dpu_id in range(self._num_dpus)\n        ]\n        my_end_elem: List[List[int]] = [\n            [\n                my_start_elem[dpu_id][i] + (self._slice_per_dpu // self._num_tasklets) - 1\n                for i in range(self._num_tasklets)\n            ]\n            for dpu_id in range(self._num_dpus)\n        ]\n\n        for dpu_id in range(self._num_dpus):\n            for i in range(self._num_tasklets):\n                if my_end_elem[dpu_id][i] > self._slice_per_dpu * (dpu_id + 1) - self._query_length:\n                    my_end_elem[dpu_id][i] = self._slice_per_dpu * (dpu_id + 1) - self._query_length\n\n        self._block_size: int = 256\n        self._elem_size: int = 4\n        increment: int = self._block_size // self._elem_size\n        self._dotpip: int = self._block_size // self._elem_size\n        iter: int = 0\n        for dpu_id in range(self._num_dpus):\n            iter = 0\n            for tasklet in range(self._num_tasklets):\n                for i in range(my_start_elem[dpu_id][tasklet], my_end_elem[dpu_id][tasklet], increment):\n                    self._cache_dotprods: List[int] = [0 for d in range(self._dotpip)]\n\n                    for j in range(self._query_length // (increment)):\n                        self.dot_product(\n                            self._t_series_buffer[i : i + increment],\n                            self._t_series_buffer[i + increment : (i + 2 * increment)],\n                            self._query_buffer[j * increment : (j + 1) * increment],\n                            self._cache_dotprods,\n                        )\n\n                    for k in range(increment):\n                        distance = 2 * (\n                            self._query_length\n                            - (\n                                self._cache_dotprods[k]\n                                - self._query_length\n                                * self._amean_buffer[k + iter * increment + dpu_id * self._slice_per_dpu]\n                                * self._query_mean\n                            )\n                            // (\n                                self._asigma_buffer[k + iter * increment + dpu_id * self._slice_per_dpu]\n                                * self._query_std\n                            )\n                        )\n\n                        if distance < self._min_val[dpu_id][tasklet]:\n                            self._min_val[dpu_id][tasklet] = distance\n                            self._min_idx[dpu_id][tasklet] = i + k - (dpu_id * self._slice_per_dpu)\n                    iter += 1\n\n        self._exclusion_zone: int = 0\n        self._kernel: int = 0\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._slice_per_dpu * dpu_id\n        end_elem = self._slice_per_dpu * (dpu_id + 1) + self._query_length\n\n        for element in self._query_buffer:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._t_series_buffer[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._amean_buffer[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._asigma_buffer[start_elem:end_elem]:\n            element_immediate = Immediate(Representation.UNSIGNED, 32, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        ts_size_immediate = Immediate(Representation.UNSIGNED, 32, self._ts_size)\n        bytes_ += ts_size_immediate.to_bytes()\n\n        query_length_immediate = Immediate(Representation.UNSIGNED, 32, self._query_length)\n        bytes_ += query_length_immediate.to_bytes()\n\n        query_mean_immediate = Immediate(Representation.UNSIGNED, 32, self._query_mean)\n        bytes_ += query_mean_immediate.to_bytes()\n\n        query_std_immediate = Immediate(Representation.UNSIGNED, 32, self._query_std)\n        bytes_ += query_std_immediate.to_bytes()\n\n        slice_per_dpu_immediate = Immediate(Representation.UNSIGNED, 32, self._slice_per_dpu)\n        bytes_ += slice_per_dpu_immediate.to_bytes()\n\n        exclusion_zone_immediate = Immediate(Representation.UNSIGNED, 32, self._exclusion_zone)\n        bytes_ += exclusion_zone_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel)\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        for tasklet in range(self._num_tasklets):\n            min_val_immediate = Immediate(Representation.UNSIGNED, 32, self._min_val[dpu_id][tasklet])\n            bytes_ += min_val_immediate.to_bytes()\n\n            min_idx_immediate = Immediate(Representation.UNSIGNED, 32, self._min_idx[dpu_id][tasklet])\n            bytes_ += min_idx_immediate.to_bytes()\n\n            max_val_immediate = Immediate(Representation.UNSIGNED, 32, self._max_val[dpu_id][tasklet])\n            bytes_ += max_val_immediate.to_bytes()\n\n            max_idx_immediate = Immediate(Representation.UNSIGNED, 32, self._max_idx[dpu_id][tasklet])\n            bytes_ += max_idx_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dot_product(\n        self,\n        vector_a: List[int],\n        vector_a_aux: List[int],\n        vector_query: List[int],\n        vector_result: List[int],\n    ):\n        for i in range(self._block_size // self._elem_size):\n            for j in range(self._dotpip):\n                if (j + i) > (self._block_size // self._elem_size) - 1:\n                    vector_result[j] += vector_a_aux[(j + i) - self._block_size // self._elem_size] * vector_query[i]\n                else:\n                    vector_result[j] += vector_a[j + i] * vector_query[i]\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/uni_data_prep.py",
    "content": "import math\nfrom typing import List, Optional\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass Result:\n    def __init__(self, t_count=0, first=0, last=0):\n        self._t_count: int = t_count\n        self._first: int = first\n        self._last: int = last\n\n\nclass UNIDataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        self._size: int = data_prep_param[0]\n\n        self._num_executions: int = 1\n\n        elem_size = 8\n\n        regs = 128\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._size if self._is_strong_scaling else self._size * self._num_dpus\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if input_size_dpu % (num_tasklets * regs) != 0:\n            self._input_size_dpu_round = math.ceil(input_size_dpu / (num_tasklets * regs)) * (num_tasklets * regs)\n        else:\n            self._input_size_dpu_round = input_size_dpu\n\n        self._buffer_a: List[int] = [0 for _ in range(self._input_size_dpu_round * self._num_dpus)]\n        for i in range(self._input_size_dpu_round * self._num_dpus):\n            if i < input_size:\n                if i % 2 == 0:\n                    self._buffer_a[i] = i\n                else:\n                    self._buffer_a[i] = i + 1\n            else:\n                self._buffer_a[i] = self._buffer_a[input_size - 1]\n\n        self._buffer_c: List[List[int]] = [\n            [0 for _ in range(self._input_size_dpu_round)] for _ in range(self._num_dpus)\n        ]\n\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_round * dpu_id\n\n            self._buffer_c[dpu_id][0] = self._buffer_a[start_elem]\n\n            self._pos = 1\n\n            for i in range(1, self._input_size_dpu_round):\n                if self._buffer_a[start_elem + i] != self._buffer_a[start_elem + i - 1]:\n                    self._buffer_c[dpu_id][self._pos] = self._buffer_a[start_elem + i]\n                    self._pos += 1\n\n        self._input_size_dpu: List[int] = [self._input_size_dpu_round * elem_size for _ in range(self._num_dpus)]\n        self._kernel: List[int] = [0 for _ in range(self._num_dpus)]\n\n        self._result: List[List[Result]] = [[] for _ in range(self._num_dpus)]\n        for dpu_id in range(self._num_dpus):\n            start_elem = self._input_size_dpu_round * dpu_id\n            for tasklet_id in range(self._num_tasklets):\n                if tasklet_id == 0 and tasklet_id != self._num_tasklets - 1:\n                    self._result[dpu_id].append(Result(0, self._buffer_a[start_elem], 0))\n                elif tasklet_id == self._num_tasklets - 1:\n                    self._result[dpu_id].append(Result(self._pos, 0, self._buffer_c[dpu_id][self._pos - 1]))\n                else:\n                    self._result[dpu_id].append(Result())\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_round * dpu_id\n\n        for i in range(self._input_size_dpu_round):\n            element_immediate = Immediate(Representation.UNSIGNED, 64, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_round * dpu_id\n\n        for i in range(self._input_size_dpu_round):\n            element_immediate = Immediate(Representation.UNSIGNED, 64, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        for element in self._buffer_c[dpu_id]:\n            element_immediate = Immediate(Representation.UNSIGNED, 64, element)\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        input_size_dpu_immediate = Immediate(Representation.UNSIGNED, 32, self._input_size_dpu[dpu_id])\n        bytes_ += input_size_dpu_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[dpu_id])\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        for element in self._result[dpu_id]:\n            t_count_immediate = Immediate(Representation.UNSIGNED, 64, element._t_count)\n            bytes_ += t_count_immediate.to_bytes()\n\n            first_immediate = Immediate(Representation.UNSIGNED, 64, element._first)\n            bytes_ += first_immediate.to_bytes()\n\n            last_immediate = Immediate(Representation.UNSIGNED, 64, element._last)\n            bytes_ += last_immediate.to_bytes()\n\n        return Bin(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/assembler/data_prep/va_data_prep.py",
    "content": "from typing import List, Optional\n\nimport numpy as np\n\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom assembler.data_prep.bin import Bin\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass VADataPrep:\n    def __init__(self, num_tasklets: int, data_prep_param: List[int], num_dpus: int):\n        assert 0 < num_tasklets < ConfigLoader.max_num_tasklets()\n\n        self._num_tasklets: int = num_tasklets\n        self._num_dpus: int = num_dpus\n\n        # NOTE(bongjoon.hyun@gmail.com): PrIM default buffer size is 2621440\n        self._buffer_size: int = data_prep_param[0]  # 1048576\n\n        self._num_executions: int = 1\n\n        elem_size = 4\n\n        self._is_strong_scaling = True  # True --> strong scaling / False --> weak scaling\n        input_size = self._buffer_size if self._is_strong_scaling else self._buffer_size * self._num_dpus\n\n        if (input_size * elem_size) % 8 != 0:\n            input_size_8bytes = (input_size // 8) * 8 + 8\n        else:\n            input_size_8bytes = input_size\n\n        input_size_dpu = ((input_size) - 1) // (self._num_dpus) + 1\n\n        if (input_size_dpu * elem_size) % 8 != 0:\n            self._input_size_dpu_8bytes = (input_size_dpu // 8) * 8 + 8\n        else:\n            self._input_size_dpu_8bytes = input_size_dpu\n\n        self._buffer_a: List[int] = [0 for _ in range(self._input_size_dpu_8bytes * num_dpus)]\n        self._buffer_b: List[int] = [0 for _ in range(self._input_size_dpu_8bytes * num_dpus)]\n\n        for i in range(input_size):\n            self._buffer_a[i] = IntInitializer.value_by_range(0, 2**31)\n            self._buffer_b[i] = IntInitializer.value_by_range(0, 2**31)\n\n        self._buffer_c: List[int] = list(np.add(self._buffer_a, self._buffer_b))\n\n        self._size: List[int] = [self._input_size_dpu_8bytes * elem_size for _ in range(self._num_dpus - 1)]\n        self._size.append((input_size_8bytes - (self._input_size_dpu_8bytes * (self._num_dpus - 1))) * elem_size)\n\n        self._transfer_size: List[int] = [self._input_size_dpu_8bytes * elem_size for _ in range(self._num_dpus)]\n\n        self._kernel: List[int] = [0 for _ in range(self._num_dpus)]\n\n    def num_executions(self) -> int:\n        return self._num_executions\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def input_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_8bytes * dpu_id\n\n        for i in range(self._input_size_dpu_8bytes):\n            element_immediate = Immediate(Representation.UNSIGNED, 32, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        for i in range(self._input_size_dpu_8bytes):\n            element_immediate = Immediate(Representation.UNSIGNED, 32, self._buffer_b[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def output_dpu_mram_heap_pointer_name(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        start_elem = self._input_size_dpu_8bytes * dpu_id\n\n        for i in range(self._input_size_dpu_8bytes):\n            element_immediate = Immediate(Representation.UNSIGNED, 32, self._buffer_a[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        for i in range(self._input_size_dpu_8bytes):\n            element_immediate = Immediate(Representation.UNSIGNED, 32, self._buffer_c[start_elem + i])\n            bytes_ += element_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_input_arguments(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        bytes_: List[Byte] = []\n\n        size_immediate = Immediate(Representation.UNSIGNED, 32, self._size[dpu_id])\n        bytes_ += size_immediate.to_bytes()\n\n        transfer_size_immediate = Immediate(Representation.UNSIGNED, 32, self._transfer_size[dpu_id])\n        bytes_ += transfer_size_immediate.to_bytes()\n\n        kernel_immediate = Immediate(Representation.UNSIGNED, 32, self._kernel[dpu_id])\n        bytes_ += kernel_immediate.to_bytes()\n\n        return Bin(bytes_)\n\n    def dpu_results(self, execution: int, dpu_id: int) -> Optional[Bin]:\n        assert 0 <= execution < self._num_executions\n        assert 0 <= dpu_id < self._num_dpus\n\n        return None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/compiler/compiler.py",
    "content": "import os\nfrom typing import Set\n\nfrom util.docker_client import DockerClient\nfrom util.path_collector import PathCollector\n\n\nclass Compiler:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def compile_benchmark(benchmark: str, num_tasklets: int):\n        source = Compiler._source_command()\n        cd = f\"cd {PathCollector.benchmark_path_in_docker()}/{benchmark}\"\n        make_clean = \"make clean\"\n        make = f\"make NR_TASKLETS={num_tasklets}\"\n        mkdir = f\"mkdir -p {PathCollector.asm_path_in_docker()}/{benchmark}.{num_tasklets}\"\n        mv = f\"mv {PathCollector.benchmark_path_in_docker()}/{benchmark}/bin/dpu_code.S {PathCollector.asm_path_in_docker()}/{benchmark}.{num_tasklets}/main.S\"\n        commands = [source, cd, make_clean, make, mkdir, mv]\n\n        return DockerClient.run(Compiler._docker_image(), commands)\n\n    @staticmethod\n    def compile_sdk(num_tasklets: int) -> bool:\n        for filepath in Compiler._sdk_filepaths_in_docker():\n            library_name, filename = filepath.split(\"/\")[-2], filepath.split(\"/\")[-1]\n\n            common_flags = f\"-O3 -S -w -DNR_TASKLETS=${num_tasklets}\"\n            include_flags = f\"-I{Compiler._misc_path()} -I{Compiler._stdlib_path()} -I{Compiler._syslib_path()}\"\n            output_flag = f\"-o {PathCollector.asm_path_in_docker()}/{library_name}/{filename[:-2]}.S\"\n\n            source = Compiler._source_command()\n            mkdir = f\"mkdir -p {PathCollector.asm_path_in_docker()}/{library_name}\"\n            dpu_upmem_dpu_rte_clang = (\n                f\"{Compiler._dpu_upmem_dpurte_clang()} {common_flags} {include_flags} {output_flag} {filepath}\"\n            )\n            commands = [source, mkdir, dpu_upmem_dpu_rte_clang]\n\n            if not DockerClient.run(Compiler._docker_image(), commands):\n                return False\n        return True\n\n    @staticmethod\n    def clean() -> bool:\n        rm = f\"rm -rf {PathCollector.asm_path_in_docker()}\"\n        return DockerClient.run(Compiler._docker_image(), [rm])\n\n    @staticmethod\n    def _sdk_filepaths_in_docker() -> Set[str]:\n        filepaths: Set[str] = set()\n        for root_path, _, filenames in os.walk(PathCollector.sdk_path_in_local()):\n            for filename in filenames:\n                if filename.split(\".\")[-1] == \"c\":\n                    library_name = root_path.split(os.path.sep)[-1]\n                    filepaths.add(f\"{PathCollector.sdk_path_in_docker()}/{library_name}/{filename}\")\n        return filepaths\n\n    @staticmethod\n    def _docker_image() -> str:\n        return \"compiler\"\n\n    @staticmethod\n    def _source_command() -> str:\n        return f\"source {PathCollector.upmem_sdk_path_in_docker()}/upmem_env.sh\"\n\n    @staticmethod\n    def _upmem_include_path() -> str:\n        return f\"{PathCollector.upmem_sdk_path_in_docker()}/include\"\n\n    @staticmethod\n    def _misc_path() -> str:\n        return f\"{PathCollector.sdk_path_in_docker()}/misc\"\n\n    @staticmethod\n    def _stdlib_path() -> str:\n        return f\"{PathCollector.sdk_path_in_docker()}/stdlib\"\n\n    @staticmethod\n    def _syslib_path() -> str:\n        return f\"{PathCollector.sdk_path_in_docker()}/syslib\"\n\n    @staticmethod\n    def _dpu_upmem_dpurte_clang() -> str:\n        return \"dpu-upmem-dpurte-clang\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/condition_converter.py",
    "content": "from abi.isa.instruction.condition import Condition\n\n\nclass ConditionConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_condition(condition: str) -> Condition:\n        if condition == \"true\":\n            return Condition.TRUE\n        elif condition == \"false\":\n            return Condition.FALSE\n        elif condition == \"z\":\n            return Condition.Z\n        elif condition == \"nz\":\n            return Condition.NZ\n        elif condition == \"e\":\n            return Condition.E\n        elif condition == \"o\":\n            return Condition.O\n        elif condition == \"pl\":\n            return Condition.PL\n        elif condition == \"mi\":\n            return Condition.MI\n        elif condition == \"ov\":\n            return Condition.OV\n        elif condition == \"nov\":\n            return Condition.NOV\n        elif condition == \"c\":\n            return Condition.C\n        elif condition == \"nc\":\n            return Condition.NC\n        elif condition == \"sz\":\n            return Condition.SZ\n        elif condition == \"snz\":\n            return Condition.SNZ\n        elif condition == \"spl\":\n            return Condition.SPL\n        elif condition == \"smi\":\n            return Condition.SMI\n        elif condition == \"so\":\n            return Condition.SO\n        elif condition == \"se\":\n            return Condition.SE\n        elif condition == \"nc5\":\n            return Condition.NC5\n        elif condition == \"nc6\":\n            return Condition.NC6\n        elif condition == \"nc7\":\n            return Condition.NC7\n        elif condition == \"nc8\":\n            return Condition.NC8\n        elif condition == \"nc9\":\n            return Condition.NC9\n        elif condition == \"nc10\":\n            return Condition.NC10\n        elif condition == \"nc11\":\n            return Condition.NC11\n        elif condition == \"nc12\":\n            return Condition.NC12\n        elif condition == \"nc13\":\n            return Condition.NC13\n        elif condition == \"nc14\":\n            return Condition.NC14\n        elif condition == \"max\":\n            return Condition.MAX\n        elif condition == \"nmax\":\n            return Condition.NMAX\n        elif condition == \"sh32\":\n            return Condition.SH32\n        elif condition == \"nsh32\":\n            return Condition.NSH32\n        elif condition == \"eq\":\n            return Condition.EQ\n        elif condition == \"neq\":\n            return Condition.NEQ\n        elif condition == \"ltu\":\n            return Condition.LTU\n        elif condition == \"leu\":\n            return Condition.LEU\n        elif condition == \"gtu\":\n            return Condition.GTU\n        elif condition == \"geu\":\n            return Condition.GEU\n        elif condition == \"lts\":\n            return Condition.LTS\n        elif condition == \"les\":\n            return Condition.LES\n        elif condition == \"gts\":\n            return Condition.GTS\n        elif condition == \"ges\":\n            return Condition.GES\n        elif condition == \"xz\":\n            return Condition.XZ\n        elif condition == \"xnz\":\n            return Condition.XNZ\n        elif condition == \"xleu\":\n            return Condition.XLEU\n        elif condition == \"xgtu\":\n            return Condition.XGTU\n        elif condition == \"xles\":\n            return Condition.XLES\n        elif condition == \"xgts\":\n            return Condition.XGTS\n        elif condition == \"small\":\n            return Condition.SMALL\n        elif condition == \"large\":\n            return Condition.LARGE\n        else:\n            raise ValueError\n\n    @staticmethod\n    def convert_to_string(condition: Condition) -> str:\n        if condition == Condition.TRUE:\n            return \"true\"\n        elif condition == Condition.FALSE:\n            return \"false\"\n        elif condition == Condition.Z:\n            return \"z\"\n        elif condition == Condition.NZ:\n            return \"nz\"\n        elif condition == Condition.E:\n            return \"e\"\n        elif condition == Condition.O:\n            return \"o\"\n        elif condition == Condition.PL:\n            return \"pl\"\n        elif condition == Condition.MI:\n            return \"mi\"\n        elif condition == Condition.OV:\n            return \"ov\"\n        elif condition == Condition.NOV:\n            return \"nov\"\n        elif condition == Condition.C:\n            return \"c\"\n        elif condition == Condition.NC:\n            return \"nc\"\n        elif condition == Condition.SZ:\n            return \"sz\"\n        elif condition == Condition.SNZ:\n            return \"snz\"\n        elif condition == Condition.SPL:\n            return \"spl\"\n        elif condition == Condition.SMI:\n            return \"smi\"\n        elif condition == Condition.SO:\n            return \"so\"\n        elif condition == Condition.SE:\n            return \"se\"\n        elif condition == Condition.NC5:\n            return \"nc5\"\n        elif condition == Condition.NC6:\n            return \"nc6\"\n        elif condition == Condition.NC7:\n            return \"nc7\"\n        elif condition == Condition.NC8:\n            return \"nc8\"\n        elif condition == Condition.NC9:\n            return \"nc9\"\n        elif condition == Condition.NC10:\n            return \"nc10\"\n        elif condition == Condition.NC11:\n            return \"nc11\"\n        elif condition == Condition.NC12:\n            return \"nc12\"\n        elif condition == Condition.NC13:\n            return \"nc13\"\n        elif condition == Condition.NC14:\n            return \"nc14\"\n        elif condition == Condition.MAX:\n            return \"max\"\n        elif condition == Condition.NMAX:\n            return \"nmax\"\n        elif condition == Condition.SH32:\n            return \"sh32\"\n        elif condition == Condition.NSH32:\n            return \"nsh32\"\n        elif condition == Condition.EQ:\n            return \"eq\"\n        elif condition == Condition.NEQ:\n            return \"neq\"\n        elif condition == Condition.LTU:\n            return \"ltu\"\n        elif condition == Condition.LEU:\n            return \"leu\"\n        elif condition == Condition.GTU:\n            return \"gtu\"\n        elif condition == Condition.GEU:\n            return \"geu\"\n        elif condition == Condition.LTS:\n            return \"lts\"\n        elif condition == Condition.LES:\n            return \"les\"\n        elif condition == Condition.GTS:\n            return \"gts\"\n        elif condition == Condition.GES:\n            return \"ges\"\n        elif condition == Condition.XZ:\n            return \"xz\"\n        elif condition == Condition.XNZ:\n            return \"xnz\"\n        elif condition == Condition.XLEU:\n            return \"xleu\"\n        elif condition == Condition.XGTU:\n            return \"xgtu\"\n        elif condition == Condition.XLES:\n            return \"xles\"\n        elif condition == Condition.XGTS:\n            return \"xgts\"\n        elif condition == Condition.SMALL:\n            return \"small\"\n        elif condition == Condition.LARGE:\n            return \"large\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/endian_converter.py",
    "content": "from abi.isa.instruction.endian import Endian\n\n\nclass EndianConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_endian(endian: str) -> Endian:\n        if endian == \"!little\":\n            return Endian.LITTLE\n        elif endian == \"!big\":\n            return Endian.BIG\n        else:\n            raise ValueError\n\n    @staticmethod\n    def convert_to_string(endian: Endian) -> str:\n        if endian == Endian.LITTLE:\n            return \"!little\"\n        elif endian == Endian.BIG:\n            return \"!big\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/instruction_converter.py",
    "content": "from abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom converter.condition_converter import ConditionConverter\nfrom converter.endian_converter import EndianConverter\nfrom converter.op_code_converter import OpCodeConverter\nfrom converter.register_converter import RegisterConverter\nfrom converter.suffix_converter import SuffixConverter\n\n\nclass InstructionConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_string(instruction: Instruction) -> str:\n        op_code = OpCodeConverter.convert_to_string(instruction.op_code())\n        suffix = SuffixConverter.convert_to_string(instruction.suffix())\n\n        if instruction.suffix() == Suffix.RICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRIC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rric_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRIF:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrif_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRIC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zric_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRIF:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrif_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRI or instruction.suffix() == Suffix.U_RRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRIC or instruction.suffix() == Suffix.U_RRIC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rric_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRICI or instruction.suffix() == Suffix.U_RRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRIF or instruction.suffix() == Suffix.U_RRIF:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrif_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRR or instruction.suffix() == Suffix.U_RRR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRRC or instruction.suffix() == Suffix.U_RRRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRRCI or instruction.suffix() == Suffix.U_RRRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RR or instruction.suffix() == Suffix.U_RR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rr_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRC or instruction.suffix() == Suffix.U_RRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRCI or instruction.suffix() == Suffix.U_RRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.DRDICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_drdici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RRRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rrrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZRRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zrrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRRI or instruction.suffix() == Suffix.U_RRRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RRRICI or instruction.suffix() == Suffix.U_RRRICI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rrrici_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RIR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rir_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RIRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rirc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RIRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rirci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZIR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zir_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZIRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zirc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZIRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zirci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RIRC or instruction.suffix() == Suffix.U_RIRC:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rirc_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RIRCI or instruction.suffix() == Suffix.U_RIRCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rirci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.R:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_r_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.RCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_rci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.Z:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_z_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ZCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_zci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_R or instruction.suffix() == Suffix.U_R:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_r_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_RCI or instruction.suffix() == Suffix.U_RCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_rci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.CI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_ci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.I:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_i_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.DDCI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_ddci_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ERRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_erri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.S_ERRI or instruction.suffix() == Suffix.U_ERRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_s_erri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.EDRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_edri_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ERII:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_erii_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ERIR:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_erir_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.ERID:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_erid_to_string(instruction)}\"\n        elif instruction.suffix() == Suffix.DMA_RRI:\n            return f\"{op_code}, {suffix}, {InstructionConverter._convert_dma_rri_to_string(instruction)}\"\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _convert_rici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RICIOpCodes\n        assert instruction.suffix() == Suffix.RICI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{ra}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_rri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.RRI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        return f\"{rc}, {ra}, {imm}\"\n\n    @staticmethod\n    def _convert_rric_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{rc}, {ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_rrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {ra}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_rrif_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.RRIF\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{rc}, {ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_rrr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.RRR\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        return f\"{rc}, {ra}, {rb}\"\n\n    @staticmethod\n    def _convert_rrrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.RRRC\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{rc}, {ra}, {rb}, {condition}\"\n\n    @staticmethod\n    def _convert_rrrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {ra}, {rb}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_zri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.ZRI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        return f\"{ra}, {imm}\"\n\n    @staticmethod\n    def _convert_zric_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.ZRIC\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_zrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{ra}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_zrif_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.ZRIF\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_zrr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.ZRR\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        return f\"{ra}, {rb}\"\n\n    @staticmethod\n    def _convert_zrrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.ZRRC\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{ra}, {rb}, {condition}\"\n\n    @staticmethod\n    def _convert_zrrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{ra}, {rb}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_rri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRI or instruction.suffix() == Suffix.U_RRI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        return f\"{dc}, {ra}, {imm}\"\n\n    @staticmethod\n    def _convert_s_rric_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.S_RRIC or instruction.suffix() == Suffix.U_RRIC\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{dc}, {ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_s_rrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI or instruction.suffix() == Suffix.U_RRICI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {ra}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_rrif_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.S_RRIF or instruction.suffix() == Suffix.U_RRIF\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{dc}, {ra}, {imm}, {condition}\"\n\n    @staticmethod\n    def _convert_s_rrr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.S_RRR or instruction.suffix() == Suffix.U_RRR\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        return f\"{dc}, {ra}, {rb}\"\n\n    @staticmethod\n    def _convert_s_rrrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.S_RRRC or instruction.suffix() == Suffix.U_RRRC\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{dc}, {ra}, {rb}, {condition}\"\n\n    @staticmethod\n    def _convert_s_rrrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRCI or instruction.suffix() == Suffix.U_RRRCI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {ra}, {rb}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_rr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.RR\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        return f\"{rc}, {ra}\"\n\n    @staticmethod\n    def _convert_rrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.RRC\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{rc}, {ra}, {condition}\"\n\n    @staticmethod\n    def _convert_rrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.RRCI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_zr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.ZR\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        return f\"{ra}\"\n\n    @staticmethod\n    def _convert_zrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.ZRC\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{ra}, {condition}\"\n\n    @staticmethod\n    def _convert_zrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRCI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_rr_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.S_RR or instruction.suffix() == Suffix.U_RR\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        return f\"{dc}, {ra}\"\n\n    @staticmethod\n    def _convert_s_rrc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.S_RRC or instruction.suffix() == Suffix.U_RRC\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{dc}, {ra}, {condition}\"\n\n    @staticmethod\n    def _convert_s_rrci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RRCI or instruction.suffix() == Suffix.U_RRCI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_drdici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.DRDICIOpCodes\n        assert instruction.suffix() == Suffix.DRDICI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        db = RegisterConverter.convert_to_string(instruction.db())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {ra}, {db}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_rrri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.RRRI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        return f\"{rc}, {ra}, {rb}, {imm}\"\n\n    @staticmethod\n    def _convert_rrrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRRICI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {ra}, {rb}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_zrri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRRI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        return f\"{ra}, {rb}, {imm}\"\n\n    @staticmethod\n    def _convert_zrrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRRICI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{ra}, {rb}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_rrri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRI or instruction.suffix() == Suffix.U_RRRI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        return f\"{dc}, {ra}, {rb}, {imm}\"\n\n    @staticmethod\n    def _convert_s_rrrici_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRICI or instruction.suffix() == Suffix.U_RRRICI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {ra}, {rb}, {imm}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_rir_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.RIR\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        return f\"{rc}, {imm}, {ra}\"\n\n    @staticmethod\n    def _convert_rirc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.RIRC\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{rc}, {imm}, {ra}, {condition}\"\n\n    @staticmethod\n    def _convert_rirci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.RIRCI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {imm}, {ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_zir_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.ZIR\n\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        return f\"{imm}, {ra}\"\n\n    @staticmethod\n    def _convert_zirc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.ZIRC\n\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{imm}, {ra}, {condition}\"\n\n    @staticmethod\n    def _convert_zirci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.ZIRCI\n\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{imm}, {ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_rirc_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.S_RIRC or instruction.suffix() == Suffix.U_RIRC\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        return f\"{dc}, {imm}, {ra}, {condition}\"\n\n    @staticmethod\n    def _convert_s_rirci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RIRCI or instruction.suffix() == Suffix.U_RIRCI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        imm = str(instruction.imm().value())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {imm}, {ra}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_r_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ROpCodes\n        assert instruction.suffix() == Suffix.R\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        return f\"{rc}\"\n\n    @staticmethod\n    def _convert_rci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.RCI\n\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{rc}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_z_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ROpCodes or instruction.op_code() == OpCode.NOP\n        assert instruction.suffix() == Suffix.Z\n\n        return \"\"\n\n    @staticmethod\n    def _convert_zci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.ZCI\n\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{condition}, {pc}\"\n\n    @staticmethod\n    def _convert_s_r_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ROpCodes\n        assert instruction.suffix() == Suffix.S_R or instruction.suffix() == Suffix.U_R\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        return f\"{dc}\"\n\n    @staticmethod\n    def _convert_s_rci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.S_RCI or instruction.suffix() == Suffix.U_RCI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_ci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.CIOpCodes\n        assert instruction.suffix() == Suffix.CI\n\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{condition}, {pc}\"\n\n    @staticmethod\n    def _convert_i_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.IOpCodes\n        assert instruction.suffix() == Suffix.I\n\n        imm = str(instruction.imm().value())\n        return f\"{imm}\"\n\n    @staticmethod\n    def _convert_ddci_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.DDCIOpCodes\n        assert instruction.suffix() == Suffix.DDCI\n\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        db = RegisterConverter.convert_to_string(instruction.db())\n        condition = ConditionConverter.convert_to_string(instruction.condition())\n        pc = str(instruction.pc().value())\n        return f\"{dc}, {db}, {condition}, {pc}\"\n\n    @staticmethod\n    def _convert_erri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ERRIOpCodes\n        assert instruction.suffix() == Suffix.ERRI\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        rc = RegisterConverter.convert_to_string(instruction.rc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        return f\"{endian}, {rc}, {ra}, {off}\"\n\n    @staticmethod\n    def _convert_s_erri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ERRIOpCodes\n        assert instruction.suffix() == Suffix.S_ERRI or instruction.suffix() == Suffix.U_ERRI\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        return f\"{endian}, {dc}, {ra}, {off}\"\n\n    @staticmethod\n    def _convert_edri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.EDRIOpCodes\n        assert instruction.suffix() == Suffix.EDRI\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        dc = RegisterConverter.convert_to_string(instruction.dc())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        return f\"{endian}, {dc}, {ra}, {off}\"\n\n    @staticmethod\n    def _convert_erii_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ERIIOpCodes\n        assert instruction.suffix() == Suffix.ERII\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        imm = str(instruction.imm().value())\n        return f\"{endian}, {ra}, {off}, {imm}\"\n\n    @staticmethod\n    def _convert_erir_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ERIROpCodes\n        assert instruction.suffix() == Suffix.ERIR\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        return f\"{endian}, {ra}, {off}, {rb}\"\n\n    @staticmethod\n    def _convert_erid_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.ERIDOpCodes\n        assert instruction.suffix() == Suffix.ERID\n\n        endian = EndianConverter.convert_to_string(instruction.endian())\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        off = str(instruction.off().value())\n        db = RegisterConverter.convert_to_string(instruction.db())\n        return f\"{endian}, {ra}, {off}, {db}\"\n\n    @staticmethod\n    def _convert_dma_rri_to_string(instruction: Instruction) -> str:\n        assert instruction.op_code() in Instruction.DMARRIOpCodes\n        assert instruction.suffix() == Suffix.DMA_RRI\n\n        ra = RegisterConverter.convert_to_string(instruction.ra())\n        rb = RegisterConverter.convert_to_string(instruction.rb())\n        imm = str(instruction.imm().value())\n        return f\"{ra}, {rb}, {imm}\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/op_code_converter.py",
    "content": "from abi.isa.instruction.op_code import OpCode\n\n\nclass OpCodeConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_op_code(op_code: str) -> OpCode:\n        if op_code == \"acquire\":\n            return OpCode.ACQUIRE\n        elif op_code == \"release\":\n            return OpCode.RELEASE\n        elif op_code == \"add\":\n            return OpCode.ADD\n        elif op_code == \"addc\":\n            return OpCode.ADDC\n        elif op_code == \"and\":\n            return OpCode.AND\n        elif op_code == \"andn\":\n            return OpCode.ANDN\n        elif op_code == \"asr\":\n            return OpCode.ASR\n        elif op_code == \"cao\":\n            return OpCode.CAO\n        elif op_code == \"clo\":\n            return OpCode.CLO\n        elif op_code == \"cls\":\n            return OpCode.CLS\n        elif op_code == \"clz\":\n            return OpCode.CLZ\n        elif op_code == \"cmpb4\":\n            return OpCode.CMPB4\n        elif op_code == \"div_step\":\n            return OpCode.DIV_STEP\n        elif op_code == \"extsb\":\n            return OpCode.EXTSB\n        elif op_code == \"extsh\":\n            return OpCode.EXTSH\n        elif op_code == \"extub\":\n            return OpCode.EXTUB\n        elif op_code == \"extuh\":\n            return OpCode.EXTUH\n        elif op_code == \"lsl\":\n            return OpCode.LSL\n        elif op_code == \"lsl_add\":\n            return OpCode.LSL_ADD\n        elif op_code == \"lsl_sub\":\n            return OpCode.LSL_SUB\n        elif op_code == \"lsl1\":\n            return OpCode.LSL1\n        elif op_code == \"lsl1x\":\n            return OpCode.LSL1X\n        elif op_code == \"lslx\":\n            return OpCode.LSLX\n        elif op_code == \"lsr\":\n            return OpCode.LSR\n        elif op_code == \"lsr_add\":\n            return OpCode.LSR_ADD\n        elif op_code == \"lsr1\":\n            return OpCode.LSR1\n        elif op_code == \"lsr1x\":\n            return OpCode.LSR1X\n        elif op_code == \"lsrx\":\n            return OpCode.LSRX\n        elif op_code == \"mul_sh_sh\":\n            return OpCode.MUL_SH_SH\n        elif op_code == \"mul_sh_sl\":\n            return OpCode.MUL_SH_SL\n        elif op_code == \"mul_sh_uh\":\n            return OpCode.MUL_SH_UH\n        elif op_code == \"mul_sh_ul\":\n            return OpCode.MUL_SH_UL\n        elif op_code == \"mul_sl_sh\":\n            return OpCode.MUL_SL_SH\n        elif op_code == \"mul_sl_sl\":\n            return OpCode.MUL_SL_SL\n        elif op_code == \"mul_sl_uh\":\n            return OpCode.MUL_SL_UH\n        elif op_code == \"mul_sl_ul\":\n            return OpCode.MUL_SL_UL\n        elif op_code == \"mul_step\":\n            return OpCode.MUL_STEP\n        elif op_code == \"mul_uh_uh\":\n            return OpCode.MUL_UH_UH\n        elif op_code == \"mul_uh_ul\":\n            return OpCode.MUL_UH_UL\n        elif op_code == \"mul_ul_uh\":\n            return OpCode.MUL_UL_UH\n        elif op_code == \"mul_ul_ul\":\n            return OpCode.MUL_UL_UL\n        elif op_code == \"nand\":\n            return OpCode.NAND\n        elif op_code == \"nor\":\n            return OpCode.NOR\n        elif op_code == \"nxor\":\n            return OpCode.NXOR\n        elif op_code == \"or\":\n            return OpCode.OR\n        elif op_code == \"orn\":\n            return OpCode.ORN\n        elif op_code == \"rol\":\n            return OpCode.ROL\n        elif op_code == \"rol_add\":\n            return OpCode.ROL_ADD\n        elif op_code == \"ror\":\n            return OpCode.ROR\n        elif op_code == \"rsub\":\n            return OpCode.RSUB\n        elif op_code == \"rsubc\":\n            return OpCode.RSUBC\n        elif op_code == \"sub\":\n            return OpCode.SUB\n        elif op_code == \"subc\":\n            return OpCode.SUBC\n        elif op_code == \"xor\":\n            return OpCode.XOR\n        elif op_code == \"boot\":\n            return OpCode.BOOT\n        elif op_code == \"resume\":\n            return OpCode.RESUME\n        elif op_code == \"stop\":\n            return OpCode.STOP\n        elif op_code == \"call\":\n            return OpCode.CALL\n        elif op_code == \"fault\":\n            return OpCode.FAULT\n        elif op_code == \"nop\":\n            return OpCode.NOP\n        elif op_code == \"sats\":\n            return OpCode.SATS\n        elif op_code == \"movd\":\n            return OpCode.MOVD\n        elif op_code == \"swapd\":\n            return OpCode.SWAPD\n        elif op_code == \"hash\":\n            return OpCode.HASH\n        elif op_code == \"time\":\n            return OpCode.TIME\n        elif op_code == \"time_cfg\":\n            return OpCode.TIME_CFG\n        elif op_code == \"lbs\":\n            return OpCode.LBS\n        elif op_code == \"lbu\":\n            return OpCode.LBU\n        elif op_code == \"ld\":\n            return OpCode.LD\n        elif op_code == \"lhs\":\n            return OpCode.LHS\n        elif op_code == \"lhu\":\n            return OpCode.LHU\n        elif op_code == \"lw\":\n            return OpCode.LW\n        elif op_code == \"sb\":\n            return OpCode.SB\n        elif op_code == \"sb_id\":\n            return OpCode.SB_ID\n        elif op_code == \"sd\":\n            return OpCode.SD\n        elif op_code == \"sd_id\":\n            return OpCode.SD_ID\n        elif op_code == \"sh\":\n            return OpCode.SH\n        elif op_code == \"sh_id\":\n            return OpCode.SH_ID\n        elif op_code == \"sw\":\n            return OpCode.SW\n        elif op_code == \"sw_id\":\n            return OpCode.SW_ID\n        elif op_code == \"ldma\":\n            return OpCode.LDMA\n        elif op_code == \"ldmai\":\n            return OpCode.LDMAI\n        elif op_code == \"sdma\":\n            return OpCode.SDMA\n        else:\n            raise ValueError\n\n    @staticmethod\n    def convert_to_string(op_code: OpCode) -> str:\n        if op_code == OpCode.ACQUIRE:\n            return \"acquire\"\n        elif op_code == OpCode.RELEASE:\n            return \"release\"\n        elif op_code == OpCode.ADD:\n            return \"add\"\n        elif op_code == OpCode.ADDC:\n            return \"addc\"\n        elif op_code == OpCode.AND:\n            return \"and\"\n        elif op_code == OpCode.ANDN:\n            return \"andn\"\n        elif op_code == OpCode.ASR:\n            return \"asr\"\n        elif op_code == OpCode.CAO:\n            return \"cao\"\n        elif op_code == OpCode.CLO:\n            return \"clo\"\n        elif op_code == OpCode.CLS:\n            return \"cls\"\n        elif op_code == OpCode.CLZ:\n            return \"clz\"\n        elif op_code == OpCode.CMPB4:\n            return \"cmpb4\"\n        elif op_code == OpCode.DIV_STEP:\n            return \"div_step\"\n        elif op_code == OpCode.EXTSB:\n            return \"extsb\"\n        elif op_code == OpCode.EXTSH:\n            return \"extsh\"\n        elif op_code == OpCode.EXTUB:\n            return \"extub\"\n        elif op_code == OpCode.EXTUH:\n            return \"extuh\"\n        elif op_code == OpCode.LSL:\n            return \"lsl\"\n        elif op_code == OpCode.LSL_ADD:\n            return \"lsl_add\"\n        elif op_code == OpCode.LSL_SUB:\n            return \"lsl_sub\"\n        elif op_code == OpCode.LSL1:\n            return \"lsl1\"\n        elif op_code == OpCode.LSL1X:\n            return \"lsl1x\"\n        elif op_code == OpCode.LSLX:\n            return \"lslx\"\n        elif op_code == OpCode.LSR:\n            return \"lsr\"\n        elif op_code == OpCode.LSR_ADD:\n            return \"lsr_add\"\n        elif op_code == OpCode.LSR1:\n            return \"lsr1\"\n        elif op_code == OpCode.LSR1X:\n            return \"lsr1x\"\n        elif op_code == OpCode.LSRX:\n            return \"lsrx\"\n        elif op_code == OpCode.MUL_SH_SH:\n            return \"mul_sh_sh\"\n        elif op_code == OpCode.MUL_SH_SL:\n            return \"mul_sh_sl\"\n        elif op_code == OpCode.MUL_SH_UH:\n            return \"mul_sh_uh\"\n        elif op_code == OpCode.MUL_SH_UL:\n            return \"mul_sh_ul\"\n        elif op_code == OpCode.MUL_SL_SH:\n            return \"mul_sl_sh\"\n        elif op_code == OpCode.MUL_SL_SL:\n            return \"mul_sl_sl\"\n        elif op_code == OpCode.MUL_SL_UH:\n            return \"mul_sl_uh\"\n        elif op_code == OpCode.MUL_SL_UL:\n            return \"mul_sl_ul\"\n        elif op_code == OpCode.MUL_STEP:\n            return \"mul_step\"\n        elif op_code == OpCode.MUL_UH_UH:\n            return \"mul_uh_uh\"\n        elif op_code == OpCode.MUL_UH_UL:\n            return \"mul_uh_ul\"\n        elif op_code == OpCode.MUL_UL_UH:\n            return \"mul_ul_uh\"\n        elif op_code == OpCode.MUL_UL_UL:\n            return \"mul_ul_ul\"\n        elif op_code == OpCode.NAND:\n            return \"nand\"\n        elif op_code == OpCode.NOR:\n            return \"nor\"\n        elif op_code == OpCode.NXOR:\n            return \"nxor\"\n        elif op_code == OpCode.OR:\n            return \"or\"\n        elif op_code == OpCode.ORN:\n            return \"orn\"\n        elif op_code == OpCode.ROL:\n            return \"rol\"\n        elif op_code == OpCode.ROL_ADD:\n            return \"rol_add\"\n        elif op_code == OpCode.ROR:\n            return \"ror\"\n        elif op_code == OpCode.RSUB:\n            return \"rsub\"\n        elif op_code == OpCode.RSUBC:\n            return \"rsubc\"\n        elif op_code == OpCode.SUB:\n            return \"sub\"\n        elif op_code == OpCode.SUBC:\n            return \"subc\"\n        elif op_code == OpCode.XOR:\n            return \"xor\"\n        elif op_code == OpCode.BOOT:\n            return \"boot\"\n        elif op_code == OpCode.RESUME:\n            return \"resume\"\n        elif op_code == OpCode.STOP:\n            return \"stop\"\n        elif op_code == OpCode.CALL:\n            return \"call\"\n        elif op_code == OpCode.FAULT:\n            return \"fault\"\n        elif op_code == OpCode.NOP:\n            return \"nop\"\n        elif op_code == OpCode.SATS:\n            return \"sats\"\n        elif op_code == OpCode.MOVD:\n            return \"movd\"\n        elif op_code == OpCode.SWAPD:\n            return \"swapd\"\n        elif op_code == OpCode.HASH:\n            return \"hash\"\n        elif op_code == OpCode.TIME:\n            return \"time\"\n        elif op_code == OpCode.TIME_CFG:\n            return \"time_cfg\"\n        elif op_code == OpCode.LBS:\n            return \"lbs\"\n        elif op_code == OpCode.LBU:\n            return \"lbu\"\n        elif op_code == OpCode.LD:\n            return \"ld\"\n        elif op_code == OpCode.LHS:\n            return \"lhs\"\n        elif op_code == OpCode.LHU:\n            return \"lhu\"\n        elif op_code == OpCode.LW:\n            return \"lw\"\n        elif op_code == OpCode.SB:\n            return \"sb\"\n        elif op_code == OpCode.SB_ID:\n            return \"sb_id\"\n        elif op_code == OpCode.SD:\n            return \"sd\"\n        elif op_code == OpCode.SD_ID:\n            return \"sd_id\"\n        elif op_code == OpCode.SH:\n            return \"sh\"\n        elif op_code == OpCode.SH_ID:\n            return \"sh_id\"\n        elif op_code == OpCode.SW:\n            return \"sw\"\n        elif op_code == OpCode.SW_ID:\n            return \"sw_id\"\n        elif op_code == OpCode.LDMA:\n            return \"ldma\"\n        elif op_code == OpCode.LDMAI:\n            return \"ldmai\"\n        elif op_code == OpCode.SDMA:\n            return \"sdma\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/register_converter.py",
    "content": "from typing import Union\n\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.isa.register.pair_register import PairRegister\nfrom abi.isa.register.sp_register import SPRegister\n\n\nclass RegisterConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_gp_register(gp_register: str) -> GPRegister:\n        assert gp_register[0] == \"r\"\n        index = int(gp_register[1:])\n        return GPRegister(index)\n\n    @staticmethod\n    def convert_to_sp_register(sp_register: str) -> SPRegister:\n        if sp_register == \"zero\":\n            return SPRegister.ZERO\n        elif sp_register == \"one\":\n            return SPRegister.ONE\n        elif sp_register == \"lneg\":\n            return SPRegister.LNEG\n        elif sp_register == \"mneg\":\n            return SPRegister.MNEG\n        elif sp_register == \"id\":\n            return SPRegister.ID\n        elif sp_register == \"id2\":\n            return SPRegister.ID2\n        elif sp_register == \"id4\":\n            return SPRegister.ID4\n        elif sp_register == \"id8\":\n            return SPRegister.ID8\n        else:\n            raise ValueError\n\n    @staticmethod\n    def convert_to_pair_register(pair_register: str) -> PairRegister:\n        assert pair_register[0] == \"d\"\n        index = int(pair_register[1:])\n        return PairRegister(index)\n\n    @staticmethod\n    def convert_to_zero_register(zero_register: str) -> SPRegister:\n        assert zero_register == \"zero\"\n        return SPRegister.ZERO\n\n    @staticmethod\n    def convert_to_source_register(source_register: str,) -> Union[GPRegister, SPRegister]:\n        if source_register[0] == \"r\":\n            return RegisterConverter.convert_to_gp_register(source_register)\n        else:\n            return RegisterConverter.convert_to_sp_register(source_register)\n\n    @staticmethod\n    def convert_to_string(register: Union[GPRegister, SPRegister, PairRegister]) -> str:\n        if isinstance(register, GPRegister):\n            return f\"r{register.index()}\"\n        elif isinstance(register, PairRegister):\n            return f\"d{register.index()}\"\n        elif register == SPRegister.ZERO:\n            return \"zero\"\n        elif register == SPRegister.ONE:\n            return \"one\"\n        elif register == SPRegister.LNEG:\n            return \"lneg\"\n        elif register == SPRegister.MNEG:\n            return \"mneg\"\n        elif register == SPRegister.ID:\n            return \"id\"\n        elif register == SPRegister.ID2:\n            return \"id2\"\n        elif register == SPRegister.ID4:\n            return \"id4\"\n        elif register == SPRegister.ID8:\n            return \"id8\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/section_flag_converter.py",
    "content": "from typing import Set\n\nfrom abi.section.section_flag import SectionFlag\n\n\nclass SectionFlagConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_section_flags(section_flags: str) -> Set[SectionFlag]:\n        def convert(section_flag: str) -> SectionFlag:\n            if section_flag == \"a\":\n                return SectionFlag.ALLOC\n            elif section_flag == \"w\":\n                return SectionFlag.WRITE\n            elif section_flag == \"x\":\n                return SectionFlag.EXECINSTR\n            elif section_flag == \"o\":\n                return SectionFlag.LINK_ORDER\n            elif section_flag == \"M\":\n                return SectionFlag.MERGE\n            elif section_flag == \"S\":\n                return SectionFlag.STRINGS\n            else:\n                raise ValueError\n\n        return {convert(section_flag) for section_flag in section_flags}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/section_name_converter.py",
    "content": "from abi.section.section_name import SectionName\n\n\nclass SectionNameConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_section_name(section_name: str) -> SectionName:\n        if section_name == \"atomic\":\n            return SectionName.ATOMIC\n        elif section_name == \"bss\":\n            return SectionName.BSS\n        elif section_name == \"data\":\n            return SectionName.DATA\n        elif section_name == \"debug_abbrev\":\n            return SectionName.DEBUG_ABBREV\n        elif section_name == \"debug_frame\":\n            return SectionName.DEBUG_FRAME\n        elif section_name == \"debug_info\":\n            return SectionName.DEBUG_INFO\n        elif section_name == \"debug_line\":\n            return SectionName.DEBUG_LINE\n        elif section_name == \"debug_loc\":\n            return SectionName.DEBUG_LOC\n        elif section_name == \"debug_ranges\":\n            return SectionName.DEBUG_RANGES\n        elif section_name == \"debug_str\":\n            return SectionName.DEBUG_STR\n        elif section_name == \"dpu_host\":\n            return SectionName.DPU_HOST\n        elif section_name == \"mram\":\n            return SectionName.MRAM\n        elif section_name == \"rodata\":\n            return SectionName.RODATA\n        elif section_name == \"stack_sizes\":\n            return SectionName.STACK_SIZES\n        elif section_name == \"text\":\n            return SectionName.TEXT\n        else:\n            raise ValueError\n\n    @staticmethod\n    def convert_to_str(section_name: SectionName) -> str:\n        if section_name == SectionName.ATOMIC:\n            return \"atomic\"\n        elif section_name == SectionName.BSS:\n            return \"bss\"\n        elif section_name == SectionName.DATA:\n            return \"data\"\n        elif section_name == SectionName.DEBUG_ABBREV:\n            return \"debug_abbrev\"\n        elif section_name == SectionName.DEBUG_FRAME:\n            return \"debug_frame\"\n        elif section_name == SectionName.DEBUG_INFO:\n            return \"debug_info\"\n        elif section_name == SectionName.DEBUG_LINE:\n            return \"debug_line\"\n        elif section_name == SectionName.DEBUG_LOC:\n            return \"debug_loc\"\n        elif section_name == SectionName.DEBUG_RANGES:\n            return \"debug_ranges\"\n        elif section_name == SectionName.DEBUG_STR:\n            return \"debug_ranges\"\n        elif section_name == SectionName.DPU_HOST:\n            return \"dpu_host\"\n        elif section_name == SectionName.MRAM:\n            return \"mram\"\n        elif section_name == SectionName.RODATA:\n            return \"rodata\"\n        elif section_name == SectionName.STACK_SIZES:\n            return \"stack_sizes\"\n        elif section_name == SectionName.TEXT:\n            return \"text\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/section_type_converter.py",
    "content": "from abi.section.section_type import SectionType\n\n\nclass SectionTypeConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_section_type(section_type: str) -> SectionType:\n        if section_type == \"@progbits\":\n            return SectionType.PROG_BITS\n        elif section_type == \"@nobits\":\n            return SectionType.NO_BITS\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/suffix_converter.py",
    "content": "from abi.isa.instruction.suffix import Suffix\n\n\nclass SuffixConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_string(suffix: Suffix):\n        if suffix == Suffix.RICI:\n            return \"rici\"\n        elif suffix == Suffix.RRI:\n            return \"rri\"\n        elif suffix == Suffix.RRIC:\n            return \"rric\"\n        elif suffix == Suffix.RRICI:\n            return \"rrici\"\n        elif suffix == Suffix.RRIF:\n            return \"rrif\"\n        elif suffix == Suffix.RRR:\n            return \"rrr\"\n        elif suffix == Suffix.RRRC:\n            return \"rrrc\"\n        elif suffix == Suffix.RRRCI:\n            return \"rrrci\"\n        elif suffix == Suffix.ZRI:\n            return \"zri\"\n        elif suffix == Suffix.ZRIC:\n            return \"zric\"\n        elif suffix == Suffix.ZRICI:\n            return \"zrici\"\n        elif suffix == Suffix.ZRIF:\n            return \"zrif\"\n        elif suffix == Suffix.ZRR:\n            return \"zrr\"\n        elif suffix == Suffix.ZRRC:\n            return \"zrrc\"\n        elif suffix == Suffix.ZRRCI:\n            return \"zrrci\"\n        elif suffix == Suffix.S_RRI:\n            return \"s_rri\"\n        elif suffix == Suffix.S_RRIC:\n            return \"s_rric\"\n        elif suffix == Suffix.S_RRICI:\n            return \"s_rrici\"\n        elif suffix == Suffix.S_RRIF:\n            return \"s_rrif\"\n        elif suffix == Suffix.S_RRR:\n            return \"s_rrr\"\n        elif suffix == Suffix.S_RRRC:\n            return \"s_rrrc\"\n        elif suffix == Suffix.S_RRRCI:\n            return \"s_rrrci\"\n        elif suffix == Suffix.U_RRI:\n            return \"u_rri\"\n        elif suffix == Suffix.U_RRIC:\n            return \"u_rric\"\n        elif suffix == Suffix.U_RRICI:\n            return \"u_rrici\"\n        elif suffix == Suffix.U_RRIF:\n            return \"u_rrif\"\n        elif suffix == Suffix.U_RRR:\n            return \"u_rrr\"\n        elif suffix == Suffix.U_RRRC:\n            return \"u_rrrc\"\n        elif suffix == Suffix.U_RRRCI:\n            return \"u_rrrci\"\n        elif suffix == Suffix.RR:\n            return \"rr\"\n        elif suffix == Suffix.RRC:\n            return \"rrc\"\n        elif suffix == Suffix.RRCI:\n            return \"rrci\"\n        elif suffix == Suffix.ZR:\n            return \"zr\"\n        elif suffix == Suffix.ZRC:\n            return \"zrc\"\n        elif suffix == Suffix.ZRCI:\n            return \"zrci\"\n        elif suffix == Suffix.S_RR:\n            return \"s_rr\"\n        elif suffix == Suffix.S_RRC:\n            return \"s_rrc\"\n        elif suffix == Suffix.S_RRCI:\n            return \"s_rrci\"\n        elif suffix == Suffix.U_RR:\n            return \"u_rr\"\n        elif suffix == Suffix.U_RRC:\n            return \"u_rrc\"\n        elif suffix == Suffix.U_RRCI:\n            return \"u_rrci\"\n        elif suffix == Suffix.DRDICI:\n            return \"drdici\"\n        elif suffix == Suffix.RRRI:\n            return \"rrri\"\n        elif suffix == Suffix.RRRICI:\n            return \"rrrici\"\n        elif suffix == Suffix.ZRRI:\n            return \"zrri\"\n        elif suffix == Suffix.ZRRICI:\n            return \"zrrici\"\n        elif suffix == Suffix.S_RRRI:\n            return \"s_rrri\"\n        elif suffix == Suffix.S_RRRICI:\n            return \"s_rrrici\"\n        elif suffix == Suffix.U_RRRI:\n            return \"u_rrri\"\n        elif suffix == Suffix.U_RRRICI:\n            return \"u_rrrici\"\n        elif suffix == Suffix.RIR:\n            return \"rir\"\n        elif suffix == Suffix.RIRC:\n            return \"rirc\"\n        elif suffix == Suffix.RIRCI:\n            return \"rirci\"\n        elif suffix == Suffix.ZIR:\n            return \"zir\"\n        elif suffix == Suffix.ZIRC:\n            return \"zirc\"\n        elif suffix == Suffix.ZIRCI:\n            return \"zirci\"\n        elif suffix == Suffix.S_RIRC:\n            return \"s_rirc\"\n        elif suffix == Suffix.S_RIRCI:\n            return \"s_rirci\"\n        elif suffix == Suffix.U_RIRC:\n            return \"u_rirc\"\n        elif suffix == Suffix.U_RIRCI:\n            return \"u_rirci\"\n        elif suffix == Suffix.R:\n            return \"r\"\n        elif suffix == Suffix.RCI:\n            return \"rci\"\n        elif suffix == Suffix.Z:\n            return \"z\"\n        elif suffix == Suffix.ZCI:\n            return \"zci\"\n        elif suffix == Suffix.S_R:\n            return \"s_r\"\n        elif suffix == Suffix.S_RCI:\n            return \"s_rci\"\n        elif suffix == Suffix.U_R:\n            return \"u_r\"\n        elif suffix == Suffix.U_RCI:\n            return \"u_rci\"\n        elif suffix == Suffix.CI:\n            return \"ci\"\n        elif suffix == Suffix.I:\n            return \"i\"\n        elif suffix == Suffix.DDCI:\n            return \"ddci\"\n        elif suffix == Suffix.ERRI:\n            return \"erri\"\n        elif suffix == Suffix.S_ERRI:\n            return \"s_erri\"\n        elif suffix == Suffix.U_ERRI:\n            return \"u_erri\"\n        elif suffix == Suffix.EDRI:\n            return \"edri\"\n        elif suffix == Suffix.ERII:\n            return \"erii\"\n        elif suffix == Suffix.ERIR:\n            return \"erir\"\n        elif suffix == Suffix.ERID:\n            return \"erid\"\n        elif suffix == Suffix.DMA_RRI:\n            return \"dma_rri\"\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/converter/symbol_converter.py",
    "content": "from abi.label.symbol import Symbol\n\n\nclass SymbolConverter:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def convert_to_symbol(symbol: str) -> Symbol:\n        if symbol == \"@function\":\n            return Symbol.FUNCTION\n        elif symbol == \"@object\":\n            return Symbol.OBJECT\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/encoder/ascii_encoder.py",
    "content": "from typing import Dict\n\nfrom encoder.byte import Byte\n\n\nclass AsciiEncoder:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def encode(character: str) -> Byte:\n        assert len(character) == 1\n\n        if character in AsciiEncoder._ascii_table().keys():\n            return Byte(AsciiEncoder._ascii_table()[character])\n        else:\n            return Byte(AsciiEncoder._ascii_table()[AsciiEncoder.unknown()])\n\n    @staticmethod\n    def decode(byte: Byte) -> str:\n        for k, v in AsciiEncoder._ascii_table().items():\n            if v == byte.value():\n                return k\n        return AsciiEncoder.unknown()\n\n    @staticmethod\n    def unknown() -> str:\n        return \"■\"\n\n    @staticmethod\n    def _ascii_table() -> Dict[str, int]:\n        return {\n            \"\\t\": 9,\n            \" \": 32,\n            \"!\": 33,\n            '\"': 34,\n            \"#\": 35,\n            \"$\": 36,\n            \"%\": 37,\n            \"&\": 38,\n            \"'\": 39,\n            \"(\": 40,\n            \")\": 41,\n            \"*\": 42,\n            \"+\": 43,\n            \",\": 44,\n            \"-\": 45,\n            \".\": 46,\n            \"/\": 47,\n            \"0\": 48,\n            \"1\": 49,\n            \"2\": 50,\n            \"3\": 51,\n            \"4\": 52,\n            \"5\": 53,\n            \"6\": 54,\n            \"7\": 55,\n            \"8\": 56,\n            \"9\": 57,\n            \":\": 58,\n            \";\": 59,\n            \"<\": 60,\n            \"=\": 61,\n            \">\": 62,\n            \"?\": 63,\n            \"@\": 64,\n            \"A\": 65,\n            \"B\": 66,\n            \"C\": 67,\n            \"D\": 68,\n            \"E\": 69,\n            \"F\": 70,\n            \"G\": 71,\n            \"H\": 72,\n            \"I\": 73,\n            \"J\": 74,\n            \"K\": 75,\n            \"L\": 76,\n            \"M\": 77,\n            \"N\": 78,\n            \"O\": 79,\n            \"P\": 80,\n            \"Q\": 81,\n            \"R\": 82,\n            \"S\": 83,\n            \"T\": 84,\n            \"U\": 85,\n            \"V\": 86,\n            \"W\": 87,\n            \"X\": 88,\n            \"Y\": 89,\n            \"Z\": 90,\n            \"[\": 91,\n            \"\\\\\": 92,\n            \"]\": 93,\n            \"^\": 94,\n            \"_\": 95,\n            \"`\": 96,\n            \"a\": 97,\n            \"b\": 98,\n            \"c\": 99,\n            \"d\": 100,\n            \"e\": 101,\n            \"f\": 102,\n            \"g\": 103,\n            \"h\": 104,\n            \"i\": 105,\n            \"j\": 106,\n            \"k\": 107,\n            \"l\": 108,\n            \"m\": 109,\n            \"n\": 110,\n            \"o\": 111,\n            \"p\": 112,\n            \"q\": 113,\n            \"r\": 114,\n            \"s\": 115,\n            \"t\": 116,\n            \"u\": 117,\n            \"v\": 118,\n            \"w\": 119,\n            \"x\": 120,\n            \"y\": 121,\n            \"z\": 122,\n            \"{\": 123,\n            \"|\": 124,\n            \"}\": 125,\n            \"~\": 126,\n            \"Ç\": 128,\n            \"ü\": 129,\n            \"é\": 130,\n            \"â\": 131,\n            \"ä\": 132,\n            \"à\": 133,\n            \"å\": 134,\n            \"ç\": 135,\n            \"ê\": 136,\n            \"ë\": 137,\n            \"è\": 138,\n            \"ï\": 139,\n            \"î\": 140,\n            \"ì\": 141,\n            \"Ä\": 142,\n            \"Å\": 143,\n            \"É\": 144,\n            \"æ\": 145,\n            \"Æ\": 146,\n            \"ô\": 147,\n            \"ö\": 148,\n            \"ò\": 149,\n            \"û\": 150,\n            \"ù\": 151,\n            \"ÿ\": 152,\n            \"Ö\": 153,\n            \"Ü\": 154,\n            \"ø\": 155,\n            \"£\": 156,\n            \"Ø\": 157,\n            \"×\": 158,\n            \"ƒ\": 159,\n            \"á\": 160,\n            \"í\": 161,\n            \"ó\": 162,\n            \"ú\": 163,\n            \"ñ\": 164,\n            \"Ñ\": 165,\n            \"ª\": 166,\n            \"º\": 167,\n            \"¿\": 168,\n            \"®\": 169,\n            \"¬\": 170,\n            \"½\": 171,\n            \"¼\": 172,\n            \"¡\": 173,\n            \"«\": 174,\n            \"»\": 175,\n            \"░\": 176,\n            \"▒\": 177,\n            \"▓\": 178,\n            \"│\": 179,\n            \"┤\": 180,\n            \"Á\": 181,\n            \"Â\": 182,\n            \"À\": 183,\n            \"©\": 184,\n            \"╣\": 185,\n            \"║\": 186,\n            \"╗\": 187,\n            \"╝\": 188,\n            \"¢\": 189,\n            \"¥\": 190,\n            \"┐\": 191,\n            \"└\": 192,\n            \"┴\": 193,\n            \"┬\": 194,\n            \"├\": 195,\n            \"─\": 196,\n            \"┼\": 197,\n            \"ã\": 198,\n            \"Ã\": 199,\n            \"╚\": 200,\n            \"╔\": 201,\n            \"╩\": 202,\n            \"╦\": 203,\n            \"╠\": 204,\n            \"═\": 205,\n            \"╬\": 206,\n            \"¤\": 207,\n            \"ð\": 208,\n            \"Ð\": 209,\n            \"Ê\": 210,\n            \"Ë\": 211,\n            \"È\": 212,\n            \"ı\": 213,\n            \"Í\": 214,\n            \"Î\": 215,\n            \"Ï\": 216,\n            \"┘\": 217,\n            \"┌\": 218,\n            \"█\": 219,\n            \"▄\": 220,\n            \"¦\": 221,\n            \"Ì\": 222,\n            \"▀\": 223,\n            \"Ó\": 224,\n            \"ß\": 225,\n            \"Ô\": 226,\n            \"Ò\": 227,\n            \"õ\": 228,\n            \"Õ\": 229,\n            \"µ\": 230,\n            \"þ\": 231,\n            \"Þ\": 232,\n            \"Ú\": 233,\n            \"Û\": 234,\n            \"Ù\": 235,\n            \"ý\": 236,\n            \"Ý\": 237,\n            \"¯\": 238,\n            \"´\": 239,\n            \"≡\": 240,\n            \"±\": 241,\n            \"‗\": 242,\n            \"¾\": 243,\n            \"¶\": 244,\n            \"§\": 245,\n            \"÷\": 246,\n            \"¸\": 247,\n            \"°\": 248,\n            \"¨\": 249,\n            \"·\": 250,\n            \"¹\": 251,\n            \"³\": 252,\n            \"²\": 253,\n            \"■\": 254,\n        }\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/encoder/byte.py",
    "content": "class Byte:\n    def __init__(self, value: int):\n        assert 0 <= value < 2 ** 8\n\n        self._value: int = value\n\n    def value(self):\n        return self._value\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/encoder/directive_encoder.py",
    "content": "from typing import List, Union\n\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom encoder.ascii_encoder import AsciiEncoder\nfrom encoder.byte import Byte\n\n\nclass DirectiveEncoder:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def encode(\n        directive: Union[\n            AsciiDirective, AscizDirective, ByteDirective, LongDirective, QuadDirective, ShortDirective, ZeroDirective,\n        ]\n    ) -> List[Byte]:\n        if isinstance(directive, AsciiDirective):\n            return DirectiveEncoder._encode_ascii(directive)\n        elif isinstance(directive, AscizDirective):\n            return DirectiveEncoder._encode_asciz(directive)\n        elif isinstance(directive, (ByteDirective, LongDirective, QuadDirective, ShortDirective)):\n            return DirectiveEncoder._encode_byte(directive)\n        elif isinstance(directive, ZeroDirective):\n            return DirectiveEncoder._encode_zero(directive)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def decode(\n        bytes_: List[Byte],\n    ) -> Union[\n        AsciiDirective, AscizDirective, ByteDirective, LongDirective, QuadDirective, ShortDirective, ZeroDirective,\n    ]:\n        raise AttributeError\n\n    @staticmethod\n    def _encode_ascii(directive: AsciiDirective):\n        return [AsciiEncoder.encode(character) for character in directive.characters()]\n\n    @staticmethod\n    def _encode_asciz(directive: AscizDirective):\n        bytes_ = [AsciiEncoder.encode(character) for character in directive.characters()]\n        bytes_.append(AsciiEncoder.encode(AsciiEncoder.unknown()))\n        return bytes_\n\n    @staticmethod\n    def _encode_byte(\n        directive: Union[ByteDirective, LongDirective, QuadDirective, ShortDirective, ZeroDirective,]\n    ):\n        return Immediate(Representation.UNSIGNED, 8 * directive.size(), directive.value()).to_bytes()\n\n    @staticmethod\n    def _encode_zero(directive: ZeroDirective):\n        assert isinstance(directive, ZeroDirective)\n\n        byte = Immediate(Representation.UNSIGNED, 8, directive.value()).to_bytes()[0]\n        return [byte for _ in range(directive.size())]\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/encoder/instruction_encoder.py",
    "content": "import math\nfrom typing import List, Tuple, Union\n\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.endian import Endian\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.isa.register.pair_register import PairRegister\nfrom abi.isa.register.sp_register import SPRegister\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\nfrom util.config_loader import ConfigLoader\n\n\nclass InstructionEncoder:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def encode(instruction: Instruction) -> List[Byte]:\n        instruction_word = InstructionWord()\n        InstructionEncoder._encode_opcode(instruction, instruction_word)\n        InstructionEncoder._encode_suffix(instruction, instruction_word)\n\n        suffix = instruction.suffix()\n        if suffix == Suffix.RICI:\n            InstructionEncoder._encode_rici(instruction, instruction_word)\n        elif suffix == Suffix.RRI:\n            InstructionEncoder._encode_rri(instruction, instruction_word)\n        elif suffix == Suffix.RRIC:\n            InstructionEncoder._encode_rric(instruction, instruction_word)\n        elif suffix == Suffix.RRICI:\n            InstructionEncoder._encode_rrici(instruction, instruction_word)\n        elif suffix == Suffix.RRIF:\n            InstructionEncoder._encode_rrif(instruction, instruction_word)\n        elif suffix == Suffix.RRR:\n            InstructionEncoder._encode_rrr(instruction, instruction_word)\n        elif suffix == Suffix.RRRC:\n            InstructionEncoder._encode_rrrc(instruction, instruction_word)\n        elif suffix == Suffix.RRRCI:\n            InstructionEncoder._encode_rrrci(instruction, instruction_word)\n        elif suffix == Suffix.ZRI:\n            InstructionEncoder._encode_zri(instruction, instruction_word)\n        elif suffix == Suffix.ZRIC:\n            InstructionEncoder._encode_zric(instruction, instruction_word)\n        elif suffix == Suffix.ZRICI:\n            InstructionEncoder._encode_zrici(instruction, instruction_word)\n        elif suffix == Suffix.ZRIF:\n            InstructionEncoder._encode_zrif(instruction, instruction_word)\n        elif suffix == Suffix.ZRR:\n            InstructionEncoder._encode_zrr(instruction, instruction_word)\n        elif suffix == Suffix.ZRRC:\n            InstructionEncoder._encode_zrrc(instruction, instruction_word)\n        elif suffix == Suffix.ZRRCI:\n            InstructionEncoder._encode_zrrci(instruction, instruction_word)\n        elif suffix == Suffix.S_RRI or suffix == Suffix.U_RRI:\n            InstructionEncoder._encode_s_rri(instruction, instruction_word)\n        elif suffix == Suffix.S_RRIC or suffix == Suffix.U_RRIC:\n            InstructionEncoder._encode_s_rric(instruction, instruction_word)\n        elif suffix == Suffix.S_RRICI or suffix == Suffix.U_RRICI:\n            InstructionEncoder._encode_s_rrici(instruction, instruction_word)\n        elif suffix == Suffix.S_RRIF or suffix == Suffix.U_RRIF:\n            InstructionEncoder._encode_s_rrif(instruction, instruction_word)\n        elif suffix == Suffix.S_RRR or suffix == Suffix.U_RRR:\n            InstructionEncoder._encode_s_rrr(instruction, instruction_word)\n        elif suffix == Suffix.S_RRRC or suffix == Suffix.U_RRRC:\n            InstructionEncoder._encode_s_rrrc(instruction, instruction_word)\n        elif suffix == Suffix.S_RRRCI or suffix == Suffix.U_RRRCI:\n            InstructionEncoder._encode_s_rrrci(instruction, instruction_word)\n        elif suffix == Suffix.RR:\n            InstructionEncoder._encode_rr(instruction, instruction_word)\n        elif suffix == Suffix.RRC:\n            InstructionEncoder._encode_rrc(instruction, instruction_word)\n        elif suffix == Suffix.RRCI:\n            InstructionEncoder._encode_rrci(instruction, instruction_word)\n        elif suffix == Suffix.ZR:\n            InstructionEncoder._encode_zr(instruction, instruction_word)\n        elif suffix == Suffix.ZRC:\n            InstructionEncoder._encode_zrc(instruction, instruction_word)\n        elif suffix == Suffix.ZRCI:\n            InstructionEncoder._encode_zrci(instruction, instruction_word)\n        elif suffix == Suffix.S_RR or suffix == Suffix.U_RR:\n            InstructionEncoder._encode_s_rr(instruction, instruction_word)\n        elif suffix == Suffix.S_RRC or suffix == Suffix.U_RRC:\n            InstructionEncoder._encode_s_rrc(instruction, instruction_word)\n        elif suffix == Suffix.S_RRCI or suffix == Suffix.U_RRCI:\n            InstructionEncoder._encode_s_rrci(instruction, instruction_word)\n        elif suffix == Suffix.DRDICI:\n            InstructionEncoder._encode_drdici(instruction, instruction_word)\n        elif suffix == Suffix.RRRI:\n            InstructionEncoder._encode_rrri(instruction, instruction_word)\n        elif suffix == Suffix.RRRICI:\n            InstructionEncoder._encode_rrrici(instruction, instruction_word)\n        elif suffix == Suffix.ZRRI:\n            InstructionEncoder._encode_zrri(instruction, instruction_word)\n        elif suffix == Suffix.ZRRICI:\n            InstructionEncoder._encode_zrrici(instruction, instruction_word)\n        elif suffix == Suffix.S_RRRI or suffix == Suffix.U_RRRI:\n            InstructionEncoder._encode_s_rrri(instruction, instruction_word)\n        elif suffix == Suffix.S_RRRICI or suffix == Suffix.U_RRRICI:\n            InstructionEncoder._encode_s_rrrici(instruction, instruction_word)\n        elif suffix == Suffix.RIR:\n            InstructionEncoder._encode_rir(instruction, instruction_word)\n        elif suffix == Suffix.RIRC:\n            InstructionEncoder._encode_rirc(instruction, instruction_word)\n        elif suffix == Suffix.RIRCI:\n            InstructionEncoder._encode_rirci(instruction, instruction_word)\n        elif suffix == Suffix.ZIR:\n            InstructionEncoder._encode_zir(instruction, instruction_word)\n        elif suffix == Suffix.ZIRC:\n            InstructionEncoder._encode_zirc(instruction, instruction_word)\n        elif suffix == Suffix.ZIRCI:\n            InstructionEncoder._encode_zirci(instruction, instruction_word)\n        elif suffix == Suffix.S_RIRC or suffix == Suffix.U_RIRC:\n            InstructionEncoder._encode_s_rirc(instruction, instruction_word)\n        elif suffix == Suffix.S_RIRCI or suffix == Suffix.U_RIRCI:\n            InstructionEncoder._encode_s_rirci(instruction, instruction_word)\n        elif suffix == Suffix.R:\n            InstructionEncoder._encode_r(instruction, instruction_word)\n        elif suffix == Suffix.RCI:\n            InstructionEncoder._encode_rci(instruction, instruction_word)\n        elif suffix == Suffix.Z:\n            InstructionEncoder._encode_z(instruction, instruction_word)\n        elif suffix == Suffix.ZCI:\n            InstructionEncoder._encode_zci(instruction, instruction_word)\n        elif suffix == Suffix.S_R or suffix == Suffix.U_R:\n            InstructionEncoder._encode_s_r(instruction, instruction_word)\n        elif suffix == Suffix.S_RCI or suffix == Suffix.U_RCI:\n            InstructionEncoder._encode_s_rci(instruction, instruction_word)\n        elif suffix == Suffix.CI:\n            InstructionEncoder._encode_ci(instruction, instruction_word)\n        elif suffix == Suffix.I:\n            InstructionEncoder._encode_i(instruction, instruction_word)\n        elif suffix == Suffix.DDCI:\n            InstructionEncoder._encode_ddci(instruction, instruction_word)\n        elif suffix == Suffix.ERRI:\n            InstructionEncoder._encode_erri(instruction, instruction_word)\n        elif suffix == Suffix.S_ERRI or suffix == Suffix.U_ERRI:\n            InstructionEncoder._encode_s_erri(instruction, instruction_word)\n        elif suffix == Suffix.EDRI:\n            InstructionEncoder._encode_edri(instruction, instruction_word)\n        elif suffix == Suffix.ERII:\n            InstructionEncoder._encode_erii(instruction, instruction_word)\n        elif suffix == Suffix.ERIR:\n            InstructionEncoder._encode_erir(instruction, instruction_word)\n        elif suffix == Suffix.ERID:\n            InstructionEncoder._encode_erid(instruction, instruction_word)\n        elif suffix == Suffix.DMA_RRI:\n            InstructionEncoder._encode_dma_rri(instruction, instruction_word)\n        else:\n            raise ValueError\n\n        return instruction_word.to_bytes()\n\n    @staticmethod\n    def decode(bytes_: List[Byte]) -> Instruction:\n        instruction_word = InstructionWord()\n        instruction_word.from_bytes(bytes_)\n\n        op_code = InstructionEncoder._decode_op_code(instruction_word)\n        suffix = InstructionEncoder._decode_suffix(instruction_word)\n\n        if suffix == Suffix.RICI:\n            return InstructionEncoder._decode_rici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRI:\n            return InstructionEncoder._decode_rri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRIC:\n            return InstructionEncoder._decode_rric(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRICI:\n            return InstructionEncoder._decode_rrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRIF:\n            return InstructionEncoder._decode_rrif(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRR:\n            return InstructionEncoder._decode_rrr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRRC:\n            return InstructionEncoder._decode_rrrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRRCI:\n            return InstructionEncoder._decode_rrrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRI:\n            return InstructionEncoder._decode_zri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRIC:\n            return InstructionEncoder._decode_zric(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRICI:\n            return InstructionEncoder._decode_zrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRIF:\n            return InstructionEncoder._decode_zrif(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRR:\n            return InstructionEncoder._decode_zrr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRRC:\n            return InstructionEncoder._decode_zrrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRRCI:\n            return InstructionEncoder._decode_zrrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRI or suffix == Suffix.U_RRI:\n            return InstructionEncoder._decode_s_rri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRIC or suffix == Suffix.U_RRIC:\n            return InstructionEncoder._decode_s_rric(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRICI or suffix == Suffix.U_RRICI:\n            return InstructionEncoder._decode_s_rrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRIF or suffix == Suffix.U_RRIF:\n            return InstructionEncoder._decode_s_rrif(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRR or suffix == Suffix.U_RRR:\n            return InstructionEncoder._decode_s_rrr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRRC or suffix == Suffix.U_RRRC:\n            return InstructionEncoder._decode_s_rrrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRRCI or suffix == Suffix.U_RRRCI:\n            return InstructionEncoder._decode_s_rrrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RR:\n            return InstructionEncoder._decode_rr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRC:\n            return InstructionEncoder._decode_rrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRCI:\n            return InstructionEncoder._decode_rrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZR:\n            return InstructionEncoder._decode_zr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRC:\n            return InstructionEncoder._decode_zrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRCI:\n            return InstructionEncoder._decode_zrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RR or suffix == Suffix.U_RR:\n            return InstructionEncoder._decode_s_rr(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRC or suffix == Suffix.U_RRC:\n            return InstructionEncoder._decode_s_rrc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRCI or suffix == Suffix.U_RRCI:\n            return InstructionEncoder._decode_s_rrci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.DRDICI:\n            return InstructionEncoder._decode_drdici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRRI:\n            return InstructionEncoder._decode_rrri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RRRICI:\n            return InstructionEncoder._decode_rrrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRRI:\n            return InstructionEncoder._decode_zrri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZRRICI:\n            return InstructionEncoder._decode_zrrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRRI or suffix == Suffix.U_RRRI:\n            return InstructionEncoder._decode_s_rrri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RRRICI or suffix == Suffix.U_RRRICI:\n            return InstructionEncoder._decode_s_rrrici(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RIR:\n            return InstructionEncoder._decode_rir(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RIRC:\n            return InstructionEncoder._decode_rirc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RIRCI:\n            return InstructionEncoder._decode_rirci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZIR:\n            return InstructionEncoder._decode_zir(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZIRC:\n            return InstructionEncoder._decode_zirc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZIRCI:\n            return InstructionEncoder._decode_zirci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RIRC or suffix == Suffix.U_RIRC:\n            return InstructionEncoder._decode_s_rirc(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RIRCI or suffix == Suffix.U_RIRCI:\n            return InstructionEncoder._decode_s_rirci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.R:\n            return InstructionEncoder._decode_r(op_code, suffix, instruction_word)\n        elif suffix == Suffix.RCI:\n            return InstructionEncoder._decode_rci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.Z:\n            return InstructionEncoder._decode_z(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ZCI:\n            return InstructionEncoder._decode_zci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_R or suffix == Suffix.U_R:\n            return InstructionEncoder._decode_s_r(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_RCI or suffix == Suffix.U_RCI:\n            return InstructionEncoder._decode_s_rci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.CI:\n            return InstructionEncoder._decode_ci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.I:\n            return InstructionEncoder._decode_i(op_code, suffix, instruction_word)\n        elif suffix == Suffix.DDCI:\n            return InstructionEncoder._decode_ddci(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ERRI:\n            return InstructionEncoder._decode_erri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.S_ERRI or suffix == Suffix.U_ERRI:\n            return InstructionEncoder._decode_s_erri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.EDRI:\n            return InstructionEncoder._decode_edri(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ERII:\n            return InstructionEncoder._decode_erii(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ERIR:\n            return InstructionEncoder._decode_erir(op_code, suffix, instruction_word)\n        elif suffix == Suffix.ERID:\n            return InstructionEncoder._decode_erid(op_code, suffix, instruction_word)\n        elif suffix == Suffix.DMA_RRI:\n            return InstructionEncoder._decode_dma_rri(op_code, suffix, instruction_word)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _op_code_slice() -> Tuple[int, int]:\n        return 0, math.ceil(math.log2(len(OpCode)))\n\n    @staticmethod\n    def _suffix_slice() -> Tuple[int, int]:\n        _, begin = InstructionEncoder._op_code_slice()\n        end = begin + math.ceil(math.log2(len(Suffix)))\n        return begin, end\n\n    @staticmethod\n    def _register_width() -> int:\n        return math.ceil(math.log2(ConfigLoader.num_gp_registers() + len(SPRegister)))\n\n    @staticmethod\n    def _condition_width() -> int:\n        return math.ceil(math.log2(len(Condition)))\n\n    @staticmethod\n    def _pc_width() -> int:\n        return ConfigLoader.iram_address_width()\n\n    @staticmethod\n    def _endian_width() -> int:\n        return math.ceil(math.log2(len(Endian)))\n\n    @staticmethod\n    def _encode_opcode(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        instruction_word.set_bit_slice(*InstructionEncoder._op_code_slice(), instruction.op_code().value)\n\n    @staticmethod\n    def _decode_op_code(instruction_word: InstructionWord) -> OpCode:\n        begin, end = InstructionEncoder._op_code_slice()\n        return OpCode(instruction_word.bit_slice(Representation.UNSIGNED, begin, end))\n\n    @staticmethod\n    def _encode_suffix(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        instruction_word.set_bit_slice(*InstructionEncoder._suffix_slice(), instruction.suffix().value)\n\n    @staticmethod\n    def _decode_suffix(instruction_word: InstructionWord) -> Suffix:\n        begin, end = InstructionEncoder._suffix_slice()\n        return Suffix(instruction_word.bit_slice(Representation.UNSIGNED, begin, end))\n\n    @staticmethod\n    def _encode_register(\n        instruction_word: InstructionWord, begin: int, end: int, register: Union[GPRegister, SPRegister, PairRegister],\n    ) -> None:\n        if isinstance(register, (GPRegister, PairRegister)):\n            instruction_word.set_bit_slice(begin, end, register.index())\n        elif isinstance(register, SPRegister):\n            instruction_word.set_bit_slice(begin, end, ConfigLoader.num_gp_registers() + register.value)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _decode_gp_register(instruction_word: InstructionWord, begin: int, end: int) -> GPRegister:\n        gp_register = instruction_word.bit_slice(Representation.UNSIGNED, begin, end)\n        if gp_register < ConfigLoader.num_gp_registers():\n            return GPRegister(gp_register)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _decode_source_register(instruction_word: InstructionWord, begin: int, end: int,) -> Instruction.SourceRegister:\n        source_register = instruction_word.bit_slice(Representation.UNSIGNED, begin, end)\n        if source_register < ConfigLoader.num_gp_registers():\n            return GPRegister(source_register)\n        elif source_register < ConfigLoader.num_gp_registers() + len(SPRegister):\n            return SPRegister(source_register - ConfigLoader.num_gp_registers())\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _decode_pair_register(instruction_word: InstructionWord, begin: int, end: int) -> PairRegister:\n        pair_register = instruction_word.bit_slice(Representation.UNSIGNED, begin, end)\n        if pair_register < ConfigLoader.num_gp_registers():\n            return PairRegister(pair_register)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _encode_imm(instruction_word: InstructionWord, begin: int, end: int, value: int) -> None:\n        instruction_word.set_bit_slice(begin, end, value)\n\n    @staticmethod\n    def _decode_imm(instruction_word: InstructionWord, begin: int, end: int, representation: Representation,) -> int:\n        return instruction_word.bit_slice(representation, begin, end)\n\n    @staticmethod\n    def _encode_off(instruction_word: InstructionWord, begin: int, end: int, value: int) -> None:\n        InstructionEncoder._encode_imm(instruction_word, begin, end, value)\n\n    @staticmethod\n    def _decode_off(instruction_word: InstructionWord, begin: int, end: int, representation: Representation,) -> int:\n        return InstructionEncoder._decode_imm(instruction_word, begin, end, representation)\n\n    @staticmethod\n    def _encode_condition(instruction_word: InstructionWord, begin: int, end: int, condition: Condition) -> None:\n        instruction_word.set_bit_slice(begin, end, condition.value)\n\n    @staticmethod\n    def _decode_condition(instruction_word: InstructionWord, begin: int, end: int) -> Condition:\n        return Condition(instruction_word.bit_slice(Representation.UNSIGNED, begin, end))\n\n    @staticmethod\n    def _encode_pc(instruction_word: InstructionWord, begin: int, end: int, pc: int):\n        InstructionEncoder._encode_imm(instruction_word, begin, end, pc)\n\n    @staticmethod\n    def _decode_pc(instruction_word: InstructionWord, begin: int, end: int) -> int:\n        return InstructionEncoder._decode_imm(instruction_word, begin, end, Representation.UNSIGNED)\n\n    @staticmethod\n    def _encode_endian(instruction_word: InstructionWord, begin: int, end: int, endian: Endian) -> None:\n        instruction_word.set_bit_slice(begin, end, endian.value)\n\n    @staticmethod\n    def _decode_endian(instruction_word: InstructionWord, begin: int, end: int) -> Endian:\n        return Endian(instruction_word.bit_slice(Representation.UNSIGNED, begin, end))\n\n    @staticmethod\n    def _encode_rici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RICIOpCodes\n        assert instruction.suffix() == Suffix.RICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RICIOpCodes\n        assert suffix == Suffix.RICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        imm_begin, imm_end = ra_end, ra_end + 16\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_rri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.RRI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_rri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.RRI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 32\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 24\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n    @staticmethod\n    def _encode_rric(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_rric(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.RRIC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 24\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_rrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.RRICI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm_begin, imm_end = ra_end, ra_end + 8\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_rrif(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.RRIF\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_rrif(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.RRIF\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        imm_begin, imm_end = ra_end, ra_end + 24\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_rrr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.RRR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n    @staticmethod\n    def _decode_rrr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.RRR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb)\n\n    @staticmethod\n    def _encode_rrrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.RRRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_rrrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.RRRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _encode_rrrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rrrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.RRRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_zri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.ZRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_zri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.ZRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 32\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 28\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm)\n\n    @staticmethod\n    def _encode_zric(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.ZRIC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_zric(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.ZRIC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 27\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_zrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.ZRICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm_begin, imm_end = ra_end, ra_end + 11\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_zrif(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.ZRIF\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_zrif(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.ZRIF\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        imm_begin, imm_end = ra_end, ra_end + 27\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_zrr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.ZRR\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n    @staticmethod\n    def _decode_zrr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.ZRR\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb)\n\n    @staticmethod\n    def _encode_zrrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.ZRRC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_zrrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.ZRRC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _encode_zrrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zrrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.ZRRCI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_rri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRI or instruction.suffix() == Suffix.U_RRI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_s_rri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.S_RRI or suffix == Suffix.U_RRI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 32\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 24\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n    @staticmethod\n    def _encode_s_rric(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n        assert instruction.suffix() == Suffix.S_RRIC or instruction.suffix() == Suffix.U_RRIC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_s_rric(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.S_RRIC or suffix == Suffix.U_RRIC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 24\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_s_rrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI or instruction.suffix() == Suffix.U_RRICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.S_RRICI or suffix == Suffix.U_RRICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm_begin, imm_end = ra_end, ra_end + 8\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm_begin, imm_end = ra_end, ra_end + 5\n            imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n        else:\n            raise ValueError\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_rrif(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.S_RRIF or instruction.suffix() == Suffix.U_RRIF\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = ra_end, ra_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_s_rrif(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.S_RRIF or suffix == Suffix.U_RRIF\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        imm_begin, imm_end = ra_end, ra_end + 24\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _encode_s_rrr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.S_RRR or instruction.suffix() == Suffix.U_RRR\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n    @staticmethod\n    def _decode_s_rrr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.S_RRR or suffix == Suffix.U_RRR\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb)\n\n    @staticmethod\n    def _encode_s_rrrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n        assert instruction.suffix() == Suffix.S_RRRC or instruction.suffix() == Suffix.U_RRRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_s_rrrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.S_RRRC or suffix == Suffix.U_RRRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _encode_s_rrrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRCI or instruction.suffix() == Suffix.U_RRRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rrrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.S_RRRCI or suffix == Suffix.U_RRRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        condition_begin, condition_end = (\n            rb_end,\n            rb_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_rr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.RR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n    @staticmethod\n    def _decode_rr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.RR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra)\n\n    @staticmethod\n    def _encode_rrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.RRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_rrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.RRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_rrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.RRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.RRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_zr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.ZR\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n    @staticmethod\n    def _decode_zr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.ZR\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        return Instruction(op_code, suffix, ra=ra)\n\n    @staticmethod\n    def _encode_zrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.ZRC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_zrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.ZRC\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_zrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRCI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.ZRCI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_rr(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.S_RR or instruction.suffix() == Suffix.U_RR\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n    @staticmethod\n    def _decode_s_rr(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.S_RR or suffix == Suffix.U_RR\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra)\n\n    @staticmethod\n    def _encode_s_rrc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.S_RRC or instruction.suffix() == Suffix.U_RRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_s_rrc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.S_RRC or suffix == Suffix.U_RRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_s_rrci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RRCI or instruction.suffix() == Suffix.U_RRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rrci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.S_RRCI or suffix == Suffix.U_RRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_drdici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.DRDICIOpCodes\n        assert instruction.suffix() == Suffix.DRDICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        db_begin, db_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, db_begin, db_end, instruction.db())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = db_end, db_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_drdici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.DRDICIOpCodes\n        assert suffix == Suffix.DRDICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        db_begin, db_end = ra_end, ra_end + InstructionEncoder._register_width()\n        db = InstructionEncoder._decode_pair_register(instruction_word, db_begin, db_end)\n\n        imm_begin, imm_end = db_end, db_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, db=db, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_rrri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.RRRI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_rrri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.RRRI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _encode_rrrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRRICI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rrrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.RRRICI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_zrri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_zrri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.ZRRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _encode_zrrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRRICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zrrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.ZRRICI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_rrri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRI or instruction.suffix() == Suffix.U_RRRI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_s_rrri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.S_RRRI or suffix == Suffix.U_RRRI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _encode_s_rrrici(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRRICI or instruction.suffix() == Suffix.U_RRRICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rrrici(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.S_RRRICI or suffix == Suffix.U_RRRICI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 5\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        condition_begin, condition_end = (\n            imm_end,\n            imm_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_rir(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.RIR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rc_end, rc_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n    @staticmethod\n    def _decode_rir(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIROpCodes\n        assert suffix == Suffix.RIR\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        imm_begin, imm_end = rc_end, rc_end + 32\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra)\n\n    @staticmethod\n    def _encode_rirc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.RIRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rc_end, rc_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_rirc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.RIRC\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        imm_begin, imm_end = rc_end, rc_end + 24\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_rirci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.RIRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rc_end, rc_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rirci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.RIRCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        imm_begin, imm_end = rc_end, rc_end + 8\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_zir(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.ZIR\n\n        imm = instruction.imm()\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n    @staticmethod\n    def _decode_zir(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIROpCodes\n        assert suffix == Suffix.ZIR\n\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + 32\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra)\n\n    @staticmethod\n    def _encode_zirc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.ZIRC\n\n        imm = instruction.imm()\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_zirc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.ZIRC\n\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + 27\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_zirci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.ZIRCI\n\n        imm = instruction.imm()\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zirci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.ZIRCI\n\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + 11\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_rirc(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.S_RIRC or instruction.suffix() == Suffix.U_RIRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = dc_end, dc_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n    @staticmethod\n    def _decode_s_rirc(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.S_RIRC or suffix == Suffix.U_RIRC\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        imm_begin, imm_end = dc_end, dc_end + 24\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        return Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _encode_s_rirci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.S_RIRCI or instruction.suffix() == Suffix.U_RIRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = dc_end, dc_end + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rirci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.S_RIRCI or suffix == Suffix.U_RIRCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        imm_begin, imm_end = dc_end, dc_end + 8\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        ra_begin, ra_end = imm_end, imm_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        condition_begin, condition_end = (\n            ra_end,\n            ra_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_r(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ROpCodes\n        assert instruction.suffix() == Suffix.R\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n    @staticmethod\n    def _decode_r(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ROpCodes\n        assert suffix == Suffix.R\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        return Instruction(op_code, suffix, rc=rc)\n\n    @staticmethod\n    def _encode_rci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.RCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            rc_end,\n            rc_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_rci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.RCI\n\n        _, rc_begin = InstructionEncoder._suffix_slice()\n        rc_end = rc_begin + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        condition_begin, condition_end = (\n            rc_end,\n            rc_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, rc=rc, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_z(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ROpCodes or instruction.op_code() == OpCode.NOP\n        assert instruction.suffix() == Suffix.Z\n\n    @staticmethod\n    def _decode_z(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ROpCodes or op_code == OpCode.NOP\n        assert suffix == Suffix.Z\n\n        return Instruction(op_code, suffix)\n\n    @staticmethod\n    def _encode_zci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.ZCI\n\n        condition = instruction.condition()\n        _, condition_begin = InstructionEncoder._suffix_slice()\n        condition_end = condition_begin + InstructionEncoder._condition_width()\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_zci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.ZCI\n\n        _, condition_begin = InstructionEncoder._suffix_slice()\n        condition_end = condition_begin + InstructionEncoder._condition_width()\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_s_r(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ROpCodes\n        assert instruction.suffix() == Suffix.S_R or instruction.suffix() == Suffix.U_R\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n    @staticmethod\n    def _decode_s_r(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ROpCodes\n        assert suffix == Suffix.S_R or suffix == Suffix.U_R\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        return Instruction(op_code, suffix, dc=dc)\n\n    @staticmethod\n    def _encode_s_rci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.RCIOpCodes\n        assert instruction.suffix() == Suffix.S_RCI or instruction.suffix() == Suffix.U_RCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            dc_end,\n            dc_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_s_rci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.S_RCI or suffix == Suffix.U_RCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        condition_begin, condition_end = (\n            dc_end,\n            dc_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_ci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.CIOpCodes\n        assert instruction.suffix() == Suffix.CI\n\n        condition = instruction.condition()\n        _, condition_begin = InstructionEncoder._suffix_slice()\n        condition_end = condition_begin + InstructionEncoder._condition_width()\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_ci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.CIOpCodes\n        assert suffix == Suffix.CI\n\n        _, condition_begin = InstructionEncoder._suffix_slice()\n        condition_end = condition_begin + InstructionEncoder._condition_width()\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_i(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.IOpCodes\n        assert instruction.suffix() == Suffix.I\n\n        imm = instruction.imm()\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + imm.width()\n        InstructionEncoder._encode_imm(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_i(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.IOpCodes\n        assert suffix == Suffix.I\n\n        _, imm_begin = InstructionEncoder._suffix_slice()\n        imm_end = imm_begin + 24\n        imm = InstructionEncoder._decode_imm(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        return Instruction(op_code, suffix, imm=imm)\n\n    @staticmethod\n    def _encode_ddci(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.DDCIOpCodes\n        assert instruction.suffix() == Suffix.DDCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        db_begin, db_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, db_begin, db_end, instruction.db())\n\n        condition = instruction.condition()\n        condition_begin, condition_end = (\n            db_end,\n            db_end + InstructionEncoder._condition_width(),\n        )\n        InstructionEncoder._encode_condition(instruction_word, condition_begin, condition_end, condition)\n\n        pc = instruction.pc()\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        InstructionEncoder._encode_pc(instruction_word, pc_begin, pc_end, pc.value())\n\n    @staticmethod\n    def _decode_ddci(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.DDCIOpCodes\n        assert suffix == Suffix.DDCI\n\n        _, dc_begin = InstructionEncoder._suffix_slice()\n        dc_end = dc_begin + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        db_begin, db_end = dc_end, dc_end + InstructionEncoder._register_width()\n        db = InstructionEncoder._decode_pair_register(instruction_word, db_begin, db_end)\n\n        condition_begin, condition_end = (\n            db_end,\n            db_end + InstructionEncoder._condition_width(),\n        )\n        condition = InstructionEncoder._decode_condition(instruction_word, condition_begin, condition_end)\n\n        pc_begin, pc_end = condition_end, condition_end + InstructionEncoder._pc_width()\n        pc = InstructionEncoder._decode_pc(instruction_word, pc_begin, pc_end)\n\n        return Instruction(op_code, suffix, dc=dc, db=db, condition=condition, pc=pc)\n\n    @staticmethod\n    def _encode_erri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ERRIOpCodes\n        assert instruction.suffix() == Suffix.ERRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        rc_begin, rc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rc_begin, rc_end, instruction.rc())\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n    @staticmethod\n    def _decode_erri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ERRIOpCodes\n        assert suffix == Suffix.ERRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        rc_begin, rc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        rc = InstructionEncoder._decode_gp_register(instruction_word, rc_begin, rc_end)\n\n        ra_begin, ra_end = rc_end, rc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        return Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n    @staticmethod\n    def _encode_s_erri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ERRIOpCodes\n        assert instruction.suffix() == Suffix.S_ERRI or instruction.suffix() == Suffix.U_ERRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        dc_begin, dc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n    @staticmethod\n    def _decode_s_erri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ERRIOpCodes\n        assert suffix == Suffix.S_ERRI or suffix == Suffix.U_ERRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        dc_begin, dc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        return Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n    @staticmethod\n    def _encode_edri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.EDRIOpCodes\n        assert instruction.suffix() == Suffix.EDRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        dc_begin, dc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, dc_begin, dc_end, instruction.dc())\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n    @staticmethod\n    def _decode_edri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.EDRIOpCodes\n        assert suffix == Suffix.EDRI\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        dc_begin, dc_end = endian_end, endian_end + InstructionEncoder._register_width()\n        dc = InstructionEncoder._decode_pair_register(instruction_word, dc_begin, dc_end)\n\n        ra_begin, ra_end = dc_end, dc_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        return Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n    @staticmethod\n    def _encode_erii(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ERIIOpCodes\n        assert instruction.suffix() == Suffix.ERII\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = off_end, off_end + imm.width()\n        InstructionEncoder._encode_off(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_erii(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ERIIOpCodes\n        assert suffix == Suffix.ERII\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        # NOTE(bongjoon.hyun@gmail.com): original width is 12\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        # NOTE(bongjoon.hyun@gmail.com): original width is 8\n        imm_begin, imm_end = off_end, off_end + 16\n        imm = InstructionEncoder._decode_off(instruction_word, imm_begin, imm_end, Representation.SIGNED)\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n    @staticmethod\n    def _encode_erir(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ERIROpCodes\n        assert instruction.suffix() == Suffix.ERIR\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n        rb_begin, rb_end = off_end, off_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n    @staticmethod\n    def _decode_erir(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ERIROpCodes\n        assert suffix == Suffix.ERIR\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        rb_begin, rb_end = off_end, off_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n    @staticmethod\n    def _encode_erid(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.ERIDOpCodes\n        assert instruction.suffix() == Suffix.ERID\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        InstructionEncoder._encode_endian(instruction_word, endian_begin, endian_end, instruction.endian())\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        off = instruction.off()\n        off_begin, off_end = ra_end, ra_end + off.width()\n        InstructionEncoder._encode_off(instruction_word, off_begin, off_end, off.value())\n\n        db_begin, db_end = off_end, off_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, db_begin, db_end, instruction.db())\n\n    @staticmethod\n    def _decode_erid(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.ERIDOpCodes\n        assert suffix == Suffix.ERID\n\n        _, endian_begin = InstructionEncoder._suffix_slice()\n        endian_end = endian_begin + InstructionEncoder._endian_width()\n        endian = InstructionEncoder._decode_endian(instruction_word, endian_begin, endian_end)\n\n        ra_begin, ra_end = endian_end, endian_end + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        off_begin, off_end = ra_end, ra_end + 24\n        off = InstructionEncoder._decode_off(instruction_word, off_begin, off_end, Representation.SIGNED)\n\n        db_begin, db_end = off_end, off_end + InstructionEncoder._register_width()\n        db = InstructionEncoder._decode_pair_register(instruction_word, db_begin, db_end)\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, db=db)\n\n    @staticmethod\n    def _encode_dma_rri(instruction: Instruction, instruction_word: InstructionWord) -> None:\n        assert instruction.op_code() in Instruction.DMARRIOpCodes\n        assert instruction.suffix() == Suffix.DMA_RRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, ra_begin, ra_end, instruction.ra())\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        InstructionEncoder._encode_register(instruction_word, rb_begin, rb_end, instruction.rb())\n\n        imm = instruction.imm()\n        imm_begin, imm_end = rb_end, rb_end + imm.width()\n        InstructionEncoder._encode_off(instruction_word, imm_begin, imm_end, imm.value())\n\n    @staticmethod\n    def _decode_dma_rri(op_code: OpCode, suffix: Suffix, instruction_word: InstructionWord) -> Instruction:\n        assert op_code in Instruction.DMARRIOpCodes\n        assert suffix == Suffix.DMA_RRI\n\n        _, ra_begin = InstructionEncoder._suffix_slice()\n        ra_end = ra_begin + InstructionEncoder._register_width()\n        ra = InstructionEncoder._decode_source_register(instruction_word, ra_begin, ra_end)\n\n        rb_begin, rb_end = ra_end, ra_end + InstructionEncoder._register_width()\n        rb = InstructionEncoder._decode_source_register(instruction_word, rb_begin, rb_end)\n\n        imm_begin, imm_end = rb_end, rb_end + 8\n        imm = InstructionEncoder._decode_off(instruction_word, imm_begin, imm_end, Representation.UNSIGNED)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/initializer/directive_initializer.py",
    "content": "from abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\nclass DirectiveInitializer:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def ascii_directive():\n        width = IntInitializer.value_by_range(1, 128)\n        characters = StrInitializer.identifier(width)\n        return AsciiDirective(characters)\n\n    @staticmethod\n    def asciz_directive():\n        width = IntInitializer.value_by_range(1, 128)\n        characters = StrInitializer.identifier(width)\n        return AscizDirective(characters)\n\n    @staticmethod\n    def byte_directive():\n        value = IntInitializer.value_by_range(0, 2 ** (8 * ByteDirective.size()))\n        return ByteDirective(value)\n\n    @staticmethod\n    def short_directive():\n        value = IntInitializer.value_by_range(0, 2 ** (8 * ShortDirective.size()))\n        return ShortDirective(value)\n\n    @staticmethod\n    def long_directive():\n        value = IntInitializer.value_by_range(0, 2 ** (8 * LongDirective.size()))\n        return LongDirective(value)\n\n    @staticmethod\n    def quad_directive():\n        value = IntInitializer.value_by_range(0, 2 ** (8 * QuadDirective.size()))\n        return QuadDirective(value)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/initializer/instruction_initializer.py",
    "content": "from typing import Set\n\nfrom abi.isa.cc.acquire_cc import AcquireCC\nfrom abi.isa.cc.add_nz_cc import AddNZCC\nfrom abi.isa.cc.boot_cc import BootCC\nfrom abi.isa.cc.count_nz_cc import CountNZCC\nfrom abi.isa.cc.div_cc import DivCC\nfrom abi.isa.cc.div_nz_cc import DivNZCC\nfrom abi.isa.cc.ext_sub_set_cc import ExtSubSetCC\nfrom abi.isa.cc.false_cc import FalseCC\nfrom abi.isa.cc.imm_shift_nz_cc import ImmShiftNZCC\nfrom abi.isa.cc.log_nz_cc import LogNZCC\nfrom abi.isa.cc.log_set_cc import LogSetCC\nfrom abi.isa.cc.mul_nz_cc import MulNZCC\nfrom abi.isa.cc.release_cc import ReleaseCC\nfrom abi.isa.cc.shift_nz_cc import ShiftNZCC\nfrom abi.isa.cc.sub_nz_cc import SubNZCC\nfrom abi.isa.cc.sub_set_cc import SubSetCC\nfrom abi.isa.cc.true_cc import TrueCC\nfrom abi.isa.cc.true_false_cc import TrueFalseCC\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.endian import Endian\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.isa.register.pair_register import PairRegister\nfrom abi.isa.register.sp_register import SPRegister\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\nclass InstructionInitializer:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def instruction(op_code: OpCode, suffix: Suffix) -> Instruction:\n        if suffix == Suffix.RICI:\n            return InstructionInitializer._rici(op_code, suffix)\n        elif suffix == Suffix.RRI:\n            return InstructionInitializer._rri(op_code, suffix)\n        elif suffix == Suffix.RRIC:\n            return InstructionInitializer._rric(op_code, suffix)\n        elif suffix == Suffix.RRICI:\n            return InstructionInitializer._rrici(op_code, suffix)\n        elif suffix == Suffix.RRIF:\n            return InstructionInitializer._rrif(op_code, suffix)\n        elif suffix == Suffix.RRR:\n            return InstructionInitializer._rrr(op_code, suffix)\n        elif suffix == Suffix.RRRC:\n            return InstructionInitializer._rrrc(op_code, suffix)\n        elif suffix == Suffix.RRRCI:\n            return InstructionInitializer._rrrci(op_code, suffix)\n        elif suffix == Suffix.ZRI:\n            return InstructionInitializer._zri(op_code, suffix)\n        elif suffix == Suffix.ZRIC:\n            return InstructionInitializer._zric(op_code, suffix)\n        elif suffix == Suffix.ZRICI:\n            return InstructionInitializer._zrici(op_code, suffix)\n        elif suffix == Suffix.ZRIF:\n            return InstructionInitializer._zrif(op_code, suffix)\n        elif suffix == Suffix.ZRR:\n            return InstructionInitializer._zrr(op_code, suffix)\n        elif suffix == Suffix.ZRRC:\n            return InstructionInitializer._zrrc(op_code, suffix)\n        elif suffix == Suffix.ZRRCI:\n            return InstructionInitializer._zrrci(op_code, suffix)\n        elif suffix == Suffix.S_RRI or suffix == Suffix.U_RRI:\n            return InstructionInitializer._s_rri(op_code, suffix)\n        elif suffix == Suffix.S_RRIC or suffix == Suffix.U_RRIC:\n            return InstructionInitializer._s_rric(op_code, suffix)\n        elif suffix == Suffix.S_RRICI or suffix == Suffix.U_RRICI:\n            return InstructionInitializer._s_rrici(op_code, suffix)\n        elif suffix == Suffix.S_RRIF or suffix == Suffix.U_RRIF:\n            return InstructionInitializer._s_rrif(op_code, suffix)\n        elif suffix == Suffix.S_RRR or suffix == Suffix.U_RRR:\n            return InstructionInitializer._s_rrr(op_code, suffix)\n        elif suffix == Suffix.S_RRRC or suffix == Suffix.U_RRRC:\n            return InstructionInitializer._s_rrrc(op_code, suffix)\n        elif suffix == Suffix.S_RRRCI or suffix == Suffix.U_RRRCI:\n            return InstructionInitializer._s_rrrci(op_code, suffix)\n        elif suffix == Suffix.RR:\n            return InstructionInitializer._rr(op_code, suffix)\n        elif suffix == Suffix.RRC:\n            return InstructionInitializer._rrc(op_code, suffix)\n        elif suffix == Suffix.RRCI:\n            return InstructionInitializer._rrci(op_code, suffix)\n        elif suffix == Suffix.ZR:\n            return InstructionInitializer._zr(op_code, suffix)\n        elif suffix == Suffix.ZRC:\n            return InstructionInitializer._zrc(op_code, suffix)\n        elif suffix == Suffix.ZRCI:\n            return InstructionInitializer._zrci(op_code, suffix)\n        elif suffix == Suffix.S_RR or suffix == Suffix.U_RR:\n            return InstructionInitializer._s_rr(op_code, suffix)\n        elif suffix == Suffix.S_RRC or suffix == Suffix.U_RRC:\n            return InstructionInitializer._s_rrc(op_code, suffix)\n        elif suffix == Suffix.S_RRCI or suffix == Suffix.U_RRCI:\n            return InstructionInitializer._s_rrci(op_code, suffix)\n        elif suffix == Suffix.DRDICI:\n            return InstructionInitializer._drdici(op_code, suffix)\n        elif suffix == Suffix.RRRI:\n            return InstructionInitializer._rrri(op_code, suffix)\n        elif suffix == Suffix.RRRICI:\n            return InstructionInitializer._rrrici(op_code, suffix)\n        elif suffix == Suffix.ZRRI:\n            return InstructionInitializer._zrri(op_code, suffix)\n        elif suffix == Suffix.ZRRICI:\n            return InstructionInitializer._zrrici(op_code, suffix)\n        elif suffix == Suffix.S_RRRI or suffix == Suffix.U_RRRI:\n            return InstructionInitializer._s_rrri(op_code, suffix)\n        elif suffix == Suffix.S_RRRICI or suffix == Suffix.U_RRRICI:\n            return InstructionInitializer._s_rrrici(op_code, suffix)\n        elif suffix == Suffix.RIR:\n            return InstructionInitializer._rir(op_code, suffix)\n        elif suffix == Suffix.RIRC:\n            return InstructionInitializer._rirc(op_code, suffix)\n        elif suffix == Suffix.RIRCI:\n            return InstructionInitializer._rirci(op_code, suffix)\n        elif suffix == Suffix.ZIR:\n            return InstructionInitializer._zir(op_code, suffix)\n        elif suffix == Suffix.ZIRC:\n            return InstructionInitializer._zirc(op_code, suffix)\n        elif suffix == Suffix.ZIRCI:\n            return InstructionInitializer._zirci(op_code, suffix)\n        elif suffix == Suffix.S_RIRC or suffix == Suffix.U_RIRC:\n            return InstructionInitializer._s_rirc(op_code, suffix)\n        elif suffix == Suffix.S_RIRCI or suffix == Suffix.U_RIRCI:\n            return InstructionInitializer._s_rirci(op_code, suffix)\n        elif suffix == Suffix.R:\n            return InstructionInitializer._r(op_code, suffix)\n        elif suffix == Suffix.RCI:\n            return InstructionInitializer._rci(op_code, suffix)\n        elif suffix == Suffix.Z:\n            return InstructionInitializer._z(op_code, suffix)\n        elif suffix == Suffix.ZCI:\n            return InstructionInitializer._zci(op_code, suffix)\n        elif suffix == Suffix.S_R or suffix == Suffix.U_R:\n            return InstructionInitializer._s_r(op_code, suffix)\n        elif suffix == Suffix.S_RCI or suffix == Suffix.U_RCI:\n            return InstructionInitializer._s_rci(op_code, suffix)\n        elif suffix == Suffix.CI:\n            return InstructionInitializer._ci(op_code, suffix)\n        elif suffix == Suffix.I:\n            return InstructionInitializer._i(op_code, suffix)\n        elif suffix == Suffix.DDCI:\n            return InstructionInitializer._ddci(op_code, suffix)\n        elif suffix == Suffix.ERRI:\n            return InstructionInitializer._erri(op_code, suffix)\n        elif suffix == Suffix.S_ERRI or suffix == Suffix.U_ERRI:\n            return InstructionInitializer._s_erri(op_code, suffix)\n        elif suffix == Suffix.EDRI:\n            return InstructionInitializer._edri(op_code, suffix)\n        elif suffix == Suffix.ERII:\n            return InstructionInitializer._erii(op_code, suffix)\n        elif suffix == Suffix.ERIR:\n            return InstructionInitializer._erir(op_code, suffix)\n        elif suffix == Suffix.ERID:\n            return InstructionInitializer._erid(op_code, suffix)\n        elif suffix == Suffix.DMA_RRI:\n            return InstructionInitializer._dma_rri(op_code, suffix)\n        else:\n            raise ValueError\n\n    @staticmethod\n    def _gp_register() -> Instruction.DestinationRegister:\n        return GPRegister(IntInitializer.value_by_range(0, ConfigLoader.num_gp_registers()))\n\n    @staticmethod\n    def _source_register() -> Instruction.SourceRegister:\n        num_gp_registers = ConfigLoader.num_gp_registers()\n        num_sp_registers = len(SPRegister)\n        num_source_registers = num_gp_registers + num_sp_registers\n\n        register_index = IntInitializer.value_by_range(0, num_source_registers)\n        if register_index < ConfigLoader.num_gp_registers():\n            return GPRegister(register_index)\n        else:\n            return SPRegister(register_index - num_gp_registers)\n\n    @staticmethod\n    def _pair_register() -> PairRegister:\n        register_index = (IntInitializer.value_by_range(0, ConfigLoader.num_gp_registers()) // 2) * 2\n        return PairRegister(register_index)\n\n    @staticmethod\n    def _imm(representation: Representation, width: int) -> int:\n        return IntInitializer.value_by_width(representation, width)\n\n    @staticmethod\n    def _condition(conditions: Set[Condition]) -> Condition:\n        return IntInitializer.value_by_list(list(conditions))\n\n    @staticmethod\n    def _pc() -> int:\n        return InstructionInitializer._imm(Representation.UNSIGNED, ConfigLoader.iram_address_width())\n\n    @staticmethod\n    def _endian() -> Endian:\n        return IntInitializer.value_by_list(list(Endian))\n\n    @staticmethod\n    def _rici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RICIOpCodes\n        assert suffix == Suffix.RICI\n\n        ra = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 16)\n\n        if op_code in Instruction.AcquireRICIOpCodes:\n            condition = InstructionInitializer._condition(AcquireCC.conditions())\n        elif op_code in Instruction.ReleaseRICIOpCodes:\n            condition = InstructionInitializer._condition(ReleaseCC.conditions())\n        elif op_code in Instruction.BootRICIOpCodes:\n            condition = InstructionInitializer._condition(BootCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _rri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.RRI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 32)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n    @staticmethod\n    def _rric(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.RRIC\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.AsrRRICOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.SubRRICOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _rrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICIOpCodes\n        assert suffix == Suffix.RRICI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm = InstructionInitializer._imm(Representation.SIGNED, 8)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRICIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            condition = InstructionInitializer._condition(ImmShiftNZCC.conditions())\n        elif op_code in Instruction.SubRRICIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _rrif(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.RRIF\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        condition = InstructionInitializer._condition(FalseCC.conditions())\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _rrr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.RRR\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb)\n\n    @staticmethod\n    def _rrrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.RRRC\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.RsubRRRCOpCodes:\n            condition = InstructionInitializer._condition(SubSetCC.conditions())\n        elif op_code in Instruction.SubRRRCOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _rrrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.RRRCI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRRCIOpCodes:\n            condition = InstructionInitializer._condition(ShiftNZCC.conditions())\n        elif op_code in Instruction.MulRRRCIOpCodes:\n            condition = InstructionInitializer._condition(MulNZCC.conditions())\n        elif op_code in Instruction.RsubRRRCIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _zri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.ZRI\n\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 32)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 28)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm)\n\n    @staticmethod\n    def _zric(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.ZRIC\n\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 27)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.AsrRRICOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.SubRRICOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _zrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICIOpCodes\n        assert suffix == Suffix.ZRICI\n\n        ra = InstructionInitializer._source_register()\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm = InstructionInitializer._imm(Representation.SIGNED, 11)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRICIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            condition = InstructionInitializer._condition(ImmShiftNZCC.conditions())\n        elif op_code in Instruction.SubRRICIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _zrif(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.ZRIF\n\n        ra = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 27)\n        condition = InstructionInitializer._condition(FalseCC.conditions())\n\n        return Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _zrr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.ZRR\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb)\n\n    @staticmethod\n    def _zrrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.ZRRC\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.RsubRRRCOpCodes:\n            condition = InstructionInitializer._condition(SubSetCC.conditions())\n        elif op_code in Instruction.SubRRRCOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _zrrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.ZRRCI\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRRCIOpCodes:\n            condition = InstructionInitializer._condition(ShiftNZCC.conditions())\n        elif op_code in Instruction.MulRRRCIOpCodes:\n            condition = InstructionInitializer._condition(MulNZCC.conditions())\n        elif op_code in Instruction.RsubRRRCIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_rri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIOpCodes\n        assert suffix == Suffix.S_RRI or suffix == Suffix.U_RRI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 32)\n        elif op_code in Instruction.AsrRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        elif op_code in Instruction.CallRRIOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n    @staticmethod\n    def _s_rric(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICOpCodes\n        assert suffix == Suffix.S_RRIC or suffix == Suffix.U_RRIC\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.SubRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        elif op_code in Instruction.AsrRRICOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICOpCodes or op_code in Instruction.AsrRRICOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.SubRRICOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _s_rrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRICIOpCodes\n        assert suffix == Suffix.S_RRICI or suffix == Suffix.U_RRICI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n\n        if (\n            op_code in Instruction.AddRRICIOpCodes\n            or op_code in Instruction.AndRRICIOpCodes\n            or op_code in Instruction.SubRRICIOpCodes\n        ):\n            imm = InstructionInitializer._imm(Representation.SIGNED, 8)\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        else:\n            raise ValueError\n\n        if op_code in Instruction.AddRRICIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRICIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRICIOpCodes:\n            condition = InstructionInitializer._condition(ImmShiftNZCC.conditions())\n        elif op_code in Instruction.SubRRICIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_rrif(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRIFOpCodes\n        assert suffix == Suffix.S_RRIF or suffix == Suffix.U_RRIF\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        condition = InstructionInitializer._condition(FalseCC.conditions())\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n    @staticmethod\n    def _s_rrr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRROpCodes\n        assert suffix == Suffix.S_RRR or suffix == Suffix.U_RRR\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb)\n\n    @staticmethod\n    def _s_rrrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCOpCodes\n        assert suffix == Suffix.S_RRRC or suffix == Suffix.U_RRRC\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCOpCodes:\n            condition = InstructionInitializer._condition(LogSetCC.conditions())\n        elif op_code in Instruction.RsubRRRCOpCodes:\n            condition = InstructionInitializer._condition(SubSetCC.conditions())\n        elif op_code in Instruction.SubRRRCOpCodes:\n            condition = InstructionInitializer._condition(ExtSubSetCC.conditions())\n        else:\n            raise ValueError\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition)\n\n    @staticmethod\n    def _s_rrrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRCIOpCodes\n        assert suffix == Suffix.S_RRRCI or suffix == Suffix.U_RRRCI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n\n        if op_code in Instruction.AddRRRCIOpCodes:\n            condition = InstructionInitializer._condition(AddNZCC.conditions())\n        elif op_code in Instruction.AndRRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.AsrRRRCIOpCodes:\n            condition = InstructionInitializer._condition(ShiftNZCC.conditions())\n        elif op_code in Instruction.MulRRRCIOpCodes:\n            condition = InstructionInitializer._condition(MulNZCC.conditions())\n        elif op_code in Instruction.RsubRRRCIOpCodes:\n            condition = InstructionInitializer._condition(SubNZCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n    @staticmethod\n    def _rr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.RR\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra)\n\n    @staticmethod\n    def _rrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.RRC\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(LogSetCC.conditions())\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition)\n\n    @staticmethod\n    def _rrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.RRCI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.CaoRRCIOpCodes:\n            condition = InstructionInitializer._condition(CountNZCC.conditions())\n        elif op_code in Instruction.ExtsbRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.TimeCfgRRCIOpCodes:\n            condition = InstructionInitializer._condition(TrueCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _zr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.ZR\n\n        ra = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, ra=ra)\n\n    @staticmethod\n    def _zrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.ZRC\n\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(LogSetCC.conditions())\n\n        return Instruction(op_code, suffix, ra=ra, condition=condition)\n\n    @staticmethod\n    def _zrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.ZRCI\n\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.CaoRRCIOpCodes:\n            condition = InstructionInitializer._condition(CountNZCC.conditions())\n        elif op_code in Instruction.ExtsbRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.TimeCfgRRCIOpCodes:\n            condition = InstructionInitializer._condition(TrueCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_rr(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RROpCodes\n        assert suffix == Suffix.S_RR or suffix == Suffix.U_RR\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra)\n\n    @staticmethod\n    def _s_rrc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCOpCodes\n        assert suffix == Suffix.S_RRC or suffix == Suffix.U_RRC\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(LogSetCC.conditions())\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition)\n\n    @staticmethod\n    def _s_rrci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRCIOpCodes\n        assert suffix == Suffix.S_RRCI or suffix == Suffix.U_RRCI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n\n        if op_code in Instruction.CaoRRCIOpCodes:\n            condition = InstructionInitializer._condition(CountNZCC.conditions())\n        elif op_code in Instruction.ExtsbRRCIOpCodes:\n            condition = InstructionInitializer._condition(LogNZCC.conditions())\n        elif op_code in Instruction.TimeCfgRRCIOpCodes:\n            condition = InstructionInitializer._condition(TrueCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _drdici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.DRDICIOpCodes\n        assert suffix == Suffix.DRDICI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        db = InstructionInitializer._pair_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n\n        if op_code in Instruction.DivStepDRDICIOpCodes:\n            condition = InstructionInitializer._condition(DivCC.conditions())\n        elif op_code in Instruction.MulStepDRDICIOpCodes:\n            condition = InstructionInitializer._condition(BootCC.conditions())\n        else:\n            raise ValueError\n\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, db=db, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _rrri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.RRRI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _rrrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.RRRICI\n\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        condition = InstructionInitializer._condition(DivNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _zrri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.ZRRI\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _zrrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.ZRRICI\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        condition = InstructionInitializer._condition(DivNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_rrri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRIOpCodes\n        assert suffix == Suffix.S_RRRI or suffix == Suffix.U_RRRI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm)\n\n    @staticmethod\n    def _s_rrrici(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RRRICIOpCodes\n        assert suffix == Suffix.S_RRRICI or suffix == Suffix.U_RRRICI\n\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 5)\n        condition = InstructionInitializer._condition(DivNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n    @staticmethod\n    def _rir(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIROpCodes\n        assert suffix == Suffix.RIR\n\n        rc = InstructionInitializer._gp_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 32)\n        ra = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra)\n\n    @staticmethod\n    def _rirc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.RIRC\n\n        rc = InstructionInitializer._gp_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubSetCC.conditions())\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _rirci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.RIRCI\n\n        rc = InstructionInitializer._gp_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 8)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _zir(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIROpCodes\n        assert suffix == Suffix.ZIR\n\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 32)\n        ra = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra)\n\n    @staticmethod\n    def _zirc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.ZIRC\n\n        imm = InstructionInitializer._imm(Representation.SIGNED, 27)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubSetCC.conditions())\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _zirci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.ZIRCI\n\n        imm = InstructionInitializer._imm(Representation.SIGNED, 11)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_rirc(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCOpCodes\n        assert suffix == Suffix.S_RIRC or suffix == Suffix.U_RIRC\n\n        dc = InstructionInitializer._pair_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubSetCC.conditions())\n\n        return Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition)\n\n    @staticmethod\n    def _s_rirci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RIRCIOpCodes\n        assert suffix == Suffix.S_RIRCI or suffix == Suffix.U_RIRCI\n\n        dc = InstructionInitializer._pair_register()\n        imm = InstructionInitializer._imm(Representation.SIGNED, 8)\n        ra = InstructionInitializer._source_register()\n        condition = InstructionInitializer._condition(SubNZCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n    @staticmethod\n    def _r(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ROpCodes\n        assert suffix == Suffix.R\n\n        rc = InstructionInitializer._gp_register()\n\n        return Instruction(op_code, suffix, rc=rc)\n\n    @staticmethod\n    def _rci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.RCI\n\n        rc = InstructionInitializer._gp_register()\n        condition = InstructionInitializer._condition(TrueCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, rc=rc, condition=condition, pc=pc)\n\n    @staticmethod\n    def _z(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ROpCodes or op_code == OpCode.NOP\n        assert suffix == Suffix.Z\n\n        return Instruction(op_code, suffix)\n\n    @staticmethod\n    def _zci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.ZCI\n\n        condition = InstructionInitializer._condition(TrueCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, condition=condition, pc=pc)\n\n    @staticmethod\n    def _s_r(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ROpCodes\n        assert suffix == Suffix.S_R or suffix == Suffix.U_R\n\n        dc = InstructionInitializer._pair_register()\n\n        return Instruction(op_code, suffix, dc=dc)\n\n    @staticmethod\n    def _s_rci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.RCIOpCodes\n        assert suffix == Suffix.S_RCI or suffix == Suffix.U_RCI\n\n        dc = InstructionInitializer._pair_register()\n        condition = InstructionInitializer._condition(TrueCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, condition=condition, pc=pc)\n\n    @staticmethod\n    def _ci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.CIOpCodes\n        assert suffix == Suffix.CI\n\n        condition = InstructionInitializer._condition(BootCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, condition=condition, pc=pc)\n\n    @staticmethod\n    def _i(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.IOpCodes\n        assert suffix == Suffix.I\n\n        imm = InstructionInitializer._imm(Representation.SIGNED, 24)\n\n        return Instruction(op_code, suffix, imm=imm)\n\n    @staticmethod\n    def _ddci(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.DDCIOpCodes\n        assert suffix == Suffix.DDCI\n\n        dc = InstructionInitializer._pair_register()\n        db = InstructionInitializer._pair_register()\n        condition = InstructionInitializer._condition(TrueFalseCC.conditions())\n        pc = InstructionInitializer._pc()\n\n        return Instruction(op_code, suffix, dc=dc, db=db, condition=condition, pc=pc)\n\n    @staticmethod\n    def _erri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ERRIOpCodes\n        assert suffix == Suffix.ERRI\n\n        endian = InstructionInitializer._endian()\n        rc = InstructionInitializer._gp_register()\n        ra = InstructionInitializer._source_register()\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n\n        return Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n    @staticmethod\n    def _s_erri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ERRIOpCodes\n        assert suffix == Suffix.S_ERRI or suffix == Suffix.U_ERRI\n\n        endian = InstructionInitializer._endian()\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n\n        return Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n    @staticmethod\n    def _edri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.EDRIOpCodes\n        assert suffix == Suffix.EDRI\n\n        endian = InstructionInitializer._endian()\n        dc = InstructionInitializer._pair_register()\n        ra = InstructionInitializer._source_register()\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n\n        return Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n    @staticmethod\n    def _erii(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ERIIOpCodes\n        assert suffix == Suffix.ERII\n\n        endian = InstructionInitializer._endian()\n        ra = InstructionInitializer._source_register()\n        # NOTE(bongjoon.hyun@gmail.com): original width is 12\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n        # NOTE(bongjoon.hyun@gmail.com): original width is 8\n        imm = InstructionInitializer._imm(Representation.SIGNED, 16)\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n    @staticmethod\n    def _erir(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ERIROpCodes\n        assert suffix == Suffix.ERIR\n\n        endian = InstructionInitializer._endian()\n        ra = InstructionInitializer._source_register()\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n        rb = InstructionInitializer._source_register()\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n    @staticmethod\n    def _erid(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.ERIDOpCodes\n        assert suffix == Suffix.ERID\n\n        endian = InstructionInitializer._endian()\n        ra = InstructionInitializer._source_register()\n        off = InstructionInitializer._imm(Representation.SIGNED, 24)\n        db = InstructionInitializer._pair_register()\n\n        return Instruction(op_code, suffix, endian=endian, ra=ra, off=off, db=db)\n\n    @staticmethod\n    def _dma_rri(op_code: OpCode, suffix: Suffix) -> Instruction:\n        assert op_code in Instruction.DMARRIOpCodes\n        assert suffix == Suffix.DMA_RRI\n\n        ra = InstructionInitializer._source_register()\n        rb = InstructionInitializer._source_register()\n        imm = InstructionInitializer._imm(Representation.UNSIGNED, 8)\n\n        return Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/initializer/int_initializer.py",
    "content": "import random\nfrom typing import Any, List\n\nfrom abi.word.representation import Representation\n\n\nclass IntInitializer:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def value_by_range(min_value: int, max_value: int) -> int:\n        assert min_value < max_value\n\n        return random.randrange(min_value, max_value)\n\n    @staticmethod\n    def value_by_width(representation: Representation, width: int):\n        assert width > 0\n\n        if representation == Representation.UNSIGNED:\n            return IntInitializer.value_by_range(0, 2 ** width)\n        elif representation == Representation.SIGNED:\n            return IntInitializer.value_by_range(-(2 ** (width - 1)), 2 ** (width - 1))\n        else:\n            raise ValueError\n\n    @staticmethod\n    def value_by_list(list_: List[Any]) -> Any:\n        return random.choice(list_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/initializer/str_initializer.py",
    "content": "import random\n\n\nclass StrInitializer:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def identifier(width: int) -> str:\n        assert width > 0\n\n        return random.choice(StrInitializer._non_digit_characters()) + \"\".join(\n            [random.choice(StrInitializer._characters()) for _ in range(width - 1)]\n        )\n\n    @staticmethod\n    def _non_digit_characters() -> str:\n        return StrInitializer._alphabets() + StrInitializer._digits()\n\n    @staticmethod\n    def _characters() -> str:\n        return StrInitializer._non_digit_characters() + StrInitializer._digits()\n\n    @staticmethod\n    def _alphabets() -> str:\n        return \"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\"\n\n    @staticmethod\n    def _digits() -> str:\n        return \"0123456789\"\n\n    @staticmethod\n    def _special_symbols() -> str:\n        return \"._\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/cpu/cpu.py",
    "content": "from iss.cpu.fini_thread import FiniThread\nfrom iss.cpu.init_thread import InitThread\nfrom iss.cpu.sched_thread import SchedThread\nfrom iss.dpu.dpu import DPU\n\n\nclass CPU:\n    def __init__(self, benchmark: str, num_tasklets: int, dpu: DPU):\n        self._init_thread: InitThread = InitThread(benchmark, num_tasklets, dpu)\n        self._sched_thread: SchedThread = SchedThread(benchmark, num_tasklets, dpu)\n        self._fini_thread: FiniThread = FiniThread(benchmark, num_tasklets, dpu)\n\n    def num_executions(self) -> int:\n        return self._sched_thread.num_executions()\n        \n    def init(self) -> None:\n        self._init_thread.init()\n\n    def launch(self) -> None:\n        self._init_thread.launch()\n\n    def sched(self, execution: int) -> None:\n        self._sched_thread.sched(execution)\n\n    def check(self, execution: int) -> None:\n        self._sched_thread.check(execution)\n\n    def fini(self) -> None:\n        self._fini_thread.fini()\n\n    def cycle(self) -> None:\n        self._init_thread.cycle()\n        self._sched_thread.cycle()\n        self._fini_thread.cycle()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/cpu/fini_thread.py",
    "content": "from iss.cpu.init_thread import InitThread\nfrom iss.dpu.dpu import DPU\nfrom iss.dpu.thread import Thread\n\n\nclass FiniThread:\n    def __init__(self, benchmark: str, num_tasklets: int, dpu: DPU):\n        self._benchmark: str = benchmark\n        self._num_tasklets: int = num_tasklets\n        self._dpu: DPU = dpu\n\n    def fini(self) -> None:\n        pass\n\n    def cycle(self) -> None:\n        sys_end_pointer = InitThread.load_sys_end_pointer(self._benchmark, self._num_tasklets)\n        for thread in self._dpu.threads():\n            if thread.register_file().read_pc() == sys_end_pointer and thread.state() == Thread.State.SLEEP:\n                thread.set_thread_state(Thread.State.ZOMBIE)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/cpu/init_thread.py",
    "content": "import os\nfrom typing import List, Tuple\n\nfrom encoder.byte import Byte\nfrom iss.dpu.dpu import DPU\nfrom util.config_loader import ConfigLoader\nfrom util.path_collector import PathCollector\n\n\nclass InitThread:\n    def __init__(self, benchmark: str, num_tasklets: int, dpu: DPU):\n        self._benchmark: str = benchmark\n        self._num_tasklets: int = num_tasklets\n        self._dpu: DPU = dpu\n\n    def init(self) -> None:\n        self._dma_transfer_atomic()\n        self._dma_transfer_iram()\n        self._dma_transfer_wram()\n        self._dma_transfer_mram()\n\n    def launch(self) -> None:\n        for thread in self._dpu.threads():\n            bootstrap = ConfigLoader.iram_offset()\n            thread.register_file().write_pc(bootstrap)\n\n        self._dpu.boot()\n\n    def cycle(self) -> None:\n        pass\n\n    def _dma_transfer_atomic(self) -> None:\n        atomic_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{self._benchmark}.{self._num_tasklets}\", \"atomic.bin\",\n        )\n        atomic_address = ConfigLoader.atomic_offset()\n        atomic_bytes = InitThread.load_bytes(atomic_bin_filepath)\n        self._dpu.dma().host_dma_transfer_to_atomic(atomic_address, atomic_bytes)\n\n    def _dma_transfer_iram(self) -> None:\n        iram_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{self._benchmark}.{self._num_tasklets}\", \"iram.bin\",\n        )\n        iram_address = ConfigLoader.iram_offset()\n        iram_bytes = InitThread.load_bytes(iram_bin_filepath)\n        self._dpu.dma().host_dma_transfer_to_iram(iram_address, iram_bytes)\n\n    def _dma_transfer_wram(self) -> None:\n        wram_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{self._benchmark}.{self._num_tasklets}\", \"wram.bin\",\n        )\n        wram_address = ConfigLoader.wram_offset()\n        wram_bytes = InitThread.load_bytes(wram_bin_filepath)\n        self._dpu.dma().host_dma_transfer_to_wram(wram_address, wram_bytes)\n\n    def _dma_transfer_mram(self) -> None:\n        mram_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{self._benchmark}.{self._num_tasklets}\", \"mram.bin\",\n        )\n        mram_address = ConfigLoader.mram_offset()\n        mram_bytes = InitThread.load_bytes(mram_bin_filepath)\n        self._dpu.dma().host_dma_transfer_to_mram(mram_address, mram_bytes)\n\n    @staticmethod\n    def load_sys_used_mram_end_pointer(benchmark: str, num_tasklets: int) -> int:\n        return InitThread.load_dpu_transfer_pointer(benchmark, num_tasklets)[0]\n\n    @staticmethod\n    def load_dpu_input_arguments_pointer(benchmark: str, num_tasklets: int) -> int:\n        return InitThread.load_dpu_transfer_pointer(benchmark, num_tasklets)[1]\n\n    @staticmethod\n    def load_dpu_results_pointer(benchmark: str, num_tasklets: int) -> int:\n        return InitThread.load_dpu_transfer_pointer(benchmark, num_tasklets)[2]\n\n    @staticmethod\n    def load_sys_end_pointer(benchmark: str, num_tasklets: int) -> int:\n        return InitThread.load_dpu_transfer_pointer(benchmark, num_tasklets)[3]\n\n    @staticmethod\n    def load_bytes(bin_filepath: str) -> List[Byte]:\n        bytes_: List[Byte] = []\n        with open(bin_filepath) as file:\n            for line in file.readlines():\n                bytes_.append(Byte(int(line)))\n        return bytes_\n\n    @staticmethod\n    def load_dpu_transfer_pointer(benchmark: str, num_tasklets: int) -> Tuple[int, int, int, int]:\n        dpu_transfer_pointer_filepath = os.path.join(\n            PathCollector.bin_path_in_local(), f\"{benchmark}.{num_tasklets}\", \"dpu_transfer_pointer.bin\",\n        )\n\n        with open(dpu_transfer_pointer_filepath) as file:\n            lines = file.readlines()\n\n            sys_used_mram_end, dpu_input_arguments, dpu_results, sys_end = (\n                int(lines[0]),\n                int(lines[1]),\n                int(lines[2]),\n                int(lines[3]),\n            )\n            return sys_used_mram_end, dpu_input_arguments, dpu_results, sys_end\n\n    @staticmethod\n    def load_num_executions(benchmark: str, num_tasklets: int) -> int:\n        num_executions_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{benchmark}.{num_tasklets}\",\n            \"num_executions.bin\",\n        )\n\n        with open(num_executions_filepath) as file:\n            lines = file.readlines()\n            num_executions = int(lines[0])\n            return num_executions"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/cpu/sched_thread.py",
    "content": "import os\nfrom typing import List\n\nfrom encoder.byte import Byte\nfrom iss.cpu.init_thread import InitThread\nfrom iss.dpu.dpu import DPU\nfrom iss.dram.mram_command import MRAMCommand\nfrom util.path_collector import PathCollector\n\n\nclass SchedThread:\n    def __init__(self, benchmark: str, num_tasklets: int, dpu: DPU):\n        self._benchmark: str = benchmark\n        self._num_tasklets: int = num_tasklets\n        self._dpu: DPU = dpu\n\n    def num_executions(self) -> int:\n        return InitThread.load_num_executions(self._benchmark, self._num_tasklets)\n\n    def sched(self, execution: int) -> None:\n        self._dma_transfer_input_mram_heap_pointer_name(execution)\n        self._dma_transfer_dpu_input_arguments(execution)\n\n    def check(self, execution: int) -> None:\n        self._dma_transfer_output_mram_heap_pointer_name(execution)\n        self._dma_transfer_dpu_results(execution)\n\n    def cycle(self) -> None:\n        pass\n\n    def _dma_transfer_input_mram_heap_pointer_name(self, execution: int) -> None:\n        input_dpu_mram_heap_pointer_name_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{self._benchmark}.{self._num_tasklets}\",\n            f\"input_dpu_mram_heap_pointer_name.{execution}.bin\",\n        )\n\n        if os.path.exists(input_dpu_mram_heap_pointer_name_bin_filepath):\n            sys_used_mram_end_pointer = InitThread.load_sys_used_mram_end_pointer(self._benchmark, self._num_tasklets)\n            input_dpu_mram_heap_pointer_name_bytes = InitThread.load_bytes(\n                input_dpu_mram_heap_pointer_name_bin_filepath\n            )\n            self._dpu.dma().host_dma_transfer_to_mram(sys_used_mram_end_pointer, input_dpu_mram_heap_pointer_name_bytes)\n\n    def _dma_transfer_dpu_input_arguments(self, execution: int) -> None:\n        dpu_input_arguments_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{self._benchmark}.{self._num_tasklets}\",\n            f\"dpu_input_arguments.{execution}.bin\",\n        )\n\n        if os.path.exists(dpu_input_arguments_bin_filepath):\n            dpu_input_arguments_pointer = InitThread.load_dpu_input_arguments_pointer(\n                self._benchmark, self._num_tasklets\n            )\n\n            if dpu_input_arguments_pointer != -1:\n                dpu_input_arguments_bytes = InitThread.load_bytes(dpu_input_arguments_bin_filepath)\n                self._dpu.dma().host_dma_transfer_to_wram(dpu_input_arguments_pointer, dpu_input_arguments_bytes)\n\n    def _dma_transfer_output_mram_heap_pointer_name(self, execution: int) -> None:\n        output_dpu_mram_heap_pointer_name_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{self._benchmark}.{self._num_tasklets}\",\n            f\"output_dpu_mram_heap_pointer_name.{execution}.bin\",\n        )\n\n        if os.path.exists(output_dpu_mram_heap_pointer_name_bin_filepath):\n            output_dpu_mram_heap_pointer_name_bytes = InitThread.load_bytes(\n                output_dpu_mram_heap_pointer_name_bin_filepath\n            )\n\n            sys_used_mram_end_pointer = InitThread.load_sys_used_mram_end_pointer(self._benchmark, self._num_tasklets)\n\n            mram_command = MRAMCommand(\n                MRAMCommand.Operation.READ, sys_used_mram_end_pointer, len(output_dpu_mram_heap_pointer_name_bytes),\n            )\n            assert self._dpu.mram().can_push()\n            self._dpu.mram().push(mram_command)\n            assert self._dpu.mram().can_pop()\n            assert self._dpu.mram().pop() == mram_command\n\n            mram_command_bytes: List[Byte] = []\n            for data_word in mram_command.data_words():\n                mram_command_bytes += data_word.to_bytes()\n\n            for output_dpu_mram_heap_pointer_name_byte, mram_command_byte in zip(\n                output_dpu_mram_heap_pointer_name_bytes, mram_command_bytes\n            ):\n                assert output_dpu_mram_heap_pointer_name_byte.value() == mram_command_byte.value()\n\n    def _dma_transfer_dpu_results(self, execution: int) -> None:\n        dpu_results_bin_filepath = os.path.join(\n            PathCollector.bin_path_in_local(),\n            f\"{self._benchmark}.{self._num_tasklets}\",\n            f\"dpu_results.{execution}.bin\",\n        )\n\n        if os.path.exists(dpu_results_bin_filepath):\n            dpu_results_bytes = InitThread.load_bytes(dpu_results_bin_filepath)\n\n            dpu_results_pointer = InitThread.load_dpu_results_pointer(self._benchmark, self._num_tasklets)\n\n            wram_bytes = self._dpu.dma().host_dma_transfer_from_wram(dpu_results_pointer, len(dpu_results_bytes))\n\n            for dpu_results_byte, wram_byte in zip(dpu_results_bytes, wram_bytes):\n                assert dpu_results_byte.value() == wram_byte.value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/alu.py",
    "content": "from typing import Tuple\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.double_data_word import DoubleDataWord\nfrom abi.word.representation import Representation\n\n\nclass ALU:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def atomic_address_hash(operand1: int, operand2: int) -> int:\n        assert operand1 + operand2 < 2 ** 8\n        return ALU.add(operand1, operand2)[0]\n\n    @staticmethod\n    def add(operand1: int, operand2: int) -> Tuple[int, bool, bool]:\n        return ALU.addc(operand1, operand2, False)\n\n    @staticmethod\n    def addc(operand1: int, operand2: int, carry_flag: bool) -> Tuple[int, bool, bool]:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result = data_word1.value(Representation.UNSIGNED) + data_word2.value(Representation.UNSIGNED) + int(carry_flag)\n\n        max_unsigned_value = 2 ** DataWord().width() - 1\n        if result > max_unsigned_value:\n            result %= 2 ** DataWord().width()\n            carry = True\n        else:\n            carry = False\n\n        result_data_word = DataWord()\n        result_data_word.set_value(result)\n\n        if data_word1.sign_bit() and data_word2.sign_bit() and not result_data_word.sign_bit():\n            overflow = True\n        elif not data_word1.sign_bit() and not data_word2.sign_bit() and result_data_word.sign_bit():\n            overflow = True\n        else:\n            overflow = False\n\n        return result, carry, overflow\n\n    @staticmethod\n    def sub(operand1: int, operand2: int) -> Tuple[int, bool, bool]:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        if data_word1.value(Representation.UNSIGNED) >= data_word2.value(Representation.UNSIGNED):\n            result = data_word1.value(Representation.UNSIGNED) - data_word2.value(Representation.UNSIGNED)\n            carry = False\n        else:\n            result = (\n                2 ** DataWord().width()\n                + data_word1.value(Representation.UNSIGNED)\n                - data_word2.value(Representation.UNSIGNED)\n            )\n            carry = True\n\n        result_data_word = DataWord()\n        result_data_word.set_value(result)\n\n        if data_word1.sign_bit() and not data_word2.sign_bit() and result_data_word.sign_bit():\n            overflow = True\n        elif not data_word1.sign_bit() and data_word2.sign_bit() and not result_data_word.sign_bit():\n            overflow = True\n        else:\n            overflow = False\n        return result, carry, overflow\n\n    @staticmethod\n    def subc(operand1: int, operand2: int, carry_flag: bool) -> Tuple[int, bool, bool]:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        # NOTE(bongjoon.hyun@gmail.com): this doesn't make sense logically, but it works\n        if data_word1.value(Representation.UNSIGNED) + int(carry_flag) >= data_word2.value(Representation.UNSIGNED):\n            result = (\n                data_word1.value(Representation.UNSIGNED) - data_word2.value(Representation.UNSIGNED) - int(carry_flag)\n            )\n            carry = False\n        else:\n            result = (\n                2 ** DataWord().width()\n                + data_word1.value(Representation.UNSIGNED)\n                - data_word2.value(Representation.UNSIGNED)\n                - int(carry_flag)\n            )\n            carry = True\n\n        result_data_word = DataWord()\n        result_data_word.set_value(result)\n\n        if data_word1.sign_bit() and not data_word2.sign_bit() and result_data_word.sign_bit():\n            overflow = True\n        elif not data_word1.sign_bit() and data_word2.sign_bit() and not result_data_word.sign_bit():\n            overflow = True\n        else:\n            overflow = False\n        return result, carry, overflow\n\n    @staticmethod\n    def and_(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if data_word1.bit(i) and data_word2.bit(i):\n                result_data_word.set_bit(i)\n            else:\n                result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def nand(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if data_word1.bit(i) and data_word2.bit(i):\n                result_data_word.clear_bit(i)\n            else:\n                result_data_word.set_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def andn(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if (not data_word1.bit(i)) and data_word2.bit(i):\n                result_data_word.set_bit(i)\n            else:\n                result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def or_(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if data_word1.bit(i) or data_word2.bit(i):\n                result_data_word.set_bit(i)\n            else:\n                result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def nor(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if data_word1.bit(i) or data_word2.bit(i):\n                result_data_word.clear_bit(i)\n            else:\n                result_data_word.set_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def orn(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if (not data_word1.bit(i)) or data_word2.bit(i):\n                result_data_word.set_bit(i)\n            else:\n                result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def xor(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if ((not data_word1.bit(i)) and data_word2.bit(i)) or (data_word1.bit(i) and (not data_word2.bit(i))):\n                result_data_word.set_bit(i)\n            else:\n                result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def nxor(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if ((not data_word1.bit(i)) and data_word2.bit(i)) or (data_word1.bit(i) and (not data_word2.bit(i))):\n                result_data_word.clear_bit(i)\n            else:\n                result_data_word.set_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def asr(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        msb = data_word.bit(data_word.width() - 1)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i + shift_value >= result_data_word.width():\n                if msb:\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n            else:\n                if data_word.bit(i + shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def lsl(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i < shift_value:\n                result_data_word.clear_bit(i)\n            else:\n                if data_word.bit(i - shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def lsl_add(operand1: int, operand2: int, shift: int) -> Tuple[int, bool, bool]:\n        return ALU.add(operand1, ALU.lsl(operand2, shift))\n\n    @staticmethod\n    def lsl_sub(operand1: int, operand2: int, shift: int) -> Tuple[int, bool, bool]:\n        return ALU.sub(operand1, ALU.lsl(operand2, shift))\n\n    @staticmethod\n    def lsl1(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i < shift_value:\n                result_data_word.set_bit(i)\n            else:\n                if data_word.bit(i - shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def lsl1x(operand: int, shift: int) -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def lslx(operand: int, shift: int) -> int:\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        if shift_value == 0:\n            return 0\n        else:\n            return ALU.lsr(operand, 32 - shift_value)\n\n    @staticmethod\n    def lsr(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n        \n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i + shift_value >= result_data_word.width():\n                result_data_word.clear_bit(i)\n            else:\n                if data_word.bit(i + shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def lsr_add(operand1: int, operand2: int, shift: int) -> Tuple[int, bool, bool]:\n        return ALU.add(operand1, ALU.lsr(operand2, shift))\n\n    @staticmethod\n    def lsr1(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i + shift_value >= result_data_word.width():\n                result_data_word.set_bit(i)\n            else:\n                if data_word.bit(i + shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def lsr1x(operand: int, shift: int) -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def lsrx(operand: int, shift: int) -> int:\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        if shift_value == 0:\n            return 0\n        else:\n            return ALU.lsl(operand, 32 - shift_value)\n\n    @staticmethod\n    def rol(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i < shift_value:\n                if data_word.bit(i + data_word.width() - shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n            else:\n                if data_word.bit(i - shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def rol_add(operand1: int, operand2: int, shift: int) -> Tuple[int, bool, bool]:\n        return ALU.add(operand1, ALU.rol(operand2, shift))\n\n    @staticmethod\n    def ror(operand: int, shift: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        shift_data_word = DataWord()\n        shift_data_word.set_value(shift)\n        shift_value = shift_data_word.bit_slice(Representation.UNSIGNED, 0, 5)\n\n        result_data_word = DataWord()\n        for i in range(result_data_word.width()):\n            if i + shift_value >= result_data_word.width():\n                if data_word.bit((i + shift_value) % data_word.width()):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n            else:\n                if data_word.bit(i + shift_value):\n                    result_data_word.set_bit(i)\n                else:\n                    result_data_word.clear_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def cao(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        ones = 0\n        for i in range(data_word.width()):\n            if data_word.bit(i):\n                ones += 1\n        return ones\n\n    @staticmethod\n    def clo(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        leading_ones = 0\n        for i in range(data_word.width()):\n            if data_word.bit(data_word.width() - 1 - i):\n                leading_ones += 1\n            else:\n                break\n        return leading_ones\n\n    @staticmethod\n    def cls(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        msb = data_word.bit(data_word.width() - 1)\n\n        leading_sign_bits = 0\n        for i in range(data_word.width()):\n            if data_word.bit(data_word.width() - 1 - i) == msb:\n                leading_sign_bits += 1\n            else:\n                break\n        return leading_sign_bits\n\n    @staticmethod\n    def clz(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        leading_zeros = 0\n        for i in range(data_word.width()):\n            if not data_word.bit(data_word.width() - 1 - i):\n                leading_zeros += 1\n            else:\n                break\n        return leading_zeros\n\n    @staticmethod\n    def cmpb4(operand1: int, operand2: int) -> int:\n        assert DataWord().width() == 4 * 8\n\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        for i in range(4):\n            begin = 8 * i\n            end = 8 * (i + 1)\n\n            byte1 = data_word1.bit_slice(Representation.UNSIGNED, begin, end)\n            byte2 = data_word2.bit_slice(Representation.UNSIGNED, begin, end)\n            if byte1 == byte2:\n                result_data_word.set_bit_slice(begin, end, 1)\n            else:\n                result_data_word.set_bit_slice(begin, end, 0)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def extsb(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        return data_word.bit_slice(Representation.SIGNED, 0, 8)\n\n    @staticmethod\n    def extsh(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        return data_word.bit_slice(Representation.SIGNED, 0, 16)\n\n    @staticmethod\n    def extub(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        return data_word.bit_slice(Representation.UNSIGNED, 0, 8)\n\n    @staticmethod\n    def extuh(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n        return data_word.bit_slice(Representation.UNSIGNED, 0, 16)\n\n    @staticmethod\n    def mul_sh_sh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 8, 16) * data_word2.bit_slice(Representation.SIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sh_sl(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 8, 16) * data_word2.bit_slice(Representation.SIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sh_uh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 8, 16) * data_word2.bit_slice(Representation.UNSIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sh_ul(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 8, 16) * data_word2.bit_slice(Representation.UNSIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sl_sh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 0, 8) * data_word2.bit_slice(Representation.SIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sl_sl(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 0, 8) * data_word2.bit_slice(Representation.SIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sl_uh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 0, 8) * data_word2.bit_slice(Representation.UNSIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_sl_ul(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.SIGNED, 0, 8) * data_word2.bit_slice(Representation.UNSIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_uh_uh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.UNSIGNED, 8, 16) * data_word2.bit_slice(Representation.UNSIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def mul_uh_ul(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.UNSIGNED, 8, 16) * data_word2.bit_slice(Representation.UNSIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_ul_uh(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.UNSIGNED, 0, 8) * data_word2.bit_slice(Representation.UNSIGNED, 8, 16)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def mul_ul_ul(operand1: int, operand2: int) -> int:\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(\n            data_word1.bit_slice(Representation.UNSIGNED, 0, 8) * data_word2.bit_slice(Representation.UNSIGNED, 0, 8)\n        )\n\n        return result_data_word.value(Representation.SIGNED)\n\n    @staticmethod\n    def sats(operand: int) -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def hash(operand1: int, operand2: int) -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def tilde(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        result_data_word = DataWord()\n        for i in range(data_word.width()):\n            if data_word.bit(i):\n                result_data_word.clear_bit(i)\n            else:\n                result_data_word.set_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def signed_extension(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        result_data_word = DoubleDataWord()\n        result_data_word.set_bit_slice(0, data_word.width(), data_word.value(Representation.UNSIGNED))\n\n        if data_word.sign_bit():\n            for i in range(data_word.width(), 2 * data_word.width()):\n                result_data_word.set_bit(i)\n        return result_data_word.value(Representation.UNSIGNED)\n\n    @staticmethod\n    def unsigned_extension(operand: int) -> int:\n        data_word = DataWord()\n        data_word.set_value(operand)\n\n        result_data_word = DoubleDataWord()\n        result_data_word.set_bit_slice(0, data_word.width(), data_word.value(Representation.UNSIGNED))\n\n        for i in range(data_word.width(), 2 * data_word.width()):\n            result_data_word.clear_bit(i)\n\n        return result_data_word.value(Representation.UNSIGNED)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/decoder.py",
    "content": "from abi.isa.instruction.instruction import Instruction\nfrom abi.word.instruction_word import InstructionWord\nfrom encoder.instruction_encoder import InstructionEncoder\n\n\nclass Decoder:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def decode(instruction_word: InstructionWord) -> Instruction:\n        bytes_ = instruction_word.to_bytes()\n        return InstructionEncoder.decode(bytes_)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/dispatcher.py",
    "content": "from abi.word.data_word import DataWord\nfrom abi.word.double_data_word import DoubleDataWord\nfrom abi.word.representation import Representation\nfrom iss.sram.wram import WRAM\n\n\nclass Dispatcher:\n    def __init__(self, wram: WRAM):\n        self._wram: WRAM = wram\n\n    def lbs(self, address: int) -> int:\n        base_address = (address // DataWord().size()) * DataWord().size()\n        offset = address % DataWord().size()\n\n        data_word = DataWord()\n        data_word.set_value(self._wram.read(base_address).value(Representation.SIGNED))\n        return data_word.bit_slice(Representation.SIGNED, 8 * offset, 8 * (offset + 1))\n\n    def lbu(self, address: int) -> int:\n        base_address = (address // DataWord().size()) * DataWord().size()\n        offset = address % DataWord().size()\n\n        data_word = DataWord()\n        data_word.set_value(self._wram.read(base_address).value(Representation.UNSIGNED))\n        return data_word.bit_slice(Representation.UNSIGNED, 8 * offset, 8 * (offset + 1))\n\n    def lhs(self, address: int) -> int:\n        data_word = DataWord()\n        data_word.set_bit_slice(0, 8, self.lbs(address))\n        data_word.set_bit_slice(8, 16, self.lbs(address + 1))\n        return data_word.bit_slice(Representation.SIGNED, 0, 16)\n\n    def lhu(self, address: int) -> int:\n        data_word = DataWord()\n        data_word.set_bit_slice(0, 8, self.lbu(address))\n        data_word.set_bit_slice(8, 16, self.lbu(address + 1))\n        return data_word.bit_slice(Representation.UNSIGNED, 0, 16)\n\n    def lw(self, address: int) -> int:\n        data_word = DataWord()\n        data_word.set_bit_slice(0, 8, self.lbu(address))\n        data_word.set_bit_slice(8, 16, self.lbu(address + 1))\n        data_word.set_bit_slice(16, 24, self.lbu(address + 2))\n        data_word.set_bit_slice(24, 32, self.lbu(address + 3))\n        return data_word.value(Representation.UNSIGNED)\n\n    def ld(self, address: int) -> int:\n        double_data_word = DoubleDataWord()\n        double_data_word.set_bit_slice(0, DataWord().width(), self.lw(address))\n        double_data_word.set_bit_slice(\n            DataWord().width(), 2 * DataWord().width(), self.lw(address + DataWord().size()),\n        )\n        return double_data_word.value(Representation.UNSIGNED)\n\n    def sb(self, address: int, value: int) -> None:\n        base_address = (address // DataWord().size()) * DataWord().size()\n        offset = address % DataWord().size()\n\n        data_word = self._wram.read(base_address)\n        data_word.set_bit_slice(8 * offset, 8 * (offset + 1), value)\n\n        self._wram.write(base_address, data_word)\n\n    def sh(self, address: int, value: int) -> None:\n        value_word = DataWord()\n        value_word.set_value(value)\n\n        self.sb(address, value_word.bit_slice(Representation.UNSIGNED, 0, 8))\n        self.sb(address + 1, value_word.bit_slice(Representation.UNSIGNED, 8, 16))\n\n    def sw(self, address: int, value: int) -> None:\n        value_word = DataWord()\n        value_word.set_value(value)\n\n        self.sb(address, value_word.bit_slice(Representation.UNSIGNED, 0, 8))\n        self.sb(address + 1, value_word.bit_slice(Representation.UNSIGNED, 8, 16))\n        self.sb(address + 2, value_word.bit_slice(Representation.UNSIGNED, 16, 24))\n        self.sb(address + 3, value_word.bit_slice(Representation.UNSIGNED, 24, 32))\n\n    def sd(self, address: int, value: int) -> None:\n        value_word = DoubleDataWord()\n        value_word.set_value(value)\n\n        self.sw(\n            address, value_word.bit_slice(Representation.UNSIGNED, 0, DataWord().width()),\n        )\n        self.sw(\n            address + DataWord().size(),\n            value_word.bit_slice(Representation.UNSIGNED, DataWord().width(), 2 * DataWord().width()),\n        )\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/dma.py",
    "content": "import math\nfrom typing import List\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\nfrom iss.dram.mram import MRAM\nfrom iss.dram.mram_command import MRAMCommand\nfrom iss.sram.atomic import Atomic\nfrom iss.sram.iram import IRAM\nfrom iss.sram.wram import WRAM\nfrom util.config_loader import ConfigLoader\n\n\nclass DMA:\n    def __init__(self, atomic: Atomic, iram: IRAM, wram: WRAM, mram: MRAM):\n        self._atomic: Atomic = atomic\n        self._iram: IRAM = iram\n        self._wram: WRAM = wram\n        self._mram: MRAM = mram\n\n    def host_dma_transfer_to_atomic(self, address: int, bytes_: List[Byte]) -> None:\n        for byte in bytes_:\n            assert byte.value() == 0\n\n    def host_dma_transfer_to_iram(self, address: int, bytes_: List[Byte]) -> None:\n        assert len(bytes_) % InstructionWord().size() == 0\n        num_instruction_words = math.ceil(len(bytes_) // InstructionWord().size())\n        for i in range(num_instruction_words):\n            instruction_word = InstructionWord()\n\n            begin = instruction_word.size() * i\n            end = instruction_word.size() * (i + 1)\n\n            instruction_word.from_bytes(bytes_[begin:end])\n            self._iram.write(address + begin, instruction_word)\n\n    def host_dma_transfer_to_wram(self, address: int, bytes_: List[Byte]) -> None:\n        for i in range(len(bytes_)):\n            cur_address = address + i\n            base_address = (cur_address // DataWord().size()) * DataWord().size()\n            offset = cur_address % DataWord().size()\n\n            data_word = self._wram.read(base_address)\n            data_word.set_bit_slice(8 * offset, 8 * (offset + 1), bytes_[i].value())\n            self._wram.write(base_address, data_word)\n\n    def host_dma_transfer_from_wram(self, address: int, size: int) -> List[Byte]:\n        bytes_: List[Byte] = []\n        for i in range(size):\n            cur_address = address + i\n            base_address = (cur_address // DataWord().size()) * DataWord().size()\n            offset = cur_address % DataWord().size()\n\n            data_word = self._wram.read(base_address)\n            bytes_.append(Byte(data_word.bit_slice(Representation.UNSIGNED, 8 * offset, 8 * (offset + 1))))\n        return bytes_\n\n    def host_dma_transfer_to_mram(self, address: int, bytes_: List[Byte]) -> None:\n        num_data_words = math.ceil(len(bytes_) / DataWord().size())\n        data_words: List[DataWord] = []\n        for i in range(num_data_words):\n            data_word = DataWord()\n\n            begin = data_word.size() * i\n            end = min(data_word.size() * (i + 1), len(bytes_))\n\n            if end - begin < data_word.size():\n                data_word.from_bytes(bytes_[begin:end] + [Byte(0) for _ in range(data_word.size() - end + begin)])\n            else:\n                data_word.from_bytes(bytes_[begin:end])\n            data_words.append(data_word)\n\n        while (len(data_words) * DataWord().size()) % ConfigLoader.min_access_granularity() != 0:\n            data_words.append(DataWord())\n\n        mram_command = MRAMCommand(MRAMCommand.Operation.WRITE, address, len(data_words) * DataWord().size())\n        mram_command.set_data_words(data_words)\n\n        assert self._mram.can_push()\n        self._mram.push(mram_command)\n        assert self._mram.can_pop()\n        assert mram_command == self._mram.pop()\n\n    def dpu_dma_transfer_from_mram_to_wram(self, src_address: int, dst_address: int, size: int) -> None:\n        assert size % ConfigLoader.min_access_granularity() == 0\n        assert size % DataWord().size() == 0\n\n        mram_command = MRAMCommand(MRAMCommand.Operation.READ, src_address, size)\n\n        assert self._mram.can_push()\n        self._mram.push(mram_command)\n        assert self._mram.can_pop()\n        assert mram_command == self._mram.pop()\n\n        for i, data_word in enumerate(mram_command.data_words()):\n            self._wram.write(dst_address + i * data_word.size(), data_word)\n\n    def dpu_dma_transfer_from_wram_to_mram(self, src_address: int, dst_address: int, size: int) -> None:\n        assert size % ConfigLoader.min_access_granularity() == 0\n        assert size % DataWord().size() == 0\n\n        num_data_words = size // DataWord().size()\n        data_words: List[DataWord] = []\n        for i in range(num_data_words):\n            data_word = self._wram.read(src_address + i * DataWord().size())\n            data_words.append(data_word)\n\n        mram_command = MRAMCommand(MRAMCommand.Operation.WRITE, dst_address, size)\n        mram_command.set_data_words(data_words)\n\n        assert self._mram.can_push()\n        self._mram.push(mram_command)\n        assert self._mram.can_pop()\n        assert mram_command == self._mram.pop()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/dpu.py",
    "content": "from typing import List\n\nfrom iss.dpu.dispatcher import Dispatcher\nfrom iss.dpu.dma import DMA\nfrom iss.dpu.logic import Logic\nfrom iss.dpu.scheduler import Scheduler\nfrom iss.dpu.thread import Thread\nfrom iss.dram.mram import MRAM\nfrom iss.sram.atomic import Atomic\nfrom iss.sram.iram import IRAM\nfrom iss.sram.wram import WRAM\nfrom util.config_loader import ConfigLoader\n\n\nclass DPU:\n    def __init__(self, num_threads: int):\n        assert 0 < num_threads <= ConfigLoader.max_num_tasklets()\n\n        self._threads: List[Thread] = [Thread(i) for i in range(num_threads)]\n        self._scheduler: Scheduler = Scheduler(self._threads)\n\n        self._atomic: Atomic = Atomic()\n        self._iram: IRAM = IRAM()\n        self._wram: WRAM = WRAM()\n        self._mram: MRAM = MRAM()\n        self._dma: DMA = DMA(self._atomic, self._iram, self._wram, self._mram)\n        self._dispatcher: Dispatcher = Dispatcher(self._wram)\n\n        self._logic = Logic(\n            self._scheduler, self._atomic, self._iram, self._wram, self._mram, self._dma, self._dispatcher,\n        )\n\n    def threads(self) -> List[Thread]:\n        return self._threads\n\n    def atomic(self) -> Atomic:\n        return self._atomic\n\n    def iram(self) -> IRAM:\n        return self._iram\n\n    def wram(self) -> WRAM:\n        return self._wram\n\n    def mram(self) -> MRAM:\n        return self._mram\n\n    def dma(self) -> DMA:\n        return self._dma\n\n    def is_zombie(self) -> bool:\n        for thread in self._threads:\n            if thread.state() != Thread.State.ZOMBIE:\n                return False\n        return True\n\n    def boot(self) -> None:\n        self._scheduler.boot(0)\n\n    def cycle(self) -> None:\n        self._logic.cycle()\n        self._scheduler.cycle()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/logic.py",
    "content": "import logging\nimport math\nfrom typing import Optional\n\nfrom abi.isa.flag import Flag\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.word.data_word import DataWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom converter.instruction_converter import InstructionConverter\nfrom iss.dpu.alu import ALU\nfrom iss.dpu.decoder import Decoder\nfrom iss.dpu.dispatcher import Dispatcher\nfrom iss.dpu.dma import DMA\nfrom iss.dpu.scheduler import Scheduler\nfrom iss.dpu.thread import Thread\nfrom iss.dram.mram import MRAM\nfrom iss.sram.atomic import Atomic\nfrom iss.sram.iram import IRAM\nfrom iss.sram.wram import WRAM\nfrom util.config_loader import ConfigLoader\n\n\nclass Logic:\n    def __init__(\n        self,\n        scheduler: Scheduler,\n        atomic: Atomic,\n        iram: IRAM,\n        wram: WRAM,\n        mram: MRAM,\n        dma: DMA,\n        dispatcher: Dispatcher,\n    ):\n        self._scheduler: Scheduler = scheduler\n        self._atomic: Atomic = atomic\n        self._iram: IRAM = iram\n        self._wram: WRAM = wram\n        self._mram: MRAM = mram\n        self._dma: DMA = dma\n        self._dispatcher: Dispatcher = dispatcher\n        self._logger: logging.Logger = logging.getLogger(\"iss\")\n\n        self._cur_thread: Optional[Thread] = None\n\n    def cycle(self) -> None:\n        self._cur_thread = self._scheduler.schedule()\n        if self._cur_thread is not None:\n            instruction_word = self._iram.read(self._cur_thread.register_file().read_pc())\n            instruction = Decoder.decode(instruction_word)\n\n            self._print_instruction(instruction)\n            self._execute_instruction(instruction)\n            self._print_register_file()\n\n    def _print_instruction(self, instruction: Instruction) -> None:\n        assert self._cur_thread is not None\n        self._logger.info(f\"[{self._cur_thread.id_()}] {InstructionConverter.convert_to_string(instruction)}\")\n\n    def _print_register_file(self) -> None:\n        assert self._cur_thread is not None\n        for i in range(ConfigLoader.num_gp_registers()):\n            self._logger.info(f\"r{i}: {self._cur_thread.register_file().read(GPRegister(i), Representation.SIGNED)}\")\n\n    def _execute_instruction(self, instruction: Instruction) -> None:\n        if instruction.suffix() == Suffix.RICI:\n            self._execute_rici(instruction)\n        elif instruction.suffix() == Suffix.RRI:\n            self._execute_rri(instruction)\n        elif instruction.suffix() == Suffix.RRIC:\n            self._execute_rric(instruction)\n        elif instruction.suffix() == Suffix.RRICI:\n            self._execute_rrici(instruction)\n        elif instruction.suffix() == Suffix.RRIF:\n            self._execute_rrif(instruction)\n        elif instruction.suffix() == Suffix.RRR:\n            self._execute_rrr(instruction)\n        elif instruction.suffix() == Suffix.RRRC:\n            self._execute_rrrc(instruction)\n        elif instruction.suffix() == Suffix.RRRCI:\n            self._execute_rrrci(instruction)\n        elif instruction.suffix() == Suffix.ZRI:\n            self._execute_zri(instruction)\n        elif instruction.suffix() == Suffix.ZRIC:\n            self._execute_zric(instruction)\n        elif instruction.suffix() == Suffix.ZRICI:\n            self._execute_zrici(instruction)\n        elif instruction.suffix() == Suffix.ZRIF:\n            self._execute_zrif(instruction)\n        elif instruction.suffix() == Suffix.ZRR:\n            self._execute_zrr(instruction)\n        elif instruction.suffix() == Suffix.ZRRC:\n            self._execute_zrrc(instruction)\n        elif instruction.suffix() == Suffix.ZRRCI:\n            self._execute_zrrci(instruction)\n        elif instruction.suffix() == Suffix.S_RRI:\n            self._execute_s_rri(instruction)\n        elif instruction.suffix() == Suffix.S_RRIC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRICI:\n            self._execute_s_rrici(instruction)\n        elif instruction.suffix() == Suffix.S_RRIF:\n            self._execute_s_rrif(instruction)\n        elif instruction.suffix() == Suffix.S_RRR:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRI:\n            self._execute_u_rri(instruction)\n        elif instruction.suffix() == Suffix.U_RRIC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRICI:\n            self._execute_u_rrici(instruction)\n        elif instruction.suffix() == Suffix.U_RRIF:\n            self._execute_u_rrif(instruction)\n        elif instruction.suffix() == Suffix.U_RRR:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.RR:\n            self._execute_rr(instruction)\n        elif instruction.suffix() == Suffix.RRC:\n            self._execute_rrc(instruction)\n        elif instruction.suffix() == Suffix.RRCI:\n            self._execute_rrci(instruction)\n        elif instruction.suffix() == Suffix.ZR:\n            self._execute_zr(instruction)\n        elif instruction.suffix() == Suffix.ZRC:\n            self._execute_zrc(instruction)\n        elif instruction.suffix() == Suffix.ZRCI:\n            self._execute_zrci(instruction)\n        elif instruction.suffix() == Suffix.S_RR:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RR:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.DRDICI:\n            self._execute_drdici(instruction)\n        elif instruction.suffix() == Suffix.RRRI:\n            self._execute_rrri(instruction)\n        elif instruction.suffix() == Suffix.RRRICI:\n            self._execute_rrrici(instruction)\n        elif instruction.suffix() == Suffix.ZRRI:\n            self._execute_zrri(instruction)\n        elif instruction.suffix() == Suffix.ZRRICI:\n            self._execute_zrrici(instruction)\n        elif instruction.suffix() == Suffix.S_RRRI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RRRICI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRRI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RRRICI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.RIR:\n            self._execute_rir(instruction)\n        elif instruction.suffix() == Suffix.RIRC:\n            self._execute_rirc(instruction)\n        elif instruction.suffix() == Suffix.RIRCI:\n            self._execute_rirci(instruction)\n        elif instruction.suffix() == Suffix.ZIR:\n            self._execute_zir(instruction)\n        elif instruction.suffix() == Suffix.ZIRC:\n            self._execute_zirc(instruction)\n        elif instruction.suffix() == Suffix.ZIRCI:\n            self._execute_zirci(instruction)\n        elif instruction.suffix() == Suffix.S_RIRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RIRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RIRC:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RIRCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.R:\n            self._execute_r(instruction)\n        elif instruction.suffix() == Suffix.RCI:\n            self._execute_rci(instruction)\n        elif instruction.suffix() == Suffix.Z:\n            self._execute_z(instruction)\n        elif instruction.suffix() == Suffix.ZCI:\n            self._execute_zci(instruction)\n        elif instruction.suffix() == Suffix.S_R:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.S_RCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_R:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_RCI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.CI:\n            self._execute_ci(instruction)\n        elif instruction.suffix() == Suffix.I:\n            self._execute_i(instruction)\n        elif instruction.suffix() == Suffix.DDCI:\n            self._execute_ddci(instruction)\n        elif instruction.suffix() == Suffix.ERRI:\n            self._execute_erri(instruction)\n        elif instruction.suffix() == Suffix.S_ERRI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.U_ERRI:\n            raise NotImplementedError\n        elif instruction.suffix() == Suffix.EDRI:\n            self._execute_edri(instruction)\n        elif instruction.suffix() == Suffix.ERII:\n            self._execute_erii(instruction)\n        elif instruction.suffix() == Suffix.ERIR:\n            self._execute_erir(instruction)\n        elif instruction.suffix() == Suffix.ERID:\n            self._execute_erid(instruction)\n        elif instruction.suffix() == Suffix.DMA_RRI:\n            self._execute_dma_rri(instruction)\n        else:\n            raise ValueError\n\n    def _execute_rici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RICIOpCodes\n\n        if instruction.op_code() in Instruction.AcquireRICIOpCodes:\n            self._execute_acquire_rici(instruction)\n        elif instruction.op_code() in Instruction.ReleaseRICIOpCodes:\n            self._execute_release_rici(instruction)\n        elif instruction.op_code() in Instruction.BootRICIOpCodes:\n            self._execute_boot_rici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_acquire_rici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AcquireRICIOpCodes\n        assert instruction.suffix() == Suffix.RICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(\n            instruction.ra(),\n            Representation.UNSIGNED,\n        )\n        imm = instruction.imm().value()\n        atomic_address = ALU.atomic_address_hash(ra, imm)\n\n        can_acquire = self._atomic.can_acquire(atomic_address)\n        if can_acquire:\n            self._atomic.acquire(atomic_address, self._cur_thread.id_())\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_acquire_cc(not can_acquire)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(not can_acquire, False)\n\n    def _execute_release_rici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ReleaseRICIOpCodes\n        assert instruction.suffix() == Suffix.RICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(\n            instruction.ra(),\n            Representation.UNSIGNED,\n        )\n        imm = instruction.imm().value()\n        atomic_address = ALU.atomic_address_hash(ra, imm)\n\n        can_release = self._atomic.can_release(atomic_address, self._cur_thread.id_())\n        if can_release:\n            self._atomic.release(atomic_address, self._cur_thread.id_())\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_release_cc(not can_release)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(not can_release, False)\n\n    def _execute_boot_rici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.BootRICIOpCodes\n        assert instruction.suffix() == Suffix.RICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(\n            instruction.ra(),\n            Representation.UNSIGNED,\n        )\n        imm = instruction.imm().value()\n        thread_id = ALU.atomic_address_hash(ra, imm)\n\n        self._cur_thread.register_file().clear_conditions()\n        if instruction.op_code() == OpCode.BOOT:\n            can_boot = self._scheduler.boot(thread_id)\n            self._set_boot_cc(ra, not can_boot)\n            self._set_flags(not can_boot, False)\n        elif instruction.op_code() == OpCode.RESUME:\n            can_resume = self._scheduler.awake(thread_id)\n            self._set_boot_cc(ra, not can_resume)\n            self._set_flags(not can_resume, False)\n        else:\n            raise ValueError\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRIOpCodes:\n            self._execute_add_rri(instruction)\n        elif instruction.op_code() in Instruction.AsrRRIOpCodes:\n            self._execute_asr_rri(instruction)\n        elif instruction.op_code() in Instruction.CallRRIOpCodes:\n            self._execute_call_rri(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRIOpCodes\n        assert instruction.suffix() == Suffix.RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRIOpCodes\n        assert instruction.suffix() == Suffix.RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_call_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.CallRRIOpCodes\n        assert instruction.suffix() == Suffix.RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if imm == 0:\n            callee_address, carry, _ = ALU.add(ra, imm)\n        else:\n            callee_address, carry, _ = ALU.add(ra * InstructionWord().size(), imm)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write(instruction.rc(), pc + InstructionWord().size())\n\n        self._cur_thread.register_file().write_pc(callee_address)\n\n        self._set_flags(callee_address, carry)\n\n    def _execute_rric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICOpCodes:\n            self._execute_add_rric(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICOpCodes:\n            self._execute_asr_rric(instruction)\n        elif instruction.op_code() in Instruction.SubRRICOpCodes:\n            self._execute_sub_rric(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_rric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_rric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_rric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_ext_sub_set_cc(ra, imm, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICIOpCodes:\n            self._execute_add_rrici(instruction)\n        elif instruction.op_code() in Instruction.AndRRICIOpCodes:\n            self._execute_and_rrici(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICIOpCodes:\n            self._execute_asr_rrici(instruction)\n        elif instruction.op_code() in Instruction.SubRRICIOpCodes:\n            self._execute_sub_rrici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, imm)\n        elif instruction.op_code() == OpCode.ANDN:\n            result = ALU.andn(ra, imm)\n        elif instruction.op_code() == OpCode.NAND:\n            result = ALU.nand(ra, imm)\n        elif instruction.op_code() == OpCode.NOR:\n            result = ALU.nor(ra, imm)\n        elif instruction.op_code() == OpCode.NXOR:\n            result = ALU.nxor(ra, imm)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, imm)\n        elif instruction.op_code() == OpCode.ORN:\n            result = ALU.orn(ra, imm)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, imm)\n        elif instruction.op_code() == OpCode.HASH:\n            result = ALU.hash(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_imm_shift_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrif(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.RRIF\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrr(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.RRR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, rb), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, rb), False\n        elif instruction.op_code() == OpCode.ASR:\n            result, carry = ALU.asr(ra, rb), False\n        elif instruction.op_code() == OpCode.CMPB4:\n            result, carry = ALU.cmpb4(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL:\n            result, carry = ALU.lsl(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1:\n            result, carry = ALU.lsl1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1X:\n            result, carry = ALU.lsl1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSLX:\n            result, carry = ALU.lslx(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR:\n            result, carry = ALU.lsr(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1:\n            result, carry = ALU.lsr1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1X:\n            result, carry = ALU.lsr1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSRX:\n            result, carry = ALU.lsrx(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SH:\n            result, carry = ALU.mul_sh_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result, carry = ALU.mul_sh_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result, carry = ALU.mul_sh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result, carry = ALU.mul_sh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result, carry = ALU.mul_sl_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result, carry = ALU.mul_sl_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result, carry = ALU.mul_sl_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result, carry = ALU.mul_sl_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result, carry = ALU.mul_uh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result, carry = ALU.mul_uh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result, carry = ALU.mul_ul_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result, carry = ALU.mul_ul_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, rb), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, rb), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, rb), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, rb), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.RSUB:\n            result, carry, _ = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, _ = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, rb), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, rb), False\n        elif instruction.op_code() == OpCode.CALL:\n            result, carry, _ = ALU.add(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        if instruction.op_code() == OpCode.CALL:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write(instruction.rc(), pc + InstructionWord().size())\n\n            self._cur_thread.register_file().write_pc(result)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), result)\n\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n\n        if instruction.op_code() in Instruction.AddRRRCOpCodes:\n            self._execute_add_rrrc(instruction)\n        elif instruction.op_code() in Instruction.RsubRRRCOpCodes:\n            self._execute_rsub_rrrc(instruction)\n        elif instruction.op_code() in Instruction.SubRRRCOpCodes:\n            self._execute_sub_rrrc(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_rrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRRCOpCodes\n        assert instruction.suffix() == Suffix.RRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, rb), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, rb), False\n        elif instruction.op_code() == OpCode.ASR:\n            result, carry = ALU.asr(ra, rb), False\n        elif instruction.op_code() == OpCode.CMPB4:\n            result, carry = ALU.cmpb4(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL:\n            result, carry = ALU.lsl(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1:\n            result, carry = ALU.lsl1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1X:\n            result, carry = ALU.lsl1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSLX:\n            result, carry = ALU.lslx(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR:\n            result, carry = ALU.lsr(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1:\n            result, carry = ALU.lsr1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1X:\n            result, carry = ALU.lsr1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSRX:\n            result, carry = ALU.lsrx(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SH:\n            result, carry = ALU.mul_sh_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result, carry = ALU.mul_sh_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result, carry = ALU.mul_sh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result, carry = ALU.mul_sh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result, carry = ALU.mul_sl_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result, carry = ALU.mul_sl_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result, carry = ALU.mul_sl_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result, carry = ALU.mul_sl_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result, carry = ALU.mul_uh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result, carry = ALU.mul_uh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result, carry = ALU.mul_ul_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result, carry = ALU.mul_ul_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, rb), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, rb), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, rb), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, rb), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, rb), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, rb), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rsub_rrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RsubRRRCOpCodes\n        assert instruction.suffix() == Suffix.RRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.RSUB:\n            result, carry, _ = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, _ = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_set_cc(ra, rb, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_sub_rrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRRCOpCodes\n        assert instruction.suffix() == Suffix.RRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_ext_sub_set_cc(ra, rb, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRRCIOpCodes:\n            self._execute_add_rrrci(instruction)\n        elif instruction.op_code() in Instruction.AndRRRCIOpCodes:\n            self._execute_and_rrrci(instruction)\n        elif instruction.op_code() in Instruction.AsrRRRCIOpCodes:\n            self._execute_asr_rrrci(instruction)\n        elif instruction.op_code() in Instruction.MulRRRCIOpCodes:\n            self._execute_mul_rrrci(instruction)\n        elif instruction.op_code() in Instruction.RsubRRRCIOpCodes:\n            self._execute_rsub_rrrci(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, rb)\n        elif instruction.op_code() == OpCode.ANDN:\n            result = ALU.andn(ra, rb)\n        elif instruction.op_code() == OpCode.NAND:\n            result = ALU.nand(ra, rb)\n        elif instruction.op_code() == OpCode.NOR:\n            result = ALU.nor(ra, rb)\n        elif instruction.op_code() == OpCode.NXOR:\n            result = ALU.nxor(ra, rb)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, rb)\n        elif instruction.op_code() == OpCode.ORN:\n            result = ALU.orn(ra, rb)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, rb)\n        elif instruction.op_code() == OpCode.HASH:\n            result = ALU.hash(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, rb)\n        elif instruction.op_code() == OpCode.CMPB4:\n            result = ALU.cmpb4(ra, rb)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, rb)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, rb)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, rb)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, rb)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, rb)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, rb)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, rb)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, rb)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, rb)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_shift_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_mul_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.MulRRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.MUL_SH_SH:\n            result = ALU.mul_sh_sh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result = ALU.mul_sh_sl(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result = ALU.mul_sh_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result = ALU.mul_sh_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result = ALU.mul_sl_sh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result = ALU.mul_sl_sl(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result = ALU.mul_sl_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result = ALU.mul_sl_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result = ALU.mul_uh_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result = ALU.mul_uh_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result = ALU.mul_ul_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result = ALU.mul_ul_ul(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_mul_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_rsub_rrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RsubRRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.RSUB:\n            result, carry, overflow = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, overflow = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, rb, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICIOpCodes:\n            self._execute_add_zri(instruction)\n        elif instruction.op_code() in Instruction.AsrRRIOpCodes:\n            self._execute_asr_zri(instruction)\n        elif instruction.op_code() in Instruction.CallRRIOpCodes:\n            self._execute_call_zri(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_zri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_zri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_call_zri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.CallRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if imm == 0:\n            callee_address, carry, _ = ALU.add(ra, imm)\n        else:\n            callee_address, carry, _ = ALU.add(ra * InstructionWord().size(), imm)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write_pc(callee_address)\n\n        self._set_flags(callee_address, carry)\n\n    def _execute_zric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICOpCodes:\n            self._execute_add_zric(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICOpCodes:\n            self._execute_asr_zric(instruction)\n        elif instruction.op_code() in Instruction.SubRRICOpCodes:\n            self._execute_sub_zric(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_zric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICOpCodes\n        assert instruction.suffix() == Suffix.ZRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_zric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICOpCodes\n        assert instruction.suffix() == Suffix.ZRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_zric(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICOpCodes\n        assert instruction.suffix() == Suffix.RRIC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_ext_sub_set_cc(ra, imm, result, carry, overflow)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICIOpCodes:\n            self._execute_add_zrici(instruction)\n        elif instruction.op_code() in Instruction.AndRRICIOpCodes:\n            self._execute_and_zrici(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICIOpCodes:\n            self._execute_asr_zrici(instruction)\n        elif instruction.op_code() in Instruction.SubRRICIOpCodes:\n            self._execute_sub_zrici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_zrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_zrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, imm)\n        elif instruction.op_code() == OpCode.ANDN:\n            result = ALU.andn(ra, imm)\n        elif instruction.op_code() == OpCode.NAND:\n            result = ALU.nand(ra, imm)\n        elif instruction.op_code() == OpCode.NOR:\n            result = ALU.nor(ra, imm)\n        elif instruction.op_code() == OpCode.NXOR:\n            result = ALU.nxor(ra, imm)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, imm)\n        elif instruction.op_code() == OpCode.ORN:\n            result = ALU.orn(ra, imm)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, imm)\n        elif instruction.op_code() == OpCode.HASH:\n            result = ALU.hash(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_zrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_imm_shift_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_zrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrif(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.ZRIF\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrr(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.ZRR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, rb), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, rb), False\n        elif instruction.op_code() == OpCode.ASR:\n            result, carry = ALU.asr(ra, rb), False\n        elif instruction.op_code() == OpCode.CMPB4:\n            result, carry = ALU.cmpb4(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL:\n            result, carry = ALU.lsl(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1:\n            result, carry = ALU.lsl1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1X:\n            result, carry = ALU.lsl1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSLX:\n            result, carry = ALU.lslx(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR:\n            result, carry = ALU.lsr(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1:\n            result, carry = ALU.lsr1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1X:\n            result, carry = ALU.lsr1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSRX:\n            result, carry = ALU.lsrx(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SH:\n            result, carry = ALU.mul_sh_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result, carry = ALU.mul_sh_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result, carry = ALU.mul_sh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result, carry = ALU.mul_sh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result, carry = ALU.mul_sl_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result, carry = ALU.mul_sl_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result, carry = ALU.mul_sl_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result, carry = ALU.mul_sl_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result, carry = ALU.mul_uh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result, carry = ALU.mul_uh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result, carry = ALU.mul_ul_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result, carry = ALU.mul_ul_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, rb), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, rb), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, rb), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, rb), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.RSUB:\n            result, carry, _ = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, _ = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, rb), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, rb), False\n        elif instruction.op_code() == OpCode.CALL:\n            result, carry, _ = ALU.add(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        if instruction.op_code() == OpCode.CALL:\n            self._cur_thread.register_file().write_pc(result)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRCOpCodes\n\n        if instruction.op_code() in Instruction.AddRRRCOpCodes:\n            self._execute_add_zrrc(instruction)\n        elif instruction.op_code() in Instruction.RsubRRRCOpCodes:\n            self._execute_rsub_zrrc(instruction)\n        elif instruction.op_code() in Instruction.SubRRRCOpCodes:\n            self._execute_sub_zrrc(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_zrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRRCOpCodes\n        assert instruction.suffix() == Suffix.ZRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, rb), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, rb), False\n        elif instruction.op_code() == OpCode.ASR:\n            result, carry = ALU.asr(ra, rb), False\n        elif instruction.op_code() == OpCode.CMPB4:\n            result, carry = ALU.cmpb4(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL:\n            result, carry = ALU.lsl(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1:\n            result, carry = ALU.lsl1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSL1X:\n            result, carry = ALU.lsl1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSLX:\n            result, carry = ALU.lslx(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR:\n            result, carry = ALU.lsr(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1:\n            result, carry = ALU.lsr1(ra, rb), False\n        elif instruction.op_code() == OpCode.LSR1X:\n            result, carry = ALU.lsr1x(ra, rb), False\n        elif instruction.op_code() == OpCode.LSRX:\n            result, carry = ALU.lsrx(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SH:\n            result, carry = ALU.mul_sh_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result, carry = ALU.mul_sh_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result, carry = ALU.mul_sh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result, carry = ALU.mul_sh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result, carry = ALU.mul_sl_sh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result, carry = ALU.mul_sl_sl(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result, carry = ALU.mul_sl_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result, carry = ALU.mul_sl_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result, carry = ALU.mul_uh_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result, carry = ALU.mul_uh_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result, carry = ALU.mul_ul_uh(ra, rb), False\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result, carry = ALU.mul_ul_ul(ra, rb), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, rb), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, rb), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, rb), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, rb), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, rb), False\n        elif instruction.op_code() == OpCode.ROL:\n            result, carry = ALU.rol(ra, rb), False\n        elif instruction.op_code() == OpCode.ROR:\n            result, carry = ALU.ror(ra, rb), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, rb), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, rb), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rsub_zrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RsubRRRCOpCodes\n        assert instruction.suffix() == Suffix.ZRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.RSUB:\n            result, carry, _ = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, _ = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_set_cc(ra, rb, result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_sub_zrrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRRCOpCodes\n        assert instruction.suffix() == Suffix.ZRRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_ext_sub_set_cc(ra, rb, result, carry, overflow)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRCIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRRCIOpCodes:\n            self._execute_add_zrrci(instruction)\n        elif instruction.op_code() in Instruction.AndRRRCIOpCodes:\n            self._execute_and_zrrci(instruction)\n        elif instruction.op_code() in Instruction.AsrRRRCIOpCodes:\n            self._execute_asr_zrrci(instruction)\n        elif instruction.op_code() in Instruction.MulRRRCIOpCodes:\n            self._execute_mul_zrrci(instruction)\n        elif instruction.op_code() in Instruction.RsubRRRCIOpCodes:\n            self._execute_rsub_zrrci(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, rb)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, rb)\n        elif instruction.op_code() == OpCode.ANDN:\n            result = ALU.andn(ra, rb)\n        elif instruction.op_code() == OpCode.NAND:\n            result = ALU.nand(ra, rb)\n        elif instruction.op_code() == OpCode.NOR:\n            result = ALU.nor(ra, rb)\n        elif instruction.op_code() == OpCode.NXOR:\n            result = ALU.nxor(ra, rb)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, rb)\n        elif instruction.op_code() == OpCode.ORN:\n            result = ALU.orn(ra, rb)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, rb)\n        elif instruction.op_code() == OpCode.HASH:\n            result = ALU.hash(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, rb)\n        elif instruction.op_code() == OpCode.CMPB4:\n            result = ALU.cmpb4(ra, rb)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, rb)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, rb)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, rb)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, rb)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, rb)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, rb)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, rb)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, rb)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, rb)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_shift_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_mul_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.MulRRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.MUL_SH_SH:\n            result = ALU.mul_sh_sh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_SL:\n            result = ALU.mul_sh_sl(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_UH:\n            result = ALU.mul_sh_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SH_UL:\n            result = ALU.mul_sh_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_SH:\n            result = ALU.mul_sl_sh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_SL:\n            result = ALU.mul_sl_sl(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_UH:\n            result = ALU.mul_sl_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_SL_UL:\n            result = ALU.mul_sl_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UH_UH:\n            result = ALU.mul_uh_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UH_UL:\n            result = ALU.mul_uh_ul(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UL_UH:\n            result = ALU.mul_ul_uh(ra, rb)\n        elif instruction.op_code() == OpCode.MUL_UL_UL:\n            result = ALU.mul_ul_ul(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_mul_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_rsub_zrrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RsubRRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.RSUB:\n            result, carry, overflow = ALU.sub(rb, ra)\n        elif instruction.op_code() == OpCode.RSUBC:\n            result, carry, _ = ALU.subc(rb, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, rb)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, rb, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, rb, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_s_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRIOpCodes:\n            self._execute_add_s_rri(instruction)\n        elif instruction.op_code() in Instruction.AsrRRIOpCodes:\n            self._execute_asr_s_rri(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_s_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_s_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRIOpCodes\n        assert instruction.suffix() == Suffix.S_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_s_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICIOpCodes:\n            self._execute_add_s_rrici(instruction)\n        elif instruction.op_code() in Instruction.AndRRICIOpCodes:\n            self._execute_and_s_rrici(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICIOpCodes:\n            self._execute_asr_s_rrici(instruction)\n        elif instruction.op_code() in Instruction.SubRRICIOpCodes:\n            self._execute_sub_s_rrici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_s_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_s_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, imm)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, imm)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_s_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_imm_shift_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_s_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICIOpCodes\n        assert instruction.suffix() == Suffix.S_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_s_rrif(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.S_RRIF\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.signed_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_u_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRIOpCodes:\n            self._execute_add_u_rri(instruction)\n        elif instruction.op_code() in Instruction.AsrRRIOpCodes:\n            self._execute_asr_u_rri(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_u_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRIOpCodes\n        assert instruction.suffix() == Suffix.U_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_asr_u_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRIOpCodes\n        assert instruction.suffix() == Suffix.U_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_u_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRICIOpCodes\n\n        if instruction.op_code() in Instruction.AddRRICIOpCodes:\n            self._execute_add_u_rrici(instruction)\n        elif instruction.op_code() in Instruction.AndRRICIOpCodes:\n            self._execute_and_u_rrici(instruction)\n        elif instruction.op_code() in Instruction.AsrRRICIOpCodes:\n            self._execute_asr_u_rrici(instruction)\n        elif instruction.op_code() in Instruction.SubRRICIOpCodes:\n            self._execute_sub_u_rrici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_add_u_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AddRRICIOpCodes\n        assert instruction.suffix() == Suffix.U_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, overflow = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, overflow = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_add_nz_cc(ra, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_and_u_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AndRRICIOpCodes\n        assert instruction.suffix() == Suffix.U_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.AND:\n            result = ALU.and_(ra, imm)\n        elif instruction.op_code() == OpCode.OR:\n            result = ALU.or_(ra, imm)\n        elif instruction.op_code() == OpCode.XOR:\n            result = ALU.xor(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_asr_u_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.AsrRRICIOpCodes\n        assert instruction.suffix() == Suffix.U_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ASR:\n            result = ALU.asr(ra, imm)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1:\n            result = ALU.lsl1(ra, imm)\n        elif instruction.op_code() == OpCode.LSL1X:\n            result = ALU.lsl1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSLX:\n            result = ALU.lslx(ra, imm)\n        elif instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1:\n            result = ALU.lsr1(ra, imm)\n        elif instruction.op_code() == OpCode.LSR1X:\n            result = ALU.lsr1x(ra, imm)\n        elif instruction.op_code() == OpCode.LSRX:\n            result = ALU.lsrx(ra, imm)\n        elif instruction.op_code() == OpCode.ROL:\n            result = ALU.rol(ra, imm)\n        elif instruction.op_code() == OpCode.ROR:\n            result = ALU.ror(ra, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_imm_shift_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_sub_u_rrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.SubRRICIOpCodes\n        assert instruction.suffix() == Suffix.U_RRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_u_rrif(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRIFOpCodes\n        assert instruction.suffix() == Suffix.U_RRIF\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.ADD:\n            result, carry, _ = ALU.add(ra, imm)\n        elif instruction.op_code() == OpCode.ADDC:\n            result, carry, _ = ALU.addc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.AND:\n            result, carry = ALU.and_(ra, imm), False\n        elif instruction.op_code() == OpCode.ANDN:\n            result, carry = ALU.andn(ra, imm), False\n        elif instruction.op_code() == OpCode.NAND:\n            result, carry = ALU.nand(ra, imm), False\n        elif instruction.op_code() == OpCode.NOR:\n            result, carry = ALU.nor(ra, imm), False\n        elif instruction.op_code() == OpCode.NXOR:\n            result, carry = ALU.nxor(ra, imm), False\n        elif instruction.op_code() == OpCode.OR:\n            result, carry = ALU.or_(ra, imm), False\n        elif instruction.op_code() == OpCode.ORN:\n            result, carry = ALU.orn(ra, imm), False\n        elif instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(ra, imm)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(ra, imm, self._cur_thread.register_file().flag(Flag.CARRY))\n        elif instruction.op_code() == OpCode.XOR:\n            result, carry = ALU.xor(ra, imm), False\n        elif instruction.op_code() == OpCode.HASH:\n            result, carry = ALU.hash(ra, imm), False\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_u_rrr(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRROpCodes\n        assert instruction.suffix() == Suffix.U_RRR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.LSR:\n            result = ALU.lsr(ra, rb)\n        elif instruction.op_code() == OpCode.LSL:\n            result = ALU.lsl(ra, rb)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), ALU.unsigned_extension(result))\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_rr(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.RR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_rrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.RRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_rrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n\n        if instruction.op_code() in Instruction.CaoRRCIOpCodes:\n            self._execute_cao_rrci(instruction)\n        elif instruction.op_code() in Instruction.ExtsbRRCIOpCodes:\n            self._execute_extsb_rrci(instruction)\n        elif instruction.op_code() in Instruction.TimeCfgRRCIOpCodes:\n            self._execute_time_cfg_rrci(instruction)\n        else:\n            raise ValueError\n\n    def _execute_cao_rrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.CaoRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_count_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_extsb_rrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ExtsbRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_time_cfg_rrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.TimeCfgRRCIOpCodes\n        assert instruction.suffix() == Suffix.RRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.TIME_CFG:\n            result = ALU.sats(ra)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_zr(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RROpCodes\n        assert instruction.suffix() == Suffix.ZR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_zrc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRCOpCodes\n        assert instruction.suffix() == Suffix.ZRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_set_cc(result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_zrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRCIOpCodes\n\n        if instruction.op_code() in Instruction.CaoRRCIOpCodes:\n            self._execute_cao_rrci(instruction)\n        elif instruction.op_code() in Instruction.ExtsbRRCIOpCodes:\n            self._execute_extsb_rrci(instruction)\n        elif instruction.op_code() in Instruction.TimeCfgRRCIOpCodes:\n            self._execute_time_cfg_rrci(instruction)\n        else:\n            raise ValueError\n\n    def _execute_cao_zrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.CaoRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.CAO:\n            result = ALU.cao(ra)\n        elif instruction.op_code() == OpCode.CLO:\n            result = ALU.clo(ra)\n        elif instruction.op_code() == OpCode.CLS:\n            result = ALU.cls(ra)\n        elif instruction.op_code() == OpCode.CLZ:\n            result = ALU.clz(ra)\n        elif instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        elif instruction.op_code() == OpCode.TIME_CFG:\n            raise NotImplementedError\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_count_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_extsb_zrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ExtsbRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.EXTSB:\n            result = ALU.extsb(ra)\n        elif instruction.op_code() == OpCode.EXTSH:\n            result = ALU.extsh(ra)\n        elif instruction.op_code() == OpCode.EXTUH:\n            result = ALU.extuh(ra)\n        elif instruction.op_code() == OpCode.SATS:\n            result = ALU.sats(ra)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_log_nz_cc(ra, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_time_cfg_zrci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.TimeCfgRRCIOpCodes\n        assert instruction.suffix() == Suffix.ZRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n\n        if instruction.op_code() == OpCode.TIME_CFG:\n            result = ALU.sats(ra)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_true_cc()\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_drdici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.DRDICIOpCodes\n        assert instruction.suffix() == Suffix.DRDICI\n        assert self._cur_thread is not None\n\n        if instruction.op_code() == OpCode.DIV_STEP:\n            self._execute_div_step_drdici(instruction)\n        elif instruction.op_code() == OpCode.MUL_STEP:\n            self._execute_mul_step_drdici(instruction)\n        else:\n            raise ValueError\n\n    def _execute_div_step_drdici(self, instruction: Instruction) -> None:\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        dbe = self._cur_thread.register_file().read(instruction.db().even_register(), Representation.SIGNED)\n        dbo = self._cur_thread.register_file().read(instruction.db().odd_register(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        dbo_data_word = DataWord()\n        dbo_data_word.set_value(dbo)\n\n        ra_shift_data_word = DataWord()\n        ra_shift_data_word.set_value(ALU.lsl(ra, imm))\n\n        result, _, _ = ALU.sub(dbo, ALU.lsl(ra, imm))\n\n        if dbo_data_word.value(Representation.UNSIGNED) >= ra_shift_data_word.value(Representation.UNSIGNED):\n            dce = ALU.lsl1(dbe, 1)\n            dco = result\n        else:\n            dce = ALU.lsl(dbe, 1)\n            dco = self._cur_thread.register_file().read(instruction.dc().odd_register(), Representation.SIGNED)\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_div_cc(ra)\n\n        self._cur_thread.register_file().write(instruction.dc().even_register(), dce)\n        self._cur_thread.register_file().write(instruction.dc().odd_register(), dco)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, False)\n\n    def _execute_mul_step_drdici(self, instruction: Instruction) -> None:\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        dbe = self._cur_thread.register_file().read(instruction.db().even_register(), Representation.SIGNED)\n        dbo = self._cur_thread.register_file().read(instruction.db().odd_register(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        result1 = ALU.lsr(dbe, 1)\n        result2, _, _ = ALU.sub(ALU.and_(dbe, 1), 1)\n\n        if result2 == 0:\n            dco, _, _ = ALU.add(dbo, ALU.lsl(ra, imm))\n        else:\n            dco = self._cur_thread.register_file().read(instruction.dc().odd_register(), Representation.SIGNED)\n        dce = ALU.lsr(dbe, 1)\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_boot_cc(ra, result1)\n\n        self._cur_thread.register_file().write(instruction.dc().even_register(), dce)\n        self._cur_thread.register_file().write(instruction.dc().odd_register(), dco)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result1, False)\n\n    def _execute_rrri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.RRRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.LSL_ADD:\n            result, carry, _ = ALU.lsl_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSL_SUB:\n            result, carry, _ = ALU.lsl_sub(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSR_ADD:\n            result, carry, _ = ALU.lsr_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.ROL_ADD:\n            result, carry, _ = ALU.rol_add(ra, rb, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rrrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.RRRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.LSL_ADD:\n            result, carry, _ = ALU.lsl_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSL_SUB:\n            result, carry, _ = ALU.lsl_sub(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSR_ADD:\n            result, carry, _ = ALU.lsr_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.ROL_ADD:\n            result, carry, _ = ALU.rol_add(ra, rb, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_div_nz_cc(ra)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRIOpCodes\n        assert instruction.suffix() == Suffix.ZRRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.LSL_ADD:\n            result, carry, _ = ALU.lsl_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSL_SUB:\n            result, carry, _ = ALU.lsl_sub(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSR_ADD:\n            result, carry, _ = ALU.lsr_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.ROL_ADD:\n            result, carry, _ = ALU.rol_add(ra, rb, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zrrici(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RRRICIOpCodes\n        assert instruction.suffix() == Suffix.ZRRICI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.LSL_ADD:\n            result, carry, _ = ALU.lsl_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSL_SUB:\n            result, carry, _ = ALU.lsl_sub(ra, rb, imm)\n        elif instruction.op_code() == OpCode.LSR_ADD:\n            result, carry, _ = ALU.lsr_add(ra, rb, imm)\n        elif instruction.op_code() == OpCode.ROL_ADD:\n            result, carry, _ = ALU.rol_add(ra, rb, imm)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_div_nz_cc(ra)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rir(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.RIR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rirc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.RIRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_set_cc(ra, imm, result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            self._cur_thread.register_file().write(instruction.rc(), 1)\n        else:\n            self._cur_thread.register_file().write(instruction.rc(), 0)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_rirci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.RIRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zir(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIROpCodes\n        assert instruction.suffix() == Suffix.ZIR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zirc(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIRCOpCodes\n        assert instruction.suffix() == Suffix.ZIRC\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, _ = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, _ = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_set_cc(ra, imm, result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_zirci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.RIRCIOpCodes\n        assert instruction.suffix() == Suffix.ZIRCI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        if instruction.op_code() == OpCode.SUB:\n            result, carry, overflow = ALU.sub(imm, ra)\n        elif instruction.op_code() == OpCode.SUBC:\n            result, carry, overflow = ALU.subc(imm, ra, self._cur_thread.register_file().flag(Flag.CARRY))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n        self._set_sub_nz_cc(ra, imm, result, carry, overflow)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n        self._set_flags(result, carry)\n\n    def _execute_r(self, instruction: Instruction) -> None:\n        raise NotImplementedError\n\n    def _execute_rci(self, instruction: Instruction) -> None:\n        raise NotImplementedError\n\n    def _execute_z(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ROpCodes or instruction.op_code() == OpCode.NOP\n        assert instruction.suffix() == Suffix.Z\n        assert self._cur_thread is not None\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_zci(self, instruction: Instruction) -> None:\n        raise NotImplementedError\n\n    def _execute_ci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.CIOpCodes\n        assert instruction.suffix() == Suffix.CI\n        assert self._cur_thread is not None\n\n        assert instruction.op_code() == OpCode.STOP\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n\n            self._cur_thread.set_thread_state(Thread.State.SLEEP)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n            self._cur_thread.set_thread_state(Thread.State.SLEEP)\n\n    def _execute_i(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.IOpCodes\n        assert instruction.suffix() == Suffix.I\n        assert self._cur_thread is not None\n\n        assert instruction.op_code() == OpCode.FAULT\n\n        # TODO(bongjoon.hyun@gmail.com): this behavior must be simulated by a host CPU thread\n        raise ValueError\n\n    def _execute_ddci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.DDCIOpCodes\n        assert instruction.suffix() == Suffix.DDCI\n        assert self._cur_thread is not None\n\n        if instruction.op_code() == OpCode.MOVD:\n            self._execute_movd_ddci(instruction)\n        elif instruction.op_code() == OpCode.SWAPD:\n            self._execute_swapd_ddci(instruction)\n        else:\n            raise ValueError\n\n    def _execute_movd_ddci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() == OpCode.MOVD\n        assert instruction.suffix() == Suffix.DDCI\n        assert self._cur_thread is not None\n\n        dbe = self._cur_thread.register_file().read(instruction.db().even_register(), Representation.SIGNED)\n        dbo = self._cur_thread.register_file().read(instruction.db().odd_register(), Representation.SIGNED)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc().even_register(), dbe)\n        self._cur_thread.register_file().write(instruction.dc().odd_register(), dbo)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_swapd_ddci(self, instruction: Instruction) -> None:\n        assert instruction.op_code() == OpCode.SWAPD\n        assert instruction.suffix() == Suffix.DDCI\n        assert self._cur_thread is not None\n\n        dbe = self._cur_thread.register_file().read(instruction.db().even_register(), Representation.SIGNED)\n        dbo = self._cur_thread.register_file().read(instruction.db().odd_register(), Representation.SIGNED)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc().even_register(), dbo)\n        self._cur_thread.register_file().write(instruction.dc().odd_register(), dbe)\n\n        if self._cur_thread.register_file().condition(instruction.condition()):\n            pc = instruction.pc().value()\n            self._cur_thread.register_file().write_pc(pc)\n        else:\n            pc = self._cur_thread.register_file().read_pc()\n            self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_erri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ERRIOpCodes\n        assert instruction.suffix() == Suffix.ERRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        off = instruction.off().value()\n\n        address, _, _ = ALU.add(ra, off)\n\n        if instruction.op_code() == OpCode.LBS:\n            result = self._dispatcher.lbs(address)\n        elif instruction.op_code() == OpCode.LBU:\n            result = self._dispatcher.lbu(address)\n        elif instruction.op_code() == OpCode.LHS:\n            result = self._dispatcher.lhs(address)\n        elif instruction.op_code() == OpCode.LHU:\n            result = self._dispatcher.lhu(address)\n        elif instruction.op_code() == OpCode.LW:\n            result = self._dispatcher.lw(address)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.rc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_edri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.EDRIOpCodes\n        assert instruction.suffix() == Suffix.EDRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        off = instruction.off().value()\n\n        address, _, _ = ALU.add(ra, off)\n\n        if instruction.op_code() == OpCode.LD:\n            result = self._dispatcher.ld(address)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        self._cur_thread.register_file().write(instruction.dc(), result)\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_erii(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ERIIOpCodes\n        assert instruction.suffix() == Suffix.ERII\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        off = instruction.off().value()\n        imm = instruction.imm().value()\n\n        address, _, _ = ALU.add(ra, off)\n\n        if instruction.op_code() == OpCode.SB:\n            self._dispatcher.sb(address, imm)\n        elif instruction.op_code() == OpCode.SB_ID:\n            id_ = self._cur_thread.id_()\n            self._dispatcher.sb(address, ALU.or_(id_, imm))\n        elif instruction.op_code() == OpCode.SH:\n            self._dispatcher.sh(address, imm)\n        elif instruction.op_code() == OpCode.SH_ID:\n            id_ = self._cur_thread.id_()\n            self._dispatcher.sh(address, ALU.or_(id_, imm))\n        elif instruction.op_code() == OpCode.SW:\n            self._dispatcher.sw(address, imm)\n        elif instruction.op_code() == OpCode.SW_ID:\n            id_ = self._cur_thread.id_()\n            self._dispatcher.sw(address, ALU.or_(id_, imm))\n        elif instruction.op_code() == OpCode.SD:\n            self._dispatcher.sd(address, imm)\n        elif instruction.op_code() == OpCode.SD_ID:\n            id_ = self._cur_thread.id_()\n            self._dispatcher.sd(address, ALU.or_(id_, imm))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_erir(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ERIROpCodes\n        assert instruction.suffix() == Suffix.ERIR\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        off = instruction.off().value()\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        rb_word = DataWord()\n        rb_word.set_value(rb)\n\n        address, _, _ = ALU.add(ra, off)\n\n        if instruction.op_code() == OpCode.SB:\n            self._dispatcher.sb(address, rb_word.bit_slice(Representation.UNSIGNED, 0, 8))\n        elif instruction.op_code() == OpCode.SH:\n            self._dispatcher.sh(address, rb_word.bit_slice(Representation.UNSIGNED, 0, 16))\n        elif instruction.op_code() == OpCode.SW:\n            self._dispatcher.sw(address, rb_word.bit_slice(Representation.UNSIGNED, 0, 32))\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_erid(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.ERIDOpCodes\n        assert instruction.suffix() == Suffix.ERID\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        off = instruction.off().value()\n        db = self._cur_thread.register_file().read(instruction.db(), Representation.SIGNED)\n\n        address, _, _ = ALU.add(ra, off)\n\n        if instruction.op_code() == OpCode.SD:\n            self._dispatcher.sd(address, db)\n        else:\n            raise ValueError\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_dma_rri(self, instruction: Instruction) -> None:\n        assert instruction.op_code() in Instruction.DMARRIOpCodes\n\n        if instruction.op_code() == OpCode.LDMA:\n            self._execute_ldma(instruction)\n        elif instruction.op_code() == OpCode.LDMAI:\n            self._execute_ldmai(instruction)\n        elif instruction.op_code() == OpCode.SDMA:\n            self._execute_sdma(instruction)\n        else:\n            raise ValueError\n\n    def _execute_ldma(self, instruction: Instruction) -> None:\n        assert instruction.op_code() == OpCode.LDMA\n        assert instruction.suffix() == Suffix.DMA_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        wram_end_address = ConfigLoader.wram_offset() + ConfigLoader.wram_size()\n        wram_end_address_width = math.floor(math.log2(wram_end_address)) + 1\n        wram_mask = 2**wram_end_address_width - 1\n        wram_address = ALU.and_(ra, wram_mask)\n\n        mram_end_address = ConfigLoader.mram_offset() + ConfigLoader.mram_size()\n        mram_end_address_width = math.floor(math.log2(mram_end_address)) + 1\n        mram_mask = 2**mram_end_address_width - 1\n        mram_address = ALU.and_(rb, mram_mask)\n\n        min_access_granularity = ConfigLoader.min_access_granularity()\n\n        num_bytes = (1 + ALU.and_(imm + ALU.and_(ALU.lsr(ra, 24), 255), 255)) * min_access_granularity\n\n        self._dma.dpu_dma_transfer_from_mram_to_wram(mram_address, wram_address, num_bytes)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _execute_ldmai(self, instruction: Instruction) -> None:\n        raise NotImplementedError\n\n    def _execute_sdma(self, instruction: Instruction) -> None:\n        assert instruction.op_code() == OpCode.SDMA\n        assert instruction.suffix() == Suffix.DMA_RRI\n        assert self._cur_thread is not None\n\n        ra = self._cur_thread.register_file().read(instruction.ra(), Representation.SIGNED)\n        rb = self._cur_thread.register_file().read(instruction.rb(), Representation.SIGNED)\n        imm = instruction.imm().value()\n\n        wram_end_address = ConfigLoader.wram_offset() + ConfigLoader.wram_size()\n        wram_end_address_width = math.floor(math.log2(wram_end_address)) + 1\n        wram_mask = 2**wram_end_address_width - 1\n        wram_address = ALU.and_(ra, wram_mask)\n\n        mram_end_address = ConfigLoader.mram_offset() + ConfigLoader.mram_size()\n        mram_end_address_width = math.floor(math.log2(mram_end_address)) + 1\n        mram_mask = 2**mram_end_address_width - 1\n        mram_address = ALU.and_(rb, mram_mask)\n\n        min_access_granularity = ConfigLoader.min_access_granularity()\n\n        num_bytes = (1 + ALU.and_(imm + ALU.and_(ALU.lsr(ra, 24), 255), 255)) * min_access_granularity\n\n        self._dma.dpu_dma_transfer_from_wram_to_mram(wram_address, mram_address, num_bytes)\n\n        self._cur_thread.register_file().clear_conditions()\n\n        pc = self._cur_thread.register_file().read_pc()\n        self._cur_thread.register_file().write_pc(pc + InstructionWord().size())\n\n    def _set_flags(self, result: int, carry: bool) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_flag(Flag.ZERO)\n        else:\n            self._cur_thread.register_file().clear_flag(Flag.ZERO)\n\n        if carry:\n            self._cur_thread.register_file().set_flag(Flag.CARRY)\n        else:\n            self._cur_thread.register_file().clear_flag(Flag.CARRY)\n\n    def _set_acquire_cc(self, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n    def _set_add_nz_cc(self, operand1: int, result: int, carry: bool, overflow: bool) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if carry:\n            self._cur_thread.register_file().set_condition(Condition.C)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NC)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if overflow:\n            self._cur_thread.register_file().set_condition(Condition.OV)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NOV)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NOV)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        result_data_word = DataWord()\n        result_data_word.set_value(result)\n\n        if result_data_word.bit(6):\n            self._cur_thread.register_file().set_condition(Condition.NC5)\n        if result_data_word.bit(7):\n            self._cur_thread.register_file().set_condition(Condition.NC6)\n        if result_data_word.bit(8):\n            self._cur_thread.register_file().set_condition(Condition.NC7)\n        if result_data_word.bit(9):\n            self._cur_thread.register_file().set_condition(Condition.NC8)\n        if result_data_word.bit(10):\n            self._cur_thread.register_file().set_condition(Condition.NC9)\n        if result_data_word.bit(11):\n            self._cur_thread.register_file().set_condition(Condition.NC10)\n        if result_data_word.bit(12):\n            self._cur_thread.register_file().set_condition(Condition.NC11)\n        if result_data_word.bit(13):\n            self._cur_thread.register_file().set_condition(Condition.NC12)\n        if result_data_word.bit(14):\n            self._cur_thread.register_file().set_condition(Condition.NC13)\n        if result_data_word.bit(15):\n            self._cur_thread.register_file().set_condition(Condition.NC14)\n\n    def _set_boot_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n    def _set_count_nz_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        if result == DataWord().width():\n            self._cur_thread.register_file().set_condition(Condition.MAX)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NMAX)\n\n    def _set_div_cc(self, operand1: int) -> None:\n        assert self._cur_thread is not None\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n    def _set_div_nz_cc(self, operand1: int) -> None:\n        assert self._cur_thread is not None\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n    def _set_ext_sub_set_cc(self, operand1: int, operand2: int, result: int, carry: bool, overflow: bool) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if carry:\n            self._cur_thread.register_file().set_condition(Condition.C)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NC)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if overflow:\n            self._cur_thread.register_file().set_condition(Condition.OV)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NOV)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == operand2:\n            self._cur_thread.register_file().set_condition(Condition.EQ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NEQ)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        if data_word1.value(Representation.UNSIGNED) < data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LTU)\n\n        if data_word1.value(Representation.UNSIGNED) <= data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LEU)\n\n        if data_word1.value(Representation.UNSIGNED) > data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GTU)\n\n        if data_word1.value(Representation.UNSIGNED) >= data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GEU)\n\n        if data_word1.value(Representation.SIGNED) < data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LTS)\n\n        if data_word1.value(Representation.SIGNED) <= data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LES)\n\n        if data_word1.value(Representation.SIGNED) > data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GTS)\n\n        if data_word1.value(Representation.SIGNED) >= data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GES)\n\n        if carry or self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XLEU)\n\n        if carry and not self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XGTU)\n\n        if self._cur_thread.register_file().flag(Flag.ZERO) and (result < 0 or overflow):\n            self._cur_thread.register_file().set_condition(Condition.XLES)\n\n        if not self._cur_thread.register_file().flag(Flag.ZERO) and (result >= 0 or overflow):\n            self._cur_thread.register_file().set_condition(Condition.XGTS)\n\n    def _set_imm_shift_nz_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if result % 2 == 0:\n            self._cur_thread.register_file().set_condition(Condition.E)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.O)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 % 2 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SE)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SO)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n    def _set_log_nz_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n    def _set_log_set_cc(self, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n    def _set_mul_nz_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        if result < 256:\n            self._cur_thread.register_file().set_condition(Condition.SMALL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.LARGE)\n\n    def _set_release_cc(self, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result != 0:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n    def _set_shift_nz_cc(self, operand1: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if result % 2 == 0:\n            self._cur_thread.register_file().set_condition(Condition.E)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.O)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SNZ)\n\n        if operand1 % 2 == 0:\n            self._cur_thread.register_file().set_condition(Condition.SE)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SO)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        if data_word1.bit(5):\n            self._cur_thread.register_file().set_condition(Condition.SH32)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NSH32)\n\n    def _set_sub_nz_cc(self, operand1: int, operand2: int, result: int, carry: bool, overflow: bool) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if carry:\n            self._cur_thread.register_file().set_condition(Condition.C)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NC)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if overflow:\n            self._cur_thread.register_file().set_condition(Condition.OV)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NOV)\n\n        if result >= 0:\n            self._cur_thread.register_file().set_condition(Condition.PL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.MI)\n\n        if operand1 == operand2:\n            self._cur_thread.register_file().set_condition(Condition.EQ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NEQ)\n\n        if operand1 >= 0:\n            self._cur_thread.register_file().set_condition(Condition.SPL)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.SMI)\n\n        data_word1 = DataWord()\n        data_word1.set_value(operand1)\n\n        data_word2 = DataWord()\n        data_word2.set_value(operand2)\n\n        if data_word1.value(Representation.UNSIGNED) < data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LTU)\n\n        if data_word1.value(Representation.UNSIGNED) <= data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LEU)\n\n        if data_word1.value(Representation.UNSIGNED) > data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GTU)\n\n        if data_word1.value(Representation.UNSIGNED) >= data_word2.value(Representation.UNSIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GEU)\n\n        if data_word1.value(Representation.SIGNED) < data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LTS)\n\n        if data_word1.value(Representation.SIGNED) <= data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.LES)\n\n        if data_word1.value(Representation.SIGNED) > data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GTS)\n\n        if data_word1.value(Representation.SIGNED) >= data_word2.value(Representation.SIGNED):\n            self._cur_thread.register_file().set_condition(Condition.GES)\n\n        if carry or self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XLEU)\n\n        if carry and not self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XGTU)\n\n        if self._cur_thread.register_file().flag(Flag.ZERO) and (result < 0 or overflow):\n            self._cur_thread.register_file().set_condition(Condition.XLES)\n\n        if not self._cur_thread.register_file().flag(Flag.ZERO) and (result >= 0 or overflow):\n            self._cur_thread.register_file().set_condition(Condition.XGTS)\n\n    def _set_sub_set_cc(self, operand1: int, operand2: int, result: int) -> None:\n        assert self._cur_thread is not None\n\n        if result == 0:\n            self._cur_thread.register_file().set_condition(Condition.Z)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NZ)\n\n        if result == 0 and self._cur_thread.register_file().flag(Flag.ZERO):\n            self._cur_thread.register_file().set_condition(Condition.XZ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.XNZ)\n\n        if operand1 == operand2:\n            self._cur_thread.register_file().set_condition(Condition.EQ)\n        else:\n            self._cur_thread.register_file().set_condition(Condition.NEQ)\n\n    def _set_true_cc(self):\n        pass\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/scheduler.py",
    "content": "from queue import Queue\nfrom typing import List, Optional\n\nfrom iss.dpu.thread import Thread\n\n\nclass Scheduler:\n    def __init__(self, threads: List[Thread]):\n        self._threads = threads\n        self._queue: Queue[Thread] = self._init_queue()\n\n    def schedule(self) -> Optional[Thread]:\n        for _ in range(len(self._threads)):\n            thread = self._queue.get()\n            self._queue.put(thread)\n\n            if thread.state() == Thread.State.RUNNABLE:\n                return thread\n        return None\n\n    def boot(self, id_: int) -> bool:\n        if id_ < len(self._threads):\n            assert self._threads[id_].id_() == id_\n\n            if self._threads[id_].state() == Thread.State.EMBRYO:\n                self._threads[id_].set_thread_state(Thread.State.RUNNABLE)\n                return True\n            elif self._threads[id_].state() == Thread.State.ZOMBIE:\n                self._threads[id_].set_thread_state(Thread.State.RUNNABLE)\n                return True\n            else:\n                raise ValueError\n        else:\n            return True\n\n    def awake(self, id_: int) -> bool:\n        assert self._threads[id_].id_() == id_\n\n        if self._threads[id_].state() == Thread.State.RUNNABLE:\n            return True\n        elif self._threads[id_].state() == Thread.State.SLEEP:\n            self._threads[id_].set_thread_state(Thread.State.RUNNABLE)\n            return True\n        else:\n            raise ValueError\n\n    def cycle(self) -> None:\n        assert self._queue.full()\n\n    def _init_queue(self) -> Queue[Thread]:\n        queue: Queue[Thread] = Queue(len(self._threads))\n        for thread in self._threads:\n            queue.put(thread)\n\n        return queue\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dpu/thread.py",
    "content": "from enum import Enum, auto\n\nfrom iss.register.register_file import RegisterFile\n\n\nclass Thread:\n    class State(Enum):\n        EMBRYO = 0\n        RUNNABLE = auto()\n        SLEEP = auto()\n        ZOMBIE = auto()\n\n    def __init__(self, id_: int):\n        self._id: int = id_\n        self._state: Thread.State = Thread.State.EMBRYO\n        self._register_file: RegisterFile = RegisterFile(id_)\n        self._issue_cycles: int = 0\n\n    def id_(self) -> int:\n        return self._id\n\n    def state(self) -> State:\n        return self._state\n\n    def set_thread_state(self, thread_state: State) -> None:\n        self._state = thread_state\n\n    def register_file(self) -> RegisterFile:\n        return self._register_file\n\n    def issue_cycles(self) -> int:\n        return self._issue_cycles\n\n    def increment_issue_cycles(self) -> None:\n        self._issue_cycles += 1\n\n    def reset_issue_cycles(self) -> None:\n        self._issue_cycles = 0\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dram/mram.py",
    "content": "from queue import Queue\nfrom typing import List\n\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom iss.dram.mram_command import MRAMCommand\nfrom util.config_loader import ConfigLoader\n\n\nclass MRAM:\n    def __init__(self):\n        self._address: DataAddressWord = DataAddressWord()\n        self._address.set_value(ConfigLoader.mram_offset())\n\n        self._data_words: List[DataWord] = [DataWord() for _ in range(ConfigLoader.mram_size() // DataWord().size())]\n        self._mram_command_queue: Queue[MRAMCommand] = Queue(-1)\n\n        assert ConfigLoader.min_access_granularity() % DataWord().size() == 0\n        self._num_min_access_data_words = ConfigLoader.min_access_granularity() // DataWord().size()\n\n    def address(self) -> int:\n        return self._address.value(Representation.UNSIGNED)\n\n    def can_push(self) -> bool:\n        return True\n\n    def push(self, mram_command: MRAMCommand) -> None:\n        self._mram_command_queue.put(mram_command)\n\n    def can_pop(self) -> bool:\n        return not self._mram_command_queue.empty()\n\n    def pop(self) -> MRAMCommand:\n        mram_command = self._mram_command_queue.get()\n        if mram_command.operation() == MRAMCommand.Operation.READ:\n            if mram_command.address() % DataWord().size() == 0:\n                self._aligned_read(mram_command)\n            else:\n                self._unaligned_read(mram_command)\n        elif mram_command.operation() == MRAMCommand.Operation.WRITE:\n            if mram_command.address() % DataWord().size() == 0:\n                self._aligned_write(mram_command)\n            else:\n                self._unaligned_write(mram_command)\n        else:\n            raise ValueError\n        return mram_command\n\n    def _aligned_read(self, mram_command: MRAMCommand) -> None:\n        assert mram_command.address() % DataWord().size() == 0\n\n        begin = self._index(mram_command.begin_address())\n        end = self._index(mram_command.end_address())\n        mram_command.set_data_words(self._data_words[begin:end])\n\n    def _aligned_write(self, mram_command: MRAMCommand) -> None:\n        assert mram_command.address() % DataWord().size() == 0\n\n        begin = self._index(mram_command.address())\n        end = self._index(mram_command.address() + mram_command.size())\n        self._data_words[begin:end] = mram_command.data_words()\n\n    def _unaligned_read(self, mram_command: MRAMCommand) -> None:\n        data_words: List[DataWord] = [DataWord() for _ in range(mram_command.size() // DataWord().size())]\n        for address in range(mram_command.begin_address(), mram_command.end_address()):\n            mram_index = self._index(address)\n            mram_offset = self._offset(address)\n\n            byte = self._data_words[mram_index].bit_slice(\n                Representation.UNSIGNED, 8 * mram_offset, 8 * (mram_offset + 1)\n            )\n\n            mram_command_index = (address - mram_command.begin_address()) // DataWord().size()\n            mram_command_offset = (address - mram_command.begin_address()) % DataWord().size()\n\n            data_words[mram_command_index].set_bit_slice(8 * mram_command_offset, 8 * (mram_command_offset + 1), byte)\n\n        mram_command.set_data_words(data_words)\n\n    def _unaligned_write(self, mram_command: MRAMCommand) -> None:\n        for address in range(mram_command.begin_address(), mram_command.end_address()):\n            mram_command_index = (address - mram_command.begin_address()) // DataWord().size()\n            mram_command_offset = (address - mram_command.begin_address()) % DataWord().size()\n\n            byte = mram_command.data_words()[mram_command_index].bit_slice(\n                Representation.UNSIGNED, 8 * mram_command_offset, 8 * (mram_command_offset + 1),\n            )\n\n            mram_index = self._index(address)\n            mram_offset = self._offset(address)\n\n            self._data_words[mram_index].set_bit_slice(8 * mram_offset, 8 * (mram_offset + 1), byte)\n\n    def cycle(self) -> None:\n        pass\n\n    def _index(self, address: int) -> int:\n        index = (address - self.address()) // DataWord().size()\n        assert 0 <= index < index + self._num_min_access_data_words <= len(self._data_words)\n        return index\n\n    def _offset(self, address: int) -> int:\n        offset = (address - self.address()) % DataWord().size()\n        return offset\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dram/mram_command.py",
    "content": "from enum import Enum, auto\nfrom typing import List\n\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass MRAMCommand:\n    class Operation(Enum):\n        READ = 0\n        WRITE = auto()\n\n    def __init__(self, operation: Operation, address: int, size: int):\n        assert size % ConfigLoader.min_access_granularity() == 0\n        assert size % DataWord().size() == 0\n\n        self._operation: MRAMCommand.Operation = operation\n\n        self._address: DataAddressWord = DataAddressWord()\n        self._address.set_value(address)\n\n        self._size = size\n\n        self._data_words: List[DataWord] = [DataWord() for _ in range(size // DataWord().size())]\n\n    def operation(self) -> Operation:\n        return self._operation\n\n    def address(self) -> int:\n        return self._address.value(Representation.UNSIGNED)\n\n    def size(self) -> int:\n        return self._size\n\n    def begin_address(self) -> int:\n        return self.address()\n\n    def end_address(self) -> int:\n        return self.address() + self.size()\n\n    def data_words(self) -> List[DataWord]:\n        data_words: List[DataWord] = [DataWord() for _ in range(len(self._data_words))]\n        for i, data_word in enumerate(self._data_words):\n            data_words[i].set_value(data_word.value(Representation.UNSIGNED))\n        return data_words\n\n    def data_word(self, address: int) -> DataWord:\n        index = self._index(address)\n\n        data_word = DataWord()\n        data_word.set_value(self._data_words[index].value(Representation.UNSIGNED))\n        return data_word\n\n    def set_data_words(self, data_words: List[DataWord]) -> None:\n        for i, data_word in enumerate(data_words):\n            self._data_words[i].set_value(data_word.value(Representation.UNSIGNED))\n\n    def set_data_word(self, address: int, data_word: DataWord) -> None:\n        index = self._index(address)\n        self._data_words[index].set_value(data_word.value(Representation.UNSIGNED))\n\n    def _index(self, address: int) -> int:\n        assert (address - self.address()) % DataWord().size() == 0\n        return (address - self.address()) // DataWord().size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/dram/word.py",
    "content": "from typing import List\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass Word:\n    def __init__(self, data_words: List[DataWord]):\n        assert ConfigLoader.min_access_granularity() % DataWord().size() == 0\n\n        self._data_words: List[DataWord] = [\n            DataWord() for _ in range(ConfigLoader.min_access_granularity() // DataWord().size())\n        ]\n\n        for src_data_word, dst_data_word in zip(data_words, self._data_words):\n            dst_data_word.set_value(src_data_word.value(Representation.UNSIGNED))\n\n    def data_words(self) -> List[DataWord]:\n        dst_data_words: List[DataWord] = [DataWord() for _ in range(len(self._data_words))]\n        for src_data_word, dst_data_word in zip(self._data_words, dst_data_words):\n            dst_data_word.set_value(src_data_word.value(Representation.UNSIGNED))\n        return dst_data_words\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/condition_register.py",
    "content": "from abi.isa.instruction.condition import Condition\n\n\nclass ConditionRegister:\n    def __init__(self):\n        self._bits = [False for _ in range(len(Condition))]\n\n    def condition(self, condition: Condition) -> bool:\n        if condition == Condition.TRUE:\n            return True\n        elif condition == Condition.FALSE:\n            return False\n        else:\n            return self._bits[condition.value]\n\n    def set_condition(self, condition: Condition) -> None:\n        assert condition != Condition.TRUE and condition != Condition.FALSE\n\n        self._bits[condition.value] = True\n\n    def clear_condition(self, condition: Condition) -> None:\n        assert condition != Condition.TRUE and condition != Condition.FALSE\n\n        self._bits[condition.value] = False\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/exception_register.py",
    "content": "from abi.isa.exception import Exception_\n\n\nclass ExceptionRegister:\n    def __init__(self):\n        self._bits = [False for _ in range(len(Exception_))]\n\n    def exception(self, exception: Exception_) -> bool:\n        return self._bits[exception.value]\n\n    def set_exception(self, exception: Exception_) -> None:\n        self._bits[exception.value] = True\n\n    def clear_exception(self, exception: Exception_) -> None:\n        self._bits[exception.value] = False\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/flag_register.py",
    "content": "from abi.isa.flag import Flag\n\n\nclass FlagRegister:\n    def __init__(self):\n        self._bits = [False for _ in range(len(Flag))]\n\n    def flag(self, flag: Flag) -> bool:\n        return self._bits[flag.value]\n\n    def set_flag(self, flag: Flag) -> None:\n        self._bits[flag.value] = True\n\n    def clear_flag(self, flag: Flag) -> None:\n        self._bits[flag.value] = False\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/gp_register.py",
    "content": "from abi.isa.register.gp_register import GPRegister as SoftGPRegister\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\n\n\nclass GPRegister:\n    def __init__(self, index: int):\n        self._soft_gp_regsiter: SoftGPRegister = SoftGPRegister(index)\n        self._word: DataWord = DataWord()\n\n    def index(self) -> int:\n        return self._soft_gp_regsiter.index()\n\n    def read(self, representation: Representation) -> int:\n        return self._word.value(representation)\n\n    def write(self, value: int) -> None:\n        self._word.set_value(value)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/pc_register.py",
    "content": "from abi.word.instruction_address_word import InstructionAddressWord\nfrom abi.word.representation import Representation\n\n\nclass PCRegister:\n    def __init__(self):\n        self._word: InstructionAddressWord = InstructionAddressWord()\n\n    def read(self) -> int:\n        return self._word.value(Representation.UNSIGNED)\n\n    def write(self, value: int) -> None:\n        self._word.set_value(value)\n\n    def increment(self) -> None:\n        self.write(self.read() + (InstructionAddressWord().size()))\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/register_file.py",
    "content": "from typing import Union\n\nfrom abi.isa.exception import Exception_\nfrom abi.isa.flag import Flag\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.register.gp_register import GPRegister as SoftGPRegister\nfrom abi.isa.register.pair_register import PairRegister as SoftPairRegister\nfrom abi.isa.register.sp_register import SPRegister as SoftSPRegister\nfrom abi.word.double_data_word import DoubleDataWord\nfrom abi.word.representation import Representation\nfrom iss.register.condition_register import ConditionRegister as HardConditionRegister\nfrom iss.register.exception_register import ExceptionRegister as HardExceptionRegister\nfrom iss.register.flag_register import FlagRegister as HardFlagRegister\nfrom iss.register.gp_register import GPRegister as HardGPRegister\nfrom iss.register.pc_register import PCRegister as HardPCRegister\nfrom iss.register.sp_register import SPRegister as HardSPRegister\nfrom util.config_loader import ConfigLoader\n\n\nclass RegisterFile:\n    Register = Union[SoftGPRegister, SoftSPRegister, SoftPairRegister]\n\n    def __init__(self, id_: int):\n        self._gp_registers = [HardGPRegister(i) for i in range(ConfigLoader.num_gp_registers())]\n        self._sp_register = HardSPRegister(id_)\n        self._pc_register = HardPCRegister()\n        self._condition_register = HardConditionRegister()\n        self._exception_register = HardExceptionRegister()\n        self._flag_register = HardFlagRegister()\n\n    def read(self, register: Register, representation: Representation) -> int:\n        if isinstance(register, SoftGPRegister):\n            return self._read_gp_register(register, representation)\n        elif isinstance(register, SoftSPRegister):\n            return self._read_sp_register(register, representation)\n        elif isinstance(register, SoftPairRegister):\n            return self._read_pair_register(register, representation)\n        else:\n            raise ValueError\n\n    def write(self, register: Register, value: int) -> None:\n        if isinstance(register, SoftGPRegister):\n            self._write_gp_register(register, value)\n        elif isinstance(register, SoftSPRegister):\n            raise ValueError\n        elif isinstance(register, SoftPairRegister):\n            self._write_pair_register(register, value)\n        else:\n            raise ValueError\n\n    def read_pc(self) -> int:\n        return self._pc_register.read()\n\n    def write_pc(self, value: int) -> None:\n        self._pc_register.write(value)\n\n    def increment_pc(self) -> None:\n        self._pc_register.increment()\n\n    def condition(self, condition: Condition) -> bool:\n        return self._condition_register.condition(condition)\n\n    def set_condition(self, condition: Condition) -> None:\n        self._condition_register.set_condition(condition)\n\n    def clear_condition(self, condition: Condition) -> None:\n        self._condition_register.clear_condition(condition)\n\n    def exception(self, exception: Exception_) -> bool:\n        return self._exception_register.exception(exception)\n\n    def set_exception(self, exception: Exception_) -> None:\n        self._exception_register.set_exception(exception)\n\n    def clear_exception(self, exception: Exception_) -> None:\n        self._exception_register.clear_exception(exception)\n\n    def flag(self, flag: Flag) -> bool:\n        return self._flag_register.flag(flag)\n\n    def set_flag(self, flag: Flag) -> None:\n        self._flag_register.set_flag(flag)\n\n    def clear_flag(self, flag: Flag) -> None:\n        self._flag_register.clear_flag(flag)\n\n    def clear_conditions(self) -> None:\n        for condition in Condition:\n            if condition == Condition.TRUE or condition == Condition.FALSE:\n                pass\n            else:\n                self.clear_condition(condition)\n\n    def cycle(self) -> None:\n        pass\n\n    def _read_gp_register(self, soft_gp_register: SoftGPRegister, representation: Representation) -> int:\n        return self._gp_registers[soft_gp_register.index()].read(representation)\n\n    def _read_sp_register(self, soft_sp_register: SoftSPRegister, representation: Representation):\n        return self._sp_register.read(soft_sp_register, representation)\n\n    def _read_pair_register(self, soft_pair_register: SoftPairRegister, representation: Representation) -> int:\n        even_register = self._gp_registers[soft_pair_register.even_register().index()]\n        odd_register = self._gp_registers[soft_pair_register.odd_register().index()]\n\n        double_data_word = DoubleDataWord()\n        double_data_word.set_bit_slice(0, double_data_word.width() // 2, odd_register.read(Representation.UNSIGNED))\n        double_data_word.set_bit_slice(\n            double_data_word.width() // 2, double_data_word.width(), even_register.read(representation),\n        )\n\n        return double_data_word.value(representation)\n\n    def _write_gp_register(self, soft_gp_register: SoftGPRegister, value: int) -> None:\n        self._gp_registers[soft_gp_register.index()].write(value)\n\n    def _write_pair_register(self, soft_pair_register: SoftPairRegister, value: int) -> None:\n        even_register = self._gp_registers[soft_pair_register.even_register().index()]\n        odd_register = self._gp_registers[soft_pair_register.odd_register().index()]\n\n        double_data_word = DoubleDataWord()\n        double_data_word.set_value(value)\n\n        odd_register.write(double_data_word.bit_slice(Representation.UNSIGNED, 0, double_data_word.width() // 2))\n        even_register.write(\n            double_data_word.bit_slice(\n                Representation.UNSIGNED, double_data_word.width() // 2, double_data_word.width(),\n            )\n        )\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/register/sp_register.py",
    "content": "from abi.isa.register.sp_register import SPRegister as SoftSPRegister\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass SPRegister:\n    def __init__(self, id_: int):\n        assert 0 <= id_ < ConfigLoader.max_num_tasklets()\n\n        self._zero = DataWord()\n        self._zero.set_value(0)\n\n        self._one = DataWord()\n        self._one.set_value(1)\n\n        self._lneg = DataWord()\n        self._lneg.set_value(-1)\n\n        self._mneg = DataWord()\n        self._mneg.set_bit(self._mneg.width() - 1)\n\n        self._id = DataWord()\n        self._id.set_value(id_)\n\n        self._id2 = DataWord()\n        self._id2.set_value(2 * id_)\n\n        self._id4 = DataWord()\n        self._id4.set_value(4 * id_)\n\n        self._id8 = DataWord()\n        self._id8.set_value(8 * id_)\n\n    def read(self, soft_sp_register: SoftSPRegister, representation: Representation) -> int:\n        if soft_sp_register == SoftSPRegister.ZERO:\n            return self._zero.value(representation)\n        elif soft_sp_register == SoftSPRegister.ONE:\n            return self._one.value(representation)\n        elif soft_sp_register == SoftSPRegister.LNEG:\n            return self._lneg.value(representation)\n        elif soft_sp_register == SoftSPRegister.MNEG:\n            return self._mneg.value(representation)\n        elif soft_sp_register == SoftSPRegister.ID:\n            return self._id.value(representation)\n        elif soft_sp_register == SoftSPRegister.ID2:\n            return self._id2.value(representation)\n        elif soft_sp_register == SoftSPRegister.ID4:\n            return self._id4.value(representation)\n        elif soft_sp_register == SoftSPRegister.ID8:\n            return self._id8.value(representation)\n        else:\n            raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/sram/atomic.py",
    "content": "from typing import List\n\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.representation import Representation\nfrom iss.sram.lock import Lock\nfrom util.config_loader import ConfigLoader\n\n\nclass Atomic:\n    def __init__(self):\n        self._address: DataAddressWord = DataAddressWord()\n        self._address.set_value(ConfigLoader.atomic_offset())\n\n        self._locks: List[Lock] = [Lock() for _ in range(ConfigLoader.atomic_size())]\n\n    def address(self) -> int:\n        return self._address.value(Representation.UNSIGNED)\n\n    def can_acquire(self, address: int) -> bool:\n        index = self._index(address)\n        return self._locks[index].can_acquire()\n\n    def acquire(self, address: int, id_: int) -> None:\n        index = self._index(address)\n        self._locks[index].acquire(id_)\n\n    def can_release(self, address: int, id_: int) -> bool:\n        index = self._index(address)\n        return self._locks[index].can_release(id_)\n\n    def release(self, address: int, id_: int) -> None:\n        index = self._index(address)\n        self._locks[index].release(id_)\n\n    def _index(self, address: int) -> int:\n        index = address - self.address()\n        assert 0 <= index < len(self._locks)\n        return index\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/sram/iram.py",
    "content": "from typing import List\n\nfrom abi.word.instruction_address_word import InstructionAddressWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass IRAM:\n    def __init__(self):\n        self._address: InstructionAddressWord = InstructionAddressWord()\n        self._address.set_value(ConfigLoader.iram_offset())\n\n        self._instruction_words: List[InstructionWord] = [\n            InstructionWord() for _ in range(ConfigLoader.iram_size() // InstructionWord().size())\n        ]\n\n    def address(self) -> int:\n        return self._address.value(Representation.UNSIGNED)\n\n    def read(self, address: int) -> InstructionWord:\n        index = self._index(address)\n        instruction_word = InstructionWord()\n        instruction_word.set_value(self._instruction_words[index].value(Representation.UNSIGNED))\n        return instruction_word\n\n    def write(self, address: int, instruction_word: InstructionWord) -> None:\n        index = self._index(address)\n        self._instruction_words[index].set_value(instruction_word.value(Representation.UNSIGNED))\n\n    def _index(self, address: int) -> int:\n        assert address % InstructionWord().size() == 0\n        index = (address - self.address()) // InstructionWord().size()\n        assert 0 <= index < len(self._instruction_words)\n\n        return index\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/sram/lock.py",
    "content": "from typing import Optional\n\n\nclass Lock:\n    def __init__(self):\n        self._id: Optional[int] = None\n\n    def can_acquire(self):\n        return self._id is None\n\n    def acquire(self, id_: int):\n        assert self.can_acquire()\n        self._id = id_\n\n    def can_release(self, id_: int):\n        return self._id is None or self._id == id_\n\n    def release(self, id_: int):\n        assert self.can_release(id_)\n        self._id = None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/sram/wram.py",
    "content": "from typing import List\n\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom util.config_loader import ConfigLoader\n\n\nclass WRAM:\n    def __init__(self):\n        self._address: DataAddressWord = DataAddressWord()\n        self._address.set_value(ConfigLoader.wram_offset())\n\n        self._data_words: List[DataWord] = [DataWord() for _ in range(ConfigLoader.wram_size() // DataWord().size())]\n\n    def address(self) -> int:\n        return self._address.value(Representation.UNSIGNED)\n\n    def read(self, address: int) -> DataWord:\n        index = self._index(address)\n        data_word = DataWord()\n        data_word.set_value(self._data_words[index].value(Representation.UNSIGNED))\n        return data_word\n\n    def write(self, address: int, data_word: DataWord) -> None:\n        index = self._index(address)\n        self._data_words[index].set_value(data_word.value(Representation.UNSIGNED))\n\n    def _index(self, address: int) -> int:\n        assert address % DataWord().size() == 0\n        index = (address - self.address()) // DataWord().size()\n        assert 0 <= index < len(self._data_words)\n\n        return index\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/iss/system.py",
    "content": "import logging\nimport os\n\nfrom iss.cpu.cpu import CPU\nfrom iss.dpu.dpu import DPU\nfrom util.path_collector import PathCollector\n\n\nclass System:\n    def __init__(self, benchmark: str, num_tasklets: int):\n        self._benchmark: str = benchmark\n        self._num_tasklets: int = num_tasklets\n        self._logger: logging.Logger = self._init_logger()\n\n        self._dpu = DPU(num_tasklets)\n        self._cpu = CPU(benchmark, num_tasklets, self._dpu)\n\n        self._execution: int = 0\n\n    def init(self) -> None:\n        self._cpu.init()\n        self._cpu.sched(self._execution)\n        self._cpu.launch()\n\n    def fini(self) -> None:\n        self._cpu.fini()\n\n    def is_finished(self) -> bool:\n        return self._execution == self._cpu.num_executions()\n\n    def is_zombie(self) -> bool:\n        return self._dpu.is_zombie()\n\n    def cycle(self):\n        self._dpu.cycle()\n        self._cpu.cycle()\n\n        if self.is_zombie():\n            self._cpu.check(self._execution)\n            self._execution += 1\n\n            if not self.is_finished():\n                self._cpu.sched(self._execution)\n                self._cpu.launch()\n\n    def _init_logger(self) -> logging.Logger:\n        logger = logging.getLogger(\"iss\")\n        logger.setLevel(logging.DEBUG)\n\n        formatter = logging.Formatter(\"%(message)s\")\n\n        trace_dirpath = PathCollector.trace_path_in_local()\n        if not os.path.exists(trace_dirpath):\n            os.makedirs(trace_dirpath)\n\n        log_filepath = os.path.join(trace_dirpath, f\"{self._benchmark}.{self._num_tasklets}.trace\",)\n        if os.path.exists(log_filepath):\n            os.remove(log_filepath)\n\n        stream_handler = logging.StreamHandler()\n        file_handler = logging.FileHandler(filename=log_filepath)\n\n        stream_handler.setLevel(logging.INFO)\n        file_handler.setLevel(logging.DEBUG)\n\n        stream_handler.setFormatter(formatter)\n        file_handler.setFormatter(formatter)\n\n        logger.addHandler(stream_handler)\n        logger.addHandler(file_handler)\n\n        return logger\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/linker.py",
    "content": "import os\nfrom typing import List, Set, Union\n\nimport antlr4\n\nfrom abi.binary.executable import Executable\nfrom abi.binary.relocatable import Relocatable\nfrom assembler.assembler import Assembler\nfrom linker_.linker_script import LinkerScript\nfrom linker_.logic.instruction_assigner import InstructionAssigner\nfrom linker_.logic.label_assigner import LabelAssigner\nfrom linker_.logic.liveness_analyzer import LivenessAnalyzer\nfrom linker_.logic.set_assigner import SetAssigner\nfrom parser_.parser import Parser\nfrom util.path_collector import PathCollector\n\n\nclass Linker:\n    def __init__(self, num_tasklets: int):\n        self._libs: List[Relocatable] = self._init_libs()\n\n    def link(self, filepath: str, data_prep_param: list, num_dpus: int):\n        num_tasklets = Linker._num_tasklets(filepath)\n        linker_script = LinkerScript(num_tasklets)\n\n        relocatable = Relocatable(filepath)\n        self._analyze_liveness(relocatable)\n        relocatables = self._resolve_symbols(relocatable, linker_script)\n\n        executable = Executable(filepath, relocatables)\n        Linker._write_bin(executable, num_dpus)\n\n        self._analyze_liveness(executable)\n        self._assign_labels(executable)\n        linker_script.assign_address(executable)\n        self._assign_set(executable)\n        self._assign_instruction(executable, linker_script)\n\n        Assembler.assemble(executable, linker_script, data_prep_param, num_dpus)\n\n    def _analyze_liveness(self, binary: Union[Relocatable, Executable]):\n        document = Parser.parse_lines(binary.lines())\n        liveness_analyzer = LivenessAnalyzer(binary)\n        parse_tree_walker = antlr4.ParseTreeWalker()\n        parse_tree_walker.walk(liveness_analyzer, document)\n\n    def _resolve_symbols(self, relocatable: Relocatable, linker_script: LinkerScript) -> Set[Relocatable]:\n        relocatables: Set[Relocatable] = {relocatable, self._crt0_relocatable()}\n\n        unresolved_symbols = self._unresolved_symbols(relocatables, linker_script)\n        while unresolved_symbols:\n            has_resolved = False\n            for unresolved_symbol in unresolved_symbols:\n                for lib in self._libs:\n                    if unresolved_symbol in lib.liveness().defs():\n                        relocatables.add(lib)\n                        has_resolved = True\n            assert has_resolved\n\n            unresolved_symbols = self._unresolved_symbols(relocatables, linker_script)\n\n        return relocatables\n\n    def _defs(self, relocatables: Set[Relocatable]) -> Set[str]:\n        defs: Set[str] = set()\n        for relocatable in relocatables:\n            defs.update(relocatable.liveness().defs())\n        return defs\n\n    def _unresolved_symbols(self, relocatables: Set[Relocatable], linker_script: LinkerScript) -> Set[str]:\n        defs = self._defs(relocatables)\n        unresolved_symbols: Set[str] = set()\n        for relocatable in relocatables:\n            for unresolved_symbol in relocatable.liveness().unresolved_symbols():\n                if (\n                    unresolved_symbol not in defs\n                    and unresolved_symbol not in linker_script.symbol_names()\n                    and unresolved_symbol not in linker_script.constant_names()\n                ):\n                    unresolved_symbols.add(unresolved_symbol)\n        return unresolved_symbols\n\n    def _assign_labels(self, executable: Executable) -> None:\n        document = Parser.parse_lines(executable.lines())\n        label_assigner = LabelAssigner(executable)\n        parse_tree_walker = antlr4.ParseTreeWalker()\n        parse_tree_walker.walk(label_assigner, document)\n\n    def _assign_set(self, executable: Executable) -> None:\n        document = Parser.parse_lines(executable.lines())\n        set_assigner = SetAssigner(executable)\n        parse_tree_walker = antlr4.ParseTreeWalker()\n        parse_tree_walker.walk(set_assigner, document)\n\n    def _assign_instruction(self, executable: Executable, linker_script: LinkerScript) -> None:\n        document = Parser.parse_lines(executable.lines())\n        instruction_assigner = InstructionAssigner(executable, linker_script)\n        parse_tree_walker = antlr4.ParseTreeWalker()\n        parse_tree_walker.walk(instruction_assigner, document)\n\n    def _init_libs(self) -> List[Relocatable]:\n        relocatables: List[Relocatable] = []\n        for lib_name in Linker.libs_names():\n            asm_lib_path = os.path.join(PathCollector.asm_path_in_local(), lib_name)\n            for root_path, _, filenames in os.walk(asm_lib_path):\n                for filename in filenames:\n                    if filename.split(\".\")[-1] == \"S\":\n                        filepath = os.path.join(root_path, filename)\n                        relocatable = Relocatable(filepath)\n                        self._analyze_liveness(relocatable)\n                        relocatables.append(relocatable)\n        return relocatables\n\n    def _crt0_relocatable(self) -> Relocatable:\n        for lib in self._libs:\n            crt0_filepath = os.path.join(PathCollector.asm_path_in_local(), \"misc\", \"crt0.S\")\n            if lib.filepath() == crt0_filepath:\n                return lib\n        raise ValueError\n\n    @staticmethod\n    def _write_bin(executable: Executable, num_dpus: int) -> None:\n        filepath = os.path.join(PathCollector.bin_path_in_local(), f\"{num_dpus}_dpus\", *executable.filepath().split(os.path.sep)[-2:])\n\n        dirname = os.path.dirname(filepath)\n        if not os.path.exists(dirname):\n            os.makedirs(dirname)\n\n        with open(filepath, \"w\") as file:\n            file.writelines(executable.lines())\n\n    @staticmethod\n    def _num_tasklets(filepath: str) -> int:\n        return int(filepath.split(os.path.sep)[-2].split(\".\")[-1])\n\n    @staticmethod\n    def libs_names() -> List[str]:\n        return [\"misc\", \"stdlib\", \"syslib\"]\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/linker_script.py",
    "content": "import math\nfrom typing import Dict, Set\n\nfrom abi.binary.executable import Executable\nfrom abi.label.label import Label\nfrom abi.section.section_name import SectionName\nfrom abi.word.instruction_word import InstructionWord\nfrom util.config_loader import ConfigLoader\n\n\nclass LinkerScript:\n    def __init__(self, num_tasklets: int):\n        self._num_tasklets: int = num_tasklets\n\n        self._constants: Dict[str, int] = self._init_constants()\n        self._symbols: Set[Label] = self._init_symbols()\n\n    def constant(self, constant_name: str) -> int:\n        return self._constants[constant_name]\n\n    def constant_names(self) -> Set[str]:\n        return set(self._constants.keys())\n\n    def symbol(self, symbol_name: str) -> Label:\n        for symbol in self._symbols:\n            if symbol.name() == symbol_name:\n                return symbol\n        raise ValueError\n\n    def symbol_names(self) -> Set[str]:\n        return {symbol.name() for symbol in self._symbols}\n\n    def assign_address(self, executable: Executable) -> None:\n        self._assign_iram(executable)\n        self._assign_atomic(executable)\n        self._assign_wram(executable)\n        self._assign_mram(executable)\n\n    def _assign_iram(self, executable: Executable) -> None:\n        cur_address = ConfigLoader.iram_offset()\n        bootstrap = executable.section(SectionName.TEXT, \"__bootstrap\")\n\n        assert bootstrap is not None\n        assert bootstrap.address() is None\n\n        bootstrap.set_address(cur_address)\n        cur_address += bootstrap.size()\n        assert bootstrap.size() % InstructionWord().size() == 0\n\n        text_section = executable.section(SectionName.TEXT, \"\")\n        if text_section is not None:\n            assert text_section.address() is None\n\n            text_section.set_address(cur_address)\n            cur_address += text_section.size()\n\n            assert text_section.size() % InstructionWord().size() == 0\n\n        for section in executable.sections(SectionName.TEXT):\n            if section.name() != \"__bootstrap\" and section.name() != \"\":\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n                assert section.size() % InstructionWord().size() == 0\n\n        assert cur_address < (ConfigLoader.iram_offset() + ConfigLoader.iram_size())\n\n    def _assign_atomic(self, executable: Executable) -> None:\n        cur_address = ConfigLoader.atomic_offset()\n        self.symbol(\"__atomic_start_addr\").set_address(cur_address)\n\n        # TODO(bongjoon.hyun@gmail.com): the original UPMEM linker script adds 200 to the cur_address\n        # cur_address += 200\n\n        self.symbol(\"__atomic_used_addr\").set_address(cur_address)\n        for section in executable.sections(SectionName.ATOMIC):\n            assert section.address() is None\n\n            section.set_address(cur_address)\n            cur_address += section.size()\n\n        self.symbol(\"__atomic_end_addr\").set_address(cur_address)\n\n        assert cur_address < (ConfigLoader.atomic_offset() + ConfigLoader.atomic_size())\n\n    def _assign_wram(self, executable: Executable) -> None:\n        cur_address = ConfigLoader.wram_offset()\n\n        sys_zero = executable.section(SectionName.DATA, \"__sys_zero\")\n        if sys_zero is not None:\n            assert sys_zero.address() is None\n\n            sys_zero.set_address(cur_address)\n            cur_address += sys_zero.size()\n\n        immediate_memory = executable.section(SectionName.DATA, \"immediate_memory\")\n        if immediate_memory is not None:\n            assert immediate_memory.address() is None\n\n            immediate_memory.set_address(cur_address)\n            cur_address += immediate_memory.size()\n\n        for section in executable.sections(SectionName.DATA):\n            if \"immediate_memory.\" in section.name():\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        self.symbol(\"__rodata_start_addr\").set_address(cur_address)\n        rodata_section = executable.section(SectionName.RODATA, \"\")\n        if rodata_section is not None:\n            assert rodata_section.address() is None\n\n            rodata_section.set_address(cur_address)\n            cur_address += rodata_section.size()\n\n        for section in executable.sections(SectionName.RODATA):\n            if section.name() != \"\":\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n        self.symbol(\"__rodata_end_addr\").set_address(cur_address)\n\n        bss_section = executable.section(SectionName.BSS, \"\")\n        if bss_section is not None:\n            assert bss_section.address() is None\n\n            bss_section.set_address(cur_address)\n            cur_address += bss_section.size()\n\n        for section in executable.sections(SectionName.BSS):\n            if section.name() != \"\":\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        sys_keep = executable.section(SectionName.DATA, \"__sys_keep\")\n        if sys_keep is not None:\n            assert sys_keep.address() is None\n\n            sys_keep.set_address(cur_address)\n            cur_address += sys_keep.size()\n\n        data_section = executable.section(SectionName.DATA, \"\")\n        if data_section is not None:\n            assert data_section.address() is None\n\n            data_section.set_address(cur_address)\n            cur_address += data_section.size()\n\n        for section in executable.sections(SectionName.DATA):\n            if (\n                section.name() != \"__sys_zero\"\n                and section.name() != \"__sys_keep\"\n                and section.name() != \"\"\n                and \"immediate_memory\" not in section.name()\n            ):\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        dpu_host = executable.section(SectionName.DPU_HOST, \"\")\n        if dpu_host is not None:\n            assert dpu_host.address() is None\n\n            dpu_host.set_address(cur_address)\n            cur_address += dpu_host.size()\n\n        for i in range(ConfigLoader.max_num_tasklets()):\n            self.symbol(f\"__sys_stack_thread_{i}\").set_address(cur_address)\n            cur_address += self.constant(f\"STACK_SIZE_TASKLET_{i}\")\n\n        self.symbol(\"__sw_cache_buffer\").set_address(cur_address)\n        cur_address += 8 * self._num_tasklets\n\n        cur_address = (\n            math.ceil(cur_address / ConfigLoader.min_access_granularity()) * ConfigLoader.min_access_granularity()\n        )\n        self.symbol(\"__sys_heap_pointer_reset\").set_address(cur_address)\n\n        assert cur_address < (ConfigLoader.wram_offset() + ConfigLoader.wram_size())\n\n    def _assign_mram(self, executable: Executable) -> None:\n        cur_address = ConfigLoader.mram_offset()\n\n        debug_abbrev_section = executable.section(SectionName.DEBUG_ABBREV, \"\")\n        if debug_abbrev_section is not None:\n            assert debug_abbrev_section.address() is None\n\n            debug_abbrev_section.set_address(cur_address)\n            cur_address += debug_abbrev_section.size()\n\n        debug_frame_section = executable.section(SectionName.DEBUG_FRAME, \"\")\n        if debug_frame_section is not None:\n            assert debug_frame_section.address() is None\n\n            debug_frame_section.set_address(cur_address)\n            cur_address += debug_frame_section.size()\n\n        debug_info_section = executable.section(SectionName.DEBUG_INFO, \"\")\n        if debug_info_section is not None:\n            assert debug_info_section.address() is None\n\n            debug_info_section.set_address(cur_address)\n            cur_address += debug_info_section.size()\n\n        debug_line_section = executable.section(SectionName.DEBUG_LINE, \"\")\n        if debug_line_section is not None:\n            assert debug_line_section.address() is None\n\n            debug_line_section.set_address(cur_address)\n            cur_address += debug_line_section.size()\n\n        debug_loc_section = executable.section(SectionName.DEBUG_LOC, \"\")\n        if debug_loc_section is not None:\n            assert debug_loc_section.address() is None\n\n            debug_loc_section.set_address(cur_address)\n            cur_address += debug_loc_section.size()\n\n        debug_ranges_section = executable.section(SectionName.DEBUG_RANGES, \"\")\n        if debug_ranges_section is not None:\n            assert debug_ranges_section.address() is None\n\n            debug_ranges_section.set_address(cur_address)\n            cur_address += debug_ranges_section.size()\n\n        debug_str_section = executable.section(SectionName.DEBUG_STR, \"\")\n        if debug_str_section is not None:\n            assert debug_str_section.address() is None\n\n            debug_str_section.set_address(cur_address)\n            cur_address += debug_str_section.size()\n\n        stack_sizes_section = executable.section(SectionName.STACK_SIZES, \"\")\n        if stack_sizes_section is not None:\n            assert stack_sizes_section.address() is None\n\n            stack_sizes_section.set_address(cur_address)\n            cur_address += stack_sizes_section.size()\n\n        noinit = executable.section(SectionName.MRAM, \"noinit\")\n        if noinit is not None:\n            assert noinit.address() is None\n\n            noinit.set_address(cur_address)\n            cur_address += noinit.size()\n\n        for section in executable.sections(SectionName.MRAM):\n            if \"noinit.\" in section.name():\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        mram_section = executable.section(SectionName.MRAM, \"\")\n        if mram_section is not None:\n            assert mram_section.address() is None\n\n            mram_section.set_address(cur_address)\n            cur_address += mram_section.size()\n\n        for section in executable.sections(SectionName.MRAM):\n            if section.name() != \"\" and \"noinit\" not in section.name() and \"keep\" not in section.name():\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        keep = executable.section(SectionName.MRAM, \"keep\")\n        if keep is not None:\n            assert keep.address() is None\n\n            keep.set_address(cur_address)\n            cur_address += keep.size()\n\n        for section in executable.sections(SectionName.MRAM):\n            if \"keep.\" in section.name():\n                assert section.address() is None\n\n                section.set_address(cur_address)\n                cur_address += section.size()\n\n        cur_address = (\n            math.ceil(cur_address / ConfigLoader.min_access_granularity()) * ConfigLoader.min_access_granularity()\n        )\n        self.symbol(\"__sys_used_mram_end\").set_address(cur_address)\n\n        assert cur_address < (ConfigLoader.mram_offset() + ConfigLoader.mram_size())\n\n    def _init_constants(self) -> Dict[str, int]:\n        return {\n            \"NR_TASKLETS\": self._num_tasklets,\n            **self._init_stack_size_constants(),\n        }\n\n    def _init_stack_size_constants(self) -> Dict[str, int]:\n        return {f\"STACK_SIZE_TASKLET_{i}\": ConfigLoader.stack_size() for i in range(ConfigLoader.max_num_tasklets())}\n\n    def _init_symbols(self) -> Set[Label]:\n        return {\n            *self._init_atomic_symbols(),\n            *self._init_wram_symbols(),\n            *self._init_mram_symbols(),\n        }\n\n    def _init_atomic_symbols(self) -> Set[Label]:\n        return {\n            Label(\"__atomic_start_addr\"),\n            Label(\"__atomic_used_addr\"),\n            Label(\"__atomic_end_addr\"),\n        }\n\n    def _init_wram_symbols(self) -> Set[Label]:\n        return {\n            Label(\"__rodata_start_addr\"),\n            Label(\"__rodata_end_addr\"),\n            *self._init_stack_symbols(),\n            Label(\"__sw_cache_buffer\"),\n            Label(\"__sys_heap_pointer_reset\"),\n        }\n\n    def _init_stack_symbols(self) -> Set[Label]:\n        return {Label(f\"__sys_stack_thread_{i}\") for i in range(ConfigLoader.max_num_tasklets())}\n\n    def _init_mram_symbols(self) -> Set[Label]:\n        return {Label(\"__sys_used_mram_end\")}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/logic/instruction_assigner.py",
    "content": "from abi.binary.executable import Executable\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.endian import Endian\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom abi.isa.register.sp_register import SPRegister\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom abi.word.instruction_word import InstructionWord\nfrom converter.condition_converter import ConditionConverter\nfrom converter.endian_converter import EndianConverter\nfrom converter.op_code_converter import OpCodeConverter\nfrom converter.register_converter import RegisterConverter\nfrom converter.section_flag_converter import SectionFlagConverter\nfrom converter.section_name_converter import SectionNameConverter\nfrom converter.section_type_converter import SectionTypeConverter\nfrom encoder.ascii_encoder import AsciiEncoder\nfrom encoder.byte import Byte\nfrom linker_.linker_script import LinkerScript\nfrom parser_.grammar.assemblyListener import assemblyListener\nfrom parser_.grammar.assemblyParser import assemblyParser\n\n\nclass InstructionAssigner(assemblyListener):\n    def __init__(self, executable: Executable, linker_script: LinkerScript):\n        self._executable = executable\n        self._linker_script = linker_script\n\n    def exitAscii_directive(self, ctx: assemblyParser.Ascii_directiveContext) -> None:\n        string_literal = str(ctx.StringLiteral())[1:-1].replace(\"\\\\b\", \"■\")\n\n        i = 0\n        characters = \"\"\n        while i < len(string_literal):\n            if string_literal[i] == \"\\\\\":\n                octal = Byte(int(string_literal[i + 1 : i + 4], base=8))\n                characters += AsciiEncoder().decode(octal)\n                i += 3\n            else:\n                characters += string_literal[i]\n                i += 1\n        ascii_directive = AsciiDirective(characters)\n\n        self._executable.append_assembler_instruction(ascii_directive)\n\n    def exitAsciz_directive(self, ctx: assemblyParser.Asciz_directiveContext) -> None:\n        characters = str(ctx.StringLiteral())[1:-1]\n        asciz_directive = AscizDirective(characters)\n        self._executable.append_assembler_instruction(asciz_directive)\n\n    def exitByte_directive(self, ctx: assemblyParser.Byte_directiveContext) -> None:\n        value = self._evaluate_program_counter(ctx.program_counter())\n        byte_directive = ByteDirective(value)\n        self._executable.append_assembler_instruction(byte_directive)\n\n    def exitLong_directive(self, ctx: assemblyParser.Long_directiveContext) -> None:\n        value = self._evaluate_program_counter(ctx.program_counter())\n        long_directive = LongDirective(value)\n        self._executable.append_assembler_instruction(long_directive)\n\n    def exitQuad_directive(self, ctx: assemblyParser.Quad_directiveContext) -> None:\n        value = self._evaluate_program_counter(ctx.program_counter())\n        quad_directive = QuadDirective(value)\n        self._executable.append_assembler_instruction(quad_directive)\n\n    def exitSection_directive(self, ctx: assemblyParser.Section_directiveContext) -> None:\n        section_name = SectionNameConverter.convert_to_section_name(str(ctx.section_name().children[0])[1:])\n\n        name = ctx.Identifier()\n        if name is not None:\n            name = str(name)\n        else:\n            name = \"\"\n\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitShort_directive(self, ctx: assemblyParser.Short_directiveContext) -> None:\n        value = self._evaluate_program_counter(ctx.program_counter())\n        short_directive = ShortDirective(value)\n        self._executable.append_assembler_instruction(short_directive)\n\n    def exitStack_sizes_directive(self, ctx: assemblyParser.Stack_sizes_directiveContext):\n        section_name = SectionName.STACK_SIZES\n\n        name = \"\"\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitText_directive(self, ctx: assemblyParser.Text_directiveContext) -> None:\n        self._executable.checkout_section(\n            SectionName.TEXT, \"\", {SectionFlag.ALLOC, SectionFlag.EXECINSTR}, SectionType.PROG_BITS,\n        )\n\n    def exitZero_directive(self, ctx: assemblyParser.Zero_directiveContext) -> None:\n        size, value = int(ctx.number(i=0).getText()), ctx.number(i=1)\n        if value is None:\n            value = 0\n        else:\n            value = int(value.getText())\n\n        zero_directive = ZeroDirective(size, value)\n        self._executable.append_assembler_instruction(zero_directive)\n\n    def exitRici_instruction(self, ctx: assemblyParser.Rici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rici_op_code().children[0])[1:])\n        suffix = Suffix.RICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_program_counter(ctx.program_counter(i=0))\n        condition = ConditionConverter.convert_to_condition(str(ctx.condition().children[0]))\n        pc = self._evaluate_program_counter(ctx.program_counter(i=1))\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRri_instruction(self, ctx: assemblyParser.Rri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRric_instruction(self, ctx: assemblyParser.Rric_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.RRIC\n        else:\n            suffix = Suffix.RRIF\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrici_instruction(self, ctx: assemblyParser.Rrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RRICI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrr_instruction(self, ctx: assemblyParser.Rrr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RRR\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrrc_instruction(self, ctx: assemblyParser.Rrrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RRRC\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrrci_instruction(self, ctx: assemblyParser.Rrrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RRRCI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZri_instruction(self, ctx: assemblyParser.Zri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZRI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZric_instruction(self, ctx: assemblyParser.Zric_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_program_counter(ctx.program_counter())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.ZRIC\n        else:\n            suffix = Suffix.ZRIF\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrici_instruction(self, ctx: assemblyParser.Zrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrr_instruction(self, ctx: assemblyParser.Zrr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZRR\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrrc_instruction(self, ctx: assemblyParser.Zrrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZRRC\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrrci_instruction(self, ctx: assemblyParser.Zrrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rri_instruction(self, ctx: assemblyParser.S_rri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rric_instruction(self, ctx: assemblyParser.S_rric_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.S_RRIC\n        else:\n            suffix = Suffix.S_RRIF\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrici_instruction(self, ctx: assemblyParser.S_rrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrr_instruction(self, ctx: assemblyParser.S_rrr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRR\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrrc_instruction(self, ctx: assemblyParser.S_rrrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrrci_instruction(self, ctx: assemblyParser.S_rrrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rri_instruction(self, ctx: assemblyParser.U_rri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rric_instruction(self, ctx: assemblyParser.U_rric_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.U_RRIC\n        else:\n            suffix = Suffix.U_RRIF\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrici_instruction(self, ctx: assemblyParser.U_rrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrr_instruction(self, ctx: assemblyParser.U_rrr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRR\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrrc_instruction(self, ctx: assemblyParser.U_rrrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrrci_instruction(self, ctx: assemblyParser.U_rrrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRr_instruction(self, ctx: assemblyParser.Rr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.RR\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrc_instruction(self, ctx: assemblyParser.Rrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.RRC\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrci_instruction(self, ctx: assemblyParser.Rrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.RRCI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZr_instruction(self, ctx: assemblyParser.Zr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.ZR\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrc_instruction(self, ctx: assemblyParser.Zrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.ZRC\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrci_instruction(self, ctx: assemblyParser.Zrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.ZRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rr_instruction(self, ctx: assemblyParser.S_rr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.S_RR\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrc_instruction(self, ctx: assemblyParser.S_rrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.S_RRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrci_instruction(self, ctx: assemblyParser.S_rrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.S_RRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rr_instruction(self, ctx: assemblyParser.U_rr_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.U_RR\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrc_instruction(self, ctx: assemblyParser.U_rrc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.U_RRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrci_instruction(self, ctx: assemblyParser.U_rrci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rr_op_code().children[0])[1:])\n        suffix = Suffix.U_RRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitDrdici_instruction(self, ctx: assemblyParser.Drdici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.drdici_op_code().children[0])[1:])\n        suffix = Suffix.DRDICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, db=db, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert db == instruction.db()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrri_instruction(self, ctx: assemblyParser.Rrri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.RRRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRrrici_instruction(self, ctx: assemblyParser.Rrrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.RRRICI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrri_instruction(self, ctx: assemblyParser.Zrri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.ZRRI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZrrici_instruction(self, ctx: assemblyParser.Zrrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.ZRRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrri_instruction(self, ctx: assemblyParser.S_rrri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rrrici_instruction(self, ctx: assemblyParser.S_rrrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.S_RRRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrri_instruction(self, ctx: assemblyParser.U_rrri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rrrici_instruction(self, ctx: assemblyParser.U_rrrici_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rrri_op_code().children[0])[1:])\n        suffix = Suffix.U_RRRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, rb=rb, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRir_instruction(self, ctx: assemblyParser.Rir_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RIR\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRirc_instruction(self, ctx: assemblyParser.Rirc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.RIRC\n        else:\n            suffix = Suffix.RRIF\n\n        instruction = Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRirci_instruction(self, ctx: assemblyParser.Rirci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.RIRCI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZir_instruction(self, ctx: assemblyParser.Zir_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZIR\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, imm=imm, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZirc_instruction(self, ctx: assemblyParser.Zirc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        if condition != Condition.FALSE:\n            suffix = Suffix.ZIRC\n        else:\n            suffix = Suffix.ZRIF\n\n        instruction = Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZirci_instruction(self, ctx: assemblyParser.Zirci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.ZIRCI\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, imm=imm, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rirc_instruction(self, ctx: assemblyParser.S_rirc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RIRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rirci_instruction(self, ctx: assemblyParser.S_rirci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.S_RIRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rirc_instruction(self, ctx: assemblyParser.U_rirc_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RIRC\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n\n        instruction = Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rirci_instruction(self, ctx: assemblyParser.U_rirci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.rri_op_code().children[0])[1:])\n        suffix = Suffix.U_RIRCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        imm = self._evaluate_number(ctx.number())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitR_instruction(self, ctx: assemblyParser.R_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.R\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n\n        instruction = Instruction(op_code, suffix, rc=rc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitRci_instruction(self, ctx: assemblyParser.Rci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.RCI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZ_instruction(self, ctx: assemblyParser.Z_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.Z\n\n        instruction = Instruction(op_code, suffix)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitZci_instruction(self, ctx: assemblyParser.Zci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.ZCI\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_r_instruction(self, ctx: assemblyParser.S_r_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.S_R\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n\n        instruction = Instruction(op_code, suffix, dc=dc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_rci_instruction(self, ctx: assemblyParser.S_rci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.S_RCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_r_instruction(self, ctx: assemblyParser.U_r_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.U_R\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n\n        instruction = Instruction(op_code, suffix, dc=dc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_rci_instruction(self, ctx: assemblyParser.U_rci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.r_op_code().children[0])[1:])\n        suffix = Suffix.U_RCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitCi_instruction(self, ctx: assemblyParser.Ci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.ci_op_code().children[0])[1:])\n        suffix = Suffix.CI\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitI_instruction(self, ctx: assemblyParser.I_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.i_op_code().children[0])[1:])\n        suffix = Suffix.I\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitDdci_instruction(self, ctx: assemblyParser.Ddci_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.ddci_op_code().children[0])[1:])\n        suffix = Suffix.DDCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, db=db, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert db == instruction.db()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitErri_instruction(self, ctx: assemblyParser.Erri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.load_op_code().children[0])[1:])\n        suffix = Suffix.ERRI\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitEdri_instruction(self, ctx: assemblyParser.Edri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.load_op_code().children[0])[1:])\n        suffix = Suffix.EDRI\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitS_erri_instruction(self, ctx: assemblyParser.S_erri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.load_op_code().children[0])[1:])\n        suffix = Suffix.S_ERRI\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitU_erri_instruction(self, ctx: assemblyParser.U_erri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.load_op_code().children[0])[1:])\n        suffix = Suffix.U_ERRI\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitErii_instruction(self, ctx: assemblyParser.Erii_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.store_op_code().children[0])[1:])\n        suffix = Suffix.ERII\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number(i=0))\n        imm = self._evaluate_number(ctx.number(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitErir_instruction(self, ctx: assemblyParser.Erir_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.store_op_code().children[0])[1:])\n        suffix = Suffix.ERIR\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitErid_instruction(self, ctx: assemblyParser.Erid_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.store_op_code().children[0])[1:])\n        suffix = Suffix.ERID\n        endian = EndianConverter.convert_to_endian(ctx.endian().getText())\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, db=db)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert db == instruction.db()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitDma_rri_instruction(self, ctx: assemblyParser.Dma_rri_instructionContext) -> None:\n        op_code = OpCodeConverter.convert_to_op_code(str(ctx.dma_op_code().children[0])[1:])\n        suffix = Suffix.DMA_RRI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitAndn_rrif_instruction(self, ctx: assemblyParser.Andn_rrif_instructionContext) -> None:\n        op_code = OpCode.ANDN\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNand_rrif_instruction(self, ctx: assemblyParser.Nand_rrif_instructionContext) -> None:\n        op_code = OpCode.NAND\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNor_rrif_instruction(self, ctx: assemblyParser.Nor_rrif_instructionContext) -> None:\n        op_code = OpCode.NOR\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNxor_rrif_instruction(self, ctx: assemblyParser.Nxor_rrif_instructionContext) -> None:\n        op_code = OpCode.NXOR\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitOrn_rrif_instruction(self, ctx: assemblyParser.Orn_rrif_instructionContext) -> None:\n        op_code = OpCode.ORN\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitHash_rrif_instruction(self, ctx: assemblyParser.Hash_rrif_instructionContext) -> None:\n        op_code = OpCode.HASH\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_ri_instruction(self, ctx: assemblyParser.Move_ri_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.RRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = SPRegister.ZERO\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_rici_instruction(self, ctx: assemblyParser.Move_rici_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.RRICI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = SPRegister.ZERO\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_rr_instruction(self, ctx: assemblyParser.Move_rr_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.RRIF\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_rrci_instruction(self, ctx: assemblyParser.Move_rrci_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.RRICI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_s_ri_instruction(self, ctx: assemblyParser.Move_s_ri_instructionContext) -> None:\n        op_code = OpCode.AND\n        suffix = Suffix.S_RRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = SPRegister.LNEG\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_s_rici_instruction(self, ctx: assemblyParser.Move_s_rici_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.S_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = SPRegister.ZERO\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_s_rr_instruction(self, ctx: assemblyParser.Move_s_rr_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.S_RRIF\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_s_rrci_instruction(self, ctx: assemblyParser.Move_s_rrci_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.S_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_u_ri_instruction(self, ctx: assemblyParser.Move_u_ri_instructionContext) -> None:\n        op_code = OpCode.AND\n        suffix = Suffix.U_RRI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = SPRegister.LNEG\n        imm = self._evaluate_number(ctx.number())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_u_rici_instruction(self, ctx: assemblyParser.Move_u_rici_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.U_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = SPRegister.ZERO\n        imm = self._evaluate_number(ctx.number())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_u_rr_instruction(self, ctx: assemblyParser.Move_u_rr_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.U_RRIF\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = Condition.FALSE\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMove_u_rrci_instruction(self, ctx: assemblyParser.Move_u_rrci_instructionContext) -> None:\n        op_code = OpCode.OR\n        suffix = Suffix.U_RRICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNeg_rr_instruction(self, ctx: assemblyParser.Neg_rr_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.RIR\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        imm = 0\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n\n        instruction = Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNeg_rrci_instruction(self, ctx: assemblyParser.Neg_rrci_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.RIRCI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        imm = 0\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, imm=imm, ra=ra, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert imm == instruction.imm().value()\n        assert ra == instruction.ra()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNot_rr_instruction(self, ctx: assemblyParser.Not_rr_instructionContext) -> None:\n        op_code = OpCode.XOR\n        suffix = Suffix.RRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = -1\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNot_rrci_instruction(self, ctx: assemblyParser.Not_rrci_instructionContext) -> None:\n        op_code = OpCode.XOR\n        suffix = Suffix.RRICI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = -1\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitNot_zrci_instruction(self, ctx: assemblyParser.Not_zrci_instructionContext) -> None:\n        op_code = OpCode.XOR\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = -1\n        condition = ConditionConverter.convert_to_condition(ctx.condition().getText())\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJeq_rii_instruction(self, ctx: assemblyParser.Jeq_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_program_counter(ctx.program_counter(i=0))\n        condition = Condition.Z\n        pc = self._evaluate_program_counter(ctx.program_counter(i=1))\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJeq_rri_instruction(self, ctx: assemblyParser.Jeq_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.Z\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJneq_rii_instruction(self, ctx: assemblyParser.Jneq_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.NZ\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJneq_rri_instruction(self, ctx: assemblyParser.Jneq_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.NZ\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJz_ri_instruction(self, ctx: assemblyParser.Jz_ri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = Condition.Z\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJnz_ri_instruction(self, ctx: assemblyParser.Jnz_ri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n        condition = Condition.NZ\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJltu_rii_instruction(self, ctx: assemblyParser.Jltu_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.LTU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJltu_rri_instruction(self, ctx: assemblyParser.Jltu_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.LTU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgtu_rii_instruction(self, ctx: assemblyParser.Jgtu_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.GTU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgtu_rri_instruction(self, ctx: assemblyParser.Jgtu_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.GTU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJleu_rii_instruction(self, ctx: assemblyParser.Jleu_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.LEU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJleu_rri_instruction(self, ctx: assemblyParser.Jleu_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.LEU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgeu_rii_instruction(self, ctx: assemblyParser.Jgeu_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.GEU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgeu_rri_instruction(self, ctx: assemblyParser.Jgeu_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.GEU\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJlts_rii_instruction(self, ctx: assemblyParser.Jlts_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.LTS\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJlts_rri_instruction(self, ctx: assemblyParser.Jlts_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.LTS\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgts_rii_instruction(self, ctx: assemblyParser.Jgts_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.GTS\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJgts_rri_instruction(self, ctx: assemblyParser.Jgts_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.GTS\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJles_rii_instruction(self, ctx: assemblyParser.Jles_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.LES\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJles_rri_instruction(self, ctx: assemblyParser.Jles_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.LES\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJges_rii_instruction(self, ctx: assemblyParser.Jges_rii_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.GES\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJges_rri_instruction(self, ctx: assemblyParser.Jges_rri_instructionContext) -> None:\n        op_code = OpCode.SUB\n        suffix = Suffix.ZRRCI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n        condition = Condition.GES\n        pc = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, rb=rb, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert rb == instruction.rb()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJump_ri_instruction(self, ctx: assemblyParser.Jump_ri_instructionContext) -> None:\n        op_code = OpCode.CALL\n        suffix = Suffix.ZRI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJump_i_instruction(self, ctx: assemblyParser.Jump_i_instructionContext) -> None:\n        op_code = OpCode.CALL\n        suffix = Suffix.ZRI\n        ra = SPRegister.ZERO\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitJump_r_instruction(self, ctx: assemblyParser.Jump_r_instructionContext) -> None:\n        op_code = OpCode.CALL\n        suffix = Suffix.ZRI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitDiv_step_drdici_instruction(self, ctx: assemblyParser.Div_step_drdici_instructionContext) -> None:\n        op_code = OpCode.DIV_STEP\n        suffix = Suffix.DRDICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, db=db, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert db == instruction.db()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMul_step_drdici_instruction(self, ctx: assemblyParser.Mul_step_drdici_instructionContext) -> None:\n        op_code = OpCode.MUL_STEP\n        suffix = Suffix.DRDICI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, dc=dc, ra=ra, db=db, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert db == instruction.db()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitBoot_rici_instruction(self, ctx: assemblyParser.Boot_rici_instructionContext) -> None:\n        op_code = OpCode.BOOT\n        suffix = Suffix.RICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitResume_rici_instruction(self, ctx: assemblyParser.Resume_rici_instructionContext) -> None:\n        op_code = OpCode.RESUME\n        suffix = Suffix.RICI\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = self._evaluate_number(ctx.number())\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, ra=ra, imm=imm, condiiton=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitStop_ci_instruction(self, ctx: assemblyParser.Stop_ci_instructionContext) -> None:\n        op_code = OpCode.STOP\n        suffix = Suffix.CI\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, condiiton=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitCall_ri_instruction(self, ctx: assemblyParser.Call_ri_instructionContext) -> None:\n        op_code = OpCode.CALL\n        suffix = Suffix.RRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = SPRegister.ZERO\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitCall_rr_instruction(self, ctx: assemblyParser.Call_rr_instructionContext) -> None:\n        op_code = OpCode.CALL\n        suffix = Suffix.RRI\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, rc=rc, ra=ra, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitBkp_instruction(self, ctx: assemblyParser.Bkp_instructionContext) -> None:\n        op_code = OpCode.FAULT\n        suffix = Suffix.I\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitMovd_ddci_instruction(self, ctx: assemblyParser.Movd_ddci_instructionContext) -> None:\n        op_code = OpCode.MOVD\n        suffix = Suffix.DDCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, dc=dc, db=db, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert db == instruction.db()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSwapd_ddci_instruction(self, ctx: assemblyParser.Swapd_ddci_instructionContext) -> None:\n        op_code = OpCode.SWAPD\n        suffix = Suffix.DDCI\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=0)))\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister(i=1)))\n        condition = Condition.FALSE\n        pc = 0\n\n        instruction = Instruction(op_code, suffix, dc=dc, db=db, condition=condition, pc=pc)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert dc == instruction.dc()\n        assert db == instruction.db()\n        assert condition == instruction.condition()\n        assert pc == instruction.pc().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitTime_cfg_zr_instruction(self, ctx: assemblyParser.Time_cfg_zr_instructionContext) -> None:\n        op_code = OpCode.TIME_CFG\n        suffix = Suffix.ZR\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n\n        instruction = Instruction(op_code, suffix, ra=ra)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert ra == instruction.ra()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLbs_erri_instruction(self, ctx: assemblyParser.Lbs_erri_instructionContext) -> None:\n        op_code = OpCode.LBS\n        suffix = Suffix.ERRI\n        endian = Endian.LITTLE\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLbs_s_erri_instruction(self, ctx: assemblyParser.Lbs_s_erri_instructionContext) -> None:\n        op_code = OpCode.LBS\n        suffix = Suffix.S_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLbu_erri_instruction(self, ctx: assemblyParser.Lbu_erri_instructionContext) -> None:\n        op_code = OpCode.LBU\n        suffix = Suffix.ERRI\n        endian = Endian.LITTLE\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLbu_u_erri_instruction(self, ctx: assemblyParser.Lbu_u_erri_instructionContext) -> None:\n        op_code = OpCode.LBS\n        suffix = Suffix.U_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLd_edri_instruction(self, ctx: assemblyParser.Ld_edri_instructionContext) -> None:\n        op_code = OpCode.LD\n        suffix = Suffix.EDRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLhs_erri_instruction(self, ctx: assemblyParser.Lhs_erri_instructionContext) -> None:\n        op_code = OpCode.LHS\n        suffix = Suffix.ERRI\n        endian = Endian.LITTLE\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLhs_s_erri_instruction(self, ctx: assemblyParser.Lhs_s_erri_instructionContext) -> None:\n        op_code = OpCode.LHS\n        suffix = Suffix.S_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLhu_erri_instruction(self, ctx: assemblyParser.Lhu_erri_instructionContext) -> None:\n        op_code = OpCode.LHU\n        suffix = Suffix.ERRI\n        endian = Endian.LITTLE\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLhu_u_erri_instruction(self, ctx: assemblyParser.Lhu_u_erri_instructionContext) -> None:\n        op_code = OpCode.LHU\n        suffix = Suffix.U_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLw_erri_instruction(self, ctx: assemblyParser.Lw_erri_instructionContext) -> None:\n        op_code = OpCode.LW\n        suffix = Suffix.ERRI\n        endian = Endian.LITTLE\n        rc = RegisterConverter.convert_to_gp_register(str(ctx.GPRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, rc=rc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert rc == instruction.rc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLw_s_erri_instruction(self, ctx: assemblyParser.Lw_s_erri_instructionContext) -> None:\n        op_code = OpCode.LW\n        suffix = Suffix.S_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLw_u_erri_instruction(self, ctx: assemblyParser.Lw_u_erri_instructionContext) -> None:\n        op_code = OpCode.LW\n        suffix = Suffix.U_ERRI\n        endian = Endian.LITTLE\n        dc = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, dc=dc, ra=ra, off=off)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert dc == instruction.dc()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSb_erii_instruction(self, ctx: assemblyParser.Sb_erii_instructionContext) -> None:\n        op_code = OpCode.SB\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert (imm % (2 ** instruction.imm().width())) == (\n            instruction.imm().value() % (2 ** instruction.imm().width())\n        )\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSb_erir_instruction(self, ctx: assemblyParser.Sb_erir_instructionContext) -> None:\n        op_code = OpCode.SB\n        suffix = Suffix.ERIR\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSb_id_rii_instruction(self, ctx: assemblyParser.Sb_id_rii_instructionContext) -> None:\n        op_code = OpCode.SB_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number(i=0))\n        imm = self._evaluate_number(ctx.number(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSb_id_ri_instruction(self, ctx: assemblyParser.Sb_id_ri_instructionContext) -> None:\n        op_code = OpCode.SB_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSd_erii_instruction(self, ctx: assemblyParser.Sd_erii_instructionContext) -> None:\n        op_code = OpCode.SD\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter(i=0))\n        imm = self._evaluate_program_counter(ctx.program_counter(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSd_erid_instruction(self, ctx: assemblyParser.Sd_erid_instructionContext) -> None:\n        op_code = OpCode.SD\n        suffix = Suffix.ERID\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        db = RegisterConverter.convert_to_pair_register(str(ctx.PairRegister()))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, db=db)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert db == instruction.db()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSd_id_rii_instruction(self, ctx: assemblyParser.Sd_id_rii_instructionContext) -> None:\n        op_code = OpCode.SD_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number(i=0))\n        imm = self._evaluate_number(ctx.number(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSd_id_ri_instruction(self, ctx: assemblyParser.Sd_id_ri_instructionContext) -> None:\n        op_code = OpCode.SD_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSh_erii_instruction(self, ctx: assemblyParser.Sh_erii_instructionContext) -> None:\n        op_code = OpCode.SH\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSh_erir_instruction(self, ctx: assemblyParser.Sh_erir_instructionContext) -> None:\n        op_code = OpCode.SH\n        suffix = Suffix.ERIR\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSh_id_rii_instruction(self, ctx: assemblyParser.Sh_id_rii_instructionContext) -> None:\n        op_code = OpCode.SH_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number(i=0))\n        imm = self._evaluate_number(ctx.number(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSh_id_ri_instruction(self, ctx: assemblyParser.Sh_id_ri_instructionContext) -> None:\n        op_code = OpCode.SH_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSw_erii_instruction(self, ctx: assemblyParser.Sw_erii_instructionContext) -> None:\n        op_code = OpCode.SW\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = self._evaluate_program_counter(ctx.program_counter())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSw_erir_instruction(self, ctx: assemblyParser.Sw_erir_instructionContext) -> None:\n        op_code = OpCode.SW\n        suffix = Suffix.ERIR\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register(i=0).getText())\n        off = self._evaluate_program_counter(ctx.program_counter())\n        rb = RegisterConverter.convert_to_source_register(ctx.src_register(i=1).getText())\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, rb=rb)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert rb == instruction.rb()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSw_id_rii_instruction(self, ctx: assemblyParser.Sw_id_rii_instructionContext) -> None:\n        op_code = OpCode.SW_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number(i=0))\n        imm = self._evaluate_number(ctx.number(i=1))\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitSw_id_ri_instruction(self, ctx: assemblyParser.Sw_id_ri_instructionContext) -> None:\n        op_code = OpCode.SW_ID\n        suffix = Suffix.ERII\n        endian = Endian.LITTLE\n        ra = RegisterConverter.convert_to_source_register(ctx.src_register().getText())\n        off = self._evaluate_number(ctx.number())\n        imm = 0\n\n        instruction = Instruction(op_code, suffix, endian=endian, ra=ra, off=off, imm=imm)\n\n        assert op_code == instruction.op_code()\n        assert suffix == instruction.suffix()\n        assert endian == instruction.endian()\n        assert ra == instruction.ra()\n        assert off == instruction.off().value()\n        assert imm == instruction.imm().value()\n\n        self._executable.append_assembler_instruction(instruction)\n\n    def exitLabel(self, ctx: assemblyParser.LabelContext) -> None:\n        label_name = str(ctx.Identifier())\n\n        # TODO(bongjoon.hyun@gmail.com): __sys_used_mram_end will be defined in the linker script\n        if label_name != \"__sys_used_mram_end\":\n            self._executable.append_label(str(ctx.Identifier()))\n\n    def _evaluate_program_counter(self, ctx: assemblyParser.Program_counterContext) -> int:\n        child = ctx.children[0]\n        if isinstance(child, assemblyParser.Primary_expressionContext):\n            return self._evaluate_primary_expression(child)\n        elif isinstance(child, assemblyParser.Add_expressionContext):\n            return self._evaluate_add_expression(child)\n        elif isinstance(child, assemblyParser.Sub_expressionContext):\n            return self._evaluate_sub_expression(child)\n        else:\n            raise ValueError\n\n    def _evaluate_primary_expression(self, ctx: assemblyParser.Primary_expressionContext) -> int:\n        identifier = ctx.Identifier()\n        if identifier is not None:\n            return self._evaluate_identifier(str(identifier))\n\n        child = ctx.children[0]\n        if isinstance(child, assemblyParser.NumberContext):\n            return InstructionAssigner._evaluate_number(child)\n        elif isinstance(child, assemblyParser.Section_nameContext):\n            return self._evaluate_section_name(child)\n        else:\n            raise ValueError\n\n    def _evaluate_add_expression(self, ctx: assemblyParser.Add_expressionContext) -> int:\n        primary_expression1 = self._evaluate_primary_expression(ctx.primary_expression(i=0))\n        primary_expression2 = self._evaluate_primary_expression(ctx.primary_expression(i=1))\n\n        if ctx.primary_expression(i=0).getText() != \"NR_TASKLETS\" and isinstance(\n            ctx.primary_expression(i=1).children[0], assemblyParser.NumberContext\n        ):\n            return primary_expression1 + InstructionWord().size() * primary_expression2\n        else:\n            return primary_expression1 + primary_expression2\n\n    def _evaluate_sub_expression(self, ctx: assemblyParser.Sub_expressionContext) -> int:\n        primary_expression1 = self._evaluate_primary_expression(ctx.primary_expression(i=0))\n        primary_expression2 = self._evaluate_primary_expression(ctx.primary_expression(i=1))\n\n        if ctx.primary_expression(i=0).getText() != \"NR_TASKLETS\" and isinstance(\n            ctx.primary_expression(i=1).children[0], assemblyParser.NumberContext\n        ):\n            return primary_expression1 - InstructionWord().size() * primary_expression2\n        else:\n            return primary_expression1 - primary_expression2\n\n    @staticmethod\n    def _evaluate_number(ctx: assemblyParser.NumberContext) -> int:\n        if ctx.getText()[:2] == \"0x\":\n            return int(ctx.getText()[2:], 16)\n        else:\n            return int(ctx.getText())\n\n    def _evaluate_identifier(self, identifier: str) -> int:\n        label = self._executable.label(identifier)\n        if label is not None:\n            assert label.address() is not None\n            return label.address()\n\n        if identifier in self._linker_script.symbol_names():\n            assert self._linker_script.symbol(identifier).address() is not None\n            return self._linker_script.symbol(identifier).address()\n\n        if identifier in self._linker_script.constant_names():\n            assert self._linker_script.constant(identifier) != 0\n            return self._linker_script.constant(identifier)\n\n        raise ValueError\n\n    def _evaluate_section_name(self, ctx: assemblyParser.Section_nameContext) -> int:\n        section_name = SectionNameConverter.convert_to_section_name(str(ctx.children[0])[1:])\n\n        return self._executable.section(section_name, \"\").address()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/logic/label_assigner.py",
    "content": "from abi.binary.executable import Executable\nfrom abi.directive.ascii_directive import AsciiDirective\nfrom abi.directive.asciz_directive import AscizDirective\nfrom abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom abi.directive.zero_directive import ZeroDirective\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom converter.section_flag_converter import SectionFlagConverter\nfrom converter.section_name_converter import SectionNameConverter\nfrom converter.section_type_converter import SectionTypeConverter\nfrom encoder.ascii_encoder import AsciiEncoder\nfrom encoder.byte import Byte\nfrom parser_.grammar.assemblyListener import assemblyListener\nfrom parser_.grammar.assemblyParser import assemblyParser\nfrom util.config_loader import ConfigLoader\n\n\nclass LabelAssigner(assemblyListener):\n    def __init__(self, executable: Executable):\n        self._executable: Executable = executable\n\n    def exitAscii_directive(self, ctx: assemblyParser.Ascii_directiveContext) -> None:\n        string_literal = str(ctx.StringLiteral())[1:-1].replace(\"\\\\b\", \"■\")\n\n        i = 0\n        characters = \"\"\n        while i < len(string_literal):\n            if string_literal[i] == \"\\\\\":\n                octal = Byte(int(string_literal[i + 1 : i + 4], base=8))\n                characters += AsciiEncoder().decode(octal)\n                i += 3\n            else:\n                characters += string_literal[i]\n                i += 1\n        ascii_directive = AsciiDirective(characters)\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + ascii_directive.size())\n\n    def exitAsciz_directive(self, ctx: assemblyParser.Asciz_directiveContext) -> None:\n        characters = str(ctx.StringLiteral())[1:-1]\n\n        asciz_directive = AscizDirective(characters)\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + asciz_directive.size())\n\n    def exitByte_directive(self, ctx: assemblyParser.Byte_directiveContext) -> None:\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + ByteDirective.size())\n\n    def exitLong_directive(self, ctx: assemblyParser.Long_directiveContext) -> None:\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + LongDirective.size())\n\n    def exitQuad_directive(self, ctx: assemblyParser.Quad_directiveContext) -> None:\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + QuadDirective.size())\n\n    def exitSection_directive(self, ctx: assemblyParser.Section_directiveContext) -> None:\n        section_name = SectionNameConverter.convert_to_section_name(str(ctx.section_name().children[0])[1:])\n\n        name = ctx.Identifier()\n        if name is not None:\n            name = str(name)\n        else:\n            name = \"\"\n\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitShort_directive(self, ctx: assemblyParser.Short_directiveContext) -> None:\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + ShortDirective.size())\n\n    def exitSize_directive(self, ctx: assemblyParser.Size_directiveContext) -> None:\n        # TODO(bongjoon.hyun@gmail.com): implement this\n        pass\n\n    def exitStack_sizes_directive(self, ctx: assemblyParser.Stack_sizes_directiveContext):\n        section_name = SectionName.STACK_SIZES\n\n        name = \"\"\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitText_directive(self, ctx: assemblyParser.Text_directiveContext) -> None:\n        self._executable.checkout_section(\n            SectionName.TEXT, \"\", {SectionFlag.ALLOC, SectionFlag.EXECINSTR}, SectionType.PROG_BITS,\n        )\n\n    def exitZero_directive(self, ctx: assemblyParser.Zero_directiveContext) -> None:\n        size, value = int(ctx.number(i=0).getText()), ctx.number(i=1)\n        if value is None:\n            value = 0\n        else:\n            value = int(value.getText())\n\n        zero_directive = ZeroDirective(size, value)\n\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + zero_directive.size())\n\n    def exitInstruction(self, ctx: assemblyParser.InstructionContext):\n        instruction_size = ConfigLoader.iram_data_width() // 8\n        cur_label = self._executable.cur_label()\n        cur_label.set_size(cur_label.size() + instruction_size)\n\n    def exitLabel(self, ctx: assemblyParser.LabelContext):\n        label_name = str(ctx.Identifier())\n\n        # TODO(bongjoon.hyun@gmail.com): __sys_used_mram_end will be defined in the linker script\n        if label_name != \"__sys_used_mram_end\":\n            self._executable.append_label(str(ctx.Identifier()))\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/logic/liveness_analyzer.py",
    "content": "from typing import Union\n\nfrom abi.binary.executable import Executable\nfrom abi.binary.relocatable import Relocatable\nfrom converter.symbol_converter import SymbolConverter\nfrom parser_.grammar.assemblyListener import assemblyListener\nfrom parser_.grammar.assemblyParser import assemblyParser\n\n\nclass LivenessAnalyzer(assemblyListener):\n    def __init__(self, binary: Union[Relocatable, Executable]):\n        self._binary: Union[Relocatable, Executable] = binary\n\n    def exitGlobal_directive(self, ctx: assemblyParser.Global_directiveContext) -> None:\n        symbol_name = str(ctx.Identifier())\n\n        # TODO(bongjoon.hyun@gmail.com): __sys_used_mram_end will be defined in the linker script\n        if symbol_name != \"__sys_used_mram_end\":\n            self._binary.liveness().add_global_symbol(symbol_name)\n\n    def exitSet_directive(self, ctx: assemblyParser.Set_directiveContext) -> None:\n        self._binary.liveness().add_def(str(ctx.Identifier(i=0)))\n        self._binary.liveness().add_use(str(ctx.Identifier(i=1)))\n\n    def exitSize_directive(self, ctx: assemblyParser.Size_directiveContext) -> None:\n        self._binary.liveness().add_use(str(ctx.Identifier()))\n\n    def exitType_directive(self, ctx: assemblyParser.Type_directiveContext):\n        self._binary.liveness().add_symbol(\n            str(ctx.Identifier()), SymbolConverter.convert_to_symbol(ctx.symbol_type().getText()),\n        )\n\n    def exitPrimary_expression(self, ctx: assemblyParser.Primary_expressionContext) -> None:\n        identifier = ctx.Identifier()\n        if identifier:\n            self._binary.liveness().add_use(str(identifier))\n\n    def exitLabel(self, ctx: assemblyParser.LabelContext) -> None:\n        label_name = str(ctx.Identifier())\n        assert label_name not in self._binary.liveness().defs()\n\n        # TODO(bongjoon.hyun@gmail.com): __sys_used_mram_end will be defined in the linker script\n        if label_name != \"__sys_used_mram_end\":\n            self._binary.liveness().checkout_def(label_name)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/linker_/logic/set_assigner.py",
    "content": "from abi.binary.executable import Executable\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom converter.section_flag_converter import SectionFlagConverter\nfrom converter.section_name_converter import SectionNameConverter\nfrom converter.section_type_converter import SectionTypeConverter\nfrom parser_.grammar.assemblyListener import assemblyListener\nfrom parser_.grammar.assemblyParser import assemblyParser\n\n\nclass SetAssigner(assemblyListener):\n    def __init__(self, executable: Executable):\n        self._executable: Executable = executable\n\n    def exitSection_directive(self, ctx: assemblyParser.Section_directiveContext) -> None:\n        section_name = SectionNameConverter.convert_to_section_name(str(ctx.section_name().children[0])[1:])\n\n        name = ctx.Identifier()\n        if name is not None:\n            name = str(name)\n        else:\n            name = \"\"\n\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitSet_directive(self, ctx: assemblyParser.Set_directiveContext) -> None:\n        src_label_name = str(ctx.Identifier(i=0))\n        dst_label_name = str(ctx.Identifier(i=1))\n\n        src_label = self._executable.cur_section().label(src_label_name)\n        assert src_label is not None\n\n        self._executable.append_label(dst_label_name)\n        dst_label = self._executable.cur_section().label(dst_label_name)\n        assert dst_label is not None\n\n        dst_label.set_address(src_label.address())\n\n    def exitSize_directive(self, ctx: assemblyParser.Size_directiveContext) -> None:\n        # TODO(bongjoon.hyun@gmail.com): implement this\n        pass\n\n    def exitStack_sizes_directive(self, ctx: assemblyParser.Stack_sizes_directiveContext):\n        section_name = SectionName.STACK_SIZES\n\n        name = \"\"\n        section_flags = SectionFlagConverter.convert_to_section_flags(str(ctx.StringLiteral())[1:-1])\n        section_type = SectionTypeConverter.convert_to_section_type(str(ctx.section_types().children[0]))\n\n        self._executable.checkout_section(section_name, name, section_flags, section_type)\n\n    def exitText_directive(self, ctx: assemblyParser.Text_directiveContext) -> None:\n        self._executable.checkout_section(\n            SectionName.TEXT, \"\", {SectionFlag.ALLOC, SectionFlag.EXECINSTR}, SectionType.PROG_BITS,\n        )\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/main.py",
    "content": "import argparse\nimport os\n\nfrom compiler.compiler import Compiler\nfrom iss.system import System\nfrom linker_.linker import Linker\nfrom util.path_collector import PathCollector\n\n\ndef compile(benchmark: str, num_tasklets: int) -> None:\n    Compiler.clean()\n    Compiler.compile_sdk(num_tasklets)\n    Compiler.compile_benchmark(benchmark, num_tasklets)\n\n\ndef link(benchmark: str, num_dpus: int,num_tasklets: int, data_prep_param: list) -> None:\n    linker = Linker(num_tasklets)\n    linker.link(os.path.join(PathCollector.asm_path_in_local(), f\"{benchmark}.{num_tasklets}\", \"main.S\"), data_prep_param, num_dpus)\n\n\ndef iss(benchmark: str, num_tasklets: int) -> None:\n    system = System(benchmark, num_tasklets)\n\n    system.init()\n    while not system.is_finished():\n        system.cycle()\n    system.fini()\n\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\"--benchmark\", type=str, default=\"SEL\")\n    parser.add_argument(\"--num_tasklets\", type=int, default=1)\n    parser.add_argument(\"--mode\", type=str, default=\"all\")\n    parser.add_argument(\"--data_prep_param\", type=str, default=\"2048\")\n    parser.add_argument(\"--num_dpus\", type=int, default=\"16\")\n    args = parser.parse_args()\n\n    data_prep_param = [int(elem) for elem in args.data_prep_param.split(',')]\n\n    if args.mode == \"compile\":\n        compile(args.benchmark, args.num_tasklets)\n    elif args.mode == \"link\":\n        link(args.benchmark, args.num_dpus, args.num_tasklets, data_prep_param)\n    elif args.mode == \"iss\":\n        iss(args.benchmark, args.num_tasklets)\n    elif args.mode == \"all\":\n        compile(args.benchmark, args.num_tasklets)\n        link(args.benchmark,  args.num_dpus, args.num_tasklets, data_prep_param)\n        iss(args.benchmark, args.num_tasklets)\n    else:\n        raise ValueError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assembly.interp",
    "content": "token literal names:\nnull\n'-'\n'0x'\n'+'\n','\n':'\n'$acquire'\n'$release'\n'$boot'\n'$resume'\n'$add'\n'$addc'\n'$and'\n'$andn'\n'$asr'\n'$cmpb4'\n'$lsl'\n'$lsl1'\n'$lsl1x'\n'$lslx'\n'$lsr'\n'$lsr1'\n'$lsr1x'\n'$lsrx'\n'$mul_sh_sh'\n'$mul_sh_sl'\n'$mul_sh_uh'\n'$mul_sh_ul'\n'$mul_sl_sh'\n'$mul_sl_sl'\n'$mul_sl_uh'\n'$mul_sl_ul'\n'$mul_uh_uh'\n'$mul_uh_ul'\n'$mul_ul_uh'\n'$mul_ul_ul'\n'$nand'\n'$nor'\n'$nxor'\n'$or'\n'$orn'\n'$rol'\n'$ror'\n'$rsub'\n'$rsubc'\n'$sub'\n'$subc'\n'$xor'\n'$call'\n'$hash'\n'$cao'\n'$clo'\n'$cls'\n'$clz'\n'$extsb'\n'$extsh'\n'$extub'\n'$extuh'\n'$sats'\n'$time_cfg'\n'$div_step'\n'$mul_step'\n'$lsl_add'\n'$lsl_sub'\n'$lsr_add'\n'$rol_add'\n'$ror_add'\n'$time'\n'$nop'\n'$stop'\n'$fault'\n'$movd'\n'$swapd'\n'$lbs'\n'$lbu'\n'$ld'\n'$lhs'\n'$lhu'\n'$lw'\n'$sb'\n'$sb_id'\n'$sd'\n'$sd_id'\n'$sh'\n'$sh_id'\n'$sw'\n'$sw_id'\n'$ldma'\n'$ldmai'\n'$sdma'\n'$move'\n'$neg'\n'$not'\n'$bkp'\n'$jeq'\n'$jneq'\n'$jz'\n'$jnz'\n'$jltu'\n'$jgtu'\n'$jleu'\n'$jgeu'\n'$jlts'\n'$jgts'\n'$jles'\n'$jges'\n'$jump'\n'%atomic'\n'%bss'\n'%data'\n'%debug_abbrev'\n'%debug_frame'\n'%debug_info'\n'%debug_line'\n'%debug_loc'\n'%debug_ranges'\n'%debug_str'\n'%dpu_host'\n'%mram'\n'%rodata'\n'%stack_sizes'\n'%text'\n'@progbits'\n'@nobits'\n'@function'\n'@object'\n'true'\n'false'\n'z'\n'nz'\n'e'\n'o'\n'pl'\n'mi'\n'ov'\n'nov'\n'c'\n'nc'\n'sz'\n'snz'\n'spl'\n'smi'\n'so'\n'se'\n'nc5'\n'nc6'\n'nc7'\n'nc8'\n'nc9'\n'nc10'\n'nc11'\n'nc12'\n'nc13'\n'nc14'\n'max'\n'nmax'\n'sh32'\n'nsh32'\n'eq'\n'neq'\n'ltu'\n'leu'\n'gtu'\n'geu'\n'lts'\n'les'\n'gts'\n'ges'\n'xz'\n'xnz'\n'xleu'\n'xgtu'\n'xles'\n'xgts'\n'small'\n'large'\n'!little'\n'!big'\n'zero'\n'one'\n'id'\n'id2'\n'id4'\n'id8'\n'lneg'\n'mneg'\n'$addrsig'\n'$addrsig_sym'\n'$ascii'\n'$asciz'\n'$byte'\n'$cfi_def_cfa_offset'\n'$cfi_endproc'\n'$cfi_offset'\n'$cfi_sections'\n'$cfi_startproc'\n'$file'\n'$globl'\n'$loc'\n'$long'\n'$p2align'\n'$quad'\n'$section'\n'$set'\n'$short'\n'$size'\n'$text'\n'$type'\n'$weak'\n'$zero'\n'is_stmt'\n'prologue_end'\n'.s'\n'.u'\nnull\nnull\nnull\nnull\nnull\nnull\nnull\n\ntoken symbolic names:\nnull\nnull\nnull\nnull\nnull\nnull\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nrule names:\ndocument\nnegative_number\nhex_number\nnumber\nrici_op_code\nrri_op_code\nrr_op_code\ndrdici_op_code\nrrri_op_code\nr_op_code\nci_op_code\ni_op_code\nddci_op_code\nload_op_code\nstore_op_code\ndma_op_code\nsection_name\nsection_types\nsymbol_type\ncondition\nendian\nsp_register\nsrc_register\nprogram_counter\nadd_expression\nsub_expression\nprimary_expression\ndirective\naddrsig_directive\naddrsig_sym_directive\nascii_directive\nasciz_directive\nbyte_directive\ncfi_def_cfa_offset_directive\ncfi_endproc_directive\ncfi_offset_directive\ncfi_sections_directive\ncfi_startproc_directive\nfile_directive\nglobal_directive\nloc_directive\nlong_directive\np2align_directive\nquad_directive\nsection_directive\nset_directive\nshort_directive\nsize_directive\nstack_sizes_directive\ntext_directive\ntype_directive\nweak_directive\nzero_directive\ninstruction\nrici_instruction\nrri_instruction\nrric_instruction\nrrici_instruction\nrrr_instruction\nrrrc_instruction\nrrrci_instruction\nzri_instruction\nzric_instruction\nzrici_instruction\nzrr_instruction\nzrrc_instruction\nzrrci_instruction\ns_rri_instruction\ns_rric_instruction\ns_rrici_instruction\ns_rrr_instruction\ns_rrrc_instruction\ns_rrrci_instruction\nu_rri_instruction\nu_rric_instruction\nu_rrici_instruction\nu_rrr_instruction\nu_rrrc_instruction\nu_rrrci_instruction\nrr_instruction\nrrc_instruction\nrrci_instruction\nzr_instruction\nzrc_instruction\nzrci_instruction\ns_rr_instruction\ns_rrc_instruction\ns_rrci_instruction\nu_rr_instruction\nu_rrc_instruction\nu_rrci_instruction\ndrdici_instruction\nrrri_instruction\nrrrici_instruction\nzrri_instruction\nzrrici_instruction\ns_rrri_instruction\ns_rrrici_instruction\nu_rrri_instruction\nu_rrrici_instruction\nrir_instruction\nrirc_instruction\nrirci_instruction\nzir_instruction\nzirc_instruction\nzirci_instruction\ns_rirc_instruction\ns_rirci_instruction\nu_rirc_instruction\nu_rirci_instruction\nr_instruction\nrci_instruction\nz_instruction\nzci_instruction\ns_r_instruction\ns_rci_instruction\nu_r_instruction\nu_rci_instruction\nci_instruction\ni_instruction\nddci_instruction\nerri_instruction\nedri_instruction\ns_erri_instruction\nu_erri_instruction\nerii_instruction\nerir_instruction\nerid_instruction\ndma_rri_instruction\nsynthetic_sugar_instruction\nrrif_instruction\nandn_rrif_instruction\nnand_rrif_instruction\nnor_rrif_instruction\nnxor_rrif_instruction\norn_rrif_instruction\nhash_rrif_instruction\nmove_instruction\nmove_ri_instruction\nmove_rici_instruction\nmove_rr_instruction\nmove_rrci_instruction\nmove_s_ri_instruction\nmove_s_rici_instruction\nmove_s_rr_instruction\nmove_s_rrci_instruction\nmove_u_ri_instruction\nmove_u_rici_instruction\nmove_u_rr_instruction\nmove_u_rrci_instruction\nneg_instruction\nneg_rr_instruction\nneg_rrci_instruction\nnot_instruction\nnot_rr_instruction\nnot_rrci_instruction\nnot_zrci_instruction\njump_instruction\njeq_rii_instruction\njeq_rri_instruction\njneq_rii_instruction\njneq_rri_instruction\njz_ri_instruction\njnz_ri_instruction\njltu_rii_instruction\njltu_rri_instruction\njgtu_rii_instruction\njgtu_rri_instruction\njleu_rii_instruction\njleu_rri_instruction\njgeu_rii_instruction\njgeu_rri_instruction\njlts_rii_instruction\njlts_rri_instruction\njgts_rii_instruction\njgts_rri_instruction\njles_rii_instruction\njles_rri_instruction\njges_rii_instruction\njges_rri_instruction\njump_ri_instruction\njump_i_instruction\njump_r_instruction\nshortcut_instruction\ndiv_step_drdici_instruction\nmul_step_drdici_instruction\nboot_rici_instruction\nresume_rici_instruction\nstop_ci_instruction\ncall_ri_instruction\ncall_rr_instruction\nbkp_instruction\nmovd_ddci_instruction\nswapd_ddci_instruction\ntime_cfg_zr_instruction\nlbs_erri_instruction\nlbs_s_erri_instruction\nlbu_erri_instruction\nlbu_u_erri_instruction\nld_edri_instruction\nlhs_erri_instruction\nlhs_s_erri_instruction\nlhu_erri_instruction\nlhu_u_erri_instruction\nlw_erri_instruction\nlw_s_erri_instruction\nlw_u_erri_instruction\nsb_erii_instruction\nsb_erir_instruction\nsb_id_rii_instruction\nsb_id_ri_instruction\nsd_erii_instruction\nsd_erid_instruction\nsd_id_rii_instruction\nsd_id_ri_instruction\nsh_erii_instruction\nsh_erir_instruction\nsh_id_rii_instruction\nsh_id_ri_instruction\nsw_erii_instruction\nsw_erir_instruction\nsw_id_rii_instruction\nsw_id_ri_instruction\nlabel\n\n\natn:\n[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 222, 2329, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 4, 24, 9, 24, 4, 25, 9, 25, 4, 26, 9, 26, 4, 27, 9, 27, 4, 28, 9, 28, 4, 29, 9, 29, 4, 30, 9, 30, 4, 31, 9, 31, 4, 32, 9, 32, 4, 33, 9, 33, 4, 34, 9, 34, 4, 35, 9, 35, 4, 36, 9, 36, 4, 37, 9, 37, 4, 38, 9, 38, 4, 39, 9, 39, 4, 40, 9, 40, 4, 41, 9, 41, 4, 42, 9, 42, 4, 43, 9, 43, 4, 44, 9, 44, 4, 45, 9, 45, 4, 46, 9, 46, 4, 47, 9, 47, 4, 48, 9, 48, 4, 49, 9, 49, 4, 50, 9, 50, 4, 51, 9, 51, 4, 52, 9, 52, 4, 53, 9, 53, 4, 54, 9, 54, 4, 55, 9, 55, 4, 56, 9, 56, 4, 57, 9, 57, 4, 58, 9, 58, 4, 59, 9, 59, 4, 60, 9, 60, 4, 61, 9, 61, 4, 62, 9, 62, 4, 63, 9, 63, 4, 64, 9, 64, 4, 65, 9, 65, 4, 66, 9, 66, 4, 67, 9, 67, 4, 68, 9, 68, 4, 69, 9, 69, 4, 70, 9, 70, 4, 71, 9, 71, 4, 72, 9, 72, 4, 73, 9, 73, 4, 74, 9, 74, 4, 75, 9, 75, 4, 76, 9, 76, 4, 77, 9, 77, 4, 78, 9, 78, 4, 79, 9, 79, 4, 80, 9, 80, 4, 81, 9, 81, 4, 82, 9, 82, 4, 83, 9, 83, 4, 84, 9, 84, 4, 85, 9, 85, 4, 86, 9, 86, 4, 87, 9, 87, 4, 88, 9, 88, 4, 89, 9, 89, 4, 90, 9, 90, 4, 91, 9, 91, 4, 92, 9, 92, 4, 93, 9, 93, 4, 94, 9, 94, 4, 95, 9, 95, 4, 96, 9, 96, 4, 97, 9, 97, 4, 98, 9, 98, 4, 99, 9, 99, 4, 100, 9, 100, 4, 101, 9, 101, 4, 102, 9, 102, 4, 103, 9, 103, 4, 104, 9, 104, 4, 105, 9, 105, 4, 106, 9, 106, 4, 107, 9, 107, 4, 108, 9, 108, 4, 109, 9, 109, 4, 110, 9, 110, 4, 111, 9, 111, 4, 112, 9, 112, 4, 113, 9, 113, 4, 114, 9, 114, 4, 115, 9, 115, 4, 116, 9, 116, 4, 117, 9, 117, 4, 118, 9, 118, 4, 119, 9, 119, 4, 120, 9, 120, 4, 121, 9, 121, 4, 122, 9, 122, 4, 123, 9, 123, 4, 124, 9, 124, 4, 125, 9, 125, 4, 126, 9, 126, 4, 127, 9, 127, 4, 128, 9, 128, 4, 129, 9, 129, 4, 130, 9, 130, 4, 131, 9, 131, 4, 132, 9, 132, 4, 133, 9, 133, 4, 134, 9, 134, 4, 135, 9, 135, 4, 136, 9, 136, 4, 137, 9, 137, 4, 138, 9, 138, 4, 139, 9, 139, 4, 140, 9, 140, 4, 141, 9, 141, 4, 142, 9, 142, 4, 143, 9, 143, 4, 144, 9, 144, 4, 145, 9, 145, 4, 146, 9, 146, 4, 147, 9, 147, 4, 148, 9, 148, 4, 149, 9, 149, 4, 150, 9, 150, 4, 151, 9, 151, 4, 152, 9, 152, 4, 153, 9, 153, 4, 154, 9, 154, 4, 155, 9, 155, 4, 156, 9, 156, 4, 157, 9, 157, 4, 158, 9, 158, 4, 159, 9, 159, 4, 160, 9, 160, 4, 161, 9, 161, 4, 162, 9, 162, 4, 163, 9, 163, 4, 164, 9, 164, 4, 165, 9, 165, 4, 166, 9, 166, 4, 167, 9, 167, 4, 168, 9, 168, 4, 169, 9, 169, 4, 170, 9, 170, 4, 171, 9, 171, 4, 172, 9, 172, 4, 173, 9, 173, 4, 174, 9, 174, 4, 175, 9, 175, 4, 176, 9, 176, 4, 177, 9, 177, 4, 178, 9, 178, 4, 179, 9, 179, 4, 180, 9, 180, 4, 181, 9, 181, 4, 182, 9, 182, 4, 183, 9, 183, 4, 184, 9, 184, 4, 185, 9, 185, 4, 186, 9, 186, 4, 187, 9, 187, 4, 188, 9, 188, 4, 189, 9, 189, 4, 190, 9, 190, 4, 191, 9, 191, 4, 192, 9, 192, 4, 193, 9, 193, 4, 194, 9, 194, 4, 195, 9, 195, 4, 196, 9, 196, 4, 197, 9, 197, 4, 198, 9, 198, 4, 199, 9, 199, 4, 200, 9, 200, 4, 201, 9, 201, 4, 202, 9, 202, 4, 203, 9, 203, 4, 204, 9, 204, 4, 205, 9, 205, 4, 206, 9, 206, 4, 207, 9, 207, 4, 208, 9, 208, 4, 209, 9, 209, 4, 210, 9, 210, 4, 211, 9, 211, 4, 212, 9, 212, 4, 213, 9, 213, 4, 214, 9, 214, 4, 215, 9, 215, 4, 216, 9, 216, 4, 217, 9, 217, 4, 218, 9, 218, 4, 219, 9, 219, 4, 220, 9, 220, 4, 221, 9, 221, 4, 222, 9, 222, 4, 223, 9, 223, 4, 224, 9, 224, 4, 225, 9, 225, 3, 2, 3, 2, 3, 2, 7, 2, 454, 10, 2, 12, 2, 14, 2, 457, 11, 2, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 3, 4, 3, 4, 3, 4, 3, 5, 3, 5, 3, 5, 5, 5, 470, 10, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 3, 9, 3, 10, 3, 10, 3, 11, 3, 11, 3, 12, 3, 12, 3, 13, 3, 13, 3, 14, 3, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 3, 20, 3, 20, 3, 21, 3, 21, 3, 22, 3, 22, 3, 23, 3, 23, 3, 24, 3, 24, 5, 24, 510, 10, 24, 3, 25, 3, 25, 3, 25, 5, 25, 515, 10, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 28, 3, 28, 3, 28, 5, 28, 528, 10, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 5, 29, 555, 10, 29, 3, 30, 3, 30, 3, 30, 3, 31, 3, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 33, 3, 33, 3, 33, 3, 33, 3, 34, 3, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 35, 3, 35, 3, 36, 3, 36, 3, 36, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 38, 3, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 39, 3, 40, 3, 40, 3, 40, 3, 40, 3, 40, 3, 40, 3, 40, 3, 40, 3, 40, 5, 40, 605, 10, 40, 3, 41, 3, 41, 3, 41, 3, 41, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 5, 42, 632, 10, 42, 3, 43, 3, 43, 3, 43, 3, 43, 3, 44, 3, 44, 3, 44, 3, 44, 3, 45, 3, 45, 3, 45, 3, 45, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 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  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assembly.tokens",
    "content": "T__0=1\nT__1=2\nT__2=3\nT__3=4\nT__4=5\nACQUIRE=6\nRELEASE=7\nBOOT=8\nRESUME=9\nADD=10\nADDC=11\nAND=12\nANDN=13\nASR=14\nCMPB4=15\nLSL=16\nLSL1=17\nLSL1X=18\nLSLX=19\nLSR=20\nLSR1=21\nLSR1X=22\nLSRX=23\nMUL_SH_SH=24\nMUL_SH_SL=25\nMUL_SH_UH=26\nMUL_SH_UL=27\nMUL_SL_SH=28\nMUL_SL_SL=29\nMUL_SL_UH=30\nMUL_SL_UL=31\nMUL_UH_UH=32\nMUL_UH_UL=33\nMUL_UL_UH=34\nMUL_UL_UL=35\nNAND=36\nNOR=37\nNXOR=38\nOR=39\nORN=40\nROL=41\nROR=42\nRSUB=43\nRSUBC=44\nSUB=45\nSUBC=46\nXOR=47\nCALL=48\nHASH=49\nCAO=50\nCLO=51\nCLS=52\nCLZ=53\nEXTSB=54\nEXTSH=55\nEXTUB=56\nEXTUH=57\nSATS=58\nTIME_CFG=59\nDIV_STEP=60\nMUL_STEP=61\nLSL_ADD=62\nLSL_SUB=63\nLSR_ADD=64\nROL_ADD=65\nROR_ADD=66\nTIME=67\nNOP=68\nSTOP=69\nFAULT=70\nMOVD=71\nSWAPD=72\nLBS=73\nLBU=74\nLD=75\nLHS=76\nLHU=77\nLW=78\nSB=79\nSB_ID=80\nSD=81\nSD_ID=82\nSH=83\nSH_ID=84\nSW=85\nSW_ID=86\nLDMA=87\nLDMAI=88\nSDMA=89\nMOVE=90\nNEG=91\nNOT=92\nBKP=93\nJEQ=94\nJNEQ=95\nJZ=96\nJNZ=97\nJLTU=98\nJGTU=99\nJLEU=100\nJGEU=101\nJLTS=102\nJGTS=103\nJLES=104\nJGES=105\nJUMP=106\nATOMIC=107\nBSS=108\nDATA=109\nDEBUG_ABBREV=110\nDEBUG_FRAME=111\nDEBUG_INFO=112\nDEBUG_LINE=113\nDEBUG_LOC=114\nDEBUG_RANGES=115\nDEBUG_STR=116\nDPU_HOST=117\nMRAM=118\nRODATA=119\nSTACK_SIZES=120\nTEXT_SECTION=121\nPROGBITS=122\nNOBITS=123\nFUNCTION=124\nOBJECT=125\nTRUE=126\nFALSE=127\nZ=128\nNZ=129\nE=130\nO=131\nPL=132\nMI=133\nOV=134\nNOV=135\nC=136\nNC=137\nSZ=138\nSNZ=139\nSPL=140\nSMI=141\nSO=142\nSE=143\nNC5=144\nNC6=145\nNC7=146\nNC8=147\nNC9=148\nNC10=149\nNC11=150\nNC12=151\nNC13=152\nNC14=153\nMAX=154\nNMAX=155\nSH32=156\nNSH32=157\nEQ=158\nNEQ=159\nLTU=160\nLEU=161\nGTU=162\nGEU=163\nLTS=164\nLES=165\nGTS=166\nGES=167\nXZ=168\nXNZ=169\nXLEU=170\nXGTU=171\nXLES=172\nXGTS=173\nSMALL=174\nLARGE=175\nLITTLE=176\nBIG=177\nZERO_REGISTER=178\nONE=179\nID=180\nID2=181\nID4=182\nID8=183\nLNEG=184\nMNEG=185\nADDRSIG=186\nADDRSIG_SYM=187\nASCII=188\nASCIZ=189\nBYTE=190\nCFI_DEF_CFA_OFFSET=191\nCFI_ENDPROC=192\nCFI_OFFSET=193\nCFI_SECTIONS=194\nCFI_STARTPROC=195\nFILE=196\nGLOBL=197\nLOC=198\nLONG=199\nP2ALIGN=200\nQUAD=201\nSECTION=202\nSET=203\nSHORT=204\nSIZE=205\nTEXT_DIRECTIVE=206\nTYPE=207\nWEAK=208\nZERO_DIRECTIVE=209\nIS_STMT=210\nPROLOGUE_END=211\nS_SUFFIX=212\nU_SUFFIX=213\nPositiveNumber=214\nGPRegister=215\nPairRegister=216\nIdentifier=217\nStringLiteral=218\nCOMMENT=219\nWHITE_SPACE=220\n'-'=1\n'0x'=2\n'+'=3\n','=4\n':'=5\n'$acquire'=6\n'$release'=7\n'$boot'=8\n'$resume'=9\n'$add'=10\n'$addc'=11\n'$and'=12\n'$andn'=13\n'$asr'=14\n'$cmpb4'=15\n'$lsl'=16\n'$lsl1'=17\n'$lsl1x'=18\n'$lslx'=19\n'$lsr'=20\n'$lsr1'=21\n'$lsr1x'=22\n'$lsrx'=23\n'$mul_sh_sh'=24\n'$mul_sh_sl'=25\n'$mul_sh_uh'=26\n'$mul_sh_ul'=27\n'$mul_sl_sh'=28\n'$mul_sl_sl'=29\n'$mul_sl_uh'=30\n'$mul_sl_ul'=31\n'$mul_uh_uh'=32\n'$mul_uh_ul'=33\n'$mul_ul_uh'=34\n'$mul_ul_ul'=35\n'$nand'=36\n'$nor'=37\n'$nxor'=38\n'$or'=39\n'$orn'=40\n'$rol'=41\n'$ror'=42\n'$rsub'=43\n'$rsubc'=44\n'$sub'=45\n'$subc'=46\n'$xor'=47\n'$call'=48\n'$hash'=49\n'$cao'=50\n'$clo'=51\n'$cls'=52\n'$clz'=53\n'$extsb'=54\n'$extsh'=55\n'$extub'=56\n'$extuh'=57\n'$sats'=58\n'$time_cfg'=59\n'$div_step'=60\n'$mul_step'=61\n'$lsl_add'=62\n'$lsl_sub'=63\n'$lsr_add'=64\n'$rol_add'=65\n'$ror_add'=66\n'$time'=67\n'$nop'=68\n'$stop'=69\n'$fault'=70\n'$movd'=71\n'$swapd'=72\n'$lbs'=73\n'$lbu'=74\n'$ld'=75\n'$lhs'=76\n'$lhu'=77\n'$lw'=78\n'$sb'=79\n'$sb_id'=80\n'$sd'=81\n'$sd_id'=82\n'$sh'=83\n'$sh_id'=84\n'$sw'=85\n'$sw_id'=86\n'$ldma'=87\n'$ldmai'=88\n'$sdma'=89\n'$move'=90\n'$neg'=91\n'$not'=92\n'$bkp'=93\n'$jeq'=94\n'$jneq'=95\n'$jz'=96\n'$jnz'=97\n'$jltu'=98\n'$jgtu'=99\n'$jleu'=100\n'$jgeu'=101\n'$jlts'=102\n'$jgts'=103\n'$jles'=104\n'$jges'=105\n'$jump'=106\n'%atomic'=107\n'%bss'=108\n'%data'=109\n'%debug_abbrev'=110\n'%debug_frame'=111\n'%debug_info'=112\n'%debug_line'=113\n'%debug_loc'=114\n'%debug_ranges'=115\n'%debug_str'=116\n'%dpu_host'=117\n'%mram'=118\n'%rodata'=119\n'%stack_sizes'=120\n'%text'=121\n'@progbits'=122\n'@nobits'=123\n'@function'=124\n'@object'=125\n'true'=126\n'false'=127\n'z'=128\n'nz'=129\n'e'=130\n'o'=131\n'pl'=132\n'mi'=133\n'ov'=134\n'nov'=135\n'c'=136\n'nc'=137\n'sz'=138\n'snz'=139\n'spl'=140\n'smi'=141\n'so'=142\n'se'=143\n'nc5'=144\n'nc6'=145\n'nc7'=146\n'nc8'=147\n'nc9'=148\n'nc10'=149\n'nc11'=150\n'nc12'=151\n'nc13'=152\n'nc14'=153\n'max'=154\n'nmax'=155\n'sh32'=156\n'nsh32'=157\n'eq'=158\n'neq'=159\n'ltu'=160\n'leu'=161\n'gtu'=162\n'geu'=163\n'lts'=164\n'les'=165\n'gts'=166\n'ges'=167\n'xz'=168\n'xnz'=169\n'xleu'=170\n'xgtu'=171\n'xles'=172\n'xgts'=173\n'small'=174\n'large'=175\n'!little'=176\n'!big'=177\n'zero'=178\n'one'=179\n'id'=180\n'id2'=181\n'id4'=182\n'id8'=183\n'lneg'=184\n'mneg'=185\n'$addrsig'=186\n'$addrsig_sym'=187\n'$ascii'=188\n'$asciz'=189\n'$byte'=190\n'$cfi_def_cfa_offset'=191\n'$cfi_endproc'=192\n'$cfi_offset'=193\n'$cfi_sections'=194\n'$cfi_startproc'=195\n'$file'=196\n'$globl'=197\n'$loc'=198\n'$long'=199\n'$p2align'=200\n'$quad'=201\n'$section'=202\n'$set'=203\n'$short'=204\n'$size'=205\n'$text'=206\n'$type'=207\n'$weak'=208\n'$zero'=209\n'is_stmt'=210\n'prologue_end'=211\n'.s'=212\n'.u'=213\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assemblyLexer.interp",
    "content": "token literal names:\nnull\n'-'\n'0x'\n'+'\n','\n':'\n'$acquire'\n'$release'\n'$boot'\n'$resume'\n'$add'\n'$addc'\n'$and'\n'$andn'\n'$asr'\n'$cmpb4'\n'$lsl'\n'$lsl1'\n'$lsl1x'\n'$lslx'\n'$lsr'\n'$lsr1'\n'$lsr1x'\n'$lsrx'\n'$mul_sh_sh'\n'$mul_sh_sl'\n'$mul_sh_uh'\n'$mul_sh_ul'\n'$mul_sl_sh'\n'$mul_sl_sl'\n'$mul_sl_uh'\n'$mul_sl_ul'\n'$mul_uh_uh'\n'$mul_uh_ul'\n'$mul_ul_uh'\n'$mul_ul_ul'\n'$nand'\n'$nor'\n'$nxor'\n'$or'\n'$orn'\n'$rol'\n'$ror'\n'$rsub'\n'$rsubc'\n'$sub'\n'$subc'\n'$xor'\n'$call'\n'$hash'\n'$cao'\n'$clo'\n'$cls'\n'$clz'\n'$extsb'\n'$extsh'\n'$extub'\n'$extuh'\n'$sats'\n'$time_cfg'\n'$div_step'\n'$mul_step'\n'$lsl_add'\n'$lsl_sub'\n'$lsr_add'\n'$rol_add'\n'$ror_add'\n'$time'\n'$nop'\n'$stop'\n'$fault'\n'$movd'\n'$swapd'\n'$lbs'\n'$lbu'\n'$ld'\n'$lhs'\n'$lhu'\n'$lw'\n'$sb'\n'$sb_id'\n'$sd'\n'$sd_id'\n'$sh'\n'$sh_id'\n'$sw'\n'$sw_id'\n'$ldma'\n'$ldmai'\n'$sdma'\n'$move'\n'$neg'\n'$not'\n'$bkp'\n'$jeq'\n'$jneq'\n'$jz'\n'$jnz'\n'$jltu'\n'$jgtu'\n'$jleu'\n'$jgeu'\n'$jlts'\n'$jgts'\n'$jles'\n'$jges'\n'$jump'\n'%atomic'\n'%bss'\n'%data'\n'%debug_abbrev'\n'%debug_frame'\n'%debug_info'\n'%debug_line'\n'%debug_loc'\n'%debug_ranges'\n'%debug_str'\n'%dpu_host'\n'%mram'\n'%rodata'\n'%stack_sizes'\n'%text'\n'@progbits'\n'@nobits'\n'@function'\n'@object'\n'true'\n'false'\n'z'\n'nz'\n'e'\n'o'\n'pl'\n'mi'\n'ov'\n'nov'\n'c'\n'nc'\n'sz'\n'snz'\n'spl'\n'smi'\n'so'\n'se'\n'nc5'\n'nc6'\n'nc7'\n'nc8'\n'nc9'\n'nc10'\n'nc11'\n'nc12'\n'nc13'\n'nc14'\n'max'\n'nmax'\n'sh32'\n'nsh32'\n'eq'\n'neq'\n'ltu'\n'leu'\n'gtu'\n'geu'\n'lts'\n'les'\n'gts'\n'ges'\n'xz'\n'xnz'\n'xleu'\n'xgtu'\n'xles'\n'xgts'\n'small'\n'large'\n'!little'\n'!big'\n'zero'\n'one'\n'id'\n'id2'\n'id4'\n'id8'\n'lneg'\n'mneg'\n'$addrsig'\n'$addrsig_sym'\n'$ascii'\n'$asciz'\n'$byte'\n'$cfi_def_cfa_offset'\n'$cfi_endproc'\n'$cfi_offset'\n'$cfi_sections'\n'$cfi_startproc'\n'$file'\n'$globl'\n'$loc'\n'$long'\n'$p2align'\n'$quad'\n'$section'\n'$set'\n'$short'\n'$size'\n'$text'\n'$type'\n'$weak'\n'$zero'\n'is_stmt'\n'prologue_end'\n'.s'\n'.u'\nnull\nnull\nnull\nnull\nnull\nnull\nnull\n\ntoken symbolic names:\nnull\nnull\nnull\nnull\nnull\nnull\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nrule names:\nT__0\nT__1\nT__2\nT__3\nT__4\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nchannel names:\nDEFAULT_TOKEN_CHANNEL\nHIDDEN\n\nmode names:\nDEFAULT_MODE\n\natn:\n[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 222, 1850, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 4, 24, 9, 24, 4, 25, 9, 25, 4, 26, 9, 26, 4, 27, 9, 27, 4, 28, 9, 28, 4, 29, 9, 29, 4, 30, 9, 30, 4, 31, 9, 31, 4, 32, 9, 32, 4, 33, 9, 33, 4, 34, 9, 34, 4, 35, 9, 35, 4, 36, 9, 36, 4, 37, 9, 37, 4, 38, 9, 38, 4, 39, 9, 39, 4, 40, 9, 40, 4, 41, 9, 41, 4, 42, 9, 42, 4, 43, 9, 43, 4, 44, 9, 44, 4, 45, 9, 45, 4, 46, 9, 46, 4, 47, 9, 47, 4, 48, 9, 48, 4, 49, 9, 49, 4, 50, 9, 50, 4, 51, 9, 51, 4, 52, 9, 52, 4, 53, 9, 53, 4, 54, 9, 54, 4, 55, 9, 55, 4, 56, 9, 56, 4, 57, 9, 57, 4, 58, 9, 58, 4, 59, 9, 59, 4, 60, 9, 60, 4, 61, 9, 61, 4, 62, 9, 62, 4, 63, 9, 63, 4, 64, 9, 64, 4, 65, 9, 65, 4, 66, 9, 66, 4, 67, 9, 67, 4, 68, 9, 68, 4, 69, 9, 69, 4, 70, 9, 70, 4, 71, 9, 71, 4, 72, 9, 72, 4, 73, 9, 73, 4, 74, 9, 74, 4, 75, 9, 75, 4, 76, 9, 76, 4, 77, 9, 77, 4, 78, 9, 78, 4, 79, 9, 79, 4, 80, 9, 80, 4, 81, 9, 81, 4, 82, 9, 82, 4, 83, 9, 83, 4, 84, 9, 84, 4, 85, 9, 85, 4, 86, 9, 86, 4, 87, 9, 87, 4, 88, 9, 88, 4, 89, 9, 89, 4, 90, 9, 90, 4, 91, 9, 91, 4, 92, 9, 92, 4, 93, 9, 93, 4, 94, 9, 94, 4, 95, 9, 95, 4, 96, 9, 96, 4, 97, 9, 97, 4, 98, 9, 98, 4, 99, 9, 99, 4, 100, 9, 100, 4, 101, 9, 101, 4, 102, 9, 102, 4, 103, 9, 103, 4, 104, 9, 104, 4, 105, 9, 105, 4, 106, 9, 106, 4, 107, 9, 107, 4, 108, 9, 108, 4, 109, 9, 109, 4, 110, 9, 110, 4, 111, 9, 111, 4, 112, 9, 112, 4, 113, 9, 113, 4, 114, 9, 114, 4, 115, 9, 115, 4, 116, 9, 116, 4, 117, 9, 117, 4, 118, 9, 118, 4, 119, 9, 119, 4, 120, 9, 120, 4, 121, 9, 121, 4, 122, 9, 122, 4, 123, 9, 123, 4, 124, 9, 124, 4, 125, 9, 125, 4, 126, 9, 126, 4, 127, 9, 127, 4, 128, 9, 128, 4, 129, 9, 129, 4, 130, 9, 130, 4, 131, 9, 131, 4, 132, 9, 132, 4, 133, 9, 133, 4, 134, 9, 134, 4, 135, 9, 135, 4, 136, 9, 136, 4, 137, 9, 137, 4, 138, 9, 138, 4, 139, 9, 139, 4, 140, 9, 140, 4, 141, 9, 141, 4, 142, 9, 142, 4, 143, 9, 143, 4, 144, 9, 144, 4, 145, 9, 145, 4, 146, 9, 146, 4, 147, 9, 147, 4, 148, 9, 148, 4, 149, 9, 149, 4, 150, 9, 150, 4, 151, 9, 151, 4, 152, 9, 152, 4, 153, 9, 153, 4, 154, 9, 154, 4, 155, 9, 155, 4, 156, 9, 156, 4, 157, 9, 157, 4, 158, 9, 158, 4, 159, 9, 159, 4, 160, 9, 160, 4, 161, 9, 161, 4, 162, 9, 162, 4, 163, 9, 163, 4, 164, 9, 164, 4, 165, 9, 165, 4, 166, 9, 166, 4, 167, 9, 167, 4, 168, 9, 168, 4, 169, 9, 169, 4, 170, 9, 170, 4, 171, 9, 171, 4, 172, 9, 172, 4, 173, 9, 173, 4, 174, 9, 174, 4, 175, 9, 175, 4, 176, 9, 176, 4, 177, 9, 177, 4, 178, 9, 178, 4, 179, 9, 179, 4, 180, 9, 180, 4, 181, 9, 181, 4, 182, 9, 182, 4, 183, 9, 183, 4, 184, 9, 184, 4, 185, 9, 185, 4, 186, 9, 186, 4, 187, 9, 187, 4, 188, 9, 188, 4, 189, 9, 189, 4, 190, 9, 190, 4, 191, 9, 191, 4, 192, 9, 192, 4, 193, 9, 193, 4, 194, 9, 194, 4, 195, 9, 195, 4, 196, 9, 196, 4, 197, 9, 197, 4, 198, 9, 198, 4, 199, 9, 199, 4, 200, 9, 200, 4, 201, 9, 201, 4, 202, 9, 202, 4, 203, 9, 203, 4, 204, 9, 204, 4, 205, 9, 205, 4, 206, 9, 206, 4, 207, 9, 207, 4, 208, 9, 208, 4, 209, 9, 209, 4, 210, 9, 210, 4, 211, 9, 211, 4, 212, 9, 212, 4, 213, 9, 213, 4, 214, 9, 214, 4, 215, 9, 215, 4, 216, 9, 216, 4, 217, 9, 217, 4, 218, 9, 218, 4, 219, 9, 219, 4, 220, 9, 220, 4, 221, 9, 221, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 17, 3, 17, 3, 17, 3, 17, 3, 17, 3, 18, 3, 18, 3, 18, 3, 18, 3, 18, 3, 18, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 20, 3, 20, 3, 20, 3, 20, 3, 20, 3, 20, 3, 21, 3, 21, 3, 21, 3, 21, 3, 21, 3, 22, 3, 22, 3, 22, 3, 22, 3, 22, 3, 22, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 24, 3, 24, 3, 24, 3, 24, 3, 24, 3, 24, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 38, 3, 38, 3, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 39, 3, 39, 3, 39, 3, 39, 3, 40, 3, 40, 3, 40, 3, 40, 3, 41, 3, 41, 3, 41, 3, 41, 3, 41, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 43, 3, 43, 3, 43, 3, 43, 3, 43, 3, 44, 3, 44, 3, 44, 3, 44, 3, 44, 3, 44, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 47, 3, 47, 3, 47, 3, 47, 3, 47, 3, 47, 3, 48, 3, 48, 3, 48, 3, 48, 3, 48, 3, 49, 3, 49, 3, 49, 3, 49, 3, 49, 3, 49, 3, 50, 3, 50, 3, 50, 3, 50, 3, 50, 3, 50, 3, 51, 3, 51, 3, 51, 3, 51, 3, 51, 3, 52, 3, 52, 3, 52, 3, 52, 3, 52, 3, 53, 3, 53, 3, 53, 3, 53, 3, 53, 3, 54, 3, 54, 3, 54, 3, 54, 3, 54, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 59, 3, 59, 3, 59, 3, 59, 3, 59, 3, 59, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 68, 3, 68, 3, 68, 3, 68, 3, 68, 3, 68, 3, 69, 3, 69, 3, 69, 3, 69, 3, 69, 3, 70, 3, 70, 3, 70, 3, 70, 3, 70, 3, 70, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 72, 3, 72, 3, 72, 3, 72, 3, 72, 3, 72, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 74, 3, 74, 3, 74, 3, 74, 3, 74, 3, 75, 3, 75, 3, 75, 3, 75, 3, 75, 3, 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2, 1760, 1761, 7, 99, 2, 2, 1761, 1762, 7, 109, 2, 2, 1762, 418, 3, 2, 2, 2, 1763, 1764, 7, 38, 2, 2, 1764, 1765, 7, 124, 2, 2, 1765, 1766, 7, 103, 2, 2, 1766, 1767, 7, 116, 2, 2, 1767, 1768, 7, 113, 2, 2, 1768, 420, 3, 2, 2, 2, 1769, 1770, 7, 107, 2, 2, 1770, 1771, 7, 117, 2, 2, 1771, 1772, 7, 97, 2, 2, 1772, 1773, 7, 117, 2, 2, 1773, 1774, 7, 118, 2, 2, 1774, 1775, 7, 111, 2, 2, 1775, 1776, 7, 118, 2, 2, 1776, 422, 3, 2, 2, 2, 1777, 1778, 7, 114, 2, 2, 1778, 1779, 7, 116, 2, 2, 1779, 1780, 7, 113, 2, 2, 1780, 1781, 7, 110, 2, 2, 1781, 1782, 7, 113, 2, 2, 1782, 1783, 7, 105, 2, 2, 1783, 1784, 7, 119, 2, 2, 1784, 1785, 7, 103, 2, 2, 1785, 1786, 7, 97, 2, 2, 1786, 1787, 7, 103, 2, 2, 1787, 1788, 7, 112, 2, 2, 1788, 1789, 7, 102, 2, 2, 1789, 424, 3, 2, 2, 2, 1790, 1791, 7, 48, 2, 2, 1791, 1792, 7, 117, 2, 2, 1792, 426, 3, 2, 2, 2, 1793, 1794, 7, 48, 2, 2, 1794, 1795, 7, 119, 2, 2, 1795, 428, 3, 2, 2, 2, 1796, 1798, 9, 2, 2, 2, 1797, 1796, 3, 2, 2, 2, 1798, 1799, 3, 2, 2, 2, 1799, 1797, 3, 2, 2, 2, 1799, 1800, 3, 2, 2, 2, 1800, 430, 3, 2, 2, 2, 1801, 1803, 7, 116, 2, 2, 1802, 1804, 9, 2, 2, 2, 1803, 1802, 3, 2, 2, 2, 1804, 1805, 3, 2, 2, 2, 1805, 1803, 3, 2, 2, 2, 1805, 1806, 3, 2, 2, 2, 1806, 432, 3, 2, 2, 2, 1807, 1809, 7, 102, 2, 2, 1808, 1810, 9, 2, 2, 2, 1809, 1808, 3, 2, 2, 2, 1810, 1811, 3, 2, 2, 2, 1811, 1809, 3, 2, 2, 2, 1811, 1812, 3, 2, 2, 2, 1812, 434, 3, 2, 2, 2, 1813, 1815, 9, 3, 2, 2, 1814, 1813, 3, 2, 2, 2, 1815, 1819, 3, 2, 2, 2, 1816, 1818, 9, 4, 2, 2, 1817, 1816, 3, 2, 2, 2, 1818, 1821, 3, 2, 2, 2, 1819, 1817, 3, 2, 2, 2, 1819, 1820, 3, 2, 2, 2, 1820, 436, 3, 2, 2, 2, 1821, 1819, 3, 2, 2, 2, 1822, 1827, 7, 36, 2, 2, 1823, 1826, 9, 5, 2, 2, 1824, 1826, 5, 441, 221, 2, 1825, 1823, 3, 2, 2, 2, 1825, 1824, 3, 2, 2, 2, 1826, 1829, 3, 2, 2, 2, 1827, 1825, 3, 2, 2, 2, 1827, 1828, 3, 2, 2, 2, 1828, 1830, 3, 2, 2, 2, 1829, 1827, 3, 2, 2, 2, 1830, 1831, 7, 36, 2, 2, 1831, 438, 3, 2, 2, 2, 1832, 1833, 7, 49, 2, 2, 1833, 1834, 7, 49, 2, 2, 1834, 1838, 3, 2, 2, 2, 1835, 1837, 10, 6, 2, 2, 1836, 1835, 3, 2, 2, 2, 1837, 1840, 3, 2, 2, 2, 1838, 1836, 3, 2, 2, 2, 1838, 1839, 3, 2, 2, 2, 1839, 1841, 3, 2, 2, 2, 1840, 1838, 3, 2, 2, 2, 1841, 1842, 8, 220, 2, 2, 1842, 440, 3, 2, 2, 2, 1843, 1845, 9, 7, 2, 2, 1844, 1843, 3, 2, 2, 2, 1845, 1846, 3, 2, 2, 2, 1846, 1844, 3, 2, 2, 2, 1846, 1847, 3, 2, 2, 2, 1847, 1848, 3, 2, 2, 2, 1848, 1849, 8, 221, 2, 2, 1849, 442, 3, 2, 2, 2, 13, 2, 1799, 1805, 1811, 1814, 1817, 1819, 1825, 1827, 1838, 1846, 3, 8, 2, 2]"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assemblyLexer.java",
    "content": "// Generated from /home/bongjoon/upmem_compiler/src/parser_/grammar/assembly.g4 by ANTLR 4.8\nimport org.antlr.v4.runtime.Lexer;\nimport org.antlr.v4.runtime.CharStream;\nimport org.antlr.v4.runtime.Token;\nimport org.antlr.v4.runtime.TokenStream;\nimport org.antlr.v4.runtime.*;\nimport org.antlr.v4.runtime.atn.*;\nimport org.antlr.v4.runtime.dfa.DFA;\nimport org.antlr.v4.runtime.misc.*;\n\n@SuppressWarnings({\"all\", \"warnings\", \"unchecked\", \"unused\", \"cast\"})\npublic class assemblyLexer extends Lexer {\n\tstatic { RuntimeMetaData.checkVersion(\"4.8\", RuntimeMetaData.VERSION); }\n\n\tprotected static final DFA[] _decisionToDFA;\n\tprotected static final PredictionContextCache _sharedContextCache =\n\t\tnew PredictionContextCache();\n\tpublic static final int\n\t\tT__0=1, T__1=2, T__2=3, T__3=4, T__4=5, ACQUIRE=6, RELEASE=7, BOOT=8, \n\t\tRESUME=9, ADD=10, ADDC=11, AND=12, ANDN=13, ASR=14, CMPB4=15, LSL=16, \n\t\tLSL1=17, LSL1X=18, LSLX=19, LSR=20, LSR1=21, LSR1X=22, LSRX=23, MUL_SH_SH=24, \n\t\tMUL_SH_SL=25, MUL_SH_UH=26, MUL_SH_UL=27, MUL_SL_SH=28, MUL_SL_SL=29, \n\t\tMUL_SL_UH=30, MUL_SL_UL=31, MUL_UH_UH=32, MUL_UH_UL=33, MUL_UL_UH=34, \n\t\tMUL_UL_UL=35, NAND=36, NOR=37, NXOR=38, OR=39, ORN=40, ROL=41, ROR=42, \n\t\tRSUB=43, RSUBC=44, SUB=45, SUBC=46, XOR=47, CALL=48, HASH=49, CAO=50, \n\t\tCLO=51, CLS=52, CLZ=53, EXTSB=54, EXTSH=55, EXTUB=56, EXTUH=57, SATS=58, \n\t\tTIME_CFG=59, DIV_STEP=60, MUL_STEP=61, LSL_ADD=62, LSL_SUB=63, LSR_ADD=64, \n\t\tROL_ADD=65, ROR_ADD=66, TIME=67, NOP=68, STOP=69, FAULT=70, MOVD=71, SWAPD=72, \n\t\tLBS=73, LBU=74, LD=75, LHS=76, LHU=77, LW=78, SB=79, SB_ID=80, SD=81, \n\t\tSD_ID=82, SH=83, SH_ID=84, SW=85, SW_ID=86, LDMA=87, LDMAI=88, SDMA=89, \n\t\tMOVE=90, NEG=91, NOT=92, BKP=93, JEQ=94, JNEQ=95, JZ=96, JNZ=97, JLTU=98, \n\t\tJGTU=99, JLEU=100, JGEU=101, JLTS=102, JGTS=103, JLES=104, JGES=105, JUMP=106, \n\t\tATOMIC=107, BSS=108, DATA=109, DEBUG_ABBREV=110, DEBUG_FRAME=111, DEBUG_INFO=112, \n\t\tDEBUG_LINE=113, DEBUG_LOC=114, DEBUG_RANGES=115, DEBUG_STR=116, DPU_HOST=117, \n\t\tMRAM=118, RODATA=119, STACK_SIZES=120, TEXT_SECTION=121, PROGBITS=122, \n\t\tNOBITS=123, FUNCTION=124, OBJECT=125, TRUE=126, FALSE=127, Z=128, NZ=129, \n\t\tE=130, O=131, PL=132, MI=133, OV=134, NOV=135, C=136, NC=137, SZ=138, \n\t\tSNZ=139, SPL=140, SMI=141, SO=142, SE=143, NC5=144, NC6=145, NC7=146, \n\t\tNC8=147, NC9=148, NC10=149, NC11=150, NC12=151, NC13=152, NC14=153, MAX=154, \n\t\tNMAX=155, SH32=156, NSH32=157, EQ=158, NEQ=159, LTU=160, LEU=161, GTU=162, \n\t\tGEU=163, LTS=164, LES=165, GTS=166, GES=167, XZ=168, XNZ=169, XLEU=170, \n\t\tXGTU=171, XLES=172, XGTS=173, SMALL=174, LARGE=175, LITTLE=176, BIG=177, \n\t\tZERO_REGISTER=178, ONE=179, ID=180, ID2=181, ID4=182, ID8=183, LNEG=184, \n\t\tMNEG=185, ADDRSIG=186, ADDRSIG_SYM=187, ASCII=188, ASCIZ=189, BYTE=190, \n\t\tCFI_DEF_CFA_OFFSET=191, CFI_ENDPROC=192, CFI_OFFSET=193, CFI_SECTIONS=194, \n\t\tCFI_STARTPROC=195, FILE=196, GLOBL=197, LOC=198, LONG=199, P2ALIGN=200, \n\t\tQUAD=201, SECTION=202, SET=203, SHORT=204, SIZE=205, TEXT_DIRECTIVE=206, \n\t\tTYPE=207, WEAK=208, ZERO_DIRECTIVE=209, IS_STMT=210, PROLOGUE_END=211, \n\t\tS_SUFFIX=212, U_SUFFIX=213, PositiveNumber=214, GPRegister=215, PairRegister=216, \n\t\tIdentifier=217, StringLiteral=218, COMMENT=219, WHITE_SPACE=220;\n\tpublic static String[] channelNames = {\n\t\t\"DEFAULT_TOKEN_CHANNEL\", \"HIDDEN\"\n\t};\n\n\tpublic static String[] modeNames = {\n\t\t\"DEFAULT_MODE\"\n\t};\n\n\tprivate static String[] makeRuleNames() {\n\t\treturn new String[] {\n\t\t\t\"T__0\", \"T__1\", \"T__2\", \"T__3\", \"T__4\", \"ACQUIRE\", \"RELEASE\", \"BOOT\", \n\t\t\t\"RESUME\", \"ADD\", \"ADDC\", \"AND\", \"ANDN\", \"ASR\", \"CMPB4\", \"LSL\", \"LSL1\", \n\t\t\t\"LSL1X\", \"LSLX\", \"LSR\", \"LSR1\", \"LSR1X\", \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \n\t\t\t\"MUL_SH_UH\", \"MUL_SH_UL\", \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \n\t\t\t\"MUL_UH_UH\", \"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \"NAND\", \"NOR\", \"NXOR\", \n\t\t\t\"OR\", \"ORN\", \"ROL\", \"ROR\", \"RSUB\", \"RSUBC\", \"SUB\", \"SUBC\", \"XOR\", \"CALL\", \n\t\t\t\"HASH\", \"CAO\", \"CLO\", \"CLS\", \"CLZ\", \"EXTSB\", \"EXTSH\", \"EXTUB\", \"EXTUH\", \n\t\t\t\"SATS\", \"TIME_CFG\", \"DIV_STEP\", \"MUL_STEP\", \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \n\t\t\t\"ROL_ADD\", \"ROR_ADD\", \"TIME\", \"NOP\", \"STOP\", \"FAULT\", \"MOVD\", \"SWAPD\", \n\t\t\t\"LBS\", \"LBU\", \"LD\", \"LHS\", \"LHU\", \"LW\", \"SB\", \"SB_ID\", \"SD\", \"SD_ID\", \n\t\t\t\"SH\", \"SH_ID\", \"SW\", \"SW_ID\", \"LDMA\", \"LDMAI\", \"SDMA\", \"MOVE\", \"NEG\", \n\t\t\t\"NOT\", \"BKP\", \"JEQ\", \"JNEQ\", \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \n\t\t\t\"JLTS\", \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \"DATA\", \"DEBUG_ABBREV\", \n\t\t\t\"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \"DEBUG_LOC\", \"DEBUG_RANGES\", \n\t\t\t\"DEBUG_STR\", \"DPU_HOST\", \"MRAM\", \"RODATA\", \"STACK_SIZES\", \"TEXT_SECTION\", \n\t\t\t\"PROGBITS\", \"NOBITS\", \"FUNCTION\", \"OBJECT\", \"TRUE\", \"FALSE\", \"Z\", \"NZ\", \n\t\t\t\"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \"C\", \"NC\", \"SZ\", \"SNZ\", \"SPL\", \"SMI\", \n\t\t\t\"SO\", \"SE\", \"NC5\", \"NC6\", \"NC7\", \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \n\t\t\t\"NC13\", \"NC14\", \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \"LTU\", \"LEU\", \n\t\t\t\"GTU\", \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \"XZ\", \"XNZ\", \"XLEU\", \"XGTU\", \n\t\t\t\"XLES\", \"XGTS\", \"SMALL\", \"LARGE\", \"LITTLE\", \"BIG\", \"ZERO_REGISTER\", \"ONE\", \n\t\t\t\"ID\", \"ID2\", \"ID4\", \"ID8\", \"LNEG\", \"MNEG\", \"ADDRSIG\", \"ADDRSIG_SYM\", \n\t\t\t\"ASCII\", \"ASCIZ\", \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \"CFI_ENDPROC\", \"CFI_OFFSET\", \n\t\t\t\"CFI_SECTIONS\", \"CFI_STARTPROC\", \"FILE\", \"GLOBL\", \"LOC\", \"LONG\", \"P2ALIGN\", \n\t\t\t\"QUAD\", \"SECTION\", \"SET\", \"SHORT\", \"SIZE\", \"TEXT_DIRECTIVE\", \"TYPE\", \n\t\t\t\"WEAK\", \"ZERO_DIRECTIVE\", \"IS_STMT\", \"PROLOGUE_END\", \"S_SUFFIX\", \"U_SUFFIX\", \n\t\t\t\"PositiveNumber\", \"GPRegister\", \"PairRegister\", \"Identifier\", \"StringLiteral\", \n\t\t\t\"COMMENT\", \"WHITE_SPACE\"\n\t\t};\n\t}\n\tpublic static final String[] ruleNames = makeRuleNames();\n\n\tprivate static String[] makeLiteralNames() {\n\t\treturn new String[] {\n\t\t\tnull, \"'-'\", \"'0x'\", \"'+'\", \"','\", \"':'\", \"'$acquire'\", \"'$release'\", \n\t\t\t\"'$boot'\", \"'$resume'\", \"'$add'\", \"'$addc'\", \"'$and'\", \"'$andn'\", \"'$asr'\", \n\t\t\t\"'$cmpb4'\", \"'$lsl'\", \"'$lsl1'\", \"'$lsl1x'\", \"'$lslx'\", \"'$lsr'\", \"'$lsr1'\", \n\t\t\t\"'$lsr1x'\", \"'$lsrx'\", \"'$mul_sh_sh'\", \"'$mul_sh_sl'\", \"'$mul_sh_uh'\", \n\t\t\t\"'$mul_sh_ul'\", \"'$mul_sl_sh'\", \"'$mul_sl_sl'\", \"'$mul_sl_uh'\", \"'$mul_sl_ul'\", \n\t\t\t\"'$mul_uh_uh'\", \"'$mul_uh_ul'\", \"'$mul_ul_uh'\", \"'$mul_ul_ul'\", \"'$nand'\", \n\t\t\t\"'$nor'\", \"'$nxor'\", \"'$or'\", \"'$orn'\", \"'$rol'\", \"'$ror'\", \"'$rsub'\", \n\t\t\t\"'$rsubc'\", \"'$sub'\", \"'$subc'\", \"'$xor'\", \"'$call'\", \"'$hash'\", \"'$cao'\", \n\t\t\t\"'$clo'\", \"'$cls'\", \"'$clz'\", \"'$extsb'\", \"'$extsh'\", \"'$extub'\", \"'$extuh'\", \n\t\t\t\"'$sats'\", \"'$time_cfg'\", \"'$div_step'\", \"'$mul_step'\", \"'$lsl_add'\", \n\t\t\t\"'$lsl_sub'\", \"'$lsr_add'\", \"'$rol_add'\", \"'$ror_add'\", \"'$time'\", \"'$nop'\", \n\t\t\t\"'$stop'\", \"'$fault'\", \"'$movd'\", \"'$swapd'\", \"'$lbs'\", \"'$lbu'\", \"'$ld'\", \n\t\t\t\"'$lhs'\", \"'$lhu'\", \"'$lw'\", \"'$sb'\", \"'$sb_id'\", \"'$sd'\", \"'$sd_id'\", \n\t\t\t\"'$sh'\", \"'$sh_id'\", \"'$sw'\", \"'$sw_id'\", \"'$ldma'\", \"'$ldmai'\", \"'$sdma'\", \n\t\t\t\"'$move'\", \"'$neg'\", \"'$not'\", \"'$bkp'\", \"'$jeq'\", \"'$jneq'\", \"'$jz'\", \n\t\t\t\"'$jnz'\", \"'$jltu'\", \"'$jgtu'\", \"'$jleu'\", \"'$jgeu'\", \"'$jlts'\", \"'$jgts'\", \n\t\t\t\"'$jles'\", \"'$jges'\", \"'$jump'\", \"'%atomic'\", \"'%bss'\", \"'%data'\", \"'%debug_abbrev'\", \n\t\t\t\"'%debug_frame'\", \"'%debug_info'\", \"'%debug_line'\", \"'%debug_loc'\", \"'%debug_ranges'\", \n\t\t\t\"'%debug_str'\", \"'%dpu_host'\", \"'%mram'\", \"'%rodata'\", \"'%stack_sizes'\", \n\t\t\t\"'%text'\", \"'@progbits'\", \"'@nobits'\", \"'@function'\", \"'@object'\", \"'true'\", \n\t\t\t\"'false'\", \"'z'\", \"'nz'\", \"'e'\", \"'o'\", \"'pl'\", \"'mi'\", \"'ov'\", \"'nov'\", \n\t\t\t\"'c'\", \"'nc'\", \"'sz'\", \"'snz'\", \"'spl'\", \"'smi'\", \"'so'\", \"'se'\", \"'nc5'\", \n\t\t\t\"'nc6'\", \"'nc7'\", \"'nc8'\", \"'nc9'\", \"'nc10'\", \"'nc11'\", \"'nc12'\", \"'nc13'\", \n\t\t\t\"'nc14'\", \"'max'\", \"'nmax'\", \"'sh32'\", \"'nsh32'\", \"'eq'\", \"'neq'\", \"'ltu'\", \n\t\t\t\"'leu'\", \"'gtu'\", \"'geu'\", \"'lts'\", \"'les'\", \"'gts'\", \"'ges'\", \"'xz'\", \n\t\t\t\"'xnz'\", \"'xleu'\", \"'xgtu'\", \"'xles'\", \"'xgts'\", \"'small'\", \"'large'\", \n\t\t\t\"'!little'\", \"'!big'\", \"'zero'\", \"'one'\", \"'id'\", \"'id2'\", \"'id4'\", \"'id8'\", \n\t\t\t\"'lneg'\", \"'mneg'\", \"'$addrsig'\", \"'$addrsig_sym'\", \"'$ascii'\", \"'$asciz'\", \n\t\t\t\"'$byte'\", \"'$cfi_def_cfa_offset'\", \"'$cfi_endproc'\", \"'$cfi_offset'\", \n\t\t\t\"'$cfi_sections'\", \"'$cfi_startproc'\", \"'$file'\", \"'$globl'\", \"'$loc'\", \n\t\t\t\"'$long'\", \"'$p2align'\", \"'$quad'\", \"'$section'\", \"'$set'\", \"'$short'\", \n\t\t\t\"'$size'\", \"'$text'\", \"'$type'\", \"'$weak'\", \"'$zero'\", \"'is_stmt'\", \"'prologue_end'\", \n\t\t\t\"'.s'\", \"'.u'\"\n\t\t};\n\t}\n\tprivate static final String[] _LITERAL_NAMES = makeLiteralNames();\n\tprivate static String[] makeSymbolicNames() {\n\t\treturn new String[] {\n\t\t\tnull, null, null, null, null, null, \"ACQUIRE\", \"RELEASE\", \"BOOT\", \"RESUME\", \n\t\t\t\"ADD\", \"ADDC\", \"AND\", \"ANDN\", \"ASR\", \"CMPB4\", \"LSL\", \"LSL1\", \"LSL1X\", \n\t\t\t\"LSLX\", \"LSR\", \"LSR1\", \"LSR1X\", \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \"MUL_SH_UH\", \n\t\t\t\"MUL_SH_UL\", \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \"MUL_UH_UH\", \n\t\t\t\"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \"NAND\", \"NOR\", \"NXOR\", \"OR\", \"ORN\", \n\t\t\t\"ROL\", \"ROR\", \"RSUB\", \"RSUBC\", \"SUB\", \"SUBC\", \"XOR\", \"CALL\", \"HASH\", \n\t\t\t\"CAO\", \"CLO\", \"CLS\", \"CLZ\", \"EXTSB\", \"EXTSH\", \"EXTUB\", \"EXTUH\", \"SATS\", \n\t\t\t\"TIME_CFG\", \"DIV_STEP\", \"MUL_STEP\", \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \n\t\t\t\"ROL_ADD\", \"ROR_ADD\", \"TIME\", \"NOP\", \"STOP\", \"FAULT\", \"MOVD\", \"SWAPD\", \n\t\t\t\"LBS\", \"LBU\", \"LD\", \"LHS\", \"LHU\", \"LW\", \"SB\", \"SB_ID\", \"SD\", \"SD_ID\", \n\t\t\t\"SH\", \"SH_ID\", \"SW\", \"SW_ID\", \"LDMA\", \"LDMAI\", \"SDMA\", \"MOVE\", \"NEG\", \n\t\t\t\"NOT\", \"BKP\", \"JEQ\", \"JNEQ\", \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \n\t\t\t\"JLTS\", \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \"DATA\", \"DEBUG_ABBREV\", \n\t\t\t\"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \"DEBUG_LOC\", \"DEBUG_RANGES\", \n\t\t\t\"DEBUG_STR\", \"DPU_HOST\", \"MRAM\", \"RODATA\", \"STACK_SIZES\", \"TEXT_SECTION\", \n\t\t\t\"PROGBITS\", \"NOBITS\", \"FUNCTION\", \"OBJECT\", \"TRUE\", \"FALSE\", \"Z\", \"NZ\", \n\t\t\t\"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \"C\", \"NC\", \"SZ\", \"SNZ\", \"SPL\", \"SMI\", \n\t\t\t\"SO\", \"SE\", \"NC5\", \"NC6\", \"NC7\", \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \n\t\t\t\"NC13\", \"NC14\", \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \"LTU\", \"LEU\", \n\t\t\t\"GTU\", \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \"XZ\", \"XNZ\", \"XLEU\", \"XGTU\", \n\t\t\t\"XLES\", \"XGTS\", \"SMALL\", \"LARGE\", \"LITTLE\", \"BIG\", \"ZERO_REGISTER\", \"ONE\", \n\t\t\t\"ID\", \"ID2\", \"ID4\", \"ID8\", \"LNEG\", \"MNEG\", \"ADDRSIG\", \"ADDRSIG_SYM\", \n\t\t\t\"ASCII\", \"ASCIZ\", \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \"CFI_ENDPROC\", \"CFI_OFFSET\", \n\t\t\t\"CFI_SECTIONS\", \"CFI_STARTPROC\", \"FILE\", \"GLOBL\", \"LOC\", \"LONG\", \"P2ALIGN\", \n\t\t\t\"QUAD\", \"SECTION\", \"SET\", \"SHORT\", \"SIZE\", \"TEXT_DIRECTIVE\", \"TYPE\", \n\t\t\t\"WEAK\", \"ZERO_DIRECTIVE\", \"IS_STMT\", \"PROLOGUE_END\", \"S_SUFFIX\", \"U_SUFFIX\", \n\t\t\t\"PositiveNumber\", \"GPRegister\", \"PairRegister\", \"Identifier\", \"StringLiteral\", \n\t\t\t\"COMMENT\", \"WHITE_SPACE\"\n\t\t};\n\t}\n\tprivate static final String[] _SYMBOLIC_NAMES = makeSymbolicNames();\n\tpublic static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES);\n\n\t/**\n\t * @deprecated Use {@link #VOCABULARY} instead.\n\t */\n\t@Deprecated\n\tpublic static final String[] tokenNames;\n\tstatic {\n\t\ttokenNames = new String[_SYMBOLIC_NAMES.length];\n\t\tfor (int i = 0; i < tokenNames.length; i++) {\n\t\t\ttokenNames[i] = VOCABULARY.getLiteralName(i);\n\t\t\tif (tokenNames[i] == null) {\n\t\t\t\ttokenNames[i] = VOCABULARY.getSymbolicName(i);\n\t\t\t}\n\n\t\t\tif (tokenNames[i] == null) {\n\t\t\t\ttokenNames[i] = \"<INVALID>\";\n\t\t\t}\n\t\t}\n\t}\n\n\t@Override\n\t@Deprecated\n\tpublic String[] getTokenNames() {\n\t\treturn tokenNames;\n\t}\n\n\t@Override\n\n\tpublic Vocabulary getVocabulary() {\n\t\treturn VOCABULARY;\n\t}\n\n\n\tpublic assemblyLexer(CharStream input) {\n\t\tsuper(input);\n\t\t_interp = new LexerATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache);\n\t}\n\n\t@Override\n\tpublic String getGrammarFileName() { return \"assembly.g4\"; }\n\n\t@Override\n\tpublic String[] getRuleNames() { return ruleNames; }\n\n\t@Override\n\tpublic String getSerializedATN() { return _serializedATN; }\n\n\t@Override\n\tpublic String[] getChannelNames() { return channelNames; }\n\n\t@Override\n\tpublic String[] getModeNames() { return modeNames; }\n\n\t@Override\n\tpublic ATN getATN() { return _ATN; }\n\n\tpublic static final String _serializedATN =\n\t\t\"\\3\\u608b\\ua72a\\u8133\\ub9ed\\u417c\\u3be7\\u7786\\u5964\\2\\u00de\\u073a\\b\\1\\4\"+\n\t\t\"\\2\\t\\2\\4\\3\\t\\3\\4\\4\\t\\4\\4\\5\\t\\5\\4\\6\\t\\6\\4\\7\\t\\7\\4\\b\\t\\b\\4\\t\\t\\t\\4\\n\\t\\n\"+\n\t\t\"\\4\\13\\t\\13\\4\\f\\t\\f\\4\\r\\t\\r\\4\\16\\t\\16\\4\\17\\t\\17\\4\\20\\t\\20\\4\\21\\t\\21\\4\\22\"+\n\t\t\"\\t\\22\\4\\23\\t\\23\\4\\24\\t\\24\\4\\25\\t\\25\\4\\26\\t\\26\\4\\27\\t\\27\\4\\30\\t\\30\\4\\31\"+\n\t\t\"\\t\\31\\4\\32\\t\\32\\4\\33\\t\\33\\4\\34\\t\\34\\4\\35\\t\\35\\4\\36\\t\\36\\4\\37\\t\\37\\4 \\t\"+\n\t\t\" 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static final ATN _ATN =\n\t\tnew ATNDeserializer().deserialize(_serializedATN.toCharArray());\n\tstatic {\n\t\t_decisionToDFA = new DFA[_ATN.getNumberOfDecisions()];\n\t\tfor (int i = 0; i < _ATN.getNumberOfDecisions(); i++) {\n\t\t\t_decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i);\n\t\t}\n\t}\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assemblyLexer.tokens",
    "content": "T__0=1\nT__1=2\nT__2=3\nT__3=4\nT__4=5\nACQUIRE=6\nRELEASE=7\nBOOT=8\nRESUME=9\nADD=10\nADDC=11\nAND=12\nANDN=13\nASR=14\nCMPB4=15\nLSL=16\nLSL1=17\nLSL1X=18\nLSLX=19\nLSR=20\nLSR1=21\nLSR1X=22\nLSRX=23\nMUL_SH_SH=24\nMUL_SH_SL=25\nMUL_SH_UH=26\nMUL_SH_UL=27\nMUL_SL_SH=28\nMUL_SL_SL=29\nMUL_SL_UH=30\nMUL_SL_UL=31\nMUL_UH_UH=32\nMUL_UH_UL=33\nMUL_UL_UH=34\nMUL_UL_UL=35\nNAND=36\nNOR=37\nNXOR=38\nOR=39\nORN=40\nROL=41\nROR=42\nRSUB=43\nRSUBC=44\nSUB=45\nSUBC=46\nXOR=47\nCALL=48\nHASH=49\nCAO=50\nCLO=51\nCLS=52\nCLZ=53\nEXTSB=54\nEXTSH=55\nEXTUB=56\nEXTUH=57\nSATS=58\nTIME_CFG=59\nDIV_STEP=60\nMUL_STEP=61\nLSL_ADD=62\nLSL_SUB=63\nLSR_ADD=64\nROL_ADD=65\nROR_ADD=66\nTIME=67\nNOP=68\nSTOP=69\nFAULT=70\nMOVD=71\nSWAPD=72\nLBS=73\nLBU=74\nLD=75\nLHS=76\nLHU=77\nLW=78\nSB=79\nSB_ID=80\nSD=81\nSD_ID=82\nSH=83\nSH_ID=84\nSW=85\nSW_ID=86\nLDMA=87\nLDMAI=88\nSDMA=89\nMOVE=90\nNEG=91\nNOT=92\nBKP=93\nJEQ=94\nJNEQ=95\nJZ=96\nJNZ=97\nJLTU=98\nJGTU=99\nJLEU=100\nJGEU=101\nJLTS=102\nJGTS=103\nJLES=104\nJGES=105\nJUMP=106\nATOMIC=107\nBSS=108\nDATA=109\nDEBUG_ABBREV=110\nDEBUG_FRAME=111\nDEBUG_INFO=112\nDEBUG_LINE=113\nDEBUG_LOC=114\nDEBUG_RANGES=115\nDEBUG_STR=116\nDPU_HOST=117\nMRAM=118\nRODATA=119\nSTACK_SIZES=120\nTEXT_SECTION=121\nPROGBITS=122\nNOBITS=123\nFUNCTION=124\nOBJECT=125\nTRUE=126\nFALSE=127\nZ=128\nNZ=129\nE=130\nO=131\nPL=132\nMI=133\nOV=134\nNOV=135\nC=136\nNC=137\nSZ=138\nSNZ=139\nSPL=140\nSMI=141\nSO=142\nSE=143\nNC5=144\nNC6=145\nNC7=146\nNC8=147\nNC9=148\nNC10=149\nNC11=150\nNC12=151\nNC13=152\nNC14=153\nMAX=154\nNMAX=155\nSH32=156\nNSH32=157\nEQ=158\nNEQ=159\nLTU=160\nLEU=161\nGTU=162\nGEU=163\nLTS=164\nLES=165\nGTS=166\nGES=167\nXZ=168\nXNZ=169\nXLEU=170\nXGTU=171\nXLES=172\nXGTS=173\nSMALL=174\nLARGE=175\nLITTLE=176\nBIG=177\nZERO_REGISTER=178\nONE=179\nID=180\nID2=181\nID4=182\nID8=183\nLNEG=184\nMNEG=185\nADDRSIG=186\nADDRSIG_SYM=187\nASCII=188\nASCIZ=189\nBYTE=190\nCFI_DEF_CFA_OFFSET=191\nCFI_ENDPROC=192\nCFI_OFFSET=193\nCFI_SECTIONS=194\nCFI_STARTPROC=195\nFILE=196\nGLOBL=197\nLOC=198\nLONG=199\nP2ALIGN=200\nQUAD=201\nSECTION=202\nSET=203\nSHORT=204\nSIZE=205\nTEXT_DIRECTIVE=206\nTYPE=207\nWEAK=208\nZERO_DIRECTIVE=209\nIS_STMT=210\nPROLOGUE_END=211\nS_SUFFIX=212\nU_SUFFIX=213\nPositiveNumber=214\nGPRegister=215\nPairRegister=216\nIdentifier=217\nStringLiteral=218\nCOMMENT=219\nWHITE_SPACE=220\n'-'=1\n'0x'=2\n'+'=3\n','=4\n':'=5\n'$acquire'=6\n'$release'=7\n'$boot'=8\n'$resume'=9\n'$add'=10\n'$addc'=11\n'$and'=12\n'$andn'=13\n'$asr'=14\n'$cmpb4'=15\n'$lsl'=16\n'$lsl1'=17\n'$lsl1x'=18\n'$lslx'=19\n'$lsr'=20\n'$lsr1'=21\n'$lsr1x'=22\n'$lsrx'=23\n'$mul_sh_sh'=24\n'$mul_sh_sl'=25\n'$mul_sh_uh'=26\n'$mul_sh_ul'=27\n'$mul_sl_sh'=28\n'$mul_sl_sl'=29\n'$mul_sl_uh'=30\n'$mul_sl_ul'=31\n'$mul_uh_uh'=32\n'$mul_uh_ul'=33\n'$mul_ul_uh'=34\n'$mul_ul_ul'=35\n'$nand'=36\n'$nor'=37\n'$nxor'=38\n'$or'=39\n'$orn'=40\n'$rol'=41\n'$ror'=42\n'$rsub'=43\n'$rsubc'=44\n'$sub'=45\n'$subc'=46\n'$xor'=47\n'$call'=48\n'$hash'=49\n'$cao'=50\n'$clo'=51\n'$cls'=52\n'$clz'=53\n'$extsb'=54\n'$extsh'=55\n'$extub'=56\n'$extuh'=57\n'$sats'=58\n'$time_cfg'=59\n'$div_step'=60\n'$mul_step'=61\n'$lsl_add'=62\n'$lsl_sub'=63\n'$lsr_add'=64\n'$rol_add'=65\n'$ror_add'=66\n'$time'=67\n'$nop'=68\n'$stop'=69\n'$fault'=70\n'$movd'=71\n'$swapd'=72\n'$lbs'=73\n'$lbu'=74\n'$ld'=75\n'$lhs'=76\n'$lhu'=77\n'$lw'=78\n'$sb'=79\n'$sb_id'=80\n'$sd'=81\n'$sd_id'=82\n'$sh'=83\n'$sh_id'=84\n'$sw'=85\n'$sw_id'=86\n'$ldma'=87\n'$ldmai'=88\n'$sdma'=89\n'$move'=90\n'$neg'=91\n'$not'=92\n'$bkp'=93\n'$jeq'=94\n'$jneq'=95\n'$jz'=96\n'$jnz'=97\n'$jltu'=98\n'$jgtu'=99\n'$jleu'=100\n'$jgeu'=101\n'$jlts'=102\n'$jgts'=103\n'$jles'=104\n'$jges'=105\n'$jump'=106\n'%atomic'=107\n'%bss'=108\n'%data'=109\n'%debug_abbrev'=110\n'%debug_frame'=111\n'%debug_info'=112\n'%debug_line'=113\n'%debug_loc'=114\n'%debug_ranges'=115\n'%debug_str'=116\n'%dpu_host'=117\n'%mram'=118\n'%rodata'=119\n'%stack_sizes'=120\n'%text'=121\n'@progbits'=122\n'@nobits'=123\n'@function'=124\n'@object'=125\n'true'=126\n'false'=127\n'z'=128\n'nz'=129\n'e'=130\n'o'=131\n'pl'=132\n'mi'=133\n'ov'=134\n'nov'=135\n'c'=136\n'nc'=137\n'sz'=138\n'snz'=139\n'spl'=140\n'smi'=141\n'so'=142\n'se'=143\n'nc5'=144\n'nc6'=145\n'nc7'=146\n'nc8'=147\n'nc9'=148\n'nc10'=149\n'nc11'=150\n'nc12'=151\n'nc13'=152\n'nc14'=153\n'max'=154\n'nmax'=155\n'sh32'=156\n'nsh32'=157\n'eq'=158\n'neq'=159\n'ltu'=160\n'leu'=161\n'gtu'=162\n'geu'=163\n'lts'=164\n'les'=165\n'gts'=166\n'ges'=167\n'xz'=168\n'xnz'=169\n'xleu'=170\n'xgtu'=171\n'xles'=172\n'xgts'=173\n'small'=174\n'large'=175\n'!little'=176\n'!big'=177\n'zero'=178\n'one'=179\n'id'=180\n'id2'=181\n'id4'=182\n'id8'=183\n'lneg'=184\n'mneg'=185\n'$addrsig'=186\n'$addrsig_sym'=187\n'$ascii'=188\n'$asciz'=189\n'$byte'=190\n'$cfi_def_cfa_offset'=191\n'$cfi_endproc'=192\n'$cfi_offset'=193\n'$cfi_sections'=194\n'$cfi_startproc'=195\n'$file'=196\n'$globl'=197\n'$loc'=198\n'$long'=199\n'$p2align'=200\n'$quad'=201\n'$section'=202\n'$set'=203\n'$short'=204\n'$size'=205\n'$text'=206\n'$type'=207\n'$weak'=208\n'$zero'=209\n'is_stmt'=210\n'prologue_end'=211\n'.s'=212\n'.u'=213\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/.antlr/assemblyParser.java",
    "content": "// Generated from /home/bongjoon/upmem_compiler/src/parser_/grammar/assembly.g4 by ANTLR 4.8\nimport org.antlr.v4.runtime.atn.*;\nimport org.antlr.v4.runtime.dfa.DFA;\nimport org.antlr.v4.runtime.*;\nimport org.antlr.v4.runtime.misc.*;\nimport org.antlr.v4.runtime.tree.*;\nimport java.util.List;\nimport java.util.Iterator;\nimport java.util.ArrayList;\n\n@SuppressWarnings({\"all\", \"warnings\", \"unchecked\", \"unused\", \"cast\"})\npublic class assemblyParser extends Parser {\n\tstatic { RuntimeMetaData.checkVersion(\"4.8\", RuntimeMetaData.VERSION); }\n\n\tprotected static final DFA[] _decisionToDFA;\n\tprotected static final PredictionContextCache _sharedContextCache =\n\t\tnew PredictionContextCache();\n\tpublic static final int\n\t\tT__0=1, T__1=2, T__2=3, T__3=4, T__4=5, ACQUIRE=6, RELEASE=7, BOOT=8, \n\t\tRESUME=9, ADD=10, ADDC=11, AND=12, ANDN=13, ASR=14, CMPB4=15, LSL=16, \n\t\tLSL1=17, LSL1X=18, LSLX=19, LSR=20, LSR1=21, LSR1X=22, LSRX=23, MUL_SH_SH=24, \n\t\tMUL_SH_SL=25, MUL_SH_UH=26, MUL_SH_UL=27, MUL_SL_SH=28, MUL_SL_SL=29, \n\t\tMUL_SL_UH=30, MUL_SL_UL=31, MUL_UH_UH=32, MUL_UH_UL=33, MUL_UL_UH=34, \n\t\tMUL_UL_UL=35, NAND=36, NOR=37, NXOR=38, OR=39, ORN=40, ROL=41, ROR=42, \n\t\tRSUB=43, RSUBC=44, SUB=45, SUBC=46, XOR=47, CALL=48, HASH=49, CAO=50, \n\t\tCLO=51, CLS=52, CLZ=53, EXTSB=54, EXTSH=55, EXTUB=56, EXTUH=57, SATS=58, \n\t\tTIME_CFG=59, DIV_STEP=60, MUL_STEP=61, LSL_ADD=62, LSL_SUB=63, LSR_ADD=64, \n\t\tROL_ADD=65, ROR_ADD=66, TIME=67, NOP=68, STOP=69, FAULT=70, MOVD=71, SWAPD=72, \n\t\tLBS=73, LBU=74, LD=75, LHS=76, LHU=77, LW=78, SB=79, SB_ID=80, SD=81, \n\t\tSD_ID=82, SH=83, SH_ID=84, SW=85, SW_ID=86, LDMA=87, LDMAI=88, SDMA=89, \n\t\tMOVE=90, NEG=91, NOT=92, BKP=93, JEQ=94, JNEQ=95, JZ=96, JNZ=97, JLTU=98, \n\t\tJGTU=99, JLEU=100, JGEU=101, JLTS=102, JGTS=103, JLES=104, JGES=105, JUMP=106, \n\t\tATOMIC=107, BSS=108, DATA=109, DEBUG_ABBREV=110, DEBUG_FRAME=111, DEBUG_INFO=112, \n\t\tDEBUG_LINE=113, DEBUG_LOC=114, DEBUG_RANGES=115, DEBUG_STR=116, DPU_HOST=117, \n\t\tMRAM=118, RODATA=119, STACK_SIZES=120, TEXT_SECTION=121, PROGBITS=122, \n\t\tNOBITS=123, FUNCTION=124, OBJECT=125, TRUE=126, FALSE=127, Z=128, NZ=129, \n\t\tE=130, O=131, PL=132, MI=133, OV=134, NOV=135, C=136, NC=137, SZ=138, \n\t\tSNZ=139, SPL=140, SMI=141, SO=142, SE=143, NC5=144, NC6=145, NC7=146, \n\t\tNC8=147, NC9=148, NC10=149, NC11=150, NC12=151, NC13=152, NC14=153, MAX=154, \n\t\tNMAX=155, SH32=156, NSH32=157, EQ=158, NEQ=159, LTU=160, LEU=161, GTU=162, \n\t\tGEU=163, LTS=164, LES=165, GTS=166, GES=167, XZ=168, XNZ=169, XLEU=170, \n\t\tXGTU=171, XLES=172, XGTS=173, SMALL=174, LARGE=175, LITTLE=176, BIG=177, \n\t\tZERO_REGISTER=178, ONE=179, ID=180, ID2=181, ID4=182, ID8=183, LNEG=184, \n\t\tMNEG=185, ADDRSIG=186, ADDRSIG_SYM=187, ASCII=188, ASCIZ=189, BYTE=190, \n\t\tCFI_DEF_CFA_OFFSET=191, CFI_ENDPROC=192, CFI_OFFSET=193, CFI_SECTIONS=194, \n\t\tCFI_STARTPROC=195, FILE=196, GLOBL=197, LOC=198, LONG=199, P2ALIGN=200, \n\t\tQUAD=201, SECTION=202, SET=203, SHORT=204, SIZE=205, TEXT_DIRECTIVE=206, \n\t\tTYPE=207, WEAK=208, ZERO_DIRECTIVE=209, IS_STMT=210, PROLOGUE_END=211, \n\t\tS_SUFFIX=212, U_SUFFIX=213, PositiveNumber=214, GPRegister=215, PairRegister=216, \n\t\tIdentifier=217, StringLiteral=218, COMMENT=219, WHITE_SPACE=220;\n\tpublic static final int\n\t\tRULE_document = 0, RULE_negative_number = 1, RULE_hex_number = 2, RULE_number = 3, \n\t\tRULE_rici_op_code = 4, RULE_rri_op_code = 5, RULE_rr_op_code = 6, RULE_drdici_op_code = 7, \n\t\tRULE_rrri_op_code = 8, RULE_r_op_code = 9, RULE_ci_op_code = 10, RULE_i_op_code = 11, \n\t\tRULE_ddci_op_code = 12, RULE_load_op_code = 13, RULE_store_op_code = 14, \n\t\tRULE_dma_op_code = 15, RULE_section_name = 16, RULE_section_types = 17, \n\t\tRULE_symbol_type = 18, RULE_condition = 19, RULE_endian = 20, RULE_sp_register = 21, \n\t\tRULE_src_register = 22, RULE_program_counter = 23, RULE_add_expression = 24, \n\t\tRULE_sub_expression = 25, RULE_primary_expression = 26, RULE_directive = 27, \n\t\tRULE_addrsig_directive = 28, RULE_addrsig_sym_directive = 29, RULE_ascii_directive = 30, \n\t\tRULE_asciz_directive = 31, RULE_byte_directive = 32, RULE_cfi_def_cfa_offset_directive = 33, \n\t\tRULE_cfi_endproc_directive = 34, RULE_cfi_offset_directive = 35, RULE_cfi_sections_directive = 36, \n\t\tRULE_cfi_startproc_directive = 37, RULE_file_directive = 38, RULE_global_directive = 39, \n\t\tRULE_loc_directive = 40, RULE_long_directive = 41, RULE_p2align_directive = 42, \n\t\tRULE_quad_directive = 43, RULE_section_directive = 44, RULE_set_directive = 45, \n\t\tRULE_short_directive = 46, RULE_size_directive = 47, RULE_stack_sizes_directive = 48, \n\t\tRULE_text_directive = 49, RULE_type_directive = 50, RULE_weak_directive = 51, \n\t\tRULE_zero_directive = 52, RULE_instruction = 53, RULE_rici_instruction = 54, \n\t\tRULE_rri_instruction = 55, RULE_rric_instruction = 56, RULE_rrici_instruction = 57, \n\t\tRULE_rrr_instruction = 58, RULE_rrrc_instruction = 59, RULE_rrrci_instruction = 60, \n\t\tRULE_zri_instruction = 61, RULE_zric_instruction = 62, RULE_zrici_instruction = 63, \n\t\tRULE_zrr_instruction = 64, RULE_zrrc_instruction = 65, RULE_zrrci_instruction = 66, \n\t\tRULE_s_rri_instruction = 67, RULE_s_rric_instruction = 68, RULE_s_rrici_instruction = 69, \n\t\tRULE_s_rrr_instruction = 70, RULE_s_rrrc_instruction = 71, RULE_s_rrrci_instruction = 72, \n\t\tRULE_u_rri_instruction = 73, RULE_u_rric_instruction = 74, RULE_u_rrici_instruction = 75, \n\t\tRULE_u_rrr_instruction = 76, RULE_u_rrrc_instruction = 77, RULE_u_rrrci_instruction = 78, \n\t\tRULE_rr_instruction = 79, RULE_rrc_instruction = 80, RULE_rrci_instruction = 81, \n\t\tRULE_zr_instruction = 82, RULE_zrc_instruction = 83, RULE_zrci_instruction = 84, \n\t\tRULE_s_rr_instruction = 85, RULE_s_rrc_instruction = 86, RULE_s_rrci_instruction = 87, \n\t\tRULE_u_rr_instruction = 88, RULE_u_rrc_instruction = 89, RULE_u_rrci_instruction = 90, \n\t\tRULE_drdici_instruction = 91, RULE_rrri_instruction = 92, RULE_rrrici_instruction = 93, \n\t\tRULE_zrri_instruction = 94, RULE_zrrici_instruction = 95, RULE_s_rrri_instruction = 96, \n\t\tRULE_s_rrrici_instruction = 97, RULE_u_rrri_instruction = 98, RULE_u_rrrici_instruction = 99, \n\t\tRULE_rir_instruction = 100, RULE_rirc_instruction = 101, RULE_rirci_instruction = 102, \n\t\tRULE_zir_instruction = 103, RULE_zirc_instruction = 104, RULE_zirci_instruction = 105, \n\t\tRULE_s_rirc_instruction = 106, RULE_s_rirci_instruction = 107, RULE_u_rirc_instruction = 108, \n\t\tRULE_u_rirci_instruction = 109, RULE_r_instruction = 110, RULE_rci_instruction = 111, \n\t\tRULE_z_instruction = 112, RULE_zci_instruction = 113, RULE_s_r_instruction = 114, \n\t\tRULE_s_rci_instruction = 115, RULE_u_r_instruction = 116, RULE_u_rci_instruction = 117, \n\t\tRULE_ci_instruction = 118, RULE_i_instruction = 119, RULE_ddci_instruction = 120, \n\t\tRULE_erri_instruction = 121, RULE_edri_instruction = 122, RULE_s_erri_instruction = 123, \n\t\tRULE_u_erri_instruction = 124, RULE_erii_instruction = 125, RULE_erir_instruction = 126, \n\t\tRULE_erid_instruction = 127, RULE_dma_rri_instruction = 128, RULE_synthetic_sugar_instruction = 129, \n\t\tRULE_rrif_instruction = 130, RULE_andn_rrif_instruction = 131, RULE_nand_rrif_instruction = 132, \n\t\tRULE_nor_rrif_instruction = 133, RULE_nxor_rrif_instruction = 134, RULE_orn_rrif_instruction = 135, \n\t\tRULE_hash_rrif_instruction = 136, RULE_move_instruction = 137, RULE_move_ri_instruction = 138, \n\t\tRULE_move_rici_instruction = 139, RULE_move_rr_instruction = 140, RULE_move_rrci_instruction = 141, \n\t\tRULE_move_s_ri_instruction = 142, RULE_move_s_rici_instruction = 143, \n\t\tRULE_move_s_rr_instruction = 144, RULE_move_s_rrci_instruction = 145, \n\t\tRULE_move_u_ri_instruction = 146, RULE_move_u_rici_instruction = 147, \n\t\tRULE_move_u_rr_instruction = 148, RULE_move_u_rrci_instruction = 149, \n\t\tRULE_neg_instruction = 150, RULE_neg_rr_instruction = 151, RULE_neg_rrci_instruction = 152, \n\t\tRULE_not_instruction = 153, RULE_not_rr_instruction = 154, RULE_not_rrci_instruction = 155, \n\t\tRULE_not_zrci_instruction = 156, RULE_jump_instruction = 157, RULE_jeq_rii_instruction = 158, \n\t\tRULE_jeq_rri_instruction = 159, RULE_jneq_rii_instruction = 160, RULE_jneq_rri_instruction = 161, \n\t\tRULE_jz_ri_instruction = 162, RULE_jnz_ri_instruction = 163, RULE_jltu_rii_instruction = 164, \n\t\tRULE_jltu_rri_instruction = 165, RULE_jgtu_rii_instruction = 166, RULE_jgtu_rri_instruction = 167, \n\t\tRULE_jleu_rii_instruction = 168, RULE_jleu_rri_instruction = 169, RULE_jgeu_rii_instruction = 170, \n\t\tRULE_jgeu_rri_instruction = 171, RULE_jlts_rii_instruction = 172, RULE_jlts_rri_instruction = 173, \n\t\tRULE_jgts_rii_instruction = 174, RULE_jgts_rri_instruction = 175, RULE_jles_rii_instruction = 176, \n\t\tRULE_jles_rri_instruction = 177, RULE_jges_rii_instruction = 178, RULE_jges_rri_instruction = 179, \n\t\tRULE_jump_ri_instruction = 180, RULE_jump_i_instruction = 181, RULE_jump_r_instruction = 182, \n\t\tRULE_shortcut_instruction = 183, RULE_div_step_drdici_instruction = 184, \n\t\tRULE_mul_step_drdici_instruction = 185, RULE_boot_rici_instruction = 186, \n\t\tRULE_resume_rici_instruction = 187, RULE_stop_ci_instruction = 188, RULE_call_ri_instruction = 189, \n\t\tRULE_call_rr_instruction = 190, RULE_bkp_instruction = 191, RULE_movd_ddci_instruction = 192, \n\t\tRULE_swapd_ddci_instruction = 193, RULE_time_cfg_zr_instruction = 194, \n\t\tRULE_lbs_erri_instruction = 195, RULE_lbs_s_erri_instruction = 196, RULE_lbu_erri_instruction = 197, \n\t\tRULE_lbu_u_erri_instruction = 198, RULE_ld_edri_instruction = 199, RULE_lhs_erri_instruction = 200, \n\t\tRULE_lhs_s_erri_instruction = 201, RULE_lhu_erri_instruction = 202, RULE_lhu_u_erri_instruction = 203, \n\t\tRULE_lw_erri_instruction = 204, RULE_lw_s_erri_instruction = 205, RULE_lw_u_erri_instruction = 206, \n\t\tRULE_sb_erii_instruction = 207, RULE_sb_erir_instruction = 208, RULE_sb_id_rii_instruction = 209, \n\t\tRULE_sb_id_ri_instruction = 210, RULE_sd_erii_instruction = 211, RULE_sd_erid_instruction = 212, \n\t\tRULE_sd_id_rii_instruction = 213, RULE_sd_id_ri_instruction = 214, RULE_sh_erii_instruction = 215, \n\t\tRULE_sh_erir_instruction = 216, RULE_sh_id_rii_instruction = 217, RULE_sh_id_ri_instruction = 218, \n\t\tRULE_sw_erii_instruction = 219, RULE_sw_erir_instruction = 220, RULE_sw_id_rii_instruction = 221, \n\t\tRULE_sw_id_ri_instruction = 222, RULE_label = 223;\n\tprivate static String[] makeRuleNames() {\n\t\treturn new String[] {\n\t\t\t\"document\", \"negative_number\", \"hex_number\", \"number\", \"rici_op_code\", \n\t\t\t\"rri_op_code\", \"rr_op_code\", \"drdici_op_code\", \"rrri_op_code\", \"r_op_code\", \n\t\t\t\"ci_op_code\", \"i_op_code\", \"ddci_op_code\", \"load_op_code\", \"store_op_code\", \n\t\t\t\"dma_op_code\", \"section_name\", \"section_types\", \"symbol_type\", \"condition\", \n\t\t\t\"endian\", \"sp_register\", \"src_register\", \"program_counter\", \"add_expression\", \n\t\t\t\"sub_expression\", \"primary_expression\", \"directive\", \"addrsig_directive\", \n\t\t\t\"addrsig_sym_directive\", \"ascii_directive\", \"asciz_directive\", \"byte_directive\", \n\t\t\t\"cfi_def_cfa_offset_directive\", \"cfi_endproc_directive\", \"cfi_offset_directive\", \n\t\t\t\"cfi_sections_directive\", \"cfi_startproc_directive\", \"file_directive\", \n\t\t\t\"global_directive\", \"loc_directive\", \"long_directive\", \"p2align_directive\", \n\t\t\t\"quad_directive\", \"section_directive\", \"set_directive\", \"short_directive\", \n\t\t\t\"size_directive\", \"stack_sizes_directive\", \"text_directive\", \"type_directive\", \n\t\t\t\"weak_directive\", \"zero_directive\", \"instruction\", \"rici_instruction\", \n\t\t\t\"rri_instruction\", \"rric_instruction\", \"rrici_instruction\", \"rrr_instruction\", \n\t\t\t\"rrrc_instruction\", \"rrrci_instruction\", \"zri_instruction\", \"zric_instruction\", \n\t\t\t\"zrici_instruction\", \"zrr_instruction\", \"zrrc_instruction\", \"zrrci_instruction\", \n\t\t\t\"s_rri_instruction\", \"s_rric_instruction\", \"s_rrici_instruction\", \"s_rrr_instruction\", \n\t\t\t\"s_rrrc_instruction\", \"s_rrrci_instruction\", \"u_rri_instruction\", \"u_rric_instruction\", \n\t\t\t\"u_rrici_instruction\", \"u_rrr_instruction\", \"u_rrrc_instruction\", \"u_rrrci_instruction\", \n\t\t\t\"rr_instruction\", \"rrc_instruction\", \"rrci_instruction\", \"zr_instruction\", \n\t\t\t\"zrc_instruction\", \"zrci_instruction\", \"s_rr_instruction\", \"s_rrc_instruction\", \n\t\t\t\"s_rrci_instruction\", \"u_rr_instruction\", \"u_rrc_instruction\", \"u_rrci_instruction\", \n\t\t\t\"drdici_instruction\", \"rrri_instruction\", \"rrrici_instruction\", \"zrri_instruction\", \n\t\t\t\"zrrici_instruction\", \"s_rrri_instruction\", \"s_rrrici_instruction\", \"u_rrri_instruction\", \n\t\t\t\"u_rrrici_instruction\", \"rir_instruction\", \"rirc_instruction\", \"rirci_instruction\", \n\t\t\t\"zir_instruction\", \"zirc_instruction\", \"zirci_instruction\", \"s_rirc_instruction\", \n\t\t\t\"s_rirci_instruction\", \"u_rirc_instruction\", \"u_rirci_instruction\", \"r_instruction\", \n\t\t\t\"rci_instruction\", \"z_instruction\", \"zci_instruction\", \"s_r_instruction\", \n\t\t\t\"s_rci_instruction\", \"u_r_instruction\", \"u_rci_instruction\", \"ci_instruction\", \n\t\t\t\"i_instruction\", \"ddci_instruction\", \"erri_instruction\", \"edri_instruction\", \n\t\t\t\"s_erri_instruction\", \"u_erri_instruction\", \"erii_instruction\", \"erir_instruction\", \n\t\t\t\"erid_instruction\", \"dma_rri_instruction\", \"synthetic_sugar_instruction\", \n\t\t\t\"rrif_instruction\", \"andn_rrif_instruction\", \"nand_rrif_instruction\", \n\t\t\t\"nor_rrif_instruction\", \"nxor_rrif_instruction\", \"orn_rrif_instruction\", \n\t\t\t\"hash_rrif_instruction\", \"move_instruction\", \"move_ri_instruction\", \"move_rici_instruction\", \n\t\t\t\"move_rr_instruction\", \"move_rrci_instruction\", \"move_s_ri_instruction\", \n\t\t\t\"move_s_rici_instruction\", \"move_s_rr_instruction\", \"move_s_rrci_instruction\", \n\t\t\t\"move_u_ri_instruction\", \"move_u_rici_instruction\", \"move_u_rr_instruction\", \n\t\t\t\"move_u_rrci_instruction\", \"neg_instruction\", \"neg_rr_instruction\", \"neg_rrci_instruction\", \n\t\t\t\"not_instruction\", \"not_rr_instruction\", \"not_rrci_instruction\", \"not_zrci_instruction\", \n\t\t\t\"jump_instruction\", \"jeq_rii_instruction\", \"jeq_rri_instruction\", \"jneq_rii_instruction\", \n\t\t\t\"jneq_rri_instruction\", \"jz_ri_instruction\", \"jnz_ri_instruction\", \"jltu_rii_instruction\", \n\t\t\t\"jltu_rri_instruction\", \"jgtu_rii_instruction\", \"jgtu_rri_instruction\", \n\t\t\t\"jleu_rii_instruction\", \"jleu_rri_instruction\", \"jgeu_rii_instruction\", \n\t\t\t\"jgeu_rri_instruction\", \"jlts_rii_instruction\", \"jlts_rri_instruction\", \n\t\t\t\"jgts_rii_instruction\", \"jgts_rri_instruction\", \"jles_rii_instruction\", \n\t\t\t\"jles_rri_instruction\", \"jges_rii_instruction\", \"jges_rri_instruction\", \n\t\t\t\"jump_ri_instruction\", \"jump_i_instruction\", \"jump_r_instruction\", \"shortcut_instruction\", \n\t\t\t\"div_step_drdici_instruction\", \"mul_step_drdici_instruction\", \"boot_rici_instruction\", \n\t\t\t\"resume_rici_instruction\", \"stop_ci_instruction\", \"call_ri_instruction\", \n\t\t\t\"call_rr_instruction\", \"bkp_instruction\", \"movd_ddci_instruction\", \"swapd_ddci_instruction\", \n\t\t\t\"time_cfg_zr_instruction\", \"lbs_erri_instruction\", \"lbs_s_erri_instruction\", \n\t\t\t\"lbu_erri_instruction\", \"lbu_u_erri_instruction\", \"ld_edri_instruction\", \n\t\t\t\"lhs_erri_instruction\", \"lhs_s_erri_instruction\", \"lhu_erri_instruction\", \n\t\t\t\"lhu_u_erri_instruction\", \"lw_erri_instruction\", \"lw_s_erri_instruction\", \n\t\t\t\"lw_u_erri_instruction\", \"sb_erii_instruction\", \"sb_erir_instruction\", \n\t\t\t\"sb_id_rii_instruction\", \"sb_id_ri_instruction\", \"sd_erii_instruction\", \n\t\t\t\"sd_erid_instruction\", \"sd_id_rii_instruction\", \"sd_id_ri_instruction\", \n\t\t\t\"sh_erii_instruction\", \"sh_erir_instruction\", \"sh_id_rii_instruction\", \n\t\t\t\"sh_id_ri_instruction\", \"sw_erii_instruction\", \"sw_erir_instruction\", \n\t\t\t\"sw_id_rii_instruction\", \"sw_id_ri_instruction\", \"label\"\n\t\t};\n\t}\n\tpublic static final String[] ruleNames = makeRuleNames();\n\n\tprivate static String[] makeLiteralNames() {\n\t\treturn new String[] {\n\t\t\tnull, \"'-'\", \"'0x'\", \"'+'\", \"','\", \"':'\", \"'$acquire'\", \"'$release'\", \n\t\t\t\"'$boot'\", \"'$resume'\", \"'$add'\", \"'$addc'\", \"'$and'\", \"'$andn'\", \"'$asr'\", \n\t\t\t\"'$cmpb4'\", \"'$lsl'\", \"'$lsl1'\", \"'$lsl1x'\", \"'$lslx'\", \"'$lsr'\", \"'$lsr1'\", \n\t\t\t\"'$lsr1x'\", \"'$lsrx'\", \"'$mul_sh_sh'\", \"'$mul_sh_sl'\", \"'$mul_sh_uh'\", \n\t\t\t\"'$mul_sh_ul'\", \"'$mul_sl_sh'\", \"'$mul_sl_sl'\", \"'$mul_sl_uh'\", \"'$mul_sl_ul'\", \n\t\t\t\"'$mul_uh_uh'\", \"'$mul_uh_ul'\", \"'$mul_ul_uh'\", \"'$mul_ul_ul'\", \"'$nand'\", \n\t\t\t\"'$nor'\", \"'$nxor'\", \"'$or'\", \"'$orn'\", \"'$rol'\", \"'$ror'\", \"'$rsub'\", \n\t\t\t\"'$rsubc'\", \"'$sub'\", \"'$subc'\", \"'$xor'\", \"'$call'\", \"'$hash'\", \"'$cao'\", \n\t\t\t\"'$clo'\", \"'$cls'\", \"'$clz'\", \"'$extsb'\", \"'$extsh'\", \"'$extub'\", \"'$extuh'\", \n\t\t\t\"'$sats'\", \"'$time_cfg'\", \"'$div_step'\", \"'$mul_step'\", \"'$lsl_add'\", \n\t\t\t\"'$lsl_sub'\", \"'$lsr_add'\", \"'$rol_add'\", \"'$ror_add'\", \"'$time'\", \"'$nop'\", \n\t\t\t\"'$stop'\", \"'$fault'\", \"'$movd'\", \"'$swapd'\", \"'$lbs'\", \"'$lbu'\", \"'$ld'\", \n\t\t\t\"'$lhs'\", \"'$lhu'\", \"'$lw'\", \"'$sb'\", \"'$sb_id'\", \"'$sd'\", \"'$sd_id'\", \n\t\t\t\"'$sh'\", \"'$sh_id'\", \"'$sw'\", \"'$sw_id'\", \"'$ldma'\", \"'$ldmai'\", \"'$sdma'\", \n\t\t\t\"'$move'\", \"'$neg'\", \"'$not'\", \"'$bkp'\", \"'$jeq'\", \"'$jneq'\", \"'$jz'\", \n\t\t\t\"'$jnz'\", \"'$jltu'\", \"'$jgtu'\", \"'$jleu'\", \"'$jgeu'\", \"'$jlts'\", \"'$jgts'\", \n\t\t\t\"'$jles'\", \"'$jges'\", \"'$jump'\", \"'%atomic'\", \"'%bss'\", \"'%data'\", \"'%debug_abbrev'\", \n\t\t\t\"'%debug_frame'\", \"'%debug_info'\", \"'%debug_line'\", \"'%debug_loc'\", \"'%debug_ranges'\", \n\t\t\t\"'%debug_str'\", \"'%dpu_host'\", \"'%mram'\", \"'%rodata'\", \"'%stack_sizes'\", \n\t\t\t\"'%text'\", \"'@progbits'\", \"'@nobits'\", \"'@function'\", \"'@object'\", \"'true'\", \n\t\t\t\"'false'\", \"'z'\", \"'nz'\", \"'e'\", \"'o'\", \"'pl'\", \"'mi'\", \"'ov'\", \"'nov'\", \n\t\t\t\"'c'\", \"'nc'\", \"'sz'\", \"'snz'\", \"'spl'\", \"'smi'\", \"'so'\", \"'se'\", \"'nc5'\", \n\t\t\t\"'nc6'\", \"'nc7'\", \"'nc8'\", \"'nc9'\", \"'nc10'\", \"'nc11'\", \"'nc12'\", \"'nc13'\", \n\t\t\t\"'nc14'\", \"'max'\", \"'nmax'\", \"'sh32'\", \"'nsh32'\", \"'eq'\", \"'neq'\", \"'ltu'\", \n\t\t\t\"'leu'\", \"'gtu'\", \"'geu'\", \"'lts'\", \"'les'\", \"'gts'\", \"'ges'\", \"'xz'\", \n\t\t\t\"'xnz'\", \"'xleu'\", \"'xgtu'\", \"'xles'\", \"'xgts'\", \"'small'\", \"'large'\", \n\t\t\t\"'!little'\", \"'!big'\", \"'zero'\", \"'one'\", \"'id'\", \"'id2'\", \"'id4'\", \"'id8'\", \n\t\t\t\"'lneg'\", \"'mneg'\", \"'$addrsig'\", \"'$addrsig_sym'\", \"'$ascii'\", \"'$asciz'\", \n\t\t\t\"'$byte'\", \"'$cfi_def_cfa_offset'\", \"'$cfi_endproc'\", \"'$cfi_offset'\", \n\t\t\t\"'$cfi_sections'\", \"'$cfi_startproc'\", \"'$file'\", \"'$globl'\", \"'$loc'\", \n\t\t\t\"'$long'\", \"'$p2align'\", \"'$quad'\", \"'$section'\", \"'$set'\", \"'$short'\", \n\t\t\t\"'$size'\", \"'$text'\", \"'$type'\", \"'$weak'\", \"'$zero'\", \"'is_stmt'\", \"'prologue_end'\", \n\t\t\t\"'.s'\", \"'.u'\"\n\t\t};\n\t}\n\tprivate static final String[] _LITERAL_NAMES = makeLiteralNames();\n\tprivate static String[] makeSymbolicNames() {\n\t\treturn new String[] {\n\t\t\tnull, null, null, null, null, null, \"ACQUIRE\", \"RELEASE\", \"BOOT\", \"RESUME\", \n\t\t\t\"ADD\", \"ADDC\", \"AND\", \"ANDN\", \"ASR\", \"CMPB4\", \"LSL\", \"LSL1\", \"LSL1X\", \n\t\t\t\"LSLX\", \"LSR\", \"LSR1\", \"LSR1X\", \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \"MUL_SH_UH\", \n\t\t\t\"MUL_SH_UL\", \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \"MUL_UH_UH\", \n\t\t\t\"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \"NAND\", \"NOR\", \"NXOR\", \"OR\", \"ORN\", \n\t\t\t\"ROL\", \"ROR\", \"RSUB\", \"RSUBC\", \"SUB\", \"SUBC\", \"XOR\", \"CALL\", \"HASH\", \n\t\t\t\"CAO\", \"CLO\", \"CLS\", \"CLZ\", \"EXTSB\", \"EXTSH\", \"EXTUB\", \"EXTUH\", \"SATS\", \n\t\t\t\"TIME_CFG\", \"DIV_STEP\", \"MUL_STEP\", \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \n\t\t\t\"ROL_ADD\", \"ROR_ADD\", \"TIME\", \"NOP\", \"STOP\", \"FAULT\", \"MOVD\", \"SWAPD\", \n\t\t\t\"LBS\", \"LBU\", \"LD\", \"LHS\", \"LHU\", \"LW\", \"SB\", \"SB_ID\", \"SD\", \"SD_ID\", \n\t\t\t\"SH\", \"SH_ID\", \"SW\", \"SW_ID\", \"LDMA\", \"LDMAI\", \"SDMA\", \"MOVE\", \"NEG\", \n\t\t\t\"NOT\", \"BKP\", \"JEQ\", \"JNEQ\", \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \n\t\t\t\"JLTS\", \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \"DATA\", \"DEBUG_ABBREV\", \n\t\t\t\"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \"DEBUG_LOC\", \"DEBUG_RANGES\", \n\t\t\t\"DEBUG_STR\", \"DPU_HOST\", \"MRAM\", \"RODATA\", \"STACK_SIZES\", \"TEXT_SECTION\", \n\t\t\t\"PROGBITS\", \"NOBITS\", \"FUNCTION\", \"OBJECT\", \"TRUE\", \"FALSE\", \"Z\", \"NZ\", \n\t\t\t\"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \"C\", \"NC\", \"SZ\", \"SNZ\", \"SPL\", \"SMI\", \n\t\t\t\"SO\", \"SE\", \"NC5\", \"NC6\", \"NC7\", \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \n\t\t\t\"NC13\", \"NC14\", \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \"LTU\", \"LEU\", \n\t\t\t\"GTU\", \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \"XZ\", \"XNZ\", \"XLEU\", \"XGTU\", \n\t\t\t\"XLES\", \"XGTS\", \"SMALL\", \"LARGE\", \"LITTLE\", \"BIG\", \"ZERO_REGISTER\", \"ONE\", \n\t\t\t\"ID\", \"ID2\", \"ID4\", \"ID8\", \"LNEG\", \"MNEG\", \"ADDRSIG\", \"ADDRSIG_SYM\", \n\t\t\t\"ASCII\", \"ASCIZ\", \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \"CFI_ENDPROC\", \"CFI_OFFSET\", \n\t\t\t\"CFI_SECTIONS\", \"CFI_STARTPROC\", \"FILE\", \"GLOBL\", \"LOC\", \"LONG\", \"P2ALIGN\", \n\t\t\t\"QUAD\", \"SECTION\", \"SET\", \"SHORT\", \"SIZE\", \"TEXT_DIRECTIVE\", \"TYPE\", \n\t\t\t\"WEAK\", \"ZERO_DIRECTIVE\", \"IS_STMT\", \"PROLOGUE_END\", \"S_SUFFIX\", \"U_SUFFIX\", \n\t\t\t\"PositiveNumber\", \"GPRegister\", \"PairRegister\", \"Identifier\", \"StringLiteral\", \n\t\t\t\"COMMENT\", \"WHITE_SPACE\"\n\t\t};\n\t}\n\tprivate static final String[] _SYMBOLIC_NAMES = makeSymbolicNames();\n\tpublic static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES);\n\n\t/**\n\t * @deprecated Use {@link #VOCABULARY} instead.\n\t */\n\t@Deprecated\n\tpublic static final String[] tokenNames;\n\tstatic {\n\t\ttokenNames = new String[_SYMBOLIC_NAMES.length];\n\t\tfor (int i = 0; i < tokenNames.length; i++) {\n\t\t\ttokenNames[i] = VOCABULARY.getLiteralName(i);\n\t\t\tif (tokenNames[i] == null) {\n\t\t\t\ttokenNames[i] = VOCABULARY.getSymbolicName(i);\n\t\t\t}\n\n\t\t\tif (tokenNames[i] == null) {\n\t\t\t\ttokenNames[i] = \"<INVALID>\";\n\t\t\t}\n\t\t}\n\t}\n\n\t@Override\n\t@Deprecated\n\tpublic String[] getTokenNames() {\n\t\treturn tokenNames;\n\t}\n\n\t@Override\n\n\tpublic Vocabulary getVocabulary() {\n\t\treturn VOCABULARY;\n\t}\n\n\t@Override\n\tpublic String getGrammarFileName() { return \"assembly.g4\"; }\n\n\t@Override\n\tpublic String[] getRuleNames() { return ruleNames; }\n\n\t@Override\n\tpublic String getSerializedATN() { return _serializedATN; }\n\n\t@Override\n\tpublic ATN getATN() { return _ATN; }\n\n\tpublic assemblyParser(TokenStream input) {\n\t\tsuper(input);\n\t\t_interp = new ParserATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache);\n\t}\n\n\tpublic static class DocumentContext extends ParserRuleContext {\n\t\tpublic TerminalNode EOF() { return getToken(assemblyParser.EOF, 0); }\n\t\tpublic List<DirectiveContext> directive() {\n\t\t\treturn getRuleContexts(DirectiveContext.class);\n\t\t}\n\t\tpublic DirectiveContext directive(int i) {\n\t\t\treturn getRuleContext(DirectiveContext.class,i);\n\t\t}\n\t\tpublic List<InstructionContext> instruction() {\n\t\t\treturn getRuleContexts(InstructionContext.class);\n\t\t}\n\t\tpublic InstructionContext instruction(int i) {\n\t\t\treturn getRuleContext(InstructionContext.class,i);\n\t\t}\n\t\tpublic List<LabelContext> label() {\n\t\t\treturn getRuleContexts(LabelContext.class);\n\t\t}\n\t\tpublic LabelContext label(int i) {\n\t\t\treturn getRuleContext(LabelContext.class,i);\n\t\t}\n\t\tpublic DocumentContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_document; }\n\t}\n\n\tpublic final DocumentContext document() throws RecognitionException {\n\t\tDocumentContext _localctx = new DocumentContext(_ctx, getState());\n\t\tenterRule(_localctx, 0, RULE_document);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(453);\n\t\t\t_errHandler.sync(this);\n\t\t\t_la = _input.LA(1);\n\t\t\twhile ((((_la) & ~0x3f) == 0 && ((1L << _la) & ((1L << ACQUIRE) | (1L << RELEASE) | (1L << BOOT) | (1L << RESUME) | (1L << ADD) | (1L << ADDC) | (1L << AND) | (1L << ANDN) | (1L << ASR) | (1L << CMPB4) | (1L << LSL) | (1L << LSL1) | (1L << LSL1X) | (1L << LSLX) | (1L << LSR) | (1L << LSR1) | (1L << LSR1X) | (1L << LSRX) | (1L << MUL_SH_SH) | (1L << MUL_SH_SL) | (1L << MUL_SH_UH) | (1L << MUL_SH_UL) | (1L << MUL_SL_SH) | (1L << MUL_SL_SL) | (1L << MUL_SL_UH) | (1L << MUL_SL_UL) | (1L << MUL_UH_UH) | (1L << MUL_UH_UL) | (1L << MUL_UL_UH) | (1L << MUL_UL_UL) | (1L << NAND) | (1L << NOR) | (1L << NXOR) | (1L << OR) | (1L << ORN) | (1L << ROL) | (1L << ROR) | (1L << RSUB) | (1L << RSUBC) | (1L << SUB) | (1L << SUBC) | (1L << XOR) | (1L << CALL) | (1L << HASH) | (1L << CAO) | (1L << CLO) | (1L << CLS) | (1L << CLZ) | (1L << EXTSB) | (1L << EXTSH) | (1L << EXTUB) | (1L << EXTUH) | (1L << SATS) | (1L << TIME_CFG) | (1L << DIV_STEP) | (1L << MUL_STEP) | (1L << LSL_ADD) | (1L << LSL_SUB))) != 0) || ((((_la - 64)) & ~0x3f) == 0 && ((1L << (_la - 64)) & ((1L << (LSR_ADD - 64)) | (1L << (ROL_ADD - 64)) | (1L << (ROR_ADD - 64)) | (1L << (TIME - 64)) | (1L << (NOP - 64)) | (1L << (STOP - 64)) | (1L << (FAULT - 64)) | (1L << (MOVD - 64)) | (1L << (SWAPD - 64)) | (1L << (LBS - 64)) | (1L << (LBU - 64)) | (1L << (LD - 64)) | (1L << (LHS - 64)) | (1L << (LHU - 64)) | (1L << (LW - 64)) | (1L << (SB - 64)) | (1L << (SB_ID - 64)) | (1L << (SD - 64)) | (1L << (SD_ID - 64)) | (1L << (SH - 64)) | (1L << (SH_ID - 64)) | (1L << (SW - 64)) | (1L << (SW_ID - 64)) | (1L << (LDMA - 64)) | (1L << (LDMAI - 64)) | (1L << (SDMA - 64)) | (1L << (MOVE - 64)) | (1L << (NEG - 64)) | (1L << (NOT - 64)) | (1L << (BKP - 64)) | (1L << (JEQ - 64)) | (1L << (JNEQ - 64)) | (1L << (JZ - 64)) | (1L << (JNZ - 64)) | (1L << (JLTU - 64)) | (1L << (JGTU - 64)) | (1L << (JLEU - 64)) | (1L << (JGEU - 64)) | (1L << (JLTS - 64)) | (1L << (JGTS - 64)) | (1L << (JLES - 64)) | (1L << (JGES - 64)) | (1L << (JUMP - 64)))) != 0) || ((((_la - 186)) & ~0x3f) == 0 && ((1L << (_la - 186)) & ((1L << (ADDRSIG - 186)) | (1L << (ADDRSIG_SYM - 186)) | (1L << (ASCII - 186)) | (1L << (ASCIZ - 186)) | (1L << (BYTE - 186)) | (1L << (CFI_DEF_CFA_OFFSET - 186)) | (1L << (CFI_ENDPROC - 186)) | (1L << (CFI_OFFSET - 186)) | (1L << (CFI_SECTIONS - 186)) | (1L << (CFI_STARTPROC - 186)) | (1L << (FILE - 186)) | (1L << (GLOBL - 186)) | (1L << (LOC - 186)) | (1L << (LONG - 186)) | (1L << (P2ALIGN - 186)) | (1L << (QUAD - 186)) | (1L << (SECTION - 186)) | (1L << (SET - 186)) | (1L << (SHORT - 186)) | (1L << (SIZE - 186)) | (1L << (TEXT_DIRECTIVE - 186)) | (1L << (TYPE - 186)) | (1L << (WEAK - 186)) | (1L << (ZERO_DIRECTIVE - 186)) | (1L << (Identifier - 186)))) != 0)) {\n\t\t\t\t{\n\t\t\t\tsetState(451);\n\t\t\t\t_errHandler.sync(this);\n\t\t\t\tswitch (_input.LA(1)) {\n\t\t\t\tcase ADDRSIG:\n\t\t\t\tcase ADDRSIG_SYM:\n\t\t\t\tcase ASCII:\n\t\t\t\tcase ASCIZ:\n\t\t\t\tcase BYTE:\n\t\t\t\tcase CFI_DEF_CFA_OFFSET:\n\t\t\t\tcase CFI_ENDPROC:\n\t\t\t\tcase CFI_OFFSET:\n\t\t\t\tcase CFI_SECTIONS:\n\t\t\t\tcase CFI_STARTPROC:\n\t\t\t\tcase FILE:\n\t\t\t\tcase GLOBL:\n\t\t\t\tcase LOC:\n\t\t\t\tcase LONG:\n\t\t\t\tcase P2ALIGN:\n\t\t\t\tcase QUAD:\n\t\t\t\tcase SECTION:\n\t\t\t\tcase SET:\n\t\t\t\tcase SHORT:\n\t\t\t\tcase SIZE:\n\t\t\t\tcase TEXT_DIRECTIVE:\n\t\t\t\tcase TYPE:\n\t\t\t\tcase WEAK:\n\t\t\t\tcase ZERO_DIRECTIVE:\n\t\t\t\t\t{\n\t\t\t\t\tsetState(448);\n\t\t\t\t\tdirective();\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase ACQUIRE:\n\t\t\t\tcase RELEASE:\n\t\t\t\tcase BOOT:\n\t\t\t\tcase RESUME:\n\t\t\t\tcase ADD:\n\t\t\t\tcase ADDC:\n\t\t\t\tcase AND:\n\t\t\t\tcase ANDN:\n\t\t\t\tcase ASR:\n\t\t\t\tcase CMPB4:\n\t\t\t\tcase LSL:\n\t\t\t\tcase LSL1:\n\t\t\t\tcase LSL1X:\n\t\t\t\tcase LSLX:\n\t\t\t\tcase LSR:\n\t\t\t\tcase LSR1:\n\t\t\t\tcase LSR1X:\n\t\t\t\tcase LSRX:\n\t\t\t\tcase MUL_SH_SH:\n\t\t\t\tcase MUL_SH_SL:\n\t\t\t\tcase MUL_SH_UH:\n\t\t\t\tcase MUL_SH_UL:\n\t\t\t\tcase MUL_SL_SH:\n\t\t\t\tcase MUL_SL_SL:\n\t\t\t\tcase MUL_SL_UH:\n\t\t\t\tcase MUL_SL_UL:\n\t\t\t\tcase MUL_UH_UH:\n\t\t\t\tcase MUL_UH_UL:\n\t\t\t\tcase MUL_UL_UH:\n\t\t\t\tcase MUL_UL_UL:\n\t\t\t\tcase NAND:\n\t\t\t\tcase NOR:\n\t\t\t\tcase NXOR:\n\t\t\t\tcase OR:\n\t\t\t\tcase ORN:\n\t\t\t\tcase ROL:\n\t\t\t\tcase ROR:\n\t\t\t\tcase RSUB:\n\t\t\t\tcase RSUBC:\n\t\t\t\tcase SUB:\n\t\t\t\tcase SUBC:\n\t\t\t\tcase XOR:\n\t\t\t\tcase CALL:\n\t\t\t\tcase HASH:\n\t\t\t\tcase CAO:\n\t\t\t\tcase CLO:\n\t\t\t\tcase CLS:\n\t\t\t\tcase CLZ:\n\t\t\t\tcase EXTSB:\n\t\t\t\tcase EXTSH:\n\t\t\t\tcase EXTUB:\n\t\t\t\tcase EXTUH:\n\t\t\t\tcase SATS:\n\t\t\t\tcase TIME_CFG:\n\t\t\t\tcase DIV_STEP:\n\t\t\t\tcase MUL_STEP:\n\t\t\t\tcase LSL_ADD:\n\t\t\t\tcase LSL_SUB:\n\t\t\t\tcase LSR_ADD:\n\t\t\t\tcase ROL_ADD:\n\t\t\t\tcase ROR_ADD:\n\t\t\t\tcase TIME:\n\t\t\t\tcase NOP:\n\t\t\t\tcase STOP:\n\t\t\t\tcase FAULT:\n\t\t\t\tcase MOVD:\n\t\t\t\tcase SWAPD:\n\t\t\t\tcase LBS:\n\t\t\t\tcase LBU:\n\t\t\t\tcase LD:\n\t\t\t\tcase LHS:\n\t\t\t\tcase LHU:\n\t\t\t\tcase LW:\n\t\t\t\tcase SB:\n\t\t\t\tcase SB_ID:\n\t\t\t\tcase SD:\n\t\t\t\tcase SD_ID:\n\t\t\t\tcase SH:\n\t\t\t\tcase SH_ID:\n\t\t\t\tcase SW:\n\t\t\t\tcase SW_ID:\n\t\t\t\tcase LDMA:\n\t\t\t\tcase LDMAI:\n\t\t\t\tcase SDMA:\n\t\t\t\tcase MOVE:\n\t\t\t\tcase NEG:\n\t\t\t\tcase NOT:\n\t\t\t\tcase BKP:\n\t\t\t\tcase JEQ:\n\t\t\t\tcase JNEQ:\n\t\t\t\tcase JZ:\n\t\t\t\tcase JNZ:\n\t\t\t\tcase JLTU:\n\t\t\t\tcase JGTU:\n\t\t\t\tcase JLEU:\n\t\t\t\tcase JGEU:\n\t\t\t\tcase JLTS:\n\t\t\t\tcase JGTS:\n\t\t\t\tcase JLES:\n\t\t\t\tcase JGES:\n\t\t\t\tcase JUMP:\n\t\t\t\t\t{\n\t\t\t\t\tsetState(449);\n\t\t\t\t\tinstruction();\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase Identifier:\n\t\t\t\t\t{\n\t\t\t\t\tsetState(450);\n\t\t\t\t\tlabel();\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tsetState(455);\n\t\t\t\t_errHandler.sync(this);\n\t\t\t\t_la = _input.LA(1);\n\t\t\t}\n\t\t\tsetState(456);\n\t\t\tmatch(EOF);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Negative_numberContext extends ParserRuleContext {\n\t\tpublic TerminalNode PositiveNumber() { return getToken(assemblyParser.PositiveNumber, 0); }\n\t\tpublic Negative_numberContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_negative_number; }\n\t}\n\n\tpublic final Negative_numberContext negative_number() throws RecognitionException {\n\t\tNegative_numberContext _localctx = new Negative_numberContext(_ctx, getState());\n\t\tenterRule(_localctx, 2, RULE_negative_number);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(458);\n\t\t\tmatch(T__0);\n\t\t\tsetState(459);\n\t\t\tmatch(PositiveNumber);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Hex_numberContext extends ParserRuleContext {\n\t\tpublic TerminalNode PositiveNumber() { return getToken(assemblyParser.PositiveNumber, 0); }\n\t\tpublic Hex_numberContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_hex_number; }\n\t}\n\n\tpublic final Hex_numberContext hex_number() throws RecognitionException {\n\t\tHex_numberContext _localctx = new Hex_numberContext(_ctx, getState());\n\t\tenterRule(_localctx, 4, RULE_hex_number);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(461);\n\t\t\tmatch(T__1);\n\t\t\tsetState(462);\n\t\t\tmatch(PositiveNumber);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class NumberContext extends ParserRuleContext {\n\t\tpublic TerminalNode PositiveNumber() { return getToken(assemblyParser.PositiveNumber, 0); }\n\t\tpublic Negative_numberContext negative_number() {\n\t\t\treturn getRuleContext(Negative_numberContext.class,0);\n\t\t}\n\t\tpublic Hex_numberContext hex_number() {\n\t\t\treturn getRuleContext(Hex_numberContext.class,0);\n\t\t}\n\t\tpublic NumberContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_number; }\n\t}\n\n\tpublic final NumberContext number() throws RecognitionException {\n\t\tNumberContext _localctx = new NumberContext(_ctx, getState());\n\t\tenterRule(_localctx, 6, RULE_number);\n\t\ttry {\n\t\t\tsetState(467);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch (_input.LA(1)) {\n\t\t\tcase PositiveNumber:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(464);\n\t\t\t\tmatch(PositiveNumber);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase T__0:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(465);\n\t\t\t\tnegative_number();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase T__1:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(466);\n\t\t\t\thex_number();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rici_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode ACQUIRE() { return getToken(assemblyParser.ACQUIRE, 0); }\n\t\tpublic TerminalNode RELEASE() { return getToken(assemblyParser.RELEASE, 0); }\n\t\tpublic TerminalNode BOOT() { return getToken(assemblyParser.BOOT, 0); }\n\t\tpublic TerminalNode RESUME() { return getToken(assemblyParser.RESUME, 0); }\n\t\tpublic Rici_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rici_op_code; }\n\t}\n\n\tpublic final Rici_op_codeContext rici_op_code() throws RecognitionException {\n\t\tRici_op_codeContext _localctx = new Rici_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 8, RULE_rici_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(469);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & ((1L << ACQUIRE) | (1L << RELEASE) | (1L << BOOT) | (1L << RESUME))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rri_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode ADD() { return getToken(assemblyParser.ADD, 0); }\n\t\tpublic TerminalNode ADDC() { return getToken(assemblyParser.ADDC, 0); }\n\t\tpublic TerminalNode AND() { return getToken(assemblyParser.AND, 0); }\n\t\tpublic TerminalNode ANDN() { return getToken(assemblyParser.ANDN, 0); }\n\t\tpublic TerminalNode ASR() { return getToken(assemblyParser.ASR, 0); }\n\t\tpublic TerminalNode CMPB4() { return getToken(assemblyParser.CMPB4, 0); }\n\t\tpublic TerminalNode LSL() { return getToken(assemblyParser.LSL, 0); }\n\t\tpublic TerminalNode LSL1() { return getToken(assemblyParser.LSL1, 0); }\n\t\tpublic TerminalNode LSL1X() { return getToken(assemblyParser.LSL1X, 0); }\n\t\tpublic TerminalNode LSLX() { return getToken(assemblyParser.LSLX, 0); }\n\t\tpublic TerminalNode LSR() { return getToken(assemblyParser.LSR, 0); }\n\t\tpublic TerminalNode LSR1() { return getToken(assemblyParser.LSR1, 0); }\n\t\tpublic TerminalNode LSR1X() { return getToken(assemblyParser.LSR1X, 0); }\n\t\tpublic TerminalNode LSRX() { return getToken(assemblyParser.LSRX, 0); }\n\t\tpublic TerminalNode MUL_SH_SH() { return getToken(assemblyParser.MUL_SH_SH, 0); }\n\t\tpublic TerminalNode MUL_SH_SL() { return getToken(assemblyParser.MUL_SH_SL, 0); }\n\t\tpublic TerminalNode MUL_SH_UH() { return getToken(assemblyParser.MUL_SH_UH, 0); }\n\t\tpublic TerminalNode MUL_SH_UL() { return getToken(assemblyParser.MUL_SH_UL, 0); }\n\t\tpublic TerminalNode MUL_SL_SH() { return getToken(assemblyParser.MUL_SL_SH, 0); }\n\t\tpublic TerminalNode MUL_SL_SL() { return getToken(assemblyParser.MUL_SL_SL, 0); }\n\t\tpublic TerminalNode MUL_SL_UH() { return getToken(assemblyParser.MUL_SL_UH, 0); }\n\t\tpublic TerminalNode MUL_SL_UL() { return getToken(assemblyParser.MUL_SL_UL, 0); }\n\t\tpublic TerminalNode MUL_UH_UH() { return getToken(assemblyParser.MUL_UH_UH, 0); }\n\t\tpublic TerminalNode MUL_UH_UL() { return getToken(assemblyParser.MUL_UH_UL, 0); }\n\t\tpublic TerminalNode MUL_UL_UH() { return getToken(assemblyParser.MUL_UL_UH, 0); }\n\t\tpublic TerminalNode MUL_UL_UL() { return getToken(assemblyParser.MUL_UL_UL, 0); }\n\t\tpublic TerminalNode NAND() { return getToken(assemblyParser.NAND, 0); }\n\t\tpublic TerminalNode NOR() { return getToken(assemblyParser.NOR, 0); }\n\t\tpublic TerminalNode NXOR() { return getToken(assemblyParser.NXOR, 0); }\n\t\tpublic TerminalNode OR() { return getToken(assemblyParser.OR, 0); }\n\t\tpublic TerminalNode ORN() { return getToken(assemblyParser.ORN, 0); }\n\t\tpublic TerminalNode ROL() { return getToken(assemblyParser.ROL, 0); }\n\t\tpublic TerminalNode ROR() { return getToken(assemblyParser.ROR, 0); }\n\t\tpublic TerminalNode RSUB() { return getToken(assemblyParser.RSUB, 0); }\n\t\tpublic TerminalNode RSUBC() { return getToken(assemblyParser.RSUBC, 0); }\n\t\tpublic TerminalNode SUB() { return getToken(assemblyParser.SUB, 0); }\n\t\tpublic TerminalNode SUBC() { return getToken(assemblyParser.SUBC, 0); }\n\t\tpublic TerminalNode XOR() { return getToken(assemblyParser.XOR, 0); }\n\t\tpublic TerminalNode CALL() { return getToken(assemblyParser.CALL, 0); }\n\t\tpublic TerminalNode HASH() { return getToken(assemblyParser.HASH, 0); }\n\t\tpublic Rri_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rri_op_code; }\n\t}\n\n\tpublic final Rri_op_codeContext rri_op_code() throws RecognitionException {\n\t\tRri_op_codeContext _localctx = new Rri_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 10, RULE_rri_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(471);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & ((1L << ADD) | (1L << ADDC) | (1L << AND) | (1L << ANDN) | (1L << ASR) | (1L << CMPB4) | (1L << LSL) | (1L << LSL1) | (1L << LSL1X) | (1L << LSLX) | (1L << LSR) | (1L << LSR1) | (1L << LSR1X) | (1L << LSRX) | (1L << MUL_SH_SH) | (1L << MUL_SH_SL) | (1L << MUL_SH_UH) | (1L << MUL_SH_UL) | (1L << MUL_SL_SH) | (1L << MUL_SL_SL) | (1L << MUL_SL_UH) | (1L << MUL_SL_UL) | (1L << MUL_UH_UH) | (1L << MUL_UH_UL) | (1L << MUL_UL_UH) | (1L << MUL_UL_UL) | (1L << NAND) | (1L << NOR) | (1L << NXOR) | (1L << OR) | (1L << ORN) | (1L << ROL) | (1L << ROR) | (1L << RSUB) | (1L << RSUBC) | (1L << SUB) | (1L << SUBC) | (1L << XOR) | (1L << CALL) | (1L << HASH))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rr_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode CAO() { return getToken(assemblyParser.CAO, 0); }\n\t\tpublic TerminalNode CLO() { return getToken(assemblyParser.CLO, 0); }\n\t\tpublic TerminalNode CLS() { return getToken(assemblyParser.CLS, 0); }\n\t\tpublic TerminalNode CLZ() { return getToken(assemblyParser.CLZ, 0); }\n\t\tpublic TerminalNode EXTSB() { return getToken(assemblyParser.EXTSB, 0); }\n\t\tpublic TerminalNode EXTSH() { return getToken(assemblyParser.EXTSH, 0); }\n\t\tpublic TerminalNode EXTUB() { return getToken(assemblyParser.EXTUB, 0); }\n\t\tpublic TerminalNode EXTUH() { return getToken(assemblyParser.EXTUH, 0); }\n\t\tpublic TerminalNode SATS() { return getToken(assemblyParser.SATS, 0); }\n\t\tpublic TerminalNode TIME_CFG() { return getToken(assemblyParser.TIME_CFG, 0); }\n\t\tpublic Rr_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rr_op_code; }\n\t}\n\n\tpublic final Rr_op_codeContext rr_op_code() throws RecognitionException {\n\t\tRr_op_codeContext _localctx = new Rr_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 12, RULE_rr_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(473);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & ((1L << CAO) | (1L << CLO) | (1L << CLS) | (1L << CLZ) | (1L << EXTSB) | (1L << EXTSH) | (1L << EXTUB) | (1L << EXTUH) | (1L << SATS) | (1L << TIME_CFG))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Drdici_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode DIV_STEP() { return getToken(assemblyParser.DIV_STEP, 0); }\n\t\tpublic TerminalNode MUL_STEP() { return getToken(assemblyParser.MUL_STEP, 0); }\n\t\tpublic Drdici_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_drdici_op_code; }\n\t}\n\n\tpublic final Drdici_op_codeContext drdici_op_code() throws RecognitionException {\n\t\tDrdici_op_codeContext _localctx = new Drdici_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 14, RULE_drdici_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(475);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==DIV_STEP || _la==MUL_STEP) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrri_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode LSL_ADD() { return getToken(assemblyParser.LSL_ADD, 0); }\n\t\tpublic TerminalNode LSL_SUB() { return getToken(assemblyParser.LSL_SUB, 0); }\n\t\tpublic TerminalNode LSR_ADD() { return getToken(assemblyParser.LSR_ADD, 0); }\n\t\tpublic TerminalNode ROL_ADD() { return getToken(assemblyParser.ROL_ADD, 0); }\n\t\tpublic TerminalNode ROR_ADD() { return getToken(assemblyParser.ROR_ADD, 0); }\n\t\tpublic Rrri_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrri_op_code; }\n\t}\n\n\tpublic final Rrri_op_codeContext rrri_op_code() throws RecognitionException {\n\t\tRrri_op_codeContext _localctx = new Rrri_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 16, RULE_rrri_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(477);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 62)) & ~0x3f) == 0 && ((1L << (_la - 62)) & ((1L << (LSL_ADD - 62)) | (1L << (LSL_SUB - 62)) | (1L << (LSR_ADD - 62)) | (1L << (ROL_ADD - 62)) | (1L << (ROR_ADD - 62)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class R_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode TIME() { return getToken(assemblyParser.TIME, 0); }\n\t\tpublic TerminalNode NOP() { return getToken(assemblyParser.NOP, 0); }\n\t\tpublic R_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_r_op_code; }\n\t}\n\n\tpublic final R_op_codeContext r_op_code() throws RecognitionException {\n\t\tR_op_codeContext _localctx = new R_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 18, RULE_r_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(479);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==TIME || _la==NOP) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ci_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode STOP() { return getToken(assemblyParser.STOP, 0); }\n\t\tpublic Ci_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ci_op_code; }\n\t}\n\n\tpublic final Ci_op_codeContext ci_op_code() throws RecognitionException {\n\t\tCi_op_codeContext _localctx = new Ci_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 20, RULE_ci_op_code);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(481);\n\t\t\tmatch(STOP);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class I_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode FAULT() { return getToken(assemblyParser.FAULT, 0); }\n\t\tpublic I_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_i_op_code; }\n\t}\n\n\tpublic final I_op_codeContext i_op_code() throws RecognitionException {\n\t\tI_op_codeContext _localctx = new I_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 22, RULE_i_op_code);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(483);\n\t\t\tmatch(FAULT);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ddci_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVD() { return getToken(assemblyParser.MOVD, 0); }\n\t\tpublic TerminalNode SWAPD() { return getToken(assemblyParser.SWAPD, 0); }\n\t\tpublic Ddci_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ddci_op_code; }\n\t}\n\n\tpublic final Ddci_op_codeContext ddci_op_code() throws RecognitionException {\n\t\tDdci_op_codeContext _localctx = new Ddci_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 24, RULE_ddci_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(485);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==MOVD || _la==SWAPD) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Load_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode LBS() { return getToken(assemblyParser.LBS, 0); }\n\t\tpublic TerminalNode LBU() { return getToken(assemblyParser.LBU, 0); }\n\t\tpublic TerminalNode LD() { return getToken(assemblyParser.LD, 0); }\n\t\tpublic TerminalNode LHS() { return getToken(assemblyParser.LHS, 0); }\n\t\tpublic TerminalNode LHU() { return getToken(assemblyParser.LHU, 0); }\n\t\tpublic TerminalNode LW() { return getToken(assemblyParser.LW, 0); }\n\t\tpublic Load_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_load_op_code; }\n\t}\n\n\tpublic final Load_op_codeContext load_op_code() throws RecognitionException {\n\t\tLoad_op_codeContext _localctx = new Load_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 26, RULE_load_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(487);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 73)) & ~0x3f) == 0 && ((1L << (_la - 73)) & ((1L << (LBS - 73)) | (1L << (LBU - 73)) | (1L << (LD - 73)) | (1L << (LHS - 73)) | (1L << (LHU - 73)) | (1L << (LW - 73)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Store_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode SB() { return getToken(assemblyParser.SB, 0); }\n\t\tpublic TerminalNode SB_ID() { return getToken(assemblyParser.SB_ID, 0); }\n\t\tpublic TerminalNode SD() { return getToken(assemblyParser.SD, 0); }\n\t\tpublic TerminalNode SD_ID() { return getToken(assemblyParser.SD_ID, 0); }\n\t\tpublic TerminalNode SH() { return getToken(assemblyParser.SH, 0); }\n\t\tpublic TerminalNode SH_ID() { return getToken(assemblyParser.SH_ID, 0); }\n\t\tpublic TerminalNode SW() { return getToken(assemblyParser.SW, 0); }\n\t\tpublic TerminalNode SW_ID() { return getToken(assemblyParser.SW_ID, 0); }\n\t\tpublic Store_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_store_op_code; }\n\t}\n\n\tpublic final Store_op_codeContext store_op_code() throws RecognitionException {\n\t\tStore_op_codeContext _localctx = new Store_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 28, RULE_store_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(489);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 79)) & ~0x3f) == 0 && ((1L << (_la - 79)) & ((1L << (SB - 79)) | (1L << (SB_ID - 79)) | (1L << (SD - 79)) | (1L << (SD_ID - 79)) | (1L << (SH - 79)) | (1L << (SH_ID - 79)) | (1L << (SW - 79)) | (1L << (SW_ID - 79)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Dma_op_codeContext extends ParserRuleContext {\n\t\tpublic TerminalNode LDMA() { return getToken(assemblyParser.LDMA, 0); }\n\t\tpublic TerminalNode LDMAI() { return getToken(assemblyParser.LDMAI, 0); }\n\t\tpublic TerminalNode SDMA() { return getToken(assemblyParser.SDMA, 0); }\n\t\tpublic Dma_op_codeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_dma_op_code; }\n\t}\n\n\tpublic final Dma_op_codeContext dma_op_code() throws RecognitionException {\n\t\tDma_op_codeContext _localctx = new Dma_op_codeContext(_ctx, getState());\n\t\tenterRule(_localctx, 30, RULE_dma_op_code);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(491);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 87)) & ~0x3f) == 0 && ((1L << (_la - 87)) & ((1L << (LDMA - 87)) | (1L << (LDMAI - 87)) | (1L << (SDMA - 87)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Section_nameContext extends ParserRuleContext {\n\t\tpublic TerminalNode ATOMIC() { return getToken(assemblyParser.ATOMIC, 0); }\n\t\tpublic TerminalNode BSS() { return getToken(assemblyParser.BSS, 0); }\n\t\tpublic TerminalNode DATA() { return getToken(assemblyParser.DATA, 0); }\n\t\tpublic TerminalNode DEBUG_ABBREV() { return getToken(assemblyParser.DEBUG_ABBREV, 0); }\n\t\tpublic TerminalNode DEBUG_FRAME() { return getToken(assemblyParser.DEBUG_FRAME, 0); }\n\t\tpublic TerminalNode DEBUG_INFO() { return getToken(assemblyParser.DEBUG_INFO, 0); }\n\t\tpublic TerminalNode DEBUG_LINE() { return getToken(assemblyParser.DEBUG_LINE, 0); }\n\t\tpublic TerminalNode DEBUG_LOC() { return getToken(assemblyParser.DEBUG_LOC, 0); }\n\t\tpublic TerminalNode DEBUG_RANGES() { return getToken(assemblyParser.DEBUG_RANGES, 0); }\n\t\tpublic TerminalNode DEBUG_STR() { return getToken(assemblyParser.DEBUG_STR, 0); }\n\t\tpublic TerminalNode DPU_HOST() { return getToken(assemblyParser.DPU_HOST, 0); }\n\t\tpublic TerminalNode MRAM() { return getToken(assemblyParser.MRAM, 0); }\n\t\tpublic TerminalNode RODATA() { return getToken(assemblyParser.RODATA, 0); }\n\t\tpublic TerminalNode STACK_SIZES() { return getToken(assemblyParser.STACK_SIZES, 0); }\n\t\tpublic TerminalNode TEXT_SECTION() { return getToken(assemblyParser.TEXT_SECTION, 0); }\n\t\tpublic Section_nameContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_section_name; }\n\t}\n\n\tpublic final Section_nameContext section_name() throws RecognitionException {\n\t\tSection_nameContext _localctx = new Section_nameContext(_ctx, getState());\n\t\tenterRule(_localctx, 32, RULE_section_name);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(493);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 107)) & ~0x3f) == 0 && ((1L << (_la - 107)) & ((1L << (ATOMIC - 107)) | (1L << (BSS - 107)) | (1L << (DATA - 107)) | (1L << (DEBUG_ABBREV - 107)) | (1L << (DEBUG_FRAME - 107)) | (1L << (DEBUG_INFO - 107)) | (1L << (DEBUG_LINE - 107)) | (1L << (DEBUG_LOC - 107)) | (1L << (DEBUG_RANGES - 107)) | (1L << (DEBUG_STR - 107)) | (1L << (DPU_HOST - 107)) | (1L << (MRAM - 107)) | (1L << (RODATA - 107)) | (1L << (STACK_SIZES - 107)) | (1L << (TEXT_SECTION - 107)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Section_typesContext extends ParserRuleContext {\n\t\tpublic TerminalNode PROGBITS() { return getToken(assemblyParser.PROGBITS, 0); }\n\t\tpublic TerminalNode NOBITS() { return getToken(assemblyParser.NOBITS, 0); }\n\t\tpublic Section_typesContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_section_types; }\n\t}\n\n\tpublic final Section_typesContext section_types() throws RecognitionException {\n\t\tSection_typesContext _localctx = new Section_typesContext(_ctx, getState());\n\t\tenterRule(_localctx, 34, RULE_section_types);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(495);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==PROGBITS || _la==NOBITS) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Symbol_typeContext extends ParserRuleContext {\n\t\tpublic TerminalNode FUNCTION() { return getToken(assemblyParser.FUNCTION, 0); }\n\t\tpublic TerminalNode OBJECT() { return getToken(assemblyParser.OBJECT, 0); }\n\t\tpublic Symbol_typeContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_symbol_type; }\n\t}\n\n\tpublic final Symbol_typeContext symbol_type() throws RecognitionException {\n\t\tSymbol_typeContext _localctx = new Symbol_typeContext(_ctx, getState());\n\t\tenterRule(_localctx, 36, RULE_symbol_type);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(497);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==FUNCTION || _la==OBJECT) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class ConditionContext extends ParserRuleContext {\n\t\tpublic TerminalNode TRUE() { return getToken(assemblyParser.TRUE, 0); }\n\t\tpublic TerminalNode FALSE() { return getToken(assemblyParser.FALSE, 0); }\n\t\tpublic TerminalNode Z() { return getToken(assemblyParser.Z, 0); }\n\t\tpublic TerminalNode NZ() { return getToken(assemblyParser.NZ, 0); }\n\t\tpublic TerminalNode E() { return getToken(assemblyParser.E, 0); }\n\t\tpublic TerminalNode O() { return getToken(assemblyParser.O, 0); }\n\t\tpublic TerminalNode PL() { return getToken(assemblyParser.PL, 0); }\n\t\tpublic TerminalNode MI() { return getToken(assemblyParser.MI, 0); }\n\t\tpublic TerminalNode OV() { return getToken(assemblyParser.OV, 0); }\n\t\tpublic TerminalNode NOV() { return getToken(assemblyParser.NOV, 0); }\n\t\tpublic TerminalNode C() { return getToken(assemblyParser.C, 0); }\n\t\tpublic TerminalNode NC() { return getToken(assemblyParser.NC, 0); }\n\t\tpublic TerminalNode SZ() { return getToken(assemblyParser.SZ, 0); }\n\t\tpublic TerminalNode SNZ() { return getToken(assemblyParser.SNZ, 0); }\n\t\tpublic TerminalNode SPL() { return getToken(assemblyParser.SPL, 0); }\n\t\tpublic TerminalNode SMI() { return getToken(assemblyParser.SMI, 0); }\n\t\tpublic TerminalNode SO() { return getToken(assemblyParser.SO, 0); }\n\t\tpublic TerminalNode SE() { return getToken(assemblyParser.SE, 0); }\n\t\tpublic TerminalNode NC5() { return getToken(assemblyParser.NC5, 0); }\n\t\tpublic TerminalNode NC6() { return getToken(assemblyParser.NC6, 0); }\n\t\tpublic TerminalNode NC7() { return getToken(assemblyParser.NC7, 0); }\n\t\tpublic TerminalNode NC8() { return getToken(assemblyParser.NC8, 0); }\n\t\tpublic TerminalNode NC9() { return getToken(assemblyParser.NC9, 0); }\n\t\tpublic TerminalNode NC10() { return getToken(assemblyParser.NC10, 0); }\n\t\tpublic TerminalNode NC11() { return getToken(assemblyParser.NC11, 0); }\n\t\tpublic TerminalNode NC12() { return getToken(assemblyParser.NC12, 0); }\n\t\tpublic TerminalNode NC13() { return getToken(assemblyParser.NC13, 0); }\n\t\tpublic TerminalNode NC14() { return getToken(assemblyParser.NC14, 0); }\n\t\tpublic TerminalNode MAX() { return getToken(assemblyParser.MAX, 0); }\n\t\tpublic TerminalNode NMAX() { return getToken(assemblyParser.NMAX, 0); }\n\t\tpublic TerminalNode SH32() { return getToken(assemblyParser.SH32, 0); }\n\t\tpublic TerminalNode NSH32() { return getToken(assemblyParser.NSH32, 0); }\n\t\tpublic TerminalNode EQ() { return getToken(assemblyParser.EQ, 0); }\n\t\tpublic TerminalNode NEQ() { return getToken(assemblyParser.NEQ, 0); }\n\t\tpublic TerminalNode LTU() { return getToken(assemblyParser.LTU, 0); }\n\t\tpublic TerminalNode LEU() { return getToken(assemblyParser.LEU, 0); }\n\t\tpublic TerminalNode GTU() { return getToken(assemblyParser.GTU, 0); }\n\t\tpublic TerminalNode GEU() { return getToken(assemblyParser.GEU, 0); }\n\t\tpublic TerminalNode LTS() { return getToken(assemblyParser.LTS, 0); }\n\t\tpublic TerminalNode LES() { return getToken(assemblyParser.LES, 0); }\n\t\tpublic TerminalNode GTS() { return getToken(assemblyParser.GTS, 0); }\n\t\tpublic TerminalNode GES() { return getToken(assemblyParser.GES, 0); }\n\t\tpublic TerminalNode XZ() { return getToken(assemblyParser.XZ, 0); }\n\t\tpublic TerminalNode XNZ() { return getToken(assemblyParser.XNZ, 0); }\n\t\tpublic TerminalNode XLEU() { return getToken(assemblyParser.XLEU, 0); }\n\t\tpublic TerminalNode XGTU() { return getToken(assemblyParser.XGTU, 0); }\n\t\tpublic TerminalNode XLES() { return getToken(assemblyParser.XLES, 0); }\n\t\tpublic TerminalNode XGTS() { return getToken(assemblyParser.XGTS, 0); }\n\t\tpublic TerminalNode SMALL() { return getToken(assemblyParser.SMALL, 0); }\n\t\tpublic TerminalNode LARGE() { return getToken(assemblyParser.LARGE, 0); }\n\t\tpublic ConditionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_condition; }\n\t}\n\n\tpublic final ConditionContext condition() throws RecognitionException {\n\t\tConditionContext _localctx = new ConditionContext(_ctx, getState());\n\t\tenterRule(_localctx, 38, RULE_condition);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(499);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 126)) & ~0x3f) == 0 && ((1L << (_la - 126)) & ((1L << (TRUE - 126)) | (1L << (FALSE - 126)) | (1L << (Z - 126)) | (1L << (NZ - 126)) | (1L << (E - 126)) | (1L << (O - 126)) | (1L << (PL - 126)) | (1L << (MI - 126)) | (1L << (OV - 126)) | (1L << (NOV - 126)) | (1L << (C - 126)) | (1L << (NC - 126)) | (1L << (SZ - 126)) | (1L << (SNZ - 126)) | (1L << (SPL - 126)) | (1L << (SMI - 126)) | (1L << (SO - 126)) | (1L << (SE - 126)) | (1L << (NC5 - 126)) | (1L << (NC6 - 126)) | (1L << (NC7 - 126)) | (1L << (NC8 - 126)) | (1L << (NC9 - 126)) | (1L << (NC10 - 126)) | (1L << (NC11 - 126)) | (1L << (NC12 - 126)) | (1L << (NC13 - 126)) | (1L << (NC14 - 126)) | (1L << (MAX - 126)) | (1L << (NMAX - 126)) | (1L << (SH32 - 126)) | (1L << (NSH32 - 126)) | (1L << (EQ - 126)) | (1L << (NEQ - 126)) | (1L << (LTU - 126)) | (1L << (LEU - 126)) | (1L << (GTU - 126)) | (1L << (GEU - 126)) | (1L << (LTS - 126)) | (1L << (LES - 126)) | (1L << (GTS - 126)) | (1L << (GES - 126)) | (1L << (XZ - 126)) | (1L << (XNZ - 126)) | (1L << (XLEU - 126)) | (1L << (XGTU - 126)) | (1L << (XLES - 126)) | (1L << (XGTS - 126)) | (1L << (SMALL - 126)) | (1L << (LARGE - 126)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class EndianContext extends ParserRuleContext {\n\t\tpublic TerminalNode LITTLE() { return getToken(assemblyParser.LITTLE, 0); }\n\t\tpublic TerminalNode BIG() { return getToken(assemblyParser.BIG, 0); }\n\t\tpublic EndianContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_endian; }\n\t}\n\n\tpublic final EndianContext endian() throws RecognitionException {\n\t\tEndianContext _localctx = new EndianContext(_ctx, getState());\n\t\tenterRule(_localctx, 40, RULE_endian);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(501);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(_la==LITTLE || _la==BIG) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sp_registerContext extends ParserRuleContext {\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic TerminalNode ONE() { return getToken(assemblyParser.ONE, 0); }\n\t\tpublic TerminalNode ID() { return getToken(assemblyParser.ID, 0); }\n\t\tpublic TerminalNode ID2() { return getToken(assemblyParser.ID2, 0); }\n\t\tpublic TerminalNode ID4() { return getToken(assemblyParser.ID4, 0); }\n\t\tpublic TerminalNode ID8() { return getToken(assemblyParser.ID8, 0); }\n\t\tpublic TerminalNode LNEG() { return getToken(assemblyParser.LNEG, 0); }\n\t\tpublic TerminalNode MNEG() { return getToken(assemblyParser.MNEG, 0); }\n\t\tpublic Sp_registerContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sp_register; }\n\t}\n\n\tpublic final Sp_registerContext sp_register() throws RecognitionException {\n\t\tSp_registerContext _localctx = new Sp_registerContext(_ctx, getState());\n\t\tenterRule(_localctx, 42, RULE_sp_register);\n\t\tint _la;\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(503);\n\t\t\t_la = _input.LA(1);\n\t\t\tif ( !(((((_la - 178)) & ~0x3f) == 0 && ((1L << (_la - 178)) & ((1L << (ZERO_REGISTER - 178)) | (1L << (ONE - 178)) | (1L << (ID - 178)) | (1L << (ID2 - 178)) | (1L << (ID4 - 178)) | (1L << (ID8 - 178)) | (1L << (LNEG - 178)) | (1L << (MNEG - 178)))) != 0)) ) {\n\t\t\t_errHandler.recoverInline(this);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif ( _input.LA(1)==Token.EOF ) matchedEOF = true;\n\t\t\t\t_errHandler.reportMatch(this);\n\t\t\t\tconsume();\n\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Src_registerContext extends ParserRuleContext {\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Sp_registerContext sp_register() {\n\t\t\treturn getRuleContext(Sp_registerContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_src_register; }\n\t}\n\n\tpublic final Src_registerContext src_register() throws RecognitionException {\n\t\tSrc_registerContext _localctx = new Src_registerContext(_ctx, getState());\n\t\tenterRule(_localctx, 44, RULE_src_register);\n\t\ttry {\n\t\t\tsetState(507);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch (_input.LA(1)) {\n\t\t\tcase GPRegister:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(505);\n\t\t\t\tmatch(GPRegister);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase ZERO_REGISTER:\n\t\t\tcase ONE:\n\t\t\tcase ID:\n\t\t\tcase ID2:\n\t\t\tcase ID4:\n\t\t\tcase ID8:\n\t\t\tcase LNEG:\n\t\t\tcase MNEG:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(506);\n\t\t\t\tsp_register();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Program_counterContext extends ParserRuleContext {\n\t\tpublic Primary_expressionContext primary_expression() {\n\t\t\treturn getRuleContext(Primary_expressionContext.class,0);\n\t\t}\n\t\tpublic Add_expressionContext add_expression() {\n\t\t\treturn getRuleContext(Add_expressionContext.class,0);\n\t\t}\n\t\tpublic Sub_expressionContext sub_expression() {\n\t\t\treturn getRuleContext(Sub_expressionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_program_counter; }\n\t}\n\n\tpublic final Program_counterContext program_counter() throws RecognitionException {\n\t\tProgram_counterContext _localctx = new Program_counterContext(_ctx, getState());\n\t\tenterRule(_localctx, 46, RULE_program_counter);\n\t\ttry {\n\t\t\tsetState(512);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,4,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(509);\n\t\t\t\tprimary_expression();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(510);\n\t\t\t\tadd_expression();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(511);\n\t\t\t\tsub_expression();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Add_expressionContext extends ParserRuleContext {\n\t\tpublic List<Primary_expressionContext> primary_expression() {\n\t\t\treturn getRuleContexts(Primary_expressionContext.class);\n\t\t}\n\t\tpublic Primary_expressionContext primary_expression(int i) {\n\t\t\treturn getRuleContext(Primary_expressionContext.class,i);\n\t\t}\n\t\tpublic Add_expressionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_add_expression; }\n\t}\n\n\tpublic final Add_expressionContext add_expression() throws RecognitionException {\n\t\tAdd_expressionContext _localctx = new Add_expressionContext(_ctx, getState());\n\t\tenterRule(_localctx, 48, RULE_add_expression);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(514);\n\t\t\tprimary_expression();\n\t\t\tsetState(515);\n\t\t\tmatch(T__2);\n\t\t\tsetState(516);\n\t\t\tprimary_expression();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sub_expressionContext extends ParserRuleContext {\n\t\tpublic List<Primary_expressionContext> primary_expression() {\n\t\t\treturn getRuleContexts(Primary_expressionContext.class);\n\t\t}\n\t\tpublic Primary_expressionContext primary_expression(int i) {\n\t\t\treturn getRuleContext(Primary_expressionContext.class,i);\n\t\t}\n\t\tpublic Sub_expressionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sub_expression; }\n\t}\n\n\tpublic final Sub_expressionContext sub_expression() throws RecognitionException {\n\t\tSub_expressionContext _localctx = new Sub_expressionContext(_ctx, getState());\n\t\tenterRule(_localctx, 50, RULE_sub_expression);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(518);\n\t\t\tprimary_expression();\n\t\t\tsetState(519);\n\t\t\tmatch(T__0);\n\t\t\tsetState(520);\n\t\t\tprimary_expression();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Primary_expressionContext extends ParserRuleContext {\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Section_nameContext section_name() {\n\t\t\treturn getRuleContext(Section_nameContext.class,0);\n\t\t}\n\t\tpublic Primary_expressionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_primary_expression; }\n\t}\n\n\tpublic final Primary_expressionContext primary_expression() throws RecognitionException {\n\t\tPrimary_expressionContext _localctx = new Primary_expressionContext(_ctx, getState());\n\t\tenterRule(_localctx, 52, RULE_primary_expression);\n\t\ttry {\n\t\t\tsetState(525);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch (_input.LA(1)) {\n\t\t\tcase T__0:\n\t\t\tcase T__1:\n\t\t\tcase PositiveNumber:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(522);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase Identifier:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(523);\n\t\t\t\tmatch(Identifier);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase ATOMIC:\n\t\t\tcase BSS:\n\t\t\tcase DATA:\n\t\t\tcase DEBUG_ABBREV:\n\t\t\tcase DEBUG_FRAME:\n\t\t\tcase DEBUG_INFO:\n\t\t\tcase DEBUG_LINE:\n\t\t\tcase DEBUG_LOC:\n\t\t\tcase DEBUG_RANGES:\n\t\t\tcase DEBUG_STR:\n\t\t\tcase DPU_HOST:\n\t\t\tcase MRAM:\n\t\t\tcase RODATA:\n\t\t\tcase STACK_SIZES:\n\t\t\tcase TEXT_SECTION:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(524);\n\t\t\t\tsection_name();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class DirectiveContext extends ParserRuleContext {\n\t\tpublic Addrsig_directiveContext addrsig_directive() {\n\t\t\treturn getRuleContext(Addrsig_directiveContext.class,0);\n\t\t}\n\t\tpublic Addrsig_sym_directiveContext addrsig_sym_directive() {\n\t\t\treturn getRuleContext(Addrsig_sym_directiveContext.class,0);\n\t\t}\n\t\tpublic Ascii_directiveContext ascii_directive() {\n\t\t\treturn getRuleContext(Ascii_directiveContext.class,0);\n\t\t}\n\t\tpublic Asciz_directiveContext asciz_directive() {\n\t\t\treturn getRuleContext(Asciz_directiveContext.class,0);\n\t\t}\n\t\tpublic Byte_directiveContext byte_directive() {\n\t\t\treturn getRuleContext(Byte_directiveContext.class,0);\n\t\t}\n\t\tpublic Cfi_def_cfa_offset_directiveContext cfi_def_cfa_offset_directive() {\n\t\t\treturn getRuleContext(Cfi_def_cfa_offset_directiveContext.class,0);\n\t\t}\n\t\tpublic Cfi_endproc_directiveContext cfi_endproc_directive() {\n\t\t\treturn getRuleContext(Cfi_endproc_directiveContext.class,0);\n\t\t}\n\t\tpublic Cfi_offset_directiveContext cfi_offset_directive() {\n\t\t\treturn getRuleContext(Cfi_offset_directiveContext.class,0);\n\t\t}\n\t\tpublic Cfi_sections_directiveContext cfi_sections_directive() {\n\t\t\treturn getRuleContext(Cfi_sections_directiveContext.class,0);\n\t\t}\n\t\tpublic Cfi_startproc_directiveContext cfi_startproc_directive() {\n\t\t\treturn getRuleContext(Cfi_startproc_directiveContext.class,0);\n\t\t}\n\t\tpublic File_directiveContext file_directive() {\n\t\t\treturn getRuleContext(File_directiveContext.class,0);\n\t\t}\n\t\tpublic Global_directiveContext global_directive() {\n\t\t\treturn getRuleContext(Global_directiveContext.class,0);\n\t\t}\n\t\tpublic Loc_directiveContext loc_directive() {\n\t\t\treturn getRuleContext(Loc_directiveContext.class,0);\n\t\t}\n\t\tpublic Long_directiveContext long_directive() {\n\t\t\treturn getRuleContext(Long_directiveContext.class,0);\n\t\t}\n\t\tpublic P2align_directiveContext p2align_directive() {\n\t\t\treturn getRuleContext(P2align_directiveContext.class,0);\n\t\t}\n\t\tpublic Quad_directiveContext quad_directive() {\n\t\t\treturn getRuleContext(Quad_directiveContext.class,0);\n\t\t}\n\t\tpublic Section_directiveContext section_directive() {\n\t\t\treturn getRuleContext(Section_directiveContext.class,0);\n\t\t}\n\t\tpublic Set_directiveContext set_directive() {\n\t\t\treturn getRuleContext(Set_directiveContext.class,0);\n\t\t}\n\t\tpublic Short_directiveContext short_directive() {\n\t\t\treturn getRuleContext(Short_directiveContext.class,0);\n\t\t}\n\t\tpublic Size_directiveContext size_directive() {\n\t\t\treturn getRuleContext(Size_directiveContext.class,0);\n\t\t}\n\t\tpublic Stack_sizes_directiveContext stack_sizes_directive() {\n\t\t\treturn getRuleContext(Stack_sizes_directiveContext.class,0);\n\t\t}\n\t\tpublic Text_directiveContext text_directive() {\n\t\t\treturn getRuleContext(Text_directiveContext.class,0);\n\t\t}\n\t\tpublic Type_directiveContext type_directive() {\n\t\t\treturn getRuleContext(Type_directiveContext.class,0);\n\t\t}\n\t\tpublic Weak_directiveContext weak_directive() {\n\t\t\treturn getRuleContext(Weak_directiveContext.class,0);\n\t\t}\n\t\tpublic Zero_directiveContext zero_directive() {\n\t\t\treturn getRuleContext(Zero_directiveContext.class,0);\n\t\t}\n\t\tpublic DirectiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_directive; }\n\t}\n\n\tpublic final DirectiveContext directive() throws RecognitionException {\n\t\tDirectiveContext _localctx = new DirectiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 54, RULE_directive);\n\t\ttry {\n\t\t\tsetState(552);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,6,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(527);\n\t\t\t\taddrsig_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(528);\n\t\t\t\taddrsig_sym_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(529);\n\t\t\t\tascii_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(530);\n\t\t\t\tasciz_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(531);\n\t\t\t\tbyte_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(532);\n\t\t\t\tcfi_def_cfa_offset_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tenterOuterAlt(_localctx, 7);\n\t\t\t\t{\n\t\t\t\tsetState(533);\n\t\t\t\tcfi_endproc_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tenterOuterAlt(_localctx, 8);\n\t\t\t\t{\n\t\t\t\tsetState(534);\n\t\t\t\tcfi_offset_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tenterOuterAlt(_localctx, 9);\n\t\t\t\t{\n\t\t\t\tsetState(535);\n\t\t\t\tcfi_sections_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tenterOuterAlt(_localctx, 10);\n\t\t\t\t{\n\t\t\t\tsetState(536);\n\t\t\t\tcfi_startproc_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tenterOuterAlt(_localctx, 11);\n\t\t\t\t{\n\t\t\t\tsetState(537);\n\t\t\t\tfile_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tenterOuterAlt(_localctx, 12);\n\t\t\t\t{\n\t\t\t\tsetState(538);\n\t\t\t\tglobal_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 13:\n\t\t\t\tenterOuterAlt(_localctx, 13);\n\t\t\t\t{\n\t\t\t\tsetState(539);\n\t\t\t\tloc_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 14:\n\t\t\t\tenterOuterAlt(_localctx, 14);\n\t\t\t\t{\n\t\t\t\tsetState(540);\n\t\t\t\tlong_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 15:\n\t\t\t\tenterOuterAlt(_localctx, 15);\n\t\t\t\t{\n\t\t\t\tsetState(541);\n\t\t\t\tp2align_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 16:\n\t\t\t\tenterOuterAlt(_localctx, 16);\n\t\t\t\t{\n\t\t\t\tsetState(542);\n\t\t\t\tquad_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 17:\n\t\t\t\tenterOuterAlt(_localctx, 17);\n\t\t\t\t{\n\t\t\t\tsetState(543);\n\t\t\t\tsection_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 18:\n\t\t\t\tenterOuterAlt(_localctx, 18);\n\t\t\t\t{\n\t\t\t\tsetState(544);\n\t\t\t\tset_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 19:\n\t\t\t\tenterOuterAlt(_localctx, 19);\n\t\t\t\t{\n\t\t\t\tsetState(545);\n\t\t\t\tshort_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 20:\n\t\t\t\tenterOuterAlt(_localctx, 20);\n\t\t\t\t{\n\t\t\t\tsetState(546);\n\t\t\t\tsize_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 21:\n\t\t\t\tenterOuterAlt(_localctx, 21);\n\t\t\t\t{\n\t\t\t\tsetState(547);\n\t\t\t\tstack_sizes_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 22:\n\t\t\t\tenterOuterAlt(_localctx, 22);\n\t\t\t\t{\n\t\t\t\tsetState(548);\n\t\t\t\ttext_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 23:\n\t\t\t\tenterOuterAlt(_localctx, 23);\n\t\t\t\t{\n\t\t\t\tsetState(549);\n\t\t\t\ttype_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 24:\n\t\t\t\tenterOuterAlt(_localctx, 24);\n\t\t\t\t{\n\t\t\t\tsetState(550);\n\t\t\t\tweak_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 25:\n\t\t\t\tenterOuterAlt(_localctx, 25);\n\t\t\t\t{\n\t\t\t\tsetState(551);\n\t\t\t\tzero_directive();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Addrsig_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode ADDRSIG() { return getToken(assemblyParser.ADDRSIG, 0); }\n\t\tpublic Addrsig_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_addrsig_directive; }\n\t}\n\n\tpublic final Addrsig_directiveContext addrsig_directive() throws RecognitionException {\n\t\tAddrsig_directiveContext _localctx = new Addrsig_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 56, RULE_addrsig_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(554);\n\t\t\tmatch(ADDRSIG);\n\t\t\tsetState(555);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Addrsig_sym_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode ADDRSIG_SYM() { return getToken(assemblyParser.ADDRSIG_SYM, 0); }\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Addrsig_sym_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_addrsig_sym_directive; }\n\t}\n\n\tpublic final Addrsig_sym_directiveContext addrsig_sym_directive() throws RecognitionException {\n\t\tAddrsig_sym_directiveContext _localctx = new Addrsig_sym_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 58, RULE_addrsig_sym_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(557);\n\t\t\tmatch(ADDRSIG_SYM);\n\t\t\tsetState(558);\n\t\t\tmatch(T__3);\n\t\t\tsetState(559);\n\t\t\tmatch(Identifier);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ascii_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode ASCII() { return getToken(assemblyParser.ASCII, 0); }\n\t\tpublic TerminalNode StringLiteral() { return getToken(assemblyParser.StringLiteral, 0); }\n\t\tpublic Ascii_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ascii_directive; }\n\t}\n\n\tpublic final Ascii_directiveContext ascii_directive() throws RecognitionException {\n\t\tAscii_directiveContext _localctx = new Ascii_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 60, RULE_ascii_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(561);\n\t\t\tmatch(ASCII);\n\t\t\tsetState(562);\n\t\t\tmatch(T__3);\n\t\t\tsetState(563);\n\t\t\tmatch(StringLiteral);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Asciz_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode ASCIZ() { return getToken(assemblyParser.ASCIZ, 0); }\n\t\tpublic TerminalNode StringLiteral() { return getToken(assemblyParser.StringLiteral, 0); }\n\t\tpublic Asciz_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_asciz_directive; }\n\t}\n\n\tpublic final Asciz_directiveContext asciz_directive() throws RecognitionException {\n\t\tAsciz_directiveContext _localctx = new Asciz_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 62, RULE_asciz_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(565);\n\t\t\tmatch(ASCIZ);\n\t\t\tsetState(566);\n\t\t\tmatch(T__3);\n\t\t\tsetState(567);\n\t\t\tmatch(StringLiteral);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Byte_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode BYTE() { return getToken(assemblyParser.BYTE, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Byte_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_byte_directive; }\n\t}\n\n\tpublic final Byte_directiveContext byte_directive() throws RecognitionException {\n\t\tByte_directiveContext _localctx = new Byte_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 64, RULE_byte_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(569);\n\t\t\tmatch(BYTE);\n\t\t\tsetState(570);\n\t\t\tmatch(T__3);\n\t\t\tsetState(571);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Cfi_def_cfa_offset_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode CFI_DEF_CFA_OFFSET() { return getToken(assemblyParser.CFI_DEF_CFA_OFFSET, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Cfi_def_cfa_offset_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_cfi_def_cfa_offset_directive; }\n\t}\n\n\tpublic final Cfi_def_cfa_offset_directiveContext cfi_def_cfa_offset_directive() throws RecognitionException {\n\t\tCfi_def_cfa_offset_directiveContext _localctx = new Cfi_def_cfa_offset_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 66, RULE_cfi_def_cfa_offset_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(573);\n\t\t\tmatch(CFI_DEF_CFA_OFFSET);\n\t\t\tsetState(574);\n\t\t\tmatch(T__3);\n\t\t\tsetState(575);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Cfi_endproc_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode CFI_ENDPROC() { return getToken(assemblyParser.CFI_ENDPROC, 0); }\n\t\tpublic Cfi_endproc_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_cfi_endproc_directive; }\n\t}\n\n\tpublic final Cfi_endproc_directiveContext cfi_endproc_directive() throws RecognitionException {\n\t\tCfi_endproc_directiveContext _localctx = new Cfi_endproc_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 68, RULE_cfi_endproc_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(577);\n\t\t\tmatch(CFI_ENDPROC);\n\t\t\tsetState(578);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Cfi_offset_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode CFI_OFFSET() { return getToken(assemblyParser.CFI_OFFSET, 0); }\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Cfi_offset_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_cfi_offset_directive; }\n\t}\n\n\tpublic final Cfi_offset_directiveContext cfi_offset_directive() throws RecognitionException {\n\t\tCfi_offset_directiveContext _localctx = new Cfi_offset_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 70, RULE_cfi_offset_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(580);\n\t\t\tmatch(CFI_OFFSET);\n\t\t\tsetState(581);\n\t\t\tmatch(T__3);\n\t\t\tsetState(582);\n\t\t\tnumber();\n\t\t\tsetState(583);\n\t\t\tmatch(T__3);\n\t\t\tsetState(584);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Cfi_sections_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode CFI_SECTIONS() { return getToken(assemblyParser.CFI_SECTIONS, 0); }\n\t\tpublic Section_nameContext section_name() {\n\t\t\treturn getRuleContext(Section_nameContext.class,0);\n\t\t}\n\t\tpublic Cfi_sections_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_cfi_sections_directive; }\n\t}\n\n\tpublic final Cfi_sections_directiveContext cfi_sections_directive() throws RecognitionException {\n\t\tCfi_sections_directiveContext _localctx = new Cfi_sections_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 72, RULE_cfi_sections_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(586);\n\t\t\tmatch(CFI_SECTIONS);\n\t\t\tsetState(587);\n\t\t\tmatch(T__3);\n\t\t\tsetState(588);\n\t\t\tsection_name();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Cfi_startproc_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode CFI_STARTPROC() { return getToken(assemblyParser.CFI_STARTPROC, 0); }\n\t\tpublic Cfi_startproc_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_cfi_startproc_directive; }\n\t}\n\n\tpublic final Cfi_startproc_directiveContext cfi_startproc_directive() throws RecognitionException {\n\t\tCfi_startproc_directiveContext _localctx = new Cfi_startproc_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 74, RULE_cfi_startproc_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(590);\n\t\t\tmatch(CFI_STARTPROC);\n\t\t\tsetState(591);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class File_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode FILE() { return getToken(assemblyParser.FILE, 0); }\n\t\tpublic List<TerminalNode> StringLiteral() { return getTokens(assemblyParser.StringLiteral); }\n\t\tpublic TerminalNode StringLiteral(int i) {\n\t\t\treturn getToken(assemblyParser.StringLiteral, i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic File_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_file_directive; }\n\t}\n\n\tpublic final File_directiveContext file_directive() throws RecognitionException {\n\t\tFile_directiveContext _localctx = new File_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 76, RULE_file_directive);\n\t\ttry {\n\t\t\tsetState(602);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,7,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(593);\n\t\t\t\tmatch(FILE);\n\t\t\t\tsetState(594);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(595);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(596);\n\t\t\t\tmatch(FILE);\n\t\t\t\tsetState(597);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(598);\n\t\t\t\tnumber();\n\t\t\t\tsetState(599);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\tsetState(600);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Global_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode GLOBL() { return getToken(assemblyParser.GLOBL, 0); }\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Global_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_global_directive; }\n\t}\n\n\tpublic final Global_directiveContext global_directive() throws RecognitionException {\n\t\tGlobal_directiveContext _localctx = new Global_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 78, RULE_global_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(604);\n\t\t\tmatch(GLOBL);\n\t\t\tsetState(605);\n\t\t\tmatch(T__3);\n\t\t\tsetState(606);\n\t\t\tmatch(Identifier);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Loc_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode LOC() { return getToken(assemblyParser.LOC, 0); }\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic TerminalNode IS_STMT() { return getToken(assemblyParser.IS_STMT, 0); }\n\t\tpublic TerminalNode PROLOGUE_END() { return getToken(assemblyParser.PROLOGUE_END, 0); }\n\t\tpublic Loc_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_loc_directive; }\n\t}\n\n\tpublic final Loc_directiveContext loc_directive() throws RecognitionException {\n\t\tLoc_directiveContext _localctx = new Loc_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 80, RULE_loc_directive);\n\t\ttry {\n\t\t\tsetState(629);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,8,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(608);\n\t\t\t\tmatch(LOC);\n\t\t\t\tsetState(609);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(610);\n\t\t\t\tnumber();\n\t\t\t\tsetState(611);\n\t\t\t\tnumber();\n\t\t\t\tsetState(612);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(614);\n\t\t\t\tmatch(LOC);\n\t\t\t\tsetState(615);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(616);\n\t\t\t\tnumber();\n\t\t\t\tsetState(617);\n\t\t\t\tnumber();\n\t\t\t\tsetState(618);\n\t\t\t\tnumber();\n\t\t\t\tsetState(619);\n\t\t\t\tmatch(IS_STMT);\n\t\t\t\tsetState(620);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(622);\n\t\t\t\tmatch(LOC);\n\t\t\t\tsetState(623);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(624);\n\t\t\t\tnumber();\n\t\t\t\tsetState(625);\n\t\t\t\tnumber();\n\t\t\t\tsetState(626);\n\t\t\t\tnumber();\n\t\t\t\tsetState(627);\n\t\t\t\tmatch(PROLOGUE_END);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Long_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode LONG() { return getToken(assemblyParser.LONG, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Long_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_long_directive; }\n\t}\n\n\tpublic final Long_directiveContext long_directive() throws RecognitionException {\n\t\tLong_directiveContext _localctx = new Long_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 82, RULE_long_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(631);\n\t\t\tmatch(LONG);\n\t\t\tsetState(632);\n\t\t\tmatch(T__3);\n\t\t\tsetState(633);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class P2align_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode P2ALIGN() { return getToken(assemblyParser.P2ALIGN, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic P2align_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_p2align_directive; }\n\t}\n\n\tpublic final P2align_directiveContext p2align_directive() throws RecognitionException {\n\t\tP2align_directiveContext _localctx = new P2align_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 84, RULE_p2align_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(635);\n\t\t\tmatch(P2ALIGN);\n\t\t\tsetState(636);\n\t\t\tmatch(T__3);\n\t\t\tsetState(637);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Quad_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode QUAD() { return getToken(assemblyParser.QUAD, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Quad_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_quad_directive; }\n\t}\n\n\tpublic final Quad_directiveContext quad_directive() throws RecognitionException {\n\t\tQuad_directiveContext _localctx = new Quad_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 86, RULE_quad_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(639);\n\t\t\tmatch(QUAD);\n\t\t\tsetState(640);\n\t\t\tmatch(T__3);\n\t\t\tsetState(641);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Section_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode SECTION() { return getToken(assemblyParser.SECTION, 0); }\n\t\tpublic Section_nameContext section_name() {\n\t\t\treturn getRuleContext(Section_nameContext.class,0);\n\t\t}\n\t\tpublic TerminalNode StringLiteral() { return getToken(assemblyParser.StringLiteral, 0); }\n\t\tpublic Section_typesContext section_types() {\n\t\t\treturn getRuleContext(Section_typesContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Section_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_section_directive; }\n\t}\n\n\tpublic final Section_directiveContext section_directive() throws RecognitionException {\n\t\tSection_directiveContext _localctx = new Section_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 88, RULE_section_directive);\n\t\ttry {\n\t\t\tsetState(683);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,9,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(643);\n\t\t\t\tmatch(SECTION);\n\t\t\t\tsetState(644);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(645);\n\t\t\t\tsection_name();\n\t\t\t\tsetState(646);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(647);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\tsetState(648);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(649);\n\t\t\t\tsection_types();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(651);\n\t\t\t\tmatch(SECTION);\n\t\t\t\tsetState(652);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(653);\n\t\t\t\tsection_name();\n\t\t\t\tsetState(654);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(655);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\tsetState(656);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(657);\n\t\t\t\tsection_types();\n\t\t\t\tsetState(658);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(659);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(661);\n\t\t\t\tmatch(SECTION);\n\t\t\t\tsetState(662);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(663);\n\t\t\t\tsection_name();\n\t\t\t\tsetState(664);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(665);\n\t\t\t\tmatch(Identifier);\n\t\t\t\tsetState(666);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(667);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\tsetState(668);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(669);\n\t\t\t\tsection_types();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(671);\n\t\t\t\tmatch(SECTION);\n\t\t\t\tsetState(672);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(673);\n\t\t\t\tsection_name();\n\t\t\t\tsetState(674);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(675);\n\t\t\t\tmatch(Identifier);\n\t\t\t\tsetState(676);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(677);\n\t\t\t\tmatch(StringLiteral);\n\t\t\t\tsetState(678);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(679);\n\t\t\t\tsection_types();\n\t\t\t\tsetState(680);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(681);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Set_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode SET() { return getToken(assemblyParser.SET, 0); }\n\t\tpublic List<TerminalNode> Identifier() { return getTokens(assemblyParser.Identifier); }\n\t\tpublic TerminalNode Identifier(int i) {\n\t\t\treturn getToken(assemblyParser.Identifier, i);\n\t\t}\n\t\tpublic Set_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_set_directive; }\n\t}\n\n\tpublic final Set_directiveContext set_directive() throws RecognitionException {\n\t\tSet_directiveContext _localctx = new Set_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 90, RULE_set_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(685);\n\t\t\tmatch(SET);\n\t\t\tsetState(686);\n\t\t\tmatch(T__3);\n\t\t\tsetState(687);\n\t\t\tmatch(Identifier);\n\t\t\tsetState(688);\n\t\t\tmatch(T__3);\n\t\t\tsetState(689);\n\t\t\tmatch(Identifier);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Short_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode SHORT() { return getToken(assemblyParser.SHORT, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Short_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_short_directive; }\n\t}\n\n\tpublic final Short_directiveContext short_directive() throws RecognitionException {\n\t\tShort_directiveContext _localctx = new Short_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 92, RULE_short_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(691);\n\t\t\tmatch(SHORT);\n\t\t\tsetState(692);\n\t\t\tmatch(T__3);\n\t\t\tsetState(693);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Size_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode SIZE() { return getToken(assemblyParser.SIZE, 0); }\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Size_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_size_directive; }\n\t}\n\n\tpublic final Size_directiveContext size_directive() throws RecognitionException {\n\t\tSize_directiveContext _localctx = new Size_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 94, RULE_size_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(695);\n\t\t\tmatch(SIZE);\n\t\t\tsetState(696);\n\t\t\tmatch(T__3);\n\t\t\tsetState(697);\n\t\t\tmatch(Identifier);\n\t\t\tsetState(698);\n\t\t\tmatch(T__3);\n\t\t\tsetState(699);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Stack_sizes_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode SECTION() { return getToken(assemblyParser.SECTION, 0); }\n\t\tpublic TerminalNode STACK_SIZES() { return getToken(assemblyParser.STACK_SIZES, 0); }\n\t\tpublic TerminalNode StringLiteral() { return getToken(assemblyParser.StringLiteral, 0); }\n\t\tpublic Section_typesContext section_types() {\n\t\t\treturn getRuleContext(Section_typesContext.class,0);\n\t\t}\n\t\tpublic Section_nameContext section_name() {\n\t\t\treturn getRuleContext(Section_nameContext.class,0);\n\t\t}\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Stack_sizes_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_stack_sizes_directive; }\n\t}\n\n\tpublic final Stack_sizes_directiveContext stack_sizes_directive() throws RecognitionException {\n\t\tStack_sizes_directiveContext _localctx = new Stack_sizes_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 96, RULE_stack_sizes_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(701);\n\t\t\tmatch(SECTION);\n\t\t\tsetState(702);\n\t\t\tmatch(T__3);\n\t\t\tsetState(703);\n\t\t\tmatch(STACK_SIZES);\n\t\t\tsetState(704);\n\t\t\tmatch(T__3);\n\t\t\tsetState(705);\n\t\t\tmatch(StringLiteral);\n\t\t\tsetState(706);\n\t\t\tmatch(T__3);\n\t\t\tsetState(707);\n\t\t\tsection_types();\n\t\t\tsetState(708);\n\t\t\tmatch(T__3);\n\t\t\tsetState(709);\n\t\t\tsection_name();\n\t\t\tsetState(710);\n\t\t\tmatch(T__3);\n\t\t\tsetState(711);\n\t\t\tmatch(Identifier);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Text_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode TEXT_DIRECTIVE() { return getToken(assemblyParser.TEXT_DIRECTIVE, 0); }\n\t\tpublic Text_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_text_directive; }\n\t}\n\n\tpublic final Text_directiveContext text_directive() throws RecognitionException {\n\t\tText_directiveContext _localctx = new Text_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 98, RULE_text_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(713);\n\t\t\tmatch(TEXT_DIRECTIVE);\n\t\t\tsetState(714);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Type_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode TYPE() { return getToken(assemblyParser.TYPE, 0); }\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Symbol_typeContext symbol_type() {\n\t\t\treturn getRuleContext(Symbol_typeContext.class,0);\n\t\t}\n\t\tpublic Type_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_type_directive; }\n\t}\n\n\tpublic final Type_directiveContext type_directive() throws RecognitionException {\n\t\tType_directiveContext _localctx = new Type_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 100, RULE_type_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(716);\n\t\t\tmatch(TYPE);\n\t\t\tsetState(717);\n\t\t\tmatch(T__3);\n\t\t\tsetState(718);\n\t\t\tmatch(Identifier);\n\t\t\tsetState(719);\n\t\t\tmatch(T__3);\n\t\t\tsetState(720);\n\t\t\tsymbol_type();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Weak_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode WEAK() { return getToken(assemblyParser.WEAK, 0); }\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic Weak_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_weak_directive; }\n\t}\n\n\tpublic final Weak_directiveContext weak_directive() throws RecognitionException {\n\t\tWeak_directiveContext _localctx = new Weak_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 102, RULE_weak_directive);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(722);\n\t\t\tmatch(WEAK);\n\t\t\tsetState(723);\n\t\t\tmatch(T__3);\n\t\t\tsetState(724);\n\t\t\tmatch(Identifier);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zero_directiveContext extends ParserRuleContext {\n\t\tpublic TerminalNode ZERO_DIRECTIVE() { return getToken(assemblyParser.ZERO_DIRECTIVE, 0); }\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Zero_directiveContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zero_directive; }\n\t}\n\n\tpublic final Zero_directiveContext zero_directive() throws RecognitionException {\n\t\tZero_directiveContext _localctx = new Zero_directiveContext(_ctx, getState());\n\t\tenterRule(_localctx, 104, RULE_zero_directive);\n\t\ttry {\n\t\t\tsetState(735);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,10,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(726);\n\t\t\t\tmatch(ZERO_DIRECTIVE);\n\t\t\t\tsetState(727);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(728);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(729);\n\t\t\t\tmatch(ZERO_DIRECTIVE);\n\t\t\t\tsetState(730);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(731);\n\t\t\t\tnumber();\n\t\t\t\tsetState(732);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(733);\n\t\t\t\tnumber();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class InstructionContext extends ParserRuleContext {\n\t\tpublic Rici_instructionContext rici_instruction() {\n\t\t\treturn getRuleContext(Rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Rri_instructionContext rri_instruction() {\n\t\t\treturn getRuleContext(Rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Rric_instructionContext rric_instruction() {\n\t\t\treturn getRuleContext(Rric_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrici_instructionContext rrici_instruction() {\n\t\t\treturn getRuleContext(Rrici_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrr_instructionContext rrr_instruction() {\n\t\t\treturn getRuleContext(Rrr_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrrc_instructionContext rrrc_instruction() {\n\t\t\treturn getRuleContext(Rrrc_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrrci_instructionContext rrrci_instruction() {\n\t\t\treturn getRuleContext(Rrrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Zri_instructionContext zri_instruction() {\n\t\t\treturn getRuleContext(Zri_instructionContext.class,0);\n\t\t}\n\t\tpublic Zric_instructionContext zric_instruction() {\n\t\t\treturn getRuleContext(Zric_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrici_instructionContext zrici_instruction() {\n\t\t\treturn getRuleContext(Zrici_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrr_instructionContext zrr_instruction() {\n\t\t\treturn getRuleContext(Zrr_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrrc_instructionContext zrrc_instruction() {\n\t\t\treturn getRuleContext(Zrrc_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrrci_instructionContext zrrci_instruction() {\n\t\t\treturn getRuleContext(Zrrci_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rri_instructionContext s_rri_instruction() {\n\t\t\treturn getRuleContext(S_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rric_instructionContext s_rric_instruction() {\n\t\t\treturn getRuleContext(S_rric_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrici_instructionContext s_rrici_instruction() {\n\t\t\treturn getRuleContext(S_rrici_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrr_instructionContext s_rrr_instruction() {\n\t\t\treturn getRuleContext(S_rrr_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrrc_instructionContext s_rrrc_instruction() {\n\t\t\treturn getRuleContext(S_rrrc_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrrci_instructionContext s_rrrci_instruction() {\n\t\t\treturn getRuleContext(S_rrrci_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rri_instructionContext u_rri_instruction() {\n\t\t\treturn getRuleContext(U_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rric_instructionContext u_rric_instruction() {\n\t\t\treturn getRuleContext(U_rric_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrici_instructionContext u_rrici_instruction() {\n\t\t\treturn getRuleContext(U_rrici_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrr_instructionContext u_rrr_instruction() {\n\t\t\treturn getRuleContext(U_rrr_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrrc_instructionContext u_rrrc_instruction() {\n\t\t\treturn getRuleContext(U_rrrc_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrrci_instructionContext u_rrrci_instruction() {\n\t\t\treturn getRuleContext(U_rrrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Rr_instructionContext rr_instruction() {\n\t\t\treturn getRuleContext(Rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrc_instructionContext rrc_instruction() {\n\t\t\treturn getRuleContext(Rrc_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrci_instructionContext rrci_instruction() {\n\t\t\treturn getRuleContext(Rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Zr_instructionContext zr_instruction() {\n\t\t\treturn getRuleContext(Zr_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrc_instructionContext zrc_instruction() {\n\t\t\treturn getRuleContext(Zrc_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrci_instructionContext zrci_instruction() {\n\t\t\treturn getRuleContext(Zrci_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rr_instructionContext s_rr_instruction() {\n\t\t\treturn getRuleContext(S_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrc_instructionContext s_rrc_instruction() {\n\t\t\treturn getRuleContext(S_rrc_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrci_instructionContext s_rrci_instruction() {\n\t\t\treturn getRuleContext(S_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rr_instructionContext u_rr_instruction() {\n\t\t\treturn getRuleContext(U_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrc_instructionContext u_rrc_instruction() {\n\t\t\treturn getRuleContext(U_rrc_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrci_instructionContext u_rrci_instruction() {\n\t\t\treturn getRuleContext(U_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Drdici_instructionContext drdici_instruction() {\n\t\t\treturn getRuleContext(Drdici_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrri_instructionContext rrri_instruction() {\n\t\t\treturn getRuleContext(Rrri_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrrici_instructionContext rrrici_instruction() {\n\t\t\treturn getRuleContext(Rrrici_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrri_instructionContext zrri_instruction() {\n\t\t\treturn getRuleContext(Zrri_instructionContext.class,0);\n\t\t}\n\t\tpublic Zrrici_instructionContext zrrici_instruction() {\n\t\t\treturn getRuleContext(Zrrici_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrri_instructionContext s_rrri_instruction() {\n\t\t\treturn getRuleContext(S_rrri_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rrrici_instructionContext s_rrrici_instruction() {\n\t\t\treturn getRuleContext(S_rrrici_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrri_instructionContext u_rrri_instruction() {\n\t\t\treturn getRuleContext(U_rrri_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rrrici_instructionContext u_rrrici_instruction() {\n\t\t\treturn getRuleContext(U_rrrici_instructionContext.class,0);\n\t\t}\n\t\tpublic Rir_instructionContext rir_instruction() {\n\t\t\treturn getRuleContext(Rir_instructionContext.class,0);\n\t\t}\n\t\tpublic Rirc_instructionContext rirc_instruction() {\n\t\t\treturn getRuleContext(Rirc_instructionContext.class,0);\n\t\t}\n\t\tpublic Rirci_instructionContext rirci_instruction() {\n\t\t\treturn getRuleContext(Rirci_instructionContext.class,0);\n\t\t}\n\t\tpublic Zir_instructionContext zir_instruction() {\n\t\t\treturn getRuleContext(Zir_instructionContext.class,0);\n\t\t}\n\t\tpublic Zirc_instructionContext zirc_instruction() {\n\t\t\treturn getRuleContext(Zirc_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rirc_instructionContext s_rirc_instruction() {\n\t\t\treturn getRuleContext(S_rirc_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rirci_instructionContext s_rirci_instruction() {\n\t\t\treturn getRuleContext(S_rirci_instructionContext.class,0);\n\t\t}\n\t\tpublic R_instructionContext r_instruction() {\n\t\t\treturn getRuleContext(R_instructionContext.class,0);\n\t\t}\n\t\tpublic Rci_instructionContext rci_instruction() {\n\t\t\treturn getRuleContext(Rci_instructionContext.class,0);\n\t\t}\n\t\tpublic Z_instructionContext z_instruction() {\n\t\t\treturn getRuleContext(Z_instructionContext.class,0);\n\t\t}\n\t\tpublic Zci_instructionContext zci_instruction() {\n\t\t\treturn getRuleContext(Zci_instructionContext.class,0);\n\t\t}\n\t\tpublic S_r_instructionContext s_r_instruction() {\n\t\t\treturn getRuleContext(S_r_instructionContext.class,0);\n\t\t}\n\t\tpublic S_rci_instructionContext s_rci_instruction() {\n\t\t\treturn getRuleContext(S_rci_instructionContext.class,0);\n\t\t}\n\t\tpublic U_r_instructionContext u_r_instruction() {\n\t\t\treturn getRuleContext(U_r_instructionContext.class,0);\n\t\t}\n\t\tpublic U_rci_instructionContext u_rci_instruction() {\n\t\t\treturn getRuleContext(U_rci_instructionContext.class,0);\n\t\t}\n\t\tpublic Ci_instructionContext ci_instruction() {\n\t\t\treturn getRuleContext(Ci_instructionContext.class,0);\n\t\t}\n\t\tpublic I_instructionContext i_instruction() {\n\t\t\treturn getRuleContext(I_instructionContext.class,0);\n\t\t}\n\t\tpublic Ddci_instructionContext ddci_instruction() {\n\t\t\treturn getRuleContext(Ddci_instructionContext.class,0);\n\t\t}\n\t\tpublic Erri_instructionContext erri_instruction() {\n\t\t\treturn getRuleContext(Erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Edri_instructionContext edri_instruction() {\n\t\t\treturn getRuleContext(Edri_instructionContext.class,0);\n\t\t}\n\t\tpublic S_erri_instructionContext s_erri_instruction() {\n\t\t\treturn getRuleContext(S_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic U_erri_instructionContext u_erri_instruction() {\n\t\t\treturn getRuleContext(U_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Erii_instructionContext erii_instruction() {\n\t\t\treturn getRuleContext(Erii_instructionContext.class,0);\n\t\t}\n\t\tpublic Erir_instructionContext erir_instruction() {\n\t\t\treturn getRuleContext(Erir_instructionContext.class,0);\n\t\t}\n\t\tpublic Erid_instructionContext erid_instruction() {\n\t\t\treturn getRuleContext(Erid_instructionContext.class,0);\n\t\t}\n\t\tpublic Dma_rri_instructionContext dma_rri_instruction() {\n\t\t\treturn getRuleContext(Dma_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Synthetic_sugar_instructionContext synthetic_sugar_instruction() {\n\t\t\treturn getRuleContext(Synthetic_sugar_instructionContext.class,0);\n\t\t}\n\t\tpublic InstructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_instruction; }\n\t}\n\n\tpublic final InstructionContext instruction() throws RecognitionException {\n\t\tInstructionContext _localctx = new InstructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 106, RULE_instruction);\n\t\ttry {\n\t\t\tsetState(813);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,11,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(737);\n\t\t\t\trici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(738);\n\t\t\t\trri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(739);\n\t\t\t\trric_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(740);\n\t\t\t\trrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(741);\n\t\t\t\trrr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(742);\n\t\t\t\trrrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tenterOuterAlt(_localctx, 7);\n\t\t\t\t{\n\t\t\t\tsetState(743);\n\t\t\t\trrrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tenterOuterAlt(_localctx, 8);\n\t\t\t\t{\n\t\t\t\tsetState(744);\n\t\t\t\tzri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tenterOuterAlt(_localctx, 9);\n\t\t\t\t{\n\t\t\t\tsetState(745);\n\t\t\t\tzric_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tenterOuterAlt(_localctx, 10);\n\t\t\t\t{\n\t\t\t\tsetState(746);\n\t\t\t\tzrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tenterOuterAlt(_localctx, 11);\n\t\t\t\t{\n\t\t\t\tsetState(747);\n\t\t\t\tzrr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tenterOuterAlt(_localctx, 12);\n\t\t\t\t{\n\t\t\t\tsetState(748);\n\t\t\t\tzrrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 13:\n\t\t\t\tenterOuterAlt(_localctx, 13);\n\t\t\t\t{\n\t\t\t\tsetState(749);\n\t\t\t\tzrrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 14:\n\t\t\t\tenterOuterAlt(_localctx, 14);\n\t\t\t\t{\n\t\t\t\tsetState(750);\n\t\t\t\ts_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 15:\n\t\t\t\tenterOuterAlt(_localctx, 15);\n\t\t\t\t{\n\t\t\t\tsetState(751);\n\t\t\t\ts_rric_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 16:\n\t\t\t\tenterOuterAlt(_localctx, 16);\n\t\t\t\t{\n\t\t\t\tsetState(752);\n\t\t\t\ts_rrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 17:\n\t\t\t\tenterOuterAlt(_localctx, 17);\n\t\t\t\t{\n\t\t\t\tsetState(753);\n\t\t\t\ts_rrr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 18:\n\t\t\t\tenterOuterAlt(_localctx, 18);\n\t\t\t\t{\n\t\t\t\tsetState(754);\n\t\t\t\ts_rrrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 19:\n\t\t\t\tenterOuterAlt(_localctx, 19);\n\t\t\t\t{\n\t\t\t\tsetState(755);\n\t\t\t\ts_rrrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 20:\n\t\t\t\tenterOuterAlt(_localctx, 20);\n\t\t\t\t{\n\t\t\t\tsetState(756);\n\t\t\t\tu_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 21:\n\t\t\t\tenterOuterAlt(_localctx, 21);\n\t\t\t\t{\n\t\t\t\tsetState(757);\n\t\t\t\tu_rric_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 22:\n\t\t\t\tenterOuterAlt(_localctx, 22);\n\t\t\t\t{\n\t\t\t\tsetState(758);\n\t\t\t\tu_rrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 23:\n\t\t\t\tenterOuterAlt(_localctx, 23);\n\t\t\t\t{\n\t\t\t\tsetState(759);\n\t\t\t\tu_rrr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 24:\n\t\t\t\tenterOuterAlt(_localctx, 24);\n\t\t\t\t{\n\t\t\t\tsetState(760);\n\t\t\t\tu_rrrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 25:\n\t\t\t\tenterOuterAlt(_localctx, 25);\n\t\t\t\t{\n\t\t\t\tsetState(761);\n\t\t\t\tu_rrrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 26:\n\t\t\t\tenterOuterAlt(_localctx, 26);\n\t\t\t\t{\n\t\t\t\tsetState(762);\n\t\t\t\trr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 27:\n\t\t\t\tenterOuterAlt(_localctx, 27);\n\t\t\t\t{\n\t\t\t\tsetState(763);\n\t\t\t\trrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 28:\n\t\t\t\tenterOuterAlt(_localctx, 28);\n\t\t\t\t{\n\t\t\t\tsetState(764);\n\t\t\t\trrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 29:\n\t\t\t\tenterOuterAlt(_localctx, 29);\n\t\t\t\t{\n\t\t\t\tsetState(765);\n\t\t\t\tzr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 30:\n\t\t\t\tenterOuterAlt(_localctx, 30);\n\t\t\t\t{\n\t\t\t\tsetState(766);\n\t\t\t\tzrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 31:\n\t\t\t\tenterOuterAlt(_localctx, 31);\n\t\t\t\t{\n\t\t\t\tsetState(767);\n\t\t\t\tzrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 32:\n\t\t\t\tenterOuterAlt(_localctx, 32);\n\t\t\t\t{\n\t\t\t\tsetState(768);\n\t\t\t\ts_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 33:\n\t\t\t\tenterOuterAlt(_localctx, 33);\n\t\t\t\t{\n\t\t\t\tsetState(769);\n\t\t\t\ts_rrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 34:\n\t\t\t\tenterOuterAlt(_localctx, 34);\n\t\t\t\t{\n\t\t\t\tsetState(770);\n\t\t\t\ts_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 35:\n\t\t\t\tenterOuterAlt(_localctx, 35);\n\t\t\t\t{\n\t\t\t\tsetState(771);\n\t\t\t\tu_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 36:\n\t\t\t\tenterOuterAlt(_localctx, 36);\n\t\t\t\t{\n\t\t\t\tsetState(772);\n\t\t\t\tu_rrc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 37:\n\t\t\t\tenterOuterAlt(_localctx, 37);\n\t\t\t\t{\n\t\t\t\tsetState(773);\n\t\t\t\tu_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 38:\n\t\t\t\tenterOuterAlt(_localctx, 38);\n\t\t\t\t{\n\t\t\t\tsetState(774);\n\t\t\t\tdrdici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 39:\n\t\t\t\tenterOuterAlt(_localctx, 39);\n\t\t\t\t{\n\t\t\t\tsetState(775);\n\t\t\t\trrri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 40:\n\t\t\t\tenterOuterAlt(_localctx, 40);\n\t\t\t\t{\n\t\t\t\tsetState(776);\n\t\t\t\trrrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 41:\n\t\t\t\tenterOuterAlt(_localctx, 41);\n\t\t\t\t{\n\t\t\t\tsetState(777);\n\t\t\t\tzrri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 42:\n\t\t\t\tenterOuterAlt(_localctx, 42);\n\t\t\t\t{\n\t\t\t\tsetState(778);\n\t\t\t\tzrrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 43:\n\t\t\t\tenterOuterAlt(_localctx, 43);\n\t\t\t\t{\n\t\t\t\tsetState(779);\n\t\t\t\ts_rrri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 44:\n\t\t\t\tenterOuterAlt(_localctx, 44);\n\t\t\t\t{\n\t\t\t\tsetState(780);\n\t\t\t\ts_rrrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 45:\n\t\t\t\tenterOuterAlt(_localctx, 45);\n\t\t\t\t{\n\t\t\t\tsetState(781);\n\t\t\t\tu_rrri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 46:\n\t\t\t\tenterOuterAlt(_localctx, 46);\n\t\t\t\t{\n\t\t\t\tsetState(782);\n\t\t\t\tu_rrrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 47:\n\t\t\t\tenterOuterAlt(_localctx, 47);\n\t\t\t\t{\n\t\t\t\tsetState(783);\n\t\t\t\trir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 48:\n\t\t\t\tenterOuterAlt(_localctx, 48);\n\t\t\t\t{\n\t\t\t\tsetState(784);\n\t\t\t\trirc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 49:\n\t\t\t\tenterOuterAlt(_localctx, 49);\n\t\t\t\t{\n\t\t\t\tsetState(785);\n\t\t\t\trirci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 50:\n\t\t\t\tenterOuterAlt(_localctx, 50);\n\t\t\t\t{\n\t\t\t\tsetState(786);\n\t\t\t\tzir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 51:\n\t\t\t\tenterOuterAlt(_localctx, 51);\n\t\t\t\t{\n\t\t\t\tsetState(787);\n\t\t\t\tzirc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 52:\n\t\t\t\tenterOuterAlt(_localctx, 52);\n\t\t\t\t{\n\t\t\t\tsetState(788);\n\t\t\t\tzrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 53:\n\t\t\t\tenterOuterAlt(_localctx, 53);\n\t\t\t\t{\n\t\t\t\tsetState(789);\n\t\t\t\ts_rirc_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 54:\n\t\t\t\tenterOuterAlt(_localctx, 54);\n\t\t\t\t{\n\t\t\t\tsetState(790);\n\t\t\t\ts_rirci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 55:\n\t\t\t\tenterOuterAlt(_localctx, 55);\n\t\t\t\t{\n\t\t\t\tsetState(791);\n\t\t\t\tu_rric_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 56:\n\t\t\t\tenterOuterAlt(_localctx, 56);\n\t\t\t\t{\n\t\t\t\tsetState(792);\n\t\t\t\tu_rrici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 57:\n\t\t\t\tenterOuterAlt(_localctx, 57);\n\t\t\t\t{\n\t\t\t\tsetState(793);\n\t\t\t\tr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 58:\n\t\t\t\tenterOuterAlt(_localctx, 58);\n\t\t\t\t{\n\t\t\t\tsetState(794);\n\t\t\t\trci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 59:\n\t\t\t\tenterOuterAlt(_localctx, 59);\n\t\t\t\t{\n\t\t\t\tsetState(795);\n\t\t\t\tz_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 60:\n\t\t\t\tenterOuterAlt(_localctx, 60);\n\t\t\t\t{\n\t\t\t\tsetState(796);\n\t\t\t\tzci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 61:\n\t\t\t\tenterOuterAlt(_localctx, 61);\n\t\t\t\t{\n\t\t\t\tsetState(797);\n\t\t\t\ts_r_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 62:\n\t\t\t\tenterOuterAlt(_localctx, 62);\n\t\t\t\t{\n\t\t\t\tsetState(798);\n\t\t\t\ts_rci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 63:\n\t\t\t\tenterOuterAlt(_localctx, 63);\n\t\t\t\t{\n\t\t\t\tsetState(799);\n\t\t\t\tu_r_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 64:\n\t\t\t\tenterOuterAlt(_localctx, 64);\n\t\t\t\t{\n\t\t\t\tsetState(800);\n\t\t\t\tu_rci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 65:\n\t\t\t\tenterOuterAlt(_localctx, 65);\n\t\t\t\t{\n\t\t\t\tsetState(801);\n\t\t\t\tci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 66:\n\t\t\t\tenterOuterAlt(_localctx, 66);\n\t\t\t\t{\n\t\t\t\tsetState(802);\n\t\t\t\ti_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 67:\n\t\t\t\tenterOuterAlt(_localctx, 67);\n\t\t\t\t{\n\t\t\t\tsetState(803);\n\t\t\t\tddci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 68:\n\t\t\t\tenterOuterAlt(_localctx, 68);\n\t\t\t\t{\n\t\t\t\tsetState(804);\n\t\t\t\terri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 69:\n\t\t\t\tenterOuterAlt(_localctx, 69);\n\t\t\t\t{\n\t\t\t\tsetState(805);\n\t\t\t\tedri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 70:\n\t\t\t\tenterOuterAlt(_localctx, 70);\n\t\t\t\t{\n\t\t\t\tsetState(806);\n\t\t\t\ts_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 71:\n\t\t\t\tenterOuterAlt(_localctx, 71);\n\t\t\t\t{\n\t\t\t\tsetState(807);\n\t\t\t\tu_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 72:\n\t\t\t\tenterOuterAlt(_localctx, 72);\n\t\t\t\t{\n\t\t\t\tsetState(808);\n\t\t\t\terii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 73:\n\t\t\t\tenterOuterAlt(_localctx, 73);\n\t\t\t\t{\n\t\t\t\tsetState(809);\n\t\t\t\terir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 74:\n\t\t\t\tenterOuterAlt(_localctx, 74);\n\t\t\t\t{\n\t\t\t\tsetState(810);\n\t\t\t\terid_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 75:\n\t\t\t\tenterOuterAlt(_localctx, 75);\n\t\t\t\t{\n\t\t\t\tsetState(811);\n\t\t\t\tdma_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 76:\n\t\t\t\tenterOuterAlt(_localctx, 76);\n\t\t\t\t{\n\t\t\t\tsetState(812);\n\t\t\t\tsynthetic_sugar_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rici_instructionContext extends ParserRuleContext {\n\t\tpublic Rici_op_codeContext rici_op_code() {\n\t\t\treturn getRuleContext(Rici_op_codeContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<Program_counterContext> program_counter() {\n\t\t\treturn getRuleContexts(Program_counterContext.class);\n\t\t}\n\t\tpublic Program_counterContext program_counter(int i) {\n\t\t\treturn getRuleContext(Program_counterContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rici_instruction; }\n\t}\n\n\tpublic final Rici_instructionContext rici_instruction() throws RecognitionException {\n\t\tRici_instructionContext _localctx = new Rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 108, RULE_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(815);\n\t\t\trici_op_code();\n\t\t\tsetState(816);\n\t\t\tmatch(T__3);\n\t\t\tsetState(817);\n\t\t\tsrc_register();\n\t\t\tsetState(818);\n\t\t\tmatch(T__3);\n\t\t\tsetState(819);\n\t\t\tprogram_counter();\n\t\t\tsetState(820);\n\t\t\tmatch(T__3);\n\t\t\tsetState(821);\n\t\t\tcondition();\n\t\t\tsetState(822);\n\t\t\tmatch(T__3);\n\t\t\tsetState(823);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rri_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rri_instruction; }\n\t}\n\n\tpublic final Rri_instructionContext rri_instruction() throws RecognitionException {\n\t\tRri_instructionContext _localctx = new Rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 110, RULE_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(825);\n\t\t\trri_op_code();\n\t\t\tsetState(826);\n\t\t\tmatch(T__3);\n\t\t\tsetState(827);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(828);\n\t\t\tmatch(T__3);\n\t\t\tsetState(829);\n\t\t\tsrc_register();\n\t\t\tsetState(830);\n\t\t\tmatch(T__3);\n\t\t\tsetState(831);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rric_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Rric_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rric_instruction; }\n\t}\n\n\tpublic final Rric_instructionContext rric_instruction() throws RecognitionException {\n\t\tRric_instructionContext _localctx = new Rric_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 112, RULE_rric_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(833);\n\t\t\trri_op_code();\n\t\t\tsetState(834);\n\t\t\tmatch(T__3);\n\t\t\tsetState(835);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(836);\n\t\t\tmatch(T__3);\n\t\t\tsetState(837);\n\t\t\tsrc_register();\n\t\t\tsetState(838);\n\t\t\tmatch(T__3);\n\t\t\tsetState(839);\n\t\t\tnumber();\n\t\t\tsetState(840);\n\t\t\tmatch(T__3);\n\t\t\tsetState(841);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrici_instruction; }\n\t}\n\n\tpublic final Rrici_instructionContext rrici_instruction() throws RecognitionException {\n\t\tRrici_instructionContext _localctx = new Rrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 114, RULE_rrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(843);\n\t\t\trri_op_code();\n\t\t\tsetState(844);\n\t\t\tmatch(T__3);\n\t\t\tsetState(845);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(846);\n\t\t\tmatch(T__3);\n\t\t\tsetState(847);\n\t\t\tsrc_register();\n\t\t\tsetState(848);\n\t\t\tmatch(T__3);\n\t\t\tsetState(849);\n\t\t\tnumber();\n\t\t\tsetState(850);\n\t\t\tmatch(T__3);\n\t\t\tsetState(851);\n\t\t\tcondition();\n\t\t\tsetState(852);\n\t\t\tmatch(T__3);\n\t\t\tsetState(853);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrr_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Rrr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrr_instruction; }\n\t}\n\n\tpublic final Rrr_instructionContext rrr_instruction() throws RecognitionException {\n\t\tRrr_instructionContext _localctx = new Rrr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 116, RULE_rrr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(855);\n\t\t\trri_op_code();\n\t\t\tsetState(856);\n\t\t\tmatch(T__3);\n\t\t\tsetState(857);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(858);\n\t\t\tmatch(T__3);\n\t\t\tsetState(859);\n\t\t\tsrc_register();\n\t\t\tsetState(860);\n\t\t\tmatch(T__3);\n\t\t\tsetState(861);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Rrrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrrc_instruction; }\n\t}\n\n\tpublic final Rrrc_instructionContext rrrc_instruction() throws RecognitionException {\n\t\tRrrc_instructionContext _localctx = new Rrrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 118, RULE_rrrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(863);\n\t\t\trri_op_code();\n\t\t\tsetState(864);\n\t\t\tmatch(T__3);\n\t\t\tsetState(865);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(866);\n\t\t\tmatch(T__3);\n\t\t\tsetState(867);\n\t\t\tsrc_register();\n\t\t\tsetState(868);\n\t\t\tmatch(T__3);\n\t\t\tsetState(869);\n\t\t\tsrc_register();\n\t\t\tsetState(870);\n\t\t\tmatch(T__3);\n\t\t\tsetState(871);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rrrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrrci_instruction; }\n\t}\n\n\tpublic final Rrrci_instructionContext rrrci_instruction() throws RecognitionException {\n\t\tRrrci_instructionContext _localctx = new Rrrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 120, RULE_rrrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(873);\n\t\t\trri_op_code();\n\t\t\tsetState(874);\n\t\t\tmatch(T__3);\n\t\t\tsetState(875);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(876);\n\t\t\tmatch(T__3);\n\t\t\tsetState(877);\n\t\t\tsrc_register();\n\t\t\tsetState(878);\n\t\t\tmatch(T__3);\n\t\t\tsetState(879);\n\t\t\tsrc_register();\n\t\t\tsetState(880);\n\t\t\tmatch(T__3);\n\t\t\tsetState(881);\n\t\t\tcondition();\n\t\t\tsetState(882);\n\t\t\tmatch(T__3);\n\t\t\tsetState(883);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zri_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zri_instruction; }\n\t}\n\n\tpublic final Zri_instructionContext zri_instruction() throws RecognitionException {\n\t\tZri_instructionContext _localctx = new Zri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 122, RULE_zri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(885);\n\t\t\trri_op_code();\n\t\t\tsetState(886);\n\t\t\tmatch(T__3);\n\t\t\tsetState(887);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(888);\n\t\t\tmatch(T__3);\n\t\t\tsetState(889);\n\t\t\tsrc_register();\n\t\t\tsetState(890);\n\t\t\tmatch(T__3);\n\t\t\tsetState(891);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zric_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Zric_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zric_instruction; }\n\t}\n\n\tpublic final Zric_instructionContext zric_instruction() throws RecognitionException {\n\t\tZric_instructionContext _localctx = new Zric_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 124, RULE_zric_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(893);\n\t\t\trri_op_code();\n\t\t\tsetState(894);\n\t\t\tmatch(T__3);\n\t\t\tsetState(895);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(896);\n\t\t\tmatch(T__3);\n\t\t\tsetState(897);\n\t\t\tsrc_register();\n\t\t\tsetState(898);\n\t\t\tmatch(T__3);\n\t\t\tsetState(899);\n\t\t\tnumber();\n\t\t\tsetState(900);\n\t\t\tmatch(T__3);\n\t\t\tsetState(901);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrici_instruction; }\n\t}\n\n\tpublic final Zrici_instructionContext zrici_instruction() throws RecognitionException {\n\t\tZrici_instructionContext _localctx = new Zrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 126, RULE_zrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(903);\n\t\t\trri_op_code();\n\t\t\tsetState(904);\n\t\t\tmatch(T__3);\n\t\t\tsetState(905);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(906);\n\t\t\tmatch(T__3);\n\t\t\tsetState(907);\n\t\t\tsrc_register();\n\t\t\tsetState(908);\n\t\t\tmatch(T__3);\n\t\t\tsetState(909);\n\t\t\tnumber();\n\t\t\tsetState(910);\n\t\t\tmatch(T__3);\n\t\t\tsetState(911);\n\t\t\tcondition();\n\t\t\tsetState(912);\n\t\t\tmatch(T__3);\n\t\t\tsetState(913);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrr_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Zrr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrr_instruction; }\n\t}\n\n\tpublic final Zrr_instructionContext zrr_instruction() throws RecognitionException {\n\t\tZrr_instructionContext _localctx = new Zrr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 128, RULE_zrr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(915);\n\t\t\trri_op_code();\n\t\t\tsetState(916);\n\t\t\tmatch(T__3);\n\t\t\tsetState(917);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(918);\n\t\t\tmatch(T__3);\n\t\t\tsetState(919);\n\t\t\tsrc_register();\n\t\t\tsetState(920);\n\t\t\tmatch(T__3);\n\t\t\tsetState(921);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Zrrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrrc_instruction; }\n\t}\n\n\tpublic final Zrrc_instructionContext zrrc_instruction() throws RecognitionException {\n\t\tZrrc_instructionContext _localctx = new Zrrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 130, RULE_zrrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(923);\n\t\t\trri_op_code();\n\t\t\tsetState(924);\n\t\t\tmatch(T__3);\n\t\t\tsetState(925);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(926);\n\t\t\tmatch(T__3);\n\t\t\tsetState(927);\n\t\t\tsrc_register();\n\t\t\tsetState(928);\n\t\t\tmatch(T__3);\n\t\t\tsetState(929);\n\t\t\tsrc_register();\n\t\t\tsetState(930);\n\t\t\tmatch(T__3);\n\t\t\tsetState(931);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zrrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrrci_instruction; }\n\t}\n\n\tpublic final Zrrci_instructionContext zrrci_instruction() throws RecognitionException {\n\t\tZrrci_instructionContext _localctx = new Zrrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 132, RULE_zrrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(933);\n\t\t\trri_op_code();\n\t\t\tsetState(934);\n\t\t\tmatch(T__3);\n\t\t\tsetState(935);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(936);\n\t\t\tmatch(T__3);\n\t\t\tsetState(937);\n\t\t\tsrc_register();\n\t\t\tsetState(938);\n\t\t\tmatch(T__3);\n\t\t\tsetState(939);\n\t\t\tsrc_register();\n\t\t\tsetState(940);\n\t\t\tmatch(T__3);\n\t\t\tsetState(941);\n\t\t\tcondition();\n\t\t\tsetState(942);\n\t\t\tmatch(T__3);\n\t\t\tsetState(943);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rri_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic S_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rri_instruction; }\n\t}\n\n\tpublic final S_rri_instructionContext s_rri_instruction() throws RecognitionException {\n\t\tS_rri_instructionContext _localctx = new S_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 134, RULE_s_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(945);\n\t\t\trri_op_code();\n\t\t\tsetState(946);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(947);\n\t\t\tmatch(T__3);\n\t\t\tsetState(948);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(949);\n\t\t\tmatch(T__3);\n\t\t\tsetState(950);\n\t\t\tsrc_register();\n\t\t\tsetState(951);\n\t\t\tmatch(T__3);\n\t\t\tsetState(952);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rric_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic S_rric_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rric_instruction; }\n\t}\n\n\tpublic final S_rric_instructionContext s_rric_instruction() throws RecognitionException {\n\t\tS_rric_instructionContext _localctx = new S_rric_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 136, RULE_s_rric_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(954);\n\t\t\trri_op_code();\n\t\t\tsetState(955);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(956);\n\t\t\tmatch(T__3);\n\t\t\tsetState(957);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(958);\n\t\t\tmatch(T__3);\n\t\t\tsetState(959);\n\t\t\tsrc_register();\n\t\t\tsetState(960);\n\t\t\tmatch(T__3);\n\t\t\tsetState(961);\n\t\t\tnumber();\n\t\t\tsetState(962);\n\t\t\tmatch(T__3);\n\t\t\tsetState(963);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrici_instruction; }\n\t}\n\n\tpublic final S_rrici_instructionContext s_rrici_instruction() throws RecognitionException {\n\t\tS_rrici_instructionContext _localctx = new S_rrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 138, RULE_s_rrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(965);\n\t\t\trri_op_code();\n\t\t\tsetState(966);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(967);\n\t\t\tmatch(T__3);\n\t\t\tsetState(968);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(969);\n\t\t\tmatch(T__3);\n\t\t\tsetState(970);\n\t\t\tsrc_register();\n\t\t\tsetState(971);\n\t\t\tmatch(T__3);\n\t\t\tsetState(972);\n\t\t\tnumber();\n\t\t\tsetState(973);\n\t\t\tmatch(T__3);\n\t\t\tsetState(974);\n\t\t\tcondition();\n\t\t\tsetState(975);\n\t\t\tmatch(T__3);\n\t\t\tsetState(976);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrr_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic S_rrr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrr_instruction; }\n\t}\n\n\tpublic final S_rrr_instructionContext s_rrr_instruction() throws RecognitionException {\n\t\tS_rrr_instructionContext _localctx = new S_rrr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 140, RULE_s_rrr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(978);\n\t\t\trri_op_code();\n\t\t\tsetState(979);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(980);\n\t\t\tmatch(T__3);\n\t\t\tsetState(981);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(982);\n\t\t\tmatch(T__3);\n\t\t\tsetState(983);\n\t\t\tsrc_register();\n\t\t\tsetState(984);\n\t\t\tmatch(T__3);\n\t\t\tsetState(985);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic S_rrrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrrc_instruction; }\n\t}\n\n\tpublic final S_rrrc_instructionContext s_rrrc_instruction() throws RecognitionException {\n\t\tS_rrrc_instructionContext _localctx = new S_rrrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 142, RULE_s_rrrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(987);\n\t\t\trri_op_code();\n\t\t\tsetState(988);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(989);\n\t\t\tmatch(T__3);\n\t\t\tsetState(990);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(991);\n\t\t\tmatch(T__3);\n\t\t\tsetState(992);\n\t\t\tsrc_register();\n\t\t\tsetState(993);\n\t\t\tmatch(T__3);\n\t\t\tsetState(994);\n\t\t\tsrc_register();\n\t\t\tsetState(995);\n\t\t\tmatch(T__3);\n\t\t\tsetState(996);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rrrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrrci_instruction; }\n\t}\n\n\tpublic final S_rrrci_instructionContext s_rrrci_instruction() throws RecognitionException {\n\t\tS_rrrci_instructionContext _localctx = new S_rrrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 144, RULE_s_rrrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(998);\n\t\t\trri_op_code();\n\t\t\tsetState(999);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1000);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1001);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1002);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1003);\n\t\t\tsrc_register();\n\t\t\tsetState(1004);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1005);\n\t\t\tsrc_register();\n\t\t\tsetState(1006);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1007);\n\t\t\tcondition();\n\t\t\tsetState(1008);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1009);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rri_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic U_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rri_instruction; }\n\t}\n\n\tpublic final U_rri_instructionContext u_rri_instruction() throws RecognitionException {\n\t\tU_rri_instructionContext _localctx = new U_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 146, RULE_u_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1011);\n\t\t\trri_op_code();\n\t\t\tsetState(1012);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1013);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1014);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1015);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1016);\n\t\t\tsrc_register();\n\t\t\tsetState(1017);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1018);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rric_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic U_rric_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rric_instruction; }\n\t}\n\n\tpublic final U_rric_instructionContext u_rric_instruction() throws RecognitionException {\n\t\tU_rric_instructionContext _localctx = new U_rric_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 148, RULE_u_rric_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1020);\n\t\t\trri_op_code();\n\t\t\tsetState(1021);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1022);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1023);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1024);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1025);\n\t\t\tsrc_register();\n\t\t\tsetState(1026);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1027);\n\t\t\tnumber();\n\t\t\tsetState(1028);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1029);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrici_instruction; }\n\t}\n\n\tpublic final U_rrici_instructionContext u_rrici_instruction() throws RecognitionException {\n\t\tU_rrici_instructionContext _localctx = new U_rrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 150, RULE_u_rrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1031);\n\t\t\trri_op_code();\n\t\t\tsetState(1032);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1033);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1034);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1035);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1036);\n\t\t\tsrc_register();\n\t\t\tsetState(1037);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1038);\n\t\t\tnumber();\n\t\t\tsetState(1039);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1040);\n\t\t\tcondition();\n\t\t\tsetState(1041);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1042);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrr_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic U_rrr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrr_instruction; }\n\t}\n\n\tpublic final U_rrr_instructionContext u_rrr_instruction() throws RecognitionException {\n\t\tU_rrr_instructionContext _localctx = new U_rrr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 152, RULE_u_rrr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1044);\n\t\t\trri_op_code();\n\t\t\tsetState(1045);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1046);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1047);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1048);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1049);\n\t\t\tsrc_register();\n\t\t\tsetState(1050);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1051);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic U_rrrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrrc_instruction; }\n\t}\n\n\tpublic final U_rrrc_instructionContext u_rrrc_instruction() throws RecognitionException {\n\t\tU_rrrc_instructionContext _localctx = new U_rrrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 154, RULE_u_rrrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1053);\n\t\t\trri_op_code();\n\t\t\tsetState(1054);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1055);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1056);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1057);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1058);\n\t\t\tsrc_register();\n\t\t\tsetState(1059);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1060);\n\t\t\tsrc_register();\n\t\t\tsetState(1061);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1062);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rrrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrrci_instruction; }\n\t}\n\n\tpublic final U_rrrci_instructionContext u_rrrci_instruction() throws RecognitionException {\n\t\tU_rrrci_instructionContext _localctx = new U_rrrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 156, RULE_u_rrrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1064);\n\t\t\trri_op_code();\n\t\t\tsetState(1065);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1066);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1067);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1068);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1069);\n\t\t\tsrc_register();\n\t\t\tsetState(1070);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1071);\n\t\t\tsrc_register();\n\t\t\tsetState(1072);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1073);\n\t\t\tcondition();\n\t\t\tsetState(1074);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1075);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rr_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rr_instruction; }\n\t}\n\n\tpublic final Rr_instructionContext rr_instruction() throws RecognitionException {\n\t\tRr_instructionContext _localctx = new Rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 158, RULE_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1077);\n\t\t\trr_op_code();\n\t\t\tsetState(1078);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1079);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1080);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1081);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Rrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrc_instruction; }\n\t}\n\n\tpublic final Rrc_instructionContext rrc_instruction() throws RecognitionException {\n\t\tRrc_instructionContext _localctx = new Rrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 160, RULE_rrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1083);\n\t\t\trr_op_code();\n\t\t\tsetState(1084);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1085);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1086);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1087);\n\t\t\tsrc_register();\n\t\t\tsetState(1088);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1089);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrci_instruction; }\n\t}\n\n\tpublic final Rrci_instructionContext rrci_instruction() throws RecognitionException {\n\t\tRrci_instructionContext _localctx = new Rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 162, RULE_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1091);\n\t\t\trr_op_code();\n\t\t\tsetState(1092);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1093);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1094);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1095);\n\t\t\tsrc_register();\n\t\t\tsetState(1096);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1097);\n\t\t\tcondition();\n\t\t\tsetState(1098);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1099);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zr_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Zr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zr_instruction; }\n\t}\n\n\tpublic final Zr_instructionContext zr_instruction() throws RecognitionException {\n\t\tZr_instructionContext _localctx = new Zr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 164, RULE_zr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1101);\n\t\t\trr_op_code();\n\t\t\tsetState(1102);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1103);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1104);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1105);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Zrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrc_instruction; }\n\t}\n\n\tpublic final Zrc_instructionContext zrc_instruction() throws RecognitionException {\n\t\tZrc_instructionContext _localctx = new Zrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 166, RULE_zrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1107);\n\t\t\trr_op_code();\n\t\t\tsetState(1108);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1109);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1110);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1111);\n\t\t\tsrc_register();\n\t\t\tsetState(1112);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1113);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrci_instruction; }\n\t}\n\n\tpublic final Zrci_instructionContext zrci_instruction() throws RecognitionException {\n\t\tZrci_instructionContext _localctx = new Zrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 168, RULE_zrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1115);\n\t\t\trr_op_code();\n\t\t\tsetState(1116);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1117);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1118);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1119);\n\t\t\tsrc_register();\n\t\t\tsetState(1120);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1121);\n\t\t\tcondition();\n\t\t\tsetState(1122);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1123);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rr_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic S_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rr_instruction; }\n\t}\n\n\tpublic final S_rr_instructionContext s_rr_instruction() throws RecognitionException {\n\t\tS_rr_instructionContext _localctx = new S_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 170, RULE_s_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1125);\n\t\t\trr_op_code();\n\t\t\tsetState(1126);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1127);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1128);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1129);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1130);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic S_rrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrc_instruction; }\n\t}\n\n\tpublic final S_rrc_instructionContext s_rrc_instruction() throws RecognitionException {\n\t\tS_rrc_instructionContext _localctx = new S_rrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 172, RULE_s_rrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1132);\n\t\t\trr_op_code();\n\t\t\tsetState(1133);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1134);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1135);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1136);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1137);\n\t\t\tsrc_register();\n\t\t\tsetState(1138);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1139);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrci_instruction; }\n\t}\n\n\tpublic final S_rrci_instructionContext s_rrci_instruction() throws RecognitionException {\n\t\tS_rrci_instructionContext _localctx = new S_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 174, RULE_s_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1141);\n\t\t\trr_op_code();\n\t\t\tsetState(1142);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1143);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1144);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1145);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1146);\n\t\t\tsrc_register();\n\t\t\tsetState(1147);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1148);\n\t\t\tcondition();\n\t\t\tsetState(1149);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1150);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rr_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic U_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rr_instruction; }\n\t}\n\n\tpublic final U_rr_instructionContext u_rr_instruction() throws RecognitionException {\n\t\tU_rr_instructionContext _localctx = new U_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 176, RULE_u_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1152);\n\t\t\trr_op_code();\n\t\t\tsetState(1153);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1154);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1155);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1156);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1157);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrc_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic U_rrc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrc_instruction; }\n\t}\n\n\tpublic final U_rrc_instructionContext u_rrc_instruction() throws RecognitionException {\n\t\tU_rrc_instructionContext _localctx = new U_rrc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 178, RULE_u_rrc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1159);\n\t\t\trr_op_code();\n\t\t\tsetState(1160);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1161);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1162);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1163);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1164);\n\t\t\tsrc_register();\n\t\t\tsetState(1165);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1166);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic Rr_op_codeContext rr_op_code() {\n\t\t\treturn getRuleContext(Rr_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrci_instruction; }\n\t}\n\n\tpublic final U_rrci_instructionContext u_rrci_instruction() throws RecognitionException {\n\t\tU_rrci_instructionContext _localctx = new U_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 180, RULE_u_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1168);\n\t\t\trr_op_code();\n\t\t\tsetState(1169);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1170);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1171);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1172);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1173);\n\t\t\tsrc_register();\n\t\t\tsetState(1174);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1175);\n\t\t\tcondition();\n\t\t\tsetState(1176);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1177);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Drdici_instructionContext extends ParserRuleContext {\n\t\tpublic Drdici_op_codeContext drdici_op_code() {\n\t\t\treturn getRuleContext(Drdici_op_codeContext.class,0);\n\t\t}\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Drdici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_drdici_instruction; }\n\t}\n\n\tpublic final Drdici_instructionContext drdici_instruction() throws RecognitionException {\n\t\tDrdici_instructionContext _localctx = new Drdici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 182, RULE_drdici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1179);\n\t\t\tdrdici_op_code();\n\t\t\tsetState(1180);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1181);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1182);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1183);\n\t\t\tsrc_register();\n\t\t\tsetState(1184);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1185);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1186);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1187);\n\t\t\tnumber();\n\t\t\tsetState(1188);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1189);\n\t\t\tcondition();\n\t\t\tsetState(1190);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1191);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrri_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Rrri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrri_instruction; }\n\t}\n\n\tpublic final Rrri_instructionContext rrri_instruction() throws RecognitionException {\n\t\tRrri_instructionContext _localctx = new Rrri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 184, RULE_rrri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1193);\n\t\t\trrri_op_code();\n\t\t\tsetState(1194);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1195);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1196);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1197);\n\t\t\tsrc_register();\n\t\t\tsetState(1198);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1199);\n\t\t\tsrc_register();\n\t\t\tsetState(1200);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1201);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rrrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrrici_instruction; }\n\t}\n\n\tpublic final Rrrici_instructionContext rrrici_instruction() throws RecognitionException {\n\t\tRrrici_instructionContext _localctx = new Rrrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 186, RULE_rrrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1203);\n\t\t\trrri_op_code();\n\t\t\tsetState(1204);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1205);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1206);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1207);\n\t\t\tsrc_register();\n\t\t\tsetState(1208);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1209);\n\t\t\tsrc_register();\n\t\t\tsetState(1210);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1211);\n\t\t\tnumber();\n\t\t\tsetState(1212);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1213);\n\t\t\tcondition();\n\t\t\tsetState(1214);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1215);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrri_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Zrri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrri_instruction; }\n\t}\n\n\tpublic final Zrri_instructionContext zrri_instruction() throws RecognitionException {\n\t\tZrri_instructionContext _localctx = new Zrri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 188, RULE_zrri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1217);\n\t\t\trrri_op_code();\n\t\t\tsetState(1218);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1219);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1220);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1221);\n\t\t\tsrc_register();\n\t\t\tsetState(1222);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1223);\n\t\t\tsrc_register();\n\t\t\tsetState(1224);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1225);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zrrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zrrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zrrici_instruction; }\n\t}\n\n\tpublic final Zrrici_instructionContext zrrici_instruction() throws RecognitionException {\n\t\tZrrici_instructionContext _localctx = new Zrrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 190, RULE_zrrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1227);\n\t\t\trrri_op_code();\n\t\t\tsetState(1228);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1229);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1230);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1231);\n\t\t\tsrc_register();\n\t\t\tsetState(1232);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1233);\n\t\t\tsrc_register();\n\t\t\tsetState(1234);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1235);\n\t\t\tnumber();\n\t\t\tsetState(1236);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1237);\n\t\t\tcondition();\n\t\t\tsetState(1238);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1239);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrri_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic S_rrri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrri_instruction; }\n\t}\n\n\tpublic final S_rrri_instructionContext s_rrri_instruction() throws RecognitionException {\n\t\tS_rrri_instructionContext _localctx = new S_rrri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 192, RULE_s_rrri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1241);\n\t\t\trrri_op_code();\n\t\t\tsetState(1242);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1243);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1244);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1245);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1246);\n\t\t\tsrc_register();\n\t\t\tsetState(1247);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1248);\n\t\t\tsrc_register();\n\t\t\tsetState(1249);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1250);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rrrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rrrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rrrici_instruction; }\n\t}\n\n\tpublic final S_rrrici_instructionContext s_rrrici_instruction() throws RecognitionException {\n\t\tS_rrrici_instructionContext _localctx = new S_rrrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 194, RULE_s_rrrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1252);\n\t\t\trrri_op_code();\n\t\t\tsetState(1253);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1254);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1255);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1256);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1257);\n\t\t\tsrc_register();\n\t\t\tsetState(1258);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1259);\n\t\t\tsrc_register();\n\t\t\tsetState(1260);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1261);\n\t\t\tnumber();\n\t\t\tsetState(1262);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1263);\n\t\t\tcondition();\n\t\t\tsetState(1264);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1265);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrri_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic U_rrri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrri_instruction; }\n\t}\n\n\tpublic final U_rrri_instructionContext u_rrri_instruction() throws RecognitionException {\n\t\tU_rrri_instructionContext _localctx = new U_rrri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 196, RULE_u_rrri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1267);\n\t\t\trrri_op_code();\n\t\t\tsetState(1268);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1269);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1270);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1271);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1272);\n\t\t\tsrc_register();\n\t\t\tsetState(1273);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1274);\n\t\t\tsrc_register();\n\t\t\tsetState(1275);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1276);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rrrici_instructionContext extends ParserRuleContext {\n\t\tpublic Rrri_op_codeContext rrri_op_code() {\n\t\t\treturn getRuleContext(Rrri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rrrici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rrrici_instruction; }\n\t}\n\n\tpublic final U_rrrici_instructionContext u_rrrici_instruction() throws RecognitionException {\n\t\tU_rrrici_instructionContext _localctx = new U_rrrici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 198, RULE_u_rrrici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1278);\n\t\t\trrri_op_code();\n\t\t\tsetState(1279);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1280);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1281);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1282);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1283);\n\t\t\tsrc_register();\n\t\t\tsetState(1284);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1285);\n\t\t\tsrc_register();\n\t\t\tsetState(1286);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1287);\n\t\t\tnumber();\n\t\t\tsetState(1288);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1289);\n\t\t\tcondition();\n\t\t\tsetState(1290);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1291);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rir_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Rir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rir_instruction; }\n\t}\n\n\tpublic final Rir_instructionContext rir_instruction() throws RecognitionException {\n\t\tRir_instructionContext _localctx = new Rir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 200, RULE_rir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1293);\n\t\t\trri_op_code();\n\t\t\tsetState(1294);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1295);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1296);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1297);\n\t\t\tnumber();\n\t\t\tsetState(1298);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1299);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rirc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Rirc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rirc_instruction; }\n\t}\n\n\tpublic final Rirc_instructionContext rirc_instruction() throws RecognitionException {\n\t\tRirc_instructionContext _localctx = new Rirc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 202, RULE_rirc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1301);\n\t\t\trri_op_code();\n\t\t\tsetState(1302);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1303);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1304);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1305);\n\t\t\tnumber();\n\t\t\tsetState(1306);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1307);\n\t\t\tsrc_register();\n\t\t\tsetState(1308);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1309);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rirci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rirci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rirci_instruction; }\n\t}\n\n\tpublic final Rirci_instructionContext rirci_instruction() throws RecognitionException {\n\t\tRirci_instructionContext _localctx = new Rirci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 204, RULE_rirci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1311);\n\t\t\trri_op_code();\n\t\t\tsetState(1312);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1313);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1314);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1315);\n\t\t\tnumber();\n\t\t\tsetState(1316);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1317);\n\t\t\tsrc_register();\n\t\t\tsetState(1318);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1319);\n\t\t\tcondition();\n\t\t\tsetState(1320);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1321);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zir_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Zir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zir_instruction; }\n\t}\n\n\tpublic final Zir_instructionContext zir_instruction() throws RecognitionException {\n\t\tZir_instructionContext _localctx = new Zir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 206, RULE_zir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1323);\n\t\t\trri_op_code();\n\t\t\tsetState(1324);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1325);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1326);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1327);\n\t\t\tnumber();\n\t\t\tsetState(1328);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1329);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zirc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Zirc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zirc_instruction; }\n\t}\n\n\tpublic final Zirc_instructionContext zirc_instruction() throws RecognitionException {\n\t\tZirc_instructionContext _localctx = new Zirc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 208, RULE_zirc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1331);\n\t\t\trri_op_code();\n\t\t\tsetState(1332);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1333);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1334);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1335);\n\t\t\tnumber();\n\t\t\tsetState(1336);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1337);\n\t\t\tsrc_register();\n\t\t\tsetState(1338);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1339);\n\t\t\tcondition();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zirci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zirci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zirci_instruction; }\n\t}\n\n\tpublic final Zirci_instructionContext zirci_instruction() throws RecognitionException {\n\t\tZirci_instructionContext _localctx = new Zirci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 210, RULE_zirci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1341);\n\t\t\trri_op_code();\n\t\t\tsetState(1342);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1343);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1344);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1345);\n\t\t\tnumber();\n\t\t\tsetState(1346);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1347);\n\t\t\tsrc_register();\n\t\t\tsetState(1348);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1349);\n\t\t\tcondition();\n\t\t\tsetState(1350);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1351);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rirc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic S_rirc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rirc_instruction; }\n\t}\n\n\tpublic final S_rirc_instructionContext s_rirc_instruction() throws RecognitionException {\n\t\tS_rirc_instructionContext _localctx = new S_rirc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 212, RULE_s_rirc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1353);\n\t\t\trri_op_code();\n\t\t\tsetState(1354);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1355);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1356);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1357);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1358);\n\t\t\tnumber();\n\t\t\tsetState(1359);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1360);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rirci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rirci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rirci_instruction; }\n\t}\n\n\tpublic final S_rirci_instructionContext s_rirci_instruction() throws RecognitionException {\n\t\tS_rirci_instructionContext _localctx = new S_rirci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 214, RULE_s_rirci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1362);\n\t\t\trri_op_code();\n\t\t\tsetState(1363);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1364);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1365);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1366);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1367);\n\t\t\tnumber();\n\t\t\tsetState(1368);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1369);\n\t\t\tsrc_register();\n\t\t\tsetState(1370);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1371);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rirc_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic U_rirc_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rirc_instruction; }\n\t}\n\n\tpublic final U_rirc_instructionContext u_rirc_instruction() throws RecognitionException {\n\t\tU_rirc_instructionContext _localctx = new U_rirc_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 216, RULE_u_rirc_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1373);\n\t\t\trri_op_code();\n\t\t\tsetState(1374);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1375);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1376);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1377);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1378);\n\t\t\tnumber();\n\t\t\tsetState(1379);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1380);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rirci_instructionContext extends ParserRuleContext {\n\t\tpublic Rri_op_codeContext rri_op_code() {\n\t\t\treturn getRuleContext(Rri_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rirci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rirci_instruction; }\n\t}\n\n\tpublic final U_rirci_instructionContext u_rirci_instruction() throws RecognitionException {\n\t\tU_rirci_instructionContext _localctx = new U_rirci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 218, RULE_u_rirci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1382);\n\t\t\trri_op_code();\n\t\t\tsetState(1383);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1384);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1385);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1386);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1387);\n\t\t\tnumber();\n\t\t\tsetState(1388);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1389);\n\t\t\tsrc_register();\n\t\t\tsetState(1390);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1391);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class R_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic R_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_r_instruction; }\n\t}\n\n\tpublic final R_instructionContext r_instruction() throws RecognitionException {\n\t\tR_instructionContext _localctx = new R_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 220, RULE_r_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1393);\n\t\t\tr_op_code();\n\t\t\tsetState(1394);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1395);\n\t\t\tmatch(GPRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rci_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic List<ConditionContext> condition() {\n\t\t\treturn getRuleContexts(ConditionContext.class);\n\t\t}\n\t\tpublic ConditionContext condition(int i) {\n\t\t\treturn getRuleContext(ConditionContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Rci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rci_instruction; }\n\t}\n\n\tpublic final Rci_instructionContext rci_instruction() throws RecognitionException {\n\t\tRci_instructionContext _localctx = new Rci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 222, RULE_rci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1397);\n\t\t\tr_op_code();\n\t\t\tsetState(1398);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1399);\n\t\t\tcondition();\n\t\t\tsetState(1400);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1401);\n\t\t\tcondition();\n\t\t\tsetState(1402);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1403);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Z_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic Z_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_z_instruction; }\n\t}\n\n\tpublic final Z_instructionContext z_instruction() throws RecognitionException {\n\t\tZ_instructionContext _localctx = new Z_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 224, RULE_z_instruction);\n\t\ttry {\n\t\t\tsetState(1412);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,12,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1405);\n\t\t\t\tr_op_code();\n\t\t\t\tsetState(1406);\n\t\t\t\tmatch(T__3);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1408);\n\t\t\t\tr_op_code();\n\t\t\t\tsetState(1409);\n\t\t\t\tmatch(T__3);\n\t\t\t\tsetState(1410);\n\t\t\t\tmatch(ZERO_REGISTER);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Zci_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode ZERO_REGISTER() { return getToken(assemblyParser.ZERO_REGISTER, 0); }\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Zci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_zci_instruction; }\n\t}\n\n\tpublic final Zci_instructionContext zci_instruction() throws RecognitionException {\n\t\tZci_instructionContext _localctx = new Zci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 226, RULE_zci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1414);\n\t\t\tr_op_code();\n\t\t\tsetState(1415);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1416);\n\t\t\tmatch(ZERO_REGISTER);\n\t\t\tsetState(1417);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1418);\n\t\t\tcondition();\n\t\t\tsetState(1419);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1420);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_r_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic S_r_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_r_instruction; }\n\t}\n\n\tpublic final S_r_instructionContext s_r_instruction() throws RecognitionException {\n\t\tS_r_instructionContext _localctx = new S_r_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 228, RULE_s_r_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1422);\n\t\t\tr_op_code();\n\t\t\tsetState(1423);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1424);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1425);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_rci_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_rci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_rci_instruction; }\n\t}\n\n\tpublic final S_rci_instructionContext s_rci_instruction() throws RecognitionException {\n\t\tS_rci_instructionContext _localctx = new S_rci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 230, RULE_s_rci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1427);\n\t\t\tr_op_code();\n\t\t\tsetState(1428);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1429);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1430);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1431);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1432);\n\t\t\tcondition();\n\t\t\tsetState(1433);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1434);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_r_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic U_r_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_r_instruction; }\n\t}\n\n\tpublic final U_r_instructionContext u_r_instruction() throws RecognitionException {\n\t\tU_r_instructionContext _localctx = new U_r_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 232, RULE_u_r_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1436);\n\t\t\tr_op_code();\n\t\t\tsetState(1437);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1438);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1439);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_rci_instructionContext extends ParserRuleContext {\n\t\tpublic R_op_codeContext r_op_code() {\n\t\t\treturn getRuleContext(R_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_rci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_rci_instruction; }\n\t}\n\n\tpublic final U_rci_instructionContext u_rci_instruction() throws RecognitionException {\n\t\tU_rci_instructionContext _localctx = new U_rci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 234, RULE_u_rci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1441);\n\t\t\tr_op_code();\n\t\t\tsetState(1442);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1443);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1444);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1445);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1446);\n\t\t\tcondition();\n\t\t\tsetState(1447);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1448);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ci_instructionContext extends ParserRuleContext {\n\t\tpublic Ci_op_codeContext ci_op_code() {\n\t\t\treturn getRuleContext(Ci_op_codeContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Ci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ci_instruction; }\n\t}\n\n\tpublic final Ci_instructionContext ci_instruction() throws RecognitionException {\n\t\tCi_instructionContext _localctx = new Ci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 236, RULE_ci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1450);\n\t\t\tci_op_code();\n\t\t\tsetState(1451);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1452);\n\t\t\tcondition();\n\t\t\tsetState(1453);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1454);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class I_instructionContext extends ParserRuleContext {\n\t\tpublic I_op_codeContext i_op_code() {\n\t\t\treturn getRuleContext(I_op_codeContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic I_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_i_instruction; }\n\t}\n\n\tpublic final I_instructionContext i_instruction() throws RecognitionException {\n\t\tI_instructionContext _localctx = new I_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 238, RULE_i_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1456);\n\t\t\ti_op_code();\n\t\t\tsetState(1457);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1458);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ddci_instructionContext extends ParserRuleContext {\n\t\tpublic Ddci_op_codeContext ddci_op_code() {\n\t\t\treturn getRuleContext(Ddci_op_codeContext.class,0);\n\t\t}\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Ddci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ddci_instruction; }\n\t}\n\n\tpublic final Ddci_instructionContext ddci_instruction() throws RecognitionException {\n\t\tDdci_instructionContext _localctx = new Ddci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 240, RULE_ddci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1460);\n\t\t\tddci_op_code();\n\t\t\tsetState(1461);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1462);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1463);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1464);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1465);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1466);\n\t\t\tcondition();\n\t\t\tsetState(1467);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1468);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Erri_instructionContext extends ParserRuleContext {\n\t\tpublic Load_op_codeContext load_op_code() {\n\t\t\treturn getRuleContext(Load_op_codeContext.class,0);\n\t\t}\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_erri_instruction; }\n\t}\n\n\tpublic final Erri_instructionContext erri_instruction() throws RecognitionException {\n\t\tErri_instructionContext _localctx = new Erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 242, RULE_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1470);\n\t\t\tload_op_code();\n\t\t\tsetState(1471);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1472);\n\t\t\tendian();\n\t\t\tsetState(1473);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1474);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1475);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1476);\n\t\t\tsrc_register();\n\t\t\tsetState(1477);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1478);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Edri_instructionContext extends ParserRuleContext {\n\t\tpublic Load_op_codeContext load_op_code() {\n\t\t\treturn getRuleContext(Load_op_codeContext.class,0);\n\t\t}\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Edri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_edri_instruction; }\n\t}\n\n\tpublic final Edri_instructionContext edri_instruction() throws RecognitionException {\n\t\tEdri_instructionContext _localctx = new Edri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 244, RULE_edri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1480);\n\t\t\tload_op_code();\n\t\t\tsetState(1481);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1482);\n\t\t\tendian();\n\t\t\tsetState(1483);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1484);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1485);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1486);\n\t\t\tsrc_register();\n\t\t\tsetState(1487);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1488);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class S_erri_instructionContext extends ParserRuleContext {\n\t\tpublic Load_op_codeContext load_op_code() {\n\t\t\treturn getRuleContext(Load_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic S_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_s_erri_instruction; }\n\t}\n\n\tpublic final S_erri_instructionContext s_erri_instruction() throws RecognitionException {\n\t\tS_erri_instructionContext _localctx = new S_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 246, RULE_s_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1490);\n\t\t\tload_op_code();\n\t\t\tsetState(1491);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1492);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1493);\n\t\t\tendian();\n\t\t\tsetState(1494);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1495);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1496);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1497);\n\t\t\tsrc_register();\n\t\t\tsetState(1498);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1499);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class U_erri_instructionContext extends ParserRuleContext {\n\t\tpublic Load_op_codeContext load_op_code() {\n\t\t\treturn getRuleContext(Load_op_codeContext.class,0);\n\t\t}\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic U_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_u_erri_instruction; }\n\t}\n\n\tpublic final U_erri_instructionContext u_erri_instruction() throws RecognitionException {\n\t\tU_erri_instructionContext _localctx = new U_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 248, RULE_u_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1501);\n\t\t\tload_op_code();\n\t\t\tsetState(1502);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1503);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1504);\n\t\t\tendian();\n\t\t\tsetState(1505);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1506);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1507);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1508);\n\t\t\tsrc_register();\n\t\t\tsetState(1509);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1510);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Erii_instructionContext extends ParserRuleContext {\n\t\tpublic Store_op_codeContext store_op_code() {\n\t\t\treturn getRuleContext(Store_op_codeContext.class,0);\n\t\t}\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Erii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_erii_instruction; }\n\t}\n\n\tpublic final Erii_instructionContext erii_instruction() throws RecognitionException {\n\t\tErii_instructionContext _localctx = new Erii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 250, RULE_erii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1512);\n\t\t\tstore_op_code();\n\t\t\tsetState(1513);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1514);\n\t\t\tendian();\n\t\t\tsetState(1515);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1516);\n\t\t\tsrc_register();\n\t\t\tsetState(1517);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1518);\n\t\t\tnumber();\n\t\t\tsetState(1519);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1520);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Erir_instructionContext extends ParserRuleContext {\n\t\tpublic Store_op_codeContext store_op_code() {\n\t\t\treturn getRuleContext(Store_op_codeContext.class,0);\n\t\t}\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Erir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_erir_instruction; }\n\t}\n\n\tpublic final Erir_instructionContext erir_instruction() throws RecognitionException {\n\t\tErir_instructionContext _localctx = new Erir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 252, RULE_erir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1522);\n\t\t\tstore_op_code();\n\t\t\tsetState(1523);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1524);\n\t\t\tendian();\n\t\t\tsetState(1525);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1526);\n\t\t\tsrc_register();\n\t\t\tsetState(1527);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1528);\n\t\t\tprogram_counter();\n\t\t\tsetState(1529);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1530);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Erid_instructionContext extends ParserRuleContext {\n\t\tpublic Store_op_codeContext store_op_code() {\n\t\t\treturn getRuleContext(Store_op_codeContext.class,0);\n\t\t}\n\t\tpublic EndianContext endian() {\n\t\t\treturn getRuleContext(EndianContext.class,0);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Erid_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_erid_instruction; }\n\t}\n\n\tpublic final Erid_instructionContext erid_instruction() throws RecognitionException {\n\t\tErid_instructionContext _localctx = new Erid_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 254, RULE_erid_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1532);\n\t\t\tstore_op_code();\n\t\t\tsetState(1533);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1534);\n\t\t\tendian();\n\t\t\tsetState(1535);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1536);\n\t\t\tsrc_register();\n\t\t\tsetState(1537);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1538);\n\t\t\tprogram_counter();\n\t\t\tsetState(1539);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1540);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Dma_rri_instructionContext extends ParserRuleContext {\n\t\tpublic Dma_op_codeContext dma_op_code() {\n\t\t\treturn getRuleContext(Dma_op_codeContext.class,0);\n\t\t}\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Dma_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_dma_rri_instruction; }\n\t}\n\n\tpublic final Dma_rri_instructionContext dma_rri_instruction() throws RecognitionException {\n\t\tDma_rri_instructionContext _localctx = new Dma_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 256, RULE_dma_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1542);\n\t\t\tdma_op_code();\n\t\t\tsetState(1543);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1544);\n\t\t\tsrc_register();\n\t\t\tsetState(1545);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1546);\n\t\t\tsrc_register();\n\t\t\tsetState(1547);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1548);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Synthetic_sugar_instructionContext extends ParserRuleContext {\n\t\tpublic Rrif_instructionContext rrif_instruction() {\n\t\t\treturn getRuleContext(Rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_instructionContext move_instruction() {\n\t\t\treturn getRuleContext(Move_instructionContext.class,0);\n\t\t}\n\t\tpublic Neg_instructionContext neg_instruction() {\n\t\t\treturn getRuleContext(Neg_instructionContext.class,0);\n\t\t}\n\t\tpublic Not_instructionContext not_instruction() {\n\t\t\treturn getRuleContext(Not_instructionContext.class,0);\n\t\t}\n\t\tpublic Jump_instructionContext jump_instruction() {\n\t\t\treturn getRuleContext(Jump_instructionContext.class,0);\n\t\t}\n\t\tpublic Shortcut_instructionContext shortcut_instruction() {\n\t\t\treturn getRuleContext(Shortcut_instructionContext.class,0);\n\t\t}\n\t\tpublic Synthetic_sugar_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_synthetic_sugar_instruction; }\n\t}\n\n\tpublic final Synthetic_sugar_instructionContext synthetic_sugar_instruction() throws RecognitionException {\n\t\tSynthetic_sugar_instructionContext _localctx = new Synthetic_sugar_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 258, RULE_synthetic_sugar_instruction);\n\t\ttry {\n\t\t\tsetState(1556);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch (_input.LA(1)) {\n\t\t\tcase ANDN:\n\t\t\tcase NAND:\n\t\t\tcase NOR:\n\t\t\tcase NXOR:\n\t\t\tcase ORN:\n\t\t\tcase HASH:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1550);\n\t\t\t\trrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase MOVE:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1551);\n\t\t\t\tmove_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase NEG:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1552);\n\t\t\t\tneg_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase NOT:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(1553);\n\t\t\t\tnot_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase JEQ:\n\t\t\tcase JNEQ:\n\t\t\tcase JZ:\n\t\t\tcase JNZ:\n\t\t\tcase JLTU:\n\t\t\tcase JGTU:\n\t\t\tcase JLEU:\n\t\t\tcase JGEU:\n\t\t\tcase JLTS:\n\t\t\tcase JGTS:\n\t\t\tcase JLES:\n\t\t\tcase JGES:\n\t\t\tcase JUMP:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(1554);\n\t\t\t\tjump_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase BOOT:\n\t\t\tcase RESUME:\n\t\t\tcase CALL:\n\t\t\tcase TIME_CFG:\n\t\t\tcase DIV_STEP:\n\t\t\tcase MUL_STEP:\n\t\t\tcase STOP:\n\t\t\tcase MOVD:\n\t\t\tcase SWAPD:\n\t\t\tcase LBS:\n\t\t\tcase LBU:\n\t\t\tcase LD:\n\t\t\tcase LHS:\n\t\t\tcase LHU:\n\t\t\tcase LW:\n\t\t\tcase SB:\n\t\t\tcase SD:\n\t\t\tcase SH:\n\t\t\tcase SW:\n\t\t\tcase BKP:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(1555);\n\t\t\t\tshortcut_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Rrif_instructionContext extends ParserRuleContext {\n\t\tpublic Andn_rrif_instructionContext andn_rrif_instruction() {\n\t\t\treturn getRuleContext(Andn_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Nand_rrif_instructionContext nand_rrif_instruction() {\n\t\t\treturn getRuleContext(Nand_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Nor_rrif_instructionContext nor_rrif_instruction() {\n\t\t\treturn getRuleContext(Nor_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Nxor_rrif_instructionContext nxor_rrif_instruction() {\n\t\t\treturn getRuleContext(Nxor_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Orn_rrif_instructionContext orn_rrif_instruction() {\n\t\t\treturn getRuleContext(Orn_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Hash_rrif_instructionContext hash_rrif_instruction() {\n\t\t\treturn getRuleContext(Hash_rrif_instructionContext.class,0);\n\t\t}\n\t\tpublic Rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_rrif_instruction; }\n\t}\n\n\tpublic final Rrif_instructionContext rrif_instruction() throws RecognitionException {\n\t\tRrif_instructionContext _localctx = new Rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 260, RULE_rrif_instruction);\n\t\ttry {\n\t\t\tsetState(1564);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch (_input.LA(1)) {\n\t\t\tcase ANDN:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1558);\n\t\t\t\tandn_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase NAND:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1559);\n\t\t\t\tnand_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase NOR:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1560);\n\t\t\t\tnor_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase NXOR:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(1561);\n\t\t\t\tnxor_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase ORN:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(1562);\n\t\t\t\torn_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase HASH:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(1563);\n\t\t\t\thash_rrif_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tthrow new NoViableAltException(this);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Andn_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode ANDN() { return getToken(assemblyParser.ANDN, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Andn_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_andn_rrif_instruction; }\n\t}\n\n\tpublic final Andn_rrif_instructionContext andn_rrif_instruction() throws RecognitionException {\n\t\tAndn_rrif_instructionContext _localctx = new Andn_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 262, RULE_andn_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1566);\n\t\t\tmatch(ANDN);\n\t\t\tsetState(1567);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1568);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1569);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1570);\n\t\t\tsrc_register();\n\t\t\tsetState(1571);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1572);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Nand_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NAND() { return getToken(assemblyParser.NAND, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Nand_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_nand_rrif_instruction; }\n\t}\n\n\tpublic final Nand_rrif_instructionContext nand_rrif_instruction() throws RecognitionException {\n\t\tNand_rrif_instructionContext _localctx = new Nand_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 264, RULE_nand_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1574);\n\t\t\tmatch(NAND);\n\t\t\tsetState(1575);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1576);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1577);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1578);\n\t\t\tsrc_register();\n\t\t\tsetState(1579);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1580);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Nor_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NOR() { return getToken(assemblyParser.NOR, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Nor_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_nor_rrif_instruction; }\n\t}\n\n\tpublic final Nor_rrif_instructionContext nor_rrif_instruction() throws RecognitionException {\n\t\tNor_rrif_instructionContext _localctx = new Nor_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 266, RULE_nor_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1582);\n\t\t\tmatch(NOR);\n\t\t\tsetState(1583);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1584);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1585);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1586);\n\t\t\tsrc_register();\n\t\t\tsetState(1587);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1588);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Nxor_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NXOR() { return getToken(assemblyParser.NXOR, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Nxor_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_nxor_rrif_instruction; }\n\t}\n\n\tpublic final Nxor_rrif_instructionContext nxor_rrif_instruction() throws RecognitionException {\n\t\tNxor_rrif_instructionContext _localctx = new Nxor_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 268, RULE_nxor_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1590);\n\t\t\tmatch(NXOR);\n\t\t\tsetState(1591);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1592);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1593);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1594);\n\t\t\tsrc_register();\n\t\t\tsetState(1595);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1596);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Orn_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode ORN() { return getToken(assemblyParser.ORN, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Orn_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_orn_rrif_instruction; }\n\t}\n\n\tpublic final Orn_rrif_instructionContext orn_rrif_instruction() throws RecognitionException {\n\t\tOrn_rrif_instructionContext _localctx = new Orn_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 270, RULE_orn_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1598);\n\t\t\tmatch(ORN);\n\t\t\tsetState(1599);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1600);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1601);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1602);\n\t\t\tsrc_register();\n\t\t\tsetState(1603);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1604);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Hash_rrif_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode HASH() { return getToken(assemblyParser.HASH, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Hash_rrif_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_hash_rrif_instruction; }\n\t}\n\n\tpublic final Hash_rrif_instructionContext hash_rrif_instruction() throws RecognitionException {\n\t\tHash_rrif_instructionContext _localctx = new Hash_rrif_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 272, RULE_hash_rrif_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1606);\n\t\t\tmatch(HASH);\n\t\t\tsetState(1607);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1608);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1609);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1610);\n\t\t\tsrc_register();\n\t\t\tsetState(1611);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1612);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_instructionContext extends ParserRuleContext {\n\t\tpublic Move_ri_instructionContext move_ri_instruction() {\n\t\t\treturn getRuleContext(Move_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_rici_instructionContext move_rici_instruction() {\n\t\t\treturn getRuleContext(Move_rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_rr_instructionContext move_rr_instruction() {\n\t\t\treturn getRuleContext(Move_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_rrci_instructionContext move_rrci_instruction() {\n\t\t\treturn getRuleContext(Move_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_s_ri_instructionContext move_s_ri_instruction() {\n\t\t\treturn getRuleContext(Move_s_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_s_rici_instructionContext move_s_rici_instruction() {\n\t\t\treturn getRuleContext(Move_s_rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_s_rr_instructionContext move_s_rr_instruction() {\n\t\t\treturn getRuleContext(Move_s_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_s_rrci_instructionContext move_s_rrci_instruction() {\n\t\t\treturn getRuleContext(Move_s_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_u_ri_instructionContext move_u_ri_instruction() {\n\t\t\treturn getRuleContext(Move_u_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_u_rici_instructionContext move_u_rici_instruction() {\n\t\t\treturn getRuleContext(Move_u_rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_u_rr_instructionContext move_u_rr_instruction() {\n\t\t\treturn getRuleContext(Move_u_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_u_rrci_instructionContext move_u_rrci_instruction() {\n\t\t\treturn getRuleContext(Move_u_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Move_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_instruction; }\n\t}\n\n\tpublic final Move_instructionContext move_instruction() throws RecognitionException {\n\t\tMove_instructionContext _localctx = new Move_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 274, RULE_move_instruction);\n\t\ttry {\n\t\t\tsetState(1626);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,15,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1614);\n\t\t\t\tmove_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1615);\n\t\t\t\tmove_rici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1616);\n\t\t\t\tmove_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(1617);\n\t\t\t\tmove_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(1618);\n\t\t\t\tmove_s_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(1619);\n\t\t\t\tmove_s_rici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tenterOuterAlt(_localctx, 7);\n\t\t\t\t{\n\t\t\t\tsetState(1620);\n\t\t\t\tmove_s_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tenterOuterAlt(_localctx, 8);\n\t\t\t\t{\n\t\t\t\tsetState(1621);\n\t\t\t\tmove_s_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tenterOuterAlt(_localctx, 9);\n\t\t\t\t{\n\t\t\t\tsetState(1622);\n\t\t\t\tmove_u_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tenterOuterAlt(_localctx, 10);\n\t\t\t\t{\n\t\t\t\tsetState(1623);\n\t\t\t\tmove_u_rici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tenterOuterAlt(_localctx, 11);\n\t\t\t\t{\n\t\t\t\tsetState(1624);\n\t\t\t\tmove_u_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tenterOuterAlt(_localctx, 12);\n\t\t\t\t{\n\t\t\t\tsetState(1625);\n\t\t\t\tmove_u_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_ri_instruction; }\n\t}\n\n\tpublic final Move_ri_instructionContext move_ri_instruction() throws RecognitionException {\n\t\tMove_ri_instructionContext _localctx = new Move_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 276, RULE_move_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1628);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1629);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1630);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1631);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1632);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_rici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_rici_instruction; }\n\t}\n\n\tpublic final Move_rici_instructionContext move_rici_instruction() throws RecognitionException {\n\t\tMove_rici_instructionContext _localctx = new Move_rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 278, RULE_move_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1634);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1635);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1636);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1637);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1638);\n\t\t\tnumber();\n\t\t\tsetState(1639);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1640);\n\t\t\tcondition();\n\t\t\tsetState(1641);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1642);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Move_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_rr_instruction; }\n\t}\n\n\tpublic final Move_rr_instructionContext move_rr_instruction() throws RecognitionException {\n\t\tMove_rr_instructionContext _localctx = new Move_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 280, RULE_move_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1644);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1645);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1646);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1647);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1648);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_rrci_instruction; }\n\t}\n\n\tpublic final Move_rrci_instructionContext move_rrci_instruction() throws RecognitionException {\n\t\tMove_rrci_instructionContext _localctx = new Move_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 282, RULE_move_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1650);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1651);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1652);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1653);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1654);\n\t\t\tsrc_register();\n\t\t\tsetState(1655);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1656);\n\t\t\tcondition();\n\t\t\tsetState(1657);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1658);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_s_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Move_s_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_s_ri_instruction; }\n\t}\n\n\tpublic final Move_s_ri_instructionContext move_s_ri_instruction() throws RecognitionException {\n\t\tMove_s_ri_instructionContext _localctx = new Move_s_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 284, RULE_move_s_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1660);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1661);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1662);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1663);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1664);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1665);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_s_rici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_s_rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_s_rici_instruction; }\n\t}\n\n\tpublic final Move_s_rici_instructionContext move_s_rici_instruction() throws RecognitionException {\n\t\tMove_s_rici_instructionContext _localctx = new Move_s_rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 286, RULE_move_s_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1667);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1668);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1669);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1670);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1671);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1672);\n\t\t\tnumber();\n\t\t\tsetState(1673);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1674);\n\t\t\tcondition();\n\t\t\tsetState(1675);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1676);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_s_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Move_s_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_s_rr_instruction; }\n\t}\n\n\tpublic final Move_s_rr_instructionContext move_s_rr_instruction() throws RecognitionException {\n\t\tMove_s_rr_instructionContext _localctx = new Move_s_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 288, RULE_move_s_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1678);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1679);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1680);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1681);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1682);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1683);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_s_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_s_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_s_rrci_instruction; }\n\t}\n\n\tpublic final Move_s_rrci_instructionContext move_s_rrci_instruction() throws RecognitionException {\n\t\tMove_s_rrci_instructionContext _localctx = new Move_s_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 290, RULE_move_s_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1685);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1686);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(1687);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1688);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1689);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1690);\n\t\t\tsrc_register();\n\t\t\tsetState(1691);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1692);\n\t\t\tcondition();\n\t\t\tsetState(1693);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1694);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_u_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Move_u_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_u_ri_instruction; }\n\t}\n\n\tpublic final Move_u_ri_instructionContext move_u_ri_instruction() throws RecognitionException {\n\t\tMove_u_ri_instructionContext _localctx = new Move_u_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 292, RULE_move_u_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1696);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1697);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1698);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1699);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1700);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1701);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_u_rici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_u_rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_u_rici_instruction; }\n\t}\n\n\tpublic final Move_u_rici_instructionContext move_u_rici_instruction() throws RecognitionException {\n\t\tMove_u_rici_instructionContext _localctx = new Move_u_rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 294, RULE_move_u_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1703);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1704);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1705);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1706);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1707);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1708);\n\t\t\tnumber();\n\t\t\tsetState(1709);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1710);\n\t\t\tcondition();\n\t\t\tsetState(1711);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1712);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_u_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Move_u_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_u_rr_instruction; }\n\t}\n\n\tpublic final Move_u_rr_instructionContext move_u_rr_instruction() throws RecognitionException {\n\t\tMove_u_rr_instructionContext _localctx = new Move_u_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 296, RULE_move_u_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1714);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1715);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1716);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1717);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1718);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1719);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Move_u_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVE() { return getToken(assemblyParser.MOVE, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Move_u_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_move_u_rrci_instruction; }\n\t}\n\n\tpublic final Move_u_rrci_instructionContext move_u_rrci_instruction() throws RecognitionException {\n\t\tMove_u_rrci_instructionContext _localctx = new Move_u_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 298, RULE_move_u_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1721);\n\t\t\tmatch(MOVE);\n\t\t\tsetState(1722);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(1723);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1724);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(1725);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1726);\n\t\t\tsrc_register();\n\t\t\tsetState(1727);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1728);\n\t\t\tcondition();\n\t\t\tsetState(1729);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1730);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Neg_instructionContext extends ParserRuleContext {\n\t\tpublic Neg_rr_instructionContext neg_rr_instruction() {\n\t\t\treturn getRuleContext(Neg_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Neg_rrci_instructionContext neg_rrci_instruction() {\n\t\t\treturn getRuleContext(Neg_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Neg_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_neg_instruction; }\n\t}\n\n\tpublic final Neg_instructionContext neg_instruction() throws RecognitionException {\n\t\tNeg_instructionContext _localctx = new Neg_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 300, RULE_neg_instruction);\n\t\ttry {\n\t\t\tsetState(1734);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,16,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1732);\n\t\t\t\tneg_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1733);\n\t\t\t\tneg_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Neg_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NEG() { return getToken(assemblyParser.NEG, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Neg_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_neg_rr_instruction; }\n\t}\n\n\tpublic final Neg_rr_instructionContext neg_rr_instruction() throws RecognitionException {\n\t\tNeg_rr_instructionContext _localctx = new Neg_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 302, RULE_neg_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1736);\n\t\t\tmatch(NEG);\n\t\t\tsetState(1737);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1738);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1739);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1740);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Neg_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NEG() { return getToken(assemblyParser.NEG, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Neg_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_neg_rrci_instruction; }\n\t}\n\n\tpublic final Neg_rrci_instructionContext neg_rrci_instruction() throws RecognitionException {\n\t\tNeg_rrci_instructionContext _localctx = new Neg_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 304, RULE_neg_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1742);\n\t\t\tmatch(NEG);\n\t\t\tsetState(1743);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1744);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1745);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1746);\n\t\t\tsrc_register();\n\t\t\tsetState(1747);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1748);\n\t\t\tcondition();\n\t\t\tsetState(1749);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1750);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Not_instructionContext extends ParserRuleContext {\n\t\tpublic Not_rr_instructionContext not_rr_instruction() {\n\t\t\treturn getRuleContext(Not_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Not_rrci_instructionContext not_rrci_instruction() {\n\t\t\treturn getRuleContext(Not_rrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Not_zrci_instructionContext not_zrci_instruction() {\n\t\t\treturn getRuleContext(Not_zrci_instructionContext.class,0);\n\t\t}\n\t\tpublic Not_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_not_instruction; }\n\t}\n\n\tpublic final Not_instructionContext not_instruction() throws RecognitionException {\n\t\tNot_instructionContext _localctx = new Not_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 306, RULE_not_instruction);\n\t\ttry {\n\t\t\tsetState(1755);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,17,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1752);\n\t\t\t\tnot_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1753);\n\t\t\t\tnot_rrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1754);\n\t\t\t\tnot_zrci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Not_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NOT() { return getToken(assemblyParser.NOT, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Not_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_not_rr_instruction; }\n\t}\n\n\tpublic final Not_rr_instructionContext not_rr_instruction() throws RecognitionException {\n\t\tNot_rr_instructionContext _localctx = new Not_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 308, RULE_not_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1757);\n\t\t\tmatch(NOT);\n\t\t\tsetState(1758);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1759);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1760);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1761);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Not_rrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NOT() { return getToken(assemblyParser.NOT, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Not_rrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_not_rrci_instruction; }\n\t}\n\n\tpublic final Not_rrci_instructionContext not_rrci_instruction() throws RecognitionException {\n\t\tNot_rrci_instructionContext _localctx = new Not_rrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 310, RULE_not_rrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1763);\n\t\t\tmatch(NOT);\n\t\t\tsetState(1764);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1765);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(1766);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1767);\n\t\t\tsrc_register();\n\t\t\tsetState(1768);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1769);\n\t\t\tcondition();\n\t\t\tsetState(1770);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1771);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Not_zrci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode NOT() { return getToken(assemblyParser.NOT, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic ConditionContext condition() {\n\t\t\treturn getRuleContext(ConditionContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Not_zrci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_not_zrci_instruction; }\n\t}\n\n\tpublic final Not_zrci_instructionContext not_zrci_instruction() throws RecognitionException {\n\t\tNot_zrci_instructionContext _localctx = new Not_zrci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 312, RULE_not_zrci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1773);\n\t\t\tmatch(NOT);\n\t\t\tsetState(1774);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1775);\n\t\t\tsrc_register();\n\t\t\tsetState(1776);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1777);\n\t\t\tcondition();\n\t\t\tsetState(1778);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1779);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jump_instructionContext extends ParserRuleContext {\n\t\tpublic Jeq_rii_instructionContext jeq_rii_instruction() {\n\t\t\treturn getRuleContext(Jeq_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jeq_rri_instructionContext jeq_rri_instruction() {\n\t\t\treturn getRuleContext(Jeq_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jneq_rii_instructionContext jneq_rii_instruction() {\n\t\t\treturn getRuleContext(Jneq_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jneq_rri_instructionContext jneq_rri_instruction() {\n\t\t\treturn getRuleContext(Jneq_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jz_ri_instructionContext jz_ri_instruction() {\n\t\t\treturn getRuleContext(Jz_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jnz_ri_instructionContext jnz_ri_instruction() {\n\t\t\treturn getRuleContext(Jnz_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jltu_rii_instructionContext jltu_rii_instruction() {\n\t\t\treturn getRuleContext(Jltu_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jltu_rri_instructionContext jltu_rri_instruction() {\n\t\t\treturn getRuleContext(Jltu_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgtu_rii_instructionContext jgtu_rii_instruction() {\n\t\t\treturn getRuleContext(Jgtu_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgtu_rri_instructionContext jgtu_rri_instruction() {\n\t\t\treturn getRuleContext(Jgtu_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jleu_rii_instructionContext jleu_rii_instruction() {\n\t\t\treturn getRuleContext(Jleu_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jleu_rri_instructionContext jleu_rri_instruction() {\n\t\t\treturn getRuleContext(Jleu_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgeu_rii_instructionContext jgeu_rii_instruction() {\n\t\t\treturn getRuleContext(Jgeu_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgeu_rri_instructionContext jgeu_rri_instruction() {\n\t\t\treturn getRuleContext(Jgeu_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jlts_rii_instructionContext jlts_rii_instruction() {\n\t\t\treturn getRuleContext(Jlts_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jlts_rri_instructionContext jlts_rri_instruction() {\n\t\t\treturn getRuleContext(Jlts_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgts_rii_instructionContext jgts_rii_instruction() {\n\t\t\treturn getRuleContext(Jgts_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jgts_rri_instructionContext jgts_rri_instruction() {\n\t\t\treturn getRuleContext(Jgts_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jles_rii_instructionContext jles_rii_instruction() {\n\t\t\treturn getRuleContext(Jles_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jles_rri_instructionContext jles_rri_instruction() {\n\t\t\treturn getRuleContext(Jles_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jges_rii_instructionContext jges_rii_instruction() {\n\t\t\treturn getRuleContext(Jges_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Jges_rri_instructionContext jges_rri_instruction() {\n\t\t\treturn getRuleContext(Jges_rri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jump_ri_instructionContext jump_ri_instruction() {\n\t\t\treturn getRuleContext(Jump_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Jump_i_instructionContext jump_i_instruction() {\n\t\t\treturn getRuleContext(Jump_i_instructionContext.class,0);\n\t\t}\n\t\tpublic Jump_r_instructionContext jump_r_instruction() {\n\t\t\treturn getRuleContext(Jump_r_instructionContext.class,0);\n\t\t}\n\t\tpublic Jump_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jump_instruction; }\n\t}\n\n\tpublic final Jump_instructionContext jump_instruction() throws RecognitionException {\n\t\tJump_instructionContext _localctx = new Jump_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 314, RULE_jump_instruction);\n\t\ttry {\n\t\t\tsetState(1806);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,18,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1781);\n\t\t\t\tjeq_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1782);\n\t\t\t\tjeq_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1783);\n\t\t\t\tjneq_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(1784);\n\t\t\t\tjneq_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(1785);\n\t\t\t\tjz_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(1786);\n\t\t\t\tjnz_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tenterOuterAlt(_localctx, 7);\n\t\t\t\t{\n\t\t\t\tsetState(1787);\n\t\t\t\tjltu_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tenterOuterAlt(_localctx, 8);\n\t\t\t\t{\n\t\t\t\tsetState(1788);\n\t\t\t\tjltu_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tenterOuterAlt(_localctx, 9);\n\t\t\t\t{\n\t\t\t\tsetState(1789);\n\t\t\t\tjgtu_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tenterOuterAlt(_localctx, 10);\n\t\t\t\t{\n\t\t\t\tsetState(1790);\n\t\t\t\tjgtu_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tenterOuterAlt(_localctx, 11);\n\t\t\t\t{\n\t\t\t\tsetState(1791);\n\t\t\t\tjleu_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tenterOuterAlt(_localctx, 12);\n\t\t\t\t{\n\t\t\t\tsetState(1792);\n\t\t\t\tjleu_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 13:\n\t\t\t\tenterOuterAlt(_localctx, 13);\n\t\t\t\t{\n\t\t\t\tsetState(1793);\n\t\t\t\tjgeu_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 14:\n\t\t\t\tenterOuterAlt(_localctx, 14);\n\t\t\t\t{\n\t\t\t\tsetState(1794);\n\t\t\t\tjgeu_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 15:\n\t\t\t\tenterOuterAlt(_localctx, 15);\n\t\t\t\t{\n\t\t\t\tsetState(1795);\n\t\t\t\tjlts_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 16:\n\t\t\t\tenterOuterAlt(_localctx, 16);\n\t\t\t\t{\n\t\t\t\tsetState(1796);\n\t\t\t\tjlts_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 17:\n\t\t\t\tenterOuterAlt(_localctx, 17);\n\t\t\t\t{\n\t\t\t\tsetState(1797);\n\t\t\t\tjgts_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 18:\n\t\t\t\tenterOuterAlt(_localctx, 18);\n\t\t\t\t{\n\t\t\t\tsetState(1798);\n\t\t\t\tjgts_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 19:\n\t\t\t\tenterOuterAlt(_localctx, 19);\n\t\t\t\t{\n\t\t\t\tsetState(1799);\n\t\t\t\tjles_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 20:\n\t\t\t\tenterOuterAlt(_localctx, 20);\n\t\t\t\t{\n\t\t\t\tsetState(1800);\n\t\t\t\tjles_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 21:\n\t\t\t\tenterOuterAlt(_localctx, 21);\n\t\t\t\t{\n\t\t\t\tsetState(1801);\n\t\t\t\tjges_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 22:\n\t\t\t\tenterOuterAlt(_localctx, 22);\n\t\t\t\t{\n\t\t\t\tsetState(1802);\n\t\t\t\tjges_rri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 23:\n\t\t\t\tenterOuterAlt(_localctx, 23);\n\t\t\t\t{\n\t\t\t\tsetState(1803);\n\t\t\t\tjump_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 24:\n\t\t\t\tenterOuterAlt(_localctx, 24);\n\t\t\t\t{\n\t\t\t\tsetState(1804);\n\t\t\t\tjump_i_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 25:\n\t\t\t\tenterOuterAlt(_localctx, 25);\n\t\t\t\t{\n\t\t\t\tsetState(1805);\n\t\t\t\tjump_r_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jeq_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JEQ() { return getToken(assemblyParser.JEQ, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<Program_counterContext> program_counter() {\n\t\t\treturn getRuleContexts(Program_counterContext.class);\n\t\t}\n\t\tpublic Program_counterContext program_counter(int i) {\n\t\t\treturn getRuleContext(Program_counterContext.class,i);\n\t\t}\n\t\tpublic Jeq_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jeq_rii_instruction; }\n\t}\n\n\tpublic final Jeq_rii_instructionContext jeq_rii_instruction() throws RecognitionException {\n\t\tJeq_rii_instructionContext _localctx = new Jeq_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 316, RULE_jeq_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1808);\n\t\t\tmatch(JEQ);\n\t\t\tsetState(1809);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1810);\n\t\t\tsrc_register();\n\t\t\tsetState(1811);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1812);\n\t\t\tprogram_counter();\n\t\t\tsetState(1813);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1814);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jeq_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JEQ() { return getToken(assemblyParser.JEQ, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jeq_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jeq_rri_instruction; }\n\t}\n\n\tpublic final Jeq_rri_instructionContext jeq_rri_instruction() throws RecognitionException {\n\t\tJeq_rri_instructionContext _localctx = new Jeq_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 318, RULE_jeq_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1816);\n\t\t\tmatch(JEQ);\n\t\t\tsetState(1817);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1818);\n\t\t\tsrc_register();\n\t\t\tsetState(1819);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1820);\n\t\t\tsrc_register();\n\t\t\tsetState(1821);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1822);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jneq_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JNEQ() { return getToken(assemblyParser.JNEQ, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jneq_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jneq_rii_instruction; }\n\t}\n\n\tpublic final Jneq_rii_instructionContext jneq_rii_instruction() throws RecognitionException {\n\t\tJneq_rii_instructionContext _localctx = new Jneq_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 320, RULE_jneq_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1824);\n\t\t\tmatch(JNEQ);\n\t\t\tsetState(1825);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1826);\n\t\t\tsrc_register();\n\t\t\tsetState(1827);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1828);\n\t\t\tnumber();\n\t\t\tsetState(1829);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1830);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jneq_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JNEQ() { return getToken(assemblyParser.JNEQ, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jneq_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jneq_rri_instruction; }\n\t}\n\n\tpublic final Jneq_rri_instructionContext jneq_rri_instruction() throws RecognitionException {\n\t\tJneq_rri_instructionContext _localctx = new Jneq_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 322, RULE_jneq_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1832);\n\t\t\tmatch(JNEQ);\n\t\t\tsetState(1833);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1834);\n\t\t\tsrc_register();\n\t\t\tsetState(1835);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1836);\n\t\t\tsrc_register();\n\t\t\tsetState(1837);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1838);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jz_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JZ() { return getToken(assemblyParser.JZ, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jz_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jz_ri_instruction; }\n\t}\n\n\tpublic final Jz_ri_instructionContext jz_ri_instruction() throws RecognitionException {\n\t\tJz_ri_instructionContext _localctx = new Jz_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 324, RULE_jz_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1840);\n\t\t\tmatch(JZ);\n\t\t\tsetState(1841);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1842);\n\t\t\tsrc_register();\n\t\t\tsetState(1843);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1844);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jnz_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JNZ() { return getToken(assemblyParser.JNZ, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jnz_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jnz_ri_instruction; }\n\t}\n\n\tpublic final Jnz_ri_instructionContext jnz_ri_instruction() throws RecognitionException {\n\t\tJnz_ri_instructionContext _localctx = new Jnz_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 326, RULE_jnz_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1846);\n\t\t\tmatch(JNZ);\n\t\t\tsetState(1847);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1848);\n\t\t\tsrc_register();\n\t\t\tsetState(1849);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1850);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jltu_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLTU() { return getToken(assemblyParser.JLTU, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jltu_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jltu_rii_instruction; }\n\t}\n\n\tpublic final Jltu_rii_instructionContext jltu_rii_instruction() throws RecognitionException {\n\t\tJltu_rii_instructionContext _localctx = new Jltu_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 328, RULE_jltu_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1852);\n\t\t\tmatch(JLTU);\n\t\t\tsetState(1853);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1854);\n\t\t\tsrc_register();\n\t\t\tsetState(1855);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1856);\n\t\t\tnumber();\n\t\t\tsetState(1857);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1858);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jltu_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLTU() { return getToken(assemblyParser.JLTU, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jltu_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jltu_rri_instruction; }\n\t}\n\n\tpublic final Jltu_rri_instructionContext jltu_rri_instruction() throws RecognitionException {\n\t\tJltu_rri_instructionContext _localctx = new Jltu_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 330, RULE_jltu_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1860);\n\t\t\tmatch(JLTU);\n\t\t\tsetState(1861);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1862);\n\t\t\tsrc_register();\n\t\t\tsetState(1863);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1864);\n\t\t\tsrc_register();\n\t\t\tsetState(1865);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1866);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgtu_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGTU() { return getToken(assemblyParser.JGTU, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgtu_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgtu_rii_instruction; }\n\t}\n\n\tpublic final Jgtu_rii_instructionContext jgtu_rii_instruction() throws RecognitionException {\n\t\tJgtu_rii_instructionContext _localctx = new Jgtu_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 332, RULE_jgtu_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1868);\n\t\t\tmatch(JGTU);\n\t\t\tsetState(1869);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1870);\n\t\t\tsrc_register();\n\t\t\tsetState(1871);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1872);\n\t\t\tnumber();\n\t\t\tsetState(1873);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1874);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgtu_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGTU() { return getToken(assemblyParser.JGTU, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgtu_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgtu_rri_instruction; }\n\t}\n\n\tpublic final Jgtu_rri_instructionContext jgtu_rri_instruction() throws RecognitionException {\n\t\tJgtu_rri_instructionContext _localctx = new Jgtu_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 334, RULE_jgtu_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1876);\n\t\t\tmatch(JGTU);\n\t\t\tsetState(1877);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1878);\n\t\t\tsrc_register();\n\t\t\tsetState(1879);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1880);\n\t\t\tsrc_register();\n\t\t\tsetState(1881);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1882);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jleu_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLEU() { return getToken(assemblyParser.JLEU, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jleu_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jleu_rii_instruction; }\n\t}\n\n\tpublic final Jleu_rii_instructionContext jleu_rii_instruction() throws RecognitionException {\n\t\tJleu_rii_instructionContext _localctx = new Jleu_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 336, RULE_jleu_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1884);\n\t\t\tmatch(JLEU);\n\t\t\tsetState(1885);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1886);\n\t\t\tsrc_register();\n\t\t\tsetState(1887);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1888);\n\t\t\tnumber();\n\t\t\tsetState(1889);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1890);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jleu_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLEU() { return getToken(assemblyParser.JLEU, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jleu_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jleu_rri_instruction; }\n\t}\n\n\tpublic final Jleu_rri_instructionContext jleu_rri_instruction() throws RecognitionException {\n\t\tJleu_rri_instructionContext _localctx = new Jleu_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 338, RULE_jleu_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1892);\n\t\t\tmatch(JLEU);\n\t\t\tsetState(1893);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1894);\n\t\t\tsrc_register();\n\t\t\tsetState(1895);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1896);\n\t\t\tsrc_register();\n\t\t\tsetState(1897);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1898);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgeu_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGEU() { return getToken(assemblyParser.JGEU, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgeu_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgeu_rii_instruction; }\n\t}\n\n\tpublic final Jgeu_rii_instructionContext jgeu_rii_instruction() throws RecognitionException {\n\t\tJgeu_rii_instructionContext _localctx = new Jgeu_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 340, RULE_jgeu_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1900);\n\t\t\tmatch(JGEU);\n\t\t\tsetState(1901);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1902);\n\t\t\tsrc_register();\n\t\t\tsetState(1903);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1904);\n\t\t\tnumber();\n\t\t\tsetState(1905);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1906);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgeu_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGEU() { return getToken(assemblyParser.JGEU, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgeu_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgeu_rri_instruction; }\n\t}\n\n\tpublic final Jgeu_rri_instructionContext jgeu_rri_instruction() throws RecognitionException {\n\t\tJgeu_rri_instructionContext _localctx = new Jgeu_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 342, RULE_jgeu_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1908);\n\t\t\tmatch(JGEU);\n\t\t\tsetState(1909);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1910);\n\t\t\tsrc_register();\n\t\t\tsetState(1911);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1912);\n\t\t\tsrc_register();\n\t\t\tsetState(1913);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1914);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jlts_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLTS() { return getToken(assemblyParser.JLTS, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jlts_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jlts_rii_instruction; }\n\t}\n\n\tpublic final Jlts_rii_instructionContext jlts_rii_instruction() throws RecognitionException {\n\t\tJlts_rii_instructionContext _localctx = new Jlts_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 344, RULE_jlts_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1916);\n\t\t\tmatch(JLTS);\n\t\t\tsetState(1917);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1918);\n\t\t\tsrc_register();\n\t\t\tsetState(1919);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1920);\n\t\t\tnumber();\n\t\t\tsetState(1921);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1922);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jlts_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLTS() { return getToken(assemblyParser.JLTS, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jlts_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jlts_rri_instruction; }\n\t}\n\n\tpublic final Jlts_rri_instructionContext jlts_rri_instruction() throws RecognitionException {\n\t\tJlts_rri_instructionContext _localctx = new Jlts_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 346, RULE_jlts_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1924);\n\t\t\tmatch(JLTS);\n\t\t\tsetState(1925);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1926);\n\t\t\tsrc_register();\n\t\t\tsetState(1927);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1928);\n\t\t\tsrc_register();\n\t\t\tsetState(1929);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1930);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgts_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGTS() { return getToken(assemblyParser.JGTS, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgts_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgts_rii_instruction; }\n\t}\n\n\tpublic final Jgts_rii_instructionContext jgts_rii_instruction() throws RecognitionException {\n\t\tJgts_rii_instructionContext _localctx = new Jgts_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 348, RULE_jgts_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1932);\n\t\t\tmatch(JGTS);\n\t\t\tsetState(1933);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1934);\n\t\t\tsrc_register();\n\t\t\tsetState(1935);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1936);\n\t\t\tnumber();\n\t\t\tsetState(1937);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1938);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jgts_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGTS() { return getToken(assemblyParser.JGTS, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jgts_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jgts_rri_instruction; }\n\t}\n\n\tpublic final Jgts_rri_instructionContext jgts_rri_instruction() throws RecognitionException {\n\t\tJgts_rri_instructionContext _localctx = new Jgts_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 350, RULE_jgts_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1940);\n\t\t\tmatch(JGTS);\n\t\t\tsetState(1941);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1942);\n\t\t\tsrc_register();\n\t\t\tsetState(1943);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1944);\n\t\t\tsrc_register();\n\t\t\tsetState(1945);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1946);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jles_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLES() { return getToken(assemblyParser.JLES, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jles_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jles_rii_instruction; }\n\t}\n\n\tpublic final Jles_rii_instructionContext jles_rii_instruction() throws RecognitionException {\n\t\tJles_rii_instructionContext _localctx = new Jles_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 352, RULE_jles_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1948);\n\t\t\tmatch(JLES);\n\t\t\tsetState(1949);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1950);\n\t\t\tsrc_register();\n\t\t\tsetState(1951);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1952);\n\t\t\tnumber();\n\t\t\tsetState(1953);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1954);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jles_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JLES() { return getToken(assemblyParser.JLES, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jles_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jles_rri_instruction; }\n\t}\n\n\tpublic final Jles_rri_instructionContext jles_rri_instruction() throws RecognitionException {\n\t\tJles_rri_instructionContext _localctx = new Jles_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 354, RULE_jles_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1956);\n\t\t\tmatch(JLES);\n\t\t\tsetState(1957);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1958);\n\t\t\tsrc_register();\n\t\t\tsetState(1959);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1960);\n\t\t\tsrc_register();\n\t\t\tsetState(1961);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1962);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jges_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGES() { return getToken(assemblyParser.JGES, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jges_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jges_rii_instruction; }\n\t}\n\n\tpublic final Jges_rii_instructionContext jges_rii_instruction() throws RecognitionException {\n\t\tJges_rii_instructionContext _localctx = new Jges_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 356, RULE_jges_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1964);\n\t\t\tmatch(JGES);\n\t\t\tsetState(1965);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1966);\n\t\t\tsrc_register();\n\t\t\tsetState(1967);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1968);\n\t\t\tnumber();\n\t\t\tsetState(1969);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1970);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jges_rri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JGES() { return getToken(assemblyParser.JGES, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jges_rri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jges_rri_instruction; }\n\t}\n\n\tpublic final Jges_rri_instructionContext jges_rri_instruction() throws RecognitionException {\n\t\tJges_rri_instructionContext _localctx = new Jges_rri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 358, RULE_jges_rri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1972);\n\t\t\tmatch(JGES);\n\t\t\tsetState(1973);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1974);\n\t\t\tsrc_register();\n\t\t\tsetState(1975);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1976);\n\t\t\tsrc_register();\n\t\t\tsetState(1977);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1978);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jump_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JUMP() { return getToken(assemblyParser.JUMP, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jump_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jump_ri_instruction; }\n\t}\n\n\tpublic final Jump_ri_instructionContext jump_ri_instruction() throws RecognitionException {\n\t\tJump_ri_instructionContext _localctx = new Jump_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 360, RULE_jump_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1980);\n\t\t\tmatch(JUMP);\n\t\t\tsetState(1981);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1982);\n\t\t\tsrc_register();\n\t\t\tsetState(1983);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1984);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jump_i_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JUMP() { return getToken(assemblyParser.JUMP, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Jump_i_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jump_i_instruction; }\n\t}\n\n\tpublic final Jump_i_instructionContext jump_i_instruction() throws RecognitionException {\n\t\tJump_i_instructionContext _localctx = new Jump_i_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 362, RULE_jump_i_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1986);\n\t\t\tmatch(JUMP);\n\t\t\tsetState(1987);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1988);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Jump_r_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode JUMP() { return getToken(assemblyParser.JUMP, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Jump_r_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_jump_r_instruction; }\n\t}\n\n\tpublic final Jump_r_instructionContext jump_r_instruction() throws RecognitionException {\n\t\tJump_r_instructionContext _localctx = new Jump_r_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 364, RULE_jump_r_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(1990);\n\t\t\tmatch(JUMP);\n\t\t\tsetState(1991);\n\t\t\tmatch(T__3);\n\t\t\tsetState(1992);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Shortcut_instructionContext extends ParserRuleContext {\n\t\tpublic Div_step_drdici_instructionContext div_step_drdici_instruction() {\n\t\t\treturn getRuleContext(Div_step_drdici_instructionContext.class,0);\n\t\t}\n\t\tpublic Mul_step_drdici_instructionContext mul_step_drdici_instruction() {\n\t\t\treturn getRuleContext(Mul_step_drdici_instructionContext.class,0);\n\t\t}\n\t\tpublic Boot_rici_instructionContext boot_rici_instruction() {\n\t\t\treturn getRuleContext(Boot_rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Resume_rici_instructionContext resume_rici_instruction() {\n\t\t\treturn getRuleContext(Resume_rici_instructionContext.class,0);\n\t\t}\n\t\tpublic Stop_ci_instructionContext stop_ci_instruction() {\n\t\t\treturn getRuleContext(Stop_ci_instructionContext.class,0);\n\t\t}\n\t\tpublic Call_ri_instructionContext call_ri_instruction() {\n\t\t\treturn getRuleContext(Call_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Call_rr_instructionContext call_rr_instruction() {\n\t\t\treturn getRuleContext(Call_rr_instructionContext.class,0);\n\t\t}\n\t\tpublic Bkp_instructionContext bkp_instruction() {\n\t\t\treturn getRuleContext(Bkp_instructionContext.class,0);\n\t\t}\n\t\tpublic Movd_ddci_instructionContext movd_ddci_instruction() {\n\t\t\treturn getRuleContext(Movd_ddci_instructionContext.class,0);\n\t\t}\n\t\tpublic Swapd_ddci_instructionContext swapd_ddci_instruction() {\n\t\t\treturn getRuleContext(Swapd_ddci_instructionContext.class,0);\n\t\t}\n\t\tpublic Time_cfg_zr_instructionContext time_cfg_zr_instruction() {\n\t\t\treturn getRuleContext(Time_cfg_zr_instructionContext.class,0);\n\t\t}\n\t\tpublic Lbs_erri_instructionContext lbs_erri_instruction() {\n\t\t\treturn getRuleContext(Lbs_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lbs_s_erri_instructionContext lbs_s_erri_instruction() {\n\t\t\treturn getRuleContext(Lbs_s_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lbu_erri_instructionContext lbu_erri_instruction() {\n\t\t\treturn getRuleContext(Lbu_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lbu_u_erri_instructionContext lbu_u_erri_instruction() {\n\t\t\treturn getRuleContext(Lbu_u_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Ld_edri_instructionContext ld_edri_instruction() {\n\t\t\treturn getRuleContext(Ld_edri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lhs_erri_instructionContext lhs_erri_instruction() {\n\t\t\treturn getRuleContext(Lhs_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lhs_s_erri_instructionContext lhs_s_erri_instruction() {\n\t\t\treturn getRuleContext(Lhs_s_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lhu_erri_instructionContext lhu_erri_instruction() {\n\t\t\treturn getRuleContext(Lhu_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lhu_u_erri_instructionContext lhu_u_erri_instruction() {\n\t\t\treturn getRuleContext(Lhu_u_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lw_erri_instructionContext lw_erri_instruction() {\n\t\t\treturn getRuleContext(Lw_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lw_s_erri_instructionContext lw_s_erri_instruction() {\n\t\t\treturn getRuleContext(Lw_s_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Lw_u_erri_instructionContext lw_u_erri_instruction() {\n\t\t\treturn getRuleContext(Lw_u_erri_instructionContext.class,0);\n\t\t}\n\t\tpublic Sb_erii_instructionContext sb_erii_instruction() {\n\t\t\treturn getRuleContext(Sb_erii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sb_erir_instructionContext sb_erir_instruction() {\n\t\t\treturn getRuleContext(Sb_erir_instructionContext.class,0);\n\t\t}\n\t\tpublic Sb_id_rii_instructionContext sb_id_rii_instruction() {\n\t\t\treturn getRuleContext(Sb_id_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sb_id_ri_instructionContext sb_id_ri_instruction() {\n\t\t\treturn getRuleContext(Sb_id_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Sd_erii_instructionContext sd_erii_instruction() {\n\t\t\treturn getRuleContext(Sd_erii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sd_erid_instructionContext sd_erid_instruction() {\n\t\t\treturn getRuleContext(Sd_erid_instructionContext.class,0);\n\t\t}\n\t\tpublic Sd_id_rii_instructionContext sd_id_rii_instruction() {\n\t\t\treturn getRuleContext(Sd_id_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sd_id_ri_instructionContext sd_id_ri_instruction() {\n\t\t\treturn getRuleContext(Sd_id_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Sh_erii_instructionContext sh_erii_instruction() {\n\t\t\treturn getRuleContext(Sh_erii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sh_erir_instructionContext sh_erir_instruction() {\n\t\t\treturn getRuleContext(Sh_erir_instructionContext.class,0);\n\t\t}\n\t\tpublic Sh_id_rii_instructionContext sh_id_rii_instruction() {\n\t\t\treturn getRuleContext(Sh_id_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sh_id_ri_instructionContext sh_id_ri_instruction() {\n\t\t\treturn getRuleContext(Sh_id_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Sw_erii_instructionContext sw_erii_instruction() {\n\t\t\treturn getRuleContext(Sw_erii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sw_erir_instructionContext sw_erir_instruction() {\n\t\t\treturn getRuleContext(Sw_erir_instructionContext.class,0);\n\t\t}\n\t\tpublic Sw_id_rii_instructionContext sw_id_rii_instruction() {\n\t\t\treturn getRuleContext(Sw_id_rii_instructionContext.class,0);\n\t\t}\n\t\tpublic Sw_id_ri_instructionContext sw_id_ri_instruction() {\n\t\t\treturn getRuleContext(Sw_id_ri_instructionContext.class,0);\n\t\t}\n\t\tpublic Shortcut_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_shortcut_instruction; }\n\t}\n\n\tpublic final Shortcut_instructionContext shortcut_instruction() throws RecognitionException {\n\t\tShortcut_instructionContext _localctx = new Shortcut_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 366, RULE_shortcut_instruction);\n\t\ttry {\n\t\t\tsetState(2033);\n\t\t\t_errHandler.sync(this);\n\t\t\tswitch ( getInterpreter().adaptivePredict(_input,19,_ctx) ) {\n\t\t\tcase 1:\n\t\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t\t{\n\t\t\t\tsetState(1994);\n\t\t\t\tdiv_step_drdici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\tenterOuterAlt(_localctx, 2);\n\t\t\t\t{\n\t\t\t\tsetState(1995);\n\t\t\t\tmul_step_drdici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tenterOuterAlt(_localctx, 3);\n\t\t\t\t{\n\t\t\t\tsetState(1996);\n\t\t\t\tboot_rici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 4:\n\t\t\t\tenterOuterAlt(_localctx, 4);\n\t\t\t\t{\n\t\t\t\tsetState(1997);\n\t\t\t\tresume_rici_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 5:\n\t\t\t\tenterOuterAlt(_localctx, 5);\n\t\t\t\t{\n\t\t\t\tsetState(1998);\n\t\t\t\tstop_ci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 6:\n\t\t\t\tenterOuterAlt(_localctx, 6);\n\t\t\t\t{\n\t\t\t\tsetState(1999);\n\t\t\t\tcall_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 7:\n\t\t\t\tenterOuterAlt(_localctx, 7);\n\t\t\t\t{\n\t\t\t\tsetState(2000);\n\t\t\t\tcall_rr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 8:\n\t\t\t\tenterOuterAlt(_localctx, 8);\n\t\t\t\t{\n\t\t\t\tsetState(2001);\n\t\t\t\tbkp_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 9:\n\t\t\t\tenterOuterAlt(_localctx, 9);\n\t\t\t\t{\n\t\t\t\tsetState(2002);\n\t\t\t\tmovd_ddci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 10:\n\t\t\t\tenterOuterAlt(_localctx, 10);\n\t\t\t\t{\n\t\t\t\tsetState(2003);\n\t\t\t\tswapd_ddci_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 11:\n\t\t\t\tenterOuterAlt(_localctx, 11);\n\t\t\t\t{\n\t\t\t\tsetState(2004);\n\t\t\t\ttime_cfg_zr_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 12:\n\t\t\t\tenterOuterAlt(_localctx, 12);\n\t\t\t\t{\n\t\t\t\tsetState(2005);\n\t\t\t\tlbs_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 13:\n\t\t\t\tenterOuterAlt(_localctx, 13);\n\t\t\t\t{\n\t\t\t\tsetState(2006);\n\t\t\t\tlbs_s_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 14:\n\t\t\t\tenterOuterAlt(_localctx, 14);\n\t\t\t\t{\n\t\t\t\tsetState(2007);\n\t\t\t\tlbu_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 15:\n\t\t\t\tenterOuterAlt(_localctx, 15);\n\t\t\t\t{\n\t\t\t\tsetState(2008);\n\t\t\t\tlbu_u_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 16:\n\t\t\t\tenterOuterAlt(_localctx, 16);\n\t\t\t\t{\n\t\t\t\tsetState(2009);\n\t\t\t\tld_edri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 17:\n\t\t\t\tenterOuterAlt(_localctx, 17);\n\t\t\t\t{\n\t\t\t\tsetState(2010);\n\t\t\t\tlhs_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 18:\n\t\t\t\tenterOuterAlt(_localctx, 18);\n\t\t\t\t{\n\t\t\t\tsetState(2011);\n\t\t\t\tlhs_s_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 19:\n\t\t\t\tenterOuterAlt(_localctx, 19);\n\t\t\t\t{\n\t\t\t\tsetState(2012);\n\t\t\t\tlhu_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 20:\n\t\t\t\tenterOuterAlt(_localctx, 20);\n\t\t\t\t{\n\t\t\t\tsetState(2013);\n\t\t\t\tlhu_u_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 21:\n\t\t\t\tenterOuterAlt(_localctx, 21);\n\t\t\t\t{\n\t\t\t\tsetState(2014);\n\t\t\t\tlw_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 22:\n\t\t\t\tenterOuterAlt(_localctx, 22);\n\t\t\t\t{\n\t\t\t\tsetState(2015);\n\t\t\t\tlw_s_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 23:\n\t\t\t\tenterOuterAlt(_localctx, 23);\n\t\t\t\t{\n\t\t\t\tsetState(2016);\n\t\t\t\tlw_u_erri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 24:\n\t\t\t\tenterOuterAlt(_localctx, 24);\n\t\t\t\t{\n\t\t\t\tsetState(2017);\n\t\t\t\tsb_erii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 25:\n\t\t\t\tenterOuterAlt(_localctx, 25);\n\t\t\t\t{\n\t\t\t\tsetState(2018);\n\t\t\t\tsb_erir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 26:\n\t\t\t\tenterOuterAlt(_localctx, 26);\n\t\t\t\t{\n\t\t\t\tsetState(2019);\n\t\t\t\tsb_id_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 27:\n\t\t\t\tenterOuterAlt(_localctx, 27);\n\t\t\t\t{\n\t\t\t\tsetState(2020);\n\t\t\t\tsb_id_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 28:\n\t\t\t\tenterOuterAlt(_localctx, 28);\n\t\t\t\t{\n\t\t\t\tsetState(2021);\n\t\t\t\tsd_erii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 29:\n\t\t\t\tenterOuterAlt(_localctx, 29);\n\t\t\t\t{\n\t\t\t\tsetState(2022);\n\t\t\t\tsd_erid_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 30:\n\t\t\t\tenterOuterAlt(_localctx, 30);\n\t\t\t\t{\n\t\t\t\tsetState(2023);\n\t\t\t\tsd_id_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 31:\n\t\t\t\tenterOuterAlt(_localctx, 31);\n\t\t\t\t{\n\t\t\t\tsetState(2024);\n\t\t\t\tsd_id_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 32:\n\t\t\t\tenterOuterAlt(_localctx, 32);\n\t\t\t\t{\n\t\t\t\tsetState(2025);\n\t\t\t\tsh_erii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 33:\n\t\t\t\tenterOuterAlt(_localctx, 33);\n\t\t\t\t{\n\t\t\t\tsetState(2026);\n\t\t\t\tsh_erir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 34:\n\t\t\t\tenterOuterAlt(_localctx, 34);\n\t\t\t\t{\n\t\t\t\tsetState(2027);\n\t\t\t\tsh_id_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 35:\n\t\t\t\tenterOuterAlt(_localctx, 35);\n\t\t\t\t{\n\t\t\t\tsetState(2028);\n\t\t\t\tsh_id_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 36:\n\t\t\t\tenterOuterAlt(_localctx, 36);\n\t\t\t\t{\n\t\t\t\tsetState(2029);\n\t\t\t\tsw_erii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 37:\n\t\t\t\tenterOuterAlt(_localctx, 37);\n\t\t\t\t{\n\t\t\t\tsetState(2030);\n\t\t\t\tsw_erir_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 38:\n\t\t\t\tenterOuterAlt(_localctx, 38);\n\t\t\t\t{\n\t\t\t\tsetState(2031);\n\t\t\t\tsw_id_rii_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 39:\n\t\t\t\tenterOuterAlt(_localctx, 39);\n\t\t\t\t{\n\t\t\t\tsetState(2032);\n\t\t\t\tsw_id_ri_instruction();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Div_step_drdici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode DIV_STEP() { return getToken(assemblyParser.DIV_STEP, 0); }\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Div_step_drdici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_div_step_drdici_instruction; }\n\t}\n\n\tpublic final Div_step_drdici_instructionContext div_step_drdici_instruction() throws RecognitionException {\n\t\tDiv_step_drdici_instructionContext _localctx = new Div_step_drdici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 368, RULE_div_step_drdici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2035);\n\t\t\tmatch(DIV_STEP);\n\t\t\tsetState(2036);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2037);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2038);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2039);\n\t\t\tsrc_register();\n\t\t\tsetState(2040);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2041);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2042);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2043);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Mul_step_drdici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MUL_STEP() { return getToken(assemblyParser.MUL_STEP, 0); }\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Mul_step_drdici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_mul_step_drdici_instruction; }\n\t}\n\n\tpublic final Mul_step_drdici_instructionContext mul_step_drdici_instruction() throws RecognitionException {\n\t\tMul_step_drdici_instructionContext _localctx = new Mul_step_drdici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 370, RULE_mul_step_drdici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2045);\n\t\t\tmatch(MUL_STEP);\n\t\t\tsetState(2046);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2047);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2048);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2049);\n\t\t\tsrc_register();\n\t\t\tsetState(2050);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2051);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2052);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2053);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Boot_rici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode BOOT() { return getToken(assemblyParser.BOOT, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Boot_rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_boot_rici_instruction; }\n\t}\n\n\tpublic final Boot_rici_instructionContext boot_rici_instruction() throws RecognitionException {\n\t\tBoot_rici_instructionContext _localctx = new Boot_rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 372, RULE_boot_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2055);\n\t\t\tmatch(BOOT);\n\t\t\tsetState(2056);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2057);\n\t\t\tsrc_register();\n\t\t\tsetState(2058);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2059);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Resume_rici_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode RESUME() { return getToken(assemblyParser.RESUME, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Resume_rici_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_resume_rici_instruction; }\n\t}\n\n\tpublic final Resume_rici_instructionContext resume_rici_instruction() throws RecognitionException {\n\t\tResume_rici_instructionContext _localctx = new Resume_rici_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 374, RULE_resume_rici_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2061);\n\t\t\tmatch(RESUME);\n\t\t\tsetState(2062);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2063);\n\t\t\tsrc_register();\n\t\t\tsetState(2064);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2065);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Stop_ci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode STOP() { return getToken(assemblyParser.STOP, 0); }\n\t\tpublic Stop_ci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_stop_ci_instruction; }\n\t}\n\n\tpublic final Stop_ci_instructionContext stop_ci_instruction() throws RecognitionException {\n\t\tStop_ci_instructionContext _localctx = new Stop_ci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 376, RULE_stop_ci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2067);\n\t\t\tmatch(STOP);\n\t\t\tsetState(2068);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Call_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode CALL() { return getToken(assemblyParser.CALL, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Call_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_call_ri_instruction; }\n\t}\n\n\tpublic final Call_ri_instructionContext call_ri_instruction() throws RecognitionException {\n\t\tCall_ri_instructionContext _localctx = new Call_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 378, RULE_call_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2070);\n\t\t\tmatch(CALL);\n\t\t\tsetState(2071);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2072);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2073);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2074);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Call_rr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode CALL() { return getToken(assemblyParser.CALL, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Call_rr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_call_rr_instruction; }\n\t}\n\n\tpublic final Call_rr_instructionContext call_rr_instruction() throws RecognitionException {\n\t\tCall_rr_instructionContext _localctx = new Call_rr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 380, RULE_call_rr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2076);\n\t\t\tmatch(CALL);\n\t\t\tsetState(2077);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2078);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2079);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2080);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Bkp_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode BKP() { return getToken(assemblyParser.BKP, 0); }\n\t\tpublic Bkp_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_bkp_instruction; }\n\t}\n\n\tpublic final Bkp_instructionContext bkp_instruction() throws RecognitionException {\n\t\tBkp_instructionContext _localctx = new Bkp_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 382, RULE_bkp_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2082);\n\t\t\tmatch(BKP);\n\t\t\tsetState(2083);\n\t\t\tmatch(T__3);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Movd_ddci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode MOVD() { return getToken(assemblyParser.MOVD, 0); }\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic Movd_ddci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_movd_ddci_instruction; }\n\t}\n\n\tpublic final Movd_ddci_instructionContext movd_ddci_instruction() throws RecognitionException {\n\t\tMovd_ddci_instructionContext _localctx = new Movd_ddci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 384, RULE_movd_ddci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2085);\n\t\t\tmatch(MOVD);\n\t\t\tsetState(2086);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2087);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2088);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2089);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Swapd_ddci_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SWAPD() { return getToken(assemblyParser.SWAPD, 0); }\n\t\tpublic List<TerminalNode> PairRegister() { return getTokens(assemblyParser.PairRegister); }\n\t\tpublic TerminalNode PairRegister(int i) {\n\t\t\treturn getToken(assemblyParser.PairRegister, i);\n\t\t}\n\t\tpublic Swapd_ddci_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_swapd_ddci_instruction; }\n\t}\n\n\tpublic final Swapd_ddci_instructionContext swapd_ddci_instruction() throws RecognitionException {\n\t\tSwapd_ddci_instructionContext _localctx = new Swapd_ddci_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 386, RULE_swapd_ddci_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2091);\n\t\t\tmatch(SWAPD);\n\t\t\tsetState(2092);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2093);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2094);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2095);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Time_cfg_zr_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode TIME_CFG() { return getToken(assemblyParser.TIME_CFG, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Time_cfg_zr_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_time_cfg_zr_instruction; }\n\t}\n\n\tpublic final Time_cfg_zr_instructionContext time_cfg_zr_instruction() throws RecognitionException {\n\t\tTime_cfg_zr_instructionContext _localctx = new Time_cfg_zr_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 388, RULE_time_cfg_zr_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2097);\n\t\t\tmatch(TIME_CFG);\n\t\t\tsetState(2098);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2099);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lbs_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LBS() { return getToken(assemblyParser.LBS, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lbs_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lbs_erri_instruction; }\n\t}\n\n\tpublic final Lbs_erri_instructionContext lbs_erri_instruction() throws RecognitionException {\n\t\tLbs_erri_instructionContext _localctx = new Lbs_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 390, RULE_lbs_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2101);\n\t\t\tmatch(LBS);\n\t\t\tsetState(2102);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2103);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2104);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2105);\n\t\t\tsrc_register();\n\t\t\tsetState(2106);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2107);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lbs_s_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LBS() { return getToken(assemblyParser.LBS, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lbs_s_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lbs_s_erri_instruction; }\n\t}\n\n\tpublic final Lbs_s_erri_instructionContext lbs_s_erri_instruction() throws RecognitionException {\n\t\tLbs_s_erri_instructionContext _localctx = new Lbs_s_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 392, RULE_lbs_s_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2109);\n\t\t\tmatch(LBS);\n\t\t\tsetState(2110);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(2111);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2112);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2113);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2114);\n\t\t\tsrc_register();\n\t\t\tsetState(2115);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2116);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lbu_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LBU() { return getToken(assemblyParser.LBU, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lbu_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lbu_erri_instruction; }\n\t}\n\n\tpublic final Lbu_erri_instructionContext lbu_erri_instruction() throws RecognitionException {\n\t\tLbu_erri_instructionContext _localctx = new Lbu_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 394, RULE_lbu_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2118);\n\t\t\tmatch(LBU);\n\t\t\tsetState(2119);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2120);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2121);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2122);\n\t\t\tsrc_register();\n\t\t\tsetState(2123);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2124);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lbu_u_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LBU() { return getToken(assemblyParser.LBU, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lbu_u_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lbu_u_erri_instruction; }\n\t}\n\n\tpublic final Lbu_u_erri_instructionContext lbu_u_erri_instruction() throws RecognitionException {\n\t\tLbu_u_erri_instructionContext _localctx = new Lbu_u_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 396, RULE_lbu_u_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2126);\n\t\t\tmatch(LBU);\n\t\t\tsetState(2127);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(2128);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2129);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2130);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2131);\n\t\t\tsrc_register();\n\t\t\tsetState(2132);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2133);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Ld_edri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LD() { return getToken(assemblyParser.LD, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Ld_edri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_ld_edri_instruction; }\n\t}\n\n\tpublic final Ld_edri_instructionContext ld_edri_instruction() throws RecognitionException {\n\t\tLd_edri_instructionContext _localctx = new Ld_edri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 398, RULE_ld_edri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2135);\n\t\t\tmatch(LD);\n\t\t\tsetState(2136);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2137);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2138);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2139);\n\t\t\tsrc_register();\n\t\t\tsetState(2140);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2141);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lhs_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LHS() { return getToken(assemblyParser.LHS, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lhs_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lhs_erri_instruction; }\n\t}\n\n\tpublic final Lhs_erri_instructionContext lhs_erri_instruction() throws RecognitionException {\n\t\tLhs_erri_instructionContext _localctx = new Lhs_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 400, RULE_lhs_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2143);\n\t\t\tmatch(LHS);\n\t\t\tsetState(2144);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2145);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2146);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2147);\n\t\t\tsrc_register();\n\t\t\tsetState(2148);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2149);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lhs_s_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LHS() { return getToken(assemblyParser.LHS, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lhs_s_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lhs_s_erri_instruction; }\n\t}\n\n\tpublic final Lhs_s_erri_instructionContext lhs_s_erri_instruction() throws RecognitionException {\n\t\tLhs_s_erri_instructionContext _localctx = new Lhs_s_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 402, RULE_lhs_s_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2151);\n\t\t\tmatch(LHS);\n\t\t\tsetState(2152);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(2153);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2154);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2155);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2156);\n\t\t\tsrc_register();\n\t\t\tsetState(2157);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2158);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lhu_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LHU() { return getToken(assemblyParser.LHU, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lhu_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lhu_erri_instruction; }\n\t}\n\n\tpublic final Lhu_erri_instructionContext lhu_erri_instruction() throws RecognitionException {\n\t\tLhu_erri_instructionContext _localctx = new Lhu_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 404, RULE_lhu_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2160);\n\t\t\tmatch(LHU);\n\t\t\tsetState(2161);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2162);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2163);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2164);\n\t\t\tsrc_register();\n\t\t\tsetState(2165);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2166);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lhu_u_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LHU() { return getToken(assemblyParser.LHU, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lhu_u_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lhu_u_erri_instruction; }\n\t}\n\n\tpublic final Lhu_u_erri_instructionContext lhu_u_erri_instruction() throws RecognitionException {\n\t\tLhu_u_erri_instructionContext _localctx = new Lhu_u_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 406, RULE_lhu_u_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2168);\n\t\t\tmatch(LHU);\n\t\t\tsetState(2169);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(2170);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2171);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2172);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2173);\n\t\t\tsrc_register();\n\t\t\tsetState(2174);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2175);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lw_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LW() { return getToken(assemblyParser.LW, 0); }\n\t\tpublic TerminalNode GPRegister() { return getToken(assemblyParser.GPRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lw_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lw_erri_instruction; }\n\t}\n\n\tpublic final Lw_erri_instructionContext lw_erri_instruction() throws RecognitionException {\n\t\tLw_erri_instructionContext _localctx = new Lw_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 408, RULE_lw_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2177);\n\t\t\tmatch(LW);\n\t\t\tsetState(2178);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2179);\n\t\t\tmatch(GPRegister);\n\t\t\tsetState(2180);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2181);\n\t\t\tsrc_register();\n\t\t\tsetState(2182);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2183);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lw_s_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LW() { return getToken(assemblyParser.LW, 0); }\n\t\tpublic TerminalNode S_SUFFIX() { return getToken(assemblyParser.S_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lw_s_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lw_s_erri_instruction; }\n\t}\n\n\tpublic final Lw_s_erri_instructionContext lw_s_erri_instruction() throws RecognitionException {\n\t\tLw_s_erri_instructionContext _localctx = new Lw_s_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 410, RULE_lw_s_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2185);\n\t\t\tmatch(LW);\n\t\t\tsetState(2186);\n\t\t\tmatch(S_SUFFIX);\n\t\t\tsetState(2187);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2188);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2189);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2190);\n\t\t\tsrc_register();\n\t\t\tsetState(2191);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2192);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Lw_u_erri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode LW() { return getToken(assemblyParser.LW, 0); }\n\t\tpublic TerminalNode U_SUFFIX() { return getToken(assemblyParser.U_SUFFIX, 0); }\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Lw_u_erri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_lw_u_erri_instruction; }\n\t}\n\n\tpublic final Lw_u_erri_instructionContext lw_u_erri_instruction() throws RecognitionException {\n\t\tLw_u_erri_instructionContext _localctx = new Lw_u_erri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 412, RULE_lw_u_erri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2194);\n\t\t\tmatch(LW);\n\t\t\tsetState(2195);\n\t\t\tmatch(U_SUFFIX);\n\t\t\tsetState(2196);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2197);\n\t\t\tmatch(PairRegister);\n\t\t\tsetState(2198);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2199);\n\t\t\tsrc_register();\n\t\t\tsetState(2200);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2201);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sb_erii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SB() { return getToken(assemblyParser.SB, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sb_erii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sb_erii_instruction; }\n\t}\n\n\tpublic final Sb_erii_instructionContext sb_erii_instruction() throws RecognitionException {\n\t\tSb_erii_instructionContext _localctx = new Sb_erii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 414, RULE_sb_erii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2203);\n\t\t\tmatch(SB);\n\t\t\tsetState(2204);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2205);\n\t\t\tsrc_register();\n\t\t\tsetState(2206);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2207);\n\t\t\tnumber();\n\t\t\tsetState(2208);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2209);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sb_erir_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SB() { return getToken(assemblyParser.SB, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sb_erir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sb_erir_instruction; }\n\t}\n\n\tpublic final Sb_erir_instructionContext sb_erir_instruction() throws RecognitionException {\n\t\tSb_erir_instructionContext _localctx = new Sb_erir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 416, RULE_sb_erir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2211);\n\t\t\tmatch(SB);\n\t\t\tsetState(2212);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2213);\n\t\t\tsrc_register();\n\t\t\tsetState(2214);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2215);\n\t\t\tprogram_counter();\n\t\t\tsetState(2216);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2217);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sb_id_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SB() { return getToken(assemblyParser.SB, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Sb_id_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sb_id_rii_instruction; }\n\t}\n\n\tpublic final Sb_id_rii_instructionContext sb_id_rii_instruction() throws RecognitionException {\n\t\tSb_id_rii_instructionContext _localctx = new Sb_id_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 418, RULE_sb_id_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2219);\n\t\t\tmatch(SB);\n\t\t\tsetState(2220);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2221);\n\t\t\tsrc_register();\n\t\t\tsetState(2222);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2223);\n\t\t\tnumber();\n\t\t\tsetState(2224);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2225);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sb_id_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SB() { return getToken(assemblyParser.SB, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Sb_id_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sb_id_ri_instruction; }\n\t}\n\n\tpublic final Sb_id_ri_instructionContext sb_id_ri_instruction() throws RecognitionException {\n\t\tSb_id_ri_instructionContext _localctx = new Sb_id_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 420, RULE_sb_id_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2227);\n\t\t\tmatch(SB);\n\t\t\tsetState(2228);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2229);\n\t\t\tsrc_register();\n\t\t\tsetState(2230);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2231);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sd_erii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SD() { return getToken(assemblyParser.SD, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<Program_counterContext> program_counter() {\n\t\t\treturn getRuleContexts(Program_counterContext.class);\n\t\t}\n\t\tpublic Program_counterContext program_counter(int i) {\n\t\t\treturn getRuleContext(Program_counterContext.class,i);\n\t\t}\n\t\tpublic Sd_erii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sd_erii_instruction; }\n\t}\n\n\tpublic final Sd_erii_instructionContext sd_erii_instruction() throws RecognitionException {\n\t\tSd_erii_instructionContext _localctx = new Sd_erii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 422, RULE_sd_erii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2233);\n\t\t\tmatch(SD);\n\t\t\tsetState(2234);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2235);\n\t\t\tsrc_register();\n\t\t\tsetState(2236);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2237);\n\t\t\tprogram_counter();\n\t\t\tsetState(2238);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2239);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sd_erid_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SD() { return getToken(assemblyParser.SD, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic TerminalNode PairRegister() { return getToken(assemblyParser.PairRegister, 0); }\n\t\tpublic Sd_erid_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sd_erid_instruction; }\n\t}\n\n\tpublic final Sd_erid_instructionContext sd_erid_instruction() throws RecognitionException {\n\t\tSd_erid_instructionContext _localctx = new Sd_erid_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 424, RULE_sd_erid_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2241);\n\t\t\tmatch(SD);\n\t\t\tsetState(2242);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2243);\n\t\t\tsrc_register();\n\t\t\tsetState(2244);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2245);\n\t\t\tprogram_counter();\n\t\t\tsetState(2246);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2247);\n\t\t\tmatch(PairRegister);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sd_id_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SD() { return getToken(assemblyParser.SD, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Sd_id_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sd_id_rii_instruction; }\n\t}\n\n\tpublic final Sd_id_rii_instructionContext sd_id_rii_instruction() throws RecognitionException {\n\t\tSd_id_rii_instructionContext _localctx = new Sd_id_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 426, RULE_sd_id_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2249);\n\t\t\tmatch(SD);\n\t\t\tsetState(2250);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2251);\n\t\t\tsrc_register();\n\t\t\tsetState(2252);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2253);\n\t\t\tnumber();\n\t\t\tsetState(2254);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2255);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sd_id_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SD() { return getToken(assemblyParser.SD, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Sd_id_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sd_id_ri_instruction; }\n\t}\n\n\tpublic final Sd_id_ri_instructionContext sd_id_ri_instruction() throws RecognitionException {\n\t\tSd_id_ri_instructionContext _localctx = new Sd_id_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 428, RULE_sd_id_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2257);\n\t\t\tmatch(SD);\n\t\t\tsetState(2258);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2259);\n\t\t\tsrc_register();\n\t\t\tsetState(2260);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2261);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sh_erii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SH() { return getToken(assemblyParser.SH, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sh_erii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sh_erii_instruction; }\n\t}\n\n\tpublic final Sh_erii_instructionContext sh_erii_instruction() throws RecognitionException {\n\t\tSh_erii_instructionContext _localctx = new Sh_erii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 430, RULE_sh_erii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2263);\n\t\t\tmatch(SH);\n\t\t\tsetState(2264);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2265);\n\t\t\tsrc_register();\n\t\t\tsetState(2266);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2267);\n\t\t\tnumber();\n\t\t\tsetState(2268);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2269);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sh_erir_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SH() { return getToken(assemblyParser.SH, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sh_erir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sh_erir_instruction; }\n\t}\n\n\tpublic final Sh_erir_instructionContext sh_erir_instruction() throws RecognitionException {\n\t\tSh_erir_instructionContext _localctx = new Sh_erir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 432, RULE_sh_erir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2271);\n\t\t\tmatch(SH);\n\t\t\tsetState(2272);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2273);\n\t\t\tsrc_register();\n\t\t\tsetState(2274);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2275);\n\t\t\tprogram_counter();\n\t\t\tsetState(2276);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2277);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sh_id_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SH() { return getToken(assemblyParser.SH, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Sh_id_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sh_id_rii_instruction; }\n\t}\n\n\tpublic final Sh_id_rii_instructionContext sh_id_rii_instruction() throws RecognitionException {\n\t\tSh_id_rii_instructionContext _localctx = new Sh_id_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 434, RULE_sh_id_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2279);\n\t\t\tmatch(SH);\n\t\t\tsetState(2280);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2281);\n\t\t\tsrc_register();\n\t\t\tsetState(2282);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2283);\n\t\t\tnumber();\n\t\t\tsetState(2284);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2285);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sh_id_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SH() { return getToken(assemblyParser.SH, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Sh_id_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sh_id_ri_instruction; }\n\t}\n\n\tpublic final Sh_id_ri_instructionContext sh_id_ri_instruction() throws RecognitionException {\n\t\tSh_id_ri_instructionContext _localctx = new Sh_id_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 436, RULE_sh_id_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2287);\n\t\t\tmatch(SH);\n\t\t\tsetState(2288);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2289);\n\t\t\tsrc_register();\n\t\t\tsetState(2290);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2291);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sw_erii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SW() { return getToken(assemblyParser.SW, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sw_erii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sw_erii_instruction; }\n\t}\n\n\tpublic final Sw_erii_instructionContext sw_erii_instruction() throws RecognitionException {\n\t\tSw_erii_instructionContext _localctx = new Sw_erii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 438, RULE_sw_erii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2293);\n\t\t\tmatch(SW);\n\t\t\tsetState(2294);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2295);\n\t\t\tsrc_register();\n\t\t\tsetState(2296);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2297);\n\t\t\tnumber();\n\t\t\tsetState(2298);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2299);\n\t\t\tprogram_counter();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sw_erir_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SW() { return getToken(assemblyParser.SW, 0); }\n\t\tpublic List<Src_registerContext> src_register() {\n\t\t\treturn getRuleContexts(Src_registerContext.class);\n\t\t}\n\t\tpublic Src_registerContext src_register(int i) {\n\t\t\treturn getRuleContext(Src_registerContext.class,i);\n\t\t}\n\t\tpublic Program_counterContext program_counter() {\n\t\t\treturn getRuleContext(Program_counterContext.class,0);\n\t\t}\n\t\tpublic Sw_erir_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sw_erir_instruction; }\n\t}\n\n\tpublic final Sw_erir_instructionContext sw_erir_instruction() throws RecognitionException {\n\t\tSw_erir_instructionContext _localctx = new Sw_erir_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 440, RULE_sw_erir_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2301);\n\t\t\tmatch(SW);\n\t\t\tsetState(2302);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2303);\n\t\t\tsrc_register();\n\t\t\tsetState(2304);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2305);\n\t\t\tprogram_counter();\n\t\t\tsetState(2306);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2307);\n\t\t\tsrc_register();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sw_id_rii_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SW() { return getToken(assemblyParser.SW, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic List<NumberContext> number() {\n\t\t\treturn getRuleContexts(NumberContext.class);\n\t\t}\n\t\tpublic NumberContext number(int i) {\n\t\t\treturn getRuleContext(NumberContext.class,i);\n\t\t}\n\t\tpublic Sw_id_rii_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sw_id_rii_instruction; }\n\t}\n\n\tpublic final Sw_id_rii_instructionContext sw_id_rii_instruction() throws RecognitionException {\n\t\tSw_id_rii_instructionContext _localctx = new Sw_id_rii_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 442, RULE_sw_id_rii_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2309);\n\t\t\tmatch(SW);\n\t\t\tsetState(2310);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2311);\n\t\t\tsrc_register();\n\t\t\tsetState(2312);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2313);\n\t\t\tnumber();\n\t\t\tsetState(2314);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2315);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class Sw_id_ri_instructionContext extends ParserRuleContext {\n\t\tpublic TerminalNode SW() { return getToken(assemblyParser.SW, 0); }\n\t\tpublic Src_registerContext src_register() {\n\t\t\treturn getRuleContext(Src_registerContext.class,0);\n\t\t}\n\t\tpublic NumberContext number() {\n\t\t\treturn getRuleContext(NumberContext.class,0);\n\t\t}\n\t\tpublic Sw_id_ri_instructionContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_sw_id_ri_instruction; }\n\t}\n\n\tpublic final Sw_id_ri_instructionContext sw_id_ri_instruction() throws RecognitionException {\n\t\tSw_id_ri_instructionContext _localctx = new Sw_id_ri_instructionContext(_ctx, getState());\n\t\tenterRule(_localctx, 444, RULE_sw_id_ri_instruction);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2317);\n\t\t\tmatch(SW);\n\t\t\tsetState(2318);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2319);\n\t\t\tsrc_register();\n\t\t\tsetState(2320);\n\t\t\tmatch(T__3);\n\t\t\tsetState(2321);\n\t\t\tnumber();\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static class LabelContext extends ParserRuleContext {\n\t\tpublic TerminalNode Identifier() { return getToken(assemblyParser.Identifier, 0); }\n\t\tpublic LabelContext(ParserRuleContext parent, int invokingState) {\n\t\t\tsuper(parent, invokingState);\n\t\t}\n\t\t@Override public int getRuleIndex() { return RULE_label; }\n\t}\n\n\tpublic final LabelContext label() throws RecognitionException {\n\t\tLabelContext _localctx = new LabelContext(_ctx, getState());\n\t\tenterRule(_localctx, 446, RULE_label);\n\t\ttry {\n\t\t\tenterOuterAlt(_localctx, 1);\n\t\t\t{\n\t\t\tsetState(2323);\n\t\t\tmatch(Identifier);\n\t\t\tsetState(2324);\n\t\t\tmatch(T__4);\n\t\t\t}\n\t\t}\n\t\tcatch (RecognitionException re) {\n\t\t\t_localctx.exception = re;\n\t\t\t_errHandler.reportError(this, re);\n\t\t\t_errHandler.recover(this, re);\n\t\t}\n\t\tfinally {\n\t\t\texitRule();\n\t\t}\n\t\treturn _localctx;\n\t}\n\n\tpublic static final String _serializedATN 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static final ATN _ATN =\n\t\tnew ATNDeserializer().deserialize(_serializedATN.toCharArray());\n\tstatic {\n\t\t_decisionToDFA = new DFA[_ATN.getNumberOfDecisions()];\n\t\tfor (int i = 0; i < _ATN.getNumberOfDecisions(); i++) {\n\t\t\t_decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i);\n\t\t}\n\t}\n}"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assembly.g4",
    "content": "grammar assembly;\n\ndocument: (directive | instruction | label)* EOF;\n\nACQUIRE: '$acquire';\nRELEASE: '$release';\nBOOT: '$boot';\nRESUME: '$resume';\n\nADD: '$add';\nADDC: '$addc';\nAND: '$and';\nANDN: '$andn';\nASR: '$asr';\nCMPB4: '$cmpb4';\nLSL: '$lsl';\nLSL1: '$lsl1';\nLSL1X: '$lsl1x';\nLSLX: '$lslx';\nLSR: '$lsr';\nLSR1: '$lsr1';\nLSR1X: '$lsr1x';\nLSRX: '$lsrx';\nMUL_SH_SH: '$mul_sh_sh';\nMUL_SH_SL: '$mul_sh_sl';\nMUL_SH_UH: '$mul_sh_uh';\nMUL_SH_UL: '$mul_sh_ul';\nMUL_SL_SH: '$mul_sl_sh';\nMUL_SL_SL: '$mul_sl_sl';\nMUL_SL_UH: '$mul_sl_uh';\nMUL_SL_UL: '$mul_sl_ul';\nMUL_UH_UH: '$mul_uh_uh';\nMUL_UH_UL: '$mul_uh_ul';\nMUL_UL_UH: '$mul_ul_uh';\nMUL_UL_UL: '$mul_ul_ul';\nNAND: '$nand';\nNOR: '$nor';\nNXOR: '$nxor';\nOR: '$or';\nORN: '$orn';\nROL: '$rol';\nROR: '$ror';\nRSUB: '$rsub';\nRSUBC: '$rsubc';\nSUB: '$sub';\nSUBC: '$subc';\nXOR: '$xor';\nCALL: '$call';\nHASH: '$hash';\n\nCAO: '$cao';\nCLO: '$clo';\nCLS: '$cls';\nCLZ: '$clz';\nEXTSB: '$extsb';\nEXTSH: '$extsh';\nEXTUB: '$extub';\nEXTUH: '$extuh';\nSATS: '$sats';\nTIME_CFG: '$time_cfg';\n\nDIV_STEP: '$div_step';\nMUL_STEP: '$mul_step';\n\nLSL_ADD: '$lsl_add';\nLSL_SUB: '$lsl_sub';\nLSR_ADD: '$lsr_add';\nROL_ADD: '$rol_add';\nROR_ADD: '$ror_add';\n\nTIME: '$time';\nNOP: '$nop';\n\nSTOP: '$stop';\n\nFAULT: '$fault';\n\nMOVD: '$movd';\nSWAPD: '$swapd';\n\nLBS: '$lbs';\nLBU: '$lbu';\nLD: '$ld';\nLHS: '$lhs';\nLHU: '$lhu';\nLW: '$lw';\n\nSB: '$sb';\nSB_ID: '$sb_id';\nSD: '$sd';\nSD_ID: '$sd_id';\nSH: '$sh';\nSH_ID: '$sh_id';\nSW: '$sw';\nSW_ID: '$sw_id';\n\nLDMA: '$ldma';\nLDMAI: '$ldmai';\nSDMA: '$sdma';\n\nMOVE: '$move';\nNEG: '$neg';\nNOT: '$not';\nBKP: '$bkp';\n\nJEQ: '$jeq';\nJNEQ: '$jneq';\nJZ: '$jz';\nJNZ: '$jnz';\nJLTU: '$jltu';\nJGTU: '$jgtu';\nJLEU: '$jleu';\nJGEU: '$jgeu';\nJLTS: '$jlts';\nJGTS: '$jgts';\nJLES: '$jles';\nJGES: '$jges';\nJUMP: '$jump';\n\nATOMIC: '%atomic';\nBSS: '%bss';\nDATA: '%data';\nDEBUG_ABBREV: '%debug_abbrev';\nDEBUG_FRAME: '%debug_frame';\nDEBUG_INFO: '%debug_info';\nDEBUG_LINE: '%debug_line';\nDEBUG_LOC: '%debug_loc';\nDEBUG_RANGES: '%debug_ranges';\nDEBUG_STR: '%debug_str';\nDPU_HOST: '%dpu_host';\nMRAM: '%mram';\nRODATA: '%rodata';\nSTACK_SIZES: '%stack_sizes';\nTEXT_SECTION: '%text';\n\nPROGBITS: '@progbits';\nNOBITS: '@nobits';\n\nFUNCTION: '@function';\nOBJECT: '@object';\n\nTRUE: 'true';\nFALSE: 'false';\nZ: 'z';\nNZ: 'nz';\nE: 'e';\nO: 'o';\nPL: 'pl';\nMI: 'mi';\nOV: 'ov';\nNOV: 'nov';\nC: 'c';\nNC: 'nc';\nSZ: 'sz';\nSNZ: 'snz';\nSPL: 'spl';\nSMI: 'smi';\nSO: 'so';\nSE: 'se';\nNC5: 'nc5';\nNC6: 'nc6';\nNC7: 'nc7';\nNC8: 'nc8';\nNC9: 'nc9';\nNC10: 'nc10';\nNC11: 'nc11';\nNC12: 'nc12';\nNC13: 'nc13';\nNC14: 'nc14';\nMAX: 'max';\nNMAX: 'nmax';\nSH32: 'sh32';\nNSH32: 'nsh32';\nEQ: 'eq';\nNEQ: 'neq';\nLTU: 'ltu';\nLEU: 'leu';\nGTU: 'gtu';\nGEU: 'geu';\nLTS: 'lts';\nLES: 'les';\nGTS: 'gts';\nGES: 'ges';\nXZ: 'xz';\nXNZ: 'xnz';\nXLEU: 'xleu';\nXGTU: 'xgtu';\nXLES: 'xles';\nXGTS: 'xgts';\nSMALL: 'small';\nLARGE: 'large';\n\nLITTLE: '!little';\nBIG: '!big';\n\nZERO_REGISTER: 'zero';\nONE: 'one';\nID: 'id';\nID2: 'id2';\nID4: 'id4';\nID8: 'id8';\nLNEG: 'lneg';\nMNEG: 'mneg';\n\nADDRSIG: '$addrsig';\nADDRSIG_SYM: '$addrsig_sym';\nASCII: '$ascii';\nASCIZ: '$asciz';\nBYTE: '$byte';\nCFI_DEF_CFA_OFFSET: '$cfi_def_cfa_offset';\nCFI_ENDPROC: '$cfi_endproc';\nCFI_OFFSET: '$cfi_offset';\nCFI_SECTIONS: '$cfi_sections';\nCFI_STARTPROC: '$cfi_startproc';\nFILE: '$file';\nGLOBL: '$globl';\nLOC: '$loc';\nLONG: '$long';\nP2ALIGN: '$p2align';\nQUAD: '$quad';\nSECTION: '$section';\nSET: '$set';\nSHORT: '$short';\nSIZE: '$size';\nTEXT_DIRECTIVE: '$text';\nTYPE: '$type';\nWEAK: '$weak';\nZERO_DIRECTIVE: '$zero';\n\nIS_STMT: 'is_stmt';\nPROLOGUE_END: 'prologue_end';\n\nS_SUFFIX: '.s';\nU_SUFFIX: '.u';\n\nPositiveNumber: [0-9]+;\nnegative_number: '-' PositiveNumber;\nhex_number: '0x' PositiveNumber;\nnumber\n\t: PositiveNumber\n\t| negative_number\n\t| hex_number\n\t;\n\nrici_op_code\n\t: ACQUIRE\n\t| RELEASE\n\t| BOOT\n\t| RESUME\n\t;\n\nrri_op_code\n\t: ADD\n\t| ADDC\n\t| AND\n\t| ANDN\n\t| ASR\n\t| CMPB4\n\t| LSL\n\t| LSL1\n\t| LSL1X\n\t| LSLX\n\t| LSR\n\t| LSR1\n\t| LSR1X\n\t| LSRX\n\t| MUL_SH_SH\n\t| MUL_SH_SL\n\t| MUL_SH_UH\n\t| MUL_SH_UL\n\t| MUL_SL_SH\n\t| MUL_SL_SL\n\t| MUL_SL_UH\n\t| MUL_SL_UL\n\t| MUL_UH_UH\n\t| MUL_UH_UL\n\t| MUL_UL_UH\n\t| MUL_UL_UL\n\t| NAND\n\t| NOR\n\t| NXOR\n\t| OR\n\t| ORN\n\t| ROL\n\t| ROR\n\t| RSUB\n\t| RSUBC\n\t| SUB\n\t| SUBC\n\t| XOR\n\t| CALL\n\t| HASH\n\t;\n\nrr_op_code\n\t: CAO\n\t| CLO\n\t| CLS\n\t| CLZ\n\t| EXTSB\n\t| EXTSH\n\t| EXTUB\n\t| EXTUH\n\t| SATS\n\t| TIME_CFG\n\t;\n\ndrdici_op_code \n\t: DIV_STEP\n\t| MUL_STEP\n\t;\n\nrrri_op_code\n\t: LSL_ADD\n\t| LSL_SUB\n\t| LSR_ADD\n\t| ROL_ADD\n\t| ROR_ADD\n\t;\n\nr_op_code\n\t: TIME\n\t| NOP\n\t;\n\nci_op_code\n\t: STOP\n\t;\n\ni_op_code\n\t: FAULT\n\t;\n\nddci_op_code\n\t: MOVD\n\t| SWAPD\n\t;\n\nload_op_code\n\t: LBS\n\t| LBU\n\t| LD\n\t| LHS\n\t| LHU\n\t| LW\n\t;\n\nstore_op_code\n\t: SB\n\t| SB_ID\n\t| SD\n\t| SD_ID\n\t| SH\n\t| SH_ID\n\t| SW\n\t| SW_ID\n\t;\n\ndma_op_code\n\t: LDMA\n\t| LDMAI\n\t| SDMA\n\t;\n\nsection_name\n\t: ATOMIC\n\t| BSS\n\t| DATA\n\t| DEBUG_ABBREV\n\t| DEBUG_FRAME\n\t| DEBUG_INFO\n\t| DEBUG_LINE\n\t| DEBUG_LOC\n\t| DEBUG_RANGES\n\t| DEBUG_STR\n\t| DPU_HOST\n\t| MRAM\n\t| RODATA\n\t| STACK_SIZES\n\t| TEXT_SECTION\n\t;\n\nsection_types: PROGBITS | NOBITS;\n\nsymbol_type: FUNCTION | OBJECT;\n\ncondition\n\t: TRUE\n\t| FALSE\n\t| Z\n\t| NZ\n\t| E\n\t| O\n\t| PL\n\t| MI\n\t| OV\n\t| NOV\n\t| C\n\t| NC\n\t| SZ\n\t| SNZ\n\t| SPL\n\t| SMI\n\t| SO\n\t| SE\n\t| NC5\n\t| NC6\n\t| NC7\n\t| NC8\n\t| NC9\n\t| NC10\n\t| NC11\n\t| NC12\n\t| NC13\n\t| NC14\n\t| MAX\n\t| NMAX\n\t| SH32\n\t| NSH32\n\t| EQ\n\t| NEQ\n\t| LTU\n\t| LEU\n\t| GTU\n\t| GEU\n\t| LTS\n\t| LES\n\t| GTS\n\t| GES\n\t| XZ\n\t| XNZ\n\t| XLEU\n\t| XGTU\n\t| XLES\n\t| XGTS\n\t| SMALL\n\t| LARGE\n\t;\n\nendian: LITTLE | BIG ;\n\nGPRegister: 'r' [0-9]+;\n\nsp_register\n\t: ZERO_REGISTER\n\t| ONE\n\t| ID\n\t| ID2\n\t| ID4\n\t| ID8\n\t| LNEG\n\t| MNEG\n\t;\n\nPairRegister: 'd' [0-9]+;\n\n\nIdentifier: ([a-zA-Z] | '.' | '_') ([a-zA-Z] | [0-9] | '.' | '_')*;\n\nStringLiteral\n\t: '\"'\n\t\t( [a-zA-Z]\n\t\t| [0-9]\n\t\t| '.'\n\t\t| ','\n\t\t| '_'\n\t\t| '+'\n\t\t| '-'\n\t\t| '/'\n\t\t| ':'\n\t\t| ';'\n\t\t| '('\n\t\t| ')'\n\t\t| '['\n\t\t| ']'\n\t\t| '{'\n\t\t| '}'\n\t\t| '?'\n\t\t| '!'\n\t\t| '\\\\'\n\t\t| WHITE_SPACE\n\t\t)*\n\t'\"'\n\t;\n\nsrc_register: GPRegister | sp_register;\n\nprogram_counter\n\t: primary_expression\n\t| add_expression\n\t| sub_expression\n\t;\nadd_expression: primary_expression '+' primary_expression;\nsub_expression: primary_expression '-' primary_expression;\nprimary_expression: number | Identifier | section_name;\n\ndirective\n\t: addrsig_directive\n\t| addrsig_sym_directive\n\t| ascii_directive\n\t| asciz_directive\n\t| byte_directive\n\t| cfi_def_cfa_offset_directive\n\t| cfi_endproc_directive\n\t| cfi_offset_directive\n\t| cfi_sections_directive\n\t| cfi_startproc_directive\n\t| file_directive\n\t| global_directive\n\t| loc_directive\n\t| long_directive\n\t| p2align_directive\n\t| quad_directive\n\t| section_directive\n\t| set_directive\n\t| short_directive\n\t| size_directive\n\t| stack_sizes_directive\n\t| text_directive\n\t| type_directive\n\t| weak_directive\n\t| zero_directive\n\t;\n\naddrsig_directive: ADDRSIG ',';\naddrsig_sym_directive: ADDRSIG_SYM ',' Identifier;\nascii_directive: ASCII ',' StringLiteral;\nasciz_directive: ASCIZ ',' StringLiteral;\nbyte_directive: BYTE ',' program_counter;\ncfi_def_cfa_offset_directive: CFI_DEF_CFA_OFFSET ',' number;\ncfi_endproc_directive: CFI_ENDPROC ',';\ncfi_offset_directive: CFI_OFFSET ',' number ',' number;\ncfi_sections_directive: CFI_SECTIONS ',' section_name;\ncfi_startproc_directive: CFI_STARTPROC ',';\nfile_directive\n\t: FILE ',' StringLiteral\n\t| FILE ',' number StringLiteral StringLiteral\n\t;\nglobal_directive: GLOBL ',' Identifier;\nloc_directive\n\t: LOC ',' number number number\n\t| LOC ',' number number number IS_STMT number\n\t| LOC ',' number number number PROLOGUE_END\n\t;\nlong_directive: LONG ',' program_counter;\np2align_directive: P2ALIGN ',' number;\nquad_directive: QUAD ',' program_counter;\nsection_directive\n\t: SECTION ',' section_name ',' StringLiteral ',' section_types\n\t| SECTION ',' section_name ',' StringLiteral ',' section_types ',' number\n\t| SECTION ',' section_name ',' Identifier ',' StringLiteral ',' section_types\n\t| SECTION ',' section_name ',' Identifier ',' StringLiteral ',' section_types ',' number\n\t;\nset_directive: SET ',' Identifier ',' Identifier;\nshort_directive: SHORT ',' program_counter;\nsize_directive: SIZE ',' Identifier ',' program_counter;\nstack_sizes_directive: SECTION ',' STACK_SIZES ',' StringLiteral ',' section_types ',' section_name ',' Identifier;\ntext_directive: TEXT_DIRECTIVE ',';\ntype_directive: TYPE ',' Identifier ',' symbol_type;\nweak_directive: WEAK ',' Identifier;\nzero_directive\n\t: ZERO_DIRECTIVE ',' number\n\t| ZERO_DIRECTIVE ',' number ',' number\n\t;\n\ninstruction\n\t: rici_instruction\n\t| rri_instruction\n\t| rric_instruction\n\t| rrici_instruction\n\t| rrr_instruction\n\t| rrrc_instruction\n\t| rrrci_instruction\n\t| zri_instruction\n\t| zric_instruction\n\t| zrici_instruction\n\t| zrr_instruction\n\t| zrrc_instruction\n\t| zrrci_instruction\n\t| s_rri_instruction\n\t| s_rric_instruction\n\t| s_rrici_instruction\n\t| s_rrr_instruction\n\t| s_rrrc_instruction\n\t| s_rrrci_instruction\n\t| u_rri_instruction\n\t| u_rric_instruction\n\t| u_rrici_instruction\n\t| u_rrr_instruction\n\t| u_rrrc_instruction\n\t| u_rrrci_instruction\n\t| rr_instruction\n\t| rrc_instruction\n\t| rrci_instruction\n\t| zr_instruction\n\t| zrc_instruction\n\t| zrci_instruction\n\t| s_rr_instruction\n\t| s_rrc_instruction\n\t| s_rrci_instruction\n\t| u_rr_instruction\n\t| u_rrc_instruction\n\t| u_rrci_instruction\n\t| drdici_instruction\n\t| rrri_instruction\n\t| rrrici_instruction\n\t| zrri_instruction\n\t| zrrici_instruction\n\t| s_rrri_instruction\n\t| s_rrrici_instruction\n\t| u_rrri_instruction\n\t| u_rrrici_instruction\n\t| rir_instruction\n\t| rirc_instruction\n\t| rirci_instruction\n\t| zir_instruction\n\t| zirc_instruction\n\t| zrici_instruction\n\t| s_rirc_instruction\n\t| s_rirci_instruction\n\t| u_rric_instruction\n\t| u_rrici_instruction\n\t| r_instruction\n\t| rci_instruction\n\t| z_instruction\n\t| zci_instruction\n\t| s_r_instruction\n\t| s_rci_instruction\n\t| u_r_instruction\n\t| u_rci_instruction\n\t| ci_instruction\n\t| i_instruction\n\t| ddci_instruction\n\t| erri_instruction\n\t| edri_instruction\n\t| s_erri_instruction\n\t| u_erri_instruction\n\t| erii_instruction\n\t| erir_instruction\n\t| erid_instruction\n\t| dma_rri_instruction\n\t| synthetic_sugar_instruction\n\t;\n\nrici_instruction: rici_op_code ',' src_register ',' program_counter ',' condition ',' program_counter;\n\nrri_instruction: rri_op_code ',' GPRegister ',' src_register ',' number;\nrric_instruction: rri_op_code ',' GPRegister ',' src_register ',' number ',' condition;\nrrici_instruction: rri_op_code ',' GPRegister ',' src_register ',' number ',' condition ',' program_counter;\nrrr_instruction: rri_op_code ',' GPRegister ',' src_register ',' src_register;\nrrrc_instruction: rri_op_code ',' GPRegister ',' src_register ',' src_register ',' condition;\nrrrci_instruction: rri_op_code ',' GPRegister ',' src_register ',' src_register ',' condition ',' program_counter;\n\nzri_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' program_counter;\nzric_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' number ',' condition;\nzrici_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' number ',' condition ',' program_counter;\nzrr_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' src_register;\nzrrc_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' src_register ',' condition;\nzrrci_instruction: rri_op_code ',' ZERO_REGISTER ',' src_register ',' src_register ',' condition ',' program_counter;\n\ns_rri_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' number;\ns_rric_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' number ',' condition;\ns_rrici_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' number ',' condition ',' program_counter;\ns_rrr_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' src_register;\ns_rrrc_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' condition;\ns_rrrci_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' condition ',' program_counter;\n\nu_rri_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' number;\nu_rric_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' number ',' condition;\nu_rrici_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' number ',' condition ',' program_counter;\nu_rrr_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' src_register;\nu_rrrc_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' condition;\nu_rrrci_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' condition ',' program_counter;\n\nrr_instruction: rr_op_code ',' GPRegister ',' src_register;\nrrc_instruction: rr_op_code ',' GPRegister ',' src_register ',' condition;\nrrci_instruction: rr_op_code ',' GPRegister ',' src_register ',' condition ',' program_counter;\n\nzr_instruction: rr_op_code ',' ZERO_REGISTER ',' src_register;\nzrc_instruction: rr_op_code ',' ZERO_REGISTER ',' src_register ',' condition;\nzrci_instruction: rr_op_code ',' ZERO_REGISTER ',' src_register ',' condition ',' program_counter;\n\ns_rr_instruction: rr_op_code S_SUFFIX ',' PairRegister ',' src_register;\ns_rrc_instruction: rr_op_code S_SUFFIX ',' PairRegister ',' src_register ',' condition;\ns_rrci_instruction: rr_op_code S_SUFFIX ',' PairRegister ',' src_register ',' condition ',' program_counter;\n\nu_rr_instruction: rr_op_code U_SUFFIX ',' PairRegister ',' src_register;\nu_rrc_instruction: rr_op_code U_SUFFIX ',' PairRegister ',' src_register ',' condition;\nu_rrci_instruction: rr_op_code U_SUFFIX ',' PairRegister ',' src_register ',' condition ',' program_counter;\n\ndrdici_instruction: drdici_op_code ',' PairRegister ',' src_register ',' PairRegister ',' number ',' condition ',' program_counter;\n\nrrri_instruction: rrri_op_code ',' GPRegister ',' src_register ',' src_register ',' number;\nrrrici_instruction: rrri_op_code ',' GPRegister ',' src_register ',' src_register ',' number ',' condition ',' program_counter;\n\nzrri_instruction: rrri_op_code ',' ZERO_REGISTER ',' src_register ',' src_register ',' number;\nzrrici_instruction: rrri_op_code ',' ZERO_REGISTER ',' src_register ',' src_register ',' number ',' condition ',' program_counter;\n\ns_rrri_instruction: rrri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' number;\ns_rrrici_instruction: rrri_op_code S_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' number ',' condition ',' program_counter;\n\nu_rrri_instruction: rrri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' number;\nu_rrrici_instruction: rrri_op_code U_SUFFIX ',' PairRegister ',' src_register ',' src_register ',' number ',' condition ',' program_counter;\n\nrir_instruction: rri_op_code ',' GPRegister ',' number ',' src_register;\nrirc_instruction: rri_op_code ',' GPRegister ',' number ',' src_register ',' condition;\nrirci_instruction: rri_op_code ',' GPRegister ',' number ',' src_register ',' condition ',' program_counter;\n\nzir_instruction: rri_op_code ',' ZERO_REGISTER ',' number ',' src_register;\nzirc_instruction: rri_op_code ',' ZERO_REGISTER ',' number ',' src_register ',' condition;\nzirci_instruction: rri_op_code ',' ZERO_REGISTER ',' number ',' src_register ',' condition ',' program_counter;\n\ns_rirc_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' number ',' src_register;\ns_rirci_instruction: rri_op_code S_SUFFIX ',' PairRegister ',' number ',' src_register ',' program_counter;\n\nu_rirc_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' number ',' src_register;\nu_rirci_instruction: rri_op_code U_SUFFIX ',' PairRegister ',' number ',' src_register ',' program_counter;\n\nr_instruction: r_op_code ',' GPRegister;\nrci_instruction: r_op_code ',' condition ',' condition ',' program_counter;\n\nz_instruction\n\t: r_op_code ','\n\t| r_op_code ',' ZERO_REGISTER\n\t;\nzci_instruction: r_op_code ',' ZERO_REGISTER ',' condition ',' program_counter;\n\ns_r_instruction: r_op_code S_SUFFIX ',' PairRegister;\ns_rci_instruction: r_op_code S_SUFFIX ',' PairRegister ',' condition ',' program_counter;\n\nu_r_instruction: r_op_code U_SUFFIX ',' PairRegister;\nu_rci_instruction: r_op_code U_SUFFIX ',' PairRegister ',' condition ',' program_counter;\n\nci_instruction: ci_op_code ',' condition ',' program_counter;\ni_instruction: i_op_code ',' number;\n\nddci_instruction: ddci_op_code ',' PairRegister ',' PairRegister ',' condition ',' program_counter;\n\nerri_instruction: load_op_code ',' endian ',' GPRegister ',' src_register ',' program_counter;\nedri_instruction: load_op_code ',' endian ',' PairRegister ',' src_register ',' program_counter;\ns_erri_instruction: load_op_code S_SUFFIX ',' endian ',' PairRegister ',' src_register ',' program_counter;\nu_erri_instruction: load_op_code U_SUFFIX ',' endian ',' PairRegister ',' src_register ',' program_counter;\n\nerii_instruction: store_op_code ',' endian ',' src_register ',' number ',' number;\nerir_instruction: store_op_code ',' endian ',' src_register ',' program_counter ',' src_register;\nerid_instruction: store_op_code ',' endian ',' src_register ',' program_counter ',' PairRegister;\n\ndma_rri_instruction: dma_op_code ',' src_register ',' src_register ',' number;\n\nsynthetic_sugar_instruction\n\t: rrif_instruction\n\t| move_instruction\n\t| neg_instruction\n\t| not_instruction\n\t| jump_instruction\n\t| shortcut_instruction\n\t;\n\nrrif_instruction\n\t: andn_rrif_instruction\n\t| nand_rrif_instruction\n\t| nor_rrif_instruction\n\t| nxor_rrif_instruction\n\t| orn_rrif_instruction\n\t| hash_rrif_instruction\n\t;\nandn_rrif_instruction: ANDN ',' GPRegister ',' src_register ',' number;\nnand_rrif_instruction: NAND ',' GPRegister ',' src_register ',' number;\nnor_rrif_instruction: NOR ',' GPRegister ',' src_register ',' number;\nnxor_rrif_instruction: NXOR ',' GPRegister ',' src_register ',' number;\norn_rrif_instruction: ORN ',' GPRegister ',' src_register ',' number;\nhash_rrif_instruction: HASH ',' GPRegister ',' src_register ',' number;\n\nmove_instruction\n\t: move_ri_instruction\n\t| move_rici_instruction\n\t| move_rr_instruction\n\t| move_rrci_instruction\n\t| move_s_ri_instruction\n\t| move_s_rici_instruction\n\t| move_s_rr_instruction\n\t| move_s_rrci_instruction\n\t| move_u_ri_instruction\n\t| move_u_rici_instruction\n\t| move_u_rr_instruction\n\t| move_u_rrci_instruction\n\t;\nmove_ri_instruction: MOVE ',' GPRegister ',' program_counter;\nmove_rici_instruction: MOVE ',' GPRegister ',' number ',' condition ',' program_counter;\nmove_rr_instruction: MOVE ',' GPRegister ',' src_register;\nmove_rrci_instruction: MOVE ',' GPRegister ',' src_register ',' condition ',' program_counter;\nmove_s_ri_instruction: MOVE S_SUFFIX ',' PairRegister ',' number;\nmove_s_rici_instruction: MOVE S_SUFFIX ',' PairRegister ',' number ',' condition ',' program_counter;\nmove_s_rr_instruction: MOVE S_SUFFIX ',' PairRegister ',' src_register;\nmove_s_rrci_instruction: MOVE S_SUFFIX ',' PairRegister ',' src_register ',' condition ',' program_counter;\nmove_u_ri_instruction: MOVE U_SUFFIX ',' PairRegister ',' number;\nmove_u_rici_instruction: MOVE U_SUFFIX ',' PairRegister ',' number ',' condition ',' program_counter;\nmove_u_rr_instruction: MOVE U_SUFFIX ',' PairRegister ',' src_register;\nmove_u_rrci_instruction: MOVE U_SUFFIX ',' PairRegister ',' src_register ',' condition ',' program_counter;\n\nneg_instruction\n\t: neg_rr_instruction\n\t| neg_rrci_instruction\n\t;\nneg_rr_instruction: NEG ',' GPRegister ',' src_register;\nneg_rrci_instruction: NEG ',' GPRegister ',' src_register ',' condition ',' program_counter;\n\nnot_instruction\n\t: not_rr_instruction\n\t| not_rrci_instruction\n\t| not_zrci_instruction\n\t;\nnot_rr_instruction: NOT ',' GPRegister ',' src_register;\nnot_rrci_instruction: NOT ',' GPRegister ',' src_register ',' condition ',' program_counter;\nnot_zrci_instruction: NOT ',' src_register ',' condition ',' program_counter;\n\njump_instruction\n\t: jeq_rii_instruction\n\t| jeq_rri_instruction\n\t| jneq_rii_instruction\n\t| jneq_rri_instruction\n\t| jz_ri_instruction\n\t| jnz_ri_instruction\n\t| jltu_rii_instruction\n\t| jltu_rri_instruction\n\t| jgtu_rii_instruction\n\t| jgtu_rri_instruction\n\t| jleu_rii_instruction\n\t| jleu_rri_instruction\n\t| jgeu_rii_instruction\n\t| jgeu_rri_instruction\n\t| jlts_rii_instruction\n\t| jlts_rri_instruction\n\t| jgts_rii_instruction\n\t| jgts_rri_instruction\n\t| jles_rii_instruction\n\t| jles_rri_instruction\n\t| jges_rii_instruction\n\t| jges_rri_instruction\n\t| jump_ri_instruction\n\t| jump_i_instruction\n\t| jump_r_instruction\n\t;\njeq_rii_instruction: JEQ ',' src_register ',' program_counter ',' program_counter;\njeq_rri_instruction: JEQ ',' src_register ',' src_register ',' program_counter;\njneq_rii_instruction: JNEQ ',' src_register ',' number ',' program_counter;\njneq_rri_instruction: JNEQ ',' src_register ',' src_register ',' program_counter;\njz_ri_instruction: JZ ',' src_register ',' program_counter;\njnz_ri_instruction: JNZ ',' src_register ',' program_counter;\njltu_rii_instruction: JLTU ',' src_register ',' number ',' program_counter;\njltu_rri_instruction: JLTU ',' src_register ',' src_register ',' program_counter;\njgtu_rii_instruction: JGTU ',' src_register ',' number ',' program_counter;\njgtu_rri_instruction: JGTU ',' src_register ',' src_register ',' program_counter;\njleu_rii_instruction: JLEU ',' src_register ',' number ',' program_counter;\njleu_rri_instruction: JLEU ',' src_register ',' src_register ',' program_counter;\njgeu_rii_instruction: JGEU ',' src_register ',' number ',' program_counter;\njgeu_rri_instruction: JGEU ',' src_register ',' src_register ',' program_counter;\njlts_rii_instruction: JLTS ',' src_register ',' number ',' program_counter;\njlts_rri_instruction: JLTS ',' src_register ',' src_register ',' program_counter;\njgts_rii_instruction: JGTS ',' src_register ',' number ',' program_counter;\njgts_rri_instruction: JGTS ',' src_register ',' src_register ',' program_counter;\njles_rii_instruction: JLES ',' src_register ',' number ',' program_counter;\njles_rri_instruction: JLES ',' src_register ',' src_register ',' program_counter;\njges_rii_instruction: JGES ',' src_register ',' number ',' program_counter;\njges_rri_instruction: JGES ',' src_register ',' src_register ',' program_counter;\njump_ri_instruction: JUMP ',' src_register ',' program_counter;\njump_i_instruction: JUMP ',' program_counter;\njump_r_instruction: JUMP ',' src_register;\n\nshortcut_instruction\n\t: div_step_drdici_instruction\n\t| mul_step_drdici_instruction\n\t| boot_rici_instruction\n\t| resume_rici_instruction\n\t| stop_ci_instruction\n\t| call_ri_instruction\n\t| call_rr_instruction\n\t| bkp_instruction\n\t| movd_ddci_instruction\n\t| swapd_ddci_instruction\n\t| time_cfg_zr_instruction\n\t| lbs_erri_instruction\n\t| lbs_s_erri_instruction\n\t| lbu_erri_instruction\n\t| lbu_u_erri_instruction\n\t| ld_edri_instruction\n\t| lhs_erri_instruction\n\t| lhs_s_erri_instruction\n\t| lhu_erri_instruction\n\t| lhu_u_erri_instruction\n\t| lw_erri_instruction\n\t| lw_s_erri_instruction\n\t| lw_u_erri_instruction\n\t| sb_erii_instruction\n\t| sb_erir_instruction\n\t| sb_id_rii_instruction\n\t| sb_id_ri_instruction\n\t| sd_erii_instruction\n\t| sd_erid_instruction\n\t| sd_id_rii_instruction\n\t| sd_id_ri_instruction\n\t| sh_erii_instruction\n\t| sh_erir_instruction\n\t| sh_id_rii_instruction\n\t| sh_id_ri_instruction\n\t| sw_erii_instruction\n\t| sw_erir_instruction\n\t| sw_id_rii_instruction\n\t| sw_id_ri_instruction\n\t;\ndiv_step_drdici_instruction: DIV_STEP ',' PairRegister ',' src_register ',' PairRegister ',' number;\nmul_step_drdici_instruction: MUL_STEP ',' PairRegister ',' src_register ',' PairRegister ',' number;\nboot_rici_instruction: BOOT ',' src_register ',' number;\nresume_rici_instruction: RESUME ',' src_register ',' number;\nstop_ci_instruction: STOP ',';\ncall_ri_instruction: CALL ',' GPRegister ',' program_counter;\ncall_rr_instruction: CALL ',' GPRegister ',' src_register;\nbkp_instruction: BKP ',';\nmovd_ddci_instruction: MOVD ',' PairRegister ',' PairRegister;\nswapd_ddci_instruction: SWAPD ',' PairRegister ',' PairRegister;\ntime_cfg_zr_instruction: TIME_CFG ',' src_register;\nlbs_erri_instruction: LBS ',' GPRegister ',' src_register ',' program_counter;\nlbs_s_erri_instruction: LBS S_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nlbu_erri_instruction: LBU ',' GPRegister ',' src_register ',' program_counter;\nlbu_u_erri_instruction: LBU U_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nld_edri_instruction: LD ',' PairRegister ',' src_register ',' program_counter;\nlhs_erri_instruction: LHS ',' GPRegister ',' src_register ',' program_counter;\nlhs_s_erri_instruction: LHS S_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nlhu_erri_instruction: LHU ',' GPRegister ',' src_register ',' program_counter;\nlhu_u_erri_instruction: LHU U_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nlw_erri_instruction: LW ',' GPRegister ',' src_register ',' program_counter;\nlw_s_erri_instruction: LW S_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nlw_u_erri_instruction: LW U_SUFFIX ',' PairRegister ',' src_register ',' program_counter;\nsb_erii_instruction: SB ',' src_register ',' number ',' program_counter;\nsb_erir_instruction: SB ',' src_register ',' program_counter ',' src_register;\nsb_id_rii_instruction: SB ',' src_register ',' number ',' number;\nsb_id_ri_instruction: SB ',' src_register ',' number;\nsd_erii_instruction: SD ',' src_register ',' program_counter ',' program_counter;\nsd_erid_instruction: SD ',' src_register ',' program_counter ',' PairRegister;\nsd_id_rii_instruction: SD ',' src_register ',' number ',' number;\nsd_id_ri_instruction: SD ',' src_register ',' number;\nsh_erii_instruction: SH ',' src_register ',' number ',' program_counter;\nsh_erir_instruction: SH ',' src_register ',' program_counter ',' src_register;\nsh_id_rii_instruction: SH ',' src_register ',' number ',' number;\nsh_id_ri_instruction: SH ',' src_register ',' number;\nsw_erii_instruction: SW ',' src_register ',' number ',' program_counter;\nsw_erir_instruction: SW ',' src_register ',' program_counter ',' src_register;\nsw_id_rii_instruction: SW ',' src_register ',' number ',' number;\nsw_id_ri_instruction: SW ',' src_register ',' number;\n\nlabel: Identifier ':';\n\nCOMMENT: '//' ~[\\n\\r]* -> skip;\nWHITE_SPACE: [ \\n\\t\\r]+ -> skip;\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assembly.interp",
    "content": "token literal names:\nnull\n'-'\n'0x'\n'+'\n','\n':'\n'$acquire'\n'$release'\n'$boot'\n'$resume'\n'$add'\n'$addc'\n'$and'\n'$andn'\n'$asr'\n'$cmpb4'\n'$lsl'\n'$lsl1'\n'$lsl1x'\n'$lslx'\n'$lsr'\n'$lsr1'\n'$lsr1x'\n'$lsrx'\n'$mul_sh_sh'\n'$mul_sh_sl'\n'$mul_sh_uh'\n'$mul_sh_ul'\n'$mul_sl_sh'\n'$mul_sl_sl'\n'$mul_sl_uh'\n'$mul_sl_ul'\n'$mul_uh_uh'\n'$mul_uh_ul'\n'$mul_ul_uh'\n'$mul_ul_ul'\n'$nand'\n'$nor'\n'$nxor'\n'$or'\n'$orn'\n'$rol'\n'$ror'\n'$rsub'\n'$rsubc'\n'$sub'\n'$subc'\n'$xor'\n'$call'\n'$hash'\n'$cao'\n'$clo'\n'$cls'\n'$clz'\n'$extsb'\n'$extsh'\n'$extub'\n'$extuh'\n'$sats'\n'$time_cfg'\n'$div_step'\n'$mul_step'\n'$lsl_add'\n'$lsl_sub'\n'$lsr_add'\n'$rol_add'\n'$ror_add'\n'$time'\n'$nop'\n'$stop'\n'$fault'\n'$movd'\n'$swapd'\n'$lbs'\n'$lbu'\n'$ld'\n'$lhs'\n'$lhu'\n'$lw'\n'$sb'\n'$sb_id'\n'$sd'\n'$sd_id'\n'$sh'\n'$sh_id'\n'$sw'\n'$sw_id'\n'$ldma'\n'$ldmai'\n'$sdma'\n'$move'\n'$neg'\n'$not'\n'$bkp'\n'$jeq'\n'$jneq'\n'$jz'\n'$jnz'\n'$jltu'\n'$jgtu'\n'$jleu'\n'$jgeu'\n'$jlts'\n'$jgts'\n'$jles'\n'$jges'\n'$jump'\n'%atomic'\n'%bss'\n'%data'\n'%debug_abbrev'\n'%debug_frame'\n'%debug_info'\n'%debug_line'\n'%debug_loc'\n'%debug_ranges'\n'%debug_str'\n'%dpu_host'\n'%mram'\n'%rodata'\n'%stack_sizes'\n'%text'\n'@progbits'\n'@nobits'\n'@function'\n'@object'\n'true'\n'false'\n'z'\n'nz'\n'e'\n'o'\n'pl'\n'mi'\n'ov'\n'nov'\n'c'\n'nc'\n'sz'\n'snz'\n'spl'\n'smi'\n'so'\n'se'\n'nc5'\n'nc6'\n'nc7'\n'nc8'\n'nc9'\n'nc10'\n'nc11'\n'nc12'\n'nc13'\n'nc14'\n'max'\n'nmax'\n'sh32'\n'nsh32'\n'eq'\n'neq'\n'ltu'\n'leu'\n'gtu'\n'geu'\n'lts'\n'les'\n'gts'\n'ges'\n'xz'\n'xnz'\n'xleu'\n'xgtu'\n'xles'\n'xgts'\n'small'\n'large'\n'!little'\n'!big'\n'zero'\n'one'\n'id'\n'id2'\n'id4'\n'id8'\n'lneg'\n'mneg'\n'$addrsig'\n'$addrsig_sym'\n'$ascii'\n'$asciz'\n'$byte'\n'$cfi_def_cfa_offset'\n'$cfi_endproc'\n'$cfi_offset'\n'$cfi_sections'\n'$cfi_startproc'\n'$file'\n'$globl'\n'$loc'\n'$long'\n'$p2align'\n'$quad'\n'$section'\n'$set'\n'$short'\n'$size'\n'$text'\n'$type'\n'$weak'\n'$zero'\n'is_stmt'\n'prologue_end'\n'.s'\n'.u'\nnull\nnull\nnull\nnull\nnull\nnull\nnull\n\ntoken symbolic names:\nnull\nnull\nnull\nnull\nnull\nnull\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nrule names:\ndocument\nnegative_number\nhex_number\nnumber\nrici_op_code\nrri_op_code\nrr_op_code\ndrdici_op_code\nrrri_op_code\nr_op_code\nci_op_code\ni_op_code\nddci_op_code\nload_op_code\nstore_op_code\ndma_op_code\nsection_name\nsection_types\nsymbol_type\ncondition\nendian\nsp_register\nsrc_register\nprogram_counter\nadd_expression\nsub_expression\nprimary_expression\ndirective\naddrsig_directive\naddrsig_sym_directive\nascii_directive\nasciz_directive\nbyte_directive\ncfi_def_cfa_offset_directive\ncfi_endproc_directive\ncfi_offset_directive\ncfi_sections_directive\ncfi_startproc_directive\nfile_directive\nglobal_directive\nloc_directive\nlong_directive\np2align_directive\nquad_directive\nsection_directive\nset_directive\nshort_directive\nsize_directive\nstack_sizes_directive\ntext_directive\ntype_directive\nweak_directive\nzero_directive\ninstruction\nrici_instruction\nrri_instruction\nrric_instruction\nrrici_instruction\nrrr_instruction\nrrrc_instruction\nrrrci_instruction\nzri_instruction\nzric_instruction\nzrici_instruction\nzrr_instruction\nzrrc_instruction\nzrrci_instruction\ns_rri_instruction\ns_rric_instruction\ns_rrici_instruction\ns_rrr_instruction\ns_rrrc_instruction\ns_rrrci_instruction\nu_rri_instruction\nu_rric_instruction\nu_rrici_instruction\nu_rrr_instruction\nu_rrrc_instruction\nu_rrrci_instruction\nrr_instruction\nrrc_instruction\nrrci_instruction\nzr_instruction\nzrc_instruction\nzrci_instruction\ns_rr_instruction\ns_rrc_instruction\ns_rrci_instruction\nu_rr_instruction\nu_rrc_instruction\nu_rrci_instruction\ndrdici_instruction\nrrri_instruction\nrrrici_instruction\nzrri_instruction\nzrrici_instruction\ns_rrri_instruction\ns_rrrici_instruction\nu_rrri_instruction\nu_rrrici_instruction\nrir_instruction\nrirc_instruction\nrirci_instruction\nzir_instruction\nzirc_instruction\nzirci_instruction\ns_rirc_instruction\ns_rirci_instruction\nu_rirc_instruction\nu_rirci_instruction\nr_instruction\nrci_instruction\nz_instruction\nzci_instruction\ns_r_instruction\ns_rci_instruction\nu_r_instruction\nu_rci_instruction\nci_instruction\ni_instruction\nddci_instruction\nerri_instruction\nedri_instruction\ns_erri_instruction\nu_erri_instruction\nerii_instruction\nerir_instruction\nerid_instruction\ndma_rri_instruction\nsynthetic_sugar_instruction\nrrif_instruction\nandn_rrif_instruction\nnand_rrif_instruction\nnor_rrif_instruction\nnxor_rrif_instruction\norn_rrif_instruction\nhash_rrif_instruction\nmove_instruction\nmove_ri_instruction\nmove_rici_instruction\nmove_rr_instruction\nmove_rrci_instruction\nmove_s_ri_instruction\nmove_s_rici_instruction\nmove_s_rr_instruction\nmove_s_rrci_instruction\nmove_u_ri_instruction\nmove_u_rici_instruction\nmove_u_rr_instruction\nmove_u_rrci_instruction\nneg_instruction\nneg_rr_instruction\nneg_rrci_instruction\nnot_instruction\nnot_rr_instruction\nnot_rrci_instruction\nnot_zrci_instruction\njump_instruction\njeq_rii_instruction\njeq_rri_instruction\njneq_rii_instruction\njneq_rri_instruction\njz_ri_instruction\njnz_ri_instruction\njltu_rii_instruction\njltu_rri_instruction\njgtu_rii_instruction\njgtu_rri_instruction\njleu_rii_instruction\njleu_rri_instruction\njgeu_rii_instruction\njgeu_rri_instruction\njlts_rii_instruction\njlts_rri_instruction\njgts_rii_instruction\njgts_rri_instruction\njles_rii_instruction\njles_rri_instruction\njges_rii_instruction\njges_rri_instruction\njump_ri_instruction\njump_i_instruction\njump_r_instruction\nshortcut_instruction\ndiv_step_drdici_instruction\nmul_step_drdici_instruction\nboot_rici_instruction\nresume_rici_instruction\nstop_ci_instruction\ncall_ri_instruction\ncall_rr_instruction\nbkp_instruction\nmovd_ddci_instruction\nswapd_ddci_instruction\ntime_cfg_zr_instruction\nlbs_erri_instruction\nlbs_s_erri_instruction\nlbu_erri_instruction\nlbu_u_erri_instruction\nld_edri_instruction\nlhs_erri_instruction\nlhs_s_erri_instruction\nlhu_erri_instruction\nlhu_u_erri_instruction\nlw_erri_instruction\nlw_s_erri_instruction\nlw_u_erri_instruction\nsb_erii_instruction\nsb_erir_instruction\nsb_id_rii_instruction\nsb_id_ri_instruction\nsd_erii_instruction\nsd_erid_instruction\nsd_id_rii_instruction\nsd_id_ri_instruction\nsh_erii_instruction\nsh_erir_instruction\nsh_id_rii_instruction\nsh_id_ri_instruction\nsw_erii_instruction\nsw_erir_instruction\nsw_id_rii_instruction\nsw_id_ri_instruction\nlabel\n\n\natn:\n[3, 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419, 3, 2, 2, 2, 2221, 2222, 7, 81, 2, 2, 2222, 2223, 7, 6, 2, 2, 2223, 2224, 5, 46, 24, 2, 2224, 2225, 7, 6, 2, 2, 2225, 2226, 5, 8, 5, 2, 2226, 2227, 7, 6, 2, 2, 2227, 2228, 5, 8, 5, 2, 2228, 421, 3, 2, 2, 2, 2229, 2230, 7, 81, 2, 2, 2230, 2231, 7, 6, 2, 2, 2231, 2232, 5, 46, 24, 2, 2232, 2233, 7, 6, 2, 2, 2233, 2234, 5, 8, 5, 2, 2234, 423, 3, 2, 2, 2, 2235, 2236, 7, 83, 2, 2, 2236, 2237, 7, 6, 2, 2, 2237, 2238, 5, 46, 24, 2, 2238, 2239, 7, 6, 2, 2, 2239, 2240, 5, 48, 25, 2, 2240, 2241, 7, 6, 2, 2, 2241, 2242, 5, 48, 25, 2, 2242, 425, 3, 2, 2, 2, 2243, 2244, 7, 83, 2, 2, 2244, 2245, 7, 6, 2, 2, 2245, 2246, 5, 46, 24, 2, 2246, 2247, 7, 6, 2, 2, 2247, 2248, 5, 48, 25, 2, 2248, 2249, 7, 6, 2, 2, 2249, 2250, 7, 218, 2, 2, 2250, 427, 3, 2, 2, 2, 2251, 2252, 7, 83, 2, 2, 2252, 2253, 7, 6, 2, 2, 2253, 2254, 5, 46, 24, 2, 2254, 2255, 7, 6, 2, 2, 2255, 2256, 5, 8, 5, 2, 2256, 2257, 7, 6, 2, 2, 2257, 2258, 5, 8, 5, 2, 2258, 429, 3, 2, 2, 2, 2259, 2260, 7, 83, 2, 2, 2260, 2261, 7, 6, 2, 2, 2261, 2262, 5, 46, 24, 2, 2262, 2263, 7, 6, 2, 2, 2263, 2264, 5, 8, 5, 2, 2264, 431, 3, 2, 2, 2, 2265, 2266, 7, 85, 2, 2, 2266, 2267, 7, 6, 2, 2, 2267, 2268, 5, 46, 24, 2, 2268, 2269, 7, 6, 2, 2, 2269, 2270, 5, 8, 5, 2, 2270, 2271, 7, 6, 2, 2, 2271, 2272, 5, 48, 25, 2, 2272, 433, 3, 2, 2, 2, 2273, 2274, 7, 85, 2, 2, 2274, 2275, 7, 6, 2, 2, 2275, 2276, 5, 46, 24, 2, 2276, 2277, 7, 6, 2, 2, 2277, 2278, 5, 48, 25, 2, 2278, 2279, 7, 6, 2, 2, 2279, 2280, 5, 46, 24, 2, 2280, 435, 3, 2, 2, 2, 2281, 2282, 7, 85, 2, 2, 2282, 2283, 7, 6, 2, 2, 2283, 2284, 5, 46, 24, 2, 2284, 2285, 7, 6, 2, 2, 2285, 2286, 5, 8, 5, 2, 2286, 2287, 7, 6, 2, 2, 2287, 2288, 5, 8, 5, 2, 2288, 437, 3, 2, 2, 2, 2289, 2290, 7, 85, 2, 2, 2290, 2291, 7, 6, 2, 2, 2291, 2292, 5, 46, 24, 2, 2292, 2293, 7, 6, 2, 2, 2293, 2294, 5, 8, 5, 2, 2294, 439, 3, 2, 2, 2, 2295, 2296, 7, 87, 2, 2, 2296, 2297, 7, 6, 2, 2, 2297, 2298, 5, 46, 24, 2, 2298, 2299, 7, 6, 2, 2, 2299, 2300, 5, 8, 5, 2, 2300, 2301, 7, 6, 2, 2, 2301, 2302, 5, 48, 25, 2, 2302, 441, 3, 2, 2, 2, 2303, 2304, 7, 87, 2, 2, 2304, 2305, 7, 6, 2, 2, 2305, 2306, 5, 46, 24, 2, 2306, 2307, 7, 6, 2, 2, 2307, 2308, 5, 48, 25, 2, 2308, 2309, 7, 6, 2, 2, 2309, 2310, 5, 46, 24, 2, 2310, 443, 3, 2, 2, 2, 2311, 2312, 7, 87, 2, 2, 2312, 2313, 7, 6, 2, 2, 2313, 2314, 5, 46, 24, 2, 2314, 2315, 7, 6, 2, 2, 2315, 2316, 5, 8, 5, 2, 2316, 2317, 7, 6, 2, 2, 2317, 2318, 5, 8, 5, 2, 2318, 445, 3, 2, 2, 2, 2319, 2320, 7, 87, 2, 2, 2320, 2321, 7, 6, 2, 2, 2321, 2322, 5, 46, 24, 2, 2322, 2323, 7, 6, 2, 2, 2323, 2324, 5, 8, 5, 2, 2324, 447, 3, 2, 2, 2, 2325, 2326, 7, 219, 2, 2, 2326, 2327, 7, 7, 2, 2, 2327, 449, 3, 2, 2, 2, 22, 453, 455, 469, 509, 514, 527, 554, 604, 631, 685, 737, 815, 1414, 1558, 1566, 1628, 1736, 1757, 1808, 2035]"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assembly.tokens",
    "content": "T__0=1\nT__1=2\nT__2=3\nT__3=4\nT__4=5\nACQUIRE=6\nRELEASE=7\nBOOT=8\nRESUME=9\nADD=10\nADDC=11\nAND=12\nANDN=13\nASR=14\nCMPB4=15\nLSL=16\nLSL1=17\nLSL1X=18\nLSLX=19\nLSR=20\nLSR1=21\nLSR1X=22\nLSRX=23\nMUL_SH_SH=24\nMUL_SH_SL=25\nMUL_SH_UH=26\nMUL_SH_UL=27\nMUL_SL_SH=28\nMUL_SL_SL=29\nMUL_SL_UH=30\nMUL_SL_UL=31\nMUL_UH_UH=32\nMUL_UH_UL=33\nMUL_UL_UH=34\nMUL_UL_UL=35\nNAND=36\nNOR=37\nNXOR=38\nOR=39\nORN=40\nROL=41\nROR=42\nRSUB=43\nRSUBC=44\nSUB=45\nSUBC=46\nXOR=47\nCALL=48\nHASH=49\nCAO=50\nCLO=51\nCLS=52\nCLZ=53\nEXTSB=54\nEXTSH=55\nEXTUB=56\nEXTUH=57\nSATS=58\nTIME_CFG=59\nDIV_STEP=60\nMUL_STEP=61\nLSL_ADD=62\nLSL_SUB=63\nLSR_ADD=64\nROL_ADD=65\nROR_ADD=66\nTIME=67\nNOP=68\nSTOP=69\nFAULT=70\nMOVD=71\nSWAPD=72\nLBS=73\nLBU=74\nLD=75\nLHS=76\nLHU=77\nLW=78\nSB=79\nSB_ID=80\nSD=81\nSD_ID=82\nSH=83\nSH_ID=84\nSW=85\nSW_ID=86\nLDMA=87\nLDMAI=88\nSDMA=89\nMOVE=90\nNEG=91\nNOT=92\nBKP=93\nJEQ=94\nJNEQ=95\nJZ=96\nJNZ=97\nJLTU=98\nJGTU=99\nJLEU=100\nJGEU=101\nJLTS=102\nJGTS=103\nJLES=104\nJGES=105\nJUMP=106\nATOMIC=107\nBSS=108\nDATA=109\nDEBUG_ABBREV=110\nDEBUG_FRAME=111\nDEBUG_INFO=112\nDEBUG_LINE=113\nDEBUG_LOC=114\nDEBUG_RANGES=115\nDEBUG_STR=116\nDPU_HOST=117\nMRAM=118\nRODATA=119\nSTACK_SIZES=120\nTEXT_SECTION=121\nPROGBITS=122\nNOBITS=123\nFUNCTION=124\nOBJECT=125\nTRUE=126\nFALSE=127\nZ=128\nNZ=129\nE=130\nO=131\nPL=132\nMI=133\nOV=134\nNOV=135\nC=136\nNC=137\nSZ=138\nSNZ=139\nSPL=140\nSMI=141\nSO=142\nSE=143\nNC5=144\nNC6=145\nNC7=146\nNC8=147\nNC9=148\nNC10=149\nNC11=150\nNC12=151\nNC13=152\nNC14=153\nMAX=154\nNMAX=155\nSH32=156\nNSH32=157\nEQ=158\nNEQ=159\nLTU=160\nLEU=161\nGTU=162\nGEU=163\nLTS=164\nLES=165\nGTS=166\nGES=167\nXZ=168\nXNZ=169\nXLEU=170\nXGTU=171\nXLES=172\nXGTS=173\nSMALL=174\nLARGE=175\nLITTLE=176\nBIG=177\nZERO_REGISTER=178\nONE=179\nID=180\nID2=181\nID4=182\nID8=183\nLNEG=184\nMNEG=185\nADDRSIG=186\nADDRSIG_SYM=187\nASCII=188\nASCIZ=189\nBYTE=190\nCFI_DEF_CFA_OFFSET=191\nCFI_ENDPROC=192\nCFI_OFFSET=193\nCFI_SECTIONS=194\nCFI_STARTPROC=195\nFILE=196\nGLOBL=197\nLOC=198\nLONG=199\nP2ALIGN=200\nQUAD=201\nSECTION=202\nSET=203\nSHORT=204\nSIZE=205\nTEXT_DIRECTIVE=206\nTYPE=207\nWEAK=208\nZERO_DIRECTIVE=209\nIS_STMT=210\nPROLOGUE_END=211\nS_SUFFIX=212\nU_SUFFIX=213\nPositiveNumber=214\nGPRegister=215\nPairRegister=216\nIdentifier=217\nStringLiteral=218\nCOMMENT=219\nWHITE_SPACE=220\n'-'=1\n'0x'=2\n'+'=3\n','=4\n':'=5\n'$acquire'=6\n'$release'=7\n'$boot'=8\n'$resume'=9\n'$add'=10\n'$addc'=11\n'$and'=12\n'$andn'=13\n'$asr'=14\n'$cmpb4'=15\n'$lsl'=16\n'$lsl1'=17\n'$lsl1x'=18\n'$lslx'=19\n'$lsr'=20\n'$lsr1'=21\n'$lsr1x'=22\n'$lsrx'=23\n'$mul_sh_sh'=24\n'$mul_sh_sl'=25\n'$mul_sh_uh'=26\n'$mul_sh_ul'=27\n'$mul_sl_sh'=28\n'$mul_sl_sl'=29\n'$mul_sl_uh'=30\n'$mul_sl_ul'=31\n'$mul_uh_uh'=32\n'$mul_uh_ul'=33\n'$mul_ul_uh'=34\n'$mul_ul_ul'=35\n'$nand'=36\n'$nor'=37\n'$nxor'=38\n'$or'=39\n'$orn'=40\n'$rol'=41\n'$ror'=42\n'$rsub'=43\n'$rsubc'=44\n'$sub'=45\n'$subc'=46\n'$xor'=47\n'$call'=48\n'$hash'=49\n'$cao'=50\n'$clo'=51\n'$cls'=52\n'$clz'=53\n'$extsb'=54\n'$extsh'=55\n'$extub'=56\n'$extuh'=57\n'$sats'=58\n'$time_cfg'=59\n'$div_step'=60\n'$mul_step'=61\n'$lsl_add'=62\n'$lsl_sub'=63\n'$lsr_add'=64\n'$rol_add'=65\n'$ror_add'=66\n'$time'=67\n'$nop'=68\n'$stop'=69\n'$fault'=70\n'$movd'=71\n'$swapd'=72\n'$lbs'=73\n'$lbu'=74\n'$ld'=75\n'$lhs'=76\n'$lhu'=77\n'$lw'=78\n'$sb'=79\n'$sb_id'=80\n'$sd'=81\n'$sd_id'=82\n'$sh'=83\n'$sh_id'=84\n'$sw'=85\n'$sw_id'=86\n'$ldma'=87\n'$ldmai'=88\n'$sdma'=89\n'$move'=90\n'$neg'=91\n'$not'=92\n'$bkp'=93\n'$jeq'=94\n'$jneq'=95\n'$jz'=96\n'$jnz'=97\n'$jltu'=98\n'$jgtu'=99\n'$jleu'=100\n'$jgeu'=101\n'$jlts'=102\n'$jgts'=103\n'$jles'=104\n'$jges'=105\n'$jump'=106\n'%atomic'=107\n'%bss'=108\n'%data'=109\n'%debug_abbrev'=110\n'%debug_frame'=111\n'%debug_info'=112\n'%debug_line'=113\n'%debug_loc'=114\n'%debug_ranges'=115\n'%debug_str'=116\n'%dpu_host'=117\n'%mram'=118\n'%rodata'=119\n'%stack_sizes'=120\n'%text'=121\n'@progbits'=122\n'@nobits'=123\n'@function'=124\n'@object'=125\n'true'=126\n'false'=127\n'z'=128\n'nz'=129\n'e'=130\n'o'=131\n'pl'=132\n'mi'=133\n'ov'=134\n'nov'=135\n'c'=136\n'nc'=137\n'sz'=138\n'snz'=139\n'spl'=140\n'smi'=141\n'so'=142\n'se'=143\n'nc5'=144\n'nc6'=145\n'nc7'=146\n'nc8'=147\n'nc9'=148\n'nc10'=149\n'nc11'=150\n'nc12'=151\n'nc13'=152\n'nc14'=153\n'max'=154\n'nmax'=155\n'sh32'=156\n'nsh32'=157\n'eq'=158\n'neq'=159\n'ltu'=160\n'leu'=161\n'gtu'=162\n'geu'=163\n'lts'=164\n'les'=165\n'gts'=166\n'ges'=167\n'xz'=168\n'xnz'=169\n'xleu'=170\n'xgtu'=171\n'xles'=172\n'xgts'=173\n'small'=174\n'large'=175\n'!little'=176\n'!big'=177\n'zero'=178\n'one'=179\n'id'=180\n'id2'=181\n'id4'=182\n'id8'=183\n'lneg'=184\n'mneg'=185\n'$addrsig'=186\n'$addrsig_sym'=187\n'$ascii'=188\n'$asciz'=189\n'$byte'=190\n'$cfi_def_cfa_offset'=191\n'$cfi_endproc'=192\n'$cfi_offset'=193\n'$cfi_sections'=194\n'$cfi_startproc'=195\n'$file'=196\n'$globl'=197\n'$loc'=198\n'$long'=199\n'$p2align'=200\n'$quad'=201\n'$section'=202\n'$set'=203\n'$short'=204\n'$size'=205\n'$text'=206\n'$type'=207\n'$weak'=208\n'$zero'=209\n'is_stmt'=210\n'prologue_end'=211\n'.s'=212\n'.u'=213\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assemblyLexer.interp",
    "content": "token literal names:\nnull\n'-'\n'0x'\n'+'\n','\n':'\n'$acquire'\n'$release'\n'$boot'\n'$resume'\n'$add'\n'$addc'\n'$and'\n'$andn'\n'$asr'\n'$cmpb4'\n'$lsl'\n'$lsl1'\n'$lsl1x'\n'$lslx'\n'$lsr'\n'$lsr1'\n'$lsr1x'\n'$lsrx'\n'$mul_sh_sh'\n'$mul_sh_sl'\n'$mul_sh_uh'\n'$mul_sh_ul'\n'$mul_sl_sh'\n'$mul_sl_sl'\n'$mul_sl_uh'\n'$mul_sl_ul'\n'$mul_uh_uh'\n'$mul_uh_ul'\n'$mul_ul_uh'\n'$mul_ul_ul'\n'$nand'\n'$nor'\n'$nxor'\n'$or'\n'$orn'\n'$rol'\n'$ror'\n'$rsub'\n'$rsubc'\n'$sub'\n'$subc'\n'$xor'\n'$call'\n'$hash'\n'$cao'\n'$clo'\n'$cls'\n'$clz'\n'$extsb'\n'$extsh'\n'$extub'\n'$extuh'\n'$sats'\n'$time_cfg'\n'$div_step'\n'$mul_step'\n'$lsl_add'\n'$lsl_sub'\n'$lsr_add'\n'$rol_add'\n'$ror_add'\n'$time'\n'$nop'\n'$stop'\n'$fault'\n'$movd'\n'$swapd'\n'$lbs'\n'$lbu'\n'$ld'\n'$lhs'\n'$lhu'\n'$lw'\n'$sb'\n'$sb_id'\n'$sd'\n'$sd_id'\n'$sh'\n'$sh_id'\n'$sw'\n'$sw_id'\n'$ldma'\n'$ldmai'\n'$sdma'\n'$move'\n'$neg'\n'$not'\n'$bkp'\n'$jeq'\n'$jneq'\n'$jz'\n'$jnz'\n'$jltu'\n'$jgtu'\n'$jleu'\n'$jgeu'\n'$jlts'\n'$jgts'\n'$jles'\n'$jges'\n'$jump'\n'%atomic'\n'%bss'\n'%data'\n'%debug_abbrev'\n'%debug_frame'\n'%debug_info'\n'%debug_line'\n'%debug_loc'\n'%debug_ranges'\n'%debug_str'\n'%dpu_host'\n'%mram'\n'%rodata'\n'%stack_sizes'\n'%text'\n'@progbits'\n'@nobits'\n'@function'\n'@object'\n'true'\n'false'\n'z'\n'nz'\n'e'\n'o'\n'pl'\n'mi'\n'ov'\n'nov'\n'c'\n'nc'\n'sz'\n'snz'\n'spl'\n'smi'\n'so'\n'se'\n'nc5'\n'nc6'\n'nc7'\n'nc8'\n'nc9'\n'nc10'\n'nc11'\n'nc12'\n'nc13'\n'nc14'\n'max'\n'nmax'\n'sh32'\n'nsh32'\n'eq'\n'neq'\n'ltu'\n'leu'\n'gtu'\n'geu'\n'lts'\n'les'\n'gts'\n'ges'\n'xz'\n'xnz'\n'xleu'\n'xgtu'\n'xles'\n'xgts'\n'small'\n'large'\n'!little'\n'!big'\n'zero'\n'one'\n'id'\n'id2'\n'id4'\n'id8'\n'lneg'\n'mneg'\n'$addrsig'\n'$addrsig_sym'\n'$ascii'\n'$asciz'\n'$byte'\n'$cfi_def_cfa_offset'\n'$cfi_endproc'\n'$cfi_offset'\n'$cfi_sections'\n'$cfi_startproc'\n'$file'\n'$globl'\n'$loc'\n'$long'\n'$p2align'\n'$quad'\n'$section'\n'$set'\n'$short'\n'$size'\n'$text'\n'$type'\n'$weak'\n'$zero'\n'is_stmt'\n'prologue_end'\n'.s'\n'.u'\nnull\nnull\nnull\nnull\nnull\nnull\nnull\n\ntoken symbolic names:\nnull\nnull\nnull\nnull\nnull\nnull\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nrule names:\nT__0\nT__1\nT__2\nT__3\nT__4\nACQUIRE\nRELEASE\nBOOT\nRESUME\nADD\nADDC\nAND\nANDN\nASR\nCMPB4\nLSL\nLSL1\nLSL1X\nLSLX\nLSR\nLSR1\nLSR1X\nLSRX\nMUL_SH_SH\nMUL_SH_SL\nMUL_SH_UH\nMUL_SH_UL\nMUL_SL_SH\nMUL_SL_SL\nMUL_SL_UH\nMUL_SL_UL\nMUL_UH_UH\nMUL_UH_UL\nMUL_UL_UH\nMUL_UL_UL\nNAND\nNOR\nNXOR\nOR\nORN\nROL\nROR\nRSUB\nRSUBC\nSUB\nSUBC\nXOR\nCALL\nHASH\nCAO\nCLO\nCLS\nCLZ\nEXTSB\nEXTSH\nEXTUB\nEXTUH\nSATS\nTIME_CFG\nDIV_STEP\nMUL_STEP\nLSL_ADD\nLSL_SUB\nLSR_ADD\nROL_ADD\nROR_ADD\nTIME\nNOP\nSTOP\nFAULT\nMOVD\nSWAPD\nLBS\nLBU\nLD\nLHS\nLHU\nLW\nSB\nSB_ID\nSD\nSD_ID\nSH\nSH_ID\nSW\nSW_ID\nLDMA\nLDMAI\nSDMA\nMOVE\nNEG\nNOT\nBKP\nJEQ\nJNEQ\nJZ\nJNZ\nJLTU\nJGTU\nJLEU\nJGEU\nJLTS\nJGTS\nJLES\nJGES\nJUMP\nATOMIC\nBSS\nDATA\nDEBUG_ABBREV\nDEBUG_FRAME\nDEBUG_INFO\nDEBUG_LINE\nDEBUG_LOC\nDEBUG_RANGES\nDEBUG_STR\nDPU_HOST\nMRAM\nRODATA\nSTACK_SIZES\nTEXT_SECTION\nPROGBITS\nNOBITS\nFUNCTION\nOBJECT\nTRUE\nFALSE\nZ\nNZ\nE\nO\nPL\nMI\nOV\nNOV\nC\nNC\nSZ\nSNZ\nSPL\nSMI\nSO\nSE\nNC5\nNC6\nNC7\nNC8\nNC9\nNC10\nNC11\nNC12\nNC13\nNC14\nMAX\nNMAX\nSH32\nNSH32\nEQ\nNEQ\nLTU\nLEU\nGTU\nGEU\nLTS\nLES\nGTS\nGES\nXZ\nXNZ\nXLEU\nXGTU\nXLES\nXGTS\nSMALL\nLARGE\nLITTLE\nBIG\nZERO_REGISTER\nONE\nID\nID2\nID4\nID8\nLNEG\nMNEG\nADDRSIG\nADDRSIG_SYM\nASCII\nASCIZ\nBYTE\nCFI_DEF_CFA_OFFSET\nCFI_ENDPROC\nCFI_OFFSET\nCFI_SECTIONS\nCFI_STARTPROC\nFILE\nGLOBL\nLOC\nLONG\nP2ALIGN\nQUAD\nSECTION\nSET\nSHORT\nSIZE\nTEXT_DIRECTIVE\nTYPE\nWEAK\nZERO_DIRECTIVE\nIS_STMT\nPROLOGUE_END\nS_SUFFIX\nU_SUFFIX\nPositiveNumber\nGPRegister\nPairRegister\nIdentifier\nStringLiteral\nCOMMENT\nWHITE_SPACE\n\nchannel names:\nDEFAULT_TOKEN_CHANNEL\nHIDDEN\n\nmode names:\nDEFAULT_MODE\n\natn:\n[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 222, 1850, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 4, 24, 9, 24, 4, 25, 9, 25, 4, 26, 9, 26, 4, 27, 9, 27, 4, 28, 9, 28, 4, 29, 9, 29, 4, 30, 9, 30, 4, 31, 9, 31, 4, 32, 9, 32, 4, 33, 9, 33, 4, 34, 9, 34, 4, 35, 9, 35, 4, 36, 9, 36, 4, 37, 9, 37, 4, 38, 9, 38, 4, 39, 9, 39, 4, 40, 9, 40, 4, 41, 9, 41, 4, 42, 9, 42, 4, 43, 9, 43, 4, 44, 9, 44, 4, 45, 9, 45, 4, 46, 9, 46, 4, 47, 9, 47, 4, 48, 9, 48, 4, 49, 9, 49, 4, 50, 9, 50, 4, 51, 9, 51, 4, 52, 9, 52, 4, 53, 9, 53, 4, 54, 9, 54, 4, 55, 9, 55, 4, 56, 9, 56, 4, 57, 9, 57, 4, 58, 9, 58, 4, 59, 9, 59, 4, 60, 9, 60, 4, 61, 9, 61, 4, 62, 9, 62, 4, 63, 9, 63, 4, 64, 9, 64, 4, 65, 9, 65, 4, 66, 9, 66, 4, 67, 9, 67, 4, 68, 9, 68, 4, 69, 9, 69, 4, 70, 9, 70, 4, 71, 9, 71, 4, 72, 9, 72, 4, 73, 9, 73, 4, 74, 9, 74, 4, 75, 9, 75, 4, 76, 9, 76, 4, 77, 9, 77, 4, 78, 9, 78, 4, 79, 9, 79, 4, 80, 9, 80, 4, 81, 9, 81, 4, 82, 9, 82, 4, 83, 9, 83, 4, 84, 9, 84, 4, 85, 9, 85, 4, 86, 9, 86, 4, 87, 9, 87, 4, 88, 9, 88, 4, 89, 9, 89, 4, 90, 9, 90, 4, 91, 9, 91, 4, 92, 9, 92, 4, 93, 9, 93, 4, 94, 9, 94, 4, 95, 9, 95, 4, 96, 9, 96, 4, 97, 9, 97, 4, 98, 9, 98, 4, 99, 9, 99, 4, 100, 9, 100, 4, 101, 9, 101, 4, 102, 9, 102, 4, 103, 9, 103, 4, 104, 9, 104, 4, 105, 9, 105, 4, 106, 9, 106, 4, 107, 9, 107, 4, 108, 9, 108, 4, 109, 9, 109, 4, 110, 9, 110, 4, 111, 9, 111, 4, 112, 9, 112, 4, 113, 9, 113, 4, 114, 9, 114, 4, 115, 9, 115, 4, 116, 9, 116, 4, 117, 9, 117, 4, 118, 9, 118, 4, 119, 9, 119, 4, 120, 9, 120, 4, 121, 9, 121, 4, 122, 9, 122, 4, 123, 9, 123, 4, 124, 9, 124, 4, 125, 9, 125, 4, 126, 9, 126, 4, 127, 9, 127, 4, 128, 9, 128, 4, 129, 9, 129, 4, 130, 9, 130, 4, 131, 9, 131, 4, 132, 9, 132, 4, 133, 9, 133, 4, 134, 9, 134, 4, 135, 9, 135, 4, 136, 9, 136, 4, 137, 9, 137, 4, 138, 9, 138, 4, 139, 9, 139, 4, 140, 9, 140, 4, 141, 9, 141, 4, 142, 9, 142, 4, 143, 9, 143, 4, 144, 9, 144, 4, 145, 9, 145, 4, 146, 9, 146, 4, 147, 9, 147, 4, 148, 9, 148, 4, 149, 9, 149, 4, 150, 9, 150, 4, 151, 9, 151, 4, 152, 9, 152, 4, 153, 9, 153, 4, 154, 9, 154, 4, 155, 9, 155, 4, 156, 9, 156, 4, 157, 9, 157, 4, 158, 9, 158, 4, 159, 9, 159, 4, 160, 9, 160, 4, 161, 9, 161, 4, 162, 9, 162, 4, 163, 9, 163, 4, 164, 9, 164, 4, 165, 9, 165, 4, 166, 9, 166, 4, 167, 9, 167, 4, 168, 9, 168, 4, 169, 9, 169, 4, 170, 9, 170, 4, 171, 9, 171, 4, 172, 9, 172, 4, 173, 9, 173, 4, 174, 9, 174, 4, 175, 9, 175, 4, 176, 9, 176, 4, 177, 9, 177, 4, 178, 9, 178, 4, 179, 9, 179, 4, 180, 9, 180, 4, 181, 9, 181, 4, 182, 9, 182, 4, 183, 9, 183, 4, 184, 9, 184, 4, 185, 9, 185, 4, 186, 9, 186, 4, 187, 9, 187, 4, 188, 9, 188, 4, 189, 9, 189, 4, 190, 9, 190, 4, 191, 9, 191, 4, 192, 9, 192, 4, 193, 9, 193, 4, 194, 9, 194, 4, 195, 9, 195, 4, 196, 9, 196, 4, 197, 9, 197, 4, 198, 9, 198, 4, 199, 9, 199, 4, 200, 9, 200, 4, 201, 9, 201, 4, 202, 9, 202, 4, 203, 9, 203, 4, 204, 9, 204, 4, 205, 9, 205, 4, 206, 9, 206, 4, 207, 9, 207, 4, 208, 9, 208, 4, 209, 9, 209, 4, 210, 9, 210, 4, 211, 9, 211, 4, 212, 9, 212, 4, 213, 9, 213, 4, 214, 9, 214, 4, 215, 9, 215, 4, 216, 9, 216, 4, 217, 9, 217, 4, 218, 9, 218, 4, 219, 9, 219, 4, 220, 9, 220, 4, 221, 9, 221, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 17, 3, 17, 3, 17, 3, 17, 3, 17, 3, 18, 3, 18, 3, 18, 3, 18, 3, 18, 3, 18, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 19, 3, 20, 3, 20, 3, 20, 3, 20, 3, 20, 3, 20, 3, 21, 3, 21, 3, 21, 3, 21, 3, 21, 3, 22, 3, 22, 3, 22, 3, 22, 3, 22, 3, 22, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 23, 3, 24, 3, 24, 3, 24, 3, 24, 3, 24, 3, 24, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 30, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 33, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 35, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 36, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 37, 3, 38, 3, 38, 3, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 39, 3, 39, 3, 39, 3, 39, 3, 40, 3, 40, 3, 40, 3, 40, 3, 41, 3, 41, 3, 41, 3, 41, 3, 41, 3, 42, 3, 42, 3, 42, 3, 42, 3, 42, 3, 43, 3, 43, 3, 43, 3, 43, 3, 43, 3, 44, 3, 44, 3, 44, 3, 44, 3, 44, 3, 44, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 45, 3, 46, 3, 46, 3, 46, 3, 46, 3, 46, 3, 47, 3, 47, 3, 47, 3, 47, 3, 47, 3, 47, 3, 48, 3, 48, 3, 48, 3, 48, 3, 48, 3, 49, 3, 49, 3, 49, 3, 49, 3, 49, 3, 49, 3, 50, 3, 50, 3, 50, 3, 50, 3, 50, 3, 50, 3, 51, 3, 51, 3, 51, 3, 51, 3, 51, 3, 52, 3, 52, 3, 52, 3, 52, 3, 52, 3, 53, 3, 53, 3, 53, 3, 53, 3, 53, 3, 54, 3, 54, 3, 54, 3, 54, 3, 54, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 55, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 56, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 57, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 58, 3, 59, 3, 59, 3, 59, 3, 59, 3, 59, 3, 59, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 60, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 61, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 62, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 63, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 64, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 65, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 66, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 67, 3, 68, 3, 68, 3, 68, 3, 68, 3, 68, 3, 68, 3, 69, 3, 69, 3, 69, 3, 69, 3, 69, 3, 70, 3, 70, 3, 70, 3, 70, 3, 70, 3, 70, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 71, 3, 72, 3, 72, 3, 72, 3, 72, 3, 72, 3, 72, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 73, 3, 74, 3, 74, 3, 74, 3, 74, 3, 74, 3, 75, 3, 75, 3, 75, 3, 75, 3, 75, 3, 76, 3, 76, 3, 76, 3, 76, 3, 77, 3, 77, 3, 77, 3, 77, 3, 77, 3, 78, 3, 78, 3, 78, 3, 78, 3, 78, 3, 79, 3, 79, 3, 79, 3, 79, 3, 80, 3, 80, 3, 80, 3, 80, 3, 81, 3, 81, 3, 81, 3, 81, 3, 81, 3, 81, 3, 81, 3, 82, 3, 82, 3, 82, 3, 82, 3, 83, 3, 83, 3, 83, 3, 83, 3, 83, 3, 83, 3, 83, 3, 84, 3, 84, 3, 84, 3, 84, 3, 85, 3, 85, 3, 85, 3, 85, 3, 85, 3, 85, 3, 85, 3, 86, 3, 86, 3, 86, 3, 86, 3, 87, 3, 87, 3, 87, 3, 87, 3, 87, 3, 87, 3, 87, 3, 88, 3, 88, 3, 88, 3, 88, 3, 88, 3, 88, 3, 89, 3, 89, 3, 89, 3, 89, 3, 89, 3, 89, 3, 89, 3, 90, 3, 90, 3, 90, 3, 90, 3, 90, 3, 90, 3, 91, 3, 91, 3, 91, 3, 91, 3, 91, 3, 91, 3, 92, 3, 92, 3, 92, 3, 92, 3, 92, 3, 93, 3, 93, 3, 93, 3, 93, 3, 93, 3, 94, 3, 94, 3, 94, 3, 94, 3, 94, 3, 95, 3, 95, 3, 95, 3, 95, 3, 95, 3, 96, 3, 96, 3, 96, 3, 96, 3, 96, 3, 96, 3, 97, 3, 97, 3, 97, 3, 97, 3, 98, 3, 98, 3, 98, 3, 98, 3, 98, 3, 99, 3, 99, 3, 99, 3, 99, 3, 99, 3, 99, 3, 100, 3, 100, 3, 100, 3, 100, 3, 100, 3, 100, 3, 101, 3, 101, 3, 101, 3, 101, 3, 101, 3, 101, 3, 102, 3, 102, 3, 102, 3, 102, 3, 102, 3, 102, 3, 103, 3, 103, 3, 103, 3, 103, 3, 103, 3, 103, 3, 104, 3, 104, 3, 104, 3, 104, 3, 104, 3, 104, 3, 105, 3, 105, 3, 105, 3, 105, 3, 105, 3, 105, 3, 106, 3, 106, 3, 106, 3, 106, 3, 106, 3, 106, 3, 107, 3, 107, 3, 107, 3, 107, 3, 107, 3, 107, 3, 108, 3, 108, 3, 108, 3, 108, 3, 108, 3, 108, 3, 108, 3, 108, 3, 109, 3, 109, 3, 109, 3, 109, 3, 109, 3, 110, 3, 110, 3, 110, 3, 110, 3, 110, 3, 110, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 111, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 112, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 113, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 114, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 115, 3, 116, 3, 116, 3, 116, 3, 116, 3, 116, 3, 116, 3, 116, 3, 116, 3, 116, 3, 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  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assemblyLexer.py",
    "content": "# Generated from assembly.g4 by ANTLR 4.9.2\nfrom antlr4 import *\nfrom io import StringIO\nimport sys\nif sys.version_info[1] > 5:\n    from typing import TextIO\nelse:\n    from typing.io import TextIO\n\n\n\ndef serializedATN():\n    with StringIO() as buf:\n        buf.write(\"\\3\\u608b\\ua72a\\u8133\\ub9ed\\u417c\\u3be7\\u7786\\u5964\\2\\u00de\")\n        buf.write(\"\\u073a\\b\\1\\4\\2\\t\\2\\4\\3\\t\\3\\4\\4\\t\\4\\4\\5\\t\\5\\4\\6\\t\\6\\4\\7\")\n        buf.write(\"\\t\\7\\4\\b\\t\\b\\4\\t\\t\\t\\4\\n\\t\\n\\4\\13\\t\\13\\4\\f\\t\\f\\4\\r\\t\\r\")\n        buf.write(\"\\4\\16\\t\\16\\4\\17\\t\\17\\4\\20\\t\\20\\4\\21\\t\\21\\4\\22\\t\\22\\4\\23\")\n        buf.write(\"\\t\\23\\4\\24\\t\\24\\4\\25\\t\\25\\4\\26\\t\\26\\4\\27\\t\\27\\4\\30\\t\\30\")\n        buf.write(\"\\4\\31\\t\\31\\4\\32\\t\\32\\4\\33\\t\\33\\4\\34\\t\\34\\4\\35\\t\\35\\4\\36\")\n        buf.write(\"\\t\\36\\4\\37\\t\\37\\4 \\t \\4!\\t!\\4\\\"\\t\\\"\\4#\\t#\\4$\\t$\\4%\\t%\")\n        buf.write(\"\\4&\\t&\\4\\'\\t\\'\\4(\\t(\\4)\\t)\\4*\\t*\\4+\\t+\\4,\\t,\\4-\\t-\\4.\")\n        buf.write(\"\\t.\\4/\\t/\\4\\60\\t\\60\\4\\61\\t\\61\\4\\62\\t\\62\\4\\63\\t\\63\\4\\64\")\n        buf.write(\"\\t\\64\\4\\65\\t\\65\\4\\66\\t\\66\\4\\67\\t\\67\\48\\t8\\49\\t9\\4:\\t:\")\n        buf.write(\"\\4;\\t;\\4<\\t<\\4=\\t=\\4>\\t>\\4?\\t?\\4@\\t@\\4A\\tA\\4B\\tB\\4C\\t\")\n        buf.write(\"C\\4D\\tD\\4E\\tE\\4F\\tF\\4G\\tG\\4H\\tH\\4I\\tI\\4J\\tJ\\4K\\tK\\4L\\t\")\n        buf.write(\"L\\4M\\tM\\4N\\tN\\4O\\tO\\4P\\tP\\4Q\\tQ\\4R\\tR\\4S\\tS\\4T\\tT\\4U\\t\")\n        buf.write(\"U\\4V\\tV\\4W\\tW\\4X\\tX\\4Y\\tY\\4Z\\tZ\\4[\\t[\\4\\\\\\t\\\\\\4]\\t]\\4\")\n        buf.write(\"^\\t^\\4_\\t_\\4`\\t`\\4a\\ta\\4b\\tb\\4c\\tc\\4d\\td\\4e\\te\\4f\\tf\\4\")\n        buf.write(\"g\\tg\\4h\\th\\4i\\ti\\4j\\tj\\4k\\tk\\4l\\tl\\4m\\tm\\4n\\tn\\4o\\to\\4\")\n        buf.write(\"p\\tp\\4q\\tq\\4r\\tr\\4s\\ts\\4t\\tt\\4u\\tu\\4v\\tv\\4w\\tw\\4x\\tx\\4\")\n        buf.write(\"y\\ty\\4z\\tz\\4{\\t{\\4|\\t|\\4}\\t}\\4~\\t~\\4\\177\\t\\177\\4\\u0080\")\n        buf.write(\"\\t\\u0080\\4\\u0081\\t\\u0081\\4\\u0082\\t\\u0082\\4\\u0083\\t\\u0083\")\n        buf.write(\"\\4\\u0084\\t\\u0084\\4\\u0085\\t\\u0085\\4\\u0086\\t\\u0086\\4\\u0087\")\n        buf.write(\"\\t\\u0087\\4\\u0088\\t\\u0088\\4\\u0089\\t\\u0089\\4\\u008a\\t\\u008a\")\n        buf.write(\"\\4\\u008b\\t\\u008b\\4\\u008c\\t\\u008c\\4\\u008d\\t\\u008d\\4\\u008e\")\n        buf.write(\"\\t\\u008e\\4\\u008f\\t\\u008f\\4\\u0090\\t\\u0090\\4\\u0091\\t\\u0091\")\n        buf.write(\"\\4\\u0092\\t\\u0092\\4\\u0093\\t\\u0093\\4\\u0094\\t\\u0094\\4\\u0095\")\n        buf.write(\"\\t\\u0095\\4\\u0096\\t\\u0096\\4\\u0097\\t\\u0097\\4\\u0098\\t\\u0098\")\n        buf.write(\"\\4\\u0099\\t\\u0099\\4\\u009a\\t\\u009a\\4\\u009b\\t\\u009b\\4\\u009c\")\n        buf.write(\"\\t\\u009c\\4\\u009d\\t\\u009d\\4\\u009e\\t\\u009e\\4\\u009f\\t\\u009f\")\n        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buf.write(\"\\7a\\2\\2\\u0685\\u0686\\7u\\2\\2\\u0686\\u0687\\7v\\2\\2\\u0687\\u0688\")\n        buf.write(\"\\7c\\2\\2\\u0688\\u0689\\7t\\2\\2\\u0689\\u068a\\7v\\2\\2\\u068a\\u068b\")\n        buf.write(\"\\7r\\2\\2\\u068b\\u068c\\7t\\2\\2\\u068c\\u068d\\7q\\2\\2\\u068d\\u068e\")\n        buf.write(\"\\7e\\2\\2\\u068e\\u0188\\3\\2\\2\\2\\u068f\\u0690\\7&\\2\\2\\u0690\\u0691\")\n        buf.write(\"\\7h\\2\\2\\u0691\\u0692\\7k\\2\\2\\u0692\\u0693\\7n\\2\\2\\u0693\\u0694\")\n        buf.write(\"\\7g\\2\\2\\u0694\\u018a\\3\\2\\2\\2\\u0695\\u0696\\7&\\2\\2\\u0696\\u0697\")\n        buf.write(\"\\7i\\2\\2\\u0697\\u0698\\7n\\2\\2\\u0698\\u0699\\7q\\2\\2\\u0699\\u069a\")\n        buf.write(\"\\7d\\2\\2\\u069a\\u069b\\7n\\2\\2\\u069b\\u018c\\3\\2\\2\\2\\u069c\\u069d\")\n        buf.write(\"\\7&\\2\\2\\u069d\\u069e\\7n\\2\\2\\u069e\\u069f\\7q\\2\\2\\u069f\\u06a0\")\n        buf.write(\"\\7e\\2\\2\\u06a0\\u018e\\3\\2\\2\\2\\u06a1\\u06a2\\7&\\2\\2\\u06a2\\u06a3\")\n        buf.write(\"\\7n\\2\\2\\u06a3\\u06a4\\7q\\2\\2\\u06a4\\u06a5\\7p\\2\\2\\u06a5\\u06a6\")\n        buf.write(\"\\7i\\2\\2\\u06a6\\u0190\\3\\2\\2\\2\\u06a7\\u06a8\\7&\\2\\2\\u06a8\\u06a9\")\n        buf.write(\"\\7r\\2\\2\\u06a9\\u06aa\\7\\64\\2\\2\\u06aa\\u06ab\\7c\\2\\2\\u06ab\")\n        buf.write(\"\\u06ac\\7n\\2\\2\\u06ac\\u06ad\\7k\\2\\2\\u06ad\\u06ae\\7i\\2\\2\\u06ae\")\n        buf.write(\"\\u06af\\7p\\2\\2\\u06af\\u0192\\3\\2\\2\\2\\u06b0\\u06b1\\7&\\2\\2\\u06b1\")\n        buf.write(\"\\u06b2\\7s\\2\\2\\u06b2\\u06b3\\7w\\2\\2\\u06b3\\u06b4\\7c\\2\\2\\u06b4\")\n        buf.write(\"\\u06b5\\7f\\2\\2\\u06b5\\u0194\\3\\2\\2\\2\\u06b6\\u06b7\\7&\\2\\2\\u06b7\")\n        buf.write(\"\\u06b8\\7u\\2\\2\\u06b8\\u06b9\\7g\\2\\2\\u06b9\\u06ba\\7e\\2\\2\\u06ba\")\n        buf.write(\"\\u06bb\\7v\\2\\2\\u06bb\\u06bc\\7k\\2\\2\\u06bc\\u06bd\\7q\\2\\2\\u06bd\")\n        buf.write(\"\\u06be\\7p\\2\\2\\u06be\\u0196\\3\\2\\2\\2\\u06bf\\u06c0\\7&\\2\\2\\u06c0\")\n        buf.write(\"\\u06c1\\7u\\2\\2\\u06c1\\u06c2\\7g\\2\\2\\u06c2\\u06c3\\7v\\2\\2\\u06c3\")\n        buf.write(\"\\u0198\\3\\2\\2\\2\\u06c4\\u06c5\\7&\\2\\2\\u06c5\\u06c6\\7u\\2\\2\\u06c6\")\n        buf.write(\"\\u06c7\\7j\\2\\2\\u06c7\\u06c8\\7q\\2\\2\\u06c8\\u06c9\\7t\\2\\2\\u06c9\")\n        buf.write(\"\\u06ca\\7v\\2\\2\\u06ca\\u019a\\3\\2\\2\\2\\u06cb\\u06cc\\7&\\2\\2\\u06cc\")\n        buf.write(\"\\u06cd\\7u\\2\\2\\u06cd\\u06ce\\7k\\2\\2\\u06ce\\u06cf\\7|\\2\\2\\u06cf\")\n        buf.write(\"\\u06d0\\7g\\2\\2\\u06d0\\u019c\\3\\2\\2\\2\\u06d1\\u06d2\\7&\\2\\2\\u06d2\")\n        buf.write(\"\\u06d3\\7v\\2\\2\\u06d3\\u06d4\\7g\\2\\2\\u06d4\\u06d5\\7z\\2\\2\\u06d5\")\n        buf.write(\"\\u06d6\\7v\\2\\2\\u06d6\\u019e\\3\\2\\2\\2\\u06d7\\u06d8\\7&\\2\\2\\u06d8\")\n        buf.write(\"\\u06d9\\7v\\2\\2\\u06d9\\u06da\\7{\\2\\2\\u06da\\u06db\\7r\\2\\2\\u06db\")\n        buf.write(\"\\u06dc\\7g\\2\\2\\u06dc\\u01a0\\3\\2\\2\\2\\u06dd\\u06de\\7&\\2\\2\\u06de\")\n        buf.write(\"\\u06df\\7y\\2\\2\\u06df\\u06e0\\7g\\2\\2\\u06e0\\u06e1\\7c\\2\\2\\u06e1\")\n        buf.write(\"\\u06e2\\7m\\2\\2\\u06e2\\u01a2\\3\\2\\2\\2\\u06e3\\u06e4\\7&\\2\\2\\u06e4\")\n        buf.write(\"\\u06e5\\7|\\2\\2\\u06e5\\u06e6\\7g\\2\\2\\u06e6\\u06e7\\7t\\2\\2\\u06e7\")\n        buf.write(\"\\u06e8\\7q\\2\\2\\u06e8\\u01a4\\3\\2\\2\\2\\u06e9\\u06ea\\7k\\2\\2\\u06ea\")\n        buf.write(\"\\u06eb\\7u\\2\\2\\u06eb\\u06ec\\7a\\2\\2\\u06ec\\u06ed\\7u\\2\\2\\u06ed\")\n        buf.write(\"\\u06ee\\7v\\2\\2\\u06ee\\u06ef\\7o\\2\\2\\u06ef\\u06f0\\7v\\2\\2\\u06f0\")\n        buf.write(\"\\u01a6\\3\\2\\2\\2\\u06f1\\u06f2\\7r\\2\\2\\u06f2\\u06f3\\7t\\2\\2\\u06f3\")\n        buf.write(\"\\u06f4\\7q\\2\\2\\u06f4\\u06f5\\7n\\2\\2\\u06f5\\u06f6\\7q\\2\\2\\u06f6\")\n        buf.write(\"\\u06f7\\7i\\2\\2\\u06f7\\u06f8\\7w\\2\\2\\u06f8\\u06f9\\7g\\2\\2\\u06f9\")\n        buf.write(\"\\u06fa\\7a\\2\\2\\u06fa\\u06fb\\7g\\2\\2\\u06fb\\u06fc\\7p\\2\\2\\u06fc\")\n        buf.write(\"\\u06fd\\7f\\2\\2\\u06fd\\u01a8\\3\\2\\2\\2\\u06fe\\u06ff\\7\\60\\2\\2\")\n        buf.write(\"\\u06ff\\u0700\\7u\\2\\2\\u0700\\u01aa\\3\\2\\2\\2\\u0701\\u0702\\7\")\n        buf.write(\"\\60\\2\\2\\u0702\\u0703\\7w\\2\\2\\u0703\\u01ac\\3\\2\\2\\2\\u0704\\u0706\")\n        buf.write(\"\\t\\2\\2\\2\\u0705\\u0704\\3\\2\\2\\2\\u0706\\u0707\\3\\2\\2\\2\\u0707\")\n        buf.write(\"\\u0705\\3\\2\\2\\2\\u0707\\u0708\\3\\2\\2\\2\\u0708\\u01ae\\3\\2\\2\\2\")\n        buf.write(\"\\u0709\\u070b\\7t\\2\\2\\u070a\\u070c\\t\\2\\2\\2\\u070b\\u070a\\3\")\n        buf.write(\"\\2\\2\\2\\u070c\\u070d\\3\\2\\2\\2\\u070d\\u070b\\3\\2\\2\\2\\u070d\\u070e\")\n        buf.write(\"\\3\\2\\2\\2\\u070e\\u01b0\\3\\2\\2\\2\\u070f\\u0711\\7f\\2\\2\\u0710\")\n        buf.write(\"\\u0712\\t\\2\\2\\2\\u0711\\u0710\\3\\2\\2\\2\\u0712\\u0713\\3\\2\\2\\2\")\n        buf.write(\"\\u0713\\u0711\\3\\2\\2\\2\\u0713\\u0714\\3\\2\\2\\2\\u0714\\u01b2\\3\")\n        buf.write(\"\\2\\2\\2\\u0715\\u0717\\t\\3\\2\\2\\u0716\\u0715\\3\\2\\2\\2\\u0717\\u071b\")\n        buf.write(\"\\3\\2\\2\\2\\u0718\\u071a\\t\\4\\2\\2\\u0719\\u0718\\3\\2\\2\\2\\u071a\")\n        buf.write(\"\\u071d\\3\\2\\2\\2\\u071b\\u0719\\3\\2\\2\\2\\u071b\\u071c\\3\\2\\2\\2\")\n        buf.write(\"\\u071c\\u01b4\\3\\2\\2\\2\\u071d\\u071b\\3\\2\\2\\2\\u071e\\u0723\\7\")\n        buf.write(\"$\\2\\2\\u071f\\u0722\\t\\5\\2\\2\\u0720\\u0722\\5\\u01b9\\u00dd\\2\")\n        buf.write(\"\\u0721\\u071f\\3\\2\\2\\2\\u0721\\u0720\\3\\2\\2\\2\\u0722\\u0725\\3\")\n        buf.write(\"\\2\\2\\2\\u0723\\u0721\\3\\2\\2\\2\\u0723\\u0724\\3\\2\\2\\2\\u0724\\u0726\")\n        buf.write(\"\\3\\2\\2\\2\\u0725\\u0723\\3\\2\\2\\2\\u0726\\u0727\\7$\\2\\2\\u0727\")\n        buf.write(\"\\u01b6\\3\\2\\2\\2\\u0728\\u0729\\7\\61\\2\\2\\u0729\\u072a\\7\\61\\2\")\n        buf.write(\"\\2\\u072a\\u072e\\3\\2\\2\\2\\u072b\\u072d\\n\\6\\2\\2\\u072c\\u072b\")\n        buf.write(\"\\3\\2\\2\\2\\u072d\\u0730\\3\\2\\2\\2\\u072e\\u072c\\3\\2\\2\\2\\u072e\")\n        buf.write(\"\\u072f\\3\\2\\2\\2\\u072f\\u0731\\3\\2\\2\\2\\u0730\\u072e\\3\\2\\2\\2\")\n        buf.write(\"\\u0731\\u0732\\b\\u00dc\\2\\2\\u0732\\u01b8\\3\\2\\2\\2\\u0733\\u0735\")\n        buf.write(\"\\t\\7\\2\\2\\u0734\\u0733\\3\\2\\2\\2\\u0735\\u0736\\3\\2\\2\\2\\u0736\")\n        buf.write(\"\\u0734\\3\\2\\2\\2\\u0736\\u0737\\3\\2\\2\\2\\u0737\\u0738\\3\\2\\2\\2\")\n        buf.write(\"\\u0738\\u0739\\b\\u00dd\\2\\2\\u0739\\u01ba\\3\\2\\2\\2\\r\\2\\u0707\")\n        buf.write(\"\\u070d\\u0713\\u0716\\u0719\\u071b\\u0721\\u0723\\u072e\\u0736\")\n        buf.write(\"\\3\\b\\2\\2\")\n        return buf.getvalue()\n\n\nclass assemblyLexer(Lexer):\n\n    atn = ATNDeserializer().deserialize(serializedATN())\n\n    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]\n\n    T__0 = 1\n    T__1 = 2\n    T__2 = 3\n    T__3 = 4\n    T__4 = 5\n    ACQUIRE = 6\n    RELEASE = 7\n    BOOT = 8\n    RESUME = 9\n    ADD = 10\n    ADDC = 11\n    AND = 12\n    ANDN = 13\n    ASR = 14\n    CMPB4 = 15\n    LSL = 16\n    LSL1 = 17\n    LSL1X = 18\n    LSLX = 19\n    LSR = 20\n    LSR1 = 21\n    LSR1X = 22\n    LSRX = 23\n    MUL_SH_SH = 24\n    MUL_SH_SL = 25\n    MUL_SH_UH = 26\n    MUL_SH_UL = 27\n    MUL_SL_SH = 28\n    MUL_SL_SL = 29\n    MUL_SL_UH = 30\n    MUL_SL_UL = 31\n    MUL_UH_UH = 32\n    MUL_UH_UL = 33\n    MUL_UL_UH = 34\n    MUL_UL_UL = 35\n    NAND = 36\n    NOR = 37\n    NXOR = 38\n    OR = 39\n    ORN = 40\n    ROL = 41\n    ROR = 42\n    RSUB = 43\n    RSUBC = 44\n    SUB = 45\n    SUBC = 46\n    XOR = 47\n    CALL = 48\n    HASH = 49\n    CAO = 50\n    CLO = 51\n    CLS = 52\n    CLZ = 53\n    EXTSB = 54\n    EXTSH = 55\n    EXTUB = 56\n    EXTUH = 57\n    SATS = 58\n    TIME_CFG = 59\n    DIV_STEP = 60\n    MUL_STEP = 61\n    LSL_ADD = 62\n    LSL_SUB = 63\n    LSR_ADD = 64\n    ROL_ADD = 65\n    ROR_ADD = 66\n    TIME = 67\n    NOP = 68\n    STOP = 69\n    FAULT = 70\n    MOVD = 71\n    SWAPD = 72\n    LBS = 73\n    LBU = 74\n    LD = 75\n    LHS = 76\n    LHU = 77\n    LW = 78\n    SB = 79\n    SB_ID = 80\n    SD = 81\n    SD_ID = 82\n    SH = 83\n    SH_ID = 84\n    SW = 85\n    SW_ID = 86\n    LDMA = 87\n    LDMAI = 88\n    SDMA = 89\n    MOVE = 90\n    NEG = 91\n    NOT = 92\n    BKP = 93\n    JEQ = 94\n    JNEQ = 95\n    JZ = 96\n    JNZ = 97\n    JLTU = 98\n    JGTU = 99\n    JLEU = 100\n    JGEU = 101\n    JLTS = 102\n    JGTS = 103\n    JLES = 104\n    JGES = 105\n    JUMP = 106\n    ATOMIC = 107\n    BSS = 108\n    DATA = 109\n    DEBUG_ABBREV = 110\n    DEBUG_FRAME = 111\n    DEBUG_INFO = 112\n    DEBUG_LINE = 113\n    DEBUG_LOC = 114\n    DEBUG_RANGES = 115\n    DEBUG_STR = 116\n    DPU_HOST = 117\n    MRAM = 118\n    RODATA = 119\n    STACK_SIZES = 120\n    TEXT_SECTION = 121\n    PROGBITS = 122\n    NOBITS = 123\n    FUNCTION = 124\n    OBJECT = 125\n    TRUE = 126\n    FALSE = 127\n    Z = 128\n    NZ = 129\n    E = 130\n    O = 131\n    PL = 132\n    MI = 133\n    OV = 134\n    NOV = 135\n    C = 136\n    NC = 137\n    SZ = 138\n    SNZ = 139\n    SPL = 140\n    SMI = 141\n    SO = 142\n    SE = 143\n    NC5 = 144\n    NC6 = 145\n    NC7 = 146\n    NC8 = 147\n    NC9 = 148\n    NC10 = 149\n    NC11 = 150\n    NC12 = 151\n    NC13 = 152\n    NC14 = 153\n    MAX = 154\n    NMAX = 155\n    SH32 = 156\n    NSH32 = 157\n    EQ = 158\n    NEQ = 159\n    LTU = 160\n    LEU = 161\n    GTU = 162\n    GEU = 163\n    LTS = 164\n    LES = 165\n    GTS = 166\n    GES = 167\n    XZ = 168\n    XNZ = 169\n    XLEU = 170\n    XGTU = 171\n    XLES = 172\n    XGTS = 173\n    SMALL = 174\n    LARGE = 175\n    LITTLE = 176\n    BIG = 177\n    ZERO_REGISTER = 178\n    ONE = 179\n    ID = 180\n    ID2 = 181\n    ID4 = 182\n    ID8 = 183\n    LNEG = 184\n    MNEG = 185\n    ADDRSIG = 186\n    ADDRSIG_SYM = 187\n    ASCII = 188\n    ASCIZ = 189\n    BYTE = 190\n    CFI_DEF_CFA_OFFSET = 191\n    CFI_ENDPROC = 192\n    CFI_OFFSET = 193\n    CFI_SECTIONS = 194\n    CFI_STARTPROC = 195\n    FILE = 196\n    GLOBL = 197\n    LOC = 198\n    LONG = 199\n    P2ALIGN = 200\n    QUAD = 201\n    SECTION = 202\n    SET = 203\n    SHORT = 204\n    SIZE = 205\n    TEXT_DIRECTIVE = 206\n    TYPE = 207\n    WEAK = 208\n    ZERO_DIRECTIVE = 209\n    IS_STMT = 210\n    PROLOGUE_END = 211\n    S_SUFFIX = 212\n    U_SUFFIX = 213\n    PositiveNumber = 214\n    GPRegister = 215\n    PairRegister = 216\n    Identifier = 217\n    StringLiteral = 218\n    COMMENT = 219\n    WHITE_SPACE = 220\n\n    channelNames = [ u\"DEFAULT_TOKEN_CHANNEL\", u\"HIDDEN\" ]\n\n    modeNames = [ \"DEFAULT_MODE\" ]\n\n    literalNames = [ \"<INVALID>\",\n            \"'-'\", \"'0x'\", \"'+'\", \"','\", \"':'\", \"'$acquire'\", \"'$release'\", \n            \"'$boot'\", \"'$resume'\", \"'$add'\", \"'$addc'\", \"'$and'\", \"'$andn'\", \n            \"'$asr'\", \"'$cmpb4'\", \"'$lsl'\", \"'$lsl1'\", \"'$lsl1x'\", \"'$lslx'\", \n            \"'$lsr'\", \"'$lsr1'\", \"'$lsr1x'\", \"'$lsrx'\", \"'$mul_sh_sh'\", \n            \"'$mul_sh_sl'\", \"'$mul_sh_uh'\", \"'$mul_sh_ul'\", \"'$mul_sl_sh'\", \n            \"'$mul_sl_sl'\", \"'$mul_sl_uh'\", \"'$mul_sl_ul'\", \"'$mul_uh_uh'\", \n            \"'$mul_uh_ul'\", \"'$mul_ul_uh'\", \"'$mul_ul_ul'\", \"'$nand'\", \"'$nor'\", \n            \"'$nxor'\", \"'$or'\", \"'$orn'\", \"'$rol'\", \"'$ror'\", \"'$rsub'\", \n            \"'$rsubc'\", \"'$sub'\", \"'$subc'\", \"'$xor'\", \"'$call'\", \"'$hash'\", \n            \"'$cao'\", \"'$clo'\", \"'$cls'\", \"'$clz'\", \"'$extsb'\", \"'$extsh'\", \n            \"'$extub'\", \"'$extuh'\", \"'$sats'\", \"'$time_cfg'\", \"'$div_step'\", \n            \"'$mul_step'\", \"'$lsl_add'\", \"'$lsl_sub'\", \"'$lsr_add'\", \"'$rol_add'\", \n            \"'$ror_add'\", \"'$time'\", \"'$nop'\", \"'$stop'\", \"'$fault'\", \"'$movd'\", \n            \"'$swapd'\", \"'$lbs'\", \"'$lbu'\", \"'$ld'\", \"'$lhs'\", \"'$lhu'\", \n            \"'$lw'\", \"'$sb'\", \"'$sb_id'\", \"'$sd'\", \"'$sd_id'\", \"'$sh'\", \n            \"'$sh_id'\", \"'$sw'\", \"'$sw_id'\", \"'$ldma'\", \"'$ldmai'\", \"'$sdma'\", \n            \"'$move'\", \"'$neg'\", \"'$not'\", \"'$bkp'\", \"'$jeq'\", \"'$jneq'\", \n            \"'$jz'\", \"'$jnz'\", \"'$jltu'\", \"'$jgtu'\", \"'$jleu'\", \"'$jgeu'\", \n            \"'$jlts'\", \"'$jgts'\", \"'$jles'\", \"'$jges'\", \"'$jump'\", \"'%atomic'\", \n            \"'%bss'\", \"'%data'\", \"'%debug_abbrev'\", \"'%debug_frame'\", \"'%debug_info'\", \n            \"'%debug_line'\", \"'%debug_loc'\", \"'%debug_ranges'\", \"'%debug_str'\", \n            \"'%dpu_host'\", \"'%mram'\", \"'%rodata'\", \"'%stack_sizes'\", \"'%text'\", \n            \"'@progbits'\", \"'@nobits'\", \"'@function'\", \"'@object'\", \"'true'\", \n            \"'false'\", \"'z'\", \"'nz'\", \"'e'\", \"'o'\", \"'pl'\", \"'mi'\", \"'ov'\", \n            \"'nov'\", \"'c'\", \"'nc'\", \"'sz'\", \"'snz'\", \"'spl'\", \"'smi'\", \"'so'\", \n            \"'se'\", \"'nc5'\", \"'nc6'\", \"'nc7'\", \"'nc8'\", \"'nc9'\", \"'nc10'\", \n            \"'nc11'\", \"'nc12'\", \"'nc13'\", \"'nc14'\", \"'max'\", \"'nmax'\", \"'sh32'\", \n            \"'nsh32'\", \"'eq'\", \"'neq'\", \"'ltu'\", \"'leu'\", \"'gtu'\", \"'geu'\", \n            \"'lts'\", \"'les'\", \"'gts'\", \"'ges'\", \"'xz'\", \"'xnz'\", \"'xleu'\", \n            \"'xgtu'\", \"'xles'\", \"'xgts'\", \"'small'\", \"'large'\", \"'!little'\", \n            \"'!big'\", \"'zero'\", \"'one'\", \"'id'\", \"'id2'\", \"'id4'\", \"'id8'\", \n            \"'lneg'\", \"'mneg'\", \"'$addrsig'\", \"'$addrsig_sym'\", \"'$ascii'\", \n            \"'$asciz'\", \"'$byte'\", \"'$cfi_def_cfa_offset'\", \"'$cfi_endproc'\", \n            \"'$cfi_offset'\", \"'$cfi_sections'\", \"'$cfi_startproc'\", \"'$file'\", \n            \"'$globl'\", \"'$loc'\", \"'$long'\", \"'$p2align'\", \"'$quad'\", \"'$section'\", \n            \"'$set'\", \"'$short'\", \"'$size'\", \"'$text'\", \"'$type'\", \"'$weak'\", \n            \"'$zero'\", \"'is_stmt'\", \"'prologue_end'\", \"'.s'\", \"'.u'\" ]\n\n    symbolicNames = [ \"<INVALID>\",\n            \"ACQUIRE\", \"RELEASE\", \"BOOT\", \"RESUME\", \"ADD\", \"ADDC\", \"AND\", \n            \"ANDN\", \"ASR\", \"CMPB4\", \"LSL\", \"LSL1\", \"LSL1X\", \"LSLX\", \"LSR\", \n            \"LSR1\", \"LSR1X\", \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \"MUL_SH_UH\", \n            \"MUL_SH_UL\", \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \n            \"MUL_UH_UH\", \"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \"NAND\", \n            \"NOR\", \"NXOR\", \"OR\", \"ORN\", \"ROL\", \"ROR\", \"RSUB\", \"RSUBC\", \"SUB\", \n            \"SUBC\", \"XOR\", \"CALL\", \"HASH\", \"CAO\", \"CLO\", \"CLS\", \"CLZ\", \"EXTSB\", \n            \"EXTSH\", \"EXTUB\", \"EXTUH\", \"SATS\", \"TIME_CFG\", \"DIV_STEP\", \"MUL_STEP\", \n            \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \"ROL_ADD\", \"ROR_ADD\", \"TIME\", \n            \"NOP\", \"STOP\", \"FAULT\", \"MOVD\", \"SWAPD\", \"LBS\", \"LBU\", \"LD\", \n            \"LHS\", \"LHU\", \"LW\", \"SB\", \"SB_ID\", \"SD\", \"SD_ID\", \"SH\", \"SH_ID\", \n            \"SW\", \"SW_ID\", \"LDMA\", \"LDMAI\", \"SDMA\", \"MOVE\", \"NEG\", \"NOT\", \n            \"BKP\", \"JEQ\", \"JNEQ\", \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \n            \"JLTS\", \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \"DATA\", \n            \"DEBUG_ABBREV\", \"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \"DEBUG_LOC\", \n            \"DEBUG_RANGES\", \"DEBUG_STR\", \"DPU_HOST\", \"MRAM\", \"RODATA\", \"STACK_SIZES\", \n            \"TEXT_SECTION\", \"PROGBITS\", \"NOBITS\", \"FUNCTION\", \"OBJECT\", \n            \"TRUE\", \"FALSE\", \"Z\", \"NZ\", \"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \n            \"C\", \"NC\", \"SZ\", \"SNZ\", \"SPL\", \"SMI\", \"SO\", \"SE\", \"NC5\", \"NC6\", \n            \"NC7\", \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \"NC13\", \"NC14\", \n            \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \"LTU\", \"LEU\", \"GTU\", \n            \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \"XZ\", \"XNZ\", \"XLEU\", \"XGTU\", \n            \"XLES\", \"XGTS\", \"SMALL\", \"LARGE\", \"LITTLE\", \"BIG\", \"ZERO_REGISTER\", \n            \"ONE\", \"ID\", \"ID2\", \"ID4\", \"ID8\", \"LNEG\", \"MNEG\", \"ADDRSIG\", \n            \"ADDRSIG_SYM\", \"ASCII\", \"ASCIZ\", \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \n            \"CFI_ENDPROC\", \"CFI_OFFSET\", \"CFI_SECTIONS\", \"CFI_STARTPROC\", \n            \"FILE\", \"GLOBL\", \"LOC\", \"LONG\", \"P2ALIGN\", \"QUAD\", \"SECTION\", \n            \"SET\", \"SHORT\", \"SIZE\", \"TEXT_DIRECTIVE\", \"TYPE\", \"WEAK\", \"ZERO_DIRECTIVE\", \n            \"IS_STMT\", \"PROLOGUE_END\", \"S_SUFFIX\", \"U_SUFFIX\", \"PositiveNumber\", \n            \"GPRegister\", \"PairRegister\", \"Identifier\", \"StringLiteral\", \n            \"COMMENT\", \"WHITE_SPACE\" ]\n\n    ruleNames = [ \"T__0\", \"T__1\", \"T__2\", \"T__3\", \"T__4\", \"ACQUIRE\", \"RELEASE\", \n                  \"BOOT\", \"RESUME\", \"ADD\", \"ADDC\", \"AND\", \"ANDN\", \"ASR\", \n                  \"CMPB4\", \"LSL\", \"LSL1\", \"LSL1X\", \"LSLX\", \"LSR\", \"LSR1\", \n                  \"LSR1X\", \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \"MUL_SH_UH\", \n                  \"MUL_SH_UL\", \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \n                  \"MUL_UH_UH\", \"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \"NAND\", \n                  \"NOR\", \"NXOR\", \"OR\", \"ORN\", \"ROL\", \"ROR\", \"RSUB\", \"RSUBC\", \n                  \"SUB\", \"SUBC\", \"XOR\", \"CALL\", \"HASH\", \"CAO\", \"CLO\", \"CLS\", \n                  \"CLZ\", \"EXTSB\", \"EXTSH\", \"EXTUB\", \"EXTUH\", \"SATS\", \"TIME_CFG\", \n                  \"DIV_STEP\", \"MUL_STEP\", \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \n                  \"ROL_ADD\", \"ROR_ADD\", \"TIME\", \"NOP\", \"STOP\", \"FAULT\", \n                  \"MOVD\", \"SWAPD\", \"LBS\", \"LBU\", \"LD\", \"LHS\", \"LHU\", \"LW\", \n                  \"SB\", \"SB_ID\", \"SD\", \"SD_ID\", \"SH\", \"SH_ID\", \"SW\", \"SW_ID\", \n                  \"LDMA\", \"LDMAI\", \"SDMA\", \"MOVE\", \"NEG\", \"NOT\", \"BKP\", \n                  \"JEQ\", \"JNEQ\", \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \n                  \"JLTS\", \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \n                  \"DATA\", \"DEBUG_ABBREV\", \"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \n                  \"DEBUG_LOC\", \"DEBUG_RANGES\", \"DEBUG_STR\", \"DPU_HOST\", \n                  \"MRAM\", \"RODATA\", \"STACK_SIZES\", \"TEXT_SECTION\", \"PROGBITS\", \n                  \"NOBITS\", \"FUNCTION\", \"OBJECT\", \"TRUE\", \"FALSE\", \"Z\", \n                  \"NZ\", \"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \"C\", \"NC\", \"SZ\", \n                  \"SNZ\", \"SPL\", \"SMI\", \"SO\", \"SE\", \"NC5\", \"NC6\", \"NC7\", \n                  \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \"NC13\", \"NC14\", \n                  \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \"LTU\", \"LEU\", \n                  \"GTU\", \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \"XZ\", \"XNZ\", \n                  \"XLEU\", \"XGTU\", \"XLES\", \"XGTS\", \"SMALL\", \"LARGE\", \"LITTLE\", \n                  \"BIG\", \"ZERO_REGISTER\", \"ONE\", \"ID\", \"ID2\", \"ID4\", \"ID8\", \n                  \"LNEG\", \"MNEG\", \"ADDRSIG\", \"ADDRSIG_SYM\", \"ASCII\", \"ASCIZ\", \n                  \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \"CFI_ENDPROC\", \"CFI_OFFSET\", \n                  \"CFI_SECTIONS\", \"CFI_STARTPROC\", \"FILE\", \"GLOBL\", \"LOC\", \n                  \"LONG\", \"P2ALIGN\", \"QUAD\", \"SECTION\", \"SET\", \"SHORT\", \n                  \"SIZE\", \"TEXT_DIRECTIVE\", \"TYPE\", \"WEAK\", \"ZERO_DIRECTIVE\", \n                  \"IS_STMT\", \"PROLOGUE_END\", \"S_SUFFIX\", \"U_SUFFIX\", \"PositiveNumber\", \n                  \"GPRegister\", \"PairRegister\", \"Identifier\", \"StringLiteral\", \n                  \"COMMENT\", \"WHITE_SPACE\" ]\n\n    grammarFileName = \"assembly.g4\"\n\n    def __init__(self, input=None, output:TextIO = sys.stdout):\n        super().__init__(input, output)\n        self.checkVersion(\"4.9.2\")\n        self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache())\n        self._actions = None\n        self._predicates = None\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assemblyLexer.tokens",
    "content": "T__0=1\nT__1=2\nT__2=3\nT__3=4\nT__4=5\nACQUIRE=6\nRELEASE=7\nBOOT=8\nRESUME=9\nADD=10\nADDC=11\nAND=12\nANDN=13\nASR=14\nCMPB4=15\nLSL=16\nLSL1=17\nLSL1X=18\nLSLX=19\nLSR=20\nLSR1=21\nLSR1X=22\nLSRX=23\nMUL_SH_SH=24\nMUL_SH_SL=25\nMUL_SH_UH=26\nMUL_SH_UL=27\nMUL_SL_SH=28\nMUL_SL_SL=29\nMUL_SL_UH=30\nMUL_SL_UL=31\nMUL_UH_UH=32\nMUL_UH_UL=33\nMUL_UL_UH=34\nMUL_UL_UL=35\nNAND=36\nNOR=37\nNXOR=38\nOR=39\nORN=40\nROL=41\nROR=42\nRSUB=43\nRSUBC=44\nSUB=45\nSUBC=46\nXOR=47\nCALL=48\nHASH=49\nCAO=50\nCLO=51\nCLS=52\nCLZ=53\nEXTSB=54\nEXTSH=55\nEXTUB=56\nEXTUH=57\nSATS=58\nTIME_CFG=59\nDIV_STEP=60\nMUL_STEP=61\nLSL_ADD=62\nLSL_SUB=63\nLSR_ADD=64\nROL_ADD=65\nROR_ADD=66\nTIME=67\nNOP=68\nSTOP=69\nFAULT=70\nMOVD=71\nSWAPD=72\nLBS=73\nLBU=74\nLD=75\nLHS=76\nLHU=77\nLW=78\nSB=79\nSB_ID=80\nSD=81\nSD_ID=82\nSH=83\nSH_ID=84\nSW=85\nSW_ID=86\nLDMA=87\nLDMAI=88\nSDMA=89\nMOVE=90\nNEG=91\nNOT=92\nBKP=93\nJEQ=94\nJNEQ=95\nJZ=96\nJNZ=97\nJLTU=98\nJGTU=99\nJLEU=100\nJGEU=101\nJLTS=102\nJGTS=103\nJLES=104\nJGES=105\nJUMP=106\nATOMIC=107\nBSS=108\nDATA=109\nDEBUG_ABBREV=110\nDEBUG_FRAME=111\nDEBUG_INFO=112\nDEBUG_LINE=113\nDEBUG_LOC=114\nDEBUG_RANGES=115\nDEBUG_STR=116\nDPU_HOST=117\nMRAM=118\nRODATA=119\nSTACK_SIZES=120\nTEXT_SECTION=121\nPROGBITS=122\nNOBITS=123\nFUNCTION=124\nOBJECT=125\nTRUE=126\nFALSE=127\nZ=128\nNZ=129\nE=130\nO=131\nPL=132\nMI=133\nOV=134\nNOV=135\nC=136\nNC=137\nSZ=138\nSNZ=139\nSPL=140\nSMI=141\nSO=142\nSE=143\nNC5=144\nNC6=145\nNC7=146\nNC8=147\nNC9=148\nNC10=149\nNC11=150\nNC12=151\nNC13=152\nNC14=153\nMAX=154\nNMAX=155\nSH32=156\nNSH32=157\nEQ=158\nNEQ=159\nLTU=160\nLEU=161\nGTU=162\nGEU=163\nLTS=164\nLES=165\nGTS=166\nGES=167\nXZ=168\nXNZ=169\nXLEU=170\nXGTU=171\nXLES=172\nXGTS=173\nSMALL=174\nLARGE=175\nLITTLE=176\nBIG=177\nZERO_REGISTER=178\nONE=179\nID=180\nID2=181\nID4=182\nID8=183\nLNEG=184\nMNEG=185\nADDRSIG=186\nADDRSIG_SYM=187\nASCII=188\nASCIZ=189\nBYTE=190\nCFI_DEF_CFA_OFFSET=191\nCFI_ENDPROC=192\nCFI_OFFSET=193\nCFI_SECTIONS=194\nCFI_STARTPROC=195\nFILE=196\nGLOBL=197\nLOC=198\nLONG=199\nP2ALIGN=200\nQUAD=201\nSECTION=202\nSET=203\nSHORT=204\nSIZE=205\nTEXT_DIRECTIVE=206\nTYPE=207\nWEAK=208\nZERO_DIRECTIVE=209\nIS_STMT=210\nPROLOGUE_END=211\nS_SUFFIX=212\nU_SUFFIX=213\nPositiveNumber=214\nGPRegister=215\nPairRegister=216\nIdentifier=217\nStringLiteral=218\nCOMMENT=219\nWHITE_SPACE=220\n'-'=1\n'0x'=2\n'+'=3\n','=4\n':'=5\n'$acquire'=6\n'$release'=7\n'$boot'=8\n'$resume'=9\n'$add'=10\n'$addc'=11\n'$and'=12\n'$andn'=13\n'$asr'=14\n'$cmpb4'=15\n'$lsl'=16\n'$lsl1'=17\n'$lsl1x'=18\n'$lslx'=19\n'$lsr'=20\n'$lsr1'=21\n'$lsr1x'=22\n'$lsrx'=23\n'$mul_sh_sh'=24\n'$mul_sh_sl'=25\n'$mul_sh_uh'=26\n'$mul_sh_ul'=27\n'$mul_sl_sh'=28\n'$mul_sl_sl'=29\n'$mul_sl_uh'=30\n'$mul_sl_ul'=31\n'$mul_uh_uh'=32\n'$mul_uh_ul'=33\n'$mul_ul_uh'=34\n'$mul_ul_ul'=35\n'$nand'=36\n'$nor'=37\n'$nxor'=38\n'$or'=39\n'$orn'=40\n'$rol'=41\n'$ror'=42\n'$rsub'=43\n'$rsubc'=44\n'$sub'=45\n'$subc'=46\n'$xor'=47\n'$call'=48\n'$hash'=49\n'$cao'=50\n'$clo'=51\n'$cls'=52\n'$clz'=53\n'$extsb'=54\n'$extsh'=55\n'$extub'=56\n'$extuh'=57\n'$sats'=58\n'$time_cfg'=59\n'$div_step'=60\n'$mul_step'=61\n'$lsl_add'=62\n'$lsl_sub'=63\n'$lsr_add'=64\n'$rol_add'=65\n'$ror_add'=66\n'$time'=67\n'$nop'=68\n'$stop'=69\n'$fault'=70\n'$movd'=71\n'$swapd'=72\n'$lbs'=73\n'$lbu'=74\n'$ld'=75\n'$lhs'=76\n'$lhu'=77\n'$lw'=78\n'$sb'=79\n'$sb_id'=80\n'$sd'=81\n'$sd_id'=82\n'$sh'=83\n'$sh_id'=84\n'$sw'=85\n'$sw_id'=86\n'$ldma'=87\n'$ldmai'=88\n'$sdma'=89\n'$move'=90\n'$neg'=91\n'$not'=92\n'$bkp'=93\n'$jeq'=94\n'$jneq'=95\n'$jz'=96\n'$jnz'=97\n'$jltu'=98\n'$jgtu'=99\n'$jleu'=100\n'$jgeu'=101\n'$jlts'=102\n'$jgts'=103\n'$jles'=104\n'$jges'=105\n'$jump'=106\n'%atomic'=107\n'%bss'=108\n'%data'=109\n'%debug_abbrev'=110\n'%debug_frame'=111\n'%debug_info'=112\n'%debug_line'=113\n'%debug_loc'=114\n'%debug_ranges'=115\n'%debug_str'=116\n'%dpu_host'=117\n'%mram'=118\n'%rodata'=119\n'%stack_sizes'=120\n'%text'=121\n'@progbits'=122\n'@nobits'=123\n'@function'=124\n'@object'=125\n'true'=126\n'false'=127\n'z'=128\n'nz'=129\n'e'=130\n'o'=131\n'pl'=132\n'mi'=133\n'ov'=134\n'nov'=135\n'c'=136\n'nc'=137\n'sz'=138\n'snz'=139\n'spl'=140\n'smi'=141\n'so'=142\n'se'=143\n'nc5'=144\n'nc6'=145\n'nc7'=146\n'nc8'=147\n'nc9'=148\n'nc10'=149\n'nc11'=150\n'nc12'=151\n'nc13'=152\n'nc14'=153\n'max'=154\n'nmax'=155\n'sh32'=156\n'nsh32'=157\n'eq'=158\n'neq'=159\n'ltu'=160\n'leu'=161\n'gtu'=162\n'geu'=163\n'lts'=164\n'les'=165\n'gts'=166\n'ges'=167\n'xz'=168\n'xnz'=169\n'xleu'=170\n'xgtu'=171\n'xles'=172\n'xgts'=173\n'small'=174\n'large'=175\n'!little'=176\n'!big'=177\n'zero'=178\n'one'=179\n'id'=180\n'id2'=181\n'id4'=182\n'id8'=183\n'lneg'=184\n'mneg'=185\n'$addrsig'=186\n'$addrsig_sym'=187\n'$ascii'=188\n'$asciz'=189\n'$byte'=190\n'$cfi_def_cfa_offset'=191\n'$cfi_endproc'=192\n'$cfi_offset'=193\n'$cfi_sections'=194\n'$cfi_startproc'=195\n'$file'=196\n'$globl'=197\n'$loc'=198\n'$long'=199\n'$p2align'=200\n'$quad'=201\n'$section'=202\n'$set'=203\n'$short'=204\n'$size'=205\n'$text'=206\n'$type'=207\n'$weak'=208\n'$zero'=209\n'is_stmt'=210\n'prologue_end'=211\n'.s'=212\n'.u'=213\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assemblyListener.py",
    "content": "# Generated from assembly.g4 by ANTLR 4.9.2\nfrom antlr4 import *\nif __name__ is not None and \".\" in __name__:\n    from .assemblyParser import assemblyParser\nelse:\n    from assemblyParser import assemblyParser\n\n# This class defines a complete listener for a parse tree produced by assemblyParser.\nclass assemblyListener(ParseTreeListener):\n\n    # Enter a parse tree produced by assemblyParser#document.\n    def enterDocument(self, ctx:assemblyParser.DocumentContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#document.\n    def exitDocument(self, ctx:assemblyParser.DocumentContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#negative_number.\n    def enterNegative_number(self, ctx:assemblyParser.Negative_numberContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#negative_number.\n    def exitNegative_number(self, ctx:assemblyParser.Negative_numberContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#hex_number.\n    def enterHex_number(self, ctx:assemblyParser.Hex_numberContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#hex_number.\n    def exitHex_number(self, ctx:assemblyParser.Hex_numberContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#number.\n    def enterNumber(self, ctx:assemblyParser.NumberContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#number.\n    def exitNumber(self, ctx:assemblyParser.NumberContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rici_op_code.\n    def enterRici_op_code(self, ctx:assemblyParser.Rici_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rici_op_code.\n    def exitRici_op_code(self, ctx:assemblyParser.Rici_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rri_op_code.\n    def enterRri_op_code(self, ctx:assemblyParser.Rri_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rri_op_code.\n    def exitRri_op_code(self, ctx:assemblyParser.Rri_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rr_op_code.\n    def enterRr_op_code(self, ctx:assemblyParser.Rr_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rr_op_code.\n    def exitRr_op_code(self, ctx:assemblyParser.Rr_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#drdici_op_code.\n    def enterDrdici_op_code(self, ctx:assemblyParser.Drdici_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#drdici_op_code.\n    def exitDrdici_op_code(self, ctx:assemblyParser.Drdici_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrri_op_code.\n    def enterRrri_op_code(self, ctx:assemblyParser.Rrri_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrri_op_code.\n    def exitRrri_op_code(self, ctx:assemblyParser.Rrri_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#r_op_code.\n    def enterR_op_code(self, ctx:assemblyParser.R_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#r_op_code.\n    def exitR_op_code(self, ctx:assemblyParser.R_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ci_op_code.\n    def enterCi_op_code(self, ctx:assemblyParser.Ci_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ci_op_code.\n    def exitCi_op_code(self, ctx:assemblyParser.Ci_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#i_op_code.\n    def enterI_op_code(self, ctx:assemblyParser.I_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#i_op_code.\n    def exitI_op_code(self, ctx:assemblyParser.I_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ddci_op_code.\n    def enterDdci_op_code(self, ctx:assemblyParser.Ddci_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ddci_op_code.\n    def exitDdci_op_code(self, ctx:assemblyParser.Ddci_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#load_op_code.\n    def enterLoad_op_code(self, ctx:assemblyParser.Load_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#load_op_code.\n    def exitLoad_op_code(self, ctx:assemblyParser.Load_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#store_op_code.\n    def enterStore_op_code(self, ctx:assemblyParser.Store_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#store_op_code.\n    def exitStore_op_code(self, ctx:assemblyParser.Store_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#dma_op_code.\n    def enterDma_op_code(self, ctx:assemblyParser.Dma_op_codeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#dma_op_code.\n    def exitDma_op_code(self, ctx:assemblyParser.Dma_op_codeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#section_name.\n    def enterSection_name(self, ctx:assemblyParser.Section_nameContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#section_name.\n    def exitSection_name(self, ctx:assemblyParser.Section_nameContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#section_types.\n    def enterSection_types(self, ctx:assemblyParser.Section_typesContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#section_types.\n    def exitSection_types(self, ctx:assemblyParser.Section_typesContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#symbol_type.\n    def enterSymbol_type(self, ctx:assemblyParser.Symbol_typeContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#symbol_type.\n    def exitSymbol_type(self, ctx:assemblyParser.Symbol_typeContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#condition.\n    def enterCondition(self, ctx:assemblyParser.ConditionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#condition.\n    def exitCondition(self, ctx:assemblyParser.ConditionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#endian.\n    def enterEndian(self, ctx:assemblyParser.EndianContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#endian.\n    def exitEndian(self, ctx:assemblyParser.EndianContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sp_register.\n    def enterSp_register(self, ctx:assemblyParser.Sp_registerContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sp_register.\n    def exitSp_register(self, ctx:assemblyParser.Sp_registerContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#src_register.\n    def enterSrc_register(self, ctx:assemblyParser.Src_registerContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#src_register.\n    def exitSrc_register(self, ctx:assemblyParser.Src_registerContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#program_counter.\n    def enterProgram_counter(self, ctx:assemblyParser.Program_counterContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#program_counter.\n    def exitProgram_counter(self, ctx:assemblyParser.Program_counterContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#add_expression.\n    def enterAdd_expression(self, ctx:assemblyParser.Add_expressionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#add_expression.\n    def exitAdd_expression(self, ctx:assemblyParser.Add_expressionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sub_expression.\n    def enterSub_expression(self, ctx:assemblyParser.Sub_expressionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sub_expression.\n    def exitSub_expression(self, ctx:assemblyParser.Sub_expressionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#primary_expression.\n    def enterPrimary_expression(self, ctx:assemblyParser.Primary_expressionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#primary_expression.\n    def exitPrimary_expression(self, ctx:assemblyParser.Primary_expressionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#directive.\n    def enterDirective(self, ctx:assemblyParser.DirectiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#directive.\n    def exitDirective(self, ctx:assemblyParser.DirectiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#addrsig_directive.\n    def enterAddrsig_directive(self, ctx:assemblyParser.Addrsig_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#addrsig_directive.\n    def exitAddrsig_directive(self, ctx:assemblyParser.Addrsig_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#addrsig_sym_directive.\n    def enterAddrsig_sym_directive(self, ctx:assemblyParser.Addrsig_sym_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#addrsig_sym_directive.\n    def exitAddrsig_sym_directive(self, ctx:assemblyParser.Addrsig_sym_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ascii_directive.\n    def enterAscii_directive(self, ctx:assemblyParser.Ascii_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ascii_directive.\n    def exitAscii_directive(self, ctx:assemblyParser.Ascii_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#asciz_directive.\n    def enterAsciz_directive(self, ctx:assemblyParser.Asciz_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#asciz_directive.\n    def exitAsciz_directive(self, ctx:assemblyParser.Asciz_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#byte_directive.\n    def enterByte_directive(self, ctx:assemblyParser.Byte_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#byte_directive.\n    def exitByte_directive(self, ctx:assemblyParser.Byte_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#cfi_def_cfa_offset_directive.\n    def enterCfi_def_cfa_offset_directive(self, ctx:assemblyParser.Cfi_def_cfa_offset_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#cfi_def_cfa_offset_directive.\n    def exitCfi_def_cfa_offset_directive(self, ctx:assemblyParser.Cfi_def_cfa_offset_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#cfi_endproc_directive.\n    def enterCfi_endproc_directive(self, ctx:assemblyParser.Cfi_endproc_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#cfi_endproc_directive.\n    def exitCfi_endproc_directive(self, ctx:assemblyParser.Cfi_endproc_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#cfi_offset_directive.\n    def enterCfi_offset_directive(self, ctx:assemblyParser.Cfi_offset_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#cfi_offset_directive.\n    def exitCfi_offset_directive(self, ctx:assemblyParser.Cfi_offset_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#cfi_sections_directive.\n    def enterCfi_sections_directive(self, ctx:assemblyParser.Cfi_sections_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#cfi_sections_directive.\n    def exitCfi_sections_directive(self, ctx:assemblyParser.Cfi_sections_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#cfi_startproc_directive.\n    def enterCfi_startproc_directive(self, ctx:assemblyParser.Cfi_startproc_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#cfi_startproc_directive.\n    def exitCfi_startproc_directive(self, ctx:assemblyParser.Cfi_startproc_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#file_directive.\n    def enterFile_directive(self, ctx:assemblyParser.File_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#file_directive.\n    def exitFile_directive(self, ctx:assemblyParser.File_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#global_directive.\n    def enterGlobal_directive(self, ctx:assemblyParser.Global_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#global_directive.\n    def exitGlobal_directive(self, ctx:assemblyParser.Global_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#loc_directive.\n    def enterLoc_directive(self, ctx:assemblyParser.Loc_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#loc_directive.\n    def exitLoc_directive(self, ctx:assemblyParser.Loc_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#long_directive.\n    def enterLong_directive(self, ctx:assemblyParser.Long_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#long_directive.\n    def exitLong_directive(self, ctx:assemblyParser.Long_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#p2align_directive.\n    def enterP2align_directive(self, ctx:assemblyParser.P2align_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#p2align_directive.\n    def exitP2align_directive(self, ctx:assemblyParser.P2align_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#quad_directive.\n    def enterQuad_directive(self, ctx:assemblyParser.Quad_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#quad_directive.\n    def exitQuad_directive(self, ctx:assemblyParser.Quad_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#section_directive.\n    def enterSection_directive(self, ctx:assemblyParser.Section_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#section_directive.\n    def exitSection_directive(self, ctx:assemblyParser.Section_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#set_directive.\n    def enterSet_directive(self, ctx:assemblyParser.Set_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#set_directive.\n    def exitSet_directive(self, ctx:assemblyParser.Set_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#short_directive.\n    def enterShort_directive(self, ctx:assemblyParser.Short_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#short_directive.\n    def exitShort_directive(self, ctx:assemblyParser.Short_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#size_directive.\n    def enterSize_directive(self, ctx:assemblyParser.Size_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#size_directive.\n    def exitSize_directive(self, ctx:assemblyParser.Size_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#stack_sizes_directive.\n    def enterStack_sizes_directive(self, ctx:assemblyParser.Stack_sizes_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#stack_sizes_directive.\n    def exitStack_sizes_directive(self, ctx:assemblyParser.Stack_sizes_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#text_directive.\n    def enterText_directive(self, ctx:assemblyParser.Text_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#text_directive.\n    def exitText_directive(self, ctx:assemblyParser.Text_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#type_directive.\n    def enterType_directive(self, ctx:assemblyParser.Type_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#type_directive.\n    def exitType_directive(self, ctx:assemblyParser.Type_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#weak_directive.\n    def enterWeak_directive(self, ctx:assemblyParser.Weak_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#weak_directive.\n    def exitWeak_directive(self, ctx:assemblyParser.Weak_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zero_directive.\n    def enterZero_directive(self, ctx:assemblyParser.Zero_directiveContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zero_directive.\n    def exitZero_directive(self, ctx:assemblyParser.Zero_directiveContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#instruction.\n    def enterInstruction(self, ctx:assemblyParser.InstructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#instruction.\n    def exitInstruction(self, ctx:assemblyParser.InstructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rici_instruction.\n    def enterRici_instruction(self, ctx:assemblyParser.Rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rici_instruction.\n    def exitRici_instruction(self, ctx:assemblyParser.Rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rri_instruction.\n    def enterRri_instruction(self, ctx:assemblyParser.Rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rri_instruction.\n    def exitRri_instruction(self, ctx:assemblyParser.Rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rric_instruction.\n    def enterRric_instruction(self, ctx:assemblyParser.Rric_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rric_instruction.\n    def exitRric_instruction(self, ctx:assemblyParser.Rric_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrici_instruction.\n    def enterRrici_instruction(self, ctx:assemblyParser.Rrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrici_instruction.\n    def exitRrici_instruction(self, ctx:assemblyParser.Rrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrr_instruction.\n    def enterRrr_instruction(self, ctx:assemblyParser.Rrr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrr_instruction.\n    def exitRrr_instruction(self, ctx:assemblyParser.Rrr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrrc_instruction.\n    def enterRrrc_instruction(self, ctx:assemblyParser.Rrrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrrc_instruction.\n    def exitRrrc_instruction(self, ctx:assemblyParser.Rrrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrrci_instruction.\n    def enterRrrci_instruction(self, ctx:assemblyParser.Rrrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrrci_instruction.\n    def exitRrrci_instruction(self, ctx:assemblyParser.Rrrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zri_instruction.\n    def enterZri_instruction(self, ctx:assemblyParser.Zri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zri_instruction.\n    def exitZri_instruction(self, ctx:assemblyParser.Zri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zric_instruction.\n    def enterZric_instruction(self, ctx:assemblyParser.Zric_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zric_instruction.\n    def exitZric_instruction(self, ctx:assemblyParser.Zric_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrici_instruction.\n    def enterZrici_instruction(self, ctx:assemblyParser.Zrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrici_instruction.\n    def exitZrici_instruction(self, ctx:assemblyParser.Zrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrr_instruction.\n    def enterZrr_instruction(self, ctx:assemblyParser.Zrr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrr_instruction.\n    def exitZrr_instruction(self, ctx:assemblyParser.Zrr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrrc_instruction.\n    def enterZrrc_instruction(self, ctx:assemblyParser.Zrrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrrc_instruction.\n    def exitZrrc_instruction(self, ctx:assemblyParser.Zrrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrrci_instruction.\n    def enterZrrci_instruction(self, ctx:assemblyParser.Zrrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrrci_instruction.\n    def exitZrrci_instruction(self, ctx:assemblyParser.Zrrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rri_instruction.\n    def enterS_rri_instruction(self, ctx:assemblyParser.S_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rri_instruction.\n    def exitS_rri_instruction(self, ctx:assemblyParser.S_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rric_instruction.\n    def enterS_rric_instruction(self, ctx:assemblyParser.S_rric_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rric_instruction.\n    def exitS_rric_instruction(self, ctx:assemblyParser.S_rric_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrici_instruction.\n    def enterS_rrici_instruction(self, ctx:assemblyParser.S_rrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrici_instruction.\n    def exitS_rrici_instruction(self, ctx:assemblyParser.S_rrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrr_instruction.\n    def enterS_rrr_instruction(self, ctx:assemblyParser.S_rrr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrr_instruction.\n    def exitS_rrr_instruction(self, ctx:assemblyParser.S_rrr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrrc_instruction.\n    def enterS_rrrc_instruction(self, ctx:assemblyParser.S_rrrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrrc_instruction.\n    def exitS_rrrc_instruction(self, ctx:assemblyParser.S_rrrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrrci_instruction.\n    def enterS_rrrci_instruction(self, ctx:assemblyParser.S_rrrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrrci_instruction.\n    def exitS_rrrci_instruction(self, ctx:assemblyParser.S_rrrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rri_instruction.\n    def enterU_rri_instruction(self, ctx:assemblyParser.U_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rri_instruction.\n    def exitU_rri_instruction(self, ctx:assemblyParser.U_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rric_instruction.\n    def enterU_rric_instruction(self, ctx:assemblyParser.U_rric_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rric_instruction.\n    def exitU_rric_instruction(self, ctx:assemblyParser.U_rric_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrici_instruction.\n    def enterU_rrici_instruction(self, ctx:assemblyParser.U_rrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrici_instruction.\n    def exitU_rrici_instruction(self, ctx:assemblyParser.U_rrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrr_instruction.\n    def enterU_rrr_instruction(self, ctx:assemblyParser.U_rrr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrr_instruction.\n    def exitU_rrr_instruction(self, ctx:assemblyParser.U_rrr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrrc_instruction.\n    def enterU_rrrc_instruction(self, ctx:assemblyParser.U_rrrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrrc_instruction.\n    def exitU_rrrc_instruction(self, ctx:assemblyParser.U_rrrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrrci_instruction.\n    def enterU_rrrci_instruction(self, ctx:assemblyParser.U_rrrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrrci_instruction.\n    def exitU_rrrci_instruction(self, ctx:assemblyParser.U_rrrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rr_instruction.\n    def enterRr_instruction(self, ctx:assemblyParser.Rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rr_instruction.\n    def exitRr_instruction(self, ctx:assemblyParser.Rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrc_instruction.\n    def enterRrc_instruction(self, ctx:assemblyParser.Rrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrc_instruction.\n    def exitRrc_instruction(self, ctx:assemblyParser.Rrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrci_instruction.\n    def enterRrci_instruction(self, ctx:assemblyParser.Rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrci_instruction.\n    def exitRrci_instruction(self, ctx:assemblyParser.Rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zr_instruction.\n    def enterZr_instruction(self, ctx:assemblyParser.Zr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zr_instruction.\n    def exitZr_instruction(self, ctx:assemblyParser.Zr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrc_instruction.\n    def enterZrc_instruction(self, ctx:assemblyParser.Zrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrc_instruction.\n    def exitZrc_instruction(self, ctx:assemblyParser.Zrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrci_instruction.\n    def enterZrci_instruction(self, ctx:assemblyParser.Zrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrci_instruction.\n    def exitZrci_instruction(self, ctx:assemblyParser.Zrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rr_instruction.\n    def enterS_rr_instruction(self, ctx:assemblyParser.S_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rr_instruction.\n    def exitS_rr_instruction(self, ctx:assemblyParser.S_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrc_instruction.\n    def enterS_rrc_instruction(self, ctx:assemblyParser.S_rrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrc_instruction.\n    def exitS_rrc_instruction(self, ctx:assemblyParser.S_rrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrci_instruction.\n    def enterS_rrci_instruction(self, ctx:assemblyParser.S_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrci_instruction.\n    def exitS_rrci_instruction(self, ctx:assemblyParser.S_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rr_instruction.\n    def enterU_rr_instruction(self, ctx:assemblyParser.U_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rr_instruction.\n    def exitU_rr_instruction(self, ctx:assemblyParser.U_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrc_instruction.\n    def enterU_rrc_instruction(self, ctx:assemblyParser.U_rrc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrc_instruction.\n    def exitU_rrc_instruction(self, ctx:assemblyParser.U_rrc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrci_instruction.\n    def enterU_rrci_instruction(self, ctx:assemblyParser.U_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrci_instruction.\n    def exitU_rrci_instruction(self, ctx:assemblyParser.U_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#drdici_instruction.\n    def enterDrdici_instruction(self, ctx:assemblyParser.Drdici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#drdici_instruction.\n    def exitDrdici_instruction(self, ctx:assemblyParser.Drdici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrri_instruction.\n    def enterRrri_instruction(self, ctx:assemblyParser.Rrri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrri_instruction.\n    def exitRrri_instruction(self, ctx:assemblyParser.Rrri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrrici_instruction.\n    def enterRrrici_instruction(self, ctx:assemblyParser.Rrrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrrici_instruction.\n    def exitRrrici_instruction(self, ctx:assemblyParser.Rrrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrri_instruction.\n    def enterZrri_instruction(self, ctx:assemblyParser.Zrri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrri_instruction.\n    def exitZrri_instruction(self, ctx:assemblyParser.Zrri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zrrici_instruction.\n    def enterZrrici_instruction(self, ctx:assemblyParser.Zrrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zrrici_instruction.\n    def exitZrrici_instruction(self, ctx:assemblyParser.Zrrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrri_instruction.\n    def enterS_rrri_instruction(self, ctx:assemblyParser.S_rrri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrri_instruction.\n    def exitS_rrri_instruction(self, ctx:assemblyParser.S_rrri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rrrici_instruction.\n    def enterS_rrrici_instruction(self, ctx:assemblyParser.S_rrrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rrrici_instruction.\n    def exitS_rrrici_instruction(self, ctx:assemblyParser.S_rrrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrri_instruction.\n    def enterU_rrri_instruction(self, ctx:assemblyParser.U_rrri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrri_instruction.\n    def exitU_rrri_instruction(self, ctx:assemblyParser.U_rrri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rrrici_instruction.\n    def enterU_rrrici_instruction(self, ctx:assemblyParser.U_rrrici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rrrici_instruction.\n    def exitU_rrrici_instruction(self, ctx:assemblyParser.U_rrrici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rir_instruction.\n    def enterRir_instruction(self, ctx:assemblyParser.Rir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rir_instruction.\n    def exitRir_instruction(self, ctx:assemblyParser.Rir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rirc_instruction.\n    def enterRirc_instruction(self, ctx:assemblyParser.Rirc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rirc_instruction.\n    def exitRirc_instruction(self, ctx:assemblyParser.Rirc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rirci_instruction.\n    def enterRirci_instruction(self, ctx:assemblyParser.Rirci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rirci_instruction.\n    def exitRirci_instruction(self, ctx:assemblyParser.Rirci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zir_instruction.\n    def enterZir_instruction(self, ctx:assemblyParser.Zir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zir_instruction.\n    def exitZir_instruction(self, ctx:assemblyParser.Zir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zirc_instruction.\n    def enterZirc_instruction(self, ctx:assemblyParser.Zirc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zirc_instruction.\n    def exitZirc_instruction(self, ctx:assemblyParser.Zirc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zirci_instruction.\n    def enterZirci_instruction(self, ctx:assemblyParser.Zirci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zirci_instruction.\n    def exitZirci_instruction(self, ctx:assemblyParser.Zirci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rirc_instruction.\n    def enterS_rirc_instruction(self, ctx:assemblyParser.S_rirc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rirc_instruction.\n    def exitS_rirc_instruction(self, ctx:assemblyParser.S_rirc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rirci_instruction.\n    def enterS_rirci_instruction(self, ctx:assemblyParser.S_rirci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rirci_instruction.\n    def exitS_rirci_instruction(self, ctx:assemblyParser.S_rirci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rirc_instruction.\n    def enterU_rirc_instruction(self, ctx:assemblyParser.U_rirc_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rirc_instruction.\n    def exitU_rirc_instruction(self, ctx:assemblyParser.U_rirc_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rirci_instruction.\n    def enterU_rirci_instruction(self, ctx:assemblyParser.U_rirci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rirci_instruction.\n    def exitU_rirci_instruction(self, ctx:assemblyParser.U_rirci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#r_instruction.\n    def enterR_instruction(self, ctx:assemblyParser.R_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#r_instruction.\n    def exitR_instruction(self, ctx:assemblyParser.R_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rci_instruction.\n    def enterRci_instruction(self, ctx:assemblyParser.Rci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rci_instruction.\n    def exitRci_instruction(self, ctx:assemblyParser.Rci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#z_instruction.\n    def enterZ_instruction(self, ctx:assemblyParser.Z_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#z_instruction.\n    def exitZ_instruction(self, ctx:assemblyParser.Z_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#zci_instruction.\n    def enterZci_instruction(self, ctx:assemblyParser.Zci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#zci_instruction.\n    def exitZci_instruction(self, ctx:assemblyParser.Zci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_r_instruction.\n    def enterS_r_instruction(self, ctx:assemblyParser.S_r_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_r_instruction.\n    def exitS_r_instruction(self, ctx:assemblyParser.S_r_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_rci_instruction.\n    def enterS_rci_instruction(self, ctx:assemblyParser.S_rci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_rci_instruction.\n    def exitS_rci_instruction(self, ctx:assemblyParser.S_rci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_r_instruction.\n    def enterU_r_instruction(self, ctx:assemblyParser.U_r_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_r_instruction.\n    def exitU_r_instruction(self, ctx:assemblyParser.U_r_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_rci_instruction.\n    def enterU_rci_instruction(self, ctx:assemblyParser.U_rci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_rci_instruction.\n    def exitU_rci_instruction(self, ctx:assemblyParser.U_rci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ci_instruction.\n    def enterCi_instruction(self, ctx:assemblyParser.Ci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ci_instruction.\n    def exitCi_instruction(self, ctx:assemblyParser.Ci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#i_instruction.\n    def enterI_instruction(self, ctx:assemblyParser.I_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#i_instruction.\n    def exitI_instruction(self, ctx:assemblyParser.I_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ddci_instruction.\n    def enterDdci_instruction(self, ctx:assemblyParser.Ddci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ddci_instruction.\n    def exitDdci_instruction(self, ctx:assemblyParser.Ddci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#erri_instruction.\n    def enterErri_instruction(self, ctx:assemblyParser.Erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#erri_instruction.\n    def exitErri_instruction(self, ctx:assemblyParser.Erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#edri_instruction.\n    def enterEdri_instruction(self, ctx:assemblyParser.Edri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#edri_instruction.\n    def exitEdri_instruction(self, ctx:assemblyParser.Edri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#s_erri_instruction.\n    def enterS_erri_instruction(self, ctx:assemblyParser.S_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#s_erri_instruction.\n    def exitS_erri_instruction(self, ctx:assemblyParser.S_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#u_erri_instruction.\n    def enterU_erri_instruction(self, ctx:assemblyParser.U_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#u_erri_instruction.\n    def exitU_erri_instruction(self, ctx:assemblyParser.U_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#erii_instruction.\n    def enterErii_instruction(self, ctx:assemblyParser.Erii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#erii_instruction.\n    def exitErii_instruction(self, ctx:assemblyParser.Erii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#erir_instruction.\n    def enterErir_instruction(self, ctx:assemblyParser.Erir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#erir_instruction.\n    def exitErir_instruction(self, ctx:assemblyParser.Erir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#erid_instruction.\n    def enterErid_instruction(self, ctx:assemblyParser.Erid_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#erid_instruction.\n    def exitErid_instruction(self, ctx:assemblyParser.Erid_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#dma_rri_instruction.\n    def enterDma_rri_instruction(self, ctx:assemblyParser.Dma_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#dma_rri_instruction.\n    def exitDma_rri_instruction(self, ctx:assemblyParser.Dma_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#synthetic_sugar_instruction.\n    def enterSynthetic_sugar_instruction(self, ctx:assemblyParser.Synthetic_sugar_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#synthetic_sugar_instruction.\n    def exitSynthetic_sugar_instruction(self, ctx:assemblyParser.Synthetic_sugar_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#rrif_instruction.\n    def enterRrif_instruction(self, ctx:assemblyParser.Rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#rrif_instruction.\n    def exitRrif_instruction(self, ctx:assemblyParser.Rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#andn_rrif_instruction.\n    def enterAndn_rrif_instruction(self, ctx:assemblyParser.Andn_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#andn_rrif_instruction.\n    def exitAndn_rrif_instruction(self, ctx:assemblyParser.Andn_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#nand_rrif_instruction.\n    def enterNand_rrif_instruction(self, ctx:assemblyParser.Nand_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#nand_rrif_instruction.\n    def exitNand_rrif_instruction(self, ctx:assemblyParser.Nand_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#nor_rrif_instruction.\n    def enterNor_rrif_instruction(self, ctx:assemblyParser.Nor_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#nor_rrif_instruction.\n    def exitNor_rrif_instruction(self, ctx:assemblyParser.Nor_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#nxor_rrif_instruction.\n    def enterNxor_rrif_instruction(self, ctx:assemblyParser.Nxor_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#nxor_rrif_instruction.\n    def exitNxor_rrif_instruction(self, ctx:assemblyParser.Nxor_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#orn_rrif_instruction.\n    def enterOrn_rrif_instruction(self, ctx:assemblyParser.Orn_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#orn_rrif_instruction.\n    def exitOrn_rrif_instruction(self, ctx:assemblyParser.Orn_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#hash_rrif_instruction.\n    def enterHash_rrif_instruction(self, ctx:assemblyParser.Hash_rrif_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#hash_rrif_instruction.\n    def exitHash_rrif_instruction(self, ctx:assemblyParser.Hash_rrif_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_instruction.\n    def enterMove_instruction(self, ctx:assemblyParser.Move_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_instruction.\n    def exitMove_instruction(self, ctx:assemblyParser.Move_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_ri_instruction.\n    def enterMove_ri_instruction(self, ctx:assemblyParser.Move_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_ri_instruction.\n    def exitMove_ri_instruction(self, ctx:assemblyParser.Move_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_rici_instruction.\n    def enterMove_rici_instruction(self, ctx:assemblyParser.Move_rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_rici_instruction.\n    def exitMove_rici_instruction(self, ctx:assemblyParser.Move_rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_rr_instruction.\n    def enterMove_rr_instruction(self, ctx:assemblyParser.Move_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_rr_instruction.\n    def exitMove_rr_instruction(self, ctx:assemblyParser.Move_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_rrci_instruction.\n    def enterMove_rrci_instruction(self, ctx:assemblyParser.Move_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_rrci_instruction.\n    def exitMove_rrci_instruction(self, ctx:assemblyParser.Move_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_s_ri_instruction.\n    def enterMove_s_ri_instruction(self, ctx:assemblyParser.Move_s_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_s_ri_instruction.\n    def exitMove_s_ri_instruction(self, ctx:assemblyParser.Move_s_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_s_rici_instruction.\n    def enterMove_s_rici_instruction(self, ctx:assemblyParser.Move_s_rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_s_rici_instruction.\n    def exitMove_s_rici_instruction(self, ctx:assemblyParser.Move_s_rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_s_rr_instruction.\n    def enterMove_s_rr_instruction(self, ctx:assemblyParser.Move_s_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_s_rr_instruction.\n    def exitMove_s_rr_instruction(self, ctx:assemblyParser.Move_s_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_s_rrci_instruction.\n    def enterMove_s_rrci_instruction(self, ctx:assemblyParser.Move_s_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_s_rrci_instruction.\n    def exitMove_s_rrci_instruction(self, ctx:assemblyParser.Move_s_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_u_ri_instruction.\n    def enterMove_u_ri_instruction(self, ctx:assemblyParser.Move_u_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_u_ri_instruction.\n    def exitMove_u_ri_instruction(self, ctx:assemblyParser.Move_u_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_u_rici_instruction.\n    def enterMove_u_rici_instruction(self, ctx:assemblyParser.Move_u_rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_u_rici_instruction.\n    def exitMove_u_rici_instruction(self, ctx:assemblyParser.Move_u_rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_u_rr_instruction.\n    def enterMove_u_rr_instruction(self, ctx:assemblyParser.Move_u_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_u_rr_instruction.\n    def exitMove_u_rr_instruction(self, ctx:assemblyParser.Move_u_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#move_u_rrci_instruction.\n    def enterMove_u_rrci_instruction(self, ctx:assemblyParser.Move_u_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#move_u_rrci_instruction.\n    def exitMove_u_rrci_instruction(self, ctx:assemblyParser.Move_u_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#neg_instruction.\n    def enterNeg_instruction(self, ctx:assemblyParser.Neg_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#neg_instruction.\n    def exitNeg_instruction(self, ctx:assemblyParser.Neg_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#neg_rr_instruction.\n    def enterNeg_rr_instruction(self, ctx:assemblyParser.Neg_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#neg_rr_instruction.\n    def exitNeg_rr_instruction(self, ctx:assemblyParser.Neg_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#neg_rrci_instruction.\n    def enterNeg_rrci_instruction(self, ctx:assemblyParser.Neg_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#neg_rrci_instruction.\n    def exitNeg_rrci_instruction(self, ctx:assemblyParser.Neg_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#not_instruction.\n    def enterNot_instruction(self, ctx:assemblyParser.Not_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#not_instruction.\n    def exitNot_instruction(self, ctx:assemblyParser.Not_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#not_rr_instruction.\n    def enterNot_rr_instruction(self, ctx:assemblyParser.Not_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#not_rr_instruction.\n    def exitNot_rr_instruction(self, ctx:assemblyParser.Not_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#not_rrci_instruction.\n    def enterNot_rrci_instruction(self, ctx:assemblyParser.Not_rrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#not_rrci_instruction.\n    def exitNot_rrci_instruction(self, ctx:assemblyParser.Not_rrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#not_zrci_instruction.\n    def enterNot_zrci_instruction(self, ctx:assemblyParser.Not_zrci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#not_zrci_instruction.\n    def exitNot_zrci_instruction(self, ctx:assemblyParser.Not_zrci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jump_instruction.\n    def enterJump_instruction(self, ctx:assemblyParser.Jump_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jump_instruction.\n    def exitJump_instruction(self, ctx:assemblyParser.Jump_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jeq_rii_instruction.\n    def enterJeq_rii_instruction(self, ctx:assemblyParser.Jeq_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jeq_rii_instruction.\n    def exitJeq_rii_instruction(self, ctx:assemblyParser.Jeq_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jeq_rri_instruction.\n    def enterJeq_rri_instruction(self, ctx:assemblyParser.Jeq_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jeq_rri_instruction.\n    def exitJeq_rri_instruction(self, ctx:assemblyParser.Jeq_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jneq_rii_instruction.\n    def enterJneq_rii_instruction(self, ctx:assemblyParser.Jneq_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jneq_rii_instruction.\n    def exitJneq_rii_instruction(self, ctx:assemblyParser.Jneq_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jneq_rri_instruction.\n    def enterJneq_rri_instruction(self, ctx:assemblyParser.Jneq_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jneq_rri_instruction.\n    def exitJneq_rri_instruction(self, ctx:assemblyParser.Jneq_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jz_ri_instruction.\n    def enterJz_ri_instruction(self, ctx:assemblyParser.Jz_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jz_ri_instruction.\n    def exitJz_ri_instruction(self, ctx:assemblyParser.Jz_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jnz_ri_instruction.\n    def enterJnz_ri_instruction(self, ctx:assemblyParser.Jnz_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jnz_ri_instruction.\n    def exitJnz_ri_instruction(self, ctx:assemblyParser.Jnz_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jltu_rii_instruction.\n    def enterJltu_rii_instruction(self, ctx:assemblyParser.Jltu_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jltu_rii_instruction.\n    def exitJltu_rii_instruction(self, ctx:assemblyParser.Jltu_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jltu_rri_instruction.\n    def enterJltu_rri_instruction(self, ctx:assemblyParser.Jltu_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jltu_rri_instruction.\n    def exitJltu_rri_instruction(self, ctx:assemblyParser.Jltu_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgtu_rii_instruction.\n    def enterJgtu_rii_instruction(self, ctx:assemblyParser.Jgtu_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgtu_rii_instruction.\n    def exitJgtu_rii_instruction(self, ctx:assemblyParser.Jgtu_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgtu_rri_instruction.\n    def enterJgtu_rri_instruction(self, ctx:assemblyParser.Jgtu_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgtu_rri_instruction.\n    def exitJgtu_rri_instruction(self, ctx:assemblyParser.Jgtu_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jleu_rii_instruction.\n    def enterJleu_rii_instruction(self, ctx:assemblyParser.Jleu_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jleu_rii_instruction.\n    def exitJleu_rii_instruction(self, ctx:assemblyParser.Jleu_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jleu_rri_instruction.\n    def enterJleu_rri_instruction(self, ctx:assemblyParser.Jleu_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jleu_rri_instruction.\n    def exitJleu_rri_instruction(self, ctx:assemblyParser.Jleu_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgeu_rii_instruction.\n    def enterJgeu_rii_instruction(self, ctx:assemblyParser.Jgeu_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgeu_rii_instruction.\n    def exitJgeu_rii_instruction(self, ctx:assemblyParser.Jgeu_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgeu_rri_instruction.\n    def enterJgeu_rri_instruction(self, ctx:assemblyParser.Jgeu_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgeu_rri_instruction.\n    def exitJgeu_rri_instruction(self, ctx:assemblyParser.Jgeu_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jlts_rii_instruction.\n    def enterJlts_rii_instruction(self, ctx:assemblyParser.Jlts_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jlts_rii_instruction.\n    def exitJlts_rii_instruction(self, ctx:assemblyParser.Jlts_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jlts_rri_instruction.\n    def enterJlts_rri_instruction(self, ctx:assemblyParser.Jlts_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jlts_rri_instruction.\n    def exitJlts_rri_instruction(self, ctx:assemblyParser.Jlts_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgts_rii_instruction.\n    def enterJgts_rii_instruction(self, ctx:assemblyParser.Jgts_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgts_rii_instruction.\n    def exitJgts_rii_instruction(self, ctx:assemblyParser.Jgts_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jgts_rri_instruction.\n    def enterJgts_rri_instruction(self, ctx:assemblyParser.Jgts_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jgts_rri_instruction.\n    def exitJgts_rri_instruction(self, ctx:assemblyParser.Jgts_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jles_rii_instruction.\n    def enterJles_rii_instruction(self, ctx:assemblyParser.Jles_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jles_rii_instruction.\n    def exitJles_rii_instruction(self, ctx:assemblyParser.Jles_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jles_rri_instruction.\n    def enterJles_rri_instruction(self, ctx:assemblyParser.Jles_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jles_rri_instruction.\n    def exitJles_rri_instruction(self, ctx:assemblyParser.Jles_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jges_rii_instruction.\n    def enterJges_rii_instruction(self, ctx:assemblyParser.Jges_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jges_rii_instruction.\n    def exitJges_rii_instruction(self, ctx:assemblyParser.Jges_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jges_rri_instruction.\n    def enterJges_rri_instruction(self, ctx:assemblyParser.Jges_rri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jges_rri_instruction.\n    def exitJges_rri_instruction(self, ctx:assemblyParser.Jges_rri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jump_ri_instruction.\n    def enterJump_ri_instruction(self, ctx:assemblyParser.Jump_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jump_ri_instruction.\n    def exitJump_ri_instruction(self, ctx:assemblyParser.Jump_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jump_i_instruction.\n    def enterJump_i_instruction(self, ctx:assemblyParser.Jump_i_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jump_i_instruction.\n    def exitJump_i_instruction(self, ctx:assemblyParser.Jump_i_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#jump_r_instruction.\n    def enterJump_r_instruction(self, ctx:assemblyParser.Jump_r_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#jump_r_instruction.\n    def exitJump_r_instruction(self, ctx:assemblyParser.Jump_r_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#shortcut_instruction.\n    def enterShortcut_instruction(self, ctx:assemblyParser.Shortcut_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#shortcut_instruction.\n    def exitShortcut_instruction(self, ctx:assemblyParser.Shortcut_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#div_step_drdici_instruction.\n    def enterDiv_step_drdici_instruction(self, ctx:assemblyParser.Div_step_drdici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#div_step_drdici_instruction.\n    def exitDiv_step_drdici_instruction(self, ctx:assemblyParser.Div_step_drdici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#mul_step_drdici_instruction.\n    def enterMul_step_drdici_instruction(self, ctx:assemblyParser.Mul_step_drdici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#mul_step_drdici_instruction.\n    def exitMul_step_drdici_instruction(self, ctx:assemblyParser.Mul_step_drdici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#boot_rici_instruction.\n    def enterBoot_rici_instruction(self, ctx:assemblyParser.Boot_rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#boot_rici_instruction.\n    def exitBoot_rici_instruction(self, ctx:assemblyParser.Boot_rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#resume_rici_instruction.\n    def enterResume_rici_instruction(self, ctx:assemblyParser.Resume_rici_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#resume_rici_instruction.\n    def exitResume_rici_instruction(self, ctx:assemblyParser.Resume_rici_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#stop_ci_instruction.\n    def enterStop_ci_instruction(self, ctx:assemblyParser.Stop_ci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#stop_ci_instruction.\n    def exitStop_ci_instruction(self, ctx:assemblyParser.Stop_ci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#call_ri_instruction.\n    def enterCall_ri_instruction(self, ctx:assemblyParser.Call_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#call_ri_instruction.\n    def exitCall_ri_instruction(self, ctx:assemblyParser.Call_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#call_rr_instruction.\n    def enterCall_rr_instruction(self, ctx:assemblyParser.Call_rr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#call_rr_instruction.\n    def exitCall_rr_instruction(self, ctx:assemblyParser.Call_rr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#bkp_instruction.\n    def enterBkp_instruction(self, ctx:assemblyParser.Bkp_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#bkp_instruction.\n    def exitBkp_instruction(self, ctx:assemblyParser.Bkp_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#movd_ddci_instruction.\n    def enterMovd_ddci_instruction(self, ctx:assemblyParser.Movd_ddci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#movd_ddci_instruction.\n    def exitMovd_ddci_instruction(self, ctx:assemblyParser.Movd_ddci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#swapd_ddci_instruction.\n    def enterSwapd_ddci_instruction(self, ctx:assemblyParser.Swapd_ddci_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#swapd_ddci_instruction.\n    def exitSwapd_ddci_instruction(self, ctx:assemblyParser.Swapd_ddci_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#time_cfg_zr_instruction.\n    def enterTime_cfg_zr_instruction(self, ctx:assemblyParser.Time_cfg_zr_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#time_cfg_zr_instruction.\n    def exitTime_cfg_zr_instruction(self, ctx:assemblyParser.Time_cfg_zr_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lbs_erri_instruction.\n    def enterLbs_erri_instruction(self, ctx:assemblyParser.Lbs_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lbs_erri_instruction.\n    def exitLbs_erri_instruction(self, ctx:assemblyParser.Lbs_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lbs_s_erri_instruction.\n    def enterLbs_s_erri_instruction(self, ctx:assemblyParser.Lbs_s_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lbs_s_erri_instruction.\n    def exitLbs_s_erri_instruction(self, ctx:assemblyParser.Lbs_s_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lbu_erri_instruction.\n    def enterLbu_erri_instruction(self, ctx:assemblyParser.Lbu_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lbu_erri_instruction.\n    def exitLbu_erri_instruction(self, ctx:assemblyParser.Lbu_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lbu_u_erri_instruction.\n    def enterLbu_u_erri_instruction(self, ctx:assemblyParser.Lbu_u_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lbu_u_erri_instruction.\n    def exitLbu_u_erri_instruction(self, ctx:assemblyParser.Lbu_u_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#ld_edri_instruction.\n    def enterLd_edri_instruction(self, ctx:assemblyParser.Ld_edri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#ld_edri_instruction.\n    def exitLd_edri_instruction(self, ctx:assemblyParser.Ld_edri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lhs_erri_instruction.\n    def enterLhs_erri_instruction(self, ctx:assemblyParser.Lhs_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lhs_erri_instruction.\n    def exitLhs_erri_instruction(self, ctx:assemblyParser.Lhs_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lhs_s_erri_instruction.\n    def enterLhs_s_erri_instruction(self, ctx:assemblyParser.Lhs_s_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lhs_s_erri_instruction.\n    def exitLhs_s_erri_instruction(self, ctx:assemblyParser.Lhs_s_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lhu_erri_instruction.\n    def enterLhu_erri_instruction(self, ctx:assemblyParser.Lhu_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lhu_erri_instruction.\n    def exitLhu_erri_instruction(self, ctx:assemblyParser.Lhu_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lhu_u_erri_instruction.\n    def enterLhu_u_erri_instruction(self, ctx:assemblyParser.Lhu_u_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lhu_u_erri_instruction.\n    def exitLhu_u_erri_instruction(self, ctx:assemblyParser.Lhu_u_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lw_erri_instruction.\n    def enterLw_erri_instruction(self, ctx:assemblyParser.Lw_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lw_erri_instruction.\n    def exitLw_erri_instruction(self, ctx:assemblyParser.Lw_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lw_s_erri_instruction.\n    def enterLw_s_erri_instruction(self, ctx:assemblyParser.Lw_s_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lw_s_erri_instruction.\n    def exitLw_s_erri_instruction(self, ctx:assemblyParser.Lw_s_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#lw_u_erri_instruction.\n    def enterLw_u_erri_instruction(self, ctx:assemblyParser.Lw_u_erri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#lw_u_erri_instruction.\n    def exitLw_u_erri_instruction(self, ctx:assemblyParser.Lw_u_erri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sb_erii_instruction.\n    def enterSb_erii_instruction(self, ctx:assemblyParser.Sb_erii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sb_erii_instruction.\n    def exitSb_erii_instruction(self, ctx:assemblyParser.Sb_erii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sb_erir_instruction.\n    def enterSb_erir_instruction(self, ctx:assemblyParser.Sb_erir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sb_erir_instruction.\n    def exitSb_erir_instruction(self, ctx:assemblyParser.Sb_erir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sb_id_rii_instruction.\n    def enterSb_id_rii_instruction(self, ctx:assemblyParser.Sb_id_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sb_id_rii_instruction.\n    def exitSb_id_rii_instruction(self, ctx:assemblyParser.Sb_id_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sb_id_ri_instruction.\n    def enterSb_id_ri_instruction(self, ctx:assemblyParser.Sb_id_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sb_id_ri_instruction.\n    def exitSb_id_ri_instruction(self, ctx:assemblyParser.Sb_id_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sd_erii_instruction.\n    def enterSd_erii_instruction(self, ctx:assemblyParser.Sd_erii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sd_erii_instruction.\n    def exitSd_erii_instruction(self, ctx:assemblyParser.Sd_erii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sd_erid_instruction.\n    def enterSd_erid_instruction(self, ctx:assemblyParser.Sd_erid_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sd_erid_instruction.\n    def exitSd_erid_instruction(self, ctx:assemblyParser.Sd_erid_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sd_id_rii_instruction.\n    def enterSd_id_rii_instruction(self, ctx:assemblyParser.Sd_id_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sd_id_rii_instruction.\n    def exitSd_id_rii_instruction(self, ctx:assemblyParser.Sd_id_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sd_id_ri_instruction.\n    def enterSd_id_ri_instruction(self, ctx:assemblyParser.Sd_id_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sd_id_ri_instruction.\n    def exitSd_id_ri_instruction(self, ctx:assemblyParser.Sd_id_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sh_erii_instruction.\n    def enterSh_erii_instruction(self, ctx:assemblyParser.Sh_erii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sh_erii_instruction.\n    def exitSh_erii_instruction(self, ctx:assemblyParser.Sh_erii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sh_erir_instruction.\n    def enterSh_erir_instruction(self, ctx:assemblyParser.Sh_erir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sh_erir_instruction.\n    def exitSh_erir_instruction(self, ctx:assemblyParser.Sh_erir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sh_id_rii_instruction.\n    def enterSh_id_rii_instruction(self, ctx:assemblyParser.Sh_id_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sh_id_rii_instruction.\n    def exitSh_id_rii_instruction(self, ctx:assemblyParser.Sh_id_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sh_id_ri_instruction.\n    def enterSh_id_ri_instruction(self, ctx:assemblyParser.Sh_id_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sh_id_ri_instruction.\n    def exitSh_id_ri_instruction(self, ctx:assemblyParser.Sh_id_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sw_erii_instruction.\n    def enterSw_erii_instruction(self, ctx:assemblyParser.Sw_erii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sw_erii_instruction.\n    def exitSw_erii_instruction(self, ctx:assemblyParser.Sw_erii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sw_erir_instruction.\n    def enterSw_erir_instruction(self, ctx:assemblyParser.Sw_erir_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sw_erir_instruction.\n    def exitSw_erir_instruction(self, ctx:assemblyParser.Sw_erir_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sw_id_rii_instruction.\n    def enterSw_id_rii_instruction(self, ctx:assemblyParser.Sw_id_rii_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sw_id_rii_instruction.\n    def exitSw_id_rii_instruction(self, ctx:assemblyParser.Sw_id_rii_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#sw_id_ri_instruction.\n    def enterSw_id_ri_instruction(self, ctx:assemblyParser.Sw_id_ri_instructionContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#sw_id_ri_instruction.\n    def exitSw_id_ri_instruction(self, ctx:assemblyParser.Sw_id_ri_instructionContext):\n        pass\n\n\n    # Enter a parse tree produced by assemblyParser#label.\n    def enterLabel(self, ctx:assemblyParser.LabelContext):\n        pass\n\n    # Exit a parse tree produced by assemblyParser#label.\n    def exitLabel(self, ctx:assemblyParser.LabelContext):\n        pass\n\n\n\ndel assemblyParser"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar/assemblyParser.py",
    "content": "# Generated from assembly.g4 by ANTLR 4.9.2\n# encoding: utf-8\nfrom antlr4 import *\nfrom io import StringIO\nimport sys\nif sys.version_info[1] > 5:\n\tfrom typing import TextIO\nelse:\n\tfrom typing.io import TextIO\n\n\ndef serializedATN():\n    with StringIO() as buf:\n        buf.write(\"\\3\\u608b\\ua72a\\u8133\\ub9ed\\u417c\\u3be7\\u7786\\u5964\\3\\u00de\")\n        buf.write(\"\\u0919\\4\\2\\t\\2\\4\\3\\t\\3\\4\\4\\t\\4\\4\\5\\t\\5\\4\\6\\t\\6\\4\\7\\t\\7\")\n        buf.write(\"\\4\\b\\t\\b\\4\\t\\t\\t\\4\\n\\t\\n\\4\\13\\t\\13\\4\\f\\t\\f\\4\\r\\t\\r\\4\\16\")\n        buf.write(\"\\t\\16\\4\\17\\t\\17\\4\\20\\t\\20\\4\\21\\t\\21\\4\\22\\t\\22\\4\\23\\t\\23\")\n        buf.write(\"\\4\\24\\t\\24\\4\\25\\t\\25\\4\\26\\t\\26\\4\\27\\t\\27\\4\\30\\t\\30\\4\\31\")\n        buf.write(\"\\t\\31\\4\\32\\t\\32\\4\\33\\t\\33\\4\\34\\t\\34\\4\\35\\t\\35\\4\\36\\t\\36\")\n        buf.write(\"\\4\\37\\t\\37\\4 \\t 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buf.write(\"\\7\\6\\2\\2\\u0867\\u0868\\5\\60\\31\\2\\u0868\\u0193\\3\\2\\2\\2\\u0869\")\n        buf.write(\"\\u086a\\7N\\2\\2\\u086a\\u086b\\7\\u00d6\\2\\2\\u086b\\u086c\\7\\6\")\n        buf.write(\"\\2\\2\\u086c\\u086d\\7\\u00da\\2\\2\\u086d\\u086e\\7\\6\\2\\2\\u086e\")\n        buf.write(\"\\u086f\\5.\\30\\2\\u086f\\u0870\\7\\6\\2\\2\\u0870\\u0871\\5\\60\\31\")\n        buf.write(\"\\2\\u0871\\u0195\\3\\2\\2\\2\\u0872\\u0873\\7O\\2\\2\\u0873\\u0874\")\n        buf.write(\"\\7\\6\\2\\2\\u0874\\u0875\\7\\u00d9\\2\\2\\u0875\\u0876\\7\\6\\2\\2\\u0876\")\n        buf.write(\"\\u0877\\5.\\30\\2\\u0877\\u0878\\7\\6\\2\\2\\u0878\\u0879\\5\\60\\31\")\n        buf.write(\"\\2\\u0879\\u0197\\3\\2\\2\\2\\u087a\\u087b\\7O\\2\\2\\u087b\\u087c\")\n        buf.write(\"\\7\\u00d7\\2\\2\\u087c\\u087d\\7\\6\\2\\2\\u087d\\u087e\\7\\u00da\\2\")\n        buf.write(\"\\2\\u087e\\u087f\\7\\6\\2\\2\\u087f\\u0880\\5.\\30\\2\\u0880\\u0881\")\n        buf.write(\"\\7\\6\\2\\2\\u0881\\u0882\\5\\60\\31\\2\\u0882\\u0199\\3\\2\\2\\2\\u0883\")\n        buf.write(\"\\u0884\\7P\\2\\2\\u0884\\u0885\\7\\6\\2\\2\\u0885\\u0886\\7\\u00d9\")\n        buf.write(\"\\2\\2\\u0886\\u0887\\7\\6\\2\\2\\u0887\\u0888\\5.\\30\\2\\u0888\\u0889\")\n        buf.write(\"\\7\\6\\2\\2\\u0889\\u088a\\5\\60\\31\\2\\u088a\\u019b\\3\\2\\2\\2\\u088b\")\n        buf.write(\"\\u088c\\7P\\2\\2\\u088c\\u088d\\7\\u00d6\\2\\2\\u088d\\u088e\\7\\6\")\n        buf.write(\"\\2\\2\\u088e\\u088f\\7\\u00da\\2\\2\\u088f\\u0890\\7\\6\\2\\2\\u0890\")\n        buf.write(\"\\u0891\\5.\\30\\2\\u0891\\u0892\\7\\6\\2\\2\\u0892\\u0893\\5\\60\\31\")\n        buf.write(\"\\2\\u0893\\u019d\\3\\2\\2\\2\\u0894\\u0895\\7P\\2\\2\\u0895\\u0896\")\n        buf.write(\"\\7\\u00d7\\2\\2\\u0896\\u0897\\7\\6\\2\\2\\u0897\\u0898\\7\\u00da\\2\")\n        buf.write(\"\\2\\u0898\\u0899\\7\\6\\2\\2\\u0899\\u089a\\5.\\30\\2\\u089a\\u089b\")\n        buf.write(\"\\7\\6\\2\\2\\u089b\\u089c\\5\\60\\31\\2\\u089c\\u019f\\3\\2\\2\\2\\u089d\")\n        buf.write(\"\\u089e\\7Q\\2\\2\\u089e\\u089f\\7\\6\\2\\2\\u089f\\u08a0\\5.\\30\\2\")\n        buf.write(\"\\u08a0\\u08a1\\7\\6\\2\\2\\u08a1\\u08a2\\5\\b\\5\\2\\u08a2\\u08a3\\7\")\n        buf.write(\"\\6\\2\\2\\u08a3\\u08a4\\5\\60\\31\\2\\u08a4\\u01a1\\3\\2\\2\\2\\u08a5\")\n        buf.write(\"\\u08a6\\7Q\\2\\2\\u08a6\\u08a7\\7\\6\\2\\2\\u08a7\\u08a8\\5.\\30\\2\")\n        buf.write(\"\\u08a8\\u08a9\\7\\6\\2\\2\\u08a9\\u08aa\\5\\60\\31\\2\\u08aa\\u08ab\")\n        buf.write(\"\\7\\6\\2\\2\\u08ab\\u08ac\\5.\\30\\2\\u08ac\\u01a3\\3\\2\\2\\2\\u08ad\")\n        buf.write(\"\\u08ae\\7Q\\2\\2\\u08ae\\u08af\\7\\6\\2\\2\\u08af\\u08b0\\5.\\30\\2\")\n        buf.write(\"\\u08b0\\u08b1\\7\\6\\2\\2\\u08b1\\u08b2\\5\\b\\5\\2\\u08b2\\u08b3\\7\")\n        buf.write(\"\\6\\2\\2\\u08b3\\u08b4\\5\\b\\5\\2\\u08b4\\u01a5\\3\\2\\2\\2\\u08b5\\u08b6\")\n        buf.write(\"\\7Q\\2\\2\\u08b6\\u08b7\\7\\6\\2\\2\\u08b7\\u08b8\\5.\\30\\2\\u08b8\")\n        buf.write(\"\\u08b9\\7\\6\\2\\2\\u08b9\\u08ba\\5\\b\\5\\2\\u08ba\\u01a7\\3\\2\\2\\2\")\n        buf.write(\"\\u08bb\\u08bc\\7S\\2\\2\\u08bc\\u08bd\\7\\6\\2\\2\\u08bd\\u08be\\5\")\n        buf.write(\".\\30\\2\\u08be\\u08bf\\7\\6\\2\\2\\u08bf\\u08c0\\5\\60\\31\\2\\u08c0\")\n        buf.write(\"\\u08c1\\7\\6\\2\\2\\u08c1\\u08c2\\5\\60\\31\\2\\u08c2\\u01a9\\3\\2\\2\")\n        buf.write(\"\\2\\u08c3\\u08c4\\7S\\2\\2\\u08c4\\u08c5\\7\\6\\2\\2\\u08c5\\u08c6\")\n        buf.write(\"\\5.\\30\\2\\u08c6\\u08c7\\7\\6\\2\\2\\u08c7\\u08c8\\5\\60\\31\\2\\u08c8\")\n        buf.write(\"\\u08c9\\7\\6\\2\\2\\u08c9\\u08ca\\7\\u00da\\2\\2\\u08ca\\u01ab\\3\\2\")\n        buf.write(\"\\2\\2\\u08cb\\u08cc\\7S\\2\\2\\u08cc\\u08cd\\7\\6\\2\\2\\u08cd\\u08ce\")\n        buf.write(\"\\5.\\30\\2\\u08ce\\u08cf\\7\\6\\2\\2\\u08cf\\u08d0\\5\\b\\5\\2\\u08d0\")\n        buf.write(\"\\u08d1\\7\\6\\2\\2\\u08d1\\u08d2\\5\\b\\5\\2\\u08d2\\u01ad\\3\\2\\2\\2\")\n        buf.write(\"\\u08d3\\u08d4\\7S\\2\\2\\u08d4\\u08d5\\7\\6\\2\\2\\u08d5\\u08d6\\5\")\n        buf.write(\".\\30\\2\\u08d6\\u08d7\\7\\6\\2\\2\\u08d7\\u08d8\\5\\b\\5\\2\\u08d8\\u01af\")\n        buf.write(\"\\3\\2\\2\\2\\u08d9\\u08da\\7U\\2\\2\\u08da\\u08db\\7\\6\\2\\2\\u08db\")\n        buf.write(\"\\u08dc\\5.\\30\\2\\u08dc\\u08dd\\7\\6\\2\\2\\u08dd\\u08de\\5\\b\\5\\2\")\n        buf.write(\"\\u08de\\u08df\\7\\6\\2\\2\\u08df\\u08e0\\5\\60\\31\\2\\u08e0\\u01b1\")\n        buf.write(\"\\3\\2\\2\\2\\u08e1\\u08e2\\7U\\2\\2\\u08e2\\u08e3\\7\\6\\2\\2\\u08e3\")\n        buf.write(\"\\u08e4\\5.\\30\\2\\u08e4\\u08e5\\7\\6\\2\\2\\u08e5\\u08e6\\5\\60\\31\")\n        buf.write(\"\\2\\u08e6\\u08e7\\7\\6\\2\\2\\u08e7\\u08e8\\5.\\30\\2\\u08e8\\u01b3\")\n        buf.write(\"\\3\\2\\2\\2\\u08e9\\u08ea\\7U\\2\\2\\u08ea\\u08eb\\7\\6\\2\\2\\u08eb\")\n        buf.write(\"\\u08ec\\5.\\30\\2\\u08ec\\u08ed\\7\\6\\2\\2\\u08ed\\u08ee\\5\\b\\5\\2\")\n        buf.write(\"\\u08ee\\u08ef\\7\\6\\2\\2\\u08ef\\u08f0\\5\\b\\5\\2\\u08f0\\u01b5\\3\")\n        buf.write(\"\\2\\2\\2\\u08f1\\u08f2\\7U\\2\\2\\u08f2\\u08f3\\7\\6\\2\\2\\u08f3\\u08f4\")\n        buf.write(\"\\5.\\30\\2\\u08f4\\u08f5\\7\\6\\2\\2\\u08f5\\u08f6\\5\\b\\5\\2\\u08f6\")\n        buf.write(\"\\u01b7\\3\\2\\2\\2\\u08f7\\u08f8\\7W\\2\\2\\u08f8\\u08f9\\7\\6\\2\\2\")\n        buf.write(\"\\u08f9\\u08fa\\5.\\30\\2\\u08fa\\u08fb\\7\\6\\2\\2\\u08fb\\u08fc\\5\")\n        buf.write(\"\\b\\5\\2\\u08fc\\u08fd\\7\\6\\2\\2\\u08fd\\u08fe\\5\\60\\31\\2\\u08fe\")\n        buf.write(\"\\u01b9\\3\\2\\2\\2\\u08ff\\u0900\\7W\\2\\2\\u0900\\u0901\\7\\6\\2\\2\")\n        buf.write(\"\\u0901\\u0902\\5.\\30\\2\\u0902\\u0903\\7\\6\\2\\2\\u0903\\u0904\\5\")\n        buf.write(\"\\60\\31\\2\\u0904\\u0905\\7\\6\\2\\2\\u0905\\u0906\\5.\\30\\2\\u0906\")\n        buf.write(\"\\u01bb\\3\\2\\2\\2\\u0907\\u0908\\7W\\2\\2\\u0908\\u0909\\7\\6\\2\\2\")\n        buf.write(\"\\u0909\\u090a\\5.\\30\\2\\u090a\\u090b\\7\\6\\2\\2\\u090b\\u090c\\5\")\n        buf.write(\"\\b\\5\\2\\u090c\\u090d\\7\\6\\2\\2\\u090d\\u090e\\5\\b\\5\\2\\u090e\\u01bd\")\n        buf.write(\"\\3\\2\\2\\2\\u090f\\u0910\\7W\\2\\2\\u0910\\u0911\\7\\6\\2\\2\\u0911\")\n        buf.write(\"\\u0912\\5.\\30\\2\\u0912\\u0913\\7\\6\\2\\2\\u0913\\u0914\\5\\b\\5\\2\")\n        buf.write(\"\\u0914\\u01bf\\3\\2\\2\\2\\u0915\\u0916\\7\\u00db\\2\\2\\u0916\\u0917\")\n        buf.write(\"\\7\\7\\2\\2\\u0917\\u01c1\\3\\2\\2\\2\\26\\u01c5\\u01c7\\u01d5\\u01fd\")\n        buf.write(\"\\u0202\\u020f\\u022a\\u025c\\u0277\\u02ad\\u02e1\\u032f\\u0586\")\n        buf.write(\"\\u0616\\u061e\\u065c\\u06c8\\u06dd\\u0710\\u07f3\")\n        return buf.getvalue()\n\n\nclass assemblyParser ( Parser ):\n\n    grammarFileName = \"assembly.g4\"\n\n    atn = ATNDeserializer().deserialize(serializedATN())\n\n    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]\n\n    sharedContextCache = PredictionContextCache()\n\n    literalNames = [ \"<INVALID>\", \"'-'\", \"'0x'\", \"'+'\", \"','\", \"':'\", \"'$acquire'\", \n                     \"'$release'\", \"'$boot'\", \"'$resume'\", \"'$add'\", \"'$addc'\", \n                     \"'$and'\", \"'$andn'\", \"'$asr'\", \"'$cmpb4'\", \"'$lsl'\", \n                     \"'$lsl1'\", \"'$lsl1x'\", \"'$lslx'\", \"'$lsr'\", \"'$lsr1'\", \n                     \"'$lsr1x'\", \"'$lsrx'\", \"'$mul_sh_sh'\", \"'$mul_sh_sl'\", \n                     \"'$mul_sh_uh'\", \"'$mul_sh_ul'\", \"'$mul_sl_sh'\", \"'$mul_sl_sl'\", \n                     \"'$mul_sl_uh'\", \"'$mul_sl_ul'\", \"'$mul_uh_uh'\", \"'$mul_uh_ul'\", \n                     \"'$mul_ul_uh'\", \"'$mul_ul_ul'\", \"'$nand'\", \"'$nor'\", \n                     \"'$nxor'\", \"'$or'\", \"'$orn'\", \"'$rol'\", \"'$ror'\", \"'$rsub'\", \n                     \"'$rsubc'\", \"'$sub'\", \"'$subc'\", \"'$xor'\", \"'$call'\", \n                     \"'$hash'\", \"'$cao'\", \"'$clo'\", \"'$cls'\", \"'$clz'\", \n                     \"'$extsb'\", \"'$extsh'\", \"'$extub'\", \"'$extuh'\", \"'$sats'\", \n                     \"'$time_cfg'\", \"'$div_step'\", \"'$mul_step'\", \"'$lsl_add'\", \n                     \"'$lsl_sub'\", \"'$lsr_add'\", \"'$rol_add'\", \"'$ror_add'\", \n                     \"'$time'\", \"'$nop'\", \"'$stop'\", \"'$fault'\", \"'$movd'\", \n                     \"'$swapd'\", \"'$lbs'\", \"'$lbu'\", \"'$ld'\", \"'$lhs'\", \n                     \"'$lhu'\", \"'$lw'\", \"'$sb'\", \"'$sb_id'\", \"'$sd'\", \"'$sd_id'\", \n                     \"'$sh'\", \"'$sh_id'\", \"'$sw'\", \"'$sw_id'\", \"'$ldma'\", \n                     \"'$ldmai'\", \"'$sdma'\", \"'$move'\", \"'$neg'\", \"'$not'\", \n                     \"'$bkp'\", \"'$jeq'\", \"'$jneq'\", \"'$jz'\", \"'$jnz'\", \"'$jltu'\", \n                     \"'$jgtu'\", \"'$jleu'\", \"'$jgeu'\", \"'$jlts'\", \"'$jgts'\", \n                     \"'$jles'\", \"'$jges'\", \"'$jump'\", \"'%atomic'\", \"'%bss'\", \n                     \"'%data'\", \"'%debug_abbrev'\", \"'%debug_frame'\", \"'%debug_info'\", \n                     \"'%debug_line'\", \"'%debug_loc'\", \"'%debug_ranges'\", \n                     \"'%debug_str'\", \"'%dpu_host'\", \"'%mram'\", \"'%rodata'\", \n                     \"'%stack_sizes'\", \"'%text'\", \"'@progbits'\", \"'@nobits'\", \n                     \"'@function'\", \"'@object'\", \"'true'\", \"'false'\", \"'z'\", \n                     \"'nz'\", \"'e'\", \"'o'\", \"'pl'\", \"'mi'\", \"'ov'\", \"'nov'\", \n                     \"'c'\", \"'nc'\", \"'sz'\", \"'snz'\", \"'spl'\", \"'smi'\", \"'so'\", \n                     \"'se'\", \"'nc5'\", \"'nc6'\", \"'nc7'\", \"'nc8'\", \"'nc9'\", \n                     \"'nc10'\", \"'nc11'\", \"'nc12'\", \"'nc13'\", \"'nc14'\", \"'max'\", \n                     \"'nmax'\", \"'sh32'\", \"'nsh32'\", \"'eq'\", \"'neq'\", \"'ltu'\", \n                     \"'leu'\", \"'gtu'\", \"'geu'\", \"'lts'\", \"'les'\", \"'gts'\", \n                     \"'ges'\", \"'xz'\", \"'xnz'\", \"'xleu'\", \"'xgtu'\", \"'xles'\", \n                     \"'xgts'\", \"'small'\", \"'large'\", \"'!little'\", \"'!big'\", \n                     \"'zero'\", \"'one'\", \"'id'\", \"'id2'\", \"'id4'\", \"'id8'\", \n                     \"'lneg'\", \"'mneg'\", \"'$addrsig'\", \"'$addrsig_sym'\", \n                     \"'$ascii'\", \"'$asciz'\", \"'$byte'\", \"'$cfi_def_cfa_offset'\", \n                     \"'$cfi_endproc'\", \"'$cfi_offset'\", \"'$cfi_sections'\", \n                     \"'$cfi_startproc'\", \"'$file'\", \"'$globl'\", \"'$loc'\", \n                     \"'$long'\", \"'$p2align'\", \"'$quad'\", \"'$section'\", \"'$set'\", \n                     \"'$short'\", \"'$size'\", \"'$text'\", \"'$type'\", \"'$weak'\", \n                     \"'$zero'\", \"'is_stmt'\", \"'prologue_end'\", \"'.s'\", \"'.u'\" ]\n\n    symbolicNames = [ \"<INVALID>\", \"<INVALID>\", \"<INVALID>\", \"<INVALID>\", \n                      \"<INVALID>\", \"<INVALID>\", \"ACQUIRE\", \"RELEASE\", \"BOOT\", \n                      \"RESUME\", \"ADD\", \"ADDC\", \"AND\", \"ANDN\", \"ASR\", \"CMPB4\", \n                      \"LSL\", \"LSL1\", \"LSL1X\", \"LSLX\", \"LSR\", \"LSR1\", \"LSR1X\", \n                      \"LSRX\", \"MUL_SH_SH\", \"MUL_SH_SL\", \"MUL_SH_UH\", \"MUL_SH_UL\", \n                      \"MUL_SL_SH\", \"MUL_SL_SL\", \"MUL_SL_UH\", \"MUL_SL_UL\", \n                      \"MUL_UH_UH\", \"MUL_UH_UL\", \"MUL_UL_UH\", \"MUL_UL_UL\", \n                      \"NAND\", \"NOR\", \"NXOR\", \"OR\", \"ORN\", \"ROL\", \"ROR\", \n                      \"RSUB\", \"RSUBC\", \"SUB\", \"SUBC\", \"XOR\", \"CALL\", \"HASH\", \n                      \"CAO\", \"CLO\", \"CLS\", \"CLZ\", \"EXTSB\", \"EXTSH\", \"EXTUB\", \n                      \"EXTUH\", \"SATS\", \"TIME_CFG\", \"DIV_STEP\", \"MUL_STEP\", \n                      \"LSL_ADD\", \"LSL_SUB\", \"LSR_ADD\", \"ROL_ADD\", \"ROR_ADD\", \n                      \"TIME\", \"NOP\", \"STOP\", \"FAULT\", \"MOVD\", \"SWAPD\", \"LBS\", \n                      \"LBU\", \"LD\", \"LHS\", \"LHU\", \"LW\", \"SB\", \"SB_ID\", \"SD\", \n                      \"SD_ID\", \"SH\", \"SH_ID\", \"SW\", \"SW_ID\", \"LDMA\", \"LDMAI\", \n                      \"SDMA\", \"MOVE\", \"NEG\", \"NOT\", \"BKP\", \"JEQ\", \"JNEQ\", \n                      \"JZ\", \"JNZ\", \"JLTU\", \"JGTU\", \"JLEU\", \"JGEU\", \"JLTS\", \n                      \"JGTS\", \"JLES\", \"JGES\", \"JUMP\", \"ATOMIC\", \"BSS\", \"DATA\", \n                      \"DEBUG_ABBREV\", \"DEBUG_FRAME\", \"DEBUG_INFO\", \"DEBUG_LINE\", \n                      \"DEBUG_LOC\", \"DEBUG_RANGES\", \"DEBUG_STR\", \"DPU_HOST\", \n                      \"MRAM\", \"RODATA\", \"STACK_SIZES\", \"TEXT_SECTION\", \"PROGBITS\", \n                      \"NOBITS\", \"FUNCTION\", \"OBJECT\", \"TRUE\", \"FALSE\", \"Z\", \n                      \"NZ\", \"E\", \"O\", \"PL\", \"MI\", \"OV\", \"NOV\", \"C\", \"NC\", \n                      \"SZ\", \"SNZ\", \"SPL\", \"SMI\", \"SO\", \"SE\", \"NC5\", \"NC6\", \n                      \"NC7\", \"NC8\", \"NC9\", \"NC10\", \"NC11\", \"NC12\", \"NC13\", \n                      \"NC14\", \"MAX\", \"NMAX\", \"SH32\", \"NSH32\", \"EQ\", \"NEQ\", \n                      \"LTU\", \"LEU\", \"GTU\", \"GEU\", \"LTS\", \"LES\", \"GTS\", \"GES\", \n                      \"XZ\", \"XNZ\", \"XLEU\", \"XGTU\", \"XLES\", \"XGTS\", \"SMALL\", \n                      \"LARGE\", \"LITTLE\", \"BIG\", \"ZERO_REGISTER\", \"ONE\", \n                      \"ID\", \"ID2\", \"ID4\", \"ID8\", \"LNEG\", \"MNEG\", \"ADDRSIG\", \n                      \"ADDRSIG_SYM\", \"ASCII\", \"ASCIZ\", \"BYTE\", \"CFI_DEF_CFA_OFFSET\", \n                      \"CFI_ENDPROC\", \"CFI_OFFSET\", \"CFI_SECTIONS\", \"CFI_STARTPROC\", \n                      \"FILE\", \"GLOBL\", \"LOC\", \"LONG\", \"P2ALIGN\", \"QUAD\", \n                      \"SECTION\", \"SET\", \"SHORT\", \"SIZE\", \"TEXT_DIRECTIVE\", \n                      \"TYPE\", \"WEAK\", \"ZERO_DIRECTIVE\", \"IS_STMT\", \"PROLOGUE_END\", \n                      \"S_SUFFIX\", \"U_SUFFIX\", \"PositiveNumber\", \"GPRegister\", \n                      \"PairRegister\", \"Identifier\", \"StringLiteral\", \"COMMENT\", \n                      \"WHITE_SPACE\" ]\n\n    RULE_document = 0\n    RULE_negative_number = 1\n    RULE_hex_number = 2\n    RULE_number = 3\n    RULE_rici_op_code = 4\n    RULE_rri_op_code = 5\n    RULE_rr_op_code = 6\n    RULE_drdici_op_code = 7\n    RULE_rrri_op_code = 8\n    RULE_r_op_code = 9\n    RULE_ci_op_code = 10\n    RULE_i_op_code = 11\n    RULE_ddci_op_code = 12\n    RULE_load_op_code = 13\n    RULE_store_op_code = 14\n    RULE_dma_op_code = 15\n    RULE_section_name = 16\n    RULE_section_types = 17\n    RULE_symbol_type = 18\n    RULE_condition = 19\n    RULE_endian = 20\n    RULE_sp_register = 21\n    RULE_src_register = 22\n    RULE_program_counter = 23\n    RULE_add_expression = 24\n    RULE_sub_expression = 25\n    RULE_primary_expression = 26\n    RULE_directive = 27\n    RULE_addrsig_directive = 28\n    RULE_addrsig_sym_directive = 29\n    RULE_ascii_directive = 30\n    RULE_asciz_directive = 31\n    RULE_byte_directive = 32\n    RULE_cfi_def_cfa_offset_directive = 33\n    RULE_cfi_endproc_directive = 34\n    RULE_cfi_offset_directive = 35\n    RULE_cfi_sections_directive = 36\n    RULE_cfi_startproc_directive = 37\n    RULE_file_directive = 38\n    RULE_global_directive = 39\n    RULE_loc_directive = 40\n    RULE_long_directive = 41\n    RULE_p2align_directive = 42\n    RULE_quad_directive = 43\n    RULE_section_directive = 44\n    RULE_set_directive = 45\n    RULE_short_directive = 46\n    RULE_size_directive = 47\n    RULE_stack_sizes_directive = 48\n    RULE_text_directive = 49\n    RULE_type_directive = 50\n    RULE_weak_directive = 51\n    RULE_zero_directive = 52\n    RULE_instruction = 53\n    RULE_rici_instruction = 54\n    RULE_rri_instruction = 55\n    RULE_rric_instruction = 56\n    RULE_rrici_instruction = 57\n    RULE_rrr_instruction = 58\n    RULE_rrrc_instruction = 59\n    RULE_rrrci_instruction = 60\n    RULE_zri_instruction = 61\n    RULE_zric_instruction = 62\n    RULE_zrici_instruction = 63\n    RULE_zrr_instruction = 64\n    RULE_zrrc_instruction = 65\n    RULE_zrrci_instruction = 66\n    RULE_s_rri_instruction = 67\n    RULE_s_rric_instruction = 68\n    RULE_s_rrici_instruction = 69\n    RULE_s_rrr_instruction = 70\n    RULE_s_rrrc_instruction = 71\n    RULE_s_rrrci_instruction = 72\n    RULE_u_rri_instruction = 73\n    RULE_u_rric_instruction = 74\n    RULE_u_rrici_instruction = 75\n    RULE_u_rrr_instruction = 76\n    RULE_u_rrrc_instruction = 77\n    RULE_u_rrrci_instruction = 78\n    RULE_rr_instruction = 79\n    RULE_rrc_instruction = 80\n    RULE_rrci_instruction = 81\n    RULE_zr_instruction = 82\n    RULE_zrc_instruction = 83\n    RULE_zrci_instruction = 84\n    RULE_s_rr_instruction = 85\n    RULE_s_rrc_instruction = 86\n    RULE_s_rrci_instruction = 87\n    RULE_u_rr_instruction = 88\n    RULE_u_rrc_instruction = 89\n    RULE_u_rrci_instruction = 90\n    RULE_drdici_instruction = 91\n    RULE_rrri_instruction = 92\n    RULE_rrrici_instruction = 93\n    RULE_zrri_instruction = 94\n    RULE_zrrici_instruction = 95\n    RULE_s_rrri_instruction = 96\n    RULE_s_rrrici_instruction = 97\n    RULE_u_rrri_instruction = 98\n    RULE_u_rrrici_instruction = 99\n    RULE_rir_instruction = 100\n    RULE_rirc_instruction = 101\n    RULE_rirci_instruction = 102\n    RULE_zir_instruction = 103\n    RULE_zirc_instruction = 104\n    RULE_zirci_instruction = 105\n    RULE_s_rirc_instruction = 106\n    RULE_s_rirci_instruction = 107\n    RULE_u_rirc_instruction = 108\n    RULE_u_rirci_instruction = 109\n    RULE_r_instruction = 110\n    RULE_rci_instruction = 111\n    RULE_z_instruction = 112\n    RULE_zci_instruction = 113\n    RULE_s_r_instruction = 114\n    RULE_s_rci_instruction = 115\n    RULE_u_r_instruction = 116\n    RULE_u_rci_instruction = 117\n    RULE_ci_instruction = 118\n    RULE_i_instruction = 119\n    RULE_ddci_instruction = 120\n    RULE_erri_instruction = 121\n    RULE_edri_instruction = 122\n    RULE_s_erri_instruction = 123\n    RULE_u_erri_instruction = 124\n    RULE_erii_instruction = 125\n    RULE_erir_instruction = 126\n    RULE_erid_instruction = 127\n    RULE_dma_rri_instruction = 128\n    RULE_synthetic_sugar_instruction = 129\n    RULE_rrif_instruction = 130\n    RULE_andn_rrif_instruction = 131\n    RULE_nand_rrif_instruction = 132\n    RULE_nor_rrif_instruction = 133\n    RULE_nxor_rrif_instruction = 134\n    RULE_orn_rrif_instruction = 135\n    RULE_hash_rrif_instruction = 136\n    RULE_move_instruction = 137\n    RULE_move_ri_instruction = 138\n    RULE_move_rici_instruction = 139\n    RULE_move_rr_instruction = 140\n    RULE_move_rrci_instruction = 141\n    RULE_move_s_ri_instruction = 142\n    RULE_move_s_rici_instruction = 143\n    RULE_move_s_rr_instruction = 144\n    RULE_move_s_rrci_instruction = 145\n    RULE_move_u_ri_instruction = 146\n    RULE_move_u_rici_instruction = 147\n    RULE_move_u_rr_instruction = 148\n    RULE_move_u_rrci_instruction = 149\n    RULE_neg_instruction = 150\n    RULE_neg_rr_instruction = 151\n    RULE_neg_rrci_instruction = 152\n    RULE_not_instruction = 153\n    RULE_not_rr_instruction = 154\n    RULE_not_rrci_instruction = 155\n    RULE_not_zrci_instruction = 156\n    RULE_jump_instruction = 157\n    RULE_jeq_rii_instruction = 158\n    RULE_jeq_rri_instruction = 159\n    RULE_jneq_rii_instruction = 160\n    RULE_jneq_rri_instruction = 161\n    RULE_jz_ri_instruction = 162\n    RULE_jnz_ri_instruction = 163\n    RULE_jltu_rii_instruction = 164\n    RULE_jltu_rri_instruction = 165\n    RULE_jgtu_rii_instruction = 166\n    RULE_jgtu_rri_instruction = 167\n    RULE_jleu_rii_instruction = 168\n    RULE_jleu_rri_instruction = 169\n    RULE_jgeu_rii_instruction = 170\n    RULE_jgeu_rri_instruction = 171\n    RULE_jlts_rii_instruction = 172\n    RULE_jlts_rri_instruction = 173\n    RULE_jgts_rii_instruction = 174\n    RULE_jgts_rri_instruction = 175\n    RULE_jles_rii_instruction = 176\n    RULE_jles_rri_instruction = 177\n    RULE_jges_rii_instruction = 178\n    RULE_jges_rri_instruction = 179\n    RULE_jump_ri_instruction = 180\n    RULE_jump_i_instruction = 181\n    RULE_jump_r_instruction = 182\n    RULE_shortcut_instruction = 183\n    RULE_div_step_drdici_instruction = 184\n    RULE_mul_step_drdici_instruction = 185\n    RULE_boot_rici_instruction = 186\n    RULE_resume_rici_instruction = 187\n    RULE_stop_ci_instruction = 188\n    RULE_call_ri_instruction = 189\n    RULE_call_rr_instruction = 190\n    RULE_bkp_instruction = 191\n    RULE_movd_ddci_instruction = 192\n    RULE_swapd_ddci_instruction = 193\n    RULE_time_cfg_zr_instruction = 194\n    RULE_lbs_erri_instruction = 195\n    RULE_lbs_s_erri_instruction = 196\n    RULE_lbu_erri_instruction = 197\n    RULE_lbu_u_erri_instruction = 198\n    RULE_ld_edri_instruction = 199\n    RULE_lhs_erri_instruction = 200\n    RULE_lhs_s_erri_instruction = 201\n    RULE_lhu_erri_instruction = 202\n    RULE_lhu_u_erri_instruction = 203\n    RULE_lw_erri_instruction = 204\n    RULE_lw_s_erri_instruction = 205\n    RULE_lw_u_erri_instruction = 206\n    RULE_sb_erii_instruction = 207\n    RULE_sb_erir_instruction = 208\n    RULE_sb_id_rii_instruction = 209\n    RULE_sb_id_ri_instruction = 210\n    RULE_sd_erii_instruction = 211\n    RULE_sd_erid_instruction = 212\n    RULE_sd_id_rii_instruction = 213\n    RULE_sd_id_ri_instruction = 214\n    RULE_sh_erii_instruction = 215\n    RULE_sh_erir_instruction = 216\n    RULE_sh_id_rii_instruction = 217\n    RULE_sh_id_ri_instruction = 218\n    RULE_sw_erii_instruction = 219\n    RULE_sw_erir_instruction = 220\n    RULE_sw_id_rii_instruction = 221\n    RULE_sw_id_ri_instruction = 222\n    RULE_label = 223\n\n    ruleNames =  [ \"document\", \"negative_number\", \"hex_number\", \"number\", \n                   \"rici_op_code\", \"rri_op_code\", \"rr_op_code\", \"drdici_op_code\", \n                   \"rrri_op_code\", \"r_op_code\", \"ci_op_code\", \"i_op_code\", \n                   \"ddci_op_code\", \"load_op_code\", \"store_op_code\", \"dma_op_code\", \n                   \"section_name\", \"section_types\", \"symbol_type\", \"condition\", \n                   \"endian\", \"sp_register\", \"src_register\", \"program_counter\", \n                   \"add_expression\", \"sub_expression\", \"primary_expression\", \n                   \"directive\", \"addrsig_directive\", \"addrsig_sym_directive\", \n                   \"ascii_directive\", \"asciz_directive\", \"byte_directive\", \n                   \"cfi_def_cfa_offset_directive\", \"cfi_endproc_directive\", \n                   \"cfi_offset_directive\", \"cfi_sections_directive\", \"cfi_startproc_directive\", \n                   \"file_directive\", \"global_directive\", \"loc_directive\", \n                   \"long_directive\", \"p2align_directive\", \"quad_directive\", \n                   \"section_directive\", \"set_directive\", \"short_directive\", \n                   \"size_directive\", \"stack_sizes_directive\", \"text_directive\", \n                   \"type_directive\", \"weak_directive\", \"zero_directive\", \n                   \"instruction\", \"rici_instruction\", \"rri_instruction\", \n                   \"rric_instruction\", \"rrici_instruction\", \"rrr_instruction\", \n                   \"rrrc_instruction\", \"rrrci_instruction\", \"zri_instruction\", \n                   \"zric_instruction\", \"zrici_instruction\", \"zrr_instruction\", \n                   \"zrrc_instruction\", \"zrrci_instruction\", \"s_rri_instruction\", \n                   \"s_rric_instruction\", \"s_rrici_instruction\", \"s_rrr_instruction\", \n                   \"s_rrrc_instruction\", \"s_rrrci_instruction\", \"u_rri_instruction\", \n                   \"u_rric_instruction\", \"u_rrici_instruction\", \"u_rrr_instruction\", \n                   \"u_rrrc_instruction\", \"u_rrrci_instruction\", \"rr_instruction\", \n                   \"rrc_instruction\", \"rrci_instruction\", \"zr_instruction\", \n                   \"zrc_instruction\", \"zrci_instruction\", \"s_rr_instruction\", \n                   \"s_rrc_instruction\", \"s_rrci_instruction\", \"u_rr_instruction\", \n                   \"u_rrc_instruction\", \"u_rrci_instruction\", \"drdici_instruction\", \n                   \"rrri_instruction\", \"rrrici_instruction\", \"zrri_instruction\", \n                   \"zrrici_instruction\", \"s_rrri_instruction\", \"s_rrrici_instruction\", \n                   \"u_rrri_instruction\", \"u_rrrici_instruction\", \"rir_instruction\", \n                   \"rirc_instruction\", \"rirci_instruction\", \"zir_instruction\", \n                   \"zirc_instruction\", \"zirci_instruction\", \"s_rirc_instruction\", \n                   \"s_rirci_instruction\", \"u_rirc_instruction\", \"u_rirci_instruction\", \n                   \"r_instruction\", \"rci_instruction\", \"z_instruction\", \n                   \"zci_instruction\", \"s_r_instruction\", \"s_rci_instruction\", \n                   \"u_r_instruction\", \"u_rci_instruction\", \"ci_instruction\", \n                   \"i_instruction\", \"ddci_instruction\", \"erri_instruction\", \n                   \"edri_instruction\", \"s_erri_instruction\", \"u_erri_instruction\", \n                   \"erii_instruction\", \"erir_instruction\", \"erid_instruction\", \n                   \"dma_rri_instruction\", \"synthetic_sugar_instruction\", \n                   \"rrif_instruction\", \"andn_rrif_instruction\", \"nand_rrif_instruction\", \n                   \"nor_rrif_instruction\", \"nxor_rrif_instruction\", \"orn_rrif_instruction\", \n                   \"hash_rrif_instruction\", \"move_instruction\", \"move_ri_instruction\", \n                   \"move_rici_instruction\", \"move_rr_instruction\", \"move_rrci_instruction\", \n                   \"move_s_ri_instruction\", \"move_s_rici_instruction\", \"move_s_rr_instruction\", \n                   \"move_s_rrci_instruction\", \"move_u_ri_instruction\", \"move_u_rici_instruction\", \n                   \"move_u_rr_instruction\", \"move_u_rrci_instruction\", \"neg_instruction\", \n                   \"neg_rr_instruction\", \"neg_rrci_instruction\", \"not_instruction\", \n                   \"not_rr_instruction\", \"not_rrci_instruction\", \"not_zrci_instruction\", \n                   \"jump_instruction\", \"jeq_rii_instruction\", \"jeq_rri_instruction\", \n                   \"jneq_rii_instruction\", \"jneq_rri_instruction\", \"jz_ri_instruction\", \n                   \"jnz_ri_instruction\", \"jltu_rii_instruction\", \"jltu_rri_instruction\", \n                   \"jgtu_rii_instruction\", \"jgtu_rri_instruction\", \"jleu_rii_instruction\", \n                   \"jleu_rri_instruction\", \"jgeu_rii_instruction\", \"jgeu_rri_instruction\", \n                   \"jlts_rii_instruction\", \"jlts_rri_instruction\", \"jgts_rii_instruction\", \n                   \"jgts_rri_instruction\", \"jles_rii_instruction\", \"jles_rri_instruction\", \n                   \"jges_rii_instruction\", \"jges_rri_instruction\", \"jump_ri_instruction\", \n                   \"jump_i_instruction\", \"jump_r_instruction\", \"shortcut_instruction\", \n                   \"div_step_drdici_instruction\", \"mul_step_drdici_instruction\", \n                   \"boot_rici_instruction\", \"resume_rici_instruction\", \"stop_ci_instruction\", \n                   \"call_ri_instruction\", \"call_rr_instruction\", \"bkp_instruction\", \n                   \"movd_ddci_instruction\", \"swapd_ddci_instruction\", \"time_cfg_zr_instruction\", \n                   \"lbs_erri_instruction\", \"lbs_s_erri_instruction\", \"lbu_erri_instruction\", \n                   \"lbu_u_erri_instruction\", \"ld_edri_instruction\", \"lhs_erri_instruction\", \n                   \"lhs_s_erri_instruction\", \"lhu_erri_instruction\", \"lhu_u_erri_instruction\", \n                   \"lw_erri_instruction\", \"lw_s_erri_instruction\", \"lw_u_erri_instruction\", \n                   \"sb_erii_instruction\", \"sb_erir_instruction\", \"sb_id_rii_instruction\", \n                   \"sb_id_ri_instruction\", \"sd_erii_instruction\", \"sd_erid_instruction\", \n                   \"sd_id_rii_instruction\", \"sd_id_ri_instruction\", \"sh_erii_instruction\", \n                   \"sh_erir_instruction\", \"sh_id_rii_instruction\", \"sh_id_ri_instruction\", \n                   \"sw_erii_instruction\", \"sw_erir_instruction\", \"sw_id_rii_instruction\", \n                   \"sw_id_ri_instruction\", \"label\" ]\n\n    EOF = Token.EOF\n    T__0=1\n    T__1=2\n    T__2=3\n    T__3=4\n    T__4=5\n    ACQUIRE=6\n    RELEASE=7\n    BOOT=8\n    RESUME=9\n    ADD=10\n    ADDC=11\n    AND=12\n    ANDN=13\n    ASR=14\n    CMPB4=15\n    LSL=16\n    LSL1=17\n    LSL1X=18\n    LSLX=19\n    LSR=20\n    LSR1=21\n    LSR1X=22\n    LSRX=23\n    MUL_SH_SH=24\n    MUL_SH_SL=25\n    MUL_SH_UH=26\n    MUL_SH_UL=27\n    MUL_SL_SH=28\n    MUL_SL_SL=29\n    MUL_SL_UH=30\n    MUL_SL_UL=31\n    MUL_UH_UH=32\n    MUL_UH_UL=33\n    MUL_UL_UH=34\n    MUL_UL_UL=35\n    NAND=36\n    NOR=37\n    NXOR=38\n    OR=39\n    ORN=40\n    ROL=41\n    ROR=42\n    RSUB=43\n    RSUBC=44\n    SUB=45\n    SUBC=46\n    XOR=47\n    CALL=48\n    HASH=49\n    CAO=50\n    CLO=51\n    CLS=52\n    CLZ=53\n    EXTSB=54\n    EXTSH=55\n    EXTUB=56\n    EXTUH=57\n    SATS=58\n    TIME_CFG=59\n    DIV_STEP=60\n    MUL_STEP=61\n    LSL_ADD=62\n    LSL_SUB=63\n    LSR_ADD=64\n    ROL_ADD=65\n    ROR_ADD=66\n    TIME=67\n    NOP=68\n    STOP=69\n    FAULT=70\n    MOVD=71\n    SWAPD=72\n    LBS=73\n    LBU=74\n    LD=75\n    LHS=76\n    LHU=77\n    LW=78\n    SB=79\n    SB_ID=80\n    SD=81\n    SD_ID=82\n    SH=83\n    SH_ID=84\n    SW=85\n    SW_ID=86\n    LDMA=87\n    LDMAI=88\n    SDMA=89\n    MOVE=90\n    NEG=91\n    NOT=92\n    BKP=93\n    JEQ=94\n    JNEQ=95\n    JZ=96\n    JNZ=97\n    JLTU=98\n    JGTU=99\n    JLEU=100\n    JGEU=101\n    JLTS=102\n    JGTS=103\n    JLES=104\n    JGES=105\n    JUMP=106\n    ATOMIC=107\n    BSS=108\n    DATA=109\n    DEBUG_ABBREV=110\n    DEBUG_FRAME=111\n    DEBUG_INFO=112\n    DEBUG_LINE=113\n    DEBUG_LOC=114\n    DEBUG_RANGES=115\n    DEBUG_STR=116\n    DPU_HOST=117\n    MRAM=118\n    RODATA=119\n    STACK_SIZES=120\n    TEXT_SECTION=121\n    PROGBITS=122\n    NOBITS=123\n    FUNCTION=124\n    OBJECT=125\n    TRUE=126\n    FALSE=127\n    Z=128\n    NZ=129\n    E=130\n    O=131\n    PL=132\n    MI=133\n    OV=134\n    NOV=135\n    C=136\n    NC=137\n    SZ=138\n    SNZ=139\n    SPL=140\n    SMI=141\n    SO=142\n    SE=143\n    NC5=144\n    NC6=145\n    NC7=146\n    NC8=147\n    NC9=148\n    NC10=149\n    NC11=150\n    NC12=151\n    NC13=152\n    NC14=153\n    MAX=154\n    NMAX=155\n    SH32=156\n    NSH32=157\n    EQ=158\n    NEQ=159\n    LTU=160\n    LEU=161\n    GTU=162\n    GEU=163\n    LTS=164\n    LES=165\n    GTS=166\n    GES=167\n    XZ=168\n    XNZ=169\n    XLEU=170\n    XGTU=171\n    XLES=172\n    XGTS=173\n    SMALL=174\n    LARGE=175\n    LITTLE=176\n    BIG=177\n    ZERO_REGISTER=178\n    ONE=179\n    ID=180\n    ID2=181\n    ID4=182\n    ID8=183\n    LNEG=184\n    MNEG=185\n    ADDRSIG=186\n    ADDRSIG_SYM=187\n    ASCII=188\n    ASCIZ=189\n    BYTE=190\n    CFI_DEF_CFA_OFFSET=191\n    CFI_ENDPROC=192\n    CFI_OFFSET=193\n    CFI_SECTIONS=194\n    CFI_STARTPROC=195\n    FILE=196\n    GLOBL=197\n    LOC=198\n    LONG=199\n    P2ALIGN=200\n    QUAD=201\n    SECTION=202\n    SET=203\n    SHORT=204\n    SIZE=205\n    TEXT_DIRECTIVE=206\n    TYPE=207\n    WEAK=208\n    ZERO_DIRECTIVE=209\n    IS_STMT=210\n    PROLOGUE_END=211\n    S_SUFFIX=212\n    U_SUFFIX=213\n    PositiveNumber=214\n    GPRegister=215\n    PairRegister=216\n    Identifier=217\n    StringLiteral=218\n    COMMENT=219\n    WHITE_SPACE=220\n\n    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):\n        super().__init__(input, output)\n        self.checkVersion(\"4.9.2\")\n        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)\n        self._predicates = None\n\n\n\n\n    class DocumentContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def EOF(self):\n            return self.getToken(assemblyParser.EOF, 0)\n\n        def directive(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.DirectiveContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.DirectiveContext,i)\n\n\n        def instruction(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.InstructionContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.InstructionContext,i)\n\n\n        def label(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.LabelContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.LabelContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_document\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDocument\" ):\n                listener.enterDocument(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDocument\" ):\n                listener.exitDocument(self)\n\n\n\n\n    def document(self):\n\n        localctx = assemblyParser.DocumentContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 0, self.RULE_document)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 453\n            self._errHandler.sync(self)\n            _la = self._input.LA(1)\n            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << assemblyParser.ACQUIRE) | (1 << assemblyParser.RELEASE) | (1 << assemblyParser.BOOT) | (1 << assemblyParser.RESUME) | (1 << assemblyParser.ADD) | (1 << assemblyParser.ADDC) | (1 << assemblyParser.AND) | (1 << assemblyParser.ANDN) | (1 << assemblyParser.ASR) | (1 << assemblyParser.CMPB4) | (1 << assemblyParser.LSL) | (1 << assemblyParser.LSL1) | (1 << assemblyParser.LSL1X) | (1 << assemblyParser.LSLX) | (1 << assemblyParser.LSR) | (1 << assemblyParser.LSR1) | (1 << assemblyParser.LSR1X) | (1 << assemblyParser.LSRX) | (1 << assemblyParser.MUL_SH_SH) | (1 << assemblyParser.MUL_SH_SL) | (1 << assemblyParser.MUL_SH_UH) | (1 << assemblyParser.MUL_SH_UL) | (1 << assemblyParser.MUL_SL_SH) | (1 << assemblyParser.MUL_SL_SL) | (1 << assemblyParser.MUL_SL_UH) | (1 << assemblyParser.MUL_SL_UL) | (1 << assemblyParser.MUL_UH_UH) | (1 << assemblyParser.MUL_UH_UL) | (1 << assemblyParser.MUL_UL_UH) | (1 << assemblyParser.MUL_UL_UL) | (1 << assemblyParser.NAND) | (1 << assemblyParser.NOR) | (1 << assemblyParser.NXOR) | (1 << assemblyParser.OR) | (1 << assemblyParser.ORN) | (1 << assemblyParser.ROL) | (1 << assemblyParser.ROR) | (1 << assemblyParser.RSUB) | (1 << assemblyParser.RSUBC) | (1 << assemblyParser.SUB) | (1 << assemblyParser.SUBC) | (1 << assemblyParser.XOR) | (1 << assemblyParser.CALL) | (1 << assemblyParser.HASH) | (1 << assemblyParser.CAO) | (1 << assemblyParser.CLO) | (1 << assemblyParser.CLS) | (1 << assemblyParser.CLZ) | (1 << assemblyParser.EXTSB) | (1 << assemblyParser.EXTSH) | (1 << assemblyParser.EXTUB) | (1 << assemblyParser.EXTUH) | (1 << assemblyParser.SATS) | (1 << assemblyParser.TIME_CFG) | (1 << assemblyParser.DIV_STEP) | (1 << assemblyParser.MUL_STEP) | (1 << assemblyParser.LSL_ADD) | (1 << assemblyParser.LSL_SUB))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (assemblyParser.LSR_ADD - 64)) | (1 << (assemblyParser.ROL_ADD - 64)) | (1 << (assemblyParser.ROR_ADD - 64)) | (1 << (assemblyParser.TIME - 64)) | (1 << (assemblyParser.NOP - 64)) | (1 << (assemblyParser.STOP - 64)) | (1 << (assemblyParser.FAULT - 64)) | (1 << (assemblyParser.MOVD - 64)) | (1 << (assemblyParser.SWAPD - 64)) | (1 << (assemblyParser.LBS - 64)) | (1 << (assemblyParser.LBU - 64)) | (1 << (assemblyParser.LD - 64)) | (1 << (assemblyParser.LHS - 64)) | (1 << (assemblyParser.LHU - 64)) | (1 << (assemblyParser.LW - 64)) | (1 << (assemblyParser.SB - 64)) | (1 << (assemblyParser.SB_ID - 64)) | (1 << (assemblyParser.SD - 64)) | (1 << (assemblyParser.SD_ID - 64)) | (1 << (assemblyParser.SH - 64)) | (1 << (assemblyParser.SH_ID - 64)) | (1 << (assemblyParser.SW - 64)) | (1 << (assemblyParser.SW_ID - 64)) | (1 << (assemblyParser.LDMA - 64)) | (1 << (assemblyParser.LDMAI - 64)) | (1 << (assemblyParser.SDMA - 64)) | (1 << (assemblyParser.MOVE - 64)) | (1 << (assemblyParser.NEG - 64)) | (1 << (assemblyParser.NOT - 64)) | (1 << (assemblyParser.BKP - 64)) | (1 << (assemblyParser.JEQ - 64)) | (1 << (assemblyParser.JNEQ - 64)) | (1 << (assemblyParser.JZ - 64)) | (1 << (assemblyParser.JNZ - 64)) | (1 << (assemblyParser.JLTU - 64)) | (1 << (assemblyParser.JGTU - 64)) | (1 << (assemblyParser.JLEU - 64)) | (1 << (assemblyParser.JGEU - 64)) | (1 << (assemblyParser.JLTS - 64)) | (1 << (assemblyParser.JGTS - 64)) | (1 << (assemblyParser.JLES - 64)) | (1 << (assemblyParser.JGES - 64)) | (1 << (assemblyParser.JUMP - 64)))) != 0) or ((((_la - 186)) & ~0x3f) == 0 and ((1 << (_la - 186)) & ((1 << (assemblyParser.ADDRSIG - 186)) | (1 << (assemblyParser.ADDRSIG_SYM - 186)) | (1 << (assemblyParser.ASCII - 186)) | (1 << (assemblyParser.ASCIZ - 186)) | (1 << (assemblyParser.BYTE - 186)) | (1 << (assemblyParser.CFI_DEF_CFA_OFFSET - 186)) | (1 << (assemblyParser.CFI_ENDPROC - 186)) | (1 << (assemblyParser.CFI_OFFSET - 186)) | (1 << (assemblyParser.CFI_SECTIONS - 186)) | (1 << (assemblyParser.CFI_STARTPROC - 186)) | (1 << (assemblyParser.FILE - 186)) | (1 << (assemblyParser.GLOBL - 186)) | (1 << (assemblyParser.LOC - 186)) | (1 << (assemblyParser.LONG - 186)) | (1 << (assemblyParser.P2ALIGN - 186)) | (1 << (assemblyParser.QUAD - 186)) | (1 << (assemblyParser.SECTION - 186)) | (1 << (assemblyParser.SET - 186)) | (1 << (assemblyParser.SHORT - 186)) | (1 << (assemblyParser.SIZE - 186)) | (1 << (assemblyParser.TEXT_DIRECTIVE - 186)) | (1 << (assemblyParser.TYPE - 186)) | (1 << (assemblyParser.WEAK - 186)) | (1 << (assemblyParser.ZERO_DIRECTIVE - 186)) | (1 << (assemblyParser.Identifier - 186)))) != 0):\n                self.state = 451\n                self._errHandler.sync(self)\n                token = self._input.LA(1)\n                if token in [assemblyParser.ADDRSIG, assemblyParser.ADDRSIG_SYM, assemblyParser.ASCII, assemblyParser.ASCIZ, assemblyParser.BYTE, assemblyParser.CFI_DEF_CFA_OFFSET, assemblyParser.CFI_ENDPROC, assemblyParser.CFI_OFFSET, assemblyParser.CFI_SECTIONS, assemblyParser.CFI_STARTPROC, assemblyParser.FILE, assemblyParser.GLOBL, assemblyParser.LOC, assemblyParser.LONG, assemblyParser.P2ALIGN, assemblyParser.QUAD, assemblyParser.SECTION, assemblyParser.SET, assemblyParser.SHORT, assemblyParser.SIZE, assemblyParser.TEXT_DIRECTIVE, assemblyParser.TYPE, assemblyParser.WEAK, assemblyParser.ZERO_DIRECTIVE]:\n                    self.state = 448\n                    self.directive()\n                    pass\n                elif token in [assemblyParser.ACQUIRE, assemblyParser.RELEASE, assemblyParser.BOOT, assemblyParser.RESUME, assemblyParser.ADD, assemblyParser.ADDC, assemblyParser.AND, assemblyParser.ANDN, assemblyParser.ASR, assemblyParser.CMPB4, assemblyParser.LSL, assemblyParser.LSL1, assemblyParser.LSL1X, assemblyParser.LSLX, assemblyParser.LSR, assemblyParser.LSR1, assemblyParser.LSR1X, assemblyParser.LSRX, assemblyParser.MUL_SH_SH, assemblyParser.MUL_SH_SL, assemblyParser.MUL_SH_UH, assemblyParser.MUL_SH_UL, assemblyParser.MUL_SL_SH, assemblyParser.MUL_SL_SL, assemblyParser.MUL_SL_UH, assemblyParser.MUL_SL_UL, assemblyParser.MUL_UH_UH, assemblyParser.MUL_UH_UL, assemblyParser.MUL_UL_UH, assemblyParser.MUL_UL_UL, assemblyParser.NAND, assemblyParser.NOR, assemblyParser.NXOR, assemblyParser.OR, assemblyParser.ORN, assemblyParser.ROL, assemblyParser.ROR, assemblyParser.RSUB, assemblyParser.RSUBC, assemblyParser.SUB, assemblyParser.SUBC, assemblyParser.XOR, assemblyParser.CALL, assemblyParser.HASH, assemblyParser.CAO, assemblyParser.CLO, assemblyParser.CLS, assemblyParser.CLZ, assemblyParser.EXTSB, assemblyParser.EXTSH, assemblyParser.EXTUB, assemblyParser.EXTUH, assemblyParser.SATS, assemblyParser.TIME_CFG, assemblyParser.DIV_STEP, assemblyParser.MUL_STEP, assemblyParser.LSL_ADD, assemblyParser.LSL_SUB, assemblyParser.LSR_ADD, assemblyParser.ROL_ADD, assemblyParser.ROR_ADD, assemblyParser.TIME, assemblyParser.NOP, assemblyParser.STOP, assemblyParser.FAULT, assemblyParser.MOVD, assemblyParser.SWAPD, assemblyParser.LBS, assemblyParser.LBU, assemblyParser.LD, assemblyParser.LHS, assemblyParser.LHU, assemblyParser.LW, assemblyParser.SB, assemblyParser.SB_ID, assemblyParser.SD, assemblyParser.SD_ID, assemblyParser.SH, assemblyParser.SH_ID, assemblyParser.SW, assemblyParser.SW_ID, assemblyParser.LDMA, assemblyParser.LDMAI, assemblyParser.SDMA, assemblyParser.MOVE, assemblyParser.NEG, assemblyParser.NOT, assemblyParser.BKP, assemblyParser.JEQ, assemblyParser.JNEQ, assemblyParser.JZ, assemblyParser.JNZ, assemblyParser.JLTU, assemblyParser.JGTU, assemblyParser.JLEU, assemblyParser.JGEU, assemblyParser.JLTS, assemblyParser.JGTS, assemblyParser.JLES, assemblyParser.JGES, assemblyParser.JUMP]:\n                    self.state = 449\n                    self.instruction()\n                    pass\n                elif token in [assemblyParser.Identifier]:\n                    self.state = 450\n                    self.label()\n                    pass\n                else:\n                    raise NoViableAltException(self)\n\n                self.state = 455\n                self._errHandler.sync(self)\n                _la = self._input.LA(1)\n\n            self.state = 456\n            self.match(assemblyParser.EOF)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Negative_numberContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def PositiveNumber(self):\n            return self.getToken(assemblyParser.PositiveNumber, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_negative_number\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNegative_number\" ):\n                listener.enterNegative_number(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNegative_number\" ):\n                listener.exitNegative_number(self)\n\n\n\n\n    def negative_number(self):\n\n        localctx = assemblyParser.Negative_numberContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 2, self.RULE_negative_number)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 458\n            self.match(assemblyParser.T__0)\n            self.state = 459\n            self.match(assemblyParser.PositiveNumber)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Hex_numberContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def PositiveNumber(self):\n            return self.getToken(assemblyParser.PositiveNumber, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_hex_number\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterHex_number\" ):\n                listener.enterHex_number(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitHex_number\" ):\n                listener.exitHex_number(self)\n\n\n\n\n    def hex_number(self):\n\n        localctx = assemblyParser.Hex_numberContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 4, self.RULE_hex_number)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 461\n            self.match(assemblyParser.T__1)\n            self.state = 462\n            self.match(assemblyParser.PositiveNumber)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class NumberContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def PositiveNumber(self):\n            return self.getToken(assemblyParser.PositiveNumber, 0)\n\n        def negative_number(self):\n            return self.getTypedRuleContext(assemblyParser.Negative_numberContext,0)\n\n\n        def hex_number(self):\n            return self.getTypedRuleContext(assemblyParser.Hex_numberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_number\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNumber\" ):\n                listener.enterNumber(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNumber\" ):\n                listener.exitNumber(self)\n\n\n\n\n    def number(self):\n\n        localctx = assemblyParser.NumberContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 6, self.RULE_number)\n        try:\n            self.state = 467\n            self._errHandler.sync(self)\n            token = self._input.LA(1)\n            if token in [assemblyParser.PositiveNumber]:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 464\n                self.match(assemblyParser.PositiveNumber)\n                pass\n            elif token in [assemblyParser.T__0]:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 465\n                self.negative_number()\n                pass\n            elif token in [assemblyParser.T__1]:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 466\n                self.hex_number()\n                pass\n            else:\n                raise NoViableAltException(self)\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rici_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ACQUIRE(self):\n            return self.getToken(assemblyParser.ACQUIRE, 0)\n\n        def RELEASE(self):\n            return self.getToken(assemblyParser.RELEASE, 0)\n\n        def BOOT(self):\n            return self.getToken(assemblyParser.BOOT, 0)\n\n        def RESUME(self):\n            return self.getToken(assemblyParser.RESUME, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rici_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRici_op_code\" ):\n                listener.enterRici_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRici_op_code\" ):\n                listener.exitRici_op_code(self)\n\n\n\n\n    def rici_op_code(self):\n\n        localctx = assemblyParser.Rici_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 8, self.RULE_rici_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 469\n            _la = self._input.LA(1)\n            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << assemblyParser.ACQUIRE) | (1 << assemblyParser.RELEASE) | (1 << assemblyParser.BOOT) | (1 << assemblyParser.RESUME))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rri_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ADD(self):\n            return self.getToken(assemblyParser.ADD, 0)\n\n        def ADDC(self):\n            return self.getToken(assemblyParser.ADDC, 0)\n\n        def AND(self):\n            return self.getToken(assemblyParser.AND, 0)\n\n        def ANDN(self):\n            return self.getToken(assemblyParser.ANDN, 0)\n\n        def ASR(self):\n            return self.getToken(assemblyParser.ASR, 0)\n\n        def CMPB4(self):\n            return self.getToken(assemblyParser.CMPB4, 0)\n\n        def LSL(self):\n            return self.getToken(assemblyParser.LSL, 0)\n\n        def LSL1(self):\n            return self.getToken(assemblyParser.LSL1, 0)\n\n        def LSL1X(self):\n            return self.getToken(assemblyParser.LSL1X, 0)\n\n        def LSLX(self):\n            return self.getToken(assemblyParser.LSLX, 0)\n\n        def LSR(self):\n            return self.getToken(assemblyParser.LSR, 0)\n\n        def LSR1(self):\n            return self.getToken(assemblyParser.LSR1, 0)\n\n        def LSR1X(self):\n            return self.getToken(assemblyParser.LSR1X, 0)\n\n        def LSRX(self):\n            return self.getToken(assemblyParser.LSRX, 0)\n\n        def MUL_SH_SH(self):\n            return self.getToken(assemblyParser.MUL_SH_SH, 0)\n\n        def MUL_SH_SL(self):\n            return self.getToken(assemblyParser.MUL_SH_SL, 0)\n\n        def MUL_SH_UH(self):\n            return self.getToken(assemblyParser.MUL_SH_UH, 0)\n\n        def MUL_SH_UL(self):\n            return self.getToken(assemblyParser.MUL_SH_UL, 0)\n\n        def MUL_SL_SH(self):\n            return self.getToken(assemblyParser.MUL_SL_SH, 0)\n\n        def MUL_SL_SL(self):\n            return self.getToken(assemblyParser.MUL_SL_SL, 0)\n\n        def MUL_SL_UH(self):\n            return self.getToken(assemblyParser.MUL_SL_UH, 0)\n\n        def MUL_SL_UL(self):\n            return self.getToken(assemblyParser.MUL_SL_UL, 0)\n\n        def MUL_UH_UH(self):\n            return self.getToken(assemblyParser.MUL_UH_UH, 0)\n\n        def MUL_UH_UL(self):\n            return self.getToken(assemblyParser.MUL_UH_UL, 0)\n\n        def MUL_UL_UH(self):\n            return self.getToken(assemblyParser.MUL_UL_UH, 0)\n\n        def MUL_UL_UL(self):\n            return self.getToken(assemblyParser.MUL_UL_UL, 0)\n\n        def NAND(self):\n            return self.getToken(assemblyParser.NAND, 0)\n\n        def NOR(self):\n            return self.getToken(assemblyParser.NOR, 0)\n\n        def NXOR(self):\n            return self.getToken(assemblyParser.NXOR, 0)\n\n        def OR(self):\n            return self.getToken(assemblyParser.OR, 0)\n\n        def ORN(self):\n            return self.getToken(assemblyParser.ORN, 0)\n\n        def ROL(self):\n            return self.getToken(assemblyParser.ROL, 0)\n\n        def ROR(self):\n            return self.getToken(assemblyParser.ROR, 0)\n\n        def RSUB(self):\n            return self.getToken(assemblyParser.RSUB, 0)\n\n        def RSUBC(self):\n            return self.getToken(assemblyParser.RSUBC, 0)\n\n        def SUB(self):\n            return self.getToken(assemblyParser.SUB, 0)\n\n        def SUBC(self):\n            return self.getToken(assemblyParser.SUBC, 0)\n\n        def XOR(self):\n            return self.getToken(assemblyParser.XOR, 0)\n\n        def CALL(self):\n            return self.getToken(assemblyParser.CALL, 0)\n\n        def HASH(self):\n            return self.getToken(assemblyParser.HASH, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rri_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRri_op_code\" ):\n                listener.enterRri_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRri_op_code\" ):\n                listener.exitRri_op_code(self)\n\n\n\n\n    def rri_op_code(self):\n\n        localctx = assemblyParser.Rri_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 10, self.RULE_rri_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 471\n            _la = self._input.LA(1)\n            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << assemblyParser.ADD) | (1 << assemblyParser.ADDC) | (1 << assemblyParser.AND) | (1 << assemblyParser.ANDN) | (1 << assemblyParser.ASR) | (1 << assemblyParser.CMPB4) | (1 << assemblyParser.LSL) | (1 << assemblyParser.LSL1) | (1 << assemblyParser.LSL1X) | (1 << assemblyParser.LSLX) | (1 << assemblyParser.LSR) | (1 << assemblyParser.LSR1) | (1 << assemblyParser.LSR1X) | (1 << assemblyParser.LSRX) | (1 << assemblyParser.MUL_SH_SH) | (1 << assemblyParser.MUL_SH_SL) | (1 << assemblyParser.MUL_SH_UH) | (1 << assemblyParser.MUL_SH_UL) | (1 << assemblyParser.MUL_SL_SH) | (1 << assemblyParser.MUL_SL_SL) | (1 << assemblyParser.MUL_SL_UH) | (1 << assemblyParser.MUL_SL_UL) | (1 << assemblyParser.MUL_UH_UH) | (1 << assemblyParser.MUL_UH_UL) | (1 << assemblyParser.MUL_UL_UH) | (1 << assemblyParser.MUL_UL_UL) | (1 << assemblyParser.NAND) | (1 << assemblyParser.NOR) | (1 << assemblyParser.NXOR) | (1 << assemblyParser.OR) | (1 << assemblyParser.ORN) | (1 << assemblyParser.ROL) | (1 << assemblyParser.ROR) | (1 << assemblyParser.RSUB) | (1 << assemblyParser.RSUBC) | (1 << assemblyParser.SUB) | (1 << assemblyParser.SUBC) | (1 << assemblyParser.XOR) | (1 << assemblyParser.CALL) | (1 << assemblyParser.HASH))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rr_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CAO(self):\n            return self.getToken(assemblyParser.CAO, 0)\n\n        def CLO(self):\n            return self.getToken(assemblyParser.CLO, 0)\n\n        def CLS(self):\n            return self.getToken(assemblyParser.CLS, 0)\n\n        def CLZ(self):\n            return self.getToken(assemblyParser.CLZ, 0)\n\n        def EXTSB(self):\n            return self.getToken(assemblyParser.EXTSB, 0)\n\n        def EXTSH(self):\n            return self.getToken(assemblyParser.EXTSH, 0)\n\n        def EXTUB(self):\n            return self.getToken(assemblyParser.EXTUB, 0)\n\n        def EXTUH(self):\n            return self.getToken(assemblyParser.EXTUH, 0)\n\n        def SATS(self):\n            return self.getToken(assemblyParser.SATS, 0)\n\n        def TIME_CFG(self):\n            return self.getToken(assemblyParser.TIME_CFG, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rr_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRr_op_code\" ):\n                listener.enterRr_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRr_op_code\" ):\n                listener.exitRr_op_code(self)\n\n\n\n\n    def rr_op_code(self):\n\n        localctx = assemblyParser.Rr_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 12, self.RULE_rr_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 473\n            _la = self._input.LA(1)\n            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << assemblyParser.CAO) | (1 << assemblyParser.CLO) | (1 << assemblyParser.CLS) | (1 << assemblyParser.CLZ) | (1 << assemblyParser.EXTSB) | (1 << assemblyParser.EXTSH) | (1 << assemblyParser.EXTUB) | (1 << assemblyParser.EXTUH) | (1 << assemblyParser.SATS) | (1 << assemblyParser.TIME_CFG))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Drdici_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def DIV_STEP(self):\n            return self.getToken(assemblyParser.DIV_STEP, 0)\n\n        def MUL_STEP(self):\n            return self.getToken(assemblyParser.MUL_STEP, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_drdici_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDrdici_op_code\" ):\n                listener.enterDrdici_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDrdici_op_code\" ):\n                listener.exitDrdici_op_code(self)\n\n\n\n\n    def drdici_op_code(self):\n\n        localctx = assemblyParser.Drdici_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 14, self.RULE_drdici_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 475\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.DIV_STEP or _la==assemblyParser.MUL_STEP):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrri_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LSL_ADD(self):\n            return self.getToken(assemblyParser.LSL_ADD, 0)\n\n        def LSL_SUB(self):\n            return self.getToken(assemblyParser.LSL_SUB, 0)\n\n        def LSR_ADD(self):\n            return self.getToken(assemblyParser.LSR_ADD, 0)\n\n        def ROL_ADD(self):\n            return self.getToken(assemblyParser.ROL_ADD, 0)\n\n        def ROR_ADD(self):\n            return self.getToken(assemblyParser.ROR_ADD, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrri_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrri_op_code\" ):\n                listener.enterRrri_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrri_op_code\" ):\n                listener.exitRrri_op_code(self)\n\n\n\n\n    def rrri_op_code(self):\n\n        localctx = assemblyParser.Rrri_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 16, self.RULE_rrri_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 477\n            _la = self._input.LA(1)\n            if not(((((_la - 62)) & ~0x3f) == 0 and ((1 << (_la - 62)) & ((1 << (assemblyParser.LSL_ADD - 62)) | (1 << (assemblyParser.LSL_SUB - 62)) | (1 << (assemblyParser.LSR_ADD - 62)) | (1 << (assemblyParser.ROL_ADD - 62)) | (1 << (assemblyParser.ROR_ADD - 62)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class R_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def TIME(self):\n            return self.getToken(assemblyParser.TIME, 0)\n\n        def NOP(self):\n            return self.getToken(assemblyParser.NOP, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_r_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterR_op_code\" ):\n                listener.enterR_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitR_op_code\" ):\n                listener.exitR_op_code(self)\n\n\n\n\n    def r_op_code(self):\n\n        localctx = assemblyParser.R_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 18, self.RULE_r_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 479\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.TIME or _la==assemblyParser.NOP):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ci_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def STOP(self):\n            return self.getToken(assemblyParser.STOP, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ci_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCi_op_code\" ):\n                listener.enterCi_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCi_op_code\" ):\n                listener.exitCi_op_code(self)\n\n\n\n\n    def ci_op_code(self):\n\n        localctx = assemblyParser.Ci_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 20, self.RULE_ci_op_code)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 481\n            self.match(assemblyParser.STOP)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class I_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def FAULT(self):\n            return self.getToken(assemblyParser.FAULT, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_i_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterI_op_code\" ):\n                listener.enterI_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitI_op_code\" ):\n                listener.exitI_op_code(self)\n\n\n\n\n    def i_op_code(self):\n\n        localctx = assemblyParser.I_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 22, self.RULE_i_op_code)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 483\n            self.match(assemblyParser.FAULT)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ddci_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVD(self):\n            return self.getToken(assemblyParser.MOVD, 0)\n\n        def SWAPD(self):\n            return self.getToken(assemblyParser.SWAPD, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ddci_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDdci_op_code\" ):\n                listener.enterDdci_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDdci_op_code\" ):\n                listener.exitDdci_op_code(self)\n\n\n\n\n    def ddci_op_code(self):\n\n        localctx = assemblyParser.Ddci_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 24, self.RULE_ddci_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 485\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.MOVD or _la==assemblyParser.SWAPD):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Load_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LBS(self):\n            return self.getToken(assemblyParser.LBS, 0)\n\n        def LBU(self):\n            return self.getToken(assemblyParser.LBU, 0)\n\n        def LD(self):\n            return self.getToken(assemblyParser.LD, 0)\n\n        def LHS(self):\n            return self.getToken(assemblyParser.LHS, 0)\n\n        def LHU(self):\n            return self.getToken(assemblyParser.LHU, 0)\n\n        def LW(self):\n            return self.getToken(assemblyParser.LW, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_load_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLoad_op_code\" ):\n                listener.enterLoad_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLoad_op_code\" ):\n                listener.exitLoad_op_code(self)\n\n\n\n\n    def load_op_code(self):\n\n        localctx = assemblyParser.Load_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 26, self.RULE_load_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 487\n            _la = self._input.LA(1)\n            if not(((((_la - 73)) & ~0x3f) == 0 and ((1 << (_la - 73)) & ((1 << (assemblyParser.LBS - 73)) | (1 << (assemblyParser.LBU - 73)) | (1 << (assemblyParser.LD - 73)) | (1 << (assemblyParser.LHS - 73)) | (1 << (assemblyParser.LHU - 73)) | (1 << (assemblyParser.LW - 73)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Store_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SB(self):\n            return self.getToken(assemblyParser.SB, 0)\n\n        def SB_ID(self):\n            return self.getToken(assemblyParser.SB_ID, 0)\n\n        def SD(self):\n            return self.getToken(assemblyParser.SD, 0)\n\n        def SD_ID(self):\n            return self.getToken(assemblyParser.SD_ID, 0)\n\n        def SH(self):\n            return self.getToken(assemblyParser.SH, 0)\n\n        def SH_ID(self):\n            return self.getToken(assemblyParser.SH_ID, 0)\n\n        def SW(self):\n            return self.getToken(assemblyParser.SW, 0)\n\n        def SW_ID(self):\n            return self.getToken(assemblyParser.SW_ID, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_store_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterStore_op_code\" ):\n                listener.enterStore_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitStore_op_code\" ):\n                listener.exitStore_op_code(self)\n\n\n\n\n    def store_op_code(self):\n\n        localctx = assemblyParser.Store_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 28, self.RULE_store_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 489\n            _la = self._input.LA(1)\n            if not(((((_la - 79)) & ~0x3f) == 0 and ((1 << (_la - 79)) & ((1 << (assemblyParser.SB - 79)) | (1 << (assemblyParser.SB_ID - 79)) | (1 << (assemblyParser.SD - 79)) | (1 << (assemblyParser.SD_ID - 79)) | (1 << (assemblyParser.SH - 79)) | (1 << (assemblyParser.SH_ID - 79)) | (1 << (assemblyParser.SW - 79)) | (1 << (assemblyParser.SW_ID - 79)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Dma_op_codeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LDMA(self):\n            return self.getToken(assemblyParser.LDMA, 0)\n\n        def LDMAI(self):\n            return self.getToken(assemblyParser.LDMAI, 0)\n\n        def SDMA(self):\n            return self.getToken(assemblyParser.SDMA, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_dma_op_code\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDma_op_code\" ):\n                listener.enterDma_op_code(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDma_op_code\" ):\n                listener.exitDma_op_code(self)\n\n\n\n\n    def dma_op_code(self):\n\n        localctx = assemblyParser.Dma_op_codeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 30, self.RULE_dma_op_code)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 491\n            _la = self._input.LA(1)\n            if not(((((_la - 87)) & ~0x3f) == 0 and ((1 << (_la - 87)) & ((1 << (assemblyParser.LDMA - 87)) | (1 << (assemblyParser.LDMAI - 87)) | (1 << (assemblyParser.SDMA - 87)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Section_nameContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ATOMIC(self):\n            return self.getToken(assemblyParser.ATOMIC, 0)\n\n        def BSS(self):\n            return self.getToken(assemblyParser.BSS, 0)\n\n        def DATA(self):\n            return self.getToken(assemblyParser.DATA, 0)\n\n        def DEBUG_ABBREV(self):\n            return self.getToken(assemblyParser.DEBUG_ABBREV, 0)\n\n        def DEBUG_FRAME(self):\n            return self.getToken(assemblyParser.DEBUG_FRAME, 0)\n\n        def DEBUG_INFO(self):\n            return self.getToken(assemblyParser.DEBUG_INFO, 0)\n\n        def DEBUG_LINE(self):\n            return self.getToken(assemblyParser.DEBUG_LINE, 0)\n\n        def DEBUG_LOC(self):\n            return self.getToken(assemblyParser.DEBUG_LOC, 0)\n\n        def DEBUG_RANGES(self):\n            return self.getToken(assemblyParser.DEBUG_RANGES, 0)\n\n        def DEBUG_STR(self):\n            return self.getToken(assemblyParser.DEBUG_STR, 0)\n\n        def DPU_HOST(self):\n            return self.getToken(assemblyParser.DPU_HOST, 0)\n\n        def MRAM(self):\n            return self.getToken(assemblyParser.MRAM, 0)\n\n        def RODATA(self):\n            return self.getToken(assemblyParser.RODATA, 0)\n\n        def STACK_SIZES(self):\n            return self.getToken(assemblyParser.STACK_SIZES, 0)\n\n        def TEXT_SECTION(self):\n            return self.getToken(assemblyParser.TEXT_SECTION, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_section_name\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSection_name\" ):\n                listener.enterSection_name(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSection_name\" ):\n                listener.exitSection_name(self)\n\n\n\n\n    def section_name(self):\n\n        localctx = assemblyParser.Section_nameContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 32, self.RULE_section_name)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 493\n            _la = self._input.LA(1)\n            if not(((((_la - 107)) & ~0x3f) == 0 and ((1 << (_la - 107)) & ((1 << (assemblyParser.ATOMIC - 107)) | (1 << (assemblyParser.BSS - 107)) | (1 << (assemblyParser.DATA - 107)) | (1 << (assemblyParser.DEBUG_ABBREV - 107)) | (1 << (assemblyParser.DEBUG_FRAME - 107)) | (1 << (assemblyParser.DEBUG_INFO - 107)) | (1 << (assemblyParser.DEBUG_LINE - 107)) | (1 << (assemblyParser.DEBUG_LOC - 107)) | (1 << (assemblyParser.DEBUG_RANGES - 107)) | (1 << (assemblyParser.DEBUG_STR - 107)) | (1 << (assemblyParser.DPU_HOST - 107)) | (1 << (assemblyParser.MRAM - 107)) | (1 << (assemblyParser.RODATA - 107)) | (1 << (assemblyParser.STACK_SIZES - 107)) | (1 << (assemblyParser.TEXT_SECTION - 107)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Section_typesContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def PROGBITS(self):\n            return self.getToken(assemblyParser.PROGBITS, 0)\n\n        def NOBITS(self):\n            return self.getToken(assemblyParser.NOBITS, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_section_types\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSection_types\" ):\n                listener.enterSection_types(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSection_types\" ):\n                listener.exitSection_types(self)\n\n\n\n\n    def section_types(self):\n\n        localctx = assemblyParser.Section_typesContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 34, self.RULE_section_types)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 495\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.PROGBITS or _la==assemblyParser.NOBITS):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Symbol_typeContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def FUNCTION(self):\n            return self.getToken(assemblyParser.FUNCTION, 0)\n\n        def OBJECT(self):\n            return self.getToken(assemblyParser.OBJECT, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_symbol_type\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSymbol_type\" ):\n                listener.enterSymbol_type(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSymbol_type\" ):\n                listener.exitSymbol_type(self)\n\n\n\n\n    def symbol_type(self):\n\n        localctx = assemblyParser.Symbol_typeContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 36, self.RULE_symbol_type)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 497\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.FUNCTION or _la==assemblyParser.OBJECT):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class ConditionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def TRUE(self):\n            return self.getToken(assemblyParser.TRUE, 0)\n\n        def FALSE(self):\n            return self.getToken(assemblyParser.FALSE, 0)\n\n        def Z(self):\n            return self.getToken(assemblyParser.Z, 0)\n\n        def NZ(self):\n            return self.getToken(assemblyParser.NZ, 0)\n\n        def E(self):\n            return self.getToken(assemblyParser.E, 0)\n\n        def O(self):\n            return self.getToken(assemblyParser.O, 0)\n\n        def PL(self):\n            return self.getToken(assemblyParser.PL, 0)\n\n        def MI(self):\n            return self.getToken(assemblyParser.MI, 0)\n\n        def OV(self):\n            return self.getToken(assemblyParser.OV, 0)\n\n        def NOV(self):\n            return self.getToken(assemblyParser.NOV, 0)\n\n        def C(self):\n            return self.getToken(assemblyParser.C, 0)\n\n        def NC(self):\n            return self.getToken(assemblyParser.NC, 0)\n\n        def SZ(self):\n            return self.getToken(assemblyParser.SZ, 0)\n\n        def SNZ(self):\n            return self.getToken(assemblyParser.SNZ, 0)\n\n        def SPL(self):\n            return self.getToken(assemblyParser.SPL, 0)\n\n        def SMI(self):\n            return self.getToken(assemblyParser.SMI, 0)\n\n        def SO(self):\n            return self.getToken(assemblyParser.SO, 0)\n\n        def SE(self):\n            return self.getToken(assemblyParser.SE, 0)\n\n        def NC5(self):\n            return self.getToken(assemblyParser.NC5, 0)\n\n        def NC6(self):\n            return self.getToken(assemblyParser.NC6, 0)\n\n        def NC7(self):\n            return self.getToken(assemblyParser.NC7, 0)\n\n        def NC8(self):\n            return self.getToken(assemblyParser.NC8, 0)\n\n        def NC9(self):\n            return self.getToken(assemblyParser.NC9, 0)\n\n        def NC10(self):\n            return self.getToken(assemblyParser.NC10, 0)\n\n        def NC11(self):\n            return self.getToken(assemblyParser.NC11, 0)\n\n        def NC12(self):\n            return self.getToken(assemblyParser.NC12, 0)\n\n        def NC13(self):\n            return self.getToken(assemblyParser.NC13, 0)\n\n        def NC14(self):\n            return self.getToken(assemblyParser.NC14, 0)\n\n        def MAX(self):\n            return self.getToken(assemblyParser.MAX, 0)\n\n        def NMAX(self):\n            return self.getToken(assemblyParser.NMAX, 0)\n\n        def SH32(self):\n            return self.getToken(assemblyParser.SH32, 0)\n\n        def NSH32(self):\n            return self.getToken(assemblyParser.NSH32, 0)\n\n        def EQ(self):\n            return self.getToken(assemblyParser.EQ, 0)\n\n        def NEQ(self):\n            return self.getToken(assemblyParser.NEQ, 0)\n\n        def LTU(self):\n            return self.getToken(assemblyParser.LTU, 0)\n\n        def LEU(self):\n            return self.getToken(assemblyParser.LEU, 0)\n\n        def GTU(self):\n            return self.getToken(assemblyParser.GTU, 0)\n\n        def GEU(self):\n            return self.getToken(assemblyParser.GEU, 0)\n\n        def LTS(self):\n            return self.getToken(assemblyParser.LTS, 0)\n\n        def LES(self):\n            return self.getToken(assemblyParser.LES, 0)\n\n        def GTS(self):\n            return self.getToken(assemblyParser.GTS, 0)\n\n        def GES(self):\n            return self.getToken(assemblyParser.GES, 0)\n\n        def XZ(self):\n            return self.getToken(assemblyParser.XZ, 0)\n\n        def XNZ(self):\n            return self.getToken(assemblyParser.XNZ, 0)\n\n        def XLEU(self):\n            return self.getToken(assemblyParser.XLEU, 0)\n\n        def XGTU(self):\n            return self.getToken(assemblyParser.XGTU, 0)\n\n        def XLES(self):\n            return self.getToken(assemblyParser.XLES, 0)\n\n        def XGTS(self):\n            return self.getToken(assemblyParser.XGTS, 0)\n\n        def SMALL(self):\n            return self.getToken(assemblyParser.SMALL, 0)\n\n        def LARGE(self):\n            return self.getToken(assemblyParser.LARGE, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_condition\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCondition\" ):\n                listener.enterCondition(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCondition\" ):\n                listener.exitCondition(self)\n\n\n\n\n    def condition(self):\n\n        localctx = assemblyParser.ConditionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 38, self.RULE_condition)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 499\n            _la = self._input.LA(1)\n            if not(((((_la - 126)) & ~0x3f) == 0 and ((1 << (_la - 126)) & ((1 << (assemblyParser.TRUE - 126)) | (1 << (assemblyParser.FALSE - 126)) | (1 << (assemblyParser.Z - 126)) | (1 << (assemblyParser.NZ - 126)) | (1 << (assemblyParser.E - 126)) | (1 << (assemblyParser.O - 126)) | (1 << (assemblyParser.PL - 126)) | (1 << (assemblyParser.MI - 126)) | (1 << (assemblyParser.OV - 126)) | (1 << (assemblyParser.NOV - 126)) | (1 << (assemblyParser.C - 126)) | (1 << (assemblyParser.NC - 126)) | (1 << (assemblyParser.SZ - 126)) | (1 << (assemblyParser.SNZ - 126)) | (1 << (assemblyParser.SPL - 126)) | (1 << (assemblyParser.SMI - 126)) | (1 << (assemblyParser.SO - 126)) | (1 << (assemblyParser.SE - 126)) | (1 << (assemblyParser.NC5 - 126)) | (1 << (assemblyParser.NC6 - 126)) | (1 << (assemblyParser.NC7 - 126)) | (1 << (assemblyParser.NC8 - 126)) | (1 << (assemblyParser.NC9 - 126)) | (1 << (assemblyParser.NC10 - 126)) | (1 << (assemblyParser.NC11 - 126)) | (1 << (assemblyParser.NC12 - 126)) | (1 << (assemblyParser.NC13 - 126)) | (1 << (assemblyParser.NC14 - 126)) | (1 << (assemblyParser.MAX - 126)) | (1 << (assemblyParser.NMAX - 126)) | (1 << (assemblyParser.SH32 - 126)) | (1 << (assemblyParser.NSH32 - 126)) | (1 << (assemblyParser.EQ - 126)) | (1 << (assemblyParser.NEQ - 126)) | (1 << (assemblyParser.LTU - 126)) | (1 << (assemblyParser.LEU - 126)) | (1 << (assemblyParser.GTU - 126)) | (1 << (assemblyParser.GEU - 126)) | (1 << (assemblyParser.LTS - 126)) | (1 << (assemblyParser.LES - 126)) | (1 << (assemblyParser.GTS - 126)) | (1 << (assemblyParser.GES - 126)) | (1 << (assemblyParser.XZ - 126)) | (1 << (assemblyParser.XNZ - 126)) | (1 << (assemblyParser.XLEU - 126)) | (1 << (assemblyParser.XGTU - 126)) | (1 << (assemblyParser.XLES - 126)) | (1 << (assemblyParser.XGTS - 126)) | (1 << (assemblyParser.SMALL - 126)) | (1 << (assemblyParser.LARGE - 126)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class EndianContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LITTLE(self):\n            return self.getToken(assemblyParser.LITTLE, 0)\n\n        def BIG(self):\n            return self.getToken(assemblyParser.BIG, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_endian\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterEndian\" ):\n                listener.enterEndian(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitEndian\" ):\n                listener.exitEndian(self)\n\n\n\n\n    def endian(self):\n\n        localctx = assemblyParser.EndianContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 40, self.RULE_endian)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 501\n            _la = self._input.LA(1)\n            if not(_la==assemblyParser.LITTLE or _la==assemblyParser.BIG):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sp_registerContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def ONE(self):\n            return self.getToken(assemblyParser.ONE, 0)\n\n        def ID(self):\n            return self.getToken(assemblyParser.ID, 0)\n\n        def ID2(self):\n            return self.getToken(assemblyParser.ID2, 0)\n\n        def ID4(self):\n            return self.getToken(assemblyParser.ID4, 0)\n\n        def ID8(self):\n            return self.getToken(assemblyParser.ID8, 0)\n\n        def LNEG(self):\n            return self.getToken(assemblyParser.LNEG, 0)\n\n        def MNEG(self):\n            return self.getToken(assemblyParser.MNEG, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sp_register\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSp_register\" ):\n                listener.enterSp_register(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSp_register\" ):\n                listener.exitSp_register(self)\n\n\n\n\n    def sp_register(self):\n\n        localctx = assemblyParser.Sp_registerContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 42, self.RULE_sp_register)\n        self._la = 0 # Token type\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 503\n            _la = self._input.LA(1)\n            if not(((((_la - 178)) & ~0x3f) == 0 and ((1 << (_la - 178)) & ((1 << (assemblyParser.ZERO_REGISTER - 178)) | (1 << (assemblyParser.ONE - 178)) | (1 << (assemblyParser.ID - 178)) | (1 << (assemblyParser.ID2 - 178)) | (1 << (assemblyParser.ID4 - 178)) | (1 << (assemblyParser.ID8 - 178)) | (1 << (assemblyParser.LNEG - 178)) | (1 << (assemblyParser.MNEG - 178)))) != 0)):\n                self._errHandler.recoverInline(self)\n            else:\n                self._errHandler.reportMatch(self)\n                self.consume()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Src_registerContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def sp_register(self):\n            return self.getTypedRuleContext(assemblyParser.Sp_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_src_register\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSrc_register\" ):\n                listener.enterSrc_register(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSrc_register\" ):\n                listener.exitSrc_register(self)\n\n\n\n\n    def src_register(self):\n\n        localctx = assemblyParser.Src_registerContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 44, self.RULE_src_register)\n        try:\n            self.state = 507\n            self._errHandler.sync(self)\n            token = self._input.LA(1)\n            if token in [assemblyParser.GPRegister]:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 505\n                self.match(assemblyParser.GPRegister)\n                pass\n            elif token in [assemblyParser.ZERO_REGISTER, assemblyParser.ONE, assemblyParser.ID, assemblyParser.ID2, assemblyParser.ID4, assemblyParser.ID8, assemblyParser.LNEG, assemblyParser.MNEG]:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 506\n                self.sp_register()\n                pass\n            else:\n                raise NoViableAltException(self)\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Program_counterContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def primary_expression(self):\n            return self.getTypedRuleContext(assemblyParser.Primary_expressionContext,0)\n\n\n        def add_expression(self):\n            return self.getTypedRuleContext(assemblyParser.Add_expressionContext,0)\n\n\n        def sub_expression(self):\n            return self.getTypedRuleContext(assemblyParser.Sub_expressionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_program_counter\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterProgram_counter\" ):\n                listener.enterProgram_counter(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitProgram_counter\" ):\n                listener.exitProgram_counter(self)\n\n\n\n\n    def program_counter(self):\n\n        localctx = assemblyParser.Program_counterContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 46, self.RULE_program_counter)\n        try:\n            self.state = 512\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,4,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 509\n                self.primary_expression()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 510\n                self.add_expression()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 511\n                self.sub_expression()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Add_expressionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def primary_expression(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Primary_expressionContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Primary_expressionContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_add_expression\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAdd_expression\" ):\n                listener.enterAdd_expression(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAdd_expression\" ):\n                listener.exitAdd_expression(self)\n\n\n\n\n    def add_expression(self):\n\n        localctx = assemblyParser.Add_expressionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 48, self.RULE_add_expression)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 514\n            self.primary_expression()\n            self.state = 515\n            self.match(assemblyParser.T__2)\n            self.state = 516\n            self.primary_expression()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sub_expressionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def primary_expression(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Primary_expressionContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Primary_expressionContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sub_expression\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSub_expression\" ):\n                listener.enterSub_expression(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSub_expression\" ):\n                listener.exitSub_expression(self)\n\n\n\n\n    def sub_expression(self):\n\n        localctx = assemblyParser.Sub_expressionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 50, self.RULE_sub_expression)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 518\n            self.primary_expression()\n            self.state = 519\n            self.match(assemblyParser.T__0)\n            self.state = 520\n            self.primary_expression()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Primary_expressionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def section_name(self):\n            return self.getTypedRuleContext(assemblyParser.Section_nameContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_primary_expression\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterPrimary_expression\" ):\n                listener.enterPrimary_expression(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitPrimary_expression\" ):\n                listener.exitPrimary_expression(self)\n\n\n\n\n    def primary_expression(self):\n\n        localctx = assemblyParser.Primary_expressionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 52, self.RULE_primary_expression)\n        try:\n            self.state = 525\n            self._errHandler.sync(self)\n            token = self._input.LA(1)\n            if token in [assemblyParser.T__0, assemblyParser.T__1, assemblyParser.PositiveNumber]:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 522\n                self.number()\n                pass\n            elif token in [assemblyParser.Identifier]:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 523\n                self.match(assemblyParser.Identifier)\n                pass\n            elif token in [assemblyParser.ATOMIC, assemblyParser.BSS, assemblyParser.DATA, assemblyParser.DEBUG_ABBREV, assemblyParser.DEBUG_FRAME, assemblyParser.DEBUG_INFO, assemblyParser.DEBUG_LINE, assemblyParser.DEBUG_LOC, assemblyParser.DEBUG_RANGES, assemblyParser.DEBUG_STR, assemblyParser.DPU_HOST, assemblyParser.MRAM, assemblyParser.RODATA, assemblyParser.STACK_SIZES, assemblyParser.TEXT_SECTION]:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 524\n                self.section_name()\n                pass\n            else:\n                raise NoViableAltException(self)\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class DirectiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def addrsig_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Addrsig_directiveContext,0)\n\n\n        def addrsig_sym_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Addrsig_sym_directiveContext,0)\n\n\n        def ascii_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Ascii_directiveContext,0)\n\n\n        def asciz_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Asciz_directiveContext,0)\n\n\n        def byte_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Byte_directiveContext,0)\n\n\n        def cfi_def_cfa_offset_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Cfi_def_cfa_offset_directiveContext,0)\n\n\n        def cfi_endproc_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Cfi_endproc_directiveContext,0)\n\n\n        def cfi_offset_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Cfi_offset_directiveContext,0)\n\n\n        def cfi_sections_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Cfi_sections_directiveContext,0)\n\n\n        def cfi_startproc_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Cfi_startproc_directiveContext,0)\n\n\n        def file_directive(self):\n            return self.getTypedRuleContext(assemblyParser.File_directiveContext,0)\n\n\n        def global_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Global_directiveContext,0)\n\n\n        def loc_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Loc_directiveContext,0)\n\n\n        def long_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Long_directiveContext,0)\n\n\n        def p2align_directive(self):\n            return self.getTypedRuleContext(assemblyParser.P2align_directiveContext,0)\n\n\n        def quad_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Quad_directiveContext,0)\n\n\n        def section_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Section_directiveContext,0)\n\n\n        def set_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Set_directiveContext,0)\n\n\n        def short_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Short_directiveContext,0)\n\n\n        def size_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Size_directiveContext,0)\n\n\n        def stack_sizes_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Stack_sizes_directiveContext,0)\n\n\n        def text_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Text_directiveContext,0)\n\n\n        def type_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Type_directiveContext,0)\n\n\n        def weak_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Weak_directiveContext,0)\n\n\n        def zero_directive(self):\n            return self.getTypedRuleContext(assemblyParser.Zero_directiveContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDirective\" ):\n                listener.enterDirective(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDirective\" ):\n                listener.exitDirective(self)\n\n\n\n\n    def directive(self):\n\n        localctx = assemblyParser.DirectiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 54, self.RULE_directive)\n        try:\n            self.state = 552\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,6,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 527\n                self.addrsig_directive()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 528\n                self.addrsig_sym_directive()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 529\n                self.ascii_directive()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 530\n                self.asciz_directive()\n                pass\n\n            elif la_ == 5:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 531\n                self.byte_directive()\n                pass\n\n            elif la_ == 6:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 532\n                self.cfi_def_cfa_offset_directive()\n                pass\n\n            elif la_ == 7:\n                self.enterOuterAlt(localctx, 7)\n                self.state = 533\n                self.cfi_endproc_directive()\n                pass\n\n            elif la_ == 8:\n                self.enterOuterAlt(localctx, 8)\n                self.state = 534\n                self.cfi_offset_directive()\n                pass\n\n            elif la_ == 9:\n                self.enterOuterAlt(localctx, 9)\n                self.state = 535\n                self.cfi_sections_directive()\n                pass\n\n            elif la_ == 10:\n                self.enterOuterAlt(localctx, 10)\n                self.state = 536\n                self.cfi_startproc_directive()\n                pass\n\n            elif la_ == 11:\n                self.enterOuterAlt(localctx, 11)\n                self.state = 537\n                self.file_directive()\n                pass\n\n            elif la_ == 12:\n                self.enterOuterAlt(localctx, 12)\n                self.state = 538\n                self.global_directive()\n                pass\n\n            elif la_ == 13:\n                self.enterOuterAlt(localctx, 13)\n                self.state = 539\n                self.loc_directive()\n                pass\n\n            elif la_ == 14:\n                self.enterOuterAlt(localctx, 14)\n                self.state = 540\n                self.long_directive()\n                pass\n\n            elif la_ == 15:\n                self.enterOuterAlt(localctx, 15)\n                self.state = 541\n                self.p2align_directive()\n                pass\n\n            elif la_ == 16:\n                self.enterOuterAlt(localctx, 16)\n                self.state = 542\n                self.quad_directive()\n                pass\n\n            elif la_ == 17:\n                self.enterOuterAlt(localctx, 17)\n                self.state = 543\n                self.section_directive()\n                pass\n\n            elif la_ == 18:\n                self.enterOuterAlt(localctx, 18)\n                self.state = 544\n                self.set_directive()\n                pass\n\n            elif la_ == 19:\n                self.enterOuterAlt(localctx, 19)\n                self.state = 545\n                self.short_directive()\n                pass\n\n            elif la_ == 20:\n                self.enterOuterAlt(localctx, 20)\n                self.state = 546\n                self.size_directive()\n                pass\n\n            elif la_ == 21:\n                self.enterOuterAlt(localctx, 21)\n                self.state = 547\n                self.stack_sizes_directive()\n                pass\n\n            elif la_ == 22:\n                self.enterOuterAlt(localctx, 22)\n                self.state = 548\n                self.text_directive()\n                pass\n\n            elif la_ == 23:\n                self.enterOuterAlt(localctx, 23)\n                self.state = 549\n                self.type_directive()\n                pass\n\n            elif la_ == 24:\n                self.enterOuterAlt(localctx, 24)\n                self.state = 550\n                self.weak_directive()\n                pass\n\n            elif la_ == 25:\n                self.enterOuterAlt(localctx, 25)\n                self.state = 551\n                self.zero_directive()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Addrsig_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ADDRSIG(self):\n            return self.getToken(assemblyParser.ADDRSIG, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_addrsig_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAddrsig_directive\" ):\n                listener.enterAddrsig_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAddrsig_directive\" ):\n                listener.exitAddrsig_directive(self)\n\n\n\n\n    def addrsig_directive(self):\n\n        localctx = assemblyParser.Addrsig_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 56, self.RULE_addrsig_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 554\n            self.match(assemblyParser.ADDRSIG)\n            self.state = 555\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Addrsig_sym_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ADDRSIG_SYM(self):\n            return self.getToken(assemblyParser.ADDRSIG_SYM, 0)\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_addrsig_sym_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAddrsig_sym_directive\" ):\n                listener.enterAddrsig_sym_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAddrsig_sym_directive\" ):\n                listener.exitAddrsig_sym_directive(self)\n\n\n\n\n    def addrsig_sym_directive(self):\n\n        localctx = assemblyParser.Addrsig_sym_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 58, self.RULE_addrsig_sym_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 557\n            self.match(assemblyParser.ADDRSIG_SYM)\n            self.state = 558\n            self.match(assemblyParser.T__3)\n            self.state = 559\n            self.match(assemblyParser.Identifier)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ascii_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ASCII(self):\n            return self.getToken(assemblyParser.ASCII, 0)\n\n        def StringLiteral(self):\n            return self.getToken(assemblyParser.StringLiteral, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ascii_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAscii_directive\" ):\n                listener.enterAscii_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAscii_directive\" ):\n                listener.exitAscii_directive(self)\n\n\n\n\n    def ascii_directive(self):\n\n        localctx = assemblyParser.Ascii_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 60, self.RULE_ascii_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 561\n            self.match(assemblyParser.ASCII)\n            self.state = 562\n            self.match(assemblyParser.T__3)\n            self.state = 563\n            self.match(assemblyParser.StringLiteral)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Asciz_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ASCIZ(self):\n            return self.getToken(assemblyParser.ASCIZ, 0)\n\n        def StringLiteral(self):\n            return self.getToken(assemblyParser.StringLiteral, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_asciz_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAsciz_directive\" ):\n                listener.enterAsciz_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAsciz_directive\" ):\n                listener.exitAsciz_directive(self)\n\n\n\n\n    def asciz_directive(self):\n\n        localctx = assemblyParser.Asciz_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 62, self.RULE_asciz_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 565\n            self.match(assemblyParser.ASCIZ)\n            self.state = 566\n            self.match(assemblyParser.T__3)\n            self.state = 567\n            self.match(assemblyParser.StringLiteral)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Byte_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def BYTE(self):\n            return self.getToken(assemblyParser.BYTE, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_byte_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterByte_directive\" ):\n                listener.enterByte_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitByte_directive\" ):\n                listener.exitByte_directive(self)\n\n\n\n\n    def byte_directive(self):\n\n        localctx = assemblyParser.Byte_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 64, self.RULE_byte_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 569\n            self.match(assemblyParser.BYTE)\n            self.state = 570\n            self.match(assemblyParser.T__3)\n            self.state = 571\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Cfi_def_cfa_offset_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CFI_DEF_CFA_OFFSET(self):\n            return self.getToken(assemblyParser.CFI_DEF_CFA_OFFSET, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_cfi_def_cfa_offset_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCfi_def_cfa_offset_directive\" ):\n                listener.enterCfi_def_cfa_offset_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCfi_def_cfa_offset_directive\" ):\n                listener.exitCfi_def_cfa_offset_directive(self)\n\n\n\n\n    def cfi_def_cfa_offset_directive(self):\n\n        localctx = assemblyParser.Cfi_def_cfa_offset_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 66, self.RULE_cfi_def_cfa_offset_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 573\n            self.match(assemblyParser.CFI_DEF_CFA_OFFSET)\n            self.state = 574\n            self.match(assemblyParser.T__3)\n            self.state = 575\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Cfi_endproc_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CFI_ENDPROC(self):\n            return self.getToken(assemblyParser.CFI_ENDPROC, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_cfi_endproc_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCfi_endproc_directive\" ):\n                listener.enterCfi_endproc_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCfi_endproc_directive\" ):\n                listener.exitCfi_endproc_directive(self)\n\n\n\n\n    def cfi_endproc_directive(self):\n\n        localctx = assemblyParser.Cfi_endproc_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 68, self.RULE_cfi_endproc_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 577\n            self.match(assemblyParser.CFI_ENDPROC)\n            self.state = 578\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Cfi_offset_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CFI_OFFSET(self):\n            return self.getToken(assemblyParser.CFI_OFFSET, 0)\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_cfi_offset_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCfi_offset_directive\" ):\n                listener.enterCfi_offset_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCfi_offset_directive\" ):\n                listener.exitCfi_offset_directive(self)\n\n\n\n\n    def cfi_offset_directive(self):\n\n        localctx = assemblyParser.Cfi_offset_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 70, self.RULE_cfi_offset_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 580\n            self.match(assemblyParser.CFI_OFFSET)\n            self.state = 581\n            self.match(assemblyParser.T__3)\n            self.state = 582\n            self.number()\n            self.state = 583\n            self.match(assemblyParser.T__3)\n            self.state = 584\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Cfi_sections_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CFI_SECTIONS(self):\n            return self.getToken(assemblyParser.CFI_SECTIONS, 0)\n\n        def section_name(self):\n            return self.getTypedRuleContext(assemblyParser.Section_nameContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_cfi_sections_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCfi_sections_directive\" ):\n                listener.enterCfi_sections_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCfi_sections_directive\" ):\n                listener.exitCfi_sections_directive(self)\n\n\n\n\n    def cfi_sections_directive(self):\n\n        localctx = assemblyParser.Cfi_sections_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 72, self.RULE_cfi_sections_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 586\n            self.match(assemblyParser.CFI_SECTIONS)\n            self.state = 587\n            self.match(assemblyParser.T__3)\n            self.state = 588\n            self.section_name()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Cfi_startproc_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CFI_STARTPROC(self):\n            return self.getToken(assemblyParser.CFI_STARTPROC, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_cfi_startproc_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCfi_startproc_directive\" ):\n                listener.enterCfi_startproc_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCfi_startproc_directive\" ):\n                listener.exitCfi_startproc_directive(self)\n\n\n\n\n    def cfi_startproc_directive(self):\n\n        localctx = assemblyParser.Cfi_startproc_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 74, self.RULE_cfi_startproc_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 590\n            self.match(assemblyParser.CFI_STARTPROC)\n            self.state = 591\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class File_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def FILE(self):\n            return self.getToken(assemblyParser.FILE, 0)\n\n        def StringLiteral(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.StringLiteral)\n            else:\n                return self.getToken(assemblyParser.StringLiteral, i)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_file_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterFile_directive\" ):\n                listener.enterFile_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitFile_directive\" ):\n                listener.exitFile_directive(self)\n\n\n\n\n    def file_directive(self):\n\n        localctx = assemblyParser.File_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 76, self.RULE_file_directive)\n        try:\n            self.state = 602\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,7,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 593\n                self.match(assemblyParser.FILE)\n                self.state = 594\n                self.match(assemblyParser.T__3)\n                self.state = 595\n                self.match(assemblyParser.StringLiteral)\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 596\n                self.match(assemblyParser.FILE)\n                self.state = 597\n                self.match(assemblyParser.T__3)\n                self.state = 598\n                self.number()\n                self.state = 599\n                self.match(assemblyParser.StringLiteral)\n                self.state = 600\n                self.match(assemblyParser.StringLiteral)\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Global_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def GLOBL(self):\n            return self.getToken(assemblyParser.GLOBL, 0)\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_global_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterGlobal_directive\" ):\n                listener.enterGlobal_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitGlobal_directive\" ):\n                listener.exitGlobal_directive(self)\n\n\n\n\n    def global_directive(self):\n\n        localctx = assemblyParser.Global_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 78, self.RULE_global_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 604\n            self.match(assemblyParser.GLOBL)\n            self.state = 605\n            self.match(assemblyParser.T__3)\n            self.state = 606\n            self.match(assemblyParser.Identifier)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Loc_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LOC(self):\n            return self.getToken(assemblyParser.LOC, 0)\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def IS_STMT(self):\n            return self.getToken(assemblyParser.IS_STMT, 0)\n\n        def PROLOGUE_END(self):\n            return self.getToken(assemblyParser.PROLOGUE_END, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_loc_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLoc_directive\" ):\n                listener.enterLoc_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLoc_directive\" ):\n                listener.exitLoc_directive(self)\n\n\n\n\n    def loc_directive(self):\n\n        localctx = assemblyParser.Loc_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 80, self.RULE_loc_directive)\n        try:\n            self.state = 629\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,8,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 608\n                self.match(assemblyParser.LOC)\n                self.state = 609\n                self.match(assemblyParser.T__3)\n                self.state = 610\n                self.number()\n                self.state = 611\n                self.number()\n                self.state = 612\n                self.number()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 614\n                self.match(assemblyParser.LOC)\n                self.state = 615\n                self.match(assemblyParser.T__3)\n                self.state = 616\n                self.number()\n                self.state = 617\n                self.number()\n                self.state = 618\n                self.number()\n                self.state = 619\n                self.match(assemblyParser.IS_STMT)\n                self.state = 620\n                self.number()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 622\n                self.match(assemblyParser.LOC)\n                self.state = 623\n                self.match(assemblyParser.T__3)\n                self.state = 624\n                self.number()\n                self.state = 625\n                self.number()\n                self.state = 626\n                self.number()\n                self.state = 627\n                self.match(assemblyParser.PROLOGUE_END)\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Long_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LONG(self):\n            return self.getToken(assemblyParser.LONG, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_long_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLong_directive\" ):\n                listener.enterLong_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLong_directive\" ):\n                listener.exitLong_directive(self)\n\n\n\n\n    def long_directive(self):\n\n        localctx = assemblyParser.Long_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 82, self.RULE_long_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 631\n            self.match(assemblyParser.LONG)\n            self.state = 632\n            self.match(assemblyParser.T__3)\n            self.state = 633\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class P2align_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def P2ALIGN(self):\n            return self.getToken(assemblyParser.P2ALIGN, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_p2align_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterP2align_directive\" ):\n                listener.enterP2align_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitP2align_directive\" ):\n                listener.exitP2align_directive(self)\n\n\n\n\n    def p2align_directive(self):\n\n        localctx = assemblyParser.P2align_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 84, self.RULE_p2align_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 635\n            self.match(assemblyParser.P2ALIGN)\n            self.state = 636\n            self.match(assemblyParser.T__3)\n            self.state = 637\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Quad_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def QUAD(self):\n            return self.getToken(assemblyParser.QUAD, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_quad_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterQuad_directive\" ):\n                listener.enterQuad_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitQuad_directive\" ):\n                listener.exitQuad_directive(self)\n\n\n\n\n    def quad_directive(self):\n\n        localctx = assemblyParser.Quad_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 86, self.RULE_quad_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 639\n            self.match(assemblyParser.QUAD)\n            self.state = 640\n            self.match(assemblyParser.T__3)\n            self.state = 641\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Section_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SECTION(self):\n            return self.getToken(assemblyParser.SECTION, 0)\n\n        def section_name(self):\n            return self.getTypedRuleContext(assemblyParser.Section_nameContext,0)\n\n\n        def StringLiteral(self):\n            return self.getToken(assemblyParser.StringLiteral, 0)\n\n        def section_types(self):\n            return self.getTypedRuleContext(assemblyParser.Section_typesContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_section_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSection_directive\" ):\n                listener.enterSection_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSection_directive\" ):\n                listener.exitSection_directive(self)\n\n\n\n\n    def section_directive(self):\n\n        localctx = assemblyParser.Section_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 88, self.RULE_section_directive)\n        try:\n            self.state = 683\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,9,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 643\n                self.match(assemblyParser.SECTION)\n                self.state = 644\n                self.match(assemblyParser.T__3)\n                self.state = 645\n                self.section_name()\n                self.state = 646\n                self.match(assemblyParser.T__3)\n                self.state = 647\n                self.match(assemblyParser.StringLiteral)\n                self.state = 648\n                self.match(assemblyParser.T__3)\n                self.state = 649\n                self.section_types()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 651\n                self.match(assemblyParser.SECTION)\n                self.state = 652\n                self.match(assemblyParser.T__3)\n                self.state = 653\n                self.section_name()\n                self.state = 654\n                self.match(assemblyParser.T__3)\n                self.state = 655\n                self.match(assemblyParser.StringLiteral)\n                self.state = 656\n                self.match(assemblyParser.T__3)\n                self.state = 657\n                self.section_types()\n                self.state = 658\n                self.match(assemblyParser.T__3)\n                self.state = 659\n                self.number()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 661\n                self.match(assemblyParser.SECTION)\n                self.state = 662\n                self.match(assemblyParser.T__3)\n                self.state = 663\n                self.section_name()\n                self.state = 664\n                self.match(assemblyParser.T__3)\n                self.state = 665\n                self.match(assemblyParser.Identifier)\n                self.state = 666\n                self.match(assemblyParser.T__3)\n                self.state = 667\n                self.match(assemblyParser.StringLiteral)\n                self.state = 668\n                self.match(assemblyParser.T__3)\n                self.state = 669\n                self.section_types()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 671\n                self.match(assemblyParser.SECTION)\n                self.state = 672\n                self.match(assemblyParser.T__3)\n                self.state = 673\n                self.section_name()\n                self.state = 674\n                self.match(assemblyParser.T__3)\n                self.state = 675\n                self.match(assemblyParser.Identifier)\n                self.state = 676\n                self.match(assemblyParser.T__3)\n                self.state = 677\n                self.match(assemblyParser.StringLiteral)\n                self.state = 678\n                self.match(assemblyParser.T__3)\n                self.state = 679\n                self.section_types()\n                self.state = 680\n                self.match(assemblyParser.T__3)\n                self.state = 681\n                self.number()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Set_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SET(self):\n            return self.getToken(assemblyParser.SET, 0)\n\n        def Identifier(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.Identifier)\n            else:\n                return self.getToken(assemblyParser.Identifier, i)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_set_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSet_directive\" ):\n                listener.enterSet_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSet_directive\" ):\n                listener.exitSet_directive(self)\n\n\n\n\n    def set_directive(self):\n\n        localctx = assemblyParser.Set_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 90, self.RULE_set_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 685\n            self.match(assemblyParser.SET)\n            self.state = 686\n            self.match(assemblyParser.T__3)\n            self.state = 687\n            self.match(assemblyParser.Identifier)\n            self.state = 688\n            self.match(assemblyParser.T__3)\n            self.state = 689\n            self.match(assemblyParser.Identifier)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Short_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SHORT(self):\n            return self.getToken(assemblyParser.SHORT, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_short_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterShort_directive\" ):\n                listener.enterShort_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitShort_directive\" ):\n                listener.exitShort_directive(self)\n\n\n\n\n    def short_directive(self):\n\n        localctx = assemblyParser.Short_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 92, self.RULE_short_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 691\n            self.match(assemblyParser.SHORT)\n            self.state = 692\n            self.match(assemblyParser.T__3)\n            self.state = 693\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Size_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SIZE(self):\n            return self.getToken(assemblyParser.SIZE, 0)\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_size_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSize_directive\" ):\n                listener.enterSize_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSize_directive\" ):\n                listener.exitSize_directive(self)\n\n\n\n\n    def size_directive(self):\n\n        localctx = assemblyParser.Size_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 94, self.RULE_size_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 695\n            self.match(assemblyParser.SIZE)\n            self.state = 696\n            self.match(assemblyParser.T__3)\n            self.state = 697\n            self.match(assemblyParser.Identifier)\n            self.state = 698\n            self.match(assemblyParser.T__3)\n            self.state = 699\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Stack_sizes_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SECTION(self):\n            return self.getToken(assemblyParser.SECTION, 0)\n\n        def STACK_SIZES(self):\n            return self.getToken(assemblyParser.STACK_SIZES, 0)\n\n        def StringLiteral(self):\n            return self.getToken(assemblyParser.StringLiteral, 0)\n\n        def section_types(self):\n            return self.getTypedRuleContext(assemblyParser.Section_typesContext,0)\n\n\n        def section_name(self):\n            return self.getTypedRuleContext(assemblyParser.Section_nameContext,0)\n\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_stack_sizes_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterStack_sizes_directive\" ):\n                listener.enterStack_sizes_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitStack_sizes_directive\" ):\n                listener.exitStack_sizes_directive(self)\n\n\n\n\n    def stack_sizes_directive(self):\n\n        localctx = assemblyParser.Stack_sizes_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 96, self.RULE_stack_sizes_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 701\n            self.match(assemblyParser.SECTION)\n            self.state = 702\n            self.match(assemblyParser.T__3)\n            self.state = 703\n            self.match(assemblyParser.STACK_SIZES)\n            self.state = 704\n            self.match(assemblyParser.T__3)\n            self.state = 705\n            self.match(assemblyParser.StringLiteral)\n            self.state = 706\n            self.match(assemblyParser.T__3)\n            self.state = 707\n            self.section_types()\n            self.state = 708\n            self.match(assemblyParser.T__3)\n            self.state = 709\n            self.section_name()\n            self.state = 710\n            self.match(assemblyParser.T__3)\n            self.state = 711\n            self.match(assemblyParser.Identifier)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Text_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def TEXT_DIRECTIVE(self):\n            return self.getToken(assemblyParser.TEXT_DIRECTIVE, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_text_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterText_directive\" ):\n                listener.enterText_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitText_directive\" ):\n                listener.exitText_directive(self)\n\n\n\n\n    def text_directive(self):\n\n        localctx = assemblyParser.Text_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 98, self.RULE_text_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 713\n            self.match(assemblyParser.TEXT_DIRECTIVE)\n            self.state = 714\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Type_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def TYPE(self):\n            return self.getToken(assemblyParser.TYPE, 0)\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def symbol_type(self):\n            return self.getTypedRuleContext(assemblyParser.Symbol_typeContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_type_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterType_directive\" ):\n                listener.enterType_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitType_directive\" ):\n                listener.exitType_directive(self)\n\n\n\n\n    def type_directive(self):\n\n        localctx = assemblyParser.Type_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 100, self.RULE_type_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 716\n            self.match(assemblyParser.TYPE)\n            self.state = 717\n            self.match(assemblyParser.T__3)\n            self.state = 718\n            self.match(assemblyParser.Identifier)\n            self.state = 719\n            self.match(assemblyParser.T__3)\n            self.state = 720\n            self.symbol_type()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Weak_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def WEAK(self):\n            return self.getToken(assemblyParser.WEAK, 0)\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_weak_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterWeak_directive\" ):\n                listener.enterWeak_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitWeak_directive\" ):\n                listener.exitWeak_directive(self)\n\n\n\n\n    def weak_directive(self):\n\n        localctx = assemblyParser.Weak_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 102, self.RULE_weak_directive)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 722\n            self.match(assemblyParser.WEAK)\n            self.state = 723\n            self.match(assemblyParser.T__3)\n            self.state = 724\n            self.match(assemblyParser.Identifier)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zero_directiveContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ZERO_DIRECTIVE(self):\n            return self.getToken(assemblyParser.ZERO_DIRECTIVE, 0)\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zero_directive\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZero_directive\" ):\n                listener.enterZero_directive(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZero_directive\" ):\n                listener.exitZero_directive(self)\n\n\n\n\n    def zero_directive(self):\n\n        localctx = assemblyParser.Zero_directiveContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 104, self.RULE_zero_directive)\n        try:\n            self.state = 735\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,10,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 726\n                self.match(assemblyParser.ZERO_DIRECTIVE)\n                self.state = 727\n                self.match(assemblyParser.T__3)\n                self.state = 728\n                self.number()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 729\n                self.match(assemblyParser.ZERO_DIRECTIVE)\n                self.state = 730\n                self.match(assemblyParser.T__3)\n                self.state = 731\n                self.number()\n                self.state = 732\n                self.match(assemblyParser.T__3)\n                self.state = 733\n                self.number()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class InstructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rici_instructionContext,0)\n\n\n        def rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_instructionContext,0)\n\n\n        def rric_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rric_instructionContext,0)\n\n\n        def rrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrici_instructionContext,0)\n\n\n        def rrr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrr_instructionContext,0)\n\n\n        def rrrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrrc_instructionContext,0)\n\n\n        def rrrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrrci_instructionContext,0)\n\n\n        def zri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zri_instructionContext,0)\n\n\n        def zric_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zric_instructionContext,0)\n\n\n        def zrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrici_instructionContext,0)\n\n\n        def zrr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrr_instructionContext,0)\n\n\n        def zrrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrrc_instructionContext,0)\n\n\n        def zrrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrrci_instructionContext,0)\n\n\n        def s_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rri_instructionContext,0)\n\n\n        def s_rric_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rric_instructionContext,0)\n\n\n        def s_rrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrici_instructionContext,0)\n\n\n        def s_rrr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrr_instructionContext,0)\n\n\n        def s_rrrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrrc_instructionContext,0)\n\n\n        def s_rrrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrrci_instructionContext,0)\n\n\n        def u_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rri_instructionContext,0)\n\n\n        def u_rric_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rric_instructionContext,0)\n\n\n        def u_rrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrici_instructionContext,0)\n\n\n        def u_rrr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrr_instructionContext,0)\n\n\n        def u_rrrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrrc_instructionContext,0)\n\n\n        def u_rrrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrrci_instructionContext,0)\n\n\n        def rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_instructionContext,0)\n\n\n        def rrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrc_instructionContext,0)\n\n\n        def rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrci_instructionContext,0)\n\n\n        def zr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zr_instructionContext,0)\n\n\n        def zrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrc_instructionContext,0)\n\n\n        def zrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrci_instructionContext,0)\n\n\n        def s_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rr_instructionContext,0)\n\n\n        def s_rrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrc_instructionContext,0)\n\n\n        def s_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrci_instructionContext,0)\n\n\n        def u_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rr_instructionContext,0)\n\n\n        def u_rrc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrc_instructionContext,0)\n\n\n        def u_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrci_instructionContext,0)\n\n\n        def drdici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Drdici_instructionContext,0)\n\n\n        def rrri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_instructionContext,0)\n\n\n        def rrrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrrici_instructionContext,0)\n\n\n        def zrri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrri_instructionContext,0)\n\n\n        def zrrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zrrici_instructionContext,0)\n\n\n        def s_rrri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrri_instructionContext,0)\n\n\n        def s_rrrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rrrici_instructionContext,0)\n\n\n        def u_rrri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrri_instructionContext,0)\n\n\n        def u_rrrici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rrrici_instructionContext,0)\n\n\n        def rir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rir_instructionContext,0)\n\n\n        def rirc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rirc_instructionContext,0)\n\n\n        def rirci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rirci_instructionContext,0)\n\n\n        def zir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zir_instructionContext,0)\n\n\n        def zirc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zirc_instructionContext,0)\n\n\n        def s_rirc_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rirc_instructionContext,0)\n\n\n        def s_rirci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rirci_instructionContext,0)\n\n\n        def r_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.R_instructionContext,0)\n\n\n        def rci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rci_instructionContext,0)\n\n\n        def z_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Z_instructionContext,0)\n\n\n        def zci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Zci_instructionContext,0)\n\n\n        def s_r_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_r_instructionContext,0)\n\n\n        def s_rci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_rci_instructionContext,0)\n\n\n        def u_r_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_r_instructionContext,0)\n\n\n        def u_rci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_rci_instructionContext,0)\n\n\n        def ci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Ci_instructionContext,0)\n\n\n        def i_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.I_instructionContext,0)\n\n\n        def ddci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Ddci_instructionContext,0)\n\n\n        def erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Erri_instructionContext,0)\n\n\n        def edri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Edri_instructionContext,0)\n\n\n        def s_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.S_erri_instructionContext,0)\n\n\n        def u_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.U_erri_instructionContext,0)\n\n\n        def erii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Erii_instructionContext,0)\n\n\n        def erir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Erir_instructionContext,0)\n\n\n        def erid_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Erid_instructionContext,0)\n\n\n        def dma_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Dma_rri_instructionContext,0)\n\n\n        def synthetic_sugar_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Synthetic_sugar_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterInstruction\" ):\n                listener.enterInstruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitInstruction\" ):\n                listener.exitInstruction(self)\n\n\n\n\n    def instruction(self):\n\n        localctx = assemblyParser.InstructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 106, self.RULE_instruction)\n        try:\n            self.state = 813\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,11,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 737\n                self.rici_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 738\n                self.rri_instruction()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 739\n                self.rric_instruction()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 740\n                self.rrici_instruction()\n                pass\n\n            elif la_ == 5:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 741\n                self.rrr_instruction()\n                pass\n\n            elif la_ == 6:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 742\n                self.rrrc_instruction()\n                pass\n\n            elif la_ == 7:\n                self.enterOuterAlt(localctx, 7)\n                self.state = 743\n                self.rrrci_instruction()\n                pass\n\n            elif la_ == 8:\n                self.enterOuterAlt(localctx, 8)\n                self.state = 744\n                self.zri_instruction()\n                pass\n\n            elif la_ == 9:\n                self.enterOuterAlt(localctx, 9)\n                self.state = 745\n                self.zric_instruction()\n                pass\n\n            elif la_ == 10:\n                self.enterOuterAlt(localctx, 10)\n                self.state = 746\n                self.zrici_instruction()\n                pass\n\n            elif la_ == 11:\n                self.enterOuterAlt(localctx, 11)\n                self.state = 747\n                self.zrr_instruction()\n                pass\n\n            elif la_ == 12:\n                self.enterOuterAlt(localctx, 12)\n                self.state = 748\n                self.zrrc_instruction()\n                pass\n\n            elif la_ == 13:\n                self.enterOuterAlt(localctx, 13)\n                self.state = 749\n                self.zrrci_instruction()\n                pass\n\n            elif la_ == 14:\n                self.enterOuterAlt(localctx, 14)\n                self.state = 750\n                self.s_rri_instruction()\n                pass\n\n            elif la_ == 15:\n                self.enterOuterAlt(localctx, 15)\n                self.state = 751\n                self.s_rric_instruction()\n                pass\n\n            elif la_ == 16:\n                self.enterOuterAlt(localctx, 16)\n                self.state = 752\n                self.s_rrici_instruction()\n                pass\n\n            elif la_ == 17:\n                self.enterOuterAlt(localctx, 17)\n                self.state = 753\n                self.s_rrr_instruction()\n                pass\n\n            elif la_ == 18:\n                self.enterOuterAlt(localctx, 18)\n                self.state = 754\n                self.s_rrrc_instruction()\n                pass\n\n            elif la_ == 19:\n                self.enterOuterAlt(localctx, 19)\n                self.state = 755\n                self.s_rrrci_instruction()\n                pass\n\n            elif la_ == 20:\n                self.enterOuterAlt(localctx, 20)\n                self.state = 756\n                self.u_rri_instruction()\n                pass\n\n            elif la_ == 21:\n                self.enterOuterAlt(localctx, 21)\n                self.state = 757\n                self.u_rric_instruction()\n                pass\n\n            elif la_ == 22:\n                self.enterOuterAlt(localctx, 22)\n                self.state = 758\n                self.u_rrici_instruction()\n                pass\n\n            elif la_ == 23:\n                self.enterOuterAlt(localctx, 23)\n                self.state = 759\n                self.u_rrr_instruction()\n                pass\n\n            elif la_ == 24:\n                self.enterOuterAlt(localctx, 24)\n                self.state = 760\n                self.u_rrrc_instruction()\n                pass\n\n            elif la_ == 25:\n                self.enterOuterAlt(localctx, 25)\n                self.state = 761\n                self.u_rrrci_instruction()\n                pass\n\n            elif la_ == 26:\n                self.enterOuterAlt(localctx, 26)\n                self.state = 762\n                self.rr_instruction()\n                pass\n\n            elif la_ == 27:\n                self.enterOuterAlt(localctx, 27)\n                self.state = 763\n                self.rrc_instruction()\n                pass\n\n            elif la_ == 28:\n                self.enterOuterAlt(localctx, 28)\n                self.state = 764\n                self.rrci_instruction()\n                pass\n\n            elif la_ == 29:\n                self.enterOuterAlt(localctx, 29)\n                self.state = 765\n                self.zr_instruction()\n                pass\n\n            elif la_ == 30:\n                self.enterOuterAlt(localctx, 30)\n                self.state = 766\n                self.zrc_instruction()\n                pass\n\n            elif la_ == 31:\n                self.enterOuterAlt(localctx, 31)\n                self.state = 767\n                self.zrci_instruction()\n                pass\n\n            elif la_ == 32:\n                self.enterOuterAlt(localctx, 32)\n                self.state = 768\n                self.s_rr_instruction()\n                pass\n\n            elif la_ == 33:\n                self.enterOuterAlt(localctx, 33)\n                self.state = 769\n                self.s_rrc_instruction()\n                pass\n\n            elif la_ == 34:\n                self.enterOuterAlt(localctx, 34)\n                self.state = 770\n                self.s_rrci_instruction()\n                pass\n\n            elif la_ == 35:\n                self.enterOuterAlt(localctx, 35)\n                self.state = 771\n                self.u_rr_instruction()\n                pass\n\n            elif la_ == 36:\n                self.enterOuterAlt(localctx, 36)\n                self.state = 772\n                self.u_rrc_instruction()\n                pass\n\n            elif la_ == 37:\n                self.enterOuterAlt(localctx, 37)\n                self.state = 773\n                self.u_rrci_instruction()\n                pass\n\n            elif la_ == 38:\n                self.enterOuterAlt(localctx, 38)\n                self.state = 774\n                self.drdici_instruction()\n                pass\n\n            elif la_ == 39:\n                self.enterOuterAlt(localctx, 39)\n                self.state = 775\n                self.rrri_instruction()\n                pass\n\n            elif la_ == 40:\n                self.enterOuterAlt(localctx, 40)\n                self.state = 776\n                self.rrrici_instruction()\n                pass\n\n            elif la_ == 41:\n                self.enterOuterAlt(localctx, 41)\n                self.state = 777\n                self.zrri_instruction()\n                pass\n\n            elif la_ == 42:\n                self.enterOuterAlt(localctx, 42)\n                self.state = 778\n                self.zrrici_instruction()\n                pass\n\n            elif la_ == 43:\n                self.enterOuterAlt(localctx, 43)\n                self.state = 779\n                self.s_rrri_instruction()\n                pass\n\n            elif la_ == 44:\n                self.enterOuterAlt(localctx, 44)\n                self.state = 780\n                self.s_rrrici_instruction()\n                pass\n\n            elif la_ == 45:\n                self.enterOuterAlt(localctx, 45)\n                self.state = 781\n                self.u_rrri_instruction()\n                pass\n\n            elif la_ == 46:\n                self.enterOuterAlt(localctx, 46)\n                self.state = 782\n                self.u_rrrici_instruction()\n                pass\n\n            elif la_ == 47:\n                self.enterOuterAlt(localctx, 47)\n                self.state = 783\n                self.rir_instruction()\n                pass\n\n            elif la_ == 48:\n                self.enterOuterAlt(localctx, 48)\n                self.state = 784\n                self.rirc_instruction()\n                pass\n\n            elif la_ == 49:\n                self.enterOuterAlt(localctx, 49)\n                self.state = 785\n                self.rirci_instruction()\n                pass\n\n            elif la_ == 50:\n                self.enterOuterAlt(localctx, 50)\n                self.state = 786\n                self.zir_instruction()\n                pass\n\n            elif la_ == 51:\n                self.enterOuterAlt(localctx, 51)\n                self.state = 787\n                self.zirc_instruction()\n                pass\n\n            elif la_ == 52:\n                self.enterOuterAlt(localctx, 52)\n                self.state = 788\n                self.zrici_instruction()\n                pass\n\n            elif la_ == 53:\n                self.enterOuterAlt(localctx, 53)\n                self.state = 789\n                self.s_rirc_instruction()\n                pass\n\n            elif la_ == 54:\n                self.enterOuterAlt(localctx, 54)\n                self.state = 790\n                self.s_rirci_instruction()\n                pass\n\n            elif la_ == 55:\n                self.enterOuterAlt(localctx, 55)\n                self.state = 791\n                self.u_rric_instruction()\n                pass\n\n            elif la_ == 56:\n                self.enterOuterAlt(localctx, 56)\n                self.state = 792\n                self.u_rrici_instruction()\n                pass\n\n            elif la_ == 57:\n                self.enterOuterAlt(localctx, 57)\n                self.state = 793\n                self.r_instruction()\n                pass\n\n            elif la_ == 58:\n                self.enterOuterAlt(localctx, 58)\n                self.state = 794\n                self.rci_instruction()\n                pass\n\n            elif la_ == 59:\n                self.enterOuterAlt(localctx, 59)\n                self.state = 795\n                self.z_instruction()\n                pass\n\n            elif la_ == 60:\n                self.enterOuterAlt(localctx, 60)\n                self.state = 796\n                self.zci_instruction()\n                pass\n\n            elif la_ == 61:\n                self.enterOuterAlt(localctx, 61)\n                self.state = 797\n                self.s_r_instruction()\n                pass\n\n            elif la_ == 62:\n                self.enterOuterAlt(localctx, 62)\n                self.state = 798\n                self.s_rci_instruction()\n                pass\n\n            elif la_ == 63:\n                self.enterOuterAlt(localctx, 63)\n                self.state = 799\n                self.u_r_instruction()\n                pass\n\n            elif la_ == 64:\n                self.enterOuterAlt(localctx, 64)\n                self.state = 800\n                self.u_rci_instruction()\n                pass\n\n            elif la_ == 65:\n                self.enterOuterAlt(localctx, 65)\n                self.state = 801\n                self.ci_instruction()\n                pass\n\n            elif la_ == 66:\n                self.enterOuterAlt(localctx, 66)\n                self.state = 802\n                self.i_instruction()\n                pass\n\n            elif la_ == 67:\n                self.enterOuterAlt(localctx, 67)\n                self.state = 803\n                self.ddci_instruction()\n                pass\n\n            elif la_ == 68:\n                self.enterOuterAlt(localctx, 68)\n                self.state = 804\n                self.erri_instruction()\n                pass\n\n            elif la_ == 69:\n                self.enterOuterAlt(localctx, 69)\n                self.state = 805\n                self.edri_instruction()\n                pass\n\n            elif la_ == 70:\n                self.enterOuterAlt(localctx, 70)\n                self.state = 806\n                self.s_erri_instruction()\n                pass\n\n            elif la_ == 71:\n                self.enterOuterAlt(localctx, 71)\n                self.state = 807\n                self.u_erri_instruction()\n                pass\n\n            elif la_ == 72:\n                self.enterOuterAlt(localctx, 72)\n                self.state = 808\n                self.erii_instruction()\n                pass\n\n            elif la_ == 73:\n                self.enterOuterAlt(localctx, 73)\n                self.state = 809\n                self.erir_instruction()\n                pass\n\n            elif la_ == 74:\n                self.enterOuterAlt(localctx, 74)\n                self.state = 810\n                self.erid_instruction()\n                pass\n\n            elif la_ == 75:\n                self.enterOuterAlt(localctx, 75)\n                self.state = 811\n                self.dma_rri_instruction()\n                pass\n\n            elif la_ == 76:\n                self.enterOuterAlt(localctx, 76)\n                self.state = 812\n                self.synthetic_sugar_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rici_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rici_op_codeContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Program_counterContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Program_counterContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRici_instruction\" ):\n                listener.enterRici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRici_instruction\" ):\n                listener.exitRici_instruction(self)\n\n\n\n\n    def rici_instruction(self):\n\n        localctx = assemblyParser.Rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 108, self.RULE_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 815\n            self.rici_op_code()\n            self.state = 816\n            self.match(assemblyParser.T__3)\n            self.state = 817\n            self.src_register()\n            self.state = 818\n            self.match(assemblyParser.T__3)\n            self.state = 819\n            self.program_counter()\n            self.state = 820\n            self.match(assemblyParser.T__3)\n            self.state = 821\n            self.condition()\n            self.state = 822\n            self.match(assemblyParser.T__3)\n            self.state = 823\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRri_instruction\" ):\n                listener.enterRri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRri_instruction\" ):\n                listener.exitRri_instruction(self)\n\n\n\n\n    def rri_instruction(self):\n\n        localctx = assemblyParser.Rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 110, self.RULE_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 825\n            self.rri_op_code()\n            self.state = 826\n            self.match(assemblyParser.T__3)\n            self.state = 827\n            self.match(assemblyParser.GPRegister)\n            self.state = 828\n            self.match(assemblyParser.T__3)\n            self.state = 829\n            self.src_register()\n            self.state = 830\n            self.match(assemblyParser.T__3)\n            self.state = 831\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rric_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rric_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRric_instruction\" ):\n                listener.enterRric_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRric_instruction\" ):\n                listener.exitRric_instruction(self)\n\n\n\n\n    def rric_instruction(self):\n\n        localctx = assemblyParser.Rric_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 112, self.RULE_rric_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 833\n            self.rri_op_code()\n            self.state = 834\n            self.match(assemblyParser.T__3)\n            self.state = 835\n            self.match(assemblyParser.GPRegister)\n            self.state = 836\n            self.match(assemblyParser.T__3)\n            self.state = 837\n            self.src_register()\n            self.state = 838\n            self.match(assemblyParser.T__3)\n            self.state = 839\n            self.number()\n            self.state = 840\n            self.match(assemblyParser.T__3)\n            self.state = 841\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrici_instruction\" ):\n                listener.enterRrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrici_instruction\" ):\n                listener.exitRrici_instruction(self)\n\n\n\n\n    def rrici_instruction(self):\n\n        localctx = assemblyParser.Rrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 114, self.RULE_rrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 843\n            self.rri_op_code()\n            self.state = 844\n            self.match(assemblyParser.T__3)\n            self.state = 845\n            self.match(assemblyParser.GPRegister)\n            self.state = 846\n            self.match(assemblyParser.T__3)\n            self.state = 847\n            self.src_register()\n            self.state = 848\n            self.match(assemblyParser.T__3)\n            self.state = 849\n            self.number()\n            self.state = 850\n            self.match(assemblyParser.T__3)\n            self.state = 851\n            self.condition()\n            self.state = 852\n            self.match(assemblyParser.T__3)\n            self.state = 853\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrr_instruction\" ):\n                listener.enterRrr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrr_instruction\" ):\n                listener.exitRrr_instruction(self)\n\n\n\n\n    def rrr_instruction(self):\n\n        localctx = assemblyParser.Rrr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 116, self.RULE_rrr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 855\n            self.rri_op_code()\n            self.state = 856\n            self.match(assemblyParser.T__3)\n            self.state = 857\n            self.match(assemblyParser.GPRegister)\n            self.state = 858\n            self.match(assemblyParser.T__3)\n            self.state = 859\n            self.src_register()\n            self.state = 860\n            self.match(assemblyParser.T__3)\n            self.state = 861\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrrc_instruction\" ):\n                listener.enterRrrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrrc_instruction\" ):\n                listener.exitRrrc_instruction(self)\n\n\n\n\n    def rrrc_instruction(self):\n\n        localctx = assemblyParser.Rrrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 118, self.RULE_rrrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 863\n            self.rri_op_code()\n            self.state = 864\n            self.match(assemblyParser.T__3)\n            self.state = 865\n            self.match(assemblyParser.GPRegister)\n            self.state = 866\n            self.match(assemblyParser.T__3)\n            self.state = 867\n            self.src_register()\n            self.state = 868\n            self.match(assemblyParser.T__3)\n            self.state = 869\n            self.src_register()\n            self.state = 870\n            self.match(assemblyParser.T__3)\n            self.state = 871\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrrci_instruction\" ):\n                listener.enterRrrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrrci_instruction\" ):\n                listener.exitRrrci_instruction(self)\n\n\n\n\n    def rrrci_instruction(self):\n\n        localctx = assemblyParser.Rrrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 120, self.RULE_rrrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 873\n            self.rri_op_code()\n            self.state = 874\n            self.match(assemblyParser.T__3)\n            self.state = 875\n            self.match(assemblyParser.GPRegister)\n            self.state = 876\n            self.match(assemblyParser.T__3)\n            self.state = 877\n            self.src_register()\n            self.state = 878\n            self.match(assemblyParser.T__3)\n            self.state = 879\n            self.src_register()\n            self.state = 880\n            self.match(assemblyParser.T__3)\n            self.state = 881\n            self.condition()\n            self.state = 882\n            self.match(assemblyParser.T__3)\n            self.state = 883\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZri_instruction\" ):\n                listener.enterZri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZri_instruction\" ):\n                listener.exitZri_instruction(self)\n\n\n\n\n    def zri_instruction(self):\n\n        localctx = assemblyParser.Zri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 122, self.RULE_zri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 885\n            self.rri_op_code()\n            self.state = 886\n            self.match(assemblyParser.T__3)\n            self.state = 887\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 888\n            self.match(assemblyParser.T__3)\n            self.state = 889\n            self.src_register()\n            self.state = 890\n            self.match(assemblyParser.T__3)\n            self.state = 891\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zric_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zric_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZric_instruction\" ):\n                listener.enterZric_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZric_instruction\" ):\n                listener.exitZric_instruction(self)\n\n\n\n\n    def zric_instruction(self):\n\n        localctx = assemblyParser.Zric_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 124, self.RULE_zric_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 893\n            self.rri_op_code()\n            self.state = 894\n            self.match(assemblyParser.T__3)\n            self.state = 895\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 896\n            self.match(assemblyParser.T__3)\n            self.state = 897\n            self.src_register()\n            self.state = 898\n            self.match(assemblyParser.T__3)\n            self.state = 899\n            self.number()\n            self.state = 900\n            self.match(assemblyParser.T__3)\n            self.state = 901\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrici_instruction\" ):\n                listener.enterZrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrici_instruction\" ):\n                listener.exitZrici_instruction(self)\n\n\n\n\n    def zrici_instruction(self):\n\n        localctx = assemblyParser.Zrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 126, self.RULE_zrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 903\n            self.rri_op_code()\n            self.state = 904\n            self.match(assemblyParser.T__3)\n            self.state = 905\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 906\n            self.match(assemblyParser.T__3)\n            self.state = 907\n            self.src_register()\n            self.state = 908\n            self.match(assemblyParser.T__3)\n            self.state = 909\n            self.number()\n            self.state = 910\n            self.match(assemblyParser.T__3)\n            self.state = 911\n            self.condition()\n            self.state = 912\n            self.match(assemblyParser.T__3)\n            self.state = 913\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrr_instruction\" ):\n                listener.enterZrr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrr_instruction\" ):\n                listener.exitZrr_instruction(self)\n\n\n\n\n    def zrr_instruction(self):\n\n        localctx = assemblyParser.Zrr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 128, self.RULE_zrr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 915\n            self.rri_op_code()\n            self.state = 916\n            self.match(assemblyParser.T__3)\n            self.state = 917\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 918\n            self.match(assemblyParser.T__3)\n            self.state = 919\n            self.src_register()\n            self.state = 920\n            self.match(assemblyParser.T__3)\n            self.state = 921\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrrc_instruction\" ):\n                listener.enterZrrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrrc_instruction\" ):\n                listener.exitZrrc_instruction(self)\n\n\n\n\n    def zrrc_instruction(self):\n\n        localctx = assemblyParser.Zrrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 130, self.RULE_zrrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 923\n            self.rri_op_code()\n            self.state = 924\n            self.match(assemblyParser.T__3)\n            self.state = 925\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 926\n            self.match(assemblyParser.T__3)\n            self.state = 927\n            self.src_register()\n            self.state = 928\n            self.match(assemblyParser.T__3)\n            self.state = 929\n            self.src_register()\n            self.state = 930\n            self.match(assemblyParser.T__3)\n            self.state = 931\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrrci_instruction\" ):\n                listener.enterZrrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrrci_instruction\" ):\n                listener.exitZrrci_instruction(self)\n\n\n\n\n    def zrrci_instruction(self):\n\n        localctx = assemblyParser.Zrrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 132, self.RULE_zrrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 933\n            self.rri_op_code()\n            self.state = 934\n            self.match(assemblyParser.T__3)\n            self.state = 935\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 936\n            self.match(assemblyParser.T__3)\n            self.state = 937\n            self.src_register()\n            self.state = 938\n            self.match(assemblyParser.T__3)\n            self.state = 939\n            self.src_register()\n            self.state = 940\n            self.match(assemblyParser.T__3)\n            self.state = 941\n            self.condition()\n            self.state = 942\n            self.match(assemblyParser.T__3)\n            self.state = 943\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rri_instruction\" ):\n                listener.enterS_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rri_instruction\" ):\n                listener.exitS_rri_instruction(self)\n\n\n\n\n    def s_rri_instruction(self):\n\n        localctx = assemblyParser.S_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 134, self.RULE_s_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 945\n            self.rri_op_code()\n            self.state = 946\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 947\n            self.match(assemblyParser.T__3)\n            self.state = 948\n            self.match(assemblyParser.PairRegister)\n            self.state = 949\n            self.match(assemblyParser.T__3)\n            self.state = 950\n            self.src_register()\n            self.state = 951\n            self.match(assemblyParser.T__3)\n            self.state = 952\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rric_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rric_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rric_instruction\" ):\n                listener.enterS_rric_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rric_instruction\" ):\n                listener.exitS_rric_instruction(self)\n\n\n\n\n    def s_rric_instruction(self):\n\n        localctx = assemblyParser.S_rric_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 136, self.RULE_s_rric_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 954\n            self.rri_op_code()\n            self.state = 955\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 956\n            self.match(assemblyParser.T__3)\n            self.state = 957\n            self.match(assemblyParser.PairRegister)\n            self.state = 958\n            self.match(assemblyParser.T__3)\n            self.state = 959\n            self.src_register()\n            self.state = 960\n            self.match(assemblyParser.T__3)\n            self.state = 961\n            self.number()\n            self.state = 962\n            self.match(assemblyParser.T__3)\n            self.state = 963\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrici_instruction\" ):\n                listener.enterS_rrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrici_instruction\" ):\n                listener.exitS_rrici_instruction(self)\n\n\n\n\n    def s_rrici_instruction(self):\n\n        localctx = assemblyParser.S_rrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 138, self.RULE_s_rrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 965\n            self.rri_op_code()\n            self.state = 966\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 967\n            self.match(assemblyParser.T__3)\n            self.state = 968\n            self.match(assemblyParser.PairRegister)\n            self.state = 969\n            self.match(assemblyParser.T__3)\n            self.state = 970\n            self.src_register()\n            self.state = 971\n            self.match(assemblyParser.T__3)\n            self.state = 972\n            self.number()\n            self.state = 973\n            self.match(assemblyParser.T__3)\n            self.state = 974\n            self.condition()\n            self.state = 975\n            self.match(assemblyParser.T__3)\n            self.state = 976\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrr_instruction\" ):\n                listener.enterS_rrr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrr_instruction\" ):\n                listener.exitS_rrr_instruction(self)\n\n\n\n\n    def s_rrr_instruction(self):\n\n        localctx = assemblyParser.S_rrr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 140, self.RULE_s_rrr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 978\n            self.rri_op_code()\n            self.state = 979\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 980\n            self.match(assemblyParser.T__3)\n            self.state = 981\n            self.match(assemblyParser.PairRegister)\n            self.state = 982\n            self.match(assemblyParser.T__3)\n            self.state = 983\n            self.src_register()\n            self.state = 984\n            self.match(assemblyParser.T__3)\n            self.state = 985\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrrc_instruction\" ):\n                listener.enterS_rrrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrrc_instruction\" ):\n                listener.exitS_rrrc_instruction(self)\n\n\n\n\n    def s_rrrc_instruction(self):\n\n        localctx = assemblyParser.S_rrrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 142, self.RULE_s_rrrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 987\n            self.rri_op_code()\n            self.state = 988\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 989\n            self.match(assemblyParser.T__3)\n            self.state = 990\n            self.match(assemblyParser.PairRegister)\n            self.state = 991\n            self.match(assemblyParser.T__3)\n            self.state = 992\n            self.src_register()\n            self.state = 993\n            self.match(assemblyParser.T__3)\n            self.state = 994\n            self.src_register()\n            self.state = 995\n            self.match(assemblyParser.T__3)\n            self.state = 996\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrrci_instruction\" ):\n                listener.enterS_rrrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrrci_instruction\" ):\n                listener.exitS_rrrci_instruction(self)\n\n\n\n\n    def s_rrrci_instruction(self):\n\n        localctx = assemblyParser.S_rrrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 144, self.RULE_s_rrrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 998\n            self.rri_op_code()\n            self.state = 999\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1000\n            self.match(assemblyParser.T__3)\n            self.state = 1001\n            self.match(assemblyParser.PairRegister)\n            self.state = 1002\n            self.match(assemblyParser.T__3)\n            self.state = 1003\n            self.src_register()\n            self.state = 1004\n            self.match(assemblyParser.T__3)\n            self.state = 1005\n            self.src_register()\n            self.state = 1006\n            self.match(assemblyParser.T__3)\n            self.state = 1007\n            self.condition()\n            self.state = 1008\n            self.match(assemblyParser.T__3)\n            self.state = 1009\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rri_instruction\" ):\n                listener.enterU_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rri_instruction\" ):\n                listener.exitU_rri_instruction(self)\n\n\n\n\n    def u_rri_instruction(self):\n\n        localctx = assemblyParser.U_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 146, self.RULE_u_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1011\n            self.rri_op_code()\n            self.state = 1012\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1013\n            self.match(assemblyParser.T__3)\n            self.state = 1014\n            self.match(assemblyParser.PairRegister)\n            self.state = 1015\n            self.match(assemblyParser.T__3)\n            self.state = 1016\n            self.src_register()\n            self.state = 1017\n            self.match(assemblyParser.T__3)\n            self.state = 1018\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rric_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rric_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rric_instruction\" ):\n                listener.enterU_rric_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rric_instruction\" ):\n                listener.exitU_rric_instruction(self)\n\n\n\n\n    def u_rric_instruction(self):\n\n        localctx = assemblyParser.U_rric_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 148, self.RULE_u_rric_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1020\n            self.rri_op_code()\n            self.state = 1021\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1022\n            self.match(assemblyParser.T__3)\n            self.state = 1023\n            self.match(assemblyParser.PairRegister)\n            self.state = 1024\n            self.match(assemblyParser.T__3)\n            self.state = 1025\n            self.src_register()\n            self.state = 1026\n            self.match(assemblyParser.T__3)\n            self.state = 1027\n            self.number()\n            self.state = 1028\n            self.match(assemblyParser.T__3)\n            self.state = 1029\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrici_instruction\" ):\n                listener.enterU_rrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrici_instruction\" ):\n                listener.exitU_rrici_instruction(self)\n\n\n\n\n    def u_rrici_instruction(self):\n\n        localctx = assemblyParser.U_rrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 150, self.RULE_u_rrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1031\n            self.rri_op_code()\n            self.state = 1032\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1033\n            self.match(assemblyParser.T__3)\n            self.state = 1034\n            self.match(assemblyParser.PairRegister)\n            self.state = 1035\n            self.match(assemblyParser.T__3)\n            self.state = 1036\n            self.src_register()\n            self.state = 1037\n            self.match(assemblyParser.T__3)\n            self.state = 1038\n            self.number()\n            self.state = 1039\n            self.match(assemblyParser.T__3)\n            self.state = 1040\n            self.condition()\n            self.state = 1041\n            self.match(assemblyParser.T__3)\n            self.state = 1042\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrr_instruction\" ):\n                listener.enterU_rrr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrr_instruction\" ):\n                listener.exitU_rrr_instruction(self)\n\n\n\n\n    def u_rrr_instruction(self):\n\n        localctx = assemblyParser.U_rrr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 152, self.RULE_u_rrr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1044\n            self.rri_op_code()\n            self.state = 1045\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1046\n            self.match(assemblyParser.T__3)\n            self.state = 1047\n            self.match(assemblyParser.PairRegister)\n            self.state = 1048\n            self.match(assemblyParser.T__3)\n            self.state = 1049\n            self.src_register()\n            self.state = 1050\n            self.match(assemblyParser.T__3)\n            self.state = 1051\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrrc_instruction\" ):\n                listener.enterU_rrrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrrc_instruction\" ):\n                listener.exitU_rrrc_instruction(self)\n\n\n\n\n    def u_rrrc_instruction(self):\n\n        localctx = assemblyParser.U_rrrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 154, self.RULE_u_rrrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1053\n            self.rri_op_code()\n            self.state = 1054\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1055\n            self.match(assemblyParser.T__3)\n            self.state = 1056\n            self.match(assemblyParser.PairRegister)\n            self.state = 1057\n            self.match(assemblyParser.T__3)\n            self.state = 1058\n            self.src_register()\n            self.state = 1059\n            self.match(assemblyParser.T__3)\n            self.state = 1060\n            self.src_register()\n            self.state = 1061\n            self.match(assemblyParser.T__3)\n            self.state = 1062\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrrci_instruction\" ):\n                listener.enterU_rrrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrrci_instruction\" ):\n                listener.exitU_rrrci_instruction(self)\n\n\n\n\n    def u_rrrci_instruction(self):\n\n        localctx = assemblyParser.U_rrrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 156, self.RULE_u_rrrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1064\n            self.rri_op_code()\n            self.state = 1065\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1066\n            self.match(assemblyParser.T__3)\n            self.state = 1067\n            self.match(assemblyParser.PairRegister)\n            self.state = 1068\n            self.match(assemblyParser.T__3)\n            self.state = 1069\n            self.src_register()\n            self.state = 1070\n            self.match(assemblyParser.T__3)\n            self.state = 1071\n            self.src_register()\n            self.state = 1072\n            self.match(assemblyParser.T__3)\n            self.state = 1073\n            self.condition()\n            self.state = 1074\n            self.match(assemblyParser.T__3)\n            self.state = 1075\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRr_instruction\" ):\n                listener.enterRr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRr_instruction\" ):\n                listener.exitRr_instruction(self)\n\n\n\n\n    def rr_instruction(self):\n\n        localctx = assemblyParser.Rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 158, self.RULE_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1077\n            self.rr_op_code()\n            self.state = 1078\n            self.match(assemblyParser.T__3)\n            self.state = 1079\n            self.match(assemblyParser.GPRegister)\n            self.state = 1080\n            self.match(assemblyParser.T__3)\n            self.state = 1081\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrc_instruction\" ):\n                listener.enterRrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrc_instruction\" ):\n                listener.exitRrc_instruction(self)\n\n\n\n\n    def rrc_instruction(self):\n\n        localctx = assemblyParser.Rrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 160, self.RULE_rrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1083\n            self.rr_op_code()\n            self.state = 1084\n            self.match(assemblyParser.T__3)\n            self.state = 1085\n            self.match(assemblyParser.GPRegister)\n            self.state = 1086\n            self.match(assemblyParser.T__3)\n            self.state = 1087\n            self.src_register()\n            self.state = 1088\n            self.match(assemblyParser.T__3)\n            self.state = 1089\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrci_instruction\" ):\n                listener.enterRrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrci_instruction\" ):\n                listener.exitRrci_instruction(self)\n\n\n\n\n    def rrci_instruction(self):\n\n        localctx = assemblyParser.Rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 162, self.RULE_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1091\n            self.rr_op_code()\n            self.state = 1092\n            self.match(assemblyParser.T__3)\n            self.state = 1093\n            self.match(assemblyParser.GPRegister)\n            self.state = 1094\n            self.match(assemblyParser.T__3)\n            self.state = 1095\n            self.src_register()\n            self.state = 1096\n            self.match(assemblyParser.T__3)\n            self.state = 1097\n            self.condition()\n            self.state = 1098\n            self.match(assemblyParser.T__3)\n            self.state = 1099\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZr_instruction\" ):\n                listener.enterZr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZr_instruction\" ):\n                listener.exitZr_instruction(self)\n\n\n\n\n    def zr_instruction(self):\n\n        localctx = assemblyParser.Zr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 164, self.RULE_zr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1101\n            self.rr_op_code()\n            self.state = 1102\n            self.match(assemblyParser.T__3)\n            self.state = 1103\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1104\n            self.match(assemblyParser.T__3)\n            self.state = 1105\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrc_instruction\" ):\n                listener.enterZrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrc_instruction\" ):\n                listener.exitZrc_instruction(self)\n\n\n\n\n    def zrc_instruction(self):\n\n        localctx = assemblyParser.Zrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 166, self.RULE_zrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1107\n            self.rr_op_code()\n            self.state = 1108\n            self.match(assemblyParser.T__3)\n            self.state = 1109\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1110\n            self.match(assemblyParser.T__3)\n            self.state = 1111\n            self.src_register()\n            self.state = 1112\n            self.match(assemblyParser.T__3)\n            self.state = 1113\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrci_instruction\" ):\n                listener.enterZrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrci_instruction\" ):\n                listener.exitZrci_instruction(self)\n\n\n\n\n    def zrci_instruction(self):\n\n        localctx = assemblyParser.Zrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 168, self.RULE_zrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1115\n            self.rr_op_code()\n            self.state = 1116\n            self.match(assemblyParser.T__3)\n            self.state = 1117\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1118\n            self.match(assemblyParser.T__3)\n            self.state = 1119\n            self.src_register()\n            self.state = 1120\n            self.match(assemblyParser.T__3)\n            self.state = 1121\n            self.condition()\n            self.state = 1122\n            self.match(assemblyParser.T__3)\n            self.state = 1123\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rr_instruction\" ):\n                listener.enterS_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rr_instruction\" ):\n                listener.exitS_rr_instruction(self)\n\n\n\n\n    def s_rr_instruction(self):\n\n        localctx = assemblyParser.S_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 170, self.RULE_s_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1125\n            self.rr_op_code()\n            self.state = 1126\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1127\n            self.match(assemblyParser.T__3)\n            self.state = 1128\n            self.match(assemblyParser.PairRegister)\n            self.state = 1129\n            self.match(assemblyParser.T__3)\n            self.state = 1130\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrc_instruction\" ):\n                listener.enterS_rrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrc_instruction\" ):\n                listener.exitS_rrc_instruction(self)\n\n\n\n\n    def s_rrc_instruction(self):\n\n        localctx = assemblyParser.S_rrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 172, self.RULE_s_rrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1132\n            self.rr_op_code()\n            self.state = 1133\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1134\n            self.match(assemblyParser.T__3)\n            self.state = 1135\n            self.match(assemblyParser.PairRegister)\n            self.state = 1136\n            self.match(assemblyParser.T__3)\n            self.state = 1137\n            self.src_register()\n            self.state = 1138\n            self.match(assemblyParser.T__3)\n            self.state = 1139\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrci_instruction\" ):\n                listener.enterS_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrci_instruction\" ):\n                listener.exitS_rrci_instruction(self)\n\n\n\n\n    def s_rrci_instruction(self):\n\n        localctx = assemblyParser.S_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 174, self.RULE_s_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1141\n            self.rr_op_code()\n            self.state = 1142\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1143\n            self.match(assemblyParser.T__3)\n            self.state = 1144\n            self.match(assemblyParser.PairRegister)\n            self.state = 1145\n            self.match(assemblyParser.T__3)\n            self.state = 1146\n            self.src_register()\n            self.state = 1147\n            self.match(assemblyParser.T__3)\n            self.state = 1148\n            self.condition()\n            self.state = 1149\n            self.match(assemblyParser.T__3)\n            self.state = 1150\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rr_instruction\" ):\n                listener.enterU_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rr_instruction\" ):\n                listener.exitU_rr_instruction(self)\n\n\n\n\n    def u_rr_instruction(self):\n\n        localctx = assemblyParser.U_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 176, self.RULE_u_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1152\n            self.rr_op_code()\n            self.state = 1153\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1154\n            self.match(assemblyParser.T__3)\n            self.state = 1155\n            self.match(assemblyParser.PairRegister)\n            self.state = 1156\n            self.match(assemblyParser.T__3)\n            self.state = 1157\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrc_instruction\" ):\n                listener.enterU_rrc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrc_instruction\" ):\n                listener.exitU_rrc_instruction(self)\n\n\n\n\n    def u_rrc_instruction(self):\n\n        localctx = assemblyParser.U_rrc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 178, self.RULE_u_rrc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1159\n            self.rr_op_code()\n            self.state = 1160\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1161\n            self.match(assemblyParser.T__3)\n            self.state = 1162\n            self.match(assemblyParser.PairRegister)\n            self.state = 1163\n            self.match(assemblyParser.T__3)\n            self.state = 1164\n            self.src_register()\n            self.state = 1165\n            self.match(assemblyParser.T__3)\n            self.state = 1166\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rr_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rr_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrci_instruction\" ):\n                listener.enterU_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrci_instruction\" ):\n                listener.exitU_rrci_instruction(self)\n\n\n\n\n    def u_rrci_instruction(self):\n\n        localctx = assemblyParser.U_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 180, self.RULE_u_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1168\n            self.rr_op_code()\n            self.state = 1169\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1170\n            self.match(assemblyParser.T__3)\n            self.state = 1171\n            self.match(assemblyParser.PairRegister)\n            self.state = 1172\n            self.match(assemblyParser.T__3)\n            self.state = 1173\n            self.src_register()\n            self.state = 1174\n            self.match(assemblyParser.T__3)\n            self.state = 1175\n            self.condition()\n            self.state = 1176\n            self.match(assemblyParser.T__3)\n            self.state = 1177\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Drdici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def drdici_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Drdici_op_codeContext,0)\n\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_drdici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDrdici_instruction\" ):\n                listener.enterDrdici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDrdici_instruction\" ):\n                listener.exitDrdici_instruction(self)\n\n\n\n\n    def drdici_instruction(self):\n\n        localctx = assemblyParser.Drdici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 182, self.RULE_drdici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1179\n            self.drdici_op_code()\n            self.state = 1180\n            self.match(assemblyParser.T__3)\n            self.state = 1181\n            self.match(assemblyParser.PairRegister)\n            self.state = 1182\n            self.match(assemblyParser.T__3)\n            self.state = 1183\n            self.src_register()\n            self.state = 1184\n            self.match(assemblyParser.T__3)\n            self.state = 1185\n            self.match(assemblyParser.PairRegister)\n            self.state = 1186\n            self.match(assemblyParser.T__3)\n            self.state = 1187\n            self.number()\n            self.state = 1188\n            self.match(assemblyParser.T__3)\n            self.state = 1189\n            self.condition()\n            self.state = 1190\n            self.match(assemblyParser.T__3)\n            self.state = 1191\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrri_instruction\" ):\n                listener.enterRrri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrri_instruction\" ):\n                listener.exitRrri_instruction(self)\n\n\n\n\n    def rrri_instruction(self):\n\n        localctx = assemblyParser.Rrri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 184, self.RULE_rrri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1193\n            self.rrri_op_code()\n            self.state = 1194\n            self.match(assemblyParser.T__3)\n            self.state = 1195\n            self.match(assemblyParser.GPRegister)\n            self.state = 1196\n            self.match(assemblyParser.T__3)\n            self.state = 1197\n            self.src_register()\n            self.state = 1198\n            self.match(assemblyParser.T__3)\n            self.state = 1199\n            self.src_register()\n            self.state = 1200\n            self.match(assemblyParser.T__3)\n            self.state = 1201\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrrici_instruction\" ):\n                listener.enterRrrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrrici_instruction\" ):\n                listener.exitRrrici_instruction(self)\n\n\n\n\n    def rrrici_instruction(self):\n\n        localctx = assemblyParser.Rrrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 186, self.RULE_rrrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1203\n            self.rrri_op_code()\n            self.state = 1204\n            self.match(assemblyParser.T__3)\n            self.state = 1205\n            self.match(assemblyParser.GPRegister)\n            self.state = 1206\n            self.match(assemblyParser.T__3)\n            self.state = 1207\n            self.src_register()\n            self.state = 1208\n            self.match(assemblyParser.T__3)\n            self.state = 1209\n            self.src_register()\n            self.state = 1210\n            self.match(assemblyParser.T__3)\n            self.state = 1211\n            self.number()\n            self.state = 1212\n            self.match(assemblyParser.T__3)\n            self.state = 1213\n            self.condition()\n            self.state = 1214\n            self.match(assemblyParser.T__3)\n            self.state = 1215\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrri_instruction\" ):\n                listener.enterZrri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrri_instruction\" ):\n                listener.exitZrri_instruction(self)\n\n\n\n\n    def zrri_instruction(self):\n\n        localctx = assemblyParser.Zrri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 188, self.RULE_zrri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1217\n            self.rrri_op_code()\n            self.state = 1218\n            self.match(assemblyParser.T__3)\n            self.state = 1219\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1220\n            self.match(assemblyParser.T__3)\n            self.state = 1221\n            self.src_register()\n            self.state = 1222\n            self.match(assemblyParser.T__3)\n            self.state = 1223\n            self.src_register()\n            self.state = 1224\n            self.match(assemblyParser.T__3)\n            self.state = 1225\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zrrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zrrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZrrici_instruction\" ):\n                listener.enterZrrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZrrici_instruction\" ):\n                listener.exitZrrici_instruction(self)\n\n\n\n\n    def zrrici_instruction(self):\n\n        localctx = assemblyParser.Zrrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 190, self.RULE_zrrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1227\n            self.rrri_op_code()\n            self.state = 1228\n            self.match(assemblyParser.T__3)\n            self.state = 1229\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1230\n            self.match(assemblyParser.T__3)\n            self.state = 1231\n            self.src_register()\n            self.state = 1232\n            self.match(assemblyParser.T__3)\n            self.state = 1233\n            self.src_register()\n            self.state = 1234\n            self.match(assemblyParser.T__3)\n            self.state = 1235\n            self.number()\n            self.state = 1236\n            self.match(assemblyParser.T__3)\n            self.state = 1237\n            self.condition()\n            self.state = 1238\n            self.match(assemblyParser.T__3)\n            self.state = 1239\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrri_instruction\" ):\n                listener.enterS_rrri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrri_instruction\" ):\n                listener.exitS_rrri_instruction(self)\n\n\n\n\n    def s_rrri_instruction(self):\n\n        localctx = assemblyParser.S_rrri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 192, self.RULE_s_rrri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1241\n            self.rrri_op_code()\n            self.state = 1242\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1243\n            self.match(assemblyParser.T__3)\n            self.state = 1244\n            self.match(assemblyParser.PairRegister)\n            self.state = 1245\n            self.match(assemblyParser.T__3)\n            self.state = 1246\n            self.src_register()\n            self.state = 1247\n            self.match(assemblyParser.T__3)\n            self.state = 1248\n            self.src_register()\n            self.state = 1249\n            self.match(assemblyParser.T__3)\n            self.state = 1250\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rrrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rrrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rrrici_instruction\" ):\n                listener.enterS_rrrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rrrici_instruction\" ):\n                listener.exitS_rrrici_instruction(self)\n\n\n\n\n    def s_rrrici_instruction(self):\n\n        localctx = assemblyParser.S_rrrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 194, self.RULE_s_rrrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1252\n            self.rrri_op_code()\n            self.state = 1253\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1254\n            self.match(assemblyParser.T__3)\n            self.state = 1255\n            self.match(assemblyParser.PairRegister)\n            self.state = 1256\n            self.match(assemblyParser.T__3)\n            self.state = 1257\n            self.src_register()\n            self.state = 1258\n            self.match(assemblyParser.T__3)\n            self.state = 1259\n            self.src_register()\n            self.state = 1260\n            self.match(assemblyParser.T__3)\n            self.state = 1261\n            self.number()\n            self.state = 1262\n            self.match(assemblyParser.T__3)\n            self.state = 1263\n            self.condition()\n            self.state = 1264\n            self.match(assemblyParser.T__3)\n            self.state = 1265\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrri_instruction\" ):\n                listener.enterU_rrri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrri_instruction\" ):\n                listener.exitU_rrri_instruction(self)\n\n\n\n\n    def u_rrri_instruction(self):\n\n        localctx = assemblyParser.U_rrri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 196, self.RULE_u_rrri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1267\n            self.rrri_op_code()\n            self.state = 1268\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1269\n            self.match(assemblyParser.T__3)\n            self.state = 1270\n            self.match(assemblyParser.PairRegister)\n            self.state = 1271\n            self.match(assemblyParser.T__3)\n            self.state = 1272\n            self.src_register()\n            self.state = 1273\n            self.match(assemblyParser.T__3)\n            self.state = 1274\n            self.src_register()\n            self.state = 1275\n            self.match(assemblyParser.T__3)\n            self.state = 1276\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rrrici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rrri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rrrici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rrrici_instruction\" ):\n                listener.enterU_rrrici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rrrici_instruction\" ):\n                listener.exitU_rrrici_instruction(self)\n\n\n\n\n    def u_rrrici_instruction(self):\n\n        localctx = assemblyParser.U_rrrici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 198, self.RULE_u_rrrici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1278\n            self.rrri_op_code()\n            self.state = 1279\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1280\n            self.match(assemblyParser.T__3)\n            self.state = 1281\n            self.match(assemblyParser.PairRegister)\n            self.state = 1282\n            self.match(assemblyParser.T__3)\n            self.state = 1283\n            self.src_register()\n            self.state = 1284\n            self.match(assemblyParser.T__3)\n            self.state = 1285\n            self.src_register()\n            self.state = 1286\n            self.match(assemblyParser.T__3)\n            self.state = 1287\n            self.number()\n            self.state = 1288\n            self.match(assemblyParser.T__3)\n            self.state = 1289\n            self.condition()\n            self.state = 1290\n            self.match(assemblyParser.T__3)\n            self.state = 1291\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRir_instruction\" ):\n                listener.enterRir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRir_instruction\" ):\n                listener.exitRir_instruction(self)\n\n\n\n\n    def rir_instruction(self):\n\n        localctx = assemblyParser.Rir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 200, self.RULE_rir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1293\n            self.rri_op_code()\n            self.state = 1294\n            self.match(assemblyParser.T__3)\n            self.state = 1295\n            self.match(assemblyParser.GPRegister)\n            self.state = 1296\n            self.match(assemblyParser.T__3)\n            self.state = 1297\n            self.number()\n            self.state = 1298\n            self.match(assemblyParser.T__3)\n            self.state = 1299\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rirc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rirc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRirc_instruction\" ):\n                listener.enterRirc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRirc_instruction\" ):\n                listener.exitRirc_instruction(self)\n\n\n\n\n    def rirc_instruction(self):\n\n        localctx = assemblyParser.Rirc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 202, self.RULE_rirc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1301\n            self.rri_op_code()\n            self.state = 1302\n            self.match(assemblyParser.T__3)\n            self.state = 1303\n            self.match(assemblyParser.GPRegister)\n            self.state = 1304\n            self.match(assemblyParser.T__3)\n            self.state = 1305\n            self.number()\n            self.state = 1306\n            self.match(assemblyParser.T__3)\n            self.state = 1307\n            self.src_register()\n            self.state = 1308\n            self.match(assemblyParser.T__3)\n            self.state = 1309\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rirci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rirci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRirci_instruction\" ):\n                listener.enterRirci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRirci_instruction\" ):\n                listener.exitRirci_instruction(self)\n\n\n\n\n    def rirci_instruction(self):\n\n        localctx = assemblyParser.Rirci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 204, self.RULE_rirci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1311\n            self.rri_op_code()\n            self.state = 1312\n            self.match(assemblyParser.T__3)\n            self.state = 1313\n            self.match(assemblyParser.GPRegister)\n            self.state = 1314\n            self.match(assemblyParser.T__3)\n            self.state = 1315\n            self.number()\n            self.state = 1316\n            self.match(assemblyParser.T__3)\n            self.state = 1317\n            self.src_register()\n            self.state = 1318\n            self.match(assemblyParser.T__3)\n            self.state = 1319\n            self.condition()\n            self.state = 1320\n            self.match(assemblyParser.T__3)\n            self.state = 1321\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZir_instruction\" ):\n                listener.enterZir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZir_instruction\" ):\n                listener.exitZir_instruction(self)\n\n\n\n\n    def zir_instruction(self):\n\n        localctx = assemblyParser.Zir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 206, self.RULE_zir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1323\n            self.rri_op_code()\n            self.state = 1324\n            self.match(assemblyParser.T__3)\n            self.state = 1325\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1326\n            self.match(assemblyParser.T__3)\n            self.state = 1327\n            self.number()\n            self.state = 1328\n            self.match(assemblyParser.T__3)\n            self.state = 1329\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zirc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zirc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZirc_instruction\" ):\n                listener.enterZirc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZirc_instruction\" ):\n                listener.exitZirc_instruction(self)\n\n\n\n\n    def zirc_instruction(self):\n\n        localctx = assemblyParser.Zirc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 208, self.RULE_zirc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1331\n            self.rri_op_code()\n            self.state = 1332\n            self.match(assemblyParser.T__3)\n            self.state = 1333\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1334\n            self.match(assemblyParser.T__3)\n            self.state = 1335\n            self.number()\n            self.state = 1336\n            self.match(assemblyParser.T__3)\n            self.state = 1337\n            self.src_register()\n            self.state = 1338\n            self.match(assemblyParser.T__3)\n            self.state = 1339\n            self.condition()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zirci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zirci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZirci_instruction\" ):\n                listener.enterZirci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZirci_instruction\" ):\n                listener.exitZirci_instruction(self)\n\n\n\n\n    def zirci_instruction(self):\n\n        localctx = assemblyParser.Zirci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 210, self.RULE_zirci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1341\n            self.rri_op_code()\n            self.state = 1342\n            self.match(assemblyParser.T__3)\n            self.state = 1343\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1344\n            self.match(assemblyParser.T__3)\n            self.state = 1345\n            self.number()\n            self.state = 1346\n            self.match(assemblyParser.T__3)\n            self.state = 1347\n            self.src_register()\n            self.state = 1348\n            self.match(assemblyParser.T__3)\n            self.state = 1349\n            self.condition()\n            self.state = 1350\n            self.match(assemblyParser.T__3)\n            self.state = 1351\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rirc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rirc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rirc_instruction\" ):\n                listener.enterS_rirc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rirc_instruction\" ):\n                listener.exitS_rirc_instruction(self)\n\n\n\n\n    def s_rirc_instruction(self):\n\n        localctx = assemblyParser.S_rirc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 212, self.RULE_s_rirc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1353\n            self.rri_op_code()\n            self.state = 1354\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1355\n            self.match(assemblyParser.T__3)\n            self.state = 1356\n            self.match(assemblyParser.PairRegister)\n            self.state = 1357\n            self.match(assemblyParser.T__3)\n            self.state = 1358\n            self.number()\n            self.state = 1359\n            self.match(assemblyParser.T__3)\n            self.state = 1360\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rirci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rirci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rirci_instruction\" ):\n                listener.enterS_rirci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rirci_instruction\" ):\n                listener.exitS_rirci_instruction(self)\n\n\n\n\n    def s_rirci_instruction(self):\n\n        localctx = assemblyParser.S_rirci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 214, self.RULE_s_rirci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1362\n            self.rri_op_code()\n            self.state = 1363\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1364\n            self.match(assemblyParser.T__3)\n            self.state = 1365\n            self.match(assemblyParser.PairRegister)\n            self.state = 1366\n            self.match(assemblyParser.T__3)\n            self.state = 1367\n            self.number()\n            self.state = 1368\n            self.match(assemblyParser.T__3)\n            self.state = 1369\n            self.src_register()\n            self.state = 1370\n            self.match(assemblyParser.T__3)\n            self.state = 1371\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rirc_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rirc_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rirc_instruction\" ):\n                listener.enterU_rirc_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rirc_instruction\" ):\n                listener.exitU_rirc_instruction(self)\n\n\n\n\n    def u_rirc_instruction(self):\n\n        localctx = assemblyParser.U_rirc_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 216, self.RULE_u_rirc_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1373\n            self.rri_op_code()\n            self.state = 1374\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1375\n            self.match(assemblyParser.T__3)\n            self.state = 1376\n            self.match(assemblyParser.PairRegister)\n            self.state = 1377\n            self.match(assemblyParser.T__3)\n            self.state = 1378\n            self.number()\n            self.state = 1379\n            self.match(assemblyParser.T__3)\n            self.state = 1380\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rirci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rri_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Rri_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rirci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rirci_instruction\" ):\n                listener.enterU_rirci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rirci_instruction\" ):\n                listener.exitU_rirci_instruction(self)\n\n\n\n\n    def u_rirci_instruction(self):\n\n        localctx = assemblyParser.U_rirci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 218, self.RULE_u_rirci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1382\n            self.rri_op_code()\n            self.state = 1383\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1384\n            self.match(assemblyParser.T__3)\n            self.state = 1385\n            self.match(assemblyParser.PairRegister)\n            self.state = 1386\n            self.match(assemblyParser.T__3)\n            self.state = 1387\n            self.number()\n            self.state = 1388\n            self.match(assemblyParser.T__3)\n            self.state = 1389\n            self.src_register()\n            self.state = 1390\n            self.match(assemblyParser.T__3)\n            self.state = 1391\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class R_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_r_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterR_instruction\" ):\n                listener.enterR_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitR_instruction\" ):\n                listener.exitR_instruction(self)\n\n\n\n\n    def r_instruction(self):\n\n        localctx = assemblyParser.R_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 220, self.RULE_r_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1393\n            self.r_op_code()\n            self.state = 1394\n            self.match(assemblyParser.T__3)\n            self.state = 1395\n            self.match(assemblyParser.GPRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def condition(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.ConditionContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.ConditionContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRci_instruction\" ):\n                listener.enterRci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRci_instruction\" ):\n                listener.exitRci_instruction(self)\n\n\n\n\n    def rci_instruction(self):\n\n        localctx = assemblyParser.Rci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 222, self.RULE_rci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1397\n            self.r_op_code()\n            self.state = 1398\n            self.match(assemblyParser.T__3)\n            self.state = 1399\n            self.condition()\n            self.state = 1400\n            self.match(assemblyParser.T__3)\n            self.state = 1401\n            self.condition()\n            self.state = 1402\n            self.match(assemblyParser.T__3)\n            self.state = 1403\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Z_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_z_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZ_instruction\" ):\n                listener.enterZ_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZ_instruction\" ):\n                listener.exitZ_instruction(self)\n\n\n\n\n    def z_instruction(self):\n\n        localctx = assemblyParser.Z_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 224, self.RULE_z_instruction)\n        try:\n            self.state = 1412\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,12,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1405\n                self.r_op_code()\n                self.state = 1406\n                self.match(assemblyParser.T__3)\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1408\n                self.r_op_code()\n                self.state = 1409\n                self.match(assemblyParser.T__3)\n                self.state = 1410\n                self.match(assemblyParser.ZERO_REGISTER)\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Zci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def ZERO_REGISTER(self):\n            return self.getToken(assemblyParser.ZERO_REGISTER, 0)\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_zci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterZci_instruction\" ):\n                listener.enterZci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitZci_instruction\" ):\n                listener.exitZci_instruction(self)\n\n\n\n\n    def zci_instruction(self):\n\n        localctx = assemblyParser.Zci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 226, self.RULE_zci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1414\n            self.r_op_code()\n            self.state = 1415\n            self.match(assemblyParser.T__3)\n            self.state = 1416\n            self.match(assemblyParser.ZERO_REGISTER)\n            self.state = 1417\n            self.match(assemblyParser.T__3)\n            self.state = 1418\n            self.condition()\n            self.state = 1419\n            self.match(assemblyParser.T__3)\n            self.state = 1420\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_r_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_r_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_r_instruction\" ):\n                listener.enterS_r_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_r_instruction\" ):\n                listener.exitS_r_instruction(self)\n\n\n\n\n    def s_r_instruction(self):\n\n        localctx = assemblyParser.S_r_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 228, self.RULE_s_r_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1422\n            self.r_op_code()\n            self.state = 1423\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1424\n            self.match(assemblyParser.T__3)\n            self.state = 1425\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_rci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_rci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_rci_instruction\" ):\n                listener.enterS_rci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_rci_instruction\" ):\n                listener.exitS_rci_instruction(self)\n\n\n\n\n    def s_rci_instruction(self):\n\n        localctx = assemblyParser.S_rci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 230, self.RULE_s_rci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1427\n            self.r_op_code()\n            self.state = 1428\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1429\n            self.match(assemblyParser.T__3)\n            self.state = 1430\n            self.match(assemblyParser.PairRegister)\n            self.state = 1431\n            self.match(assemblyParser.T__3)\n            self.state = 1432\n            self.condition()\n            self.state = 1433\n            self.match(assemblyParser.T__3)\n            self.state = 1434\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_r_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_r_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_r_instruction\" ):\n                listener.enterU_r_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_r_instruction\" ):\n                listener.exitU_r_instruction(self)\n\n\n\n\n    def u_r_instruction(self):\n\n        localctx = assemblyParser.U_r_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 232, self.RULE_u_r_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1436\n            self.r_op_code()\n            self.state = 1437\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1438\n            self.match(assemblyParser.T__3)\n            self.state = 1439\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_rci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def r_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.R_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_rci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_rci_instruction\" ):\n                listener.enterU_rci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_rci_instruction\" ):\n                listener.exitU_rci_instruction(self)\n\n\n\n\n    def u_rci_instruction(self):\n\n        localctx = assemblyParser.U_rci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 234, self.RULE_u_rci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1441\n            self.r_op_code()\n            self.state = 1442\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1443\n            self.match(assemblyParser.T__3)\n            self.state = 1444\n            self.match(assemblyParser.PairRegister)\n            self.state = 1445\n            self.match(assemblyParser.T__3)\n            self.state = 1446\n            self.condition()\n            self.state = 1447\n            self.match(assemblyParser.T__3)\n            self.state = 1448\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ci_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Ci_op_codeContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCi_instruction\" ):\n                listener.enterCi_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCi_instruction\" ):\n                listener.exitCi_instruction(self)\n\n\n\n\n    def ci_instruction(self):\n\n        localctx = assemblyParser.Ci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 236, self.RULE_ci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1450\n            self.ci_op_code()\n            self.state = 1451\n            self.match(assemblyParser.T__3)\n            self.state = 1452\n            self.condition()\n            self.state = 1453\n            self.match(assemblyParser.T__3)\n            self.state = 1454\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class I_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def i_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.I_op_codeContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_i_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterI_instruction\" ):\n                listener.enterI_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitI_instruction\" ):\n                listener.exitI_instruction(self)\n\n\n\n\n    def i_instruction(self):\n\n        localctx = assemblyParser.I_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 238, self.RULE_i_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1456\n            self.i_op_code()\n            self.state = 1457\n            self.match(assemblyParser.T__3)\n            self.state = 1458\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ddci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ddci_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Ddci_op_codeContext,0)\n\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ddci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDdci_instruction\" ):\n                listener.enterDdci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDdci_instruction\" ):\n                listener.exitDdci_instruction(self)\n\n\n\n\n    def ddci_instruction(self):\n\n        localctx = assemblyParser.Ddci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 240, self.RULE_ddci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1460\n            self.ddci_op_code()\n            self.state = 1461\n            self.match(assemblyParser.T__3)\n            self.state = 1462\n            self.match(assemblyParser.PairRegister)\n            self.state = 1463\n            self.match(assemblyParser.T__3)\n            self.state = 1464\n            self.match(assemblyParser.PairRegister)\n            self.state = 1465\n            self.match(assemblyParser.T__3)\n            self.state = 1466\n            self.condition()\n            self.state = 1467\n            self.match(assemblyParser.T__3)\n            self.state = 1468\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def load_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Load_op_codeContext,0)\n\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterErri_instruction\" ):\n                listener.enterErri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitErri_instruction\" ):\n                listener.exitErri_instruction(self)\n\n\n\n\n    def erri_instruction(self):\n\n        localctx = assemblyParser.Erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 242, self.RULE_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1470\n            self.load_op_code()\n            self.state = 1471\n            self.match(assemblyParser.T__3)\n            self.state = 1472\n            self.endian()\n            self.state = 1473\n            self.match(assemblyParser.T__3)\n            self.state = 1474\n            self.match(assemblyParser.GPRegister)\n            self.state = 1475\n            self.match(assemblyParser.T__3)\n            self.state = 1476\n            self.src_register()\n            self.state = 1477\n            self.match(assemblyParser.T__3)\n            self.state = 1478\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Edri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def load_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Load_op_codeContext,0)\n\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_edri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterEdri_instruction\" ):\n                listener.enterEdri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitEdri_instruction\" ):\n                listener.exitEdri_instruction(self)\n\n\n\n\n    def edri_instruction(self):\n\n        localctx = assemblyParser.Edri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 244, self.RULE_edri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1480\n            self.load_op_code()\n            self.state = 1481\n            self.match(assemblyParser.T__3)\n            self.state = 1482\n            self.endian()\n            self.state = 1483\n            self.match(assemblyParser.T__3)\n            self.state = 1484\n            self.match(assemblyParser.PairRegister)\n            self.state = 1485\n            self.match(assemblyParser.T__3)\n            self.state = 1486\n            self.src_register()\n            self.state = 1487\n            self.match(assemblyParser.T__3)\n            self.state = 1488\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class S_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def load_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Load_op_codeContext,0)\n\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_s_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterS_erri_instruction\" ):\n                listener.enterS_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitS_erri_instruction\" ):\n                listener.exitS_erri_instruction(self)\n\n\n\n\n    def s_erri_instruction(self):\n\n        localctx = assemblyParser.S_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 246, self.RULE_s_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1490\n            self.load_op_code()\n            self.state = 1491\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1492\n            self.match(assemblyParser.T__3)\n            self.state = 1493\n            self.endian()\n            self.state = 1494\n            self.match(assemblyParser.T__3)\n            self.state = 1495\n            self.match(assemblyParser.PairRegister)\n            self.state = 1496\n            self.match(assemblyParser.T__3)\n            self.state = 1497\n            self.src_register()\n            self.state = 1498\n            self.match(assemblyParser.T__3)\n            self.state = 1499\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class U_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def load_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Load_op_codeContext,0)\n\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_u_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterU_erri_instruction\" ):\n                listener.enterU_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitU_erri_instruction\" ):\n                listener.exitU_erri_instruction(self)\n\n\n\n\n    def u_erri_instruction(self):\n\n        localctx = assemblyParser.U_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 248, self.RULE_u_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1501\n            self.load_op_code()\n            self.state = 1502\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1503\n            self.match(assemblyParser.T__3)\n            self.state = 1504\n            self.endian()\n            self.state = 1505\n            self.match(assemblyParser.T__3)\n            self.state = 1506\n            self.match(assemblyParser.PairRegister)\n            self.state = 1507\n            self.match(assemblyParser.T__3)\n            self.state = 1508\n            self.src_register()\n            self.state = 1509\n            self.match(assemblyParser.T__3)\n            self.state = 1510\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Erii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def store_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Store_op_codeContext,0)\n\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_erii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterErii_instruction\" ):\n                listener.enterErii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitErii_instruction\" ):\n                listener.exitErii_instruction(self)\n\n\n\n\n    def erii_instruction(self):\n\n        localctx = assemblyParser.Erii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 250, self.RULE_erii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1512\n            self.store_op_code()\n            self.state = 1513\n            self.match(assemblyParser.T__3)\n            self.state = 1514\n            self.endian()\n            self.state = 1515\n            self.match(assemblyParser.T__3)\n            self.state = 1516\n            self.src_register()\n            self.state = 1517\n            self.match(assemblyParser.T__3)\n            self.state = 1518\n            self.number()\n            self.state = 1519\n            self.match(assemblyParser.T__3)\n            self.state = 1520\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Erir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def store_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Store_op_codeContext,0)\n\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_erir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterErir_instruction\" ):\n                listener.enterErir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitErir_instruction\" ):\n                listener.exitErir_instruction(self)\n\n\n\n\n    def erir_instruction(self):\n\n        localctx = assemblyParser.Erir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 252, self.RULE_erir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1522\n            self.store_op_code()\n            self.state = 1523\n            self.match(assemblyParser.T__3)\n            self.state = 1524\n            self.endian()\n            self.state = 1525\n            self.match(assemblyParser.T__3)\n            self.state = 1526\n            self.src_register()\n            self.state = 1527\n            self.match(assemblyParser.T__3)\n            self.state = 1528\n            self.program_counter()\n            self.state = 1529\n            self.match(assemblyParser.T__3)\n            self.state = 1530\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Erid_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def store_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Store_op_codeContext,0)\n\n\n        def endian(self):\n            return self.getTypedRuleContext(assemblyParser.EndianContext,0)\n\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_erid_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterErid_instruction\" ):\n                listener.enterErid_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitErid_instruction\" ):\n                listener.exitErid_instruction(self)\n\n\n\n\n    def erid_instruction(self):\n\n        localctx = assemblyParser.Erid_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 254, self.RULE_erid_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1532\n            self.store_op_code()\n            self.state = 1533\n            self.match(assemblyParser.T__3)\n            self.state = 1534\n            self.endian()\n            self.state = 1535\n            self.match(assemblyParser.T__3)\n            self.state = 1536\n            self.src_register()\n            self.state = 1537\n            self.match(assemblyParser.T__3)\n            self.state = 1538\n            self.program_counter()\n            self.state = 1539\n            self.match(assemblyParser.T__3)\n            self.state = 1540\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Dma_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def dma_op_code(self):\n            return self.getTypedRuleContext(assemblyParser.Dma_op_codeContext,0)\n\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_dma_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDma_rri_instruction\" ):\n                listener.enterDma_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDma_rri_instruction\" ):\n                listener.exitDma_rri_instruction(self)\n\n\n\n\n    def dma_rri_instruction(self):\n\n        localctx = assemblyParser.Dma_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 256, self.RULE_dma_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1542\n            self.dma_op_code()\n            self.state = 1543\n            self.match(assemblyParser.T__3)\n            self.state = 1544\n            self.src_register()\n            self.state = 1545\n            self.match(assemblyParser.T__3)\n            self.state = 1546\n            self.src_register()\n            self.state = 1547\n            self.match(assemblyParser.T__3)\n            self.state = 1548\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Synthetic_sugar_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Rrif_instructionContext,0)\n\n\n        def move_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_instructionContext,0)\n\n\n        def neg_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Neg_instructionContext,0)\n\n\n        def not_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Not_instructionContext,0)\n\n\n        def jump_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jump_instructionContext,0)\n\n\n        def shortcut_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Shortcut_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_synthetic_sugar_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSynthetic_sugar_instruction\" ):\n                listener.enterSynthetic_sugar_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSynthetic_sugar_instruction\" ):\n                listener.exitSynthetic_sugar_instruction(self)\n\n\n\n\n    def synthetic_sugar_instruction(self):\n\n        localctx = assemblyParser.Synthetic_sugar_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 258, self.RULE_synthetic_sugar_instruction)\n        try:\n            self.state = 1556\n            self._errHandler.sync(self)\n            token = self._input.LA(1)\n            if token in [assemblyParser.ANDN, assemblyParser.NAND, assemblyParser.NOR, assemblyParser.NXOR, assemblyParser.ORN, assemblyParser.HASH]:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1550\n                self.rrif_instruction()\n                pass\n            elif token in [assemblyParser.MOVE]:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1551\n                self.move_instruction()\n                pass\n            elif token in [assemblyParser.NEG]:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1552\n                self.neg_instruction()\n                pass\n            elif token in [assemblyParser.NOT]:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 1553\n                self.not_instruction()\n                pass\n            elif token in [assemblyParser.JEQ, assemblyParser.JNEQ, assemblyParser.JZ, assemblyParser.JNZ, assemblyParser.JLTU, assemblyParser.JGTU, assemblyParser.JLEU, assemblyParser.JGEU, assemblyParser.JLTS, assemblyParser.JGTS, assemblyParser.JLES, assemblyParser.JGES, assemblyParser.JUMP]:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 1554\n                self.jump_instruction()\n                pass\n            elif token in [assemblyParser.BOOT, assemblyParser.RESUME, assemblyParser.CALL, assemblyParser.TIME_CFG, assemblyParser.DIV_STEP, assemblyParser.MUL_STEP, assemblyParser.STOP, assemblyParser.MOVD, assemblyParser.SWAPD, assemblyParser.LBS, assemblyParser.LBU, assemblyParser.LD, assemblyParser.LHS, assemblyParser.LHU, assemblyParser.LW, assemblyParser.SB, assemblyParser.SD, assemblyParser.SH, assemblyParser.SW, assemblyParser.BKP]:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 1555\n                self.shortcut_instruction()\n                pass\n            else:\n                raise NoViableAltException(self)\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def andn_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Andn_rrif_instructionContext,0)\n\n\n        def nand_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Nand_rrif_instructionContext,0)\n\n\n        def nor_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Nor_rrif_instructionContext,0)\n\n\n        def nxor_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Nxor_rrif_instructionContext,0)\n\n\n        def orn_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Orn_rrif_instructionContext,0)\n\n\n        def hash_rrif_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Hash_rrif_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterRrif_instruction\" ):\n                listener.enterRrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitRrif_instruction\" ):\n                listener.exitRrif_instruction(self)\n\n\n\n\n    def rrif_instruction(self):\n\n        localctx = assemblyParser.Rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 260, self.RULE_rrif_instruction)\n        try:\n            self.state = 1564\n            self._errHandler.sync(self)\n            token = self._input.LA(1)\n            if token in [assemblyParser.ANDN]:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1558\n                self.andn_rrif_instruction()\n                pass\n            elif token in [assemblyParser.NAND]:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1559\n                self.nand_rrif_instruction()\n                pass\n            elif token in [assemblyParser.NOR]:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1560\n                self.nor_rrif_instruction()\n                pass\n            elif token in [assemblyParser.NXOR]:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 1561\n                self.nxor_rrif_instruction()\n                pass\n            elif token in [assemblyParser.ORN]:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 1562\n                self.orn_rrif_instruction()\n                pass\n            elif token in [assemblyParser.HASH]:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 1563\n                self.hash_rrif_instruction()\n                pass\n            else:\n                raise NoViableAltException(self)\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Andn_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ANDN(self):\n            return self.getToken(assemblyParser.ANDN, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_andn_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterAndn_rrif_instruction\" ):\n                listener.enterAndn_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitAndn_rrif_instruction\" ):\n                listener.exitAndn_rrif_instruction(self)\n\n\n\n\n    def andn_rrif_instruction(self):\n\n        localctx = assemblyParser.Andn_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 262, self.RULE_andn_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1566\n            self.match(assemblyParser.ANDN)\n            self.state = 1567\n            self.match(assemblyParser.T__3)\n            self.state = 1568\n            self.match(assemblyParser.GPRegister)\n            self.state = 1569\n            self.match(assemblyParser.T__3)\n            self.state = 1570\n            self.src_register()\n            self.state = 1571\n            self.match(assemblyParser.T__3)\n            self.state = 1572\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Nand_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NAND(self):\n            return self.getToken(assemblyParser.NAND, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_nand_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNand_rrif_instruction\" ):\n                listener.enterNand_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNand_rrif_instruction\" ):\n                listener.exitNand_rrif_instruction(self)\n\n\n\n\n    def nand_rrif_instruction(self):\n\n        localctx = assemblyParser.Nand_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 264, self.RULE_nand_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1574\n            self.match(assemblyParser.NAND)\n            self.state = 1575\n            self.match(assemblyParser.T__3)\n            self.state = 1576\n            self.match(assemblyParser.GPRegister)\n            self.state = 1577\n            self.match(assemblyParser.T__3)\n            self.state = 1578\n            self.src_register()\n            self.state = 1579\n            self.match(assemblyParser.T__3)\n            self.state = 1580\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Nor_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NOR(self):\n            return self.getToken(assemblyParser.NOR, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_nor_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNor_rrif_instruction\" ):\n                listener.enterNor_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNor_rrif_instruction\" ):\n                listener.exitNor_rrif_instruction(self)\n\n\n\n\n    def nor_rrif_instruction(self):\n\n        localctx = assemblyParser.Nor_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 266, self.RULE_nor_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1582\n            self.match(assemblyParser.NOR)\n            self.state = 1583\n            self.match(assemblyParser.T__3)\n            self.state = 1584\n            self.match(assemblyParser.GPRegister)\n            self.state = 1585\n            self.match(assemblyParser.T__3)\n            self.state = 1586\n            self.src_register()\n            self.state = 1587\n            self.match(assemblyParser.T__3)\n            self.state = 1588\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Nxor_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NXOR(self):\n            return self.getToken(assemblyParser.NXOR, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_nxor_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNxor_rrif_instruction\" ):\n                listener.enterNxor_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNxor_rrif_instruction\" ):\n                listener.exitNxor_rrif_instruction(self)\n\n\n\n\n    def nxor_rrif_instruction(self):\n\n        localctx = assemblyParser.Nxor_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 268, self.RULE_nxor_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1590\n            self.match(assemblyParser.NXOR)\n            self.state = 1591\n            self.match(assemblyParser.T__3)\n            self.state = 1592\n            self.match(assemblyParser.GPRegister)\n            self.state = 1593\n            self.match(assemblyParser.T__3)\n            self.state = 1594\n            self.src_register()\n            self.state = 1595\n            self.match(assemblyParser.T__3)\n            self.state = 1596\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Orn_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def ORN(self):\n            return self.getToken(assemblyParser.ORN, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_orn_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterOrn_rrif_instruction\" ):\n                listener.enterOrn_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitOrn_rrif_instruction\" ):\n                listener.exitOrn_rrif_instruction(self)\n\n\n\n\n    def orn_rrif_instruction(self):\n\n        localctx = assemblyParser.Orn_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 270, self.RULE_orn_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1598\n            self.match(assemblyParser.ORN)\n            self.state = 1599\n            self.match(assemblyParser.T__3)\n            self.state = 1600\n            self.match(assemblyParser.GPRegister)\n            self.state = 1601\n            self.match(assemblyParser.T__3)\n            self.state = 1602\n            self.src_register()\n            self.state = 1603\n            self.match(assemblyParser.T__3)\n            self.state = 1604\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Hash_rrif_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def HASH(self):\n            return self.getToken(assemblyParser.HASH, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_hash_rrif_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterHash_rrif_instruction\" ):\n                listener.enterHash_rrif_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitHash_rrif_instruction\" ):\n                listener.exitHash_rrif_instruction(self)\n\n\n\n\n    def hash_rrif_instruction(self):\n\n        localctx = assemblyParser.Hash_rrif_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 272, self.RULE_hash_rrif_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1606\n            self.match(assemblyParser.HASH)\n            self.state = 1607\n            self.match(assemblyParser.T__3)\n            self.state = 1608\n            self.match(assemblyParser.GPRegister)\n            self.state = 1609\n            self.match(assemblyParser.T__3)\n            self.state = 1610\n            self.src_register()\n            self.state = 1611\n            self.match(assemblyParser.T__3)\n            self.state = 1612\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def move_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_ri_instructionContext,0)\n\n\n        def move_rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_rici_instructionContext,0)\n\n\n        def move_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_rr_instructionContext,0)\n\n\n        def move_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_rrci_instructionContext,0)\n\n\n        def move_s_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_s_ri_instructionContext,0)\n\n\n        def move_s_rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_s_rici_instructionContext,0)\n\n\n        def move_s_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_s_rr_instructionContext,0)\n\n\n        def move_s_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_s_rrci_instructionContext,0)\n\n\n        def move_u_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_u_ri_instructionContext,0)\n\n\n        def move_u_rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_u_rici_instructionContext,0)\n\n\n        def move_u_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_u_rr_instructionContext,0)\n\n\n        def move_u_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Move_u_rrci_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_instruction\" ):\n                listener.enterMove_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_instruction\" ):\n                listener.exitMove_instruction(self)\n\n\n\n\n    def move_instruction(self):\n\n        localctx = assemblyParser.Move_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 274, self.RULE_move_instruction)\n        try:\n            self.state = 1626\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,15,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1614\n                self.move_ri_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1615\n                self.move_rici_instruction()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1616\n                self.move_rr_instruction()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 1617\n                self.move_rrci_instruction()\n                pass\n\n            elif la_ == 5:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 1618\n                self.move_s_ri_instruction()\n                pass\n\n            elif la_ == 6:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 1619\n                self.move_s_rici_instruction()\n                pass\n\n            elif la_ == 7:\n                self.enterOuterAlt(localctx, 7)\n                self.state = 1620\n                self.move_s_rr_instruction()\n                pass\n\n            elif la_ == 8:\n                self.enterOuterAlt(localctx, 8)\n                self.state = 1621\n                self.move_s_rrci_instruction()\n                pass\n\n            elif la_ == 9:\n                self.enterOuterAlt(localctx, 9)\n                self.state = 1622\n                self.move_u_ri_instruction()\n                pass\n\n            elif la_ == 10:\n                self.enterOuterAlt(localctx, 10)\n                self.state = 1623\n                self.move_u_rici_instruction()\n                pass\n\n            elif la_ == 11:\n                self.enterOuterAlt(localctx, 11)\n                self.state = 1624\n                self.move_u_rr_instruction()\n                pass\n\n            elif la_ == 12:\n                self.enterOuterAlt(localctx, 12)\n                self.state = 1625\n                self.move_u_rrci_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_ri_instruction\" ):\n                listener.enterMove_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_ri_instruction\" ):\n                listener.exitMove_ri_instruction(self)\n\n\n\n\n    def move_ri_instruction(self):\n\n        localctx = assemblyParser.Move_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 276, self.RULE_move_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1628\n            self.match(assemblyParser.MOVE)\n            self.state = 1629\n            self.match(assemblyParser.T__3)\n            self.state = 1630\n            self.match(assemblyParser.GPRegister)\n            self.state = 1631\n            self.match(assemblyParser.T__3)\n            self.state = 1632\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_rici_instruction\" ):\n                listener.enterMove_rici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_rici_instruction\" ):\n                listener.exitMove_rici_instruction(self)\n\n\n\n\n    def move_rici_instruction(self):\n\n        localctx = assemblyParser.Move_rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 278, self.RULE_move_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1634\n            self.match(assemblyParser.MOVE)\n            self.state = 1635\n            self.match(assemblyParser.T__3)\n            self.state = 1636\n            self.match(assemblyParser.GPRegister)\n            self.state = 1637\n            self.match(assemblyParser.T__3)\n            self.state = 1638\n            self.number()\n            self.state = 1639\n            self.match(assemblyParser.T__3)\n            self.state = 1640\n            self.condition()\n            self.state = 1641\n            self.match(assemblyParser.T__3)\n            self.state = 1642\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_rr_instruction\" ):\n                listener.enterMove_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_rr_instruction\" ):\n                listener.exitMove_rr_instruction(self)\n\n\n\n\n    def move_rr_instruction(self):\n\n        localctx = assemblyParser.Move_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 280, self.RULE_move_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1644\n            self.match(assemblyParser.MOVE)\n            self.state = 1645\n            self.match(assemblyParser.T__3)\n            self.state = 1646\n            self.match(assemblyParser.GPRegister)\n            self.state = 1647\n            self.match(assemblyParser.T__3)\n            self.state = 1648\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_rrci_instruction\" ):\n                listener.enterMove_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_rrci_instruction\" ):\n                listener.exitMove_rrci_instruction(self)\n\n\n\n\n    def move_rrci_instruction(self):\n\n        localctx = assemblyParser.Move_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 282, self.RULE_move_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1650\n            self.match(assemblyParser.MOVE)\n            self.state = 1651\n            self.match(assemblyParser.T__3)\n            self.state = 1652\n            self.match(assemblyParser.GPRegister)\n            self.state = 1653\n            self.match(assemblyParser.T__3)\n            self.state = 1654\n            self.src_register()\n            self.state = 1655\n            self.match(assemblyParser.T__3)\n            self.state = 1656\n            self.condition()\n            self.state = 1657\n            self.match(assemblyParser.T__3)\n            self.state = 1658\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_s_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_s_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_s_ri_instruction\" ):\n                listener.enterMove_s_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_s_ri_instruction\" ):\n                listener.exitMove_s_ri_instruction(self)\n\n\n\n\n    def move_s_ri_instruction(self):\n\n        localctx = assemblyParser.Move_s_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 284, self.RULE_move_s_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1660\n            self.match(assemblyParser.MOVE)\n            self.state = 1661\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1662\n            self.match(assemblyParser.T__3)\n            self.state = 1663\n            self.match(assemblyParser.PairRegister)\n            self.state = 1664\n            self.match(assemblyParser.T__3)\n            self.state = 1665\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_s_rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_s_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_s_rici_instruction\" ):\n                listener.enterMove_s_rici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_s_rici_instruction\" ):\n                listener.exitMove_s_rici_instruction(self)\n\n\n\n\n    def move_s_rici_instruction(self):\n\n        localctx = assemblyParser.Move_s_rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 286, self.RULE_move_s_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1667\n            self.match(assemblyParser.MOVE)\n            self.state = 1668\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1669\n            self.match(assemblyParser.T__3)\n            self.state = 1670\n            self.match(assemblyParser.PairRegister)\n            self.state = 1671\n            self.match(assemblyParser.T__3)\n            self.state = 1672\n            self.number()\n            self.state = 1673\n            self.match(assemblyParser.T__3)\n            self.state = 1674\n            self.condition()\n            self.state = 1675\n            self.match(assemblyParser.T__3)\n            self.state = 1676\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_s_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_s_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_s_rr_instruction\" ):\n                listener.enterMove_s_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_s_rr_instruction\" ):\n                listener.exitMove_s_rr_instruction(self)\n\n\n\n\n    def move_s_rr_instruction(self):\n\n        localctx = assemblyParser.Move_s_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 288, self.RULE_move_s_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1678\n            self.match(assemblyParser.MOVE)\n            self.state = 1679\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1680\n            self.match(assemblyParser.T__3)\n            self.state = 1681\n            self.match(assemblyParser.PairRegister)\n            self.state = 1682\n            self.match(assemblyParser.T__3)\n            self.state = 1683\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_s_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_s_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_s_rrci_instruction\" ):\n                listener.enterMove_s_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_s_rrci_instruction\" ):\n                listener.exitMove_s_rrci_instruction(self)\n\n\n\n\n    def move_s_rrci_instruction(self):\n\n        localctx = assemblyParser.Move_s_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 290, self.RULE_move_s_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1685\n            self.match(assemblyParser.MOVE)\n            self.state = 1686\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 1687\n            self.match(assemblyParser.T__3)\n            self.state = 1688\n            self.match(assemblyParser.PairRegister)\n            self.state = 1689\n            self.match(assemblyParser.T__3)\n            self.state = 1690\n            self.src_register()\n            self.state = 1691\n            self.match(assemblyParser.T__3)\n            self.state = 1692\n            self.condition()\n            self.state = 1693\n            self.match(assemblyParser.T__3)\n            self.state = 1694\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_u_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_u_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_u_ri_instruction\" ):\n                listener.enterMove_u_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_u_ri_instruction\" ):\n                listener.exitMove_u_ri_instruction(self)\n\n\n\n\n    def move_u_ri_instruction(self):\n\n        localctx = assemblyParser.Move_u_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 292, self.RULE_move_u_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1696\n            self.match(assemblyParser.MOVE)\n            self.state = 1697\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1698\n            self.match(assemblyParser.T__3)\n            self.state = 1699\n            self.match(assemblyParser.PairRegister)\n            self.state = 1700\n            self.match(assemblyParser.T__3)\n            self.state = 1701\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_u_rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_u_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_u_rici_instruction\" ):\n                listener.enterMove_u_rici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_u_rici_instruction\" ):\n                listener.exitMove_u_rici_instruction(self)\n\n\n\n\n    def move_u_rici_instruction(self):\n\n        localctx = assemblyParser.Move_u_rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 294, self.RULE_move_u_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1703\n            self.match(assemblyParser.MOVE)\n            self.state = 1704\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1705\n            self.match(assemblyParser.T__3)\n            self.state = 1706\n            self.match(assemblyParser.PairRegister)\n            self.state = 1707\n            self.match(assemblyParser.T__3)\n            self.state = 1708\n            self.number()\n            self.state = 1709\n            self.match(assemblyParser.T__3)\n            self.state = 1710\n            self.condition()\n            self.state = 1711\n            self.match(assemblyParser.T__3)\n            self.state = 1712\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_u_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_u_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_u_rr_instruction\" ):\n                listener.enterMove_u_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_u_rr_instruction\" ):\n                listener.exitMove_u_rr_instruction(self)\n\n\n\n\n    def move_u_rr_instruction(self):\n\n        localctx = assemblyParser.Move_u_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 296, self.RULE_move_u_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1714\n            self.match(assemblyParser.MOVE)\n            self.state = 1715\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1716\n            self.match(assemblyParser.T__3)\n            self.state = 1717\n            self.match(assemblyParser.PairRegister)\n            self.state = 1718\n            self.match(assemblyParser.T__3)\n            self.state = 1719\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Move_u_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVE(self):\n            return self.getToken(assemblyParser.MOVE, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_move_u_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMove_u_rrci_instruction\" ):\n                listener.enterMove_u_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMove_u_rrci_instruction\" ):\n                listener.exitMove_u_rrci_instruction(self)\n\n\n\n\n    def move_u_rrci_instruction(self):\n\n        localctx = assemblyParser.Move_u_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 298, self.RULE_move_u_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1721\n            self.match(assemblyParser.MOVE)\n            self.state = 1722\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 1723\n            self.match(assemblyParser.T__3)\n            self.state = 1724\n            self.match(assemblyParser.PairRegister)\n            self.state = 1725\n            self.match(assemblyParser.T__3)\n            self.state = 1726\n            self.src_register()\n            self.state = 1727\n            self.match(assemblyParser.T__3)\n            self.state = 1728\n            self.condition()\n            self.state = 1729\n            self.match(assemblyParser.T__3)\n            self.state = 1730\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Neg_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def neg_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Neg_rr_instructionContext,0)\n\n\n        def neg_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Neg_rrci_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_neg_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNeg_instruction\" ):\n                listener.enterNeg_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNeg_instruction\" ):\n                listener.exitNeg_instruction(self)\n\n\n\n\n    def neg_instruction(self):\n\n        localctx = assemblyParser.Neg_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 300, self.RULE_neg_instruction)\n        try:\n            self.state = 1734\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,16,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1732\n                self.neg_rr_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1733\n                self.neg_rrci_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Neg_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NEG(self):\n            return self.getToken(assemblyParser.NEG, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_neg_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNeg_rr_instruction\" ):\n                listener.enterNeg_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNeg_rr_instruction\" ):\n                listener.exitNeg_rr_instruction(self)\n\n\n\n\n    def neg_rr_instruction(self):\n\n        localctx = assemblyParser.Neg_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 302, self.RULE_neg_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1736\n            self.match(assemblyParser.NEG)\n            self.state = 1737\n            self.match(assemblyParser.T__3)\n            self.state = 1738\n            self.match(assemblyParser.GPRegister)\n            self.state = 1739\n            self.match(assemblyParser.T__3)\n            self.state = 1740\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Neg_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NEG(self):\n            return self.getToken(assemblyParser.NEG, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_neg_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNeg_rrci_instruction\" ):\n                listener.enterNeg_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNeg_rrci_instruction\" ):\n                listener.exitNeg_rrci_instruction(self)\n\n\n\n\n    def neg_rrci_instruction(self):\n\n        localctx = assemblyParser.Neg_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 304, self.RULE_neg_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1742\n            self.match(assemblyParser.NEG)\n            self.state = 1743\n            self.match(assemblyParser.T__3)\n            self.state = 1744\n            self.match(assemblyParser.GPRegister)\n            self.state = 1745\n            self.match(assemblyParser.T__3)\n            self.state = 1746\n            self.src_register()\n            self.state = 1747\n            self.match(assemblyParser.T__3)\n            self.state = 1748\n            self.condition()\n            self.state = 1749\n            self.match(assemblyParser.T__3)\n            self.state = 1750\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Not_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def not_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Not_rr_instructionContext,0)\n\n\n        def not_rrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Not_rrci_instructionContext,0)\n\n\n        def not_zrci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Not_zrci_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_not_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNot_instruction\" ):\n                listener.enterNot_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNot_instruction\" ):\n                listener.exitNot_instruction(self)\n\n\n\n\n    def not_instruction(self):\n\n        localctx = assemblyParser.Not_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 306, self.RULE_not_instruction)\n        try:\n            self.state = 1755\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,17,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1752\n                self.not_rr_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1753\n                self.not_rrci_instruction()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1754\n                self.not_zrci_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Not_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NOT(self):\n            return self.getToken(assemblyParser.NOT, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_not_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNot_rr_instruction\" ):\n                listener.enterNot_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNot_rr_instruction\" ):\n                listener.exitNot_rr_instruction(self)\n\n\n\n\n    def not_rr_instruction(self):\n\n        localctx = assemblyParser.Not_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 308, self.RULE_not_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1757\n            self.match(assemblyParser.NOT)\n            self.state = 1758\n            self.match(assemblyParser.T__3)\n            self.state = 1759\n            self.match(assemblyParser.GPRegister)\n            self.state = 1760\n            self.match(assemblyParser.T__3)\n            self.state = 1761\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Not_rrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NOT(self):\n            return self.getToken(assemblyParser.NOT, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_not_rrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNot_rrci_instruction\" ):\n                listener.enterNot_rrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNot_rrci_instruction\" ):\n                listener.exitNot_rrci_instruction(self)\n\n\n\n\n    def not_rrci_instruction(self):\n\n        localctx = assemblyParser.Not_rrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 310, self.RULE_not_rrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1763\n            self.match(assemblyParser.NOT)\n            self.state = 1764\n            self.match(assemblyParser.T__3)\n            self.state = 1765\n            self.match(assemblyParser.GPRegister)\n            self.state = 1766\n            self.match(assemblyParser.T__3)\n            self.state = 1767\n            self.src_register()\n            self.state = 1768\n            self.match(assemblyParser.T__3)\n            self.state = 1769\n            self.condition()\n            self.state = 1770\n            self.match(assemblyParser.T__3)\n            self.state = 1771\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Not_zrci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def NOT(self):\n            return self.getToken(assemblyParser.NOT, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def condition(self):\n            return self.getTypedRuleContext(assemblyParser.ConditionContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_not_zrci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterNot_zrci_instruction\" ):\n                listener.enterNot_zrci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitNot_zrci_instruction\" ):\n                listener.exitNot_zrci_instruction(self)\n\n\n\n\n    def not_zrci_instruction(self):\n\n        localctx = assemblyParser.Not_zrci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 312, self.RULE_not_zrci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1773\n            self.match(assemblyParser.NOT)\n            self.state = 1774\n            self.match(assemblyParser.T__3)\n            self.state = 1775\n            self.src_register()\n            self.state = 1776\n            self.match(assemblyParser.T__3)\n            self.state = 1777\n            self.condition()\n            self.state = 1778\n            self.match(assemblyParser.T__3)\n            self.state = 1779\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jump_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def jeq_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jeq_rii_instructionContext,0)\n\n\n        def jeq_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jeq_rri_instructionContext,0)\n\n\n        def jneq_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jneq_rii_instructionContext,0)\n\n\n        def jneq_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jneq_rri_instructionContext,0)\n\n\n        def jz_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jz_ri_instructionContext,0)\n\n\n        def jnz_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jnz_ri_instructionContext,0)\n\n\n        def jltu_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jltu_rii_instructionContext,0)\n\n\n        def jltu_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jltu_rri_instructionContext,0)\n\n\n        def jgtu_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgtu_rii_instructionContext,0)\n\n\n        def jgtu_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgtu_rri_instructionContext,0)\n\n\n        def jleu_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jleu_rii_instructionContext,0)\n\n\n        def jleu_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jleu_rri_instructionContext,0)\n\n\n        def jgeu_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgeu_rii_instructionContext,0)\n\n\n        def jgeu_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgeu_rri_instructionContext,0)\n\n\n        def jlts_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jlts_rii_instructionContext,0)\n\n\n        def jlts_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jlts_rri_instructionContext,0)\n\n\n        def jgts_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgts_rii_instructionContext,0)\n\n\n        def jgts_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jgts_rri_instructionContext,0)\n\n\n        def jles_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jles_rii_instructionContext,0)\n\n\n        def jles_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jles_rri_instructionContext,0)\n\n\n        def jges_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jges_rii_instructionContext,0)\n\n\n        def jges_rri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jges_rri_instructionContext,0)\n\n\n        def jump_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jump_ri_instructionContext,0)\n\n\n        def jump_i_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jump_i_instructionContext,0)\n\n\n        def jump_r_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Jump_r_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jump_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJump_instruction\" ):\n                listener.enterJump_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJump_instruction\" ):\n                listener.exitJump_instruction(self)\n\n\n\n\n    def jump_instruction(self):\n\n        localctx = assemblyParser.Jump_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 314, self.RULE_jump_instruction)\n        try:\n            self.state = 1806\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,18,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1781\n                self.jeq_rii_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1782\n                self.jeq_rri_instruction()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1783\n                self.jneq_rii_instruction()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 1784\n                self.jneq_rri_instruction()\n                pass\n\n            elif la_ == 5:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 1785\n                self.jz_ri_instruction()\n                pass\n\n            elif la_ == 6:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 1786\n                self.jnz_ri_instruction()\n                pass\n\n            elif la_ == 7:\n                self.enterOuterAlt(localctx, 7)\n                self.state = 1787\n                self.jltu_rii_instruction()\n                pass\n\n            elif la_ == 8:\n                self.enterOuterAlt(localctx, 8)\n                self.state = 1788\n                self.jltu_rri_instruction()\n                pass\n\n            elif la_ == 9:\n                self.enterOuterAlt(localctx, 9)\n                self.state = 1789\n                self.jgtu_rii_instruction()\n                pass\n\n            elif la_ == 10:\n                self.enterOuterAlt(localctx, 10)\n                self.state = 1790\n                self.jgtu_rri_instruction()\n                pass\n\n            elif la_ == 11:\n                self.enterOuterAlt(localctx, 11)\n                self.state = 1791\n                self.jleu_rii_instruction()\n                pass\n\n            elif la_ == 12:\n                self.enterOuterAlt(localctx, 12)\n                self.state = 1792\n                self.jleu_rri_instruction()\n                pass\n\n            elif la_ == 13:\n                self.enterOuterAlt(localctx, 13)\n                self.state = 1793\n                self.jgeu_rii_instruction()\n                pass\n\n            elif la_ == 14:\n                self.enterOuterAlt(localctx, 14)\n                self.state = 1794\n                self.jgeu_rri_instruction()\n                pass\n\n            elif la_ == 15:\n                self.enterOuterAlt(localctx, 15)\n                self.state = 1795\n                self.jlts_rii_instruction()\n                pass\n\n            elif la_ == 16:\n                self.enterOuterAlt(localctx, 16)\n                self.state = 1796\n                self.jlts_rri_instruction()\n                pass\n\n            elif la_ == 17:\n                self.enterOuterAlt(localctx, 17)\n                self.state = 1797\n                self.jgts_rii_instruction()\n                pass\n\n            elif la_ == 18:\n                self.enterOuterAlt(localctx, 18)\n                self.state = 1798\n                self.jgts_rri_instruction()\n                pass\n\n            elif la_ == 19:\n                self.enterOuterAlt(localctx, 19)\n                self.state = 1799\n                self.jles_rii_instruction()\n                pass\n\n            elif la_ == 20:\n                self.enterOuterAlt(localctx, 20)\n                self.state = 1800\n                self.jles_rri_instruction()\n                pass\n\n            elif la_ == 21:\n                self.enterOuterAlt(localctx, 21)\n                self.state = 1801\n                self.jges_rii_instruction()\n                pass\n\n            elif la_ == 22:\n                self.enterOuterAlt(localctx, 22)\n                self.state = 1802\n                self.jges_rri_instruction()\n                pass\n\n            elif la_ == 23:\n                self.enterOuterAlt(localctx, 23)\n                self.state = 1803\n                self.jump_ri_instruction()\n                pass\n\n            elif la_ == 24:\n                self.enterOuterAlt(localctx, 24)\n                self.state = 1804\n                self.jump_i_instruction()\n                pass\n\n            elif la_ == 25:\n                self.enterOuterAlt(localctx, 25)\n                self.state = 1805\n                self.jump_r_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jeq_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JEQ(self):\n            return self.getToken(assemblyParser.JEQ, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Program_counterContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Program_counterContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jeq_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJeq_rii_instruction\" ):\n                listener.enterJeq_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJeq_rii_instruction\" ):\n                listener.exitJeq_rii_instruction(self)\n\n\n\n\n    def jeq_rii_instruction(self):\n\n        localctx = assemblyParser.Jeq_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 316, self.RULE_jeq_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1808\n            self.match(assemblyParser.JEQ)\n            self.state = 1809\n            self.match(assemblyParser.T__3)\n            self.state = 1810\n            self.src_register()\n            self.state = 1811\n            self.match(assemblyParser.T__3)\n            self.state = 1812\n            self.program_counter()\n            self.state = 1813\n            self.match(assemblyParser.T__3)\n            self.state = 1814\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jeq_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JEQ(self):\n            return self.getToken(assemblyParser.JEQ, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jeq_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJeq_rri_instruction\" ):\n                listener.enterJeq_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJeq_rri_instruction\" ):\n                listener.exitJeq_rri_instruction(self)\n\n\n\n\n    def jeq_rri_instruction(self):\n\n        localctx = assemblyParser.Jeq_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 318, self.RULE_jeq_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1816\n            self.match(assemblyParser.JEQ)\n            self.state = 1817\n            self.match(assemblyParser.T__3)\n            self.state = 1818\n            self.src_register()\n            self.state = 1819\n            self.match(assemblyParser.T__3)\n            self.state = 1820\n            self.src_register()\n            self.state = 1821\n            self.match(assemblyParser.T__3)\n            self.state = 1822\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jneq_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JNEQ(self):\n            return self.getToken(assemblyParser.JNEQ, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jneq_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJneq_rii_instruction\" ):\n                listener.enterJneq_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJneq_rii_instruction\" ):\n                listener.exitJneq_rii_instruction(self)\n\n\n\n\n    def jneq_rii_instruction(self):\n\n        localctx = assemblyParser.Jneq_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 320, self.RULE_jneq_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1824\n            self.match(assemblyParser.JNEQ)\n            self.state = 1825\n            self.match(assemblyParser.T__3)\n            self.state = 1826\n            self.src_register()\n            self.state = 1827\n            self.match(assemblyParser.T__3)\n            self.state = 1828\n            self.number()\n            self.state = 1829\n            self.match(assemblyParser.T__3)\n            self.state = 1830\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jneq_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JNEQ(self):\n            return self.getToken(assemblyParser.JNEQ, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jneq_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJneq_rri_instruction\" ):\n                listener.enterJneq_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJneq_rri_instruction\" ):\n                listener.exitJneq_rri_instruction(self)\n\n\n\n\n    def jneq_rri_instruction(self):\n\n        localctx = assemblyParser.Jneq_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 322, self.RULE_jneq_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1832\n            self.match(assemblyParser.JNEQ)\n            self.state = 1833\n            self.match(assemblyParser.T__3)\n            self.state = 1834\n            self.src_register()\n            self.state = 1835\n            self.match(assemblyParser.T__3)\n            self.state = 1836\n            self.src_register()\n            self.state = 1837\n            self.match(assemblyParser.T__3)\n            self.state = 1838\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jz_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JZ(self):\n            return self.getToken(assemblyParser.JZ, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jz_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJz_ri_instruction\" ):\n                listener.enterJz_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJz_ri_instruction\" ):\n                listener.exitJz_ri_instruction(self)\n\n\n\n\n    def jz_ri_instruction(self):\n\n        localctx = assemblyParser.Jz_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 324, self.RULE_jz_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1840\n            self.match(assemblyParser.JZ)\n            self.state = 1841\n            self.match(assemblyParser.T__3)\n            self.state = 1842\n            self.src_register()\n            self.state = 1843\n            self.match(assemblyParser.T__3)\n            self.state = 1844\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jnz_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JNZ(self):\n            return self.getToken(assemblyParser.JNZ, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jnz_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJnz_ri_instruction\" ):\n                listener.enterJnz_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJnz_ri_instruction\" ):\n                listener.exitJnz_ri_instruction(self)\n\n\n\n\n    def jnz_ri_instruction(self):\n\n        localctx = assemblyParser.Jnz_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 326, self.RULE_jnz_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1846\n            self.match(assemblyParser.JNZ)\n            self.state = 1847\n            self.match(assemblyParser.T__3)\n            self.state = 1848\n            self.src_register()\n            self.state = 1849\n            self.match(assemblyParser.T__3)\n            self.state = 1850\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jltu_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLTU(self):\n            return self.getToken(assemblyParser.JLTU, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jltu_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJltu_rii_instruction\" ):\n                listener.enterJltu_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJltu_rii_instruction\" ):\n                listener.exitJltu_rii_instruction(self)\n\n\n\n\n    def jltu_rii_instruction(self):\n\n        localctx = assemblyParser.Jltu_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 328, self.RULE_jltu_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1852\n            self.match(assemblyParser.JLTU)\n            self.state = 1853\n            self.match(assemblyParser.T__3)\n            self.state = 1854\n            self.src_register()\n            self.state = 1855\n            self.match(assemblyParser.T__3)\n            self.state = 1856\n            self.number()\n            self.state = 1857\n            self.match(assemblyParser.T__3)\n            self.state = 1858\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jltu_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLTU(self):\n            return self.getToken(assemblyParser.JLTU, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jltu_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJltu_rri_instruction\" ):\n                listener.enterJltu_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJltu_rri_instruction\" ):\n                listener.exitJltu_rri_instruction(self)\n\n\n\n\n    def jltu_rri_instruction(self):\n\n        localctx = assemblyParser.Jltu_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 330, self.RULE_jltu_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1860\n            self.match(assemblyParser.JLTU)\n            self.state = 1861\n            self.match(assemblyParser.T__3)\n            self.state = 1862\n            self.src_register()\n            self.state = 1863\n            self.match(assemblyParser.T__3)\n            self.state = 1864\n            self.src_register()\n            self.state = 1865\n            self.match(assemblyParser.T__3)\n            self.state = 1866\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgtu_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGTU(self):\n            return self.getToken(assemblyParser.JGTU, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgtu_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgtu_rii_instruction\" ):\n                listener.enterJgtu_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgtu_rii_instruction\" ):\n                listener.exitJgtu_rii_instruction(self)\n\n\n\n\n    def jgtu_rii_instruction(self):\n\n        localctx = assemblyParser.Jgtu_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 332, self.RULE_jgtu_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1868\n            self.match(assemblyParser.JGTU)\n            self.state = 1869\n            self.match(assemblyParser.T__3)\n            self.state = 1870\n            self.src_register()\n            self.state = 1871\n            self.match(assemblyParser.T__3)\n            self.state = 1872\n            self.number()\n            self.state = 1873\n            self.match(assemblyParser.T__3)\n            self.state = 1874\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgtu_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGTU(self):\n            return self.getToken(assemblyParser.JGTU, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgtu_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgtu_rri_instruction\" ):\n                listener.enterJgtu_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgtu_rri_instruction\" ):\n                listener.exitJgtu_rri_instruction(self)\n\n\n\n\n    def jgtu_rri_instruction(self):\n\n        localctx = assemblyParser.Jgtu_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 334, self.RULE_jgtu_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1876\n            self.match(assemblyParser.JGTU)\n            self.state = 1877\n            self.match(assemblyParser.T__3)\n            self.state = 1878\n            self.src_register()\n            self.state = 1879\n            self.match(assemblyParser.T__3)\n            self.state = 1880\n            self.src_register()\n            self.state = 1881\n            self.match(assemblyParser.T__3)\n            self.state = 1882\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jleu_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLEU(self):\n            return self.getToken(assemblyParser.JLEU, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jleu_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJleu_rii_instruction\" ):\n                listener.enterJleu_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJleu_rii_instruction\" ):\n                listener.exitJleu_rii_instruction(self)\n\n\n\n\n    def jleu_rii_instruction(self):\n\n        localctx = assemblyParser.Jleu_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 336, self.RULE_jleu_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1884\n            self.match(assemblyParser.JLEU)\n            self.state = 1885\n            self.match(assemblyParser.T__3)\n            self.state = 1886\n            self.src_register()\n            self.state = 1887\n            self.match(assemblyParser.T__3)\n            self.state = 1888\n            self.number()\n            self.state = 1889\n            self.match(assemblyParser.T__3)\n            self.state = 1890\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jleu_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLEU(self):\n            return self.getToken(assemblyParser.JLEU, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jleu_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJleu_rri_instruction\" ):\n                listener.enterJleu_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJleu_rri_instruction\" ):\n                listener.exitJleu_rri_instruction(self)\n\n\n\n\n    def jleu_rri_instruction(self):\n\n        localctx = assemblyParser.Jleu_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 338, self.RULE_jleu_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1892\n            self.match(assemblyParser.JLEU)\n            self.state = 1893\n            self.match(assemblyParser.T__3)\n            self.state = 1894\n            self.src_register()\n            self.state = 1895\n            self.match(assemblyParser.T__3)\n            self.state = 1896\n            self.src_register()\n            self.state = 1897\n            self.match(assemblyParser.T__3)\n            self.state = 1898\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgeu_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGEU(self):\n            return self.getToken(assemblyParser.JGEU, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgeu_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgeu_rii_instruction\" ):\n                listener.enterJgeu_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgeu_rii_instruction\" ):\n                listener.exitJgeu_rii_instruction(self)\n\n\n\n\n    def jgeu_rii_instruction(self):\n\n        localctx = assemblyParser.Jgeu_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 340, self.RULE_jgeu_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1900\n            self.match(assemblyParser.JGEU)\n            self.state = 1901\n            self.match(assemblyParser.T__3)\n            self.state = 1902\n            self.src_register()\n            self.state = 1903\n            self.match(assemblyParser.T__3)\n            self.state = 1904\n            self.number()\n            self.state = 1905\n            self.match(assemblyParser.T__3)\n            self.state = 1906\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgeu_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGEU(self):\n            return self.getToken(assemblyParser.JGEU, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgeu_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgeu_rri_instruction\" ):\n                listener.enterJgeu_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgeu_rri_instruction\" ):\n                listener.exitJgeu_rri_instruction(self)\n\n\n\n\n    def jgeu_rri_instruction(self):\n\n        localctx = assemblyParser.Jgeu_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 342, self.RULE_jgeu_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1908\n            self.match(assemblyParser.JGEU)\n            self.state = 1909\n            self.match(assemblyParser.T__3)\n            self.state = 1910\n            self.src_register()\n            self.state = 1911\n            self.match(assemblyParser.T__3)\n            self.state = 1912\n            self.src_register()\n            self.state = 1913\n            self.match(assemblyParser.T__3)\n            self.state = 1914\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jlts_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLTS(self):\n            return self.getToken(assemblyParser.JLTS, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jlts_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJlts_rii_instruction\" ):\n                listener.enterJlts_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJlts_rii_instruction\" ):\n                listener.exitJlts_rii_instruction(self)\n\n\n\n\n    def jlts_rii_instruction(self):\n\n        localctx = assemblyParser.Jlts_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 344, self.RULE_jlts_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1916\n            self.match(assemblyParser.JLTS)\n            self.state = 1917\n            self.match(assemblyParser.T__3)\n            self.state = 1918\n            self.src_register()\n            self.state = 1919\n            self.match(assemblyParser.T__3)\n            self.state = 1920\n            self.number()\n            self.state = 1921\n            self.match(assemblyParser.T__3)\n            self.state = 1922\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jlts_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLTS(self):\n            return self.getToken(assemblyParser.JLTS, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jlts_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJlts_rri_instruction\" ):\n                listener.enterJlts_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJlts_rri_instruction\" ):\n                listener.exitJlts_rri_instruction(self)\n\n\n\n\n    def jlts_rri_instruction(self):\n\n        localctx = assemblyParser.Jlts_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 346, self.RULE_jlts_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1924\n            self.match(assemblyParser.JLTS)\n            self.state = 1925\n            self.match(assemblyParser.T__3)\n            self.state = 1926\n            self.src_register()\n            self.state = 1927\n            self.match(assemblyParser.T__3)\n            self.state = 1928\n            self.src_register()\n            self.state = 1929\n            self.match(assemblyParser.T__3)\n            self.state = 1930\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgts_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGTS(self):\n            return self.getToken(assemblyParser.JGTS, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgts_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgts_rii_instruction\" ):\n                listener.enterJgts_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgts_rii_instruction\" ):\n                listener.exitJgts_rii_instruction(self)\n\n\n\n\n    def jgts_rii_instruction(self):\n\n        localctx = assemblyParser.Jgts_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 348, self.RULE_jgts_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1932\n            self.match(assemblyParser.JGTS)\n            self.state = 1933\n            self.match(assemblyParser.T__3)\n            self.state = 1934\n            self.src_register()\n            self.state = 1935\n            self.match(assemblyParser.T__3)\n            self.state = 1936\n            self.number()\n            self.state = 1937\n            self.match(assemblyParser.T__3)\n            self.state = 1938\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jgts_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGTS(self):\n            return self.getToken(assemblyParser.JGTS, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jgts_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJgts_rri_instruction\" ):\n                listener.enterJgts_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJgts_rri_instruction\" ):\n                listener.exitJgts_rri_instruction(self)\n\n\n\n\n    def jgts_rri_instruction(self):\n\n        localctx = assemblyParser.Jgts_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 350, self.RULE_jgts_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1940\n            self.match(assemblyParser.JGTS)\n            self.state = 1941\n            self.match(assemblyParser.T__3)\n            self.state = 1942\n            self.src_register()\n            self.state = 1943\n            self.match(assemblyParser.T__3)\n            self.state = 1944\n            self.src_register()\n            self.state = 1945\n            self.match(assemblyParser.T__3)\n            self.state = 1946\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jles_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLES(self):\n            return self.getToken(assemblyParser.JLES, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jles_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJles_rii_instruction\" ):\n                listener.enterJles_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJles_rii_instruction\" ):\n                listener.exitJles_rii_instruction(self)\n\n\n\n\n    def jles_rii_instruction(self):\n\n        localctx = assemblyParser.Jles_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 352, self.RULE_jles_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1948\n            self.match(assemblyParser.JLES)\n            self.state = 1949\n            self.match(assemblyParser.T__3)\n            self.state = 1950\n            self.src_register()\n            self.state = 1951\n            self.match(assemblyParser.T__3)\n            self.state = 1952\n            self.number()\n            self.state = 1953\n            self.match(assemblyParser.T__3)\n            self.state = 1954\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jles_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JLES(self):\n            return self.getToken(assemblyParser.JLES, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jles_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJles_rri_instruction\" ):\n                listener.enterJles_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJles_rri_instruction\" ):\n                listener.exitJles_rri_instruction(self)\n\n\n\n\n    def jles_rri_instruction(self):\n\n        localctx = assemblyParser.Jles_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 354, self.RULE_jles_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1956\n            self.match(assemblyParser.JLES)\n            self.state = 1957\n            self.match(assemblyParser.T__3)\n            self.state = 1958\n            self.src_register()\n            self.state = 1959\n            self.match(assemblyParser.T__3)\n            self.state = 1960\n            self.src_register()\n            self.state = 1961\n            self.match(assemblyParser.T__3)\n            self.state = 1962\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jges_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGES(self):\n            return self.getToken(assemblyParser.JGES, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jges_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJges_rii_instruction\" ):\n                listener.enterJges_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJges_rii_instruction\" ):\n                listener.exitJges_rii_instruction(self)\n\n\n\n\n    def jges_rii_instruction(self):\n\n        localctx = assemblyParser.Jges_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 356, self.RULE_jges_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1964\n            self.match(assemblyParser.JGES)\n            self.state = 1965\n            self.match(assemblyParser.T__3)\n            self.state = 1966\n            self.src_register()\n            self.state = 1967\n            self.match(assemblyParser.T__3)\n            self.state = 1968\n            self.number()\n            self.state = 1969\n            self.match(assemblyParser.T__3)\n            self.state = 1970\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jges_rri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JGES(self):\n            return self.getToken(assemblyParser.JGES, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jges_rri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJges_rri_instruction\" ):\n                listener.enterJges_rri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJges_rri_instruction\" ):\n                listener.exitJges_rri_instruction(self)\n\n\n\n\n    def jges_rri_instruction(self):\n\n        localctx = assemblyParser.Jges_rri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 358, self.RULE_jges_rri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1972\n            self.match(assemblyParser.JGES)\n            self.state = 1973\n            self.match(assemblyParser.T__3)\n            self.state = 1974\n            self.src_register()\n            self.state = 1975\n            self.match(assemblyParser.T__3)\n            self.state = 1976\n            self.src_register()\n            self.state = 1977\n            self.match(assemblyParser.T__3)\n            self.state = 1978\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jump_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JUMP(self):\n            return self.getToken(assemblyParser.JUMP, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jump_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJump_ri_instruction\" ):\n                listener.enterJump_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJump_ri_instruction\" ):\n                listener.exitJump_ri_instruction(self)\n\n\n\n\n    def jump_ri_instruction(self):\n\n        localctx = assemblyParser.Jump_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 360, self.RULE_jump_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1980\n            self.match(assemblyParser.JUMP)\n            self.state = 1981\n            self.match(assemblyParser.T__3)\n            self.state = 1982\n            self.src_register()\n            self.state = 1983\n            self.match(assemblyParser.T__3)\n            self.state = 1984\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jump_i_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JUMP(self):\n            return self.getToken(assemblyParser.JUMP, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jump_i_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJump_i_instruction\" ):\n                listener.enterJump_i_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJump_i_instruction\" ):\n                listener.exitJump_i_instruction(self)\n\n\n\n\n    def jump_i_instruction(self):\n\n        localctx = assemblyParser.Jump_i_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 362, self.RULE_jump_i_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1986\n            self.match(assemblyParser.JUMP)\n            self.state = 1987\n            self.match(assemblyParser.T__3)\n            self.state = 1988\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Jump_r_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def JUMP(self):\n            return self.getToken(assemblyParser.JUMP, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_jump_r_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterJump_r_instruction\" ):\n                listener.enterJump_r_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitJump_r_instruction\" ):\n                listener.exitJump_r_instruction(self)\n\n\n\n\n    def jump_r_instruction(self):\n\n        localctx = assemblyParser.Jump_r_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 364, self.RULE_jump_r_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 1990\n            self.match(assemblyParser.JUMP)\n            self.state = 1991\n            self.match(assemblyParser.T__3)\n            self.state = 1992\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Shortcut_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def div_step_drdici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Div_step_drdici_instructionContext,0)\n\n\n        def mul_step_drdici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Mul_step_drdici_instructionContext,0)\n\n\n        def boot_rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Boot_rici_instructionContext,0)\n\n\n        def resume_rici_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Resume_rici_instructionContext,0)\n\n\n        def stop_ci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Stop_ci_instructionContext,0)\n\n\n        def call_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Call_ri_instructionContext,0)\n\n\n        def call_rr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Call_rr_instructionContext,0)\n\n\n        def bkp_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Bkp_instructionContext,0)\n\n\n        def movd_ddci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Movd_ddci_instructionContext,0)\n\n\n        def swapd_ddci_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Swapd_ddci_instructionContext,0)\n\n\n        def time_cfg_zr_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Time_cfg_zr_instructionContext,0)\n\n\n        def lbs_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lbs_erri_instructionContext,0)\n\n\n        def lbs_s_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lbs_s_erri_instructionContext,0)\n\n\n        def lbu_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lbu_erri_instructionContext,0)\n\n\n        def lbu_u_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lbu_u_erri_instructionContext,0)\n\n\n        def ld_edri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Ld_edri_instructionContext,0)\n\n\n        def lhs_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lhs_erri_instructionContext,0)\n\n\n        def lhs_s_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lhs_s_erri_instructionContext,0)\n\n\n        def lhu_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lhu_erri_instructionContext,0)\n\n\n        def lhu_u_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lhu_u_erri_instructionContext,0)\n\n\n        def lw_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lw_erri_instructionContext,0)\n\n\n        def lw_s_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lw_s_erri_instructionContext,0)\n\n\n        def lw_u_erri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Lw_u_erri_instructionContext,0)\n\n\n        def sb_erii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sb_erii_instructionContext,0)\n\n\n        def sb_erir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sb_erir_instructionContext,0)\n\n\n        def sb_id_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sb_id_rii_instructionContext,0)\n\n\n        def sb_id_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sb_id_ri_instructionContext,0)\n\n\n        def sd_erii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sd_erii_instructionContext,0)\n\n\n        def sd_erid_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sd_erid_instructionContext,0)\n\n\n        def sd_id_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sd_id_rii_instructionContext,0)\n\n\n        def sd_id_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sd_id_ri_instructionContext,0)\n\n\n        def sh_erii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sh_erii_instructionContext,0)\n\n\n        def sh_erir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sh_erir_instructionContext,0)\n\n\n        def sh_id_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sh_id_rii_instructionContext,0)\n\n\n        def sh_id_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sh_id_ri_instructionContext,0)\n\n\n        def sw_erii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sw_erii_instructionContext,0)\n\n\n        def sw_erir_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sw_erir_instructionContext,0)\n\n\n        def sw_id_rii_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sw_id_rii_instructionContext,0)\n\n\n        def sw_id_ri_instruction(self):\n            return self.getTypedRuleContext(assemblyParser.Sw_id_ri_instructionContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_shortcut_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterShortcut_instruction\" ):\n                listener.enterShortcut_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitShortcut_instruction\" ):\n                listener.exitShortcut_instruction(self)\n\n\n\n\n    def shortcut_instruction(self):\n\n        localctx = assemblyParser.Shortcut_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 366, self.RULE_shortcut_instruction)\n        try:\n            self.state = 2033\n            self._errHandler.sync(self)\n            la_ = self._interp.adaptivePredict(self._input,19,self._ctx)\n            if la_ == 1:\n                self.enterOuterAlt(localctx, 1)\n                self.state = 1994\n                self.div_step_drdici_instruction()\n                pass\n\n            elif la_ == 2:\n                self.enterOuterAlt(localctx, 2)\n                self.state = 1995\n                self.mul_step_drdici_instruction()\n                pass\n\n            elif la_ == 3:\n                self.enterOuterAlt(localctx, 3)\n                self.state = 1996\n                self.boot_rici_instruction()\n                pass\n\n            elif la_ == 4:\n                self.enterOuterAlt(localctx, 4)\n                self.state = 1997\n                self.resume_rici_instruction()\n                pass\n\n            elif la_ == 5:\n                self.enterOuterAlt(localctx, 5)\n                self.state = 1998\n                self.stop_ci_instruction()\n                pass\n\n            elif la_ == 6:\n                self.enterOuterAlt(localctx, 6)\n                self.state = 1999\n                self.call_ri_instruction()\n                pass\n\n            elif la_ == 7:\n                self.enterOuterAlt(localctx, 7)\n                self.state = 2000\n                self.call_rr_instruction()\n                pass\n\n            elif la_ == 8:\n                self.enterOuterAlt(localctx, 8)\n                self.state = 2001\n                self.bkp_instruction()\n                pass\n\n            elif la_ == 9:\n                self.enterOuterAlt(localctx, 9)\n                self.state = 2002\n                self.movd_ddci_instruction()\n                pass\n\n            elif la_ == 10:\n                self.enterOuterAlt(localctx, 10)\n                self.state = 2003\n                self.swapd_ddci_instruction()\n                pass\n\n            elif la_ == 11:\n                self.enterOuterAlt(localctx, 11)\n                self.state = 2004\n                self.time_cfg_zr_instruction()\n                pass\n\n            elif la_ == 12:\n                self.enterOuterAlt(localctx, 12)\n                self.state = 2005\n                self.lbs_erri_instruction()\n                pass\n\n            elif la_ == 13:\n                self.enterOuterAlt(localctx, 13)\n                self.state = 2006\n                self.lbs_s_erri_instruction()\n                pass\n\n            elif la_ == 14:\n                self.enterOuterAlt(localctx, 14)\n                self.state = 2007\n                self.lbu_erri_instruction()\n                pass\n\n            elif la_ == 15:\n                self.enterOuterAlt(localctx, 15)\n                self.state = 2008\n                self.lbu_u_erri_instruction()\n                pass\n\n            elif la_ == 16:\n                self.enterOuterAlt(localctx, 16)\n                self.state = 2009\n                self.ld_edri_instruction()\n                pass\n\n            elif la_ == 17:\n                self.enterOuterAlt(localctx, 17)\n                self.state = 2010\n                self.lhs_erri_instruction()\n                pass\n\n            elif la_ == 18:\n                self.enterOuterAlt(localctx, 18)\n                self.state = 2011\n                self.lhs_s_erri_instruction()\n                pass\n\n            elif la_ == 19:\n                self.enterOuterAlt(localctx, 19)\n                self.state = 2012\n                self.lhu_erri_instruction()\n                pass\n\n            elif la_ == 20:\n                self.enterOuterAlt(localctx, 20)\n                self.state = 2013\n                self.lhu_u_erri_instruction()\n                pass\n\n            elif la_ == 21:\n                self.enterOuterAlt(localctx, 21)\n                self.state = 2014\n                self.lw_erri_instruction()\n                pass\n\n            elif la_ == 22:\n                self.enterOuterAlt(localctx, 22)\n                self.state = 2015\n                self.lw_s_erri_instruction()\n                pass\n\n            elif la_ == 23:\n                self.enterOuterAlt(localctx, 23)\n                self.state = 2016\n                self.lw_u_erri_instruction()\n                pass\n\n            elif la_ == 24:\n                self.enterOuterAlt(localctx, 24)\n                self.state = 2017\n                self.sb_erii_instruction()\n                pass\n\n            elif la_ == 25:\n                self.enterOuterAlt(localctx, 25)\n                self.state = 2018\n                self.sb_erir_instruction()\n                pass\n\n            elif la_ == 26:\n                self.enterOuterAlt(localctx, 26)\n                self.state = 2019\n                self.sb_id_rii_instruction()\n                pass\n\n            elif la_ == 27:\n                self.enterOuterAlt(localctx, 27)\n                self.state = 2020\n                self.sb_id_ri_instruction()\n                pass\n\n            elif la_ == 28:\n                self.enterOuterAlt(localctx, 28)\n                self.state = 2021\n                self.sd_erii_instruction()\n                pass\n\n            elif la_ == 29:\n                self.enterOuterAlt(localctx, 29)\n                self.state = 2022\n                self.sd_erid_instruction()\n                pass\n\n            elif la_ == 30:\n                self.enterOuterAlt(localctx, 30)\n                self.state = 2023\n                self.sd_id_rii_instruction()\n                pass\n\n            elif la_ == 31:\n                self.enterOuterAlt(localctx, 31)\n                self.state = 2024\n                self.sd_id_ri_instruction()\n                pass\n\n            elif la_ == 32:\n                self.enterOuterAlt(localctx, 32)\n                self.state = 2025\n                self.sh_erii_instruction()\n                pass\n\n            elif la_ == 33:\n                self.enterOuterAlt(localctx, 33)\n                self.state = 2026\n                self.sh_erir_instruction()\n                pass\n\n            elif la_ == 34:\n                self.enterOuterAlt(localctx, 34)\n                self.state = 2027\n                self.sh_id_rii_instruction()\n                pass\n\n            elif la_ == 35:\n                self.enterOuterAlt(localctx, 35)\n                self.state = 2028\n                self.sh_id_ri_instruction()\n                pass\n\n            elif la_ == 36:\n                self.enterOuterAlt(localctx, 36)\n                self.state = 2029\n                self.sw_erii_instruction()\n                pass\n\n            elif la_ == 37:\n                self.enterOuterAlt(localctx, 37)\n                self.state = 2030\n                self.sw_erir_instruction()\n                pass\n\n            elif la_ == 38:\n                self.enterOuterAlt(localctx, 38)\n                self.state = 2031\n                self.sw_id_rii_instruction()\n                pass\n\n            elif la_ == 39:\n                self.enterOuterAlt(localctx, 39)\n                self.state = 2032\n                self.sw_id_ri_instruction()\n                pass\n\n\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Div_step_drdici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def DIV_STEP(self):\n            return self.getToken(assemblyParser.DIV_STEP, 0)\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_div_step_drdici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterDiv_step_drdici_instruction\" ):\n                listener.enterDiv_step_drdici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitDiv_step_drdici_instruction\" ):\n                listener.exitDiv_step_drdici_instruction(self)\n\n\n\n\n    def div_step_drdici_instruction(self):\n\n        localctx = assemblyParser.Div_step_drdici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 368, self.RULE_div_step_drdici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2035\n            self.match(assemblyParser.DIV_STEP)\n            self.state = 2036\n            self.match(assemblyParser.T__3)\n            self.state = 2037\n            self.match(assemblyParser.PairRegister)\n            self.state = 2038\n            self.match(assemblyParser.T__3)\n            self.state = 2039\n            self.src_register()\n            self.state = 2040\n            self.match(assemblyParser.T__3)\n            self.state = 2041\n            self.match(assemblyParser.PairRegister)\n            self.state = 2042\n            self.match(assemblyParser.T__3)\n            self.state = 2043\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Mul_step_drdici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MUL_STEP(self):\n            return self.getToken(assemblyParser.MUL_STEP, 0)\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_mul_step_drdici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMul_step_drdici_instruction\" ):\n                listener.enterMul_step_drdici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMul_step_drdici_instruction\" ):\n                listener.exitMul_step_drdici_instruction(self)\n\n\n\n\n    def mul_step_drdici_instruction(self):\n\n        localctx = assemblyParser.Mul_step_drdici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 370, self.RULE_mul_step_drdici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2045\n            self.match(assemblyParser.MUL_STEP)\n            self.state = 2046\n            self.match(assemblyParser.T__3)\n            self.state = 2047\n            self.match(assemblyParser.PairRegister)\n            self.state = 2048\n            self.match(assemblyParser.T__3)\n            self.state = 2049\n            self.src_register()\n            self.state = 2050\n            self.match(assemblyParser.T__3)\n            self.state = 2051\n            self.match(assemblyParser.PairRegister)\n            self.state = 2052\n            self.match(assemblyParser.T__3)\n            self.state = 2053\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Boot_rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def BOOT(self):\n            return self.getToken(assemblyParser.BOOT, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_boot_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterBoot_rici_instruction\" ):\n                listener.enterBoot_rici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitBoot_rici_instruction\" ):\n                listener.exitBoot_rici_instruction(self)\n\n\n\n\n    def boot_rici_instruction(self):\n\n        localctx = assemblyParser.Boot_rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 372, self.RULE_boot_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2055\n            self.match(assemblyParser.BOOT)\n            self.state = 2056\n            self.match(assemblyParser.T__3)\n            self.state = 2057\n            self.src_register()\n            self.state = 2058\n            self.match(assemblyParser.T__3)\n            self.state = 2059\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Resume_rici_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def RESUME(self):\n            return self.getToken(assemblyParser.RESUME, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_resume_rici_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterResume_rici_instruction\" ):\n                listener.enterResume_rici_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitResume_rici_instruction\" ):\n                listener.exitResume_rici_instruction(self)\n\n\n\n\n    def resume_rici_instruction(self):\n\n        localctx = assemblyParser.Resume_rici_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 374, self.RULE_resume_rici_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2061\n            self.match(assemblyParser.RESUME)\n            self.state = 2062\n            self.match(assemblyParser.T__3)\n            self.state = 2063\n            self.src_register()\n            self.state = 2064\n            self.match(assemblyParser.T__3)\n            self.state = 2065\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Stop_ci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def STOP(self):\n            return self.getToken(assemblyParser.STOP, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_stop_ci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterStop_ci_instruction\" ):\n                listener.enterStop_ci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitStop_ci_instruction\" ):\n                listener.exitStop_ci_instruction(self)\n\n\n\n\n    def stop_ci_instruction(self):\n\n        localctx = assemblyParser.Stop_ci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 376, self.RULE_stop_ci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2067\n            self.match(assemblyParser.STOP)\n            self.state = 2068\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Call_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CALL(self):\n            return self.getToken(assemblyParser.CALL, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_call_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCall_ri_instruction\" ):\n                listener.enterCall_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCall_ri_instruction\" ):\n                listener.exitCall_ri_instruction(self)\n\n\n\n\n    def call_ri_instruction(self):\n\n        localctx = assemblyParser.Call_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 378, self.RULE_call_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2070\n            self.match(assemblyParser.CALL)\n            self.state = 2071\n            self.match(assemblyParser.T__3)\n            self.state = 2072\n            self.match(assemblyParser.GPRegister)\n            self.state = 2073\n            self.match(assemblyParser.T__3)\n            self.state = 2074\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Call_rr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def CALL(self):\n            return self.getToken(assemblyParser.CALL, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_call_rr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterCall_rr_instruction\" ):\n                listener.enterCall_rr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitCall_rr_instruction\" ):\n                listener.exitCall_rr_instruction(self)\n\n\n\n\n    def call_rr_instruction(self):\n\n        localctx = assemblyParser.Call_rr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 380, self.RULE_call_rr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2076\n            self.match(assemblyParser.CALL)\n            self.state = 2077\n            self.match(assemblyParser.T__3)\n            self.state = 2078\n            self.match(assemblyParser.GPRegister)\n            self.state = 2079\n            self.match(assemblyParser.T__3)\n            self.state = 2080\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Bkp_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def BKP(self):\n            return self.getToken(assemblyParser.BKP, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_bkp_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterBkp_instruction\" ):\n                listener.enterBkp_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitBkp_instruction\" ):\n                listener.exitBkp_instruction(self)\n\n\n\n\n    def bkp_instruction(self):\n\n        localctx = assemblyParser.Bkp_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 382, self.RULE_bkp_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2082\n            self.match(assemblyParser.BKP)\n            self.state = 2083\n            self.match(assemblyParser.T__3)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Movd_ddci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def MOVD(self):\n            return self.getToken(assemblyParser.MOVD, 0)\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_movd_ddci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterMovd_ddci_instruction\" ):\n                listener.enterMovd_ddci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitMovd_ddci_instruction\" ):\n                listener.exitMovd_ddci_instruction(self)\n\n\n\n\n    def movd_ddci_instruction(self):\n\n        localctx = assemblyParser.Movd_ddci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 384, self.RULE_movd_ddci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2085\n            self.match(assemblyParser.MOVD)\n            self.state = 2086\n            self.match(assemblyParser.T__3)\n            self.state = 2087\n            self.match(assemblyParser.PairRegister)\n            self.state = 2088\n            self.match(assemblyParser.T__3)\n            self.state = 2089\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Swapd_ddci_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SWAPD(self):\n            return self.getToken(assemblyParser.SWAPD, 0)\n\n        def PairRegister(self, i:int=None):\n            if i is None:\n                return self.getTokens(assemblyParser.PairRegister)\n            else:\n                return self.getToken(assemblyParser.PairRegister, i)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_swapd_ddci_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSwapd_ddci_instruction\" ):\n                listener.enterSwapd_ddci_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSwapd_ddci_instruction\" ):\n                listener.exitSwapd_ddci_instruction(self)\n\n\n\n\n    def swapd_ddci_instruction(self):\n\n        localctx = assemblyParser.Swapd_ddci_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 386, self.RULE_swapd_ddci_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2091\n            self.match(assemblyParser.SWAPD)\n            self.state = 2092\n            self.match(assemblyParser.T__3)\n            self.state = 2093\n            self.match(assemblyParser.PairRegister)\n            self.state = 2094\n            self.match(assemblyParser.T__3)\n            self.state = 2095\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Time_cfg_zr_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def TIME_CFG(self):\n            return self.getToken(assemblyParser.TIME_CFG, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_time_cfg_zr_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterTime_cfg_zr_instruction\" ):\n                listener.enterTime_cfg_zr_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitTime_cfg_zr_instruction\" ):\n                listener.exitTime_cfg_zr_instruction(self)\n\n\n\n\n    def time_cfg_zr_instruction(self):\n\n        localctx = assemblyParser.Time_cfg_zr_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 388, self.RULE_time_cfg_zr_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2097\n            self.match(assemblyParser.TIME_CFG)\n            self.state = 2098\n            self.match(assemblyParser.T__3)\n            self.state = 2099\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lbs_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LBS(self):\n            return self.getToken(assemblyParser.LBS, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lbs_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLbs_erri_instruction\" ):\n                listener.enterLbs_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLbs_erri_instruction\" ):\n                listener.exitLbs_erri_instruction(self)\n\n\n\n\n    def lbs_erri_instruction(self):\n\n        localctx = assemblyParser.Lbs_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 390, self.RULE_lbs_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2101\n            self.match(assemblyParser.LBS)\n            self.state = 2102\n            self.match(assemblyParser.T__3)\n            self.state = 2103\n            self.match(assemblyParser.GPRegister)\n            self.state = 2104\n            self.match(assemblyParser.T__3)\n            self.state = 2105\n            self.src_register()\n            self.state = 2106\n            self.match(assemblyParser.T__3)\n            self.state = 2107\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lbs_s_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LBS(self):\n            return self.getToken(assemblyParser.LBS, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lbs_s_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLbs_s_erri_instruction\" ):\n                listener.enterLbs_s_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLbs_s_erri_instruction\" ):\n                listener.exitLbs_s_erri_instruction(self)\n\n\n\n\n    def lbs_s_erri_instruction(self):\n\n        localctx = assemblyParser.Lbs_s_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 392, self.RULE_lbs_s_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2109\n            self.match(assemblyParser.LBS)\n            self.state = 2110\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 2111\n            self.match(assemblyParser.T__3)\n            self.state = 2112\n            self.match(assemblyParser.PairRegister)\n            self.state = 2113\n            self.match(assemblyParser.T__3)\n            self.state = 2114\n            self.src_register()\n            self.state = 2115\n            self.match(assemblyParser.T__3)\n            self.state = 2116\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lbu_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LBU(self):\n            return self.getToken(assemblyParser.LBU, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lbu_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLbu_erri_instruction\" ):\n                listener.enterLbu_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLbu_erri_instruction\" ):\n                listener.exitLbu_erri_instruction(self)\n\n\n\n\n    def lbu_erri_instruction(self):\n\n        localctx = assemblyParser.Lbu_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 394, self.RULE_lbu_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2118\n            self.match(assemblyParser.LBU)\n            self.state = 2119\n            self.match(assemblyParser.T__3)\n            self.state = 2120\n            self.match(assemblyParser.GPRegister)\n            self.state = 2121\n            self.match(assemblyParser.T__3)\n            self.state = 2122\n            self.src_register()\n            self.state = 2123\n            self.match(assemblyParser.T__3)\n            self.state = 2124\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lbu_u_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LBU(self):\n            return self.getToken(assemblyParser.LBU, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lbu_u_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLbu_u_erri_instruction\" ):\n                listener.enterLbu_u_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLbu_u_erri_instruction\" ):\n                listener.exitLbu_u_erri_instruction(self)\n\n\n\n\n    def lbu_u_erri_instruction(self):\n\n        localctx = assemblyParser.Lbu_u_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 396, self.RULE_lbu_u_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2126\n            self.match(assemblyParser.LBU)\n            self.state = 2127\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 2128\n            self.match(assemblyParser.T__3)\n            self.state = 2129\n            self.match(assemblyParser.PairRegister)\n            self.state = 2130\n            self.match(assemblyParser.T__3)\n            self.state = 2131\n            self.src_register()\n            self.state = 2132\n            self.match(assemblyParser.T__3)\n            self.state = 2133\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Ld_edri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LD(self):\n            return self.getToken(assemblyParser.LD, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_ld_edri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLd_edri_instruction\" ):\n                listener.enterLd_edri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLd_edri_instruction\" ):\n                listener.exitLd_edri_instruction(self)\n\n\n\n\n    def ld_edri_instruction(self):\n\n        localctx = assemblyParser.Ld_edri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 398, self.RULE_ld_edri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2135\n            self.match(assemblyParser.LD)\n            self.state = 2136\n            self.match(assemblyParser.T__3)\n            self.state = 2137\n            self.match(assemblyParser.PairRegister)\n            self.state = 2138\n            self.match(assemblyParser.T__3)\n            self.state = 2139\n            self.src_register()\n            self.state = 2140\n            self.match(assemblyParser.T__3)\n            self.state = 2141\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lhs_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LHS(self):\n            return self.getToken(assemblyParser.LHS, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lhs_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLhs_erri_instruction\" ):\n                listener.enterLhs_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLhs_erri_instruction\" ):\n                listener.exitLhs_erri_instruction(self)\n\n\n\n\n    def lhs_erri_instruction(self):\n\n        localctx = assemblyParser.Lhs_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 400, self.RULE_lhs_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2143\n            self.match(assemblyParser.LHS)\n            self.state = 2144\n            self.match(assemblyParser.T__3)\n            self.state = 2145\n            self.match(assemblyParser.GPRegister)\n            self.state = 2146\n            self.match(assemblyParser.T__3)\n            self.state = 2147\n            self.src_register()\n            self.state = 2148\n            self.match(assemblyParser.T__3)\n            self.state = 2149\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lhs_s_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LHS(self):\n            return self.getToken(assemblyParser.LHS, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lhs_s_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLhs_s_erri_instruction\" ):\n                listener.enterLhs_s_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLhs_s_erri_instruction\" ):\n                listener.exitLhs_s_erri_instruction(self)\n\n\n\n\n    def lhs_s_erri_instruction(self):\n\n        localctx = assemblyParser.Lhs_s_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 402, self.RULE_lhs_s_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2151\n            self.match(assemblyParser.LHS)\n            self.state = 2152\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 2153\n            self.match(assemblyParser.T__3)\n            self.state = 2154\n            self.match(assemblyParser.PairRegister)\n            self.state = 2155\n            self.match(assemblyParser.T__3)\n            self.state = 2156\n            self.src_register()\n            self.state = 2157\n            self.match(assemblyParser.T__3)\n            self.state = 2158\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lhu_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LHU(self):\n            return self.getToken(assemblyParser.LHU, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lhu_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLhu_erri_instruction\" ):\n                listener.enterLhu_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLhu_erri_instruction\" ):\n                listener.exitLhu_erri_instruction(self)\n\n\n\n\n    def lhu_erri_instruction(self):\n\n        localctx = assemblyParser.Lhu_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 404, self.RULE_lhu_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2160\n            self.match(assemblyParser.LHU)\n            self.state = 2161\n            self.match(assemblyParser.T__3)\n            self.state = 2162\n            self.match(assemblyParser.GPRegister)\n            self.state = 2163\n            self.match(assemblyParser.T__3)\n            self.state = 2164\n            self.src_register()\n            self.state = 2165\n            self.match(assemblyParser.T__3)\n            self.state = 2166\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lhu_u_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LHU(self):\n            return self.getToken(assemblyParser.LHU, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lhu_u_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLhu_u_erri_instruction\" ):\n                listener.enterLhu_u_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLhu_u_erri_instruction\" ):\n                listener.exitLhu_u_erri_instruction(self)\n\n\n\n\n    def lhu_u_erri_instruction(self):\n\n        localctx = assemblyParser.Lhu_u_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 406, self.RULE_lhu_u_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2168\n            self.match(assemblyParser.LHU)\n            self.state = 2169\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 2170\n            self.match(assemblyParser.T__3)\n            self.state = 2171\n            self.match(assemblyParser.PairRegister)\n            self.state = 2172\n            self.match(assemblyParser.T__3)\n            self.state = 2173\n            self.src_register()\n            self.state = 2174\n            self.match(assemblyParser.T__3)\n            self.state = 2175\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lw_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LW(self):\n            return self.getToken(assemblyParser.LW, 0)\n\n        def GPRegister(self):\n            return self.getToken(assemblyParser.GPRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lw_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLw_erri_instruction\" ):\n                listener.enterLw_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLw_erri_instruction\" ):\n                listener.exitLw_erri_instruction(self)\n\n\n\n\n    def lw_erri_instruction(self):\n\n        localctx = assemblyParser.Lw_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 408, self.RULE_lw_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2177\n            self.match(assemblyParser.LW)\n            self.state = 2178\n            self.match(assemblyParser.T__3)\n            self.state = 2179\n            self.match(assemblyParser.GPRegister)\n            self.state = 2180\n            self.match(assemblyParser.T__3)\n            self.state = 2181\n            self.src_register()\n            self.state = 2182\n            self.match(assemblyParser.T__3)\n            self.state = 2183\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lw_s_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LW(self):\n            return self.getToken(assemblyParser.LW, 0)\n\n        def S_SUFFIX(self):\n            return self.getToken(assemblyParser.S_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lw_s_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLw_s_erri_instruction\" ):\n                listener.enterLw_s_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLw_s_erri_instruction\" ):\n                listener.exitLw_s_erri_instruction(self)\n\n\n\n\n    def lw_s_erri_instruction(self):\n\n        localctx = assemblyParser.Lw_s_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 410, self.RULE_lw_s_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2185\n            self.match(assemblyParser.LW)\n            self.state = 2186\n            self.match(assemblyParser.S_SUFFIX)\n            self.state = 2187\n            self.match(assemblyParser.T__3)\n            self.state = 2188\n            self.match(assemblyParser.PairRegister)\n            self.state = 2189\n            self.match(assemblyParser.T__3)\n            self.state = 2190\n            self.src_register()\n            self.state = 2191\n            self.match(assemblyParser.T__3)\n            self.state = 2192\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Lw_u_erri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def LW(self):\n            return self.getToken(assemblyParser.LW, 0)\n\n        def U_SUFFIX(self):\n            return self.getToken(assemblyParser.U_SUFFIX, 0)\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_lw_u_erri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLw_u_erri_instruction\" ):\n                listener.enterLw_u_erri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLw_u_erri_instruction\" ):\n                listener.exitLw_u_erri_instruction(self)\n\n\n\n\n    def lw_u_erri_instruction(self):\n\n        localctx = assemblyParser.Lw_u_erri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 412, self.RULE_lw_u_erri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2194\n            self.match(assemblyParser.LW)\n            self.state = 2195\n            self.match(assemblyParser.U_SUFFIX)\n            self.state = 2196\n            self.match(assemblyParser.T__3)\n            self.state = 2197\n            self.match(assemblyParser.PairRegister)\n            self.state = 2198\n            self.match(assemblyParser.T__3)\n            self.state = 2199\n            self.src_register()\n            self.state = 2200\n            self.match(assemblyParser.T__3)\n            self.state = 2201\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sb_erii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SB(self):\n            return self.getToken(assemblyParser.SB, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sb_erii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSb_erii_instruction\" ):\n                listener.enterSb_erii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSb_erii_instruction\" ):\n                listener.exitSb_erii_instruction(self)\n\n\n\n\n    def sb_erii_instruction(self):\n\n        localctx = assemblyParser.Sb_erii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 414, self.RULE_sb_erii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2203\n            self.match(assemblyParser.SB)\n            self.state = 2204\n            self.match(assemblyParser.T__3)\n            self.state = 2205\n            self.src_register()\n            self.state = 2206\n            self.match(assemblyParser.T__3)\n            self.state = 2207\n            self.number()\n            self.state = 2208\n            self.match(assemblyParser.T__3)\n            self.state = 2209\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sb_erir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SB(self):\n            return self.getToken(assemblyParser.SB, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sb_erir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSb_erir_instruction\" ):\n                listener.enterSb_erir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSb_erir_instruction\" ):\n                listener.exitSb_erir_instruction(self)\n\n\n\n\n    def sb_erir_instruction(self):\n\n        localctx = assemblyParser.Sb_erir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 416, self.RULE_sb_erir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2211\n            self.match(assemblyParser.SB)\n            self.state = 2212\n            self.match(assemblyParser.T__3)\n            self.state = 2213\n            self.src_register()\n            self.state = 2214\n            self.match(assemblyParser.T__3)\n            self.state = 2215\n            self.program_counter()\n            self.state = 2216\n            self.match(assemblyParser.T__3)\n            self.state = 2217\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sb_id_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SB(self):\n            return self.getToken(assemblyParser.SB, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sb_id_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSb_id_rii_instruction\" ):\n                listener.enterSb_id_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSb_id_rii_instruction\" ):\n                listener.exitSb_id_rii_instruction(self)\n\n\n\n\n    def sb_id_rii_instruction(self):\n\n        localctx = assemblyParser.Sb_id_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 418, self.RULE_sb_id_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2219\n            self.match(assemblyParser.SB)\n            self.state = 2220\n            self.match(assemblyParser.T__3)\n            self.state = 2221\n            self.src_register()\n            self.state = 2222\n            self.match(assemblyParser.T__3)\n            self.state = 2223\n            self.number()\n            self.state = 2224\n            self.match(assemblyParser.T__3)\n            self.state = 2225\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sb_id_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SB(self):\n            return self.getToken(assemblyParser.SB, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sb_id_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSb_id_ri_instruction\" ):\n                listener.enterSb_id_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSb_id_ri_instruction\" ):\n                listener.exitSb_id_ri_instruction(self)\n\n\n\n\n    def sb_id_ri_instruction(self):\n\n        localctx = assemblyParser.Sb_id_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 420, self.RULE_sb_id_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2227\n            self.match(assemblyParser.SB)\n            self.state = 2228\n            self.match(assemblyParser.T__3)\n            self.state = 2229\n            self.src_register()\n            self.state = 2230\n            self.match(assemblyParser.T__3)\n            self.state = 2231\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sd_erii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SD(self):\n            return self.getToken(assemblyParser.SD, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Program_counterContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Program_counterContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sd_erii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSd_erii_instruction\" ):\n                listener.enterSd_erii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSd_erii_instruction\" ):\n                listener.exitSd_erii_instruction(self)\n\n\n\n\n    def sd_erii_instruction(self):\n\n        localctx = assemblyParser.Sd_erii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 422, self.RULE_sd_erii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2233\n            self.match(assemblyParser.SD)\n            self.state = 2234\n            self.match(assemblyParser.T__3)\n            self.state = 2235\n            self.src_register()\n            self.state = 2236\n            self.match(assemblyParser.T__3)\n            self.state = 2237\n            self.program_counter()\n            self.state = 2238\n            self.match(assemblyParser.T__3)\n            self.state = 2239\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sd_erid_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SD(self):\n            return self.getToken(assemblyParser.SD, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def PairRegister(self):\n            return self.getToken(assemblyParser.PairRegister, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sd_erid_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSd_erid_instruction\" ):\n                listener.enterSd_erid_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSd_erid_instruction\" ):\n                listener.exitSd_erid_instruction(self)\n\n\n\n\n    def sd_erid_instruction(self):\n\n        localctx = assemblyParser.Sd_erid_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 424, self.RULE_sd_erid_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2241\n            self.match(assemblyParser.SD)\n            self.state = 2242\n            self.match(assemblyParser.T__3)\n            self.state = 2243\n            self.src_register()\n            self.state = 2244\n            self.match(assemblyParser.T__3)\n            self.state = 2245\n            self.program_counter()\n            self.state = 2246\n            self.match(assemblyParser.T__3)\n            self.state = 2247\n            self.match(assemblyParser.PairRegister)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sd_id_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SD(self):\n            return self.getToken(assemblyParser.SD, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sd_id_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSd_id_rii_instruction\" ):\n                listener.enterSd_id_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSd_id_rii_instruction\" ):\n                listener.exitSd_id_rii_instruction(self)\n\n\n\n\n    def sd_id_rii_instruction(self):\n\n        localctx = assemblyParser.Sd_id_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 426, self.RULE_sd_id_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2249\n            self.match(assemblyParser.SD)\n            self.state = 2250\n            self.match(assemblyParser.T__3)\n            self.state = 2251\n            self.src_register()\n            self.state = 2252\n            self.match(assemblyParser.T__3)\n            self.state = 2253\n            self.number()\n            self.state = 2254\n            self.match(assemblyParser.T__3)\n            self.state = 2255\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sd_id_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SD(self):\n            return self.getToken(assemblyParser.SD, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sd_id_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSd_id_ri_instruction\" ):\n                listener.enterSd_id_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSd_id_ri_instruction\" ):\n                listener.exitSd_id_ri_instruction(self)\n\n\n\n\n    def sd_id_ri_instruction(self):\n\n        localctx = assemblyParser.Sd_id_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 428, self.RULE_sd_id_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2257\n            self.match(assemblyParser.SD)\n            self.state = 2258\n            self.match(assemblyParser.T__3)\n            self.state = 2259\n            self.src_register()\n            self.state = 2260\n            self.match(assemblyParser.T__3)\n            self.state = 2261\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sh_erii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SH(self):\n            return self.getToken(assemblyParser.SH, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sh_erii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSh_erii_instruction\" ):\n                listener.enterSh_erii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSh_erii_instruction\" ):\n                listener.exitSh_erii_instruction(self)\n\n\n\n\n    def sh_erii_instruction(self):\n\n        localctx = assemblyParser.Sh_erii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 430, self.RULE_sh_erii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2263\n            self.match(assemblyParser.SH)\n            self.state = 2264\n            self.match(assemblyParser.T__3)\n            self.state = 2265\n            self.src_register()\n            self.state = 2266\n            self.match(assemblyParser.T__3)\n            self.state = 2267\n            self.number()\n            self.state = 2268\n            self.match(assemblyParser.T__3)\n            self.state = 2269\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sh_erir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SH(self):\n            return self.getToken(assemblyParser.SH, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sh_erir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSh_erir_instruction\" ):\n                listener.enterSh_erir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSh_erir_instruction\" ):\n                listener.exitSh_erir_instruction(self)\n\n\n\n\n    def sh_erir_instruction(self):\n\n        localctx = assemblyParser.Sh_erir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 432, self.RULE_sh_erir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2271\n            self.match(assemblyParser.SH)\n            self.state = 2272\n            self.match(assemblyParser.T__3)\n            self.state = 2273\n            self.src_register()\n            self.state = 2274\n            self.match(assemblyParser.T__3)\n            self.state = 2275\n            self.program_counter()\n            self.state = 2276\n            self.match(assemblyParser.T__3)\n            self.state = 2277\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sh_id_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SH(self):\n            return self.getToken(assemblyParser.SH, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sh_id_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSh_id_rii_instruction\" ):\n                listener.enterSh_id_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSh_id_rii_instruction\" ):\n                listener.exitSh_id_rii_instruction(self)\n\n\n\n\n    def sh_id_rii_instruction(self):\n\n        localctx = assemblyParser.Sh_id_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 434, self.RULE_sh_id_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2279\n            self.match(assemblyParser.SH)\n            self.state = 2280\n            self.match(assemblyParser.T__3)\n            self.state = 2281\n            self.src_register()\n            self.state = 2282\n            self.match(assemblyParser.T__3)\n            self.state = 2283\n            self.number()\n            self.state = 2284\n            self.match(assemblyParser.T__3)\n            self.state = 2285\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sh_id_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SH(self):\n            return self.getToken(assemblyParser.SH, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sh_id_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSh_id_ri_instruction\" ):\n                listener.enterSh_id_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSh_id_ri_instruction\" ):\n                listener.exitSh_id_ri_instruction(self)\n\n\n\n\n    def sh_id_ri_instruction(self):\n\n        localctx = assemblyParser.Sh_id_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 436, self.RULE_sh_id_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2287\n            self.match(assemblyParser.SH)\n            self.state = 2288\n            self.match(assemblyParser.T__3)\n            self.state = 2289\n            self.src_register()\n            self.state = 2290\n            self.match(assemblyParser.T__3)\n            self.state = 2291\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sw_erii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SW(self):\n            return self.getToken(assemblyParser.SW, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sw_erii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSw_erii_instruction\" ):\n                listener.enterSw_erii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSw_erii_instruction\" ):\n                listener.exitSw_erii_instruction(self)\n\n\n\n\n    def sw_erii_instruction(self):\n\n        localctx = assemblyParser.Sw_erii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 438, self.RULE_sw_erii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2293\n            self.match(assemblyParser.SW)\n            self.state = 2294\n            self.match(assemblyParser.T__3)\n            self.state = 2295\n            self.src_register()\n            self.state = 2296\n            self.match(assemblyParser.T__3)\n            self.state = 2297\n            self.number()\n            self.state = 2298\n            self.match(assemblyParser.T__3)\n            self.state = 2299\n            self.program_counter()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sw_erir_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SW(self):\n            return self.getToken(assemblyParser.SW, 0)\n\n        def src_register(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.Src_registerContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.Src_registerContext,i)\n\n\n        def program_counter(self):\n            return self.getTypedRuleContext(assemblyParser.Program_counterContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sw_erir_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSw_erir_instruction\" ):\n                listener.enterSw_erir_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSw_erir_instruction\" ):\n                listener.exitSw_erir_instruction(self)\n\n\n\n\n    def sw_erir_instruction(self):\n\n        localctx = assemblyParser.Sw_erir_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 440, self.RULE_sw_erir_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2301\n            self.match(assemblyParser.SW)\n            self.state = 2302\n            self.match(assemblyParser.T__3)\n            self.state = 2303\n            self.src_register()\n            self.state = 2304\n            self.match(assemblyParser.T__3)\n            self.state = 2305\n            self.program_counter()\n            self.state = 2306\n            self.match(assemblyParser.T__3)\n            self.state = 2307\n            self.src_register()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sw_id_rii_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SW(self):\n            return self.getToken(assemblyParser.SW, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self, i:int=None):\n            if i is None:\n                return self.getTypedRuleContexts(assemblyParser.NumberContext)\n            else:\n                return self.getTypedRuleContext(assemblyParser.NumberContext,i)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sw_id_rii_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSw_id_rii_instruction\" ):\n                listener.enterSw_id_rii_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSw_id_rii_instruction\" ):\n                listener.exitSw_id_rii_instruction(self)\n\n\n\n\n    def sw_id_rii_instruction(self):\n\n        localctx = assemblyParser.Sw_id_rii_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 442, self.RULE_sw_id_rii_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2309\n            self.match(assemblyParser.SW)\n            self.state = 2310\n            self.match(assemblyParser.T__3)\n            self.state = 2311\n            self.src_register()\n            self.state = 2312\n            self.match(assemblyParser.T__3)\n            self.state = 2313\n            self.number()\n            self.state = 2314\n            self.match(assemblyParser.T__3)\n            self.state = 2315\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class Sw_id_ri_instructionContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def SW(self):\n            return self.getToken(assemblyParser.SW, 0)\n\n        def src_register(self):\n            return self.getTypedRuleContext(assemblyParser.Src_registerContext,0)\n\n\n        def number(self):\n            return self.getTypedRuleContext(assemblyParser.NumberContext,0)\n\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_sw_id_ri_instruction\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterSw_id_ri_instruction\" ):\n                listener.enterSw_id_ri_instruction(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitSw_id_ri_instruction\" ):\n                listener.exitSw_id_ri_instruction(self)\n\n\n\n\n    def sw_id_ri_instruction(self):\n\n        localctx = assemblyParser.Sw_id_ri_instructionContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 444, self.RULE_sw_id_ri_instruction)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2317\n            self.match(assemblyParser.SW)\n            self.state = 2318\n            self.match(assemblyParser.T__3)\n            self.state = 2319\n            self.src_register()\n            self.state = 2320\n            self.match(assemblyParser.T__3)\n            self.state = 2321\n            self.number()\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n    class LabelContext(ParserRuleContext):\n        __slots__ = 'parser'\n\n        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):\n            super().__init__(parent, invokingState)\n            self.parser = parser\n\n        def Identifier(self):\n            return self.getToken(assemblyParser.Identifier, 0)\n\n        def getRuleIndex(self):\n            return assemblyParser.RULE_label\n\n        def enterRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"enterLabel\" ):\n                listener.enterLabel(self)\n\n        def exitRule(self, listener:ParseTreeListener):\n            if hasattr( listener, \"exitLabel\" ):\n                listener.exitLabel(self)\n\n\n\n\n    def label(self):\n\n        localctx = assemblyParser.LabelContext(self, self._ctx, self.state)\n        self.enterRule(localctx, 446, self.RULE_label)\n        try:\n            self.enterOuterAlt(localctx, 1)\n            self.state = 2323\n            self.match(assemblyParser.Identifier)\n            self.state = 2324\n            self.match(assemblyParser.T__4)\n        except RecognitionException as re:\n            localctx.exception = re\n            self._errHandler.reportError(self, re)\n            self._errHandler.recover(self, re)\n        finally:\n            self.exitRule()\n        return localctx\n\n\n\n\n\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/grammar_generator.py",
    "content": "from typing import List\n\nfrom util.docker_client import DockerClient\nfrom util.path_collector import PathCollector\n\n\nclass GrammarGenerator:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def generate() -> bool:\n        cd = f\"cd {GrammarGenerator._grammar_path_in_docker()}\"\n        antlr = f\"{GrammarGenerator._antlr()} -Dlanguage=Python3 {GrammarGenerator.grammar()}.g4\"\n\n        return DockerClient.run(GrammarGenerator._docker_image(), [cd, antlr])\n\n    @staticmethod\n    def clean() -> bool:\n        commands = [f\"cd {GrammarGenerator._grammar_path_in_docker()}\"]\n        for filename in GrammarGenerator.generated_filenames():\n            commands.append(f\"rm -f {filename}\")\n        return DockerClient.run(\"compiler\", commands)\n\n    @staticmethod\n    def grammar() -> str:\n        return \"assembly\"\n\n    @staticmethod\n    def generated_filenames() -> List[str]:\n        return [\n            f\"{GrammarGenerator.grammar()}.interp\",\n            f\"{GrammarGenerator.grammar()}.tokens\",\n            f\"{GrammarGenerator.grammar()}Lexer.interp\",\n            f\"{GrammarGenerator.grammar()}Lexer.py\",\n            f\"{GrammarGenerator.grammar()}Lexer.tokens\",\n            f\"{GrammarGenerator.grammar()}Listener.py\",\n            f\"{GrammarGenerator.grammar()}Parser.py\",\n        ]\n\n    @staticmethod\n    def _grammar_path_in_docker() -> str:\n        return f\"{PathCollector.src_path_in_docker()}/parser_/grammar\"\n\n    @staticmethod\n    def _docker_image() -> str:\n        return \"parser\"\n\n    @staticmethod\n    def _class_path() -> str:\n        return \"/root/antlr-4.9.2-complete.jar:$CLASSPATH\"\n\n    @staticmethod\n    def _antlr() -> str:\n        return f'java -Xmx500M -cp \"{GrammarGenerator._class_path()}\" org.antlr.v4.Tool'\n\n    @staticmethod\n    def _grun() -> str:\n        return f'java -Xmx500M -cp \"{GrammarGenerator._class_path()}\" org.antlr.v4.gui.TestRig'\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/parser_/parser.py",
    "content": "from typing import Set\n\nimport antlr4\n\nfrom parser_.grammar.assemblyLexer import assemblyLexer\nfrom parser_.grammar.assemblyParser import assemblyParser\n\n\nclass Parser:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def parse_lines(lines: str) -> assemblyParser.DocumentContext:\n        input_stream = antlr4.InputStream(lines)\n        lexer = assemblyLexer(input_stream)\n        common_token_stream = antlr4.CommonTokenStream(lexer)\n        parser = assemblyParser(common_token_stream)\n        return parser.document()\n\n    @staticmethod\n    def preprocess(lines: str) -> str:\n        lines = Parser._preprocess_directive(lines)\n        lines = Parser._preprocess_instruction(lines)\n        lines = Parser._preprocess_section(lines)\n        lines = Parser._preprocess_operator(lines)\n        return lines\n\n    @staticmethod\n    def _preprocess_directive(lines: str) -> str:\n        for directive in Parser._directives():\n            lines = lines.replace(f\".{directive} \", f\"${directive}, \")\n            lines = lines.replace(f\".{directive}\\t\", f\"${directive},\\t\")\n            lines = lines.replace(f\".{directive}\\n\", f\"${directive},\\n\")\n        return lines\n\n    @staticmethod\n    def _preprocess_instruction(lines: str) -> str:\n        for op_code in Parser._op_codes():\n            for suffix in Parser._suffixes():\n                lines = lines.replace(f\"\\t{op_code}{suffix} \", f\"\\t${op_code} {suffix}, \")\n                lines = lines.replace(f\"\\t{op_code}{suffix}\\t\", f\"\\t${op_code} {suffix},\\t\")\n                lines = lines.replace(f\"\\t{op_code}{suffix}\\n\", f\"\\t${op_code} {suffix},\\n\")\n        return lines\n\n    @staticmethod\n    def _preprocess_section(lines: str) -> str:\n        for section_name in Parser._section_names():\n            lines = lines.replace(f\".{section_name}\", f\"%{section_name}\")\n            lines = lines.replace(f\"%{section_name}.\", f\"%{section_name}, \")\n        return lines\n\n    @staticmethod\n    def _preprocess_operator(lines: str) -> str:\n        for operator in Parser._operators():\n            lines = lines.replace(f\"{operator}\", f\" {operator} \")\n        return lines\n\n    @staticmethod\n    def _directives() -> Set[str]:\n        return {\n            \"addrsig\",\n            \"addrsig_sym\",\n            \"ascii\",\n            \"asciz\",\n            \"bss\",\n            \"byte\",\n            \"cfi_def_cfa_offset\",\n            \"cfi_endproc\",\n            \"cfi_offset\",\n            \"cfi_sections\",\n            \"cfi_startproc\",\n            \"file\",\n            \"globl\",\n            \"loc\",\n            \"long\",\n            \"p2align\",\n            \"quad\",\n            \"section\",\n            \"set\",\n            \"short\",\n            \"size\",\n            \"text\",\n            \"type\",\n            \"weak\",\n            \"zero\",\n        }\n\n    @staticmethod\n    def _op_codes() -> Set[str]:\n        return {\n            \"acquire\",\n            \"release\",\n            \"add\",\n            \"addc\",\n            \"and\",\n            \"andn\",\n            \"asr\",\n            \"cao\",\n            \"clo\",\n            \"cls\",\n            \"clz\",\n            \"cmpb4\",\n            \"div_step\",\n            \"extsb\",\n            \"extsh\",\n            \"extub\",\n            \"extuh\",\n            \"lsl\",\n            \"lsl1\",\n            \"lsl1x\",\n            \"lsl_add\",\n            \"lsl_sub\",\n            \"lslx\",\n            \"lsr\",\n            \"lsr1\",\n            \"lsr1x\",\n            \"lsr_add\",\n            \"lsrx\",\n            \"mul_sh_sh\",\n            \"mul_sh_sl\",\n            \"mul_sh_uh\",\n            \"mul_sh_ul\",\n            \"mul_sl_sh\",\n            \"mul_sl_sl\",\n            \"mul_sl_uh\",\n            \"mul_sl_ul\",\n            \"mul_step\",\n            \"mul_uh_uh\",\n            \"mul_uh_ul\",\n            \"mul_ul_uh\",\n            \"mul_ul_ul\",\n            \"nand\",\n            \"nor\",\n            \"nxor\",\n            \"or\",\n            \"orn\",\n            \"rol\",\n            \"rol_add\",\n            \"ror\",\n            \"rsub\",\n            \"rsubc\",\n            \"sub\",\n            \"subc\",\n            \"xor\",\n            \"boot\",\n            \"resume\",\n            \"stop\",\n            \"call\",\n            \"fault\",\n            \"nop\",\n            \"sats\",\n            \"hash\",\n            \"movd\",\n            \"swapd\",\n            \"time\",\n            \"time_cfg\",\n            \"lbs\",\n            \"lbu\",\n            \"ld\",\n            \"lhs\",\n            \"lhu\",\n            \"lw\",\n            \"sb\",\n            \"sb_id\",\n            \"sd\",\n            \"sd_id\",\n            \"sh\",\n            \"sh_id\",\n            \"sw\",\n            \"sw_id\",\n            \"ldma\",\n            \"ldmai\",\n            \"sdma\",\n            \"adds\",\n            \"move\",\n            \"neg\",\n            \"subs\",\n            \"jump\",\n            \"jeq\",\n            \"jneq\",\n            \"jz\",\n            \"jnz\",\n            \"jltu\",\n            \"jgtu\",\n            \"jleu\",\n            \"jgeu\",\n            \"jlts\",\n            \"jgts\",\n            \"jles\",\n            \"jges\",\n            \"not\",\n            \"bkp\",\n            \"lbss\",\n            \"lbus\",\n            \"lds\",\n            \"lhss\",\n            \"lhus\",\n            \"lws\",\n            \"sbs\",\n            \"sds\",\n            \"shs\",\n            \"sws\",\n        }\n\n    @staticmethod\n    def _suffixes() -> Set[str]:\n        return {\"\", \".s\", \".u\"}\n\n    @staticmethod\n    def _section_names() -> Set[str]:\n        return {\n            \"atomic\",\n            \"bss\",\n            \"data\",\n            \"debug_abbrev\",\n            \"debug_frame\",\n            \"debug_info\",\n            \"debug_line\",\n            \"debug_loc\",\n            \"debug_ranges\",\n            \"debug_str\",\n            \"dpu_host\",\n            \"mram\",\n            \"rodata\",\n            \"stack_sizes\",\n            \"text\",\n        }\n\n    @staticmethod\n    def _operators() -> Set[str]:\n        return {\"+\", \"-\"}\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/util/config_loader.py",
    "content": "class ConfigLoader:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def atomic_address_width() -> int:\n        return 32\n\n    @staticmethod\n    def atomic_data_width() -> int:\n        return 32\n\n    @staticmethod\n    def atomic_offset() -> int:\n        return 0\n\n    @staticmethod\n    def atomic_size() -> int:\n        return 256\n\n    @staticmethod\n    def iram_address_width() -> int:\n        return 32\n\n    @staticmethod\n    def iram_data_width() -> int:\n        return 96\n\n    @staticmethod\n    def iram_offset() -> int:\n        return 384 * 1024\n\n    @staticmethod\n    def iram_size() -> int:\n        return 48 * 1024\n\n    @staticmethod\n    def wram_address_width() -> int:\n        return 32\n\n    @staticmethod\n    def wram_data_width() -> int:\n        return 32\n\n    @staticmethod\n    def wram_offset() -> int:\n        return 512\n\n    @staticmethod\n    def wram_size() -> int:\n        return 128 * 1024\n\n    @staticmethod\n    def stack_size() -> int:\n        return 2 * 1024\n\n    @staticmethod\n    def heap_size() -> int:\n        return 4 * 1024\n\n    @staticmethod\n    def mram_address_width() -> int:\n        return 32\n\n    @staticmethod\n    def mram_data_width() -> int:\n        return 32\n\n    @staticmethod\n    def mram_offset() -> int:\n        return 512 * 1024\n\n    @staticmethod\n    def mram_size() -> int:\n        return 64 * 1024 * 1024\n\n    @staticmethod\n    def num_gp_registers() -> int:\n        return 24\n\n    @staticmethod\n    def max_num_tasklets() -> int:\n        return 24\n\n    @staticmethod\n    def min_access_granularity() -> int:\n        return 8\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/util/docker_client.py",
    "content": "import os\nimport subprocess\nfrom typing import List\n\nfrom util.path_collector import PathCollector\n\n\nclass DockerClient:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def repo_name() -> str:\n        return \"bongjoonhyun\"\n\n    @staticmethod\n    def build(image: str) -> bool:\n        result = subprocess.run(\n            [\n                \"docker\",\n                \"build\",\n                \"-t\",\n                f\"{DockerClient.repo_name()}/{image}\",\n                \"-f\",\n                f\"{DockerClient._dockerfile(image)}\",\n                \".\",\n            ],\n            capture_output=True,\n            text=True,\n            check=True,\n        )\n\n        if result.stderr != \"\":\n            print(result.stderr)\n\n        return result.stderr == \"\"\n\n    @staticmethod\n    def build_all() -> bool:\n        for dockerfile in DockerClient._dockerfiles_path():\n            if not DockerClient.build(DockerClient._image(dockerfile)):\n                return False\n        return True\n\n    @staticmethod\n    def run(image: str, commands: List[str]) -> bool:\n        DockerClient.build(image)\n\n        result = subprocess.run(\n            [\n                \"docker\",\n                \"run\",\n                \"--rm\",\n                \"-v\",\n                f\"{PathCollector().root_path_in_local()}:/root/{PathCollector().project_name()}\",\n                f\"{DockerClient.repo_name()}/{image}:latest\",\n                \"bash\",\n                \"-c\",\n                \" && \".join(commands),\n            ],\n            capture_output=True,\n            text=True,\n            check=True,\n        )\n\n        if result.stderr != \"\":\n            print(result.stderr)\n\n        return result.stderr == \"\"\n\n    @staticmethod\n    def _docker_path() -> str:\n        return os.path.join(PathCollector().root_path_in_local(), \"docker\")\n\n    @staticmethod\n    def _dockerfiles_path() -> List[str]:\n        return [os.path.join(DockerClient._docker_path(), f) for f in os.listdir(DockerClient._docker_path())]\n\n    @staticmethod\n    def _image(dockerfile: str) -> str:\n        return os.path.basename(dockerfile).split(\".\")[0]\n\n    @staticmethod\n    def _dockerfile(image: str) -> str:\n        return os.path.join(DockerClient._docker_path(), f\"{image}.dockerfile\")\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/util/param_loader.py",
    "content": "from abi.word.data_word import DataWord\nfrom util.config_loader import ConfigLoader\n\n\nclass ParamLoader:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def logic_frequency() -> int:\n        return 450\n\n    @staticmethod\n    def memory_frequency() -> int:\n        return 2666\n\n    @staticmethod\n    def num_pipeline_stages() -> int:\n        return 14\n\n    @staticmethod\n    def instruction_scheduling_policy() -> str:\n        return \"revolver\"\n\n    @staticmethod\n    def num_revolver_scheduling_cycles() -> int:\n        return 11\n\n    @staticmethod\n    def memory_scheduling_policy() -> str:\n        return \"FIFO\"\n\n    @staticmethod\n    def num_wordlines() -> int:\n        return 512\n\n    @staticmethod\n    def wordline_size() -> int:\n        assert ConfigLoader.mram_size() % ParamLoader.num_wordlines() == 0\n        wordline_size = ConfigLoader.mram_size() // ParamLoader.num_wordlines()\n        assert wordline_size % DataWord().size() == 0\n        return wordline_size\n\n    @staticmethod\n    def t_rcd() -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def t_ras() -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def t_cl() -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def t_cwl() -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def t_bl() -> int:\n        raise NotImplementedError\n\n    @staticmethod\n    def t_rp() -> int:\n        raise NotImplementedError\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/src/util/path_collector.py",
    "content": "import os\nfrom pathlib import Path\n\n\nclass PathCollector:\n    def __init__(self):\n        pass\n\n    @staticmethod\n    def project_name() -> str:\n        return \"uPIMulator_frontend\"\n\n    @staticmethod\n    def root_path_in_local() -> str:\n        dirpath = Path(__file__).resolve().parent.as_posix()\n        dirnames = dirpath.split(os.path.sep)\n        for i in range(len(dirnames)):\n            if dirnames[i] == PathCollector.project_name():\n                return os.path.sep.join(dirnames[: i + 1])\n        raise ValueError\n\n    @staticmethod\n    def root_path_in_docker() -> str:\n        return f\"/root/{PathCollector.project_name()}\"\n\n    @staticmethod\n    def asm_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"asm\")\n\n    @staticmethod\n    def asm_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/asm\"\n\n    @staticmethod\n    def benchmark_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"benchmark\")\n\n    @staticmethod\n    def benchmark_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/benchmark\"\n\n    @staticmethod\n    def bin_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"bin\")\n\n    @staticmethod\n    def bin_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/bin\"\n\n    @staticmethod\n    def trace_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"trace\")\n\n    @staticmethod\n    def trace_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/trace\"\n\n    @staticmethod\n    def sdk_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"sdk\")\n\n    @staticmethod\n    def sdk_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/sdk\"\n\n    @staticmethod\n    def src_path_in_local() -> str:\n        return os.path.join(PathCollector.root_path_in_local(), \"src\")\n\n    @staticmethod\n    def src_path_in_docker() -> str:\n        return f\"{PathCollector.root_path_in_docker()}/src\"\n\n    @staticmethod\n    def upmem_sdk_path_in_local() -> str:\n        raise ValueError\n\n    @staticmethod\n    def upmem_sdk_path_in_docker() -> str:\n        return \"/root/upmem-2021.3.0-Linux-x86_64\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/binary/executable_test.py",
    "content": "from typing import Set\n\nimport pytest\n\nfrom abi.binary.executable import Executable\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\n@pytest.fixture\ndef executable() -> Executable:\n    return Executable(\"\", set())\n\n\n@pytest.fixture\ndef section_name() -> SectionName:\n    return SectionName.TEXT\n\n\n@pytest.fixture\ndef name() -> str:\n    return StrInitializer.identifier(IntInitializer.value_by_range(1, 64))\n\n\n@pytest.fixture\ndef section_flags() -> Set[SectionFlag]:\n    return {SectionFlag.ALLOC, SectionFlag.EXECINSTR}\n\n\n@pytest.fixture\ndef section_type() -> SectionType:\n    return SectionType.PROG_BITS\n\n\ndef test_checkout_section(\n    executable: Executable,\n    section_name: SectionName,\n    name: str,\n    section_flags: Set[SectionFlag],\n    section_type: SectionType,\n):\n    executable.checkout_section(section_name, name, section_flags, section_type)\n    assert executable.section(section_name, name) is not None\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/binary/liveness_test.py",
    "content": "import pytest\n\nfrom abi.binary.liveness import Liveness\n\n\n@pytest.fixture\ndef liveness() -> Liveness:\n    return Liveness()\n\n\ndef test_def(liveness: Liveness):\n    liveness.checkout_def(\"foo\")\n\n    assert \"foo\" in liveness.defs()\n\n\ndef test_use(liveness: Liveness):\n    liveness.checkout_def(\"foo\")\n    liveness.add_use(\"bar\")\n\n    assert \"bar\" in liveness.uses(\"foo\")\n\n\ndef test_global_symbol(liveness: Liveness):\n    liveness.add_global_symbol(\"foo\")\n\n    assert \"foo\" in liveness.global_symbols()\n\n\ndef test_local_symbol(liveness: Liveness):\n    liveness.checkout_def(\"foo\")\n\n    assert \"foo\" in liveness.local_symbols()\n\n\ndef test_unresolved_symbol(liveness: Liveness):\n    liveness.checkout_def(\"foo\")\n    liveness.add_use(\"bar\")\n\n    assert \"bar\" in liveness.unresolved_symbols()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/ascii_directive_test.py",
    "content": "from abi.directive.ascii_directive import AsciiDirective\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\ndef test_ascii_directive():\n    for _ in range(100):\n        characters_width = IntInitializer.value_by_range(1, 64)\n        characters = StrInitializer.identifier(characters_width)\n\n        ascii_directive = AsciiDirective(characters)\n\n        assert characters == ascii_directive.characters()\n        assert len(characters) == ascii_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/asciz_directive_test.py",
    "content": "from abi.directive.asciz_directive import AscizDirective\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\ndef test_ascii_directive():\n    for _ in range(100):\n        characters_width = IntInitializer.value_by_range(1, 64)\n        characters = StrInitializer.identifier(characters_width)\n\n        asciz_directive = AscizDirective(characters)\n\n        assert characters == asciz_directive.characters()\n        assert len(characters) + 1 == asciz_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/byte_directive_test.py",
    "content": "from abi.directive.byte_directive import ByteDirective\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_byte_directive():\n    for _ in range(100):\n        value = IntInitializer.value_by_width(Representation.UNSIGNED, 8)\n\n        byte_directive = ByteDirective(value)\n\n        assert value == byte_directive.value()\n        assert 1 == byte_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/long_directive_test.py",
    "content": "from abi.directive.long_directive import LongDirective\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_long_directive():\n    for _ in range(100):\n        value = IntInitializer.value_by_width(Representation.UNSIGNED, 32)\n\n        long_directive = LongDirective(value)\n\n        assert value == long_directive.value()\n        assert 4 == long_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/quad_directive_test.py",
    "content": "from abi.directive.quad_directive import QuadDirective\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_quad_directive():\n    for _ in range(100):\n        value = IntInitializer.value_by_width(Representation.UNSIGNED, 64)\n\n        quad_directive = QuadDirective(value)\n\n        assert value == quad_directive.value()\n        assert 8 == quad_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/short_directive_test.py",
    "content": "from abi.directive.short_directive import ShortDirective\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_short_directive():\n    for _ in range(100):\n        value = IntInitializer.value_by_width(Representation.UNSIGNED, 16)\n\n        short_directive = ShortDirective(value)\n\n        assert value == short_directive.value()\n        assert 2 == short_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/directive/zero_directive_test.py",
    "content": "from abi.directive.zero_directive import ZeroDirective\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_zero_directive():\n    for _ in range(100):\n        size = IntInitializer.value_by_range(1, 32)\n        value = IntInitializer.value_by_width(Representation.UNSIGNED, 8)\n\n        zero_directive = ZeroDirective(size, value)\n\n        assert value == zero_directive.value()\n        assert size == zero_directive.size()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/isa/register/gp_register_test.py",
    "content": "from abi.isa.register.gp_register import GPRegister\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\ndef test_gp_register():\n    index = IntInitializer.value_by_range(0, ConfigLoader.num_gp_registers())\n    gp_register = GPRegister(index)\n\n    assert index == gp_register.index()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/isa/register/pair_register_test.py",
    "content": "from abi.isa.register.pair_register import PairRegister\nfrom initializer.int_initializer import IntInitializer\nfrom util.config_loader import ConfigLoader\n\n\ndef test_pair_register():\n    index = (IntInitializer.value_by_range(0, ConfigLoader.num_gp_registers()) // 2) * 2\n    pair_register = PairRegister(index)\n\n    assert index == pair_register.index()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/label/label_test.py",
    "content": "import pytest\n\nfrom abi.label.label import Label\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.instruction_address_word import InstructionAddressWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\n@pytest.fixture\ndef label() -> Label:\n    return Label(\"foo\")\n\n\ndef test_name():\n    for _ in range(100):\n        name_width = IntInitializer.value_by_range(1, 64)\n        name = StrInitializer.identifier(name_width)\n\n        label = Label(name)\n\n        assert name == label.name()\n\n\ndef test_address(label: Label):\n    address_width = min(InstructionAddressWord().width(), DataAddressWord().width())\n    address = IntInitializer.value_by_width(Representation.UNSIGNED, address_width)\n\n    label.set_address(address)\n\n    assert address == label.address()\n\n\ndef test_size(label: Label):\n    address_width = min(InstructionAddressWord().width(), DataAddressWord().width())\n    max_size = 2 ** address_width - 1\n    size = IntInitializer.value_by_range(0, max_size + 1)\n\n    label.set_size(size)\n\n    assert size == label.size()\n\n\ndef test_begin_address(label: Label):\n    address_width = min(InstructionAddressWord().width(), DataAddressWord().width())\n    address = IntInitializer.value_by_width(Representation.UNSIGNED, address_width)\n\n    label.set_address(address)\n\n    assert address == label.begin_address()\n\n\ndef test_end_address(label: Label):\n    address_width = min(InstructionAddressWord().width(), DataAddressWord().width())\n    address = IntInitializer.value_by_width(Representation.UNSIGNED, address_width)\n    max_size = 2 ** address_width - 1\n    size = IntInitializer.value_by_range(0, max_size + 1)\n\n    label.set_address(address)\n    label.set_size(size)\n\n    assert address + size == label.end_address()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/section/section_test.py",
    "content": "from typing import Set\n\nimport pytest\n\nfrom abi.section.section import Section\nfrom abi.section.section_flag import SectionFlag\nfrom abi.section.section_name import SectionName\nfrom abi.section.section_type import SectionType\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\n@pytest.fixture\ndef section_names() -> Set[SectionName]:\n    return set(SectionName)\n\n\n@pytest.fixture\ndef name() -> str:\n    return StrInitializer.identifier(IntInitializer.value_by_range(1, 64))\n\n\n@pytest.fixture\ndef section_flags() -> Set[SectionFlag]:\n    return {SectionFlag.ALLOC, SectionFlag.EXECINSTR}\n\n\n@pytest.fixture\ndef section_type() -> SectionType:\n    return SectionType.PROG_BITS\n\n\ndef test_address(\n    section_names: Set[SectionName],\n    section_flags: Set[SectionFlag],\n    section_type: SectionType,\n):\n    for section_name in section_names:\n        for _ in range(100):\n            address = (\n                IntInitializer.value_by_width(Representation.UNSIGNED, DataAddressWord().width())\n                // InstructionWord().size()\n            ) * InstructionWord().size()\n\n            section = Section(section_name, \"\", section_flags, section_type)\n            section.set_address(address)\n\n            assert address == section.address()\n\n\ndef test_label(\n    section_names: Set[SectionName],\n    name: str,\n    section_flags: Set[SectionFlag],\n    section_type: SectionType,\n):\n    for section_name in section_names:\n        for _ in range(100):\n            section = Section(section_name, name, section_flags, section_type)\n            section.append_label(name)\n\n            label = section.label(name)\n            assert label is not None\n            assert label.name() == name\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/word/immediate_test.py",
    "content": "from abi.word.immediate import Immediate\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\ndef test_value():\n    for _ in range(100):\n        representation = IntInitializer.value_by_list(list(Representation))\n        width = IntInitializer.value_by_range(1, 64)\n        value = IntInitializer.value_by_width(representation, width)\n        immediate = Immediate(representation, width, value)\n\n        assert value == immediate.value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/abi/word/words_test.py",
    "content": "from typing import Set, Union\n\nimport pytest\n\nfrom abi.word.data_address_word import DataAddressWord\nfrom abi.word.data_word import DataWord\nfrom abi.word.double_data_word import DoubleDataWord\nfrom abi.word.instruction_address_word import InstructionAddressWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\n\n\n@pytest.fixture\ndef words() -> Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord, DoubleDataWord,]]:\n    return {\n        DataAddressWord(),\n        DataWord(),\n        InstructionAddressWord(),\n        InstructionWord(),\n        DoubleDataWord(),\n    }\n\n\ndef test_bit(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        for i in range(word.width()):\n            assert not word.bit(i)\n\n            word.set_bit(i)\n            assert word.bit(i)\n\n            word.clear_bit(i)\n            assert not word.bit(i)\n\n\ndef test_bit_slice(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        for _ in range(100):\n            representation = IntInitializer.value_by_list(list(Representation))\n\n            slice_width = IntInitializer.value_by_range(1, word.width())\n            begin = IntInitializer.value_by_range(0, word.width() - slice_width + 1)\n            end = IntInitializer.value_by_range(begin + slice_width, word.width() + 1)\n            value = IntInitializer.value_by_width(representation, slice_width)\n\n            word.set_bit_slice(begin, end, value)\n            assert value == word.bit_slice(representation, begin, end)\n\n\ndef test_value(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        for _ in range(100):\n            representation = IntInitializer.value_by_list(list(Representation))\n            value = IntInitializer.value_by_width(representation, word.width())\n            word.set_value(value)\n            assert value == word.value(representation)\n\n\ndef test_zero(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        word.set_value(0)\n\n        for i in range(word.width()):\n            assert not word.bit(i)\n\n\ndef test_lneg(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        word.set_value(-1)\n\n        for i in range(word.width()):\n            assert word.bit(i)\n\n\ndef test_bytes(words: Set[Union[DataAddressWord, DataWord, InstructionAddressWord, InstructionWord]]):\n    for word in words:\n        for _ in range(100):\n            representation = IntInitializer.value_by_list(list(Representation))\n            value = IntInitializer.value_by_width(representation, word.width())\n\n            word.set_value(value)\n            bytes_ = word.to_bytes()\n\n            word.set_value(0)\n            word.from_bytes(bytes_)\n\n            assert value == word.value(representation)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/compiler/compiler_test.py",
    "content": "import os\n\nimport pytest\n\nfrom compiler.compiler import Compiler\nfrom util.path_collector import PathCollector\n\n\n# TODO(bongjoon.hyun@gmail.com): compile for num_tasklets from 1 to 24\n@pytest.fixture\ndef num_tasklets() -> int:\n    return 1\n\n\ndef test_compile_benchmarks(num_tasklets: int):\n    for benchmark in os.listdir(PathCollector.benchmark_path_in_local()):\n        assert Compiler.compile_benchmark(benchmark, num_tasklets)\n\n\ndef test_compile_sdk(num_tasklets: int):\n    assert Compiler.compile_sdk(num_tasklets)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/encoder/ascii_encoder_test.py",
    "content": "from encoder.ascii_encoder import AsciiEncoder\nfrom initializer.int_initializer import IntInitializer\nfrom initializer.str_initializer import StrInitializer\n\n\ndef test_identifier():\n    for _ in range(100):\n        width = IntInitializer.value_by_range(1, 64)\n        identifier = StrInitializer.identifier(width)\n\n        bytes_ = [AsciiEncoder.encode(character) for character in identifier]\n\n        assert identifier == \"\".join([AsciiEncoder.decode(ascii_code) for ascii_code in bytes_])\n\n\ndef test_hello_world():\n    hello_world = \"Hello, World!\"\n\n    bytes_ = [AsciiEncoder.encode(character) for character in hello_world]\n\n    assert hello_world == \"\".join([AsciiEncoder.decode(ascii_code) for ascii_code in bytes_])\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/encoder/directive_encoder_test.py",
    "content": "from abi.directive.byte_directive import ByteDirective\nfrom abi.directive.long_directive import LongDirective\nfrom abi.directive.quad_directive import QuadDirective\nfrom abi.directive.short_directive import ShortDirective\nfrom encoder.ascii_encoder import AsciiEncoder\nfrom encoder.directive_encoder import DirectiveEncoder\nfrom initializer.directive_initializer import DirectiveInitializer\n\n\ndef test_ascii_directive():\n    ascii_directive = DirectiveInitializer.ascii_directive()\n\n    bytes_ = DirectiveEncoder.encode(ascii_directive)\n    characters = \"\".join([AsciiEncoder.decode(byte) for byte in bytes_])\n\n    assert ascii_directive.characters() == characters\n\n\ndef test_asciz_directive():\n    asciz_directive = DirectiveInitializer.asciz_directive()\n\n    bytes_ = DirectiveEncoder.encode(asciz_directive)\n    characters = \"\".join([AsciiEncoder.decode(byte) for byte in bytes_])\n\n    assert asciz_directive.characters() == characters[:-1]\n\n\ndef test_byte_directive():\n    byte_directive = DirectiveInitializer.byte_directive()\n\n    bytes_ = DirectiveEncoder.encode(byte_directive)\n\n    for i in range(ByteDirective.size()):\n        byte_directive.value() == bytes_[i].value()\n\n\ndef test_short_directive():\n    short_directive = DirectiveInitializer.short_directive()\n\n    bytes_ = DirectiveEncoder.encode(short_directive)\n\n    for i in range(ShortDirective.size()):\n        short_directive.value() == bytes_[i].value()\n\n\ndef test_long_directive():\n    long_directive = DirectiveInitializer.long_directive()\n\n    bytes_ = DirectiveEncoder.encode(long_directive)\n\n    for i in range(LongDirective.size()):\n        long_directive.value() == bytes_[i].value()\n\n\ndef test_quad_directive():\n    quad_directive = DirectiveInitializer.quad_directive()\n\n    bytes_ = DirectiveEncoder.encode(quad_directive)\n\n    for i in range(QuadDirective.size()):\n        quad_directive.value() == bytes_[i].value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/encoder/instruction_encoder_test.py",
    "content": "from abi.isa.instruction.condition import Condition\nfrom abi.isa.instruction.instruction import Instruction\nfrom abi.isa.instruction.op_code import OpCode\nfrom abi.isa.instruction.suffix import Suffix\nfrom encoder.instruction_encoder import InstructionEncoder\nfrom initializer.instruction_initializer import InstructionInitializer\n\n\ndef test_rici():\n    for _ in range(100):\n        for op_code in Instruction.RICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RICI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_rri():\n    for _ in range(100):\n        for op_code in Instruction.RRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_rric():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRIC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRIC\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_rrici():\n    for _ in range(100):\n        for op_code in Instruction.RRICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRICI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_rrif():\n    for _ in range(100):\n        for op_code in Instruction.RRIFOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRIF)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRIF\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition() == Condition.FALSE\n\n\ndef test_rrr():\n    for _ in range(100):\n        for op_code in Instruction.RRROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRR\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n\n\ndef test_rrrc():\n    for _ in range(100):\n        for op_code in Instruction.RRRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRRC\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_rrrci():\n    for _ in range(100):\n        for op_code in Instruction.RRRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRRCI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_zri():\n    for _ in range(100):\n        for op_code in Instruction.RRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_zric():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRIC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRIC\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_zrici():\n    for _ in range(100):\n        for op_code in Instruction.RRICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRICI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_zrif():\n    for _ in range(100):\n        for op_code in Instruction.RRIFOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRIF)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRIF\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition() == Condition.FALSE\n\n\ndef test_zrr():\n    for _ in range(100):\n        for op_code in Instruction.RRROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRR\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n\n\ndef test_zrrc():\n    for _ in range(100):\n        for op_code in Instruction.RRRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRRC\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_zrrci():\n    for _ in range(100):\n        for op_code in Instruction.RRRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRRCI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_rri():\n    for _ in range(100):\n        for op_code in Instruction.RRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_u_rri():\n    for _ in range(100):\n        for op_code in Instruction.RRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_s_rric():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRIC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRIC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_u_rric():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRIC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRIC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_s_rrici():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRICI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rrici():\n    for _ in range(100):\n        for op_code in Instruction.RRICOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRICI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_rrif():\n    for _ in range(100):\n        for op_code in Instruction.RRIFOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRIF)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRIF\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition() == Condition.FALSE\n\n\ndef test_u_rrif():\n    for _ in range(100):\n        for op_code in Instruction.RRIFOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRIF)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRIF\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition() == Condition.FALSE\n\n\ndef test_s_rrr():\n    for _ in range(100):\n        for op_code in Instruction.RRROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRR\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n\n\ndef test_u_rrr():\n    for _ in range(100):\n        for op_code in Instruction.RRROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRR\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n\n\ndef test_s_rrrc():\n    for _ in range(100):\n        for op_code in Instruction.RRRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_u_rrrc():\n    for _ in range(100):\n        for op_code in Instruction.RRRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_s_rrrci():\n    for _ in range(100):\n        for op_code in Instruction.RRRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rrrci():\n    for _ in range(100):\n        for op_code in Instruction.RRRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_rr():\n    for _ in range(100):\n        for op_code in Instruction.RROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RR\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_rrc():\n    for _ in range(100):\n        for op_code in Instruction.RRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRC\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_rrci():\n    for _ in range(100):\n        for op_code in Instruction.RRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRCI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_zr():\n    for _ in range(100):\n        for op_code in Instruction.RROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZR\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_zrc():\n    for _ in range(100):\n        for op_code in Instruction.RRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRC\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_zrci():\n    for _ in range(100):\n        for op_code in Instruction.RRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRCI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_rr():\n    for _ in range(100):\n        for op_code in Instruction.RROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RR\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_u_rr():\n    for _ in range(100):\n        for op_code in Instruction.RROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RR\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_s_rrc():\n    for _ in range(100):\n        for op_code in Instruction.RRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_u_rrc():\n    for _ in range(100):\n        for op_code in Instruction.RRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_s_rrci():\n    for _ in range(100):\n        for op_code in Instruction.RRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rrci():\n    for _ in range(100):\n        for op_code in Instruction.RRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_drdici():\n    for _ in range(100):\n        for op_code in Instruction.DRDICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.DRDICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.DRDICI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.db() == dst_instruction.db()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_rrri():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRRI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_rrrici():\n    for _ in range(100):\n        for op_code in Instruction.RRRICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RRRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RRRICI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_zrri():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRRI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_zrrici():\n    for _ in range(100):\n        for op_code in Instruction.RRRICIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZRRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZRRICI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_rrri():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRRI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_u_rrri():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRRI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_s_rrrici():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RRRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RRRICI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rrrici():\n    for _ in range(100):\n        for op_code in Instruction.RRRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RRRICI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RRRICI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_rir():\n    for _ in range(100):\n        for op_code in Instruction.RIROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RIR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RIR\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_rirc():\n    for _ in range(100):\n        for op_code in Instruction.RIRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RIRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RIRC\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_rirci():\n    for _ in range(100):\n        for op_code in Instruction.RIRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RIRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RIRCI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_zir():\n    for _ in range(100):\n        for op_code in Instruction.RIROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZIR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZIR\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n\n\ndef test_zirc():\n    for _ in range(100):\n        for op_code in Instruction.RIRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZIRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZIRC\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_zirci():\n    for _ in range(100):\n        for op_code in Instruction.RIRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZIRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZIRCI\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_rirc():\n    for _ in range(100):\n        for op_code in Instruction.RIRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RIRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RIRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_u_rirc():\n    for _ in range(100):\n        for op_code in Instruction.RIRCOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RIRC)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RIRC\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n\n\ndef test_s_rirci():\n    for _ in range(100):\n        for op_code in Instruction.RIRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RIRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RIRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rirci():\n    for _ in range(100):\n        for op_code in Instruction.RIRCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RIRCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RIRCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_r():\n    for _ in range(100):\n        for op_code in Instruction.ROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.R)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.R\n            assert src_instruction.rc() == dst_instruction.rc()\n\n\ndef test_rci():\n    for _ in range(100):\n        for op_code in Instruction.RCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.RCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.RCI\n            assert src_instruction.rc() == dst_instruction.rc()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_z():\n    for _ in range(100):\n        for op_code in {*Instruction.ROpCodes, OpCode.NOP}:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.Z)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.Z\n\n\ndef test_zci():\n    for _ in range(100):\n        for op_code in Instruction.RCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ZCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ZCI\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_s_r():\n    for _ in range(100):\n        for op_code in Instruction.ROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_R)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_R\n            assert src_instruction.dc() == dst_instruction.dc()\n\n\ndef test_u_r():\n    for _ in range(100):\n        for op_code in Instruction.ROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_R)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_R\n            assert src_instruction.dc() == dst_instruction.dc()\n\n\ndef test_s_rci():\n    for _ in range(100):\n        for op_code in Instruction.RCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_RCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_RCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_u_rci():\n    for _ in range(100):\n        for op_code in Instruction.RCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_RCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_RCI\n            assert src_instruction.dc() == dst_instruction.dc()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_ci():\n    for _ in range(100):\n        for op_code in Instruction.CIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.CI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.CI\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_i():\n    for _ in range(100):\n        for op_code in Instruction.IOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.I)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.I\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_ddci():\n    for _ in range(100):\n        for op_code in Instruction.DDCIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.DDCI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.DDCI\n            assert src_instruction.dc() == src_instruction.dc()\n            assert src_instruction.db() == src_instruction.db()\n            assert src_instruction.condition() == dst_instruction.condition()\n            assert src_instruction.pc().value() == dst_instruction.pc().value()\n\n\ndef test_erri():\n    for _ in range(100):\n        for op_code in Instruction.ERRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ERRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ERRI\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.rc() == src_instruction.rc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n\n\ndef test_s_erri():\n    for _ in range(100):\n        for op_code in Instruction.ERRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.S_ERRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.S_ERRI\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.dc() == src_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n\n\ndef test_u_erri():\n    for _ in range(100):\n        for op_code in Instruction.ERRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.U_ERRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.U_ERRI\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.dc() == src_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n\n\ndef test_edri():\n    for _ in range(100):\n        for op_code in Instruction.EDRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.EDRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.EDRI\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.dc() == src_instruction.dc()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n\n\ndef test_erii():\n    for _ in range(100):\n        for op_code in Instruction.ERIIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ERII)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ERII\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n\n\ndef test_erir():\n    for _ in range(100):\n        for op_code in Instruction.ERIROpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ERIR)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ERIR\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n            assert src_instruction.rb() == dst_instruction.rb()\n\n\ndef test_erid():\n    for _ in range(100):\n        for op_code in Instruction.ERIDOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.ERID)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.ERID\n            assert src_instruction.endian() == src_instruction.endian()\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.off().value() == dst_instruction.off().value()\n            assert src_instruction.db() == dst_instruction.db()\n\n\ndef test_dma_rri():\n    for _ in range(100):\n        for op_code in Instruction.DMARRIOpCodes:\n            src_instruction = InstructionInitializer.instruction(op_code, Suffix.DMA_RRI)\n\n            bytes_ = InstructionEncoder.encode(src_instruction)\n            dst_instruction = InstructionEncoder.decode(bytes_)\n\n            assert src_instruction.op_code() == dst_instruction.op_code() == op_code\n            assert src_instruction.suffix() == dst_instruction.suffix() == Suffix.DMA_RRI\n            assert src_instruction.ra() == dst_instruction.ra()\n            assert src_instruction.rb() == dst_instruction.rb()\n            assert src_instruction.imm().value() == dst_instruction.imm().value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/dpu/dma_test.py",
    "content": "import math\nfrom typing import List\n\nimport pytest\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom encoder.byte import Byte\nfrom initializer.int_initializer import IntInitializer\nfrom iss.dpu.dma import DMA\nfrom iss.dram.mram import MRAM\nfrom iss.dram.mram_command import MRAMCommand\nfrom iss.sram.atomic import Atomic\nfrom iss.sram.iram import IRAM\nfrom iss.sram.wram import WRAM\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef atomic() -> Atomic:\n    return Atomic()\n\n\n@pytest.fixture\ndef iram() -> IRAM:\n    return IRAM()\n\n\n@pytest.fixture\ndef wram() -> WRAM:\n    return WRAM()\n\n\n@pytest.fixture\ndef mram() -> MRAM:\n    return MRAM()\n\n\n@pytest.fixture\ndef atomic_address() -> int:\n    return ConfigLoader.atomic_offset()\n\n\n@pytest.fixture\ndef atomic_bytes() -> List[Byte]:\n    return [Byte(0) for _ in range(100)]\n\n\n@pytest.fixture\ndef iram_address() -> int:\n    return ConfigLoader.iram_offset()\n\n\n@pytest.fixture\ndef iram_bytes() -> List[Byte]:\n    bytes_: List[Byte] = []\n    for _ in range(100):\n        instruction_word = InstructionWord()\n        instruction_word.set_value(IntInitializer.value_by_width(Representation.UNSIGNED, instruction_word.width()))\n        bytes_ += instruction_word.to_bytes()\n    return bytes_\n\n\n@pytest.fixture\ndef wram_address() -> int:\n    return ConfigLoader.wram_offset()\n\n\n@pytest.fixture\ndef wram_bytes() -> List[Byte]:\n    return [Byte(IntInitializer.value_by_range(0, 2 ** 8)) for _ in range(100)]\n\n\n@pytest.fixture\ndef mram_address() -> int:\n    return ConfigLoader.mram_offset()\n\n\n@pytest.fixture\ndef unaligned_mram_bytes() -> List[Byte]:\n    return [Byte(IntInitializer.value_by_range(0, 2 ** 8)) for _ in range(100)]\n\n\n@pytest.fixture\ndef aligned_mram_bytes() -> List[Byte]:\n    return [Byte(IntInitializer.value_by_range(0, 2 ** 8)) for _ in range(100 * ConfigLoader.min_access_granularity())]\n\n\ndef test_host_dma_transfer_to_atomic(\n    atomic: Atomic, iram: IRAM, wram: WRAM, mram: MRAM, atomic_address: int, atomic_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_atomic(atomic_address, atomic_bytes)\n\n    for address in range(atomic_address, atomic_address + len(atomic_bytes)):\n        assert atomic.can_acquire(address)\n\n\ndef test_host_dma_transfer_to_iram(\n    atomic: Atomic, iram: IRAM, wram: WRAM, mram: MRAM, iram_address: int, iram_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_iram(iram_address, iram_bytes)\n\n    num_instruction_word = len(iram_bytes) // InstructionWord().size()\n    bytes_: List[Byte] = []\n    for i in range(num_instruction_word):\n        instruction_word = iram.read(iram_address + i * InstructionWord().size())\n        bytes_ += instruction_word.to_bytes()\n\n    for iram_byte, byte in zip(iram_bytes, bytes_):\n        assert iram_byte.value() == byte.value()\n\n\ndef test_host_dma_transfer_to_wram(\n    atomic: Atomic, iram: IRAM, wram: WRAM, mram: MRAM, wram_address: int, wram_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_wram(wram_address, wram_bytes)\n\n    num_data_words = math.ceil(len(wram_bytes) / DataWord().size())\n    bytes_: List[Byte] = []\n    for i in range(num_data_words):\n        data_word = wram.read(wram_address + i * DataWord().size())\n        bytes_ += data_word.to_bytes()\n\n    for i in range(len(wram_bytes)):\n        assert wram_bytes[i].value() == bytes_[i].value()\n\n\ndef test_host_dma_transfer_to_mram(\n    atomic: Atomic, iram: IRAM, wram: WRAM, mram: MRAM, mram_address: int, unaligned_mram_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_mram(mram_address, unaligned_mram_bytes)\n\n    mram_command_size = (\n        math.ceil(len(unaligned_mram_bytes) / ConfigLoader.min_access_granularity())\n        * ConfigLoader.min_access_granularity()\n    )\n    mram_command = MRAMCommand(MRAMCommand.Operation.READ, mram_address, mram_command_size)\n\n    assert mram.can_push()\n    mram.push(mram_command)\n    assert mram.can_pop()\n    mram_command_bytes: List[Byte] = []\n    for data_word in mram.pop().data_words():\n        mram_command_bytes += data_word.to_bytes()\n\n    for i in range(len(unaligned_mram_bytes)):\n        assert unaligned_mram_bytes[i].value() == mram_command_bytes[i].value()\n\n\ndef test_dpu_dma_transfer_from_mram_to_wram(\n    atomic: Atomic,\n    iram: IRAM,\n    wram: WRAM,\n    mram: MRAM,\n    wram_address: int,\n    mram_address: int,\n    aligned_mram_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_mram(mram_address, aligned_mram_bytes)\n    dma.dpu_dma_transfer_from_mram_to_wram(mram_address, wram_address, len(aligned_mram_bytes))\n\n    num_data_words = len(aligned_mram_bytes) // DataWord().size()\n    bytes_: List[Byte] = []\n    for i in range(num_data_words):\n        data_word = wram.read(wram_address + i * DataWord().size())\n        bytes_ += data_word.to_bytes()\n\n    for i in range(len(aligned_mram_bytes)):\n        assert aligned_mram_bytes[i].value() == bytes_[i].value()\n\n\ndef test_dpu_dma_transfer_from_wram_to_mram(\n    atomic: Atomic,\n    iram: IRAM,\n    wram: WRAM,\n    mram: MRAM,\n    wram_address: int,\n    mram_address: int,\n    aligned_mram_bytes: List[Byte],\n):\n    dma = DMA(atomic, iram, wram, mram)\n    dma.host_dma_transfer_to_wram(wram_address, aligned_mram_bytes)\n    dma.dpu_dma_transfer_from_wram_to_mram(wram_address, mram_address, len(aligned_mram_bytes))\n\n    mram_command_size = (\n        len(aligned_mram_bytes) // ConfigLoader.min_access_granularity()\n    ) * ConfigLoader.min_access_granularity()\n\n    mram_command = MRAMCommand(MRAMCommand.Operation.READ, mram_address, mram_command_size)\n\n    assert mram.can_push()\n    mram.push(mram_command)\n    assert mram.can_pop()\n    mram_command_bytes: List[Byte] = []\n    for data_word in mram.pop().data_words():\n        mram_command_bytes += data_word.to_bytes()\n\n    for i in range(len(aligned_mram_bytes)):\n        assert aligned_mram_bytes[i].value() == mram_command_bytes[i].value()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/dpu/scheduler_test.py",
    "content": "from typing import List\n\nimport pytest\n\nfrom iss.dpu.scheduler import Scheduler\nfrom iss.dpu.thread import Thread\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef threads() -> List[Thread]:\n    return [Thread(i) for i in range(ConfigLoader.max_num_tasklets())]\n\n\ndef test_single_thread():\n    thread = Thread(0)\n    thread.set_thread_state(Thread.State.RUNNABLE)\n    scheduler = Scheduler([thread])\n\n    for i in range(100):\n        assert scheduler.schedule() == thread\n        scheduler.cycle()\n\n\ndef test_max_threads(threads: List[Thread]):\n    scheduler = Scheduler(threads)\n    for thread in threads:\n        thread.set_thread_state(Thread.State.RUNNABLE)\n\n    for i in range(100):\n        assert scheduler.schedule() == threads[i % len(threads)]\n        scheduler.cycle()\n\n\ndef test_awake():\n    thread = Thread(0)\n    thread.set_thread_state(Thread.State.RUNNABLE)\n    thread.set_thread_state(Thread.State.SLEEP)\n    scheduler = Scheduler([thread])\n\n    for _ in range(100):\n        assert scheduler.schedule() is None\n        scheduler.cycle()\n\n    scheduler.awake(0)\n    assert thread.state() == Thread.State.RUNNABLE\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/dram/mram_test.py",
    "content": "import pytest\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom iss.dram.mram import MRAM\nfrom iss.dram.mram_command import MRAMCommand\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef mram() -> MRAM:\n    return MRAM()\n\n\ndef test_mram(mram: MRAM):\n    for _ in range(100):\n        address = IntInitializer.value_by_range(\n            ConfigLoader.mram_offset(),\n            ConfigLoader.mram_offset() + ConfigLoader.mram_size() - ConfigLoader.min_access_granularity(),\n        )\n\n        if address % ConfigLoader.min_access_granularity() == 0:\n            write_mram_command = MRAMCommand(\n                MRAMCommand.Operation.WRITE, address, ConfigLoader.min_access_granularity(),\n            )\n            read_mram_command = MRAMCommand(MRAMCommand.Operation.READ, address, ConfigLoader.min_access_granularity(),)\n\n            data_words = [DataWord() for _ in range(ConfigLoader.min_access_granularity() // DataWord().size())]\n            for data_word in data_words:\n                data_word.set_value(IntInitializer.value_by_width(Representation.UNSIGNED, DataWord().width()))\n            write_mram_command.set_data_words(data_words)\n\n            assert not mram.can_pop()\n\n            assert mram.can_push()\n            mram.push(write_mram_command)\n\n            assert mram.can_push()\n            mram.push(read_mram_command)\n\n            assert mram.can_pop()\n            assert write_mram_command == mram.pop()\n\n            assert mram.can_pop()\n            assert read_mram_command == mram.pop()\n\n            for data_word, read_mram_command_data_word in zip(data_words, read_mram_command.data_words()):\n                assert data_word.value(Representation.UNSIGNED) == read_mram_command_data_word.value(\n                    Representation.UNSIGNED\n                )\n\n            assert not mram.can_pop()\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/register/register_file_test.py",
    "content": "import pytest\n\nfrom abi.isa.exception import Exception_\nfrom abi.isa.flag import Flag\nfrom abi.isa.instruction.condition import Condition\nfrom abi.isa.register.gp_register import GPRegister\nfrom abi.isa.register.pair_register import PairRegister\nfrom abi.isa.register.sp_register import SPRegister\nfrom abi.word.data_word import DataWord\nfrom abi.word.double_data_word import DoubleDataWord\nfrom abi.word.instruction_address_word import InstructionAddressWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom iss.register.register_file import RegisterFile\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef id_() -> int:\n    return IntInitializer.value_by_range(0, ConfigLoader.max_num_tasklets())\n\n\n@pytest.fixture\ndef instruction_address_word_value() -> int:\n    return IntInitializer.value_by_width(Representation.UNSIGNED, InstructionAddressWord().width())\n\n\n@pytest.fixture\ndef data_word_value() -> int:\n    return IntInitializer.value_by_width(Representation.SIGNED, DataWord().width())\n\n\n@pytest.fixture\ndef double_data_word_value() -> int:\n    return IntInitializer.value_by_width(Representation.SIGNED, DoubleDataWord().width())\n\n\ndef test_gp_register(id_: int, data_word_value: int):\n    register_file = RegisterFile(id_)\n    for i in range(ConfigLoader.num_gp_registers()):\n        gp_register = GPRegister(i)\n\n        register_file.write(gp_register, data_word_value)\n        assert data_word_value == register_file.read(gp_register, Representation.SIGNED)\n\n        register_file.cycle()\n\n\ndef test_sp_register(id_: int):\n    register_file = RegisterFile(id_)\n\n    assert register_file.read(SPRegister.ZERO, Representation.SIGNED) == 0\n    assert register_file.read(SPRegister.ONE, Representation.SIGNED) == 1\n    assert register_file.read(SPRegister.ID, Representation.SIGNED) == id_\n    assert register_file.read(SPRegister.LNEG, Representation.SIGNED) == -1\n    assert register_file.read(SPRegister.MNEG, Representation.SIGNED) == -(2 ** (DataWord().width() - 1))\n    assert register_file.read(SPRegister.ID2, Representation.SIGNED) == (2 * id_)\n    assert register_file.read(SPRegister.ID4, Representation.SIGNED) == (4 * id_)\n    assert register_file.read(SPRegister.ID8, Representation.SIGNED) == (8 * id_)\n\n\ndef test_pair_register(id_: int, double_data_word_value: int):\n    register_file = RegisterFile(id_)\n\n    for i in range(ConfigLoader.num_gp_registers()):\n        if i % 2 == 0:\n            pair_register = PairRegister(i)\n\n            register_file.write(pair_register, double_data_word_value)\n            assert double_data_word_value == register_file.read(pair_register, Representation.SIGNED)\n\n            register_file.cycle()\n\n\ndef test_pc_register(id_: int, instruction_address_word_value: int):\n    register_file = RegisterFile(id_)\n\n    register_file.write_pc(instruction_address_word_value)\n    assert instruction_address_word_value == register_file.read_pc()\n\n    register_file.increment_pc()\n    assert (instruction_address_word_value + InstructionAddressWord().size()) == register_file.read_pc()\n\n\ndef test_condition_register(id_: int):\n    register_file = RegisterFile(id_)\n\n    for condition in Condition:\n        if condition == Condition.TRUE:\n            assert register_file.condition(condition)\n        elif condition == Condition.FALSE:\n            assert not register_file.condition(condition)\n        elif (\n            condition == Condition.Z\n            or condition == Condition.NZ\n            or condition == Condition.C\n            or condition == Condition.NC\n        ):\n            pass\n        else:\n            assert not register_file.condition(condition)\n\n            register_file.set_condition(condition)\n            assert register_file.condition(condition)\n\n            register_file.clear_condition(condition)\n            assert not register_file.condition(condition)\n\n\ndef test_exception_register(id_: int):\n    register_file = RegisterFile(id_)\n\n    for exception in Exception_:\n        assert not register_file.exception(exception)\n\n        register_file.set_exception(exception)\n        assert register_file.exception(exception)\n\n        register_file.clear_exception(exception)\n        assert not register_file.exception(exception)\n\n\ndef test_flag_register(id_: int):\n    register_file = RegisterFile(id_)\n\n    for flag in Flag:\n        assert not register_file.flag(flag)\n\n        register_file.set_flag(flag)\n        assert register_file.flag(flag)\n\n        register_file.clear_flag(flag)\n        assert not register_file.flag(flag)\n\n\ndef test_clear_all(id_: int):\n    register_file = RegisterFile(id_)\n\n    for condition in Condition:\n        if (\n            condition == Condition.TRUE\n            or condition == Condition.FALSE\n            or condition == Condition.Z\n            or condition == Condition.NZ\n            or condition == Condition.C\n            or condition == Condition.NC\n        ):\n            pass\n        else:\n            assert not register_file.condition(condition)\n\n    for exception in Exception_:\n        assert not register_file.exception(exception)\n\n    for flag in Flag:\n        assert not register_file.flag(flag)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/sram/atomic_test.py",
    "content": "import pytest\n\nfrom initializer.int_initializer import IntInitializer\nfrom iss.sram.atomic import Atomic\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef atomic() -> Atomic:\n    return Atomic()\n\n\ndef test_atomic(atomic: Atomic):\n    for _ in range(100):\n        address = IntInitializer.value_by_range(\n            ConfigLoader.atomic_offset(), ConfigLoader.atomic_offset() + ConfigLoader.atomic_size() - 1,\n        )\n\n        id_ = IntInitializer.value_by_range(0, ConfigLoader.max_num_tasklets() - 1)\n\n        assert atomic.can_acquire(address)\n        atomic.acquire(address, id_)\n        assert not atomic.can_acquire(address)\n\n        assert atomic.can_release(address, id_)\n        atomic.release(address, id_)\n        assert atomic.can_acquire(address)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/sram/iram_test.py",
    "content": "import pytest\n\nfrom abi.word.instruction_word import InstructionWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom iss.sram.iram import IRAM\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef iram() -> IRAM:\n    return IRAM()\n\n\ndef test_iram(iram: IRAM):\n    for _ in range(100):\n        address = IntInitializer.value_by_range(\n            ConfigLoader.iram_offset(),\n            ConfigLoader.iram_offset() + ConfigLoader.iram_size() - InstructionWord().size(),\n        )\n\n        if address % InstructionWord().size() == 0:\n            instruction_word = InstructionWord()\n            instruction_word.set_value(IntInitializer.value_by_width(Representation.UNSIGNED, instruction_word.width()))\n\n            iram.write(address, instruction_word)\n            instruction_word.value(Representation.UNSIGNED) == iram.read(address).value(Representation.UNSIGNED)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/iss/sram/wram_test.py",
    "content": "import pytest\n\nfrom abi.word.data_word import DataWord\nfrom abi.word.representation import Representation\nfrom initializer.int_initializer import IntInitializer\nfrom iss.sram.wram import WRAM\nfrom util.config_loader import ConfigLoader\n\n\n@pytest.fixture\ndef wram() -> WRAM:\n    return WRAM()\n\n\ndef test_wram(wram: WRAM):\n    for _ in range(100):\n        address = IntInitializer.value_by_range(\n            ConfigLoader.wram_offset(), ConfigLoader.wram_offset() + ConfigLoader.wram_size() - DataWord().size(),\n        )\n\n        if address % DataWord().size() == 0:\n            data_word = DataWord()\n            data_word.set_value(IntInitializer.value_by_width(Representation.UNSIGNED, data_word.width()))\n\n            wram.write(address, data_word)\n            data_word.value(Representation.UNSIGNED) == wram.read(address).value(Representation.UNSIGNED)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/linker_/linker_test.py",
    "content": "import os\nfrom typing import Set\n\nimport pytest\n\nfrom linker_.linker import Linker\nfrom util.path_collector import PathCollector\n\n\n@pytest.fixture\ndef asm_benchmark_filepaths() -> Set[str]:\n    benchmarks = os.listdir(PathCollector.benchmark_path_in_local())\n    filepaths: Set[str] = set()\n    for root_path, _, filenames in os.walk(PathCollector.asm_path_in_local()):\n        benchmark = root_path.split(os.path.sep)[-1].split(\".\")[0]\n\n        if benchmark in benchmarks:\n            for filename in filenames:\n                if filename.split(\".\")[-1] == \"S\":\n                    filepaths.add(os.path.join(root_path, filename))\n    return filepaths\n\n\n@pytest.fixture\ndef num_tasklets() -> int:\n    return 1\n\n\n# TODO(bongjoon.hyun@gmail.com): instantiate linker based on num_tasklets\ndef test_link(asm_benchmark_filepaths: Set[str], num_tasklets: int):\n    linker = Linker(num_tasklets)\n    for asm_benchmark_filepath in asm_benchmark_filepaths:\n        linker.link(asm_benchmark_filepath)\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/parser_/grammar_generator_test.py",
    "content": "import os\n\nfrom parser_.grammar_generator import GrammarGenerator\nfrom util.path_collector import PathCollector\n\n\ndef test_generate():\n    assert GrammarGenerator.generate()\n\n    for filename in GrammarGenerator.generated_filenames():\n        assert os.path.exists(os.path.join(PathCollector.src_path_in_local(), \"parser_\", \"grammar\", filename))\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/parser_/parser_test.py",
    "content": "import os\nimport subprocess\nfrom typing import Set\n\nimport pytest\n\nfrom parser_.grammar_generator import GrammarGenerator\nfrom parser_.parser import Parser\nfrom util.path_collector import PathCollector\n\n\n@pytest.fixture\ndef parser_path() -> str:\n    return os.path.join(PathCollector().src_path_in_local(), \"parser_\", \"parser.py\",)\n\n\n@pytest.fixture\ndef asm_filepaths() -> Set[str]:\n    filepaths: Set[str] = set()\n    for root_path, _, filenames in os.walk(PathCollector.asm_path_in_local()):\n        for filename in filenames:\n            if filename.split(\".\")[-1] == \"S\":\n                filepaths.add(os.path.join(root_path, filename))\n    return filepaths\n\n\n@pytest.fixture\ndef bin_filepaths() -> Set[str]:\n    filepaths: Set[str] = set()\n    for root_path, _, filenames in os.walk(PathCollector.bin_path_in_local()):\n        for filename in filenames:\n            if filename.split(\".\")[-1] == \"S\":\n                filepaths.add(os.path.join(root_path, filename))\n    return filepaths\n\n\n@pytest.fixture\ndef num_tasklets() -> int:\n    return 16\n\n\ndef test_parse_asm(parser_path: str, asm_filepaths: Set[str]):\n    assert GrammarGenerator.clean()\n    assert GrammarGenerator.generate()\n\n    for asm_filepath in asm_filepaths:\n        commands = [\"python\", f\"{parser_path}\", \"--file\", f\"{asm_filepath}\"]\n\n        result = subprocess.run(commands, capture_output=True, text=True,)\n\n        if result.stderr != \"\":\n            with open(asm_filepath, encoding=\"ISO-8859-1\") as file:\n                for line in file.readlines():\n                    line = Parser.preprocess(line)\n\n                    commands = [\"python\", f\"{parser_path}\", \"--line\", f\"{line}\"]\n\n                    result = subprocess.run(commands, capture_output=True, text=True,)\n\n                    print(\" \".join(commands))\n                    assert result.stderr == \"\"\n\n\ndef test_parse_bin(parser_path: str, bin_filepaths: Set[str]):\n    assert GrammarGenerator.clean()\n    assert GrammarGenerator.generate()\n\n    for bin_filepath in bin_filepaths:\n        commands = [\"python\", f\"{parser_path}\", \"--file\", f\"{bin_filepath}\"]\n\n        result = subprocess.run(commands, capture_output=True, text=True,)\n\n        if result.stderr != \"\":\n            with open(bin_filepath, encoding=\"ISO-8859-1\") as file:\n                for line in file.readlines():\n                    line = Parser.preprocess(line)\n\n                    commands = [\"python\", f\"{parser_path}\", \"--line\", f\"{line}\"]\n\n                    result = subprocess.run(commands, capture_output=True, text=True,)\n\n                    print(\" \".join(commands))\n                    assert result.stderr == \"\"\n"
  },
  {
    "path": "python_cpp/uPIMulator_frontend/test/util/config_loader_test.py",
    "content": "from util.config_loader import ConfigLoader\n\n\ndef is_overlap(offset1: int, size1: int, offset2: int, size2) -> bool:\n    if offset2 <= offset1 <= offset2 + size2:\n        return True\n    elif offset1 <= offset2 <= offset1 + size1:\n        return True\n    elif offset2 <= offset1 + size1 <= offset2 + size2:\n        return True\n    elif offset1 <= offset2 + size2 <= offset1 + size1:\n        return True\n    else:\n        return False\n\n\ndef test_overlap():\n    atomic_offset = ConfigLoader.atomic_offset()\n    atomic_size = ConfigLoader.atomic_size()\n\n    assert atomic_offset >= 0\n    assert atomic_size > 0\n\n    iram_offset = ConfigLoader.iram_offset()\n    iram_size = ConfigLoader.iram_size()\n\n    assert iram_offset >= 0\n    assert iram_size > 0\n\n    wram_offset = ConfigLoader.wram_offset()\n    wram_size = ConfigLoader.wram_size()\n\n    assert wram_offset >= 0\n    assert wram_size > 0\n\n    mram_offset = ConfigLoader.mram_offset()\n    mram_size = ConfigLoader.mram_size()\n\n    assert mram_offset >= 0\n    assert mram_size > 0\n\n    assert not is_overlap(atomic_offset, atomic_size, iram_offset, iram_size)\n    assert not is_overlap(atomic_offset, atomic_size, wram_offset, wram_size)\n    assert not is_overlap(atomic_offset, atomic_size, mram_offset, mram_size)\n    assert not is_overlap(iram_offset, iram_size, wram_offset, wram_size)\n    assert not is_overlap(iram_offset, iram_size, mram_offset, mram_size)\n    assert not is_overlap(wram_offset, wram_size, mram_offset, mram_size)\n"
  },
  {
    "path": "tools/README.md",
    "content": ""
  },
  {
    "path": "tools/upmem_profiler/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\n#set(CMAKE_CXX_COMPILER \"/opt/rh/devtoolset-8/root/usr/bin/g++\")\nset(CMAKE_CXX_COMPILER \"/usr/bin/g++\")\nset(CMAKE_CXX_STANDARD 20)\nset(CMAKE_CXX_FLAGS \"-O3\")\n#set(CMAKE_CXX_FLAGS  \"-g\")\n\nlink_libraries(stdc++fs)\n\nproject(upmem_profiler)\n\nadd_subdirectory(src)\n"
  },
  {
    "path": "tools/upmem_profiler/script/active_tasklet_profile.sh",
    "content": "#data_size=(32768 2048 128 128 256 524288 65536 65536 524288 1024 2048 524288 524288) # 100ms\n#data_size=(8192 512 32 32 64 131072 16384 16384 131072 256 512 131072 131072)\n# data_size=(1024)\n# idx=0\n\n# #for benchmark in \"BS\" \"GEMV\" \"HST-L\" \"HST-S\" \"MLP\" \"RED\" \"SCAN-RSS\" \"SCAN-SSA\" \"SEL\" \"TRNS\" \"TS\" \"UNI\" \"VA\"\n# for benchmark in \"TRNS\"\n# do\n#     for tasklet in 16\n#     do\n#         eval \"mkdir -p /home/dongjae/new_data_sweep/active_tasklet/${benchmark}/${data_size[${idx}]}/\"\n#         eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}/labels.bin --logpath /home/dongjae/new_data_sweep/trace/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.trace --mode active_tasklet > /home/dongjae/new_data_sweep/active_tasklet/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.txt &\"\n#     done\n#     let \"idx=idx+1\"\n# done\n\n\ncase=$1 # data_sweep_hbm, new_data_sweep\nbenchmark=$2 \ndata_size=$3\n\nfor tasklet in 1 2 4 8 16\ndo\n    echo \"mkdir -p /home/dongjae/${case}/active_tasklet/${benchmark}/${data_size}/\"\n    echo \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${data_size}/${benchmark}.${tasklet}/labels.bin --logpath /home/dongjae/${case}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode active_tasklet > /home/dongjae/${case}/active_tasklet/${benchmark}/${data_size}/${benchmark}.${tasklet}.txt &\"\n    eval \"mkdir -p /home/dongjae/${case}/active_tasklet/${benchmark}/${data_size}/\"\n    eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${data_size}/${benchmark}.${tasklet}/labels.bin --logpath /home/dongjae/${case}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode active_tasklet > /home/dongjae/${case}/active_tasklet/${benchmark}/${data_size}/${benchmark}.${tasklet}.txt &\"\ndone\n\necho \"All profilers are running the server!\""
  },
  {
    "path": "tools/upmem_profiler/script/build.sh",
    "content": "#!/bin/bash\n\nmkdir -p ../build\ncd ../build || exit\n# shellcheck disable=SC2035\nrm -rf *\ncmake ..\nmake -j\ncd - || exit"
  },
  {
    "path": "tools/upmem_profiler/script/example.sh",
    "content": "benchmark=$1\nfor size in 128\ndo\n    eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --num_tasklets 16 --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${size}/${benchmark}.16/labels.bin --logpath /home/dongjae/data_sweep/trace/${benchmark}/${size}/${benchmark}.16.trace --mode instruction_mix > ${benchmark}_${size}.txt &\"\ndone\n"
  },
  {
    "path": "tools/upmem_profiler/script/function_profile.sh",
    "content": "#data_size=(32768 2048 128 128 256 524288 65536 65536 524288 1024 2048 524288 524288)\ndata_size=(32768 2048 128 128 256 524288 524288 1024 2048 524288 524288)\nidx=0\n\nfor benchmark in \"BS\" \"GEMV\" \"HST-L\" \"HST-S\" \"MLP\" \"RED\" \"SEL\" \"TRNS\" \"TS\" \"UNI\" \"VA\" #\"BS\" \"GEMV\" \"HST-L\" \"HST-S\" \"MLP\" \"RED\" \"SCAN-RSS\" \"SCAN-SSA\" \"SEL\" \"TRNS\" \"TS\" \"UNI\" \"VA\"\ndo\n    for tasklet in 1 2 4 8 16\n    do\n        eval \"mkdir -p /home/dongjae/data_sweep/function/${benchmark}/${data_size[${idx}]}/\"\n        eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}/labels.bin --logpath /home/dongjae/data_sweep/trace/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.trace --mode function > /home/dongjae/data_sweep/function/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.txt &\"\n    done\n    let \"idx=idx+1\"\ndone\n\n\necho \"All profilers are running the server!\""
  },
  {
    "path": "tools/upmem_profiler/script/instruction_mix_profile.sh",
    "content": "#/bin/bash\n\ndirectory=$1 # data_sweep_hbm, new_data_sweep\nbenchmark=$2\ndata_size=$3\n\nfor tasklet in 1 2 4 8 16\ndo\n    eval \"mkdir -p /home/dongjae/pimulator/new_experiment_result/${directory}/instruction_mix/${benchmark}/${data_size}/\"\n    echo \"mkdir -p /home/dongjae/pimulator/new_experiment_result/${directory}/instruction_mix/${benchmark}/${data_size}/\"\n    eval \"nohup /home/dongjae/pimulator/tool/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/pimulator/new_experiment_result/${directory}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode instruction_mix > /home/dongjae/pimulator/new_experiment_result/${directory}/instruction_mix/${benchmark}/${data_size}/${benchmark}.${tasklet}.txt &\"\n    echo \"nohup /home/dongjae/pimulator/tool/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/pimulator/new_experiment_result/${directory}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode instruction_mix > /home/dongjae/pimulator/new_experiment_result/${directory}/instruction_mix/${benchmark}/${data_size}/${benchmark}.${tasklet}.txt &\"\ndone"
  },
  {
    "path": "tools/upmem_profiler/script/mram_access_pattern_profile.sh",
    "content": "#/bin/bash\ndirectory=$1 # data_sweep_hbm, new_data_sweep\ncase=$2\nbenchmark=$3 \ndata_size=$4\n\nfor tasklet in 1 2 4 8 16\ndo\n    eval \"mkdir -p /home/dongjae/${directory}/mram_access_pattern/${benchmark}/${data_size}/\"\n    echo \"mkdir -p /home/dongjae/${directory}/mram_access_pattern/${benchmark}/${data_size}/\"\n    eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/${directory}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode mram_access_pattern --case_study ${case} > /home/dongjae/${directory}/mram_access_pattern/${benchmark}/${data_size}/${benchmark}.${tasklet}.csv &\"\n    echo \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/${directory}/trace/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode mram_access_pattern --case_study ${case} > /home/dongjae/${directory}/mram_access_pattern/${benchmark}/${data_size}/${benchmark}.${tasklet}.csv &\"\ndone"
  },
  {
    "path": "tools/upmem_profiler/script/timeline_profile.sh",
    "content": "data_size=(32768 2048 128 128 256 524288 65536 65536 524288 1024 2048 524288 524288)\nidx=0\n\nfor benchmark in \"BS\" \"GEMV\" \"HST-L\" \"HST-S\" \"MLP\" \"RED\" \"SCAN-RSS\" \"SCAN-SSA\" \"SEL\" \"TRNS\" \"TS\" \"UNI\" \"VA\"\ndo\n    for tasklet in 1 2 4 8 16\n    do\n        eval \"mkdir -p /home/dongjae/data_sweep/timeline/${benchmark}/${data_size[${idx}]}/\"\n        eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --labelpath /home/dongjae/data_sweep/bin/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}/labels.bin --logpath /home/dongjae/data_sweep/trace/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.trace --mode timeline > /home/dongjae/data_sweep/timeline/${benchmark}/${data_size[${idx}]}/${benchmark}.${tasklet}.txt &\"\n    done\n    let \"idx=idx+1\"\ndone\n\n\necho \"All profilers are running the server!\""
  },
  {
    "path": "tools/upmem_profiler/script/tlb_behavior_profile.sh",
    "content": "#/bin/bash\ndirectory=$1 # data_sweep_hbm, new_data_sweep\nptw=$2\ntlb_way=$3\ntlb_set=$4\nbenchmark=$5 \ndata_size=$6\n\nfor tasklet in 1 2 4 8 16\ndo\n    eval \"mkdir -p /home/dongjae/${directory}/tlb_behavior/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/\"\n    echo \"mkdir -p /home/dongjae/${directory}/tlb_behavior/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/\"\n    eval \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/${directory}/trace/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode tlb_behavior > /home/dongjae/${directory}/tlb_behavior/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/${benchmark}.${tasklet}.csv &\"\n    echo \"nohup /home/dongjae/upmem_profiler/build/src/upmem_profiler --benchmark ${benchmark} --num_tasklets ${tasklet} --logpath /home/dongjae/${directory}/trace/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/${benchmark}.${tasklet}.trace --mode tlb_behavior > /home/dongjae/${directory}/tlb_behavior/ptw${ptw}_tlbway${tlb_way}_tlbset${tlb_set}/${benchmark}/${data_size}/${benchmark}.${tasklet}.csv &\"\ndone"
  },
  {
    "path": "tools/upmem_profiler/src/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.16)\n\ninclude_directories(.)\n\nfile(GLOB_RECURSE SRCS *.cc)\n\nadd_executable(upmem_profiler ${SRCS})\n"
  },
  {
    "path": "tools/upmem_profiler/src/abi/instruction/op_code.h",
    "content": "#ifndef UPMEM_PROFILER_ABI_INSTRUCTION_OP_CODE_H_\n#define UPMEM_PROFILER_ABI_INSTRUCTION_OP_CODE_H_\n\nnamespace upmem_profiler::abi::instruction {\n\nenum OpCode {\n  ACQUIRE,\n  RELEASE,\n\n  ADD,\n  ADDC,\n  AND,\n  ANDN,\n  ASR,\n  CAO,\n  CLO,\n  CLS,\n  CLZ,\n  CMPB4,\n  DIV_STEP,\n  EXTSB,\n  EXTSH,\n  EXTUB,\n  EXTUH,\n  LSL,\n  LSL_ADD,\n  LSL_SUB,\n  LSL1,\n  LSL1X,\n  LSLX,\n  LSR,\n  LSR_ADD,\n  LSR1,\n  LSR1X,\n  LSRX,\n  MUL_SH_SH,\n  MUL_SH_SL,\n  MUL_SH_UH,\n  MUL_SH_UL,\n  MUL_SL_SH,\n  MUL_SL_SL,\n  MUL_SL_UH,\n  MUL_SL_UL,\n  MUL_STEP,\n  MUL_UH_UH,\n  MUL_UH_UL,\n  MUL_UL_UH,\n  MUL_UL_UL,\n  NAND,\n  NOR,\n  NXOR,\n  OR,\n  ORN,\n  ROL,\n  ROL_ADD,\n  ROR,\n  RSUB,\n  RSUBC,\n  SUB,\n  SUBC,\n  XOR,\n\n  BOOT,\n  RESUME,\n  STOP,\n\n  CALL,\n\n  FAULT,\n  NOP,\n  SATS,\n  MOVD,\n  SWAPD,\n\n  HASH,\n  TIME,\n  TIME_CFG,\n\n  LBS,\n  LBU,\n  LD,\n  LHS,\n  LHU,\n  LW,\n\n  SB,\n  SB_ID,\n  SD,\n  SD_ID,\n  SH,\n  SH_ID,\n  SW,\n  SW_ID,\n\n  LDMA,\n  LDMAI,\n  SDMA\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/abi/instruction/suffix.h",
    "content": "#ifndef UPMEM_PROFILER_ABI_INSTRUCTION_SUFFIX_H_\n#define UPMEM_PROFILER_ABI_INSTRUCTION_SUFFIX_H_\n\nnamespace upmem_profiler::abi::instruction {\n\nenum Suffix {\n  RICI,\n\n  RRI,\n  RRIC,\n  RRICI,\n  RRIF,\n  RRR,\n  RRRC,\n  RRRCI,\n\n  ZRI,\n  ZRIC,\n  ZRICI,\n  ZRIF,\n  ZRR,\n  ZRRC,\n  ZRRCI,\n\n  S_RRI,\n  S_RRIC,\n  S_RRICI,\n  S_RRIF,\n  S_RRR,\n  S_RRRC,\n  S_RRRCI,\n\n  U_RRI,\n  U_RRIC,\n  U_RRICI,\n  U_RRIF,\n  U_RRR,\n  U_RRRC,\n  U_RRRCI,\n\n  RR,\n  RRC,\n  RRCI,\n\n  ZR,\n  ZRC,\n  ZRCI,\n\n  S_RR,\n  S_RRC,\n  S_RRCI,\n\n  U_RR,\n  U_RRC,\n  U_RRCI,\n\n  DRDICI,\n\n  RRRI,\n  RRRICI,\n\n  ZRRI,\n  ZRRICI,\n\n  S_RRRI,\n  S_RRRICI,\n\n  U_RRRI,\n  U_RRRICI,\n\n  RIR,\n  RIRC,\n  RIRCI,\n\n  ZIR,\n  ZIRC,\n  ZIRCI,\n\n  S_RIRC,\n  S_RIRCI,\n\n  U_RIRC,\n  U_RIRCI,\n\n  R,\n  RCI,\n\n  Z,\n  ZCI,\n\n  S_R,\n  S_RCI,\n\n  U_R,\n  U_RCI,\n\n  CI,\n  I,\n\n  DDCI,\n\n  ERRI,\n\n  S_ERRI,\n  U_ERRI,\n\n  EDRI,\n\n  ERII,\n  ERIR,\n  ERID,\n\n  DMA_RRI\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/instruction_parser.cc",
    "content": "#include \"basic/instruction_parser.h\"\n\n#include <algorithm>\n#include <cmath>\n#include <iostream>\n\n#include \"converter/op_code_converter.h\"\n#include \"converter/suffix_converter.h\"\n\nnamespace upmem_profiler::basic {\n\nThreadID InstructionParser::parse_thread_id(std::string line) {\n  int open_bracket_pos = line.find(\"[\");\n  int close_bracket_pos = line.find(\"]\");\n\n  ThreadID thread_id = std::stoi(line.substr(open_bracket_pos + 1, close_bracket_pos - 1));\n  return thread_id;\n}\n\nabi::instruction::OpCode InstructionParser::parse_op_code(std::string line) {\n  int close_bracket_pos = line.find(\"]\");\n\n  std::vector<std::string> tokens = split_by_comma(line.substr(close_bracket_pos + 1));\n  std::string op_code = tokens[0];\n\n  return converter::OpCodeConverter::to_op_code(op_code);\n}\n\nabi::instruction::Suffix InstructionParser::parse_suffix(std::string line) {\n  std::vector<std::string> tokens = split_by_comma(line);\n  std::string suffix = tokens[1];\n\n  return converter::SuffixConverter::to_suffix(suffix);\n}\n\nstd::tuple<ThreadID, Address> InstructionParser::parse_call_rri_instruction(std::string line, RegFile reg_file) {\n  ThreadID thread_id = parse_thread_id(line);\n\n  std::vector<std::string> tokens = split_by_comma(line);\n  std::string ra = tokens[3];\n  int64_t imm = std::stoi(tokens[4]);\n\n  int64_t ra_value = lookup_reg_file(ra, thread_id, reg_file);\n\n  Address callee_address = ra_value + imm;\n\n  return {thread_id, callee_address};\n}\n\nstd::tuple<ThreadID, Address> InstructionParser::parse_call_rrr_instruction(std::string line, RegFile reg_file) {\n  ThreadID thread_id = parse_thread_id(line);\n\n  std::vector<std::string> tokens = split_by_comma(line);\n  std::string ra = tokens[3];\n  std::string rb = tokens[4];\n\n  int64_t ra_value = lookup_reg_file(ra, thread_id, reg_file);\n  int64_t rb_value = lookup_reg_file(rb, thread_id, reg_file);\n\n  Address callee_address = ra_value + rb_value;\n\n  return {thread_id, callee_address};\n}\n\nThreadID InstructionParser::parse_return_instruction(std::string line) { return parse_thread_id(line); }\n\nstd::vector<std::string> InstructionParser::split_by_comma(std::string line) {\n  std::vector<std::string> tokens;\n  int pos;\n  while ((pos = line.find(\",\")) != std::string::npos) {\n    std::string token = line.substr(0, pos);\n\n    if (token.substr(0, 1) == \" \") {\n      token = token.substr(1);\n    }\n\n    line.erase(0, pos + 1);\n    tokens.push_back(token);\n  }\n  tokens.push_back(line);\n  return std::move(tokens);\n}\n\nint64_t InstructionParser::lookup_reg_file(std::string reg, ThreadID thread_id, RegFile reg_file) {\n  if (reg == \"zero\") {\n    return 0;\n  } else if (reg == \"one\") {\n    return 1;\n  } else if (reg == \"lneg\") {\n    return -1;\n  } else if (reg == \"mneg\") {\n    return static_cast<int64_t>(pow(2, 30));\n  } else if (reg == \"id\") {\n    return thread_id;\n  } else if (reg == \"id2\") {\n    return 2 * thread_id;\n  } else if (reg == \"id4\") {\n    return 4 * thread_id;\n  } else if (reg == \"id8\") {\n    return 8 * thread_id;\n  } else if (reg.substr(0, 1) == \"r\") {\n    RegIndex reg_index = std::stoi(reg.substr(1));\n    return reg_file[reg_index];\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n} // namespace upmem_profiler::basic\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/instruction_parser.h",
    "content": "#ifndef UPMEM_PROFILER_BASIC_INSTRUCTION_PASER_H_\n#define UPMEM_PROFILER_BASIC_INSTRUCTION_PASER_H_\n\n#include <map>\n#include <string>\n#include <tuple>\n#include <vector>\n\n#include \"abi/instruction/op_code.h\"\n#include \"abi/instruction/suffix.h\"\n#include \"basic/reg_file_parser.h\"\n#include \"main.h\"\n\nnamespace upmem_profiler::basic {\n\nclass InstructionParser {\npublic:\n  static ThreadID parse_thread_id(std::string line);\n  static abi::instruction::OpCode parse_op_code(std::string line);\n  static abi::instruction::Suffix parse_suffix(std::string line);\n\n  static bool is_instruction(std::string line) {\n    return line.find(\"[\") != std::string::npos and line.find(\"]\") != std::string::npos;\n  }\n  static bool is_call_rri_instruction(std::string line) { return line.find(\"call, rri\") != std::string::npos; }\n  static bool is_call_rrr_instruction(std::string line) { return line.find(\"call, rrr\") != std::string::npos; }\n  static bool is_return_instruction(std::string line) { return line.find(\"call, zri, r23, 0\") != std::string::npos; }\n\n  static std::tuple<ThreadID, Address> parse_call_rri_instruction(std::string line, RegFile reg_file);\n  static std::tuple<ThreadID, Address> parse_call_rrr_instruction(std::string line, RegFile reg_file);\n  static ThreadID parse_return_instruction(std::string line);\n\nprotected:\n  static std::vector<std::string> split_by_comma(std::string line);\n  static int64_t lookup_reg_file(std::string reg, ThreadID thread_id, RegFile reg_file);\n};\n\n} // namespace upmem_profiler::basic\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/interval.cc",
    "content": "#include \"basic/interval.h\"\n\nnamespace upmem_profiler::basic {\n\nStats Interval::stats() {\n  Stats stats;\n  for (auto &[end_stat, end_value] : end_) {\n    if (begin_.count(end_stat)) {\n      stats[end_stat] = end_value - begin_[end_stat];\n    } else {\n      stats[end_stat] = end_value;\n    }\n  }\n  return std::move(stats);\n}\n\n} // namespace upmem_profiler::basic\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/interval.h",
    "content": "#ifndef UPMEM_PROFILER_BASIC_INTERVAL_H_\n#define UPMEM_PROFILER_BASIC_INTERVAL_H_\n\n#include <cstdint>\n\n#include \"basic/stats_parser.h\"\n\nnamespace upmem_profiler::basic {\n\nclass Interval {\npublic:\n  explicit Interval() = default;\n  ~Interval() = default;\n\n  void set_begin(Stats begin) { begin_ = begin; }\n  void set_end(Stats end) { end_ = end; }\n\n  int64_t begin_value(std::string stat) { return begin_[stat]; }\n  int64_t end_value(std::string stat) { return end_[stat]; }\n\n  Stats stats();\n\nprivate:\n  Stats begin_;\n  Stats end_;\n};\n\n} // namespace upmem_profiler::basic\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/reg_file_parser.cc",
    "content": "#include \"basic/reg_file_parser.h\"\n\n#include <iostream>\n\n#include \"util/config_loader.h\"\n\nnamespace upmem_profiler::basic {\n\nstd::map<RegIndex, int64_t> RegFileParser::parse(std::ifstream &ifs) {\n  std::map<RegIndex, int64_t> reg_file;\n  for (RegIndex index = 0; index < util::ConfigLoader::num_gp_registers(); index++) {\n    std::string reg;\n    int64_t value;\n\n    ifs >> reg >> value;\n\n    RegIndex reg_index = std::stoi(reg.substr(1, reg.length() - 1));\n\n    reg_file[reg_index] = value;\n  }\n  return std::move(reg_file);\n}\n\n} // namespace upmem_profiler::basic\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/reg_file_parser.h",
    "content": "#ifndef UPMEM_PROFILER_BASIC_REG_FILE_PARSER_H_\n#define UPMEM_PROFILER_BASIC_REG_FILE_PARSER_H_\n\n#include <fstream>\n#include <map>\n\n#include \"main.h\"\n\nnamespace upmem_profiler::basic {\n\nusing RegFile = std::map<RegIndex, int64_t>;\n\nclass RegFileParser {\npublic:\n  static RegFile parse(std::ifstream &ifs);\n};\n\n} // namespace upmem_profiler::basic\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/stats_parser.cc",
    "content": "#include \"basic/stats_parser.h\"\n\n#include <fstream>\n#include <vector>\n\nnamespace upmem_profiler::basic {\n\nStats StatsParser::parse(std::ifstream &ifs) {\n  Stats stats;\n\n  while (true) {\n    std::string line;\n    std::getline(ifs, line);\n\n    if (line == \"\") {\n      break;\n    }\n\n    std::vector<std::string> tokens = split_by_colon(line);\n\n    if (tokens.size() == 2) {\n      std::string stat = tokens[0];\n      int64_t value = std::stoi(tokens[1]);\n\n      stats[stat] = value;\n    }\n  }\n\n  return std::move(stats);\n}\n\nstd::vector<std::string> StatsParser::split_by_colon(std::string line) {\n  std::vector<std::string> tokens;\n  int pos;\n  while ((pos = line.find(\":\")) != std::string::npos) {\n    std::string token = line.substr(0, pos);\n\n    if (token.substr(0, 1) == \" \") {\n      token = token.substr(1);\n    }\n\n    line.erase(0, pos + 1);\n    tokens.push_back(token);\n  }\n  tokens.push_back(line);\n  return std::move(tokens);\n}\n\n} // namespace upmem_profiler::basic\n"
  },
  {
    "path": "tools/upmem_profiler/src/basic/stats_parser.h",
    "content": "#ifndef UPMEM_PROFILER_BASIC_STATS_PARSER_H_\n#define UPMEM_PROFILER_BASIC_STATS_PARSER_H_\n\n#include <map>\n#include <set>\n#include <string>\n#include <vector>\n\nnamespace upmem_profiler::basic {\n\nusing Stats = std::map<std::string, int64_t>;\n\nclass StatsParser {\npublic:\n  static Stats parse(std::ifstream &ifs);\n\nprotected:\n  static std::vector<std::string> split_by_colon(std::string line);\n\nprivate:\n  std::set<std::string> stats_;\n};\n\n} // namespace upmem_profiler::basic\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/converter/op_code_converter.cc",
    "content": "#include \"converter/op_code_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_profiler::converter {\n\nabi::instruction::OpCode OpCodeConverter::to_op_code(std::string op_code) {\n  if (op_code == \"acquire\") {\n    return abi::instruction::ACQUIRE;\n  } else if (op_code == \"release\") {\n    return abi::instruction::RELEASE;\n  } else if (op_code == \"add\") {\n    return abi::instruction::ADD;\n  } else if (op_code == \"addc\") {\n    return abi::instruction::ADDC;\n  } else if (op_code == \"and\") {\n    return abi::instruction::AND;\n  } else if (op_code == \"andn\") {\n    return abi::instruction::ANDN;\n  } else if (op_code == \"asr\") {\n    return abi::instruction::ASR;\n  } else if (op_code == \"cao\") {\n    return abi::instruction::CAO;\n  } else if (op_code == \"clo\") {\n    return abi::instruction::CLO;\n  } else if (op_code == \"cls\") {\n    return abi::instruction::CLS;\n  } else if (op_code == \"clz\") {\n    return abi::instruction::CLZ;\n  } else if (op_code == \"cmpb4\") {\n    return abi::instruction::CMPB4;\n  } else if (op_code == \"div_step\") {\n    return abi::instruction::DIV_STEP;\n  } else if (op_code == \"extsb\") {\n    return abi::instruction::EXTSB;\n  } else if (op_code == \"extsh\") {\n    return abi::instruction::EXTSH;\n  } else if (op_code == \"extub\") {\n    return abi::instruction::EXTUB;\n  } else if (op_code == \"extuh\") {\n    return abi::instruction::EXTUH;\n  } else if (op_code == \"lsl\") {\n    return abi::instruction::LSL;\n  } else if (op_code == \"lsl_add\") {\n    return abi::instruction::LSL_ADD;\n  } else if (op_code == \"lsl_sub\") {\n    return abi::instruction::LSL_SUB;\n  } else if (op_code == \"lsl1\") {\n    return abi::instruction::LSL1;\n  } else if (op_code == \"lsl1x\") {\n    return abi::instruction::LSL1X;\n  } else if (op_code == \"lslx\") {\n    return abi::instruction::LSLX;\n  } else if (op_code == \"lsr\") {\n    return abi::instruction::LSR;\n  } else if (op_code == \"lsr_add\") {\n    return abi::instruction::LSR_ADD;\n  } else if (op_code == \"lsr1\") {\n    return abi::instruction::LSR1;\n  } else if (op_code == \"lsr1x\") {\n    return abi::instruction::LSR1X;\n  } else if (op_code == \"lsrx\") {\n    return abi::instruction::LSRX;\n  } else if (op_code == \"mul_sh_sh\") {\n    return abi::instruction::MUL_SH_SH;\n  } else if (op_code == \"mul_sh_sl\") {\n    return abi::instruction::MUL_SH_SL;\n  } else if (op_code == \"mul_sh_uh\") {\n    return abi::instruction::MUL_SH_UH;\n  } else if (op_code == \"mul_sh_ul\") {\n    return abi::instruction::MUL_SH_UL;\n  } else if (op_code == \"mul_sl_sh\") {\n    return abi::instruction::MUL_SL_SH;\n  } else if (op_code == \"mul_sl_sl\") {\n    return abi::instruction::MUL_SL_SL;\n  } else if (op_code == \"mul_sl_uh\") {\n    return abi::instruction::MUL_SL_UH;\n  } else if (op_code == \"mul_sl_ul\") {\n    return abi::instruction::MUL_SL_UL;\n  } else if (op_code == \"mul_step\") {\n    return abi::instruction::MUL_STEP;\n  } else if (op_code == \"mul_uh_uh\") {\n    return abi::instruction::MUL_UH_UH;\n  } else if (op_code == \"mul_uh_ul\") {\n    return abi::instruction::MUL_UH_UL;\n  } else if (op_code == \"mul_ul_uh\") {\n    return abi::instruction::MUL_UL_UH;\n  } else if (op_code == \"mul_ul_ul\") {\n    return abi::instruction::MUL_UL_UL;\n  } else if (op_code == \"nand\") {\n    return abi::instruction::NAND;\n  } else if (op_code == \"nor\") {\n    return abi::instruction::NOR;\n  } else if (op_code == \"nxor\") {\n    return abi::instruction::NXOR;\n  } else if (op_code == \"or\") {\n    return abi::instruction::OR;\n  } else if (op_code == \"orn\") {\n    return abi::instruction::ORN;\n  } else if (op_code == \"rol\") {\n    return abi::instruction::ROL;\n  } else if (op_code == \"rol_add\") {\n    return abi::instruction::ROL_ADD;\n  } else if (op_code == \"ror\") {\n    return abi::instruction::ROR;\n  } else if (op_code == \"rsub\") {\n    return abi::instruction::RSUB;\n  } else if (op_code == \"rsubc\") {\n    return abi::instruction::RSUBC;\n  } else if (op_code == \"sub\") {\n    return abi::instruction::SUB;\n  } else if (op_code == \"subc\") {\n    return abi::instruction::SUBC;\n  } else if (op_code == \"xor\") {\n    return abi::instruction::XOR;\n  } else if (op_code == \"boot\") {\n    return abi::instruction::BOOT;\n  } else if (op_code == \"resume\") {\n    return abi::instruction::RESUME;\n  } else if (op_code == \"stop\") {\n    return abi::instruction::STOP;\n  } else if (op_code == \"call\") {\n    return abi::instruction::CALL;\n  } else if (op_code == \"fault\") {\n    return abi::instruction::FAULT;\n  } else if (op_code == \"nop\") {\n    return abi::instruction::NOP;\n  } else if (op_code == \"sats\") {\n    return abi::instruction::SATS;\n  } else if (op_code == \"movd\") {\n    return abi::instruction::MOVD;\n  } else if (op_code == \"swapd\") {\n    return abi::instruction::SWAPD;\n  } else if (op_code == \"hash\") {\n    return abi::instruction::HASH;\n  } else if (op_code == \"time\") {\n    return abi::instruction::TIME;\n  } else if (op_code == \"time_cfg\") {\n    return abi::instruction::TIME_CFG;\n  } else if (op_code == \"lbs\") {\n    return abi::instruction::LBS;\n  } else if (op_code == \"lbu\") {\n    return abi::instruction::LBU;\n  } else if (op_code == \"ld\") {\n    return abi::instruction::LD;\n  } else if (op_code == \"lhs\") {\n    return abi::instruction::LHS;\n  } else if (op_code == \"lhu\") {\n    return abi::instruction::LHU;\n  } else if (op_code == \"lw\") {\n    return abi::instruction::LW;\n  } else if (op_code == \"sb\") {\n    return abi::instruction::SB;\n  } else if (op_code == \"sb_id\") {\n    return abi::instruction::SB_ID;\n  } else if (op_code == \"sd\") {\n    return abi::instruction::SD;\n  } else if (op_code == \"sd_id\") {\n    return abi::instruction::SD_ID;\n  } else if (op_code == \"sh\") {\n    return abi::instruction::SH;\n  } else if (op_code == \"SH_ID\") {\n    return abi::instruction::SH_ID;\n  } else if (op_code == \"sw\") {\n    return abi::instruction::SW;\n  } else if (op_code == \"sw_id\") {\n    return abi::instruction::SW_ID;\n  } else if (op_code == \"ldma\") {\n    return abi::instruction::LDMA;\n  } else if (op_code == \"ldmai\") {\n    return abi::instruction::LDMAI;\n  } else if (op_code == \"sdma\") {\n    return abi::instruction::SDMA;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n} // namespace upmem_profiler::converter\n"
  },
  {
    "path": "tools/upmem_profiler/src/converter/op_code_converter.h",
    "content": "#ifndef UPMEM_PROFILER_CONVERTER_OP_CODE_CONVERTER_H_\n#define UPMEM_PROFILER_CONVERTER_OP_CODE_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/instruction/op_code.h\"\n\nnamespace upmem_profiler::converter {\n\nclass OpCodeConverter {\npublic:\n  static abi::instruction::OpCode to_op_code(std::string op_code);\n};\n\n} // namespace upmem_profiler::converter\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/converter/suffix_converter.cc",
    "content": "#include \"converter/suffix_converter.h\"\n\n#include <stdexcept>\n\nnamespace upmem_profiler::converter {\n\nabi::instruction::Suffix SuffixConverter::to_suffix(std::string suffix) {\n  if (suffix == \"rici\") {\n    return abi::instruction::RICI;\n  } else if (suffix == \"rri\") {\n    return abi::instruction::RRI;\n  } else if (suffix == \"rric\") {\n    return abi::instruction::RRIC;\n  } else if (suffix == \"rrici\") {\n    return abi::instruction::RRICI;\n  } else if (suffix == \"rrif\") {\n    return abi::instruction::RRIF;\n  } else if (suffix == \"rrr\") {\n    return abi::instruction::RRR;\n  } else if (suffix == \"rrrc\") {\n    return abi::instruction::RRRC;\n  } else if (suffix == \"rrrci\") {\n    return abi::instruction::RRRCI;\n  } else if (suffix == \"zri\") {\n    return abi::instruction::ZRI;\n  } else if (suffix == \"zric\") {\n    return abi::instruction::ZRIC;\n  } else if (suffix == \"zrici\") {\n    return abi::instruction::ZRICI;\n  } else if (suffix == \"zrif\") {\n    return abi::instruction::ZRIF;\n  } else if (suffix == \"zrr\") {\n    return abi::instruction::ZRR;\n  } else if (suffix == \"zrrc\") {\n    return abi::instruction::ZRRC;\n  } else if (suffix == \"zrrci\") {\n    return abi::instruction::ZRRCI;\n  } else if (suffix == \"s_rri\") {\n    return abi::instruction::S_RRI;\n  } else if (suffix == \"s_rric\") {\n    return abi::instruction::S_RRIC;\n  } else if (suffix == \"s_rrici\") {\n    return abi::instruction::S_RRICI;\n  } else if (suffix == \"s_rrif\") {\n    return abi::instruction::S_RRIF;\n  } else if (suffix == \"s_rrr\") {\n    return abi::instruction::S_RRR;\n  } else if (suffix == \"s_rrrc\") {\n    return abi::instruction::S_RRRC;\n  } else if (suffix == \"s_rrrci\") {\n    return abi::instruction::S_RRRCI;\n  } else if (suffix == \"u_rri\") {\n    return abi::instruction::U_RRI;\n  } else if (suffix == \"u_rric\") {\n    return abi::instruction::U_RRIC;\n  } else if (suffix == \"u_rrici\") {\n    return abi::instruction::U_RRICI;\n  } else if (suffix == \"u_rrif\") {\n    return abi::instruction::U_RRIF;\n  } else if (suffix == \"u_rrr\") {\n    return abi::instruction::U_RRR;\n  } else if (suffix == \"u_rrrc\") {\n    return abi::instruction::U_RRRC;\n  } else if (suffix == \"u_rrrci\") {\n    return abi::instruction::U_RRRCI;\n  } else if (suffix == \"rr\") {\n    return abi::instruction::RR;\n  } else if (suffix == \"rrc\") {\n    return abi::instruction::RRC;\n  } else if (suffix == \"rrci\") {\n    return abi::instruction::RRCI;\n  } else if (suffix == \"zr\") {\n    return abi::instruction::ZR;\n  } else if (suffix == \"zrc\") {\n    return abi::instruction::ZRC;\n  } else if (suffix == \"zrci\") {\n    return abi::instruction::ZRCI;\n  } else if (suffix == \"s_rr\") {\n    return abi::instruction::S_RR;\n  } else if (suffix == \"s_rrc\") {\n    return abi::instruction::S_RRC;\n  } else if (suffix == \"s_rrci\") {\n    return abi::instruction::S_RRCI;\n  } else if (suffix == \"u_rr\") {\n    return abi::instruction::U_RR;\n  } else if (suffix == \"u_rrc\") {\n    return abi::instruction::U_RRC;\n  } else if (suffix == \"u_rrci\") {\n    return abi::instruction::U_RRCI;\n  } else if (suffix == \"drdici\") {\n    return abi::instruction::DRDICI;\n  } else if (suffix == \"rrri\") {\n    return abi::instruction::RRRI;\n  } else if (suffix == \"rrrici\") {\n    return abi::instruction::RRRICI;\n  } else if (suffix == \"zrri\") {\n    return abi::instruction::ZRRI;\n  } else if (suffix == \"zrrici\") {\n    return abi::instruction::ZRRICI;\n  } else if (suffix == \"s_rrri\") {\n    return abi::instruction::S_RRRI;\n  } else if (suffix == \"s_rrrici\") {\n    return abi::instruction::S_RRRICI;\n  } else if (suffix == \"u_rrri\") {\n    return abi::instruction::U_RRRI;\n  } else if (suffix == \"u_rrrici\") {\n    return abi::instruction::U_RRRICI;\n  } else if (suffix == \"rir\") {\n    return abi::instruction::RIR;\n  } else if (suffix == \"rirc\") {\n    return abi::instruction::RIRC;\n  } else if (suffix == \"rirci\") {\n    return abi::instruction::RIRCI;\n  } else if (suffix == \"zir\") {\n    return abi::instruction::ZIR;\n  } else if (suffix == \"zirc\") {\n    return abi::instruction::ZIRC;\n  } else if (suffix == \"zirci\") {\n    return abi::instruction::ZIRCI;\n  } else if (suffix == \"s_rirc\") {\n    return abi::instruction::S_RIRC;\n  } else if (suffix == \"s_rirci\") {\n    return abi::instruction::S_RIRCI;\n  } else if (suffix == \"u_rirc\") {\n    return abi::instruction::U_RIRC;\n  } else if (suffix == \"u_rirci\") {\n    return abi::instruction::U_RIRCI;\n  } else if (suffix == \"r\") {\n    return abi::instruction::R;\n  } else if (suffix == \"rci\") {\n    return abi::instruction::RCI;\n  } else if (suffix == \"z\") {\n    return abi::instruction::Z;\n  } else if (suffix == \"zci\") {\n    return abi::instruction::ZCI;\n  } else if (suffix == \"s_r\") {\n    return abi::instruction::S_R;\n  } else if (suffix == \"s_rci\") {\n    return abi::instruction::S_RCI;\n  } else if (suffix == \"u_r\") {\n    return abi::instruction::U_R;\n  } else if (suffix == \"u_rci\") {\n    return abi::instruction::U_RCI;\n  } else if (suffix == \"ci\") {\n    return abi::instruction::CI;\n  } else if (suffix == \"i\") {\n    return abi::instruction::I;\n  } else if (suffix == \"ddci\") {\n    return abi::instruction::DDCI;\n  } else if (suffix == \"erri\") {\n    return abi::instruction::ERRI;\n  } else if (suffix == \"s_erri\") {\n    return abi::instruction::S_ERRI;\n  } else if (suffix == \"u_erri\") {\n    return abi::instruction::U_ERRI;\n  } else if (suffix == \"edri\") {\n    return abi::instruction::EDRI;\n  } else if (suffix == \"erii\") {\n    return abi::instruction::ERII;\n  } else if (suffix == \"erir\") {\n    return abi::instruction::ERIR;\n  } else if (suffix == \"erid\") {\n    return abi::instruction::ERID;\n  } else if (suffix == \"dma_rri\") {\n    return abi::instruction::DMA_RRI;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n}\n\n} // namespace upmem_profiler::converter\n"
  },
  {
    "path": "tools/upmem_profiler/src/converter/suffix_converter.h",
    "content": "#ifndef UPMEM_PROFILER_CONVERTER_SUFFIX_CONVERTER_H_\n#define UPMEM_PROFILER_CONVERTER_SUFFIX_CONVERTER_H_\n\n#include <string>\n\n#include \"abi/instruction/suffix.h\"\n\nnamespace upmem_profiler::converter {\n\nclass SuffixConverter {\npublic:\n  static abi::instruction::Suffix to_suffix(std::string suffix);\n};\n\n} // namespace upmem_profiler::converter\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/instruction_mix/instruction_mix_profiler.cc",
    "content": "#include \"instruction_mix/instruction_mix_profiler.h\"\n\n#include <cassert>\n#include <fstream>\n#include <iostream>\n\n#include \"basic/instruction_parser.h\"\n\nnamespace upmem_profiler::instruciton_mix {\n\nInstructionMixProfiler::InstructionMixProfiler(util::ArgumentParser *argument_parser) {\n  std::string log_file = argument_parser->get_string_parameter(\"logpath\");\n  instructions_.resize(argument_parser->get_int_parameter(\"num_tasklets\"));\n\n  total_inst_cnt_ = 0;\n\n  std::ifstream ifs(log_file);\n  std::string line;\n  while (std::getline(ifs, line)) {\n    if (basic::InstructionParser::is_instruction(line)) {\n      ThreadID thread_id = basic::InstructionParser::parse_thread_id(line);\n      abi::instruction::OpCode op_code = basic::InstructionParser::parse_op_code(line);\n      abi::instruction::Suffix suffix = basic::InstructionParser::parse_suffix(line);\n\n      instructions_[thread_id].push_back({op_code, suffix});\n      total_inst_cnt_++;\n    }\n\n  }\n\n  register_mix(\"synchronization\", abi::instruction::ACQUIRE, abi::instruction::RICI);\n  register_mix(\"synchronization\", abi::instruction::RELEASE, abi::instruction::RICI);\n\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::RRRCI);\n  //register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::); // add:ssi\n  //register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::); // add:sss\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADD, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADD, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ADDC, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ADDC, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::ZRRCI);\n  //register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::); // and.s:rki\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::S_RRRCI);\n  //register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::); // and.u:rki\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::AND, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::AND, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ANDN, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ANDN, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ASR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ASR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CAO, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CAO, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CAO, abi::instruction::S_RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::CAO, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CAO, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLO, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLO, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLO, abi::instruction::S_RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLO, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLO, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLS, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLS, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLS, abi::instruction::S_RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLS, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLS, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLZ, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLZ, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLZ, abi::instruction::S_RRCI);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::CLZ, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CLZ, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CMPB4, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CMPB4, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CMPB4, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::CMPB4, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::CMPB4, abi::instruction::U_RRRCI);\n\n\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::DIV_STEP, abi::instruction::DRDICI);\n\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSB, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSB, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSB, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSB, abi::instruction::S_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSH, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSH, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::S_RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTSH, abi::instruction::S_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTSH, abi::instruction::S_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUB, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUB, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUB, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUB, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUH, abi::instruction::RRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::ZR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::ZRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUH, abi::instruction::ZRCI);\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::U_RR);\n  register_mix(\"arithmetic\", abi::instruction::EXTUH, abi::instruction::U_RRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::EXTUH, abi::instruction::U_RRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSL_ADD, abi::instruction::RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_ADD, abi::instruction::RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_ADD, abi::instruction::ZRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_ADD, abi::instruction::ZRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_ADD, abi::instruction::S_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_ADD, abi::instruction::S_RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_ADD, abi::instruction::U_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_ADD, abi::instruction::U_RRRICI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSL_SUB, abi::instruction::RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_SUB, abi::instruction::RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_SUB, abi::instruction::ZRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_SUB, abi::instruction::ZRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_SUB, abi::instruction::S_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_SUB, abi::instruction::S_RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL_SUB, abi::instruction::U_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL_SUB, abi::instruction::U_RRRICI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSL1X, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSL1X, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSLX, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSLX, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSR_ADD, abi::instruction::RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR_ADD, abi::instruction::RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR_ADD, abi::instruction::ZRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR_ADD, abi::instruction::ZRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR_ADD, abi::instruction::S_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR_ADD, abi::instruction::S_RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR_ADD, abi::instruction::U_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR_ADD, abi::instruction::U_RRRICI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSR1X, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSR1X, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::LSRX, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::LSRX, abi::instruction::U_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SH, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SH, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_SL, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_SL, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UH, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UH, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SH_UL, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SH_UL, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SH, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SH, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_SL, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_SL, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UH, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UH, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::S_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_SL_UL, abi::instruction::S_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_SL_UL, abi::instruction::S_RRRCI);\n\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_STEP, abi::instruction::DRDICI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::U_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UH, abi::instruction::U_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UH, abi::instruction::U_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::U_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UH_UL, abi::instruction::U_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UH_UL, abi::instruction::U_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UH, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UH, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::U_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UH, abi::instruction::U_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UH, abi::instruction::U_RRRCI);\n\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UL, abi::instruction::RRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::ZRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::ZRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UL, abi::instruction::ZRRCI);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::U_RRR);\n  register_mix(\"heavy_arithmetic\", abi::instruction::MUL_UL_UL, abi::instruction::U_RRRC);\n  register_mix(\"heavy_arithmetic_and_cond_branch\", abi::instruction::MUL_UL_UL, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NAND, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NAND, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NOR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NOR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::NXOR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::NXOR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::OR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::OR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ORN, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ORN, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROL, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::ROL_ADD, abi::instruction::RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL_ADD, abi::instruction::RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL_ADD, abi::instruction::ZRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL_ADD, abi::instruction::ZRRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL_ADD, abi::instruction::S_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL_ADD, abi::instruction::S_RRRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROL_ADD, abi::instruction::U_RRRI);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROL_ADD, abi::instruction::U_RRRICI);\n\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::S_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::U_RRI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::ROR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::ROR, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUB, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUB, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUB, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUB, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUB, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUBC, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUBC, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUBC, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::RSUBC, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::RSUBC, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RIR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::); //sub:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::RRRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::); // sub:ssi\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::); // sub:sss\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZIR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::ZIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::); // sub:zirf\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::S_RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::S_RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::); // sub.s:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::U_RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RIRF); // sub.u:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUB, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUB, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RIR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::); //sub:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZIR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::ZIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::); // sub:zirf\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::S_RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::S_RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::); // sub.s:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RIRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::U_RIRCI);\n  //register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RIRF); // sub.u:rirf\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::SUBC, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::SUBC, abi::instruction::U_RRRCI);\n\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::RRI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::RRICI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::RRIF);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::RRR);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::ZRI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::ZRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::ZRICI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::ZRIF);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::ZRR);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::ZRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::ZRRCI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::S_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::S_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::S_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::S_RRR);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::S_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::S_RRRCI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::U_RRIC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::U_RRICI);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::U_RRIF);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::U_RRR);\n  register_mix(\"arithmetic\", abi::instruction::XOR, abi::instruction::U_RRRC);\n  register_mix(\"arithmetic_and_cond_branch\", abi::instruction::XOR, abi::instruction::U_RRRCI);\n\n  register_mix(\"system\", abi::instruction::BOOT, abi::instruction::RICI);\n  register_mix(\"system\", abi::instruction::RESUME, abi::instruction::RICI);\n  register_mix(\"system\", abi::instruction::STOP, abi::instruction::CI);\n  register_mix(\"system\", abi::instruction::FAULT, abi::instruction::I);\n\n  register_mix(\"system\", abi::instruction::TIME, abi::instruction::R);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME, abi::instruction::RCI);\n  register_mix(\"system\", abi::instruction::TIME, abi::instruction::Z);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME, abi::instruction::ZCI);\n  register_mix(\"system\", abi::instruction::TIME, abi::instruction::S_R);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME, abi::instruction::S_RCI);\n  register_mix(\"system\", abi::instruction::TIME, abi::instruction::U_R);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME, abi::instruction::U_RCI);\n\n  register_mix(\"system\", abi::instruction::TIME_CFG, abi::instruction::RR);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME_CFG, abi::instruction::RRCI);\n  register_mix(\"system\", abi::instruction::TIME_CFG, abi::instruction::ZR);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME_CFG, abi::instruction::ZRCI);\n  register_mix(\"system\", abi::instruction::TIME_CFG, abi::instruction::S_RR);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME_CFG, abi::instruction::S_RRCI);\n  register_mix(\"system\", abi::instruction::TIME_CFG, abi::instruction::U_RR);\n  register_mix(\"system_and_cond_branch\", abi::instruction::TIME_CFG, abi::instruction::U_RRCI);\n\n  //register_mix(\"nop\", abi::instruction::NOP, \"\");\n\n  register_mix(\"call\", abi::instruction::CALL, abi::instruction::RRI);\n  register_mix(\"call\", abi::instruction::CALL, abi::instruction::RRR);\n  register_mix(\"call\", abi::instruction::CALL, abi::instruction::ZRI);\n  register_mix(\"call\", abi::instruction::CALL, abi::instruction::ZRR);\n\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::RR);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::RRC);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::RRCI);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::ZR);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::ZRC);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::ZRCI);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::S_RR);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::S_RRC);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::S_RRCI);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::U_RR);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::U_RRC);\n  register_mix(\"sats\", abi::instruction::SATS, abi::instruction::U_RRCI);\n\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::RRIC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::RRICI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::RRIF);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::RRR);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::RRRC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::RRRCI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::ZRIC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::ZRICI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::ZRIF);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::ZRR);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::ZRRC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::ZRRCI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::S_RRIC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::S_RRICI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::S_RRIF);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::S_RRR);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::S_RRRC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::S_RRRCI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::U_RRIC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::U_RRICI);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::U_RRIF);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::U_RRR);\n  register_mix(\"hash\", abi::instruction::HASH, abi::instruction::U_RRRC);\n  register_mix(\"hash_and_cond_branch\", abi::instruction::HASH, abi::instruction::U_RRRCI);\n  \n  //register_mix(\"reg_move_and_cond_branch\", abi::instruction::MOVD, abi::instruction::RRCI);\n  register_mix(\"reg_move_and_cond_branch\", abi::instruction::MOVD, abi::instruction::DDCI);\n  register_mix(\"reg_move_and_cond_branch\", abi::instruction::SWAPD, abi::instruction::RRCI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::LBS, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LBS, abi::instruction::EDRI);// lbs:ersi\n  register_mix(\"scratchpad_access\", abi::instruction::LBS, abi::instruction::S_ERRI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::LBU, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LBU, abi::instruction::EDRI); // lbu:ersi\n  register_mix(\"scratchpad_access\", abi::instruction::LBU, abi::instruction::U_ERRI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::LD, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LD, abi::instruction::EDRI); // ld:ersi\n\n  register_mix(\"scratchpad_access\", abi::instruction::LHS, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LHS, abi::instruction::EDRI); // lhs:ersi\n  register_mix(\"scratchpad_access\", abi::instruction::LHS, abi::instruction::S_ERRI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::LHU, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LHU, abi::instruction::EDRI); // lhu:ersi\n  register_mix(\"scratchpad_access\", abi::instruction::LHU, abi::instruction::U_ERRI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::LW, abi::instruction::ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LW, abi::instruction::EDRI); // lw:ersi\n  register_mix(\"scratchpad_access\", abi::instruction::LW, abi::instruction::S_ERRI);\n  register_mix(\"scratchpad_access\", abi::instruction::LW, abi::instruction::U_ERRI);\n\n  register_mix(\"scratchpad_access\", abi::instruction::SB, abi::instruction::ERII);\n  register_mix(\"scratchpad_access\", abi::instruction::SB, abi::instruction::ERIR);\n  //register_mix(\"scratchpad_access\", abi::instruction::SB, abi::instruction::ESII); // sb:esii\n  register_mix(\"scratchpad_access\", abi::instruction::SB, abi::instruction::ERID); // sb:esir\n\n  register_mix(\"scratchpad_access\", abi::instruction::SB_ID, abi::instruction::ERII);\n\n  register_mix(\"scratchpad_access\", abi::instruction::SD, abi::instruction::ERII);\n  register_mix(\"scratchpad_access\", abi::instruction::SD, abi::instruction::ERIR);\n  //register_mix(\"scratchpad_access\", abi::instruction::SD, abi::instruction::); // sd:esii\n  register_mix(\"scratchpad_access\", abi::instruction::SD, abi::instruction::ERID); // sd:esir\n\n  register_mix(\"scratchpad_access\", abi::instruction::SD_ID, abi::instruction::ERII);\n\n  register_mix(\"scratchpad_access\", abi::instruction::SH, abi::instruction::ERII);\n  register_mix(\"scratchpad_access\", abi::instruction::SH, abi::instruction::ERIR);\n  //register_mix(\"scratchpad_access\", abi::instruction::SH, abi::instruction::); // sh:esii\n  register_mix(\"scratchpad_access\", abi::instruction::SH, abi::instruction::ERID); // sh:esir\n\n  register_mix(\"scratchpad_access\", abi::instruction::SH_ID, abi::instruction::ERII);\n\n  register_mix(\"scratchpad_access\", abi::instruction::SW, abi::instruction::ERII);\n  register_mix(\"scratchpad_access\", abi::instruction::SW, abi::instruction::ERIR);\n  //register_mix(\"scratchpad_access\", abi::instruction::SW, abi::instruction::); // sw:esii\n  register_mix(\"scratchpad_access\", abi::instruction::SW, abi::instruction::ERID); // sw:esir\n\n  register_mix(\"scratchpad_access\", abi::instruction::SW_ID, abi::instruction::ERII);\n\n  register_mix(\"mainmemory_access\", abi::instruction::LDMA, abi::instruction::DMA_RRI);\n  register_mix(\"mainmemory_access\", abi::instruction::LDMAI, abi::instruction::DMA_RRI);\n  register_mix(\"mainmemory_access\", abi::instruction::SDMA, abi::instruction::DMA_RRI);\n\n}\n\nvoid InstructionMixProfiler::register_mix(std::string mix, abi::instruction::OpCode op_code,\n                                          abi::instruction::Suffix suffix) {\n  assert(mix != \"etc\");\n\n  mixes_[mix].insert({op_code, suffix});\n}\n\nvoid InstructionMixProfiler::profile() {\n  std::vector<std::map<std::string, int64_t>> instruction_mixes;\n  //auto dbg = instructions_;\n  instruction_mixes.resize(instructions_.size());\n  for (ThreadID thread_id = 0; thread_id < instructions_.size(); thread_id++) {\n    uint64_t non_etc_count = 0;\n    for (auto &[op_code, suffix] : instructions_[thread_id]) {\n      bool dbg_flag = false;\n      for (auto &[mix, mix_specs] : mixes_) {\n        for (auto &mix_spec : mix_specs) {\n          auto [mix_op_code, mix_suffix] = mix_spec;\n          if (op_code == mix_op_code and suffix == mix_suffix) {\n            instruction_mixes[thread_id][mix]++;\n            non_etc_count++;\n            dbg_flag = true;\n          }\n        }\n        //instruction_mixes[thread_id][\"etc\"] = instructions_[thread_id].size() - non_etc_count;\n      }\n      if (dbg_flag == false) {\n        std::cout << op_code << \" \" << suffix << std::endl;\n      }\n    }\n    instruction_mixes[thread_id][\"etc\"] = instructions_[thread_id].size() - non_etc_count;\n  }\n\n  // for (ThreadID thread_id = 0; thread_id < instruction_mixes.size(); thread_id++) {\n  //   std::cout << \"ThreadID: \" << thread_id << std::endl;\n\n  //   for (auto &[mix, count] : instruction_mixes[thread_id]) {\n  //     std::cout << thread_id  << \"_\" <<mix << \": \" << count << std::endl;\n  //   }\n\n  //   std::cout << std::endl;\n  // }\n\n  std::cout << \"INSTRUCTION_MIX: \" << std::endl;\n\n  for (auto &type_ : inst_type_) {\n    uint64_t cnt_inst = 0;\n    for (ThreadID thread_id = 0; thread_id < instruction_mixes.size(); thread_id++) { \n      cnt_inst += instruction_mixes[thread_id][type_];\n    }\n    std::cout << type_ << \",\" << ((double)cnt_inst / (double)total_inst_cnt_) << std::endl;\n  }\n}\n\n} // namespace upmem_profiler::instruciton_mix\n"
  },
  {
    "path": "tools/upmem_profiler/src/instruction_mix/instruction_mix_profiler.h",
    "content": "#ifndef UPMEM_PROFILER_INSTRUCTION_MIX_INSTRUCTION_MIX_PROFILER_H_\n#define UPMEM_PROFILER_INSTRUCTION_MIX_INSTRUCTION_MIX_PROFILER_H_\n\n#include <map>\n#include <set>\n#include <string>\n#include <tuple>\n#include <vector>\n\n#include \"abi/instruction/op_code.h\"\n#include \"abi/instruction/suffix.h\"\n#include \"main.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_profiler::instruciton_mix {\n\nclass InstructionMixProfiler {\npublic:\n  explicit InstructionMixProfiler(util::ArgumentParser *argument_parser);\n  ~InstructionMixProfiler() = default;\n\n  void register_mix(std::string mix, abi::instruction::OpCode op_code, abi::instruction::Suffix suffix);\n\n  void profile();\n\nprivate:\n  std::map<std::string, std::set<std::tuple<abi::instruction::OpCode, abi::instruction::Suffix>>> mixes_;\n  std::vector<std::vector<std::tuple<abi::instruction::OpCode, abi::instruction::Suffix>>> instructions_;\n  std::vector<std::string> inst_type_{\"arithmetic\", \"arithmetic_and_cond_branch\", \"heavy_arithmetic\", \"heavy_arithmetic_and_cond_branch\",\n    \"system\", \"system_and_cond_branch\", \"call\", \"reg_move_and_cond_branch\", \"scratchpad_access\", \"mainmemory_access\", \"synchronization\"};\n  \n  uint64_t total_inst_cnt_;\n};\n\n} // namespace upmem_profiler::instruciton_mix\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/main.cc",
    "content": "#include <iostream>\n\n#include \"instruction_mix/instruction_mix_profiler.h\"\n#include \"util/argument_parser.h\"\n\nnamespace upmem_profiler {\n\nutil::ArgumentParser *init_argument_parser() {\n  auto argument_parser = new util::ArgumentParser();\n\n  argument_parser->add_option(\"mode\", util::ArgumentParser::STRING, \"instruction_mix\");\n\n  argument_parser->add_option(\"labelpath\", util::ArgumentParser::STRING, \"/home/dongjaelee/upmem_profiler/bin/1024/VA.16/labels.bin\");\n  argument_parser->add_option(\"logpath\", util::ArgumentParser::STRING, \"/home/dongjae/data_sweep_hbm_mmu/trace/ptw1_tlbway16_tlbset1/VA/131072/VA.16.trace\");\n  argument_parser->add_option(\"num_tasklets\", util::ArgumentParser::INT, \"16\");\n\n  return argument_parser;\n}\n\n} // namespace upmem_profiler\n\nint main(int argc, char **argv) {\n  upmem_profiler::util::ArgumentParser *argument_parser = upmem_profiler::init_argument_parser();\n  argument_parser->parse(argc, argv);\n\n  std::string mode = argument_parser->get_string_parameter(\"mode\");\n  if (mode == \"instruction_mix\") {\n    auto instruction_mix_profiler = new upmem_profiler::instruciton_mix::InstructionMixProfiler(argument_parser);\n    instruction_mix_profiler->profile();\n    delete instruction_mix_profiler;\n  } else {\n    throw std::invalid_argument(\"\");\n  }\n\n  delete argument_parser;\n\n  return 0;\n}\n"
  },
  {
    "path": "tools/upmem_profiler/src/main.h",
    "content": "#ifndef UPMEM_PROFILER_MAIN_H_\n#define UPMEM_PROFILER_MAIN_H_\n\n#include <cstdint>\n\nnamespace upmem_profiler {\n\nusing Address = int64_t;\nusing ThreadID = int;\nusing RegIndex = int;\n\n} // namespace upmem_profiler\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/util/argument_parser.cc",
    "content": "#include \"util/argument_parser.h\"\n\n#include <cassert>\n\nnamespace upmem_profiler::util {\n\nvoid ArgumentParser::add_option(Option option, OptionType option_type, Parameter default_parameter) {\n  assert(not option_types_.count(option));\n  assert(not default_parameters_.count(option));\n  assert(not custom_parameters_.count(option));\n\n  option_types_[option] = option_type;\n  default_parameters_[option] = default_parameter;\n}\n\nvoid ArgumentParser::parse(int argc, char **argv) {\n  assert(argc % 2 == 1);\n\n  for (int i = 1; i < argc; i += 2) {\n    for (auto &[option, option_type] : option_types_) {\n      std::string argv_option = std::string(argv[i]);\n\n      assert(argv_option.substr(0, 2) == \"--\");\n\n      if (option == argv_option.substr(2)) {\n        assert(not custom_parameters_.count(option));\n\n        std::string argv_parameter = std::string(argv[i + 1]);\n        custom_parameters_[option] = argv_parameter;\n      }\n    }\n  }\n}\n\nstd::set<ArgumentParser::Option> ArgumentParser::options() {\n  std::set<Option> options;\n  for (auto &[option, option_type] : option_types_) {\n    options.insert(option);\n  }\n  return std::move(options);\n}\n\nstd::string ArgumentParser::get_string_parameter(Option option) {\n  assert(option_types_[option] == STRING);\n\n  if (custom_parameters_.count(option)) {\n    return custom_parameters_[option];\n  } else {\n    return default_parameters_[option];\n  }\n}\n\nint64_t ArgumentParser::get_int_parameter(Option option) {\n  assert(option_types_[option] == INT);\n\n  if (custom_parameters_.count(option)) {\n    return std::stoi(custom_parameters_[option]);\n  } else {\n    return std::stoi(default_parameters_[option]);\n  }\n}\n\n} // namespace upmem_profiler::util\n"
  },
  {
    "path": "tools/upmem_profiler/src/util/argument_parser.h",
    "content": "#ifndef UPMEM_PROFILER_UTIL_ARGUMENT_PARSER_H_\n#define UPMEM_PROFILER_UTIL_ARGUMENT_PARSER_H_\n\n#include <map>\n#include <set>\n#include <string>\n\nnamespace upmem_profiler::util {\n\nclass ArgumentParser {\npublic:\n  using Option = std::string;\n  using Parameter = std::string;\n\n  enum OptionType { STRING = 0, INT };\n\n  explicit ArgumentParser() = default;\n  ~ArgumentParser() = default;\n\n  void add_option(Option option, OptionType option_type, Parameter default_parameter);\n  void parse(int argc, char **argv);\n\n  std::set<Option> options();\n  OptionType option_type(Option option) { return option_types_[option]; }\n\n  std::string get_string_parameter(Option option);\n  int64_t get_int_parameter(Option option);\n\nprivate:\n  std::map<Option, OptionType> option_types_;\n  std::map<Option, Parameter> default_parameters_;\n  std::map<Option, Parameter> custom_parameters_;\n};\n\n} // namespace upmem_profiler::util\n\n#endif\n"
  },
  {
    "path": "tools/upmem_profiler/src/util/config_loader.h",
    "content": "#ifndef UPMEM_PROFILER_UTIL_CONFIG_LOADER_H_\n#define UPMEM_PROFILER_UTIL_CONFIG_LOADER_H_\n\nnamespace upmem_profiler::util {\n\nclass ConfigLoader {\npublic:\n  static int num_gp_registers() { return 24; }\n};\n\n} // namespace upmem_profiler::util\n\n#endif\n"
  },
  {
    "path": "tools/upmem_reg_model/script/format.sh",
    "content": "cd ../src || exit\nblack -l 120 .\nisort .\nautoflake -r --in-place --remove-all-unused-imports --remove-unused-variables .\ncd - || exit\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/_base_benchmark.py",
    "content": "class _BaseBenchmark:\n    def __init__(\n        self,\n        name: str,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        self._name: str = name\n        self._num_dpus: int = num_dpus\n        self._data_prep_param: int = data_prep_param\n        self._hw_kernel: float = hw_kernel\n        self._hw_cpu_to_dpu: float = hw_cpu_to_dpu\n        self._hw_dpu_to_cpu: float = hw_dpu_to_cpu\n        self._hw_dpu_to_dpu: float = hw_dpu_to_dpu\n        self._sim_kernel: float = sim_kernel\n\n    def name(self) -> str:\n        return self._name\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def data_prep_param(self) -> int:\n        return self._data_prep_param\n\n    def hw_kerenl(self) -> float:\n        return self._hw_kernel\n\n    def hw_cpu_to_dpu(self) -> float:\n        return self._hw_cpu_to_dpu\n\n    def hw_dpu_to_cpu(self) -> float:\n        return self._hw_dpu_to_cpu\n\n    def hw_dpu_to_dpu(self) -> float:\n        return self._hw_dpu_to_dpu\n\n    def sim_kernel(self) -> float:\n        return self._sim_kernel\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        raise AttributeError\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        raise AttributeError\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        raise AttributeError\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        raise AttributeError\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/bs.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass BS(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"BS\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 20\n\n        vector_length = self._data_prep_param\n        query_length = self._data_prep_param // 8\n        elem_size = 8\n\n        mram_transfer_size = vector_length * elem_size + (query_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        results_size = 128\n\n        return results_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/gemv.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass GEMV(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"GEMV\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        elem_size = 4\n        matrix_length = self._data_prep_param * 64\n        vector_length = 64\n\n        mram_transfer_size = (matrix_length // self._num_dpus) * elem_size + vector_length * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        elem_size = 4\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/hst_l.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass HST_L(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"HST-L\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        elem_size = 4\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        elem_size = 4\n        bin_length = 256\n\n        mram_transfer_size = bin_length * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/hst_s.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass HST_S(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"HST-S\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        elem_size = 4\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        elem_size = 4\n        bin_length = 256\n\n        mram_transfer_size = bin_length * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/mlp.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass MLP(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"MLP\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        elem_size = 4\n        num_layers = 3\n        matrix_length = self._data_prep_param * self._data_prep_param\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (matrix_length // self._num_dpus) * elem_size * num_layers + vector_length * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        elem_size = 4\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        elem_size = 4\n        num_layers = 3\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size * (num_layers - 1)\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        elem_size = 4\n        num_layers = 3\n        vector_length = self._data_prep_param\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size * (num_layers - 1)\n\n        return mram_transfer_size\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/red.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass RED(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"RED\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        results_size = 256\n\n        return results_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/scan_rss.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass SCAN_RSS(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"SCAN-RSS\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size_1 = 16\n        input_argument_size_2 = 8\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size_1 + mram_transfer_size + input_argument_size_2\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size_2 = 8\n        return input_argument_size_2\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        results_size_1 = 128\n        return results_size_1\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/scan_ssa.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass SCAN_SSA(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"SCAN-SSA\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size_1 = 16\n        input_argument_size_2 = 8\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size_1 + mram_transfer_size + input_argument_size_2\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size_2 = 8\n        return input_argument_size_2\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        results_size_1 = 128\n        return results_size_1\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/sel.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass SEL(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"SEL\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 8\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        results_size = 64\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = ((vector_length // 2) // self._num_dpus) * elem_size\n\n        return results_size + mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/trns.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass TRNS(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"TRNS\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 16\n\n        N_ = 64\n        n_ = 8\n        M_ = self._data_prep_param\n        m_ = 4\n        matrix_length = N_ * n_ * M_ * m_\n        elem_size = 8\n\n        mram_transfer_size = (matrix_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size + input_argument_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        N_ = 64\n        n_ = 8\n        M_ = self._data_prep_param\n        m_ = 4\n        matrix_length = N_ * n_ * M_ * m_\n        elem_size = 8\n\n        mram_transfer_size = (matrix_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/ts.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass TS(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"TS\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 28\n\n        ts_length = self._data_prep_param\n        query_length = 64\n        elem_size = 4\n\n        mram_transfer_size = ((ts_length + query_length) // self._num_dpus) * elem_size * 3\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        results_size = 256\n\n        return results_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/uni.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass UNI(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"UNI\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 8\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        results_size = 384\n\n        vector_length = self._data_prep_param\n        elem_size = 8\n\n        mram_transfer_size = round((vector_length // 2 + 1) / self._num_dpus) * elem_size\n\n        return results_size + mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/benchmark/va.py",
    "content": "from benchmark._base_benchmark import _BaseBenchmark\n\n\nclass VA(_BaseBenchmark):\n    def __init__(\n        self,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n    ):\n        super().__init__(\n            \"VA\", num_dpus, data_prep_param, hw_kernel, hw_cpu_to_dpu, hw_dpu_to_cpu, hw_dpu_to_dpu, sim_kernel\n        )\n\n    def calculate_cpu_to_dpu_bytes(self) -> int:\n        input_argument_size = 12\n\n        vector_length = self._data_prep_param\n        elem_size = 4\n        num_input_vector = 2\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size * num_input_vector\n\n        return input_argument_size + mram_transfer_size\n\n    def calculate_dpu_to_cpu_bytes(self) -> int:\n        vector_length = self._data_prep_param\n        elem_size = 4\n\n        mram_transfer_size = (vector_length // self._num_dpus) * elem_size\n\n        return mram_transfer_size\n\n    def calculate_dpu_to_dpu_from_cpu_to_dpu_bytes(self) -> int:\n        return 0\n\n    def calculate_dpu_to_dpu_from_dpu_to_cpu_bytes(self) -> int:\n        return 0\n"
  },
  {
    "path": "tools/upmem_reg_model/src/io_/excel_reader.py",
    "content": "import math\nfrom typing import Set, Union\n\nimport pandas as pd\n\nfrom benchmark.bs import BS\nfrom benchmark.gemv import GEMV\nfrom benchmark.hst_l import HST_L\nfrom benchmark.hst_s import HST_S\nfrom benchmark.mlp import MLP\nfrom benchmark.red import RED\nfrom benchmark.scan_rss import SCAN_RSS\nfrom benchmark.scan_ssa import SCAN_SSA\nfrom benchmark.sel import SEL\nfrom benchmark.trns import TRNS\nfrom benchmark.ts import TS\nfrom benchmark.uni import UNI\nfrom benchmark.va import VA\n\n\nclass ExcelReader:\n    Benchmark = Union[BS, GEMV, HST_L, HST_S, MLP, RED, SCAN_RSS, SCAN_SSA, SEL, TRNS, TS, UNI, VA]\n\n    def __init__(self, excel_filepath: str):\n        self._excel_filepath: str = excel_filepath\n\n        self._data_frame: pd.DataFrame = pd.DataFrame(pd.read_excel(excel_filepath))\n\n        self._benchmarks: Set[ExcelReader.Benchmark] = set()\n        for (\n            benchmark,\n            num_dpus,\n            data_prep_param,\n            hw_kernel,\n            hw_cpu_to_dpu,\n            hw_dpu_to_cpu,\n            hw_dpu_to_dpu,\n            sim_kernel,\n        ) in zip(\n            self._data_frame[\"benchmark\"],\n            self._data_frame[\"num_dpus\"],\n            self._data_frame[\"data_prep_param\"],\n            self._data_frame[\"hw_kernel\"],\n            self._data_frame[\"hw_cpu_to_dpu\"],\n            self._data_frame[\"hw_dpu_to_cpu\"],\n            self._data_frame[\"hw_dpu_to_dpu\"],\n            self._data_frame[\"sim_kernel\"],\n        ):\n            if (\n                not (\n                    math.isnan(hw_kernel)\n                    or math.isnan(hw_cpu_to_dpu)\n                    or math.isnan(hw_dpu_to_cpu)\n                    or math.isnan(hw_dpu_to_dpu)\n                    or math.isnan(sim_kernel)\n                )\n                # and hw_kernel + hw_cpu_to_dpu + hw_dpu_to_cpu + hw_dpu_to_dpu <= 500\n            ):\n                if benchmark == \"BS\":\n                    self._benchmarks.add(\n                        BS(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"GEMV\":\n                    self._benchmarks.add(\n                        GEMV(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"HST-L\":\n                    self._benchmarks.add(\n                        HST_L(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"HST-S\":\n                    self._benchmarks.add(\n                        HST_S(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"MLP\":\n                    self._benchmarks.add(\n                        MLP(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"RED\":\n                    self._benchmarks.add(\n                        RED(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"SCAN-RSS\":\n                    self._benchmarks.add(\n                        SCAN_RSS(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"SCAN-SSA\":\n                    self._benchmarks.add(\n                        SCAN_SSA(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"SEL\":\n                    self._benchmarks.add(\n                        SEL(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"TRNS\":\n                    self._benchmarks.add(\n                        TRNS(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"TS\":\n                    self._benchmarks.add(\n                        TS(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"UNI\":\n                    self._benchmarks.add(\n                        UNI(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                elif benchmark == \"VA\":\n                    self._benchmarks.add(\n                        VA(\n                            num_dpus,\n                            data_prep_param,\n                            hw_kernel,\n                            hw_cpu_to_dpu,\n                            hw_dpu_to_cpu,\n                            hw_dpu_to_dpu,\n                            sim_kernel,\n                        )\n                    )\n                else:\n                    raise ValueError\n\n    def benchmarks(self) -> Set[Union[Benchmark]]:\n        return self._benchmarks\n"
  },
  {
    "path": "tools/upmem_reg_model/src/io_/excel_writer.py",
    "content": "from typing import Set\n\nimport pandas as pd\n\nfrom regression.datum import Datum\n\n\nclass ExcelWriter:\n    def __init__(self, excel_filepath: str, data: Set[Datum]):\n        self._data_frame: pd.DataFrame = pd.DataFrame(\n            [\n                [\n                    datum.name(),\n                    datum.num_dpus(),\n                    datum.data_prep_param(),\n                    datum.hw_total(),\n                    datum.sim_reg_total(),\n                    datum.sim_kernel(),\n                    datum.regression_cpu_to_dpu(),\n                    datum.regression_dpu_to_cpu(),\n                    datum.regression_dpu_to_dpu(),\n                ]\n                for datum in data\n            ],\n            columns=[\n                \"benchmark\",\n                \"num_dpus\",\n                \"data_prep_param\",\n                \"hw_total\",\n                \"sim_reg_total\",\n                \"sim_kernel\",\n                \"regression_cpu_to_dpu\",\n                \"regression_dpu_to_cpu\",\n                \"regression_dpu_to_dpu\",\n            ],\n        )\n\n        self._data_frame.to_excel(excel_filepath, sheet_name=\"Sheet1\")\n"
  },
  {
    "path": "tools/upmem_reg_model/src/main.py",
    "content": "import argparse\n\nfrom io_.excel_reader import ExcelReader\nfrom io_.excel_writer import ExcelWriter\nfrom regression.model import Model\n\nif __name__ == \"__main__\":\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\n        \"--input_excel_filepath\",\n        type=str,\n        default=\"/Users/bongjoon/upimulator_beta/tools/upmem_reg_model/data/input.xlsx\",\n    )\n    parser.add_argument(\n        \"--output_excel_filepath\",\n        type=str,\n        default=\"/Users/bongjoon/upimulator_beta/tools/upmem_reg_model/data/output.xlsx\",\n    )\n\n    args = parser.parse_args()\n\n    excel_reader = ExcelReader(args.input_excel_filepath)\n\n    min_cpu_to_dpu_bw = 0.0\n    min_cpu_to_dpu_mae = 1e10\n    for i in range(1, 10000):\n        cpu_to_dpu_bw = i * (1.0 / 10000)\n\n        model = Model(excel_reader.benchmarks(), cpu_to_dpu_bw, 0.035)\n\n        cpu_to_dpu_r2, cpu_to_dpu_mae = model.regress_cpu_to_dpu()\n        if cpu_to_dpu_mae < min_cpu_to_dpu_mae:\n            min_cpu_to_dpu_bw = cpu_to_dpu_bw\n            min_cpu_to_dpu_mae = cpu_to_dpu_mae\n\n    min_dpu_to_cpu_bw = 0.0\n    min_dpu_to_cpu_mae = 1e10\n    for i in range(1, 10000):\n        dpu_to_cpu_bw = i * (1.0 / 10000)\n\n        model = Model(excel_reader.benchmarks(), 0.105, dpu_to_cpu_bw)\n\n        dpu_to_cpu_r2, dpu_to_cpu_mae = model.regress_dpu_to_cpu()\n        if dpu_to_cpu_mae < min_dpu_to_cpu_mae:\n            min_dpu_to_cpu_bw = dpu_to_cpu_bw\n            min_dpu_to_cpu_mae = dpu_to_cpu_mae\n\n    min_cpu_to_dpu_bw = 0.2957\n    min_dpu_to_cpu_bw = 0.0627\n    model = Model(excel_reader.benchmarks(), min_cpu_to_dpu_bw, min_dpu_to_cpu_bw)\n\n    print(f\"CPU-DPU BW: {min_cpu_to_dpu_bw}\")\n    print(f\"DPU-CPU BW: {min_dpu_to_cpu_bw}\")\n\n    print(f\"Kernel: {model.regress_kernel()}\")\n    print(f\"CPU-DPU: {model.regress_cpu_to_dpu()}\")\n    print(f\"DPU-CPU: {model.regress_dpu_to_cpu()}\")\n    print(f\"DPU-DPU: {model.regress_dpu_to_dpu()}\")\n    print(f\"Communication: {model.regress_communication()}\")\n    print(f\"Total: {model.regress_total()}\")\n\n    excel_writer = ExcelWriter(args.output_excel_filepath, model.data())\n"
  },
  {
    "path": "tools/upmem_reg_model/src/regression/datum.py",
    "content": "class Datum:\n    def __init__(\n        self,\n        name: str,\n        num_dpus: int,\n        data_prep_param: int,\n        hw_kernel: float,\n        hw_cpu_to_dpu: float,\n        hw_dpu_to_cpu: float,\n        hw_dpu_to_dpu: float,\n        sim_kernel: float,\n        regression_cpu_to_dpu: float,\n        regression_dpu_to_cpu: float,\n        regression_dpu_to_dpu: float,\n    ):\n        self._name: str = name\n        self._num_dpus: int = num_dpus\n        self._data_prep_param: int = data_prep_param\n        self._hw_kernel: float = hw_kernel\n        self._hw_cpu_to_dpu: float = hw_cpu_to_dpu\n        self._hw_dpu_to_cpu: float = hw_dpu_to_cpu\n        self._hw_dpu_to_dpu: float = hw_dpu_to_dpu\n        self._sim_kernel: float = sim_kernel\n        self._regression_cpu_to_dpu: float = regression_cpu_to_dpu\n        self._regression_dpu_to_cpu: float = regression_dpu_to_cpu\n        self._regression_dpu_to_dpu: float = regression_dpu_to_dpu\n\n    def name(self) -> str:\n        return self._name\n\n    def num_dpus(self) -> int:\n        return self._num_dpus\n\n    def data_prep_param(self) -> int:\n        return self._data_prep_param\n\n    def hw_kernel(self) -> float:\n        return self._hw_kernel\n\n    def hw_cpu_to_dpu(self) -> float:\n        return self._hw_cpu_to_dpu\n\n    def hw_dpu_to_cpu(self) -> float:\n        return self._hw_dpu_to_cpu\n\n    def hw_dpu_to_dpu(self) -> float:\n        return self._hw_dpu_to_dpu\n\n    def hw_communication(self) -> float:\n        return self._hw_cpu_to_dpu + self._hw_dpu_to_cpu + self._hw_dpu_to_dpu\n\n    def hw_total(self) -> float:\n        return self.hw_kernel() + self.hw_communication()\n\n    def sim_kernel(self) -> float:\n        return self._sim_kernel\n\n    def regression_cpu_to_dpu(self) -> float:\n        return self._regression_cpu_to_dpu\n\n    def regression_dpu_to_cpu(self) -> float:\n        return self._regression_dpu_to_cpu\n\n    def regression_dpu_to_dpu(self) -> float:\n        return self._regression_dpu_to_dpu\n\n    def regression_communication(self) -> float:\n        return self._regression_cpu_to_dpu + self._regression_dpu_to_cpu + self._regression_dpu_to_dpu\n\n    def sim_reg_total(self) -> float:\n        return self.sim_kernel() + self.regression_communication()\n\n    def kernel_err(self) -> float:\n        return self._sim_kernel - self._hw_kernel\n\n    def cpu_to_dpu_err(self) -> float:\n        return self._regression_cpu_to_dpu - self._hw_cpu_to_dpu\n\n    def dpu_to_cpu_err(self) -> float:\n        return self._regression_dpu_to_cpu - self._hw_dpu_to_cpu\n\n    def dpu_to_dpu_err(self) -> float:\n        return self._regression_dpu_to_dpu - self._hw_dpu_to_dpu\n\n    def communication_err(self) -> float:\n        return self.regression_communication() - self.hw_communication()\n\n    def total_err(self) -> float:\n        return self.kernel_err() + self.communication_err()\n"
  },
  {
    "path": "tools/upmem_reg_model/src/regression/model.py",
    "content": "from typing import Set, Tuple\n\nimport numpy as np\nimport scipy\n\nfrom io_.excel_reader import ExcelReader\nfrom regression.datum import Datum\n\n\nclass Model:\n    def __init__(self, benchmarks: Set[ExcelReader.Benchmark], cpu_to_dpu_bw: float, dpu_to_cpu_bw: float):\n        self._cpu_to_dpu_bw: float = cpu_to_dpu_bw\n        self._dpu_to_cpu_bw: float = dpu_to_cpu_bw\n\n        self._data = set()\n        for benchmark in benchmarks:\n            regression_cpu_to_dpu = (benchmark.calculate_cpu_to_dpu_bytes() * (10**3)) / (\n                cpu_to_dpu_bw * (2**30)\n            )\n            regression_dpu_to_cpu = (benchmark.calculate_dpu_to_cpu_bytes() * (10**3)) / (\n                dpu_to_cpu_bw * (2**30)\n            )\n            regression_dpu_to_dpu = (benchmark.calculate_dpu_to_dpu_from_cpu_to_dpu_bytes() * (10**3)) / (\n                cpu_to_dpu_bw * (2**30)\n            ) + (benchmark.calculate_dpu_to_dpu_from_dpu_to_cpu_bytes() * (10**3)) / (\n                dpu_to_cpu_bw * (2**30)\n            )\n            self._data.add(\n                Datum(\n                    benchmark.name(),\n                    benchmark.num_dpus(),\n                    benchmark.data_prep_param(),\n                    benchmark.hw_kerenl(),\n                    benchmark.hw_cpu_to_dpu(),\n                    benchmark.hw_dpu_to_cpu(),\n                    benchmark.hw_dpu_to_dpu(),\n                    benchmark.sim_kernel(),\n                    regression_cpu_to_dpu,\n                    regression_dpu_to_cpu,\n                    regression_dpu_to_dpu,\n                )\n            )\n\n    def data(self) -> Set[Datum]:\n        return self._data\n\n    def regress_kernel(self) -> Tuple[float, float]:\n        hw_kernels = [datum.hw_kernel() for datum in self._data]\n        sim_kernels = [datum.sim_kernel() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(hw_kernels, sim_kernels)\n        mae = float(np.mean([abs(datum.kernel_err() / datum.hw_kernel()) for datum in self._data]))\n\n        return r_value**2, mae\n\n    def regress_cpu_to_dpu(self):\n        hw_cpu_to_dpus = [datum.hw_cpu_to_dpu() for datum in self._data]\n        regression_cpu_to_dpus = [datum.regression_cpu_to_dpu() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(hw_cpu_to_dpus, regression_cpu_to_dpus)\n        mae = float(np.mean([abs(datum.cpu_to_dpu_err() / datum.hw_cpu_to_dpu()) for datum in self._data]))\n\n        return r_value**2, mae\n\n    def regress_dpu_to_cpu(self):\n        hw_dpu_to_cpus = [datum.hw_dpu_to_cpu() for datum in self._data]\n        regression_dpu_to_cpus = [datum.regression_dpu_to_cpu() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(hw_dpu_to_cpus, regression_dpu_to_cpus)\n        mae = float(np.mean([abs(datum.dpu_to_cpu_err() / datum.hw_dpu_to_cpu()) for datum in self._data]))\n\n        return r_value**2, mae\n\n    def regress_dpu_to_dpu(self):\n        hw_dpu_to_dpus = [datum.hw_dpu_to_dpu() for datum in self._data]\n        regression_dpu_to_dpus = [datum.regression_dpu_to_dpu() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(hw_dpu_to_dpus, regression_dpu_to_dpus)\n        mae = float(\n            np.mean(\n                [\n                    abs(datum.dpu_to_dpu_err() / datum.hw_dpu_to_dpu())\n                    for datum in self._data\n                    if datum.hw_dpu_to_dpu() != 0\n                ]\n            )\n        )\n\n        return r_value**2, mae\n\n    def regress_communication(self):\n        hw_communications = [datum.hw_communication() for datum in self._data]\n        regression_communications = [datum.regression_communication() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(\n            hw_communications, regression_communications\n        )\n        mae = float(np.mean([abs(datum.communication_err() / datum.hw_communication()) for datum in self._data]))\n\n        return r_value**2, mae\n\n    def regress_total(self):\n        hw_totals = [datum.hw_total() for datum in self._data]\n        regression_totals = [datum.sim_reg_total() for datum in self._data]\n\n        slope, intercept, r_value, p_value, std_err = scipy.stats.linregress(hw_totals, regression_totals)\n        mae = float(np.mean([abs(datum.total_err() / datum.hw_total()) for datum in self._data]))\n\n        return r_value**2, mae\n"
  }
]